Operating Instructions

TM

Alcatel 1641 SX
4/1 MultiService Metro Gateway

Release 6.3 1 Subracks

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Alcatel Terrestrial Networks Division
3AL 74401 AAAA Edition 02 / April 2001

Operating Instructions Subracks

Contents
Customer Documentation 4/1 MultiService Metro Gateway Alcatel OptinexTM 1641 SX (4/1 OMSG) Release 6.3 1 Preliminary remarks on Page 3 and following Abbreviations on Page 9 and following

Registers
Product Safety Instructions Computer Subracks Matrix Subracks ESS/CSS, HESS/HCSS I/O STM 4 via ADM Alcatel 1651 SM Common I/O Shelf SDH dedicated Input/Output Subracks PDH dedicated Input/Output Subracks Ordering Information 1 2 3 see next side 4 5 6 7

NOTICE

Read the section Product Safety Instructions (Register 1) before operating the system for the first time. It is also recommended to re read this section at certain intervals in order to refresh your knowledge about safety. Please find the translation of these instructions in different languages in the Appendix of the Hardware Installation Manual.

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Add/Drop Multiplexer System (ADM) Alcatel 1651 SM

I/O STM 4 access is performed by an Add/Drop Multiplexer system Alcatel 1651 SM integrated in a separate 4/1 OMSG rack which has been specially modified. The ADM system is controlled by a network management system or a local craft terminal directly connected to the ADM equipment on opening the rack doors. The management of the ADM is in dependent from the partsystem Control of the 4/1 OMSG. The alarms Urgent and Non urgent, indicated by LEDs on the ADM equipment, are forwarded to the lamps in the Top Rack Unit TRU of the ADM modified rack (see Section 2.9 in the Hardware Installation Manual). For a description of the ADM and information on how it is operated refer to the accompanying Alcatel 1651 SM documentation Technical Handbook and Operators Handbook.

NOTICE

The alarm Attended indicated by an LED on the ADM equipment is not forwarded to the lamps in the TRU of the ADM modified rack.

In general, the feature Attended Alarm is not presently supported by the 4/1 OMSG hardware. Therefore, the occurrence of an attended alarm is only visible on the ADM equipment after opening the rack doors.

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Customer Documentation Alcatel OptinexTM 1641 SX Release 6.3 1

Organization of the Documentation
The 4/1 MultiService Metro Gateway Alcatel OptinexTM 1641SX (4/1 OMSG) customer documentation consists of the following manuals (the manual on hand is printed in bold): Functional Description Partsystems Operating Instructions Subracks Hardware Installation Manual Operation Manual Craft Terminal Software Alcatel 1651 SM Technical Handbook and Operators Handbook (if equipped)

Apart from this documentation, especially created for customers, Alcatel SEL supplies manufacturer documents as well. The manufacturer documents are only supplied to departments which are responsible for maintaining and modifying the system. These documents are not described here.

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Contents of the Manuals

The manual Functional Descriptions Partsystems de scribes the way the 4/1 OMSG works. The logical subdivi sion of the system in partsystems does not correspond to its mechanical construction. The partsystems are: Control Clock Generation and Distribution Matrix Common I/O shelf Input/Output of synchronous and plesiochronous signals.

The manual Operating Instructions Subracks de scribes their mechanical features and the use of the operat ing elements. Not all boards contained in the subrack be long to the partsystem corresponding to this subrack. An Operating Instruction consists of: the subrack equipment the assignment of the connector strips Common I/O shelf the subrack cabling test sockets, switches, alarm indicators on the front panel of the boards and their function.

The Hardware Installation Manual summarizes the mechanical construction details of racks, Common I/O shelf and subracks. It provides information on hardware start up and upgrade procedures for the entire 4/1 OMSG. The Operation Manual Craft Terminal/Craft Termi nal for Multiple NE/Users describes the operation of the 4/1 OMSG using the CT or SH DXC, performing adminis trative and maintenance tasks and alarm handling.

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The manual consists of the Operation Manual CT/SH DXC Introduction describing the main features of the graphical interface and providing a general overview of the system architecture, the managed equipment and the different functionalities provided by the SDH Manager. the Operation Manual CT/SH DXC Construction describing the operations related to the management of Maps, Submaps and symbols within the SDH Manager and indicating the actions leading to the creation, edition, deletion, storage and listing of Maps. the Operation Manual CT/SH DXC Error Messages reporting any error that is propagated to the operator interface, as well as an explanation and some possible actions whenever appropriate. the Operation Manual CT/SH DXC Administration describing administrative and maintenance tasks provided by the System Maintenance Features such as creating users and installing the AU application. the Alarm Reference Guide providing information of all possible alarms on the CT concerning cause, effect on service and ways to get out of the alarm situation. the Operation Manual Alarm Manager ALMAP AS providing information concerning alarm surveillance and alarm management such as displaying alarm lists, acknowledging alarms. the Operation Manual Security Management ALMAP SEC describing the operation of the SEC Access Control Information Administration (ACA) tool. It introduces the different access control concepts, such as functions, objects and combinations, Functional Access Domains (FADs), and Object Access Domains (OADs), operators groups, initiators, targets, and user profiles. the Operation Manual Log Management ALMAP ELM describing the operation of the ELM (Element Log Manager) generic component, which deals with the

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management of Event Forward Discriminators (EFDs) together with the management and the browsing of logs. The Alcatel 1651 SM system handbooks comprise all information concerning the ADM extension of the 4/1 OMSG for STM 4 access. These handbooks are supplied only if an ADM equipment is contained in the system sup plied.

Symbols
The manual at hand contains the following symbols:

ATTENTION

is used to mark information provided to prevent material damages or operation errors.

NOTICE

is used to emphasize particularly important information.

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Registered Trademarks
HP is a registered trademark of the Hewlett Packard Corporation HP OpenView is a registered trademark of the Hewlett Packard Corporation Sun, SunOS, SPARC, NeWSprint and Solaris are registered Trademarks of Sun Microsystems, Inc. UNIX is a registered trademark of UNIX System Laboratories, AT&T. DEC VT is a registered trademark of Digital Equipment Corp. Seagate is a registered trademark of Seagate Technology, Inc. Motorola, VMEexec and UNIX SYSTEM V/88 are registered trademarks of Motorola, Inc. All other names, products and services mentioned are trademarks of their respective holders.

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CE Conformity
The 4/1 MultiService Metro Gateway Alcatel OptinexTM 1641 SX (4/1 OMSG) meets the EU Directives 73/23/EEC 89/336/EEC Compatibility. Low voltage Electro Magnetic

The 4/1 OMSG complies with the standards or normative documents EN60950 Ed. 08.1992 with A3 Ed. 01.1996 and A4 Ed. 03.1997 EN55022 Ed. 04.1987 EN50082 2 Ed. 03.1995 ETS300386 2 Ed. 12.1997 Safety of information technology equipment

EMC (Electro Magnetic Compatibility; Emission) EMC (Electro Magnetic Compatibility; Immunity) EMC (Electro Magnetic Compatibility)

and can therefore carry the CE marking.

Service Information
In case of problems with the 4/1 OMSG, please contact your Customer Support Center for any information.

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Abbreviations
A21E1 A4ES1 ADB ADM AD.. ADIS ADOS AIS AS ASIC AU Access board 21x2 Mbit/s Access board 4xSTM 1 Electrical Adapter Board (IOS45, IOS2D) Add/Drop Multiplexer Adapter GTI to LMC960/480 Adapter Input Signals Adapter Output Signals Alarm Indication Signal Adaptation (double) Subrack Application Specific IC Administrative Unit

BER BIP BP BPF BSB

Bit Error Ratio Bit Interleaved Parity Backpanel BP Format Battery Supervision Board (TRU)

C C 12 C3 C4 CDB CDBE CDBF CDBC/D CDC CEPT CFC

Container (SDH) for plesiochronous signals Container C 12 (2 Mbit/s) Container C 3 (34 Mbit/s) Container C 4 (140 Mbit/s) Clock Distribution Board CDB for LVDS signals (ESSD) CDB for LVDS signals (HESS) CDB for ECL signals (Dedicated I/O) Clock Distribution Circuit Confrence Europenne des Administration des Postes et des Tlcommunications Clock + Frame receive Circuit

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CIB CK, Cl CKD CMI CONGI CONV CONV3 CONV3A CONV3B CONV4A CP CPU CRC CRU CS Byte CSIFA CSSD CT CXB CXB32 CXB40

Clock Interface Board Clock Clock Dominator Coded Mark Inversion Control and General Interface Converter unit Converter 5.1/+5.6 V 30 A , Converter 5.1/+5.6/+3.7 V 30 A , Converter 5.1/+5.6, 30 A Converter 3.7/+3.7/+12 V Communication Processor Central Processing Unit Cyclic Redundancy Check Clock Reference Unit Connection Supervision Byte in the SOH Control System Interface ASIC Center Stage Double Subrack Craft Terminal Center stage Matrix Board CXB 32x32 ports CXB 40x40 ports

D Bit DCE DCC DM DMA DRAM DSB

Urgent alarm message from the remote station Data Communication Equipment (modem) Data Communication Channel Demapping (of the GTI signal / transmit direction) Direct Memory Access Dynamic RAM DCC Server Board

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DTE DTSCA DU

Data Terminal Equipment Duplex To Simplex Converter ASIC Domestic Unit

EC ECC ECL EEPROM EM EMC EMI EPB EPS EQUICO ESS ESSD ETB ETSI EXB EXBA EXBB EXB32

Equipment Controller Embedded Control Channel Emitter Coupled Logic Electrically Erasable Programmable Read Only Memory Electro Magnetic Electro Magnetic Compatibility Electro Magnetic Interference External Protection Board Equipment Protection Switching Equipment Controller End Stage Subrack End Stage Double Subrack Extension Board European Telecommunications Standardization Institute End stage Matrix Board EXB 16x16 STM 1 equivalents, LMC448 EXB 16x16 STM 1 equivalents, LMC480 EXB 32x32 STM 1 equivalents, LMC960

EXT Extraction ASIC EXT DM EXT Demapping on IOB140 EXT MP EXT Mapping ASIC on IOB140

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FAW FPE FPGA FRCL

Frame Alignment Word Functional Protection Earth Free Programmable Gate Array Frame Clock

GND GTI GTIP GTIS

Ground Generic Transfer Interface, internal interface I/OMatrix, STM 1 modified Parallel GTI signal Serial GTI signal

HCMOS HDB3 HDLC HOA HP HPA HPC HCSS HESS HPOM HPT HPROT HSC HSUT

High speed Complementary Metal Oxide Semiconductor High Density Bipolar code, level 3 High level Data Link Control, P bus Higher Order Assembler Higher order Path HP Adaptation HP Connection HPC Center Stage Subrack HPC End Stage Subrack HP Overhead Monitoring HP Termination High speed PROTection Hitless Switching Circuit Higher order Supervised Unequipped Termination

IC I2C, IIC IEC

Integrated Circuit Inter Integrated Circuit bus IPBB Extension Connector

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IO IOB IOB140 IOB155 IOB2 IOB2400 IOB34 IOB45 IOS IOS2400 IOS155 IOS155D IOS140 IOS140D IOS45 IOS34 IOS34D IOS2 IOS2D IPB IPBB ISO ITU T

Input/Output Input/Output Board IOB 140 Mbit/s IOB 155 Mbit/s IOB 2 Mbit/s IOB 2488 Mbit/s IOB 34 Mbit/s IOB 45 Mbit/s Input/Output Subrack IOS 2488 Mbit/s (STM 16) IOS 155 Mbit/s IOS 155 Mbit/s (Double Subrack) IOS 140 Mbit/s IOS 140 Mbit/s (Double Subrack) IOS 45 Mbit/s IOS 34 Mbit/s IOS 34 Mbit/s (Double Subrack) IOS 2 Mbit/s IOS 2 Mbit/s (Double Subrack) Internal Protection Board (IOS140D, IOS34D, IOS2D) Internal Protection Board type B (IOS2400, IOS155D, IOS45) International Organization for Standardization International Telecommunication Union sector Telecommunication

LAN LED LAPD LIF.. LIFAG LIFAL LIFG LIFL LIF2G LIF2L LMC

Local Area Network Light Emitting Diode Link Access Protocol for D channel Low order Interface adapter LIF Asymmetrical GTI/LVDS (EXBB/EXB32) LIF Asymmetrical LVDS/GTI (EXBB/EXB32) LIF GTI/LVDS (EXBA/EXBB) LIF LVDS/GTI (EXBA/EXBB) LIF GTI/LVDS (EXBB/EXB32) LIF LVDS/GTI (EXBB/EXB32) Large Matrix Configuration

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LOx LOC LOF LOM LOP LOS LP LPA LPC LPOM LPT LSI LSUT LVDS

Loss Of ... Loss Of Clock Loss Of Frame Loss Of Multiframe Loss Of Pointer Loss Of Signal Lower order Path LP Adaptation LP Connection LP Overhead Monitoring LP Termination Large Scale Integration circuit Lower order Supervised Unequipped Termination Low Voltage Differential Signal

MAC MCB MDVC3 MDX140 MP MPB

Medium Access Control Master Clock Board Mapping Demapping ASIC on IOB34 140 Mbit/s Multiplexer/Demultiplexer Mapping (to GTI Signal / receive direction) Main Power Block

MS SPRINGMultiplex Section Shared Protection Ring MPU MS MSA MSOH MSP MSPB MST MS AIS Microprocessor Unit Multiplexer Section MS Adaptation MS Overhead MS Protection MSP Board MS Termination MS Alarm Indication Signal

MTOS UX Operating System of the SPBs MUX2 MUX2/34 Multiplexer Board (in AS) Multiplexer/Demultiplexer for 2, 8 and 34 Mbit/s signals

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NAU NALMB N Bit

New Administrative Unit New Alarm Board Non urgent alarm message from the remote station

NCC New Communication Controller NCC PE NCC Processing Element NCO NGI NRZ NUTS NVRAM Numerically Controlled Oscillator New Generic transport Interface Non Return to Zero New Utility Subrack Non Volatile RAM

OA OBPS ODL

Optical Amplifier On Board Power Supply Overhead Data Link

OMSG OptinexTM MultiService Gateway 4/1 OMSG MultiService Metro Gateway Alcatel OptinexTM 1641 SX 4/4 OMSG MultiService Core Gateway and Cross Connect Alcatel OptinexTM 1664 SX OOF OS OSI Out Of Frame Operation System (Network Management System) Open System Interconnection

P4ES1 P4S1 P63E1 P/S P bus

Port board 4xSTM 1 Electrical Port board 4xSTM 1 Optical Port board 63x2 Mbit/s Parallel to Serial conversion HDLC bus between SPB and UBPE

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PC PCB PCS PCS140 PCS2 PCS34 PCS45 PCS8 PDH PFU PISO PLL PMP .. PMPRX PMPTX PMMF POH PPI PS PSU PSCE QDCN

Personal Computer Protection and Clock distribution Board Plesiochronous Supervision PCS of the 140 Mbit/s signal PCS of the 2 Mbit/s signal PCS of the 34 Mbit/s signal PCS of the 45 Mbit/s signal PCS of the 8 Mbit/s signal Plesiochronous Digital Hierarchy Power Filter Unit Parallel Input Serial Output Phase Locked Loop Protected Monitoring Point Test Socket Receive Signal Test Socket Transmission Signal Physical Machine Management Function Path Overhead Plesiochronous Physical Interface Power Supply Power Supply Unit Physical Shelf Control Element Connection Network Management Interface

R bus RA RAB RAM RC RDI REI

I2C bus for RI of subracks and boards Remote Alarm Rack Alarm Board Random Access Memory Receive Clock Remote Defect Indication Remote Error Indication

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RI RIM RS232/485 RS RSOH RST RTZ RX

Remote Inventory RI Module Recommended Standard, American EIA Interface Standard Regeneration Section RS Overhead RS Termination Return To Zero Receive Side

S16 S2231 S4 S bus SC SCI SCGL SDH SEC SIO SLM SMC SMX SNC P SOH SPB SPBB SPC SPRING SPI

Port board STM 16 TUG22 Mapping Demapping LSI Port board STM 4 I2C bus between SPB and CSIFA System Clock (from CDB) Switch Control Interface Signal Cable Grounding Labyrinth Synchronous Digital Hierarchy Synchronous Equipment Clock Serial Input/Output Signal Label Mismatch Switching Matrix Circuit Shelf Matrix Extender SubNetwork Connection Protection Section Overhead Satellite Processor Board SPB type B Serial Parallel Converter Shared Protection Ring Synchronous Physical Interface

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SSF SSM SSU STM STM STM STM STM STM STM 1 1E 1S 1L 4 16

Server Signal Failure Synchronization Status Message Synchronization Supply Unit Synchronous Transport Module STM Signal 155 Mbit/s Board STM 1 electrical Board STM 1 optical (short haul) Board STM 1 optical (long haul) STM 4 Signal 622 Mbit/s STM 16 Signal 2488 Mbit/s

TC TIM TRU TS TSD TSF TTF TTL TUG TUG22 TX

Transmit Clock Trace Identifier Mismatch Top Rack Unit Trail Signal TS Degrade TS Failure Transport Termination Function Transistor Transistor Logic Tributary Unit Group TUG level 2 (8 Mbit/s) CEPT Transmit Side

UB UBPE

User Board UB Processing Element

VC VC 12 VC 3 VC 4 VMEbus

Virtual Container Virtual Container for C 12 (2 Mbit/s) Virtual Container for C 3 (34 Mbit/s) Virtual Container for C 4 (140 Mbit/s) VME bus system

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WAN WDM X.25

Wide Area Network Wavelength Division Multiplexer Interface according to ITU T X.25

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