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Homework1ECE445

This document outlines the homework assignments for a CMOS VLSI Design course. Part A includes designing CMOS logic circuits for two logic functions, analyzing why silicon is preferred over germanium for fabrication, and explaining MOS transistor operation. Part B covers qualitatively comparing FETs and BJTs for VLSI processing, deriving MOSFET current equations, and plotting an Ids vs Vds graph for an nMOS transistor with given parameters.

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Prince Kumar
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24 views1 page

Homework1ECE445

This document outlines the homework assignments for a CMOS VLSI Design course. Part A includes designing CMOS logic circuits for two logic functions, analyzing why silicon is preferred over germanium for fabrication, and explaining MOS transistor operation. Part B covers qualitatively comparing FETs and BJTs for VLSI processing, deriving MOSFET current equations, and plotting an Ids vs Vds graph for an nMOS transistor with given parameters.

Uploaded by

Prince Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Department of Electronics & Communication Course: CMOS VLSI Design Course Code: ECE445

DOA:31-01-2012

Homework:1 Part A

DOS:08-02-2012

1. Design CMOS logic circuit that implements the logic functions given below a) Y= NOT ((AB+CD)) b) Y= NOT((ABC+DE) 2. Analyse with proper reason why Silicon is a preferred material over Germanium for VLSI fabrication process. 3. Explain the operation of MOS transistor using structural diagrams.

Part B

4. FET Vs BJT a qualitative analysis in perspective of VLSI Processing. 5. Derive the MOSFET current equations in saturation and linear region. 6. Consider an nMOS transistor with W/L ( 20/2 um). In this process, the gate oxide capacitance is 7*10-8 F/cm2and the mobility of electrons is 600 cm2/V s at 70 C. The threshold voltage is 1.0V. Plot Ids vs. Vds for Vgs = 0, 0.3, 0.6, 0.9, 1.2, 1.5, and 1.8 V.

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