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Tektronix Logic Analyzer Series Product Specications & Performance Verication Technical Reference Manual

This document applies to TLA System Software Version 5.6 or above

www.tektronix.com
077-1763-03

Copyright Tektronix. All rights reserved. Licensed software products are owned by Tektronix or its subsidiaries or suppliers, and are protected by national copyright laws and international treaty provisions. Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material. Specications and price change privileges reserved. TEKTRONIX and TEK are registered trademarks of Tektronix, Inc. MagniVu and iView are registered trademarks of Tektronix, Inc.

Contacting Tektronix
Tektronix, Inc. 14200 SW Karl Braun Drive P.O. Box 500 Beaverton, OR 97077 USA For product information, sales, service, and technical support: In North America, call 1-800-833-9200. Worldwide, visit www.tektronix.com to nd contacts in your area.

Warranty 2
Tektronix warrants that this product will be free from defects in materials and workmanship for a period of one (1) year from the date of shipment. If any such product proves defective during this warranty period, Tektronix, at its option, either will repair the defective product without charge for parts and labor, or will provide a replacement in exchange for the defective product. Parts, modules and replacement products used by Tektronix for warranty work may be new or reconditioned to like new performance. All replaced parts, modules and products become the property of Tektronix. In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration of the warranty period and make suitable arrangements for the performance of service. Customer shall be responsible for packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a location within the country in which the Tektronix service center is located. Customer shall be responsible for paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations. This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate maintenance and care. Tektronix shall not be obligated to furnish service under this warranty a) to repair damage resulting from attempts by personnel other than Tektronix representatives to install, repair or service the product; b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any damage or malfunction caused by the use of non-Tektronix supplies; or d) to service a product that has been modied or integrated with other products when the effect of such modication or integration increases the time or difculty of servicing the product. THIS WARRANTY IS GIVEN BY TEKTRONIX WITH RESPECT TO THE PRODUCT IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

Table of Contents
Preface ............................................................................................................... Related Documentation ....................................................................................... Specications and Characteristics ................................................................................ Characteristic Tables .......................................................................................... Atmospheric Characteristics for the Tektronix Logic Analyzer Family ................................. TLA7000 System Specications.................................................................................. TLA7012 Portable Mainframe Specications ................................................................... TLA7016 Benchtop Mainframe Characteristics ............................................................... TLA7PC1 Controller Specications............................................................................. TL708EX TekLink 8-Port Hub Characteristics ................................................................ TLA700 System Specications .................................................................................. TLA715 Dual Monitor Portable Mainframe Specications................................................... Benchtop and Expansion Mainframe Specications........................................................... TLA721 Dual Monitor Benchtop Controller Specications .................................................. TLA600 Series Specications.................................................................................... TLA7Axx/TLANAx Series Logic Analyzer Module Specications ........................................ TLA7Lx/Mx/Nx/Px/Qx Module Specications................................................................ TLA7PG2 Module Specications ............................................................................... DSO Module Specications ...................................................................................... External Oscilloscope (iView) Characteristics ................................................................. Performance Verication Procedures............................................................................ Summary Verication ........................................................................................ Test Equipment................................................................................................ Functional Verication ....................................................................................... Certication ................................................................................................... Performance Verication Procedures ....................................................................... Calibration Data Report........................................................................................... TLA7012 and TLA7016 Test Record ...................................................................... System Clock Test Data ...................................................................................... v v 1 1 2 3 9 14 19 22 24 29 34 38 41 52 62 68 71 76 78 78 78 79 81 81 83 83 83

TLA Product Specications & Performance Verication

Table of Contents

List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Dimensions of the TLA7012 Portable mainframe ................................................. Dimensions of the TLA7016 Benchtop mainframe ................................................ Dimensions of the TLA7016 Benchtop mainframe with rackmount option..................... Dimensions of the TLA7PC1 Benchtop PC Controller............................................ Dimensions of TLA715 Portable mainframe ....................................................... Dimensions of the benchtop and expansion mainframe ........................................... Dimensions of the benchtop and expansion mainframe with rackmount option................ Dimensions of the TLA600 series logic analyzer .................................................. 13 18 18 21 33 36 37 51

List of Tables
Table 1: Atmospheric characteristics............................................................................. Table 2: TLA7000 Backplane interface.......................................................................... Table 3: System trigger and external signal input latencies (Typical) ........................................ Table 4: System trigger and external signal output latencies (Typical) ....................................... Table 5: Intermodule latencies for LA source (Typical)........................................................ Table 6: TLA7000 External signal interface .................................................................... Table 7: TLA7012 Internal controller ............................................................................ Table 8: TLA7012 Display system .............................................................................. Table 9: TLA7012 Front-panel interface ....................................................................... Table 10: TLA7012 Rear-panel interface ....................................................................... Table 11: TLA7012 AC power source .......................................................................... Table 12: TLA7012 Portable mainframe transportation and storage ........................................ Table 13: TLA7012 Cooling ..................................................................................... Table 14: TLA7012 Mechanical ................................................................................. Table 15: TLA7016 Benchtop mainframe AC power source (Serial numbers B020000 and higher).... Table 16: TLA7016 Benchtop mainframe AC power source (Serial numbers B01000 B019999)..... Table 17: TLA7016 Benchtop mainframe transportation and storage....................................... Table 18: TLA7016 Benchtop mainframe cooling ............................................................ Table 19: Enhanced monitor ..................................................................................... Table 20: TLA7016 Benchtop mainframe Interface Module front panel characteristics .................. Table 21: TLA7016 Benchtop mainframe mechanical ........................................................ Table 22: TLA7PC1 Internal specications .................................................................... Table 23: External controls and connectors .................................................................... 2 3 4 5 6 7 9 10 11 11 11 12 12 13 14 14 15 15 16 16 17 19 20

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TLA Product Specications & Performance Verication

Table of Contents

Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64:

TLA7PC1 mechanical................................................................................. TL708 EX TekLink 8-Port Hub signal switching characteristics ................................ TL708EX TekLink 8-Port Hub AC power source characteristics................................ TL708EX TekLink 8-Port Hub atmospherics ...................................................... TL708EX TekLink 8-Port Hub miscellaneous ..................................................... TL708EX TekLink 8-Port Hub mechanical ........................................................ TLA700 Backplane interface......................................................................... TLA700 Backplane latencies......................................................................... TLA700 External signal interface ................................................................... TLA715 Internal controller ........................................................................... TLA715 display system............................................................................... TLA715 front-panel interface ........................................................................ TLA715 rear-panel interface ......................................................................... TLA715 AC power source............................................................................ TLA715 cooling ....................................................................................... TLA715 mechanical................................................................................... Benchtop and expansion mainframe AC power source ........................................... Benchtop and expansion mainframe cooling ....................................................... Enhanced monitor ..................................................................................... Benchtop and expansion mainframe mechanical................................................... TLA721 benchtop controller characteristics........................................................ Front panel characteristics ............................................................................ TLA600 input parameters with probes .............................................................. TLA600 timing latencies ............................................................................. TLA600 external signal interface .................................................................... TLA600 channel width and depth ................................................................... TLA600 clocking ...................................................................................... TLA600 trigger system ............................................................................... TLA600 MagniVu feature ............................................................................ TLA600 Data handling................................................................................ TLA600 internal controller ........................................................................... TLA600 display system............................................................................... TLA600 front-panel interface ........................................................................ TLA600 rear-panel interface ......................................................................... TLA600 AC power source............................................................................ TLA600 cooling ....................................................................................... TLA600 mechanical characteristics ................................................................. TLA7Axx/TLA7NAx input parameters (with probes) ............................................ TLA7Axx analog output .............................................................................. Channel width and depth.............................................................................. Clocking ................................................................................................

21 22 22 23 23 23 24 25 27 29 30 31 31 31 32 32 34 34 35 35 38 40 41 41 42 43 44 45 47 47 47 48 49 49 50 50 50 52 53 53 53

TLA Product Specications & Performance Verication

iii

Table of Contents

Table 65: TLA7Axx/TLA7NAx module trigger system ...................................................... Table 66: MagniVu acquisition .................................................................................. Table 67: Merged modules ....................................................................................... Table 68: Data placement......................................................................................... Table 69: NVRAM ................................................................................................ Table 70: Mechanical ............................................................................................. Table 71: LA module channel width and depth ................................................................ Table 72: LA module clocking................................................................................... Table 73: LA module trigger system ............................................................................ Table 74: LA module MagniVu feature ......................................................................... Table 75: LA module data handling ............................................................................. Table 76: LA module input parameters with probes........................................................... Table 77: LA module mechanical ............................................................................... Table 78: PG module electrical specication, operational mode............................................. Table 79: PG module clocking ................................................................................... Table 80: PG module event processing ......................................................................... Table 81: PG module inter-module interactions ............................................................... Table 82: PG module merged PG modules ..................................................................... Table 83: PG module mechanical................................................................................ Table 84: DSO module signal acquisition system ............................................................. Table 85: DSO module timebase system ....................................................................... Table 86: DSO module trigger system .......................................................................... Table 87: DSO module front-panel connectors ................................................................ Table 88: DSO module mechanical ............................................................................. Table 89: External oscilloscope (Integrated View or iView) characteristics ................................ Table 90: TDS1000B, TDS2000B, TDS1000, and TDS2000 Series oscilloscope waveform edge alignment ...................................................................................................... Table 91: Test equipment ......................................................................................... Table 92: Functional verication procedures................................................................... Table 93: Performance verication procedures ................................................................

58 60 60 61 61 61 62 62 64 66 66 66 67 68 69 70 70 70 70 71 73 73 75 75 76 77 78 79 81

iv

TLA Product Specications & Performance Verication

Preface
This document lists characteristics and specications of the following Tektronix Logic Analyzer Family products: TLA7000 series mainframes TLA7PC1 Controller TL708EX TekLink 8-Port Hub TLA700 series mainframes TLA600 series logic analyzers TLA7Axx/TLA7Nx series logic analyzer modules TLA7Lx/Mx/Nx/Px/Qx series logic analyzer modules TLA7PG2 pattern generation modules DSO digital storage oscilloscope modules Other Tektronix Logic Analyzer modules, microprocessor-related products, and individual logic analyzer probes have their own documentation for characteristics and specications. This document also contains performance verication procedures for the TLA7000 Series mainframes. To prevent personal injury or damage consider the following requirements before attempting service: Read the General Safety Summary and Service Safety Summary found in the Tektronix Logic Analyzer Family Product Safety & Compliance Instructions (Tektronix part number 071-2591-xx).

Related Documentation
Refer to the individual service manuals for the performance verication procedures and adjustment procedures for earlier TLA products. The following table lists related documentation available for your logic analyzer. The documentation is available on the TLA Documentation CD and on the Tektronix Web site (www.tektronix.com/manuals). You can also check the release notes on the instrument for additional information. To access the release notes, select Start > All Programs > Tektronix Logic Analyzer > TLA Release Notes.

TLA Product Specications & Performance Verication

Preface

Related Documentation
Item TLA Quick Start User Manuals Online Help Purpose High-level operational overview In-depth operation and UI help Location

Installation Quick Reference Cards Installation Manuals XYZs of Logic Analyzers

High-level installation information Detailed rst-time installation information Logic analyzer basics

Declassication and Securities instructions Application notes Product Specications & Performance Verication Procedures TPI.NET Documentation Field upgrade kits Optional Service Manuals

Data security concerns specic to sanitizing or removing memory devices from Tektronix products Collection of logic analyzer application specic notes TLA Product specications and performance verication procedures Detailed information for controlling the logic analyzer using .NET Upgrade information for your logic analyzer Self-service documentation for modules and mainframes

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TLA Product Specications & Performance Verication

Specications and Characteristics

This document lists the specications for the Tektronix Logic Analyzer mainframes and other logic analyzer products. Additional specication documents are available on the TLA Documentation CD or on the Tektronix Web site. For the most current documentation, refer to the Tektronix Web site (http://www.Tektronix.com).

Characteristic Tables
All specications are guaranteed unless noted Typical. Typical characteristics describe typical or average performance and provide useful reference information. Specications that are marked with the symbol are checked directly (or indirectly) using performance verication procedures. For mainframes and modules, the performance limits in this specication are valid with these conditions: The logic analyzer must be in an environment with temperature, altitude, humidity, and vibration within the operating limits described in these specications. The logic analyzer must have had a warm-up period of at least 30 minutes. For modules, the performance limits in this specication are valid with these conditions: The modules must be installed in a Logic Analyzer Mainframe. The module must have been calibrated/adjusted at an ambient temperature between +20 C and +30 C. The DSO module must have had its signal-path-compensation routine (self calibration or self cal) last executed after at least a 30 minute warm-up period. After the warm-up period, the DSO module must have had its signal-path-compensation routine last executed at an ambient temperature within 5 C of the current ambient temperature. For optimum performance using an external oscilloscope, please consult the documentation for any external oscilloscopes used with your Tektronix Logic Analyzer to determine the warm-up period and signal-path compensation requirements.

TLA Product Specications & Performance Verication

Specications and Characteristics

Atmospheric Characteristics for the Tektronix Logic Analyzer Family

The following table lists the Atmospheric characteristics of components in the Tektronix Logic Analyzer family. Table 1: Atmospheric characteristics
Characteristic Temperature Description Operating (no media in CD or DVD drive) +5 C to +50 C, 15 C/hr maximum gradient, noncondensing (derated 1 C per 305 m (1000 ft) above 1524 m (5000 ft) altitude) 1 2 Nonoperating (no media in drive) -20 C to +60 C, 15 C/hr maximum gradient, noncondensing Relative Humidity Operating (no media in drive) 20% to 80% relative humidity, noncondensing. Maximum wet bulb temperature: +29 C (derates relative humidity to approximately 22% at +50 C). 3 4 Nonoperating (no media in drive) 8% to 80% relative humidity, noncondensing. Maximum wet bulb temperature: +29 C (derates relative humidity to approximately 22% at +50 C). 5 Altitude Operating To 3000 m (9843 ft), (derated 1 C per 305 m (1000 ft) above 1524 m (5000 ft) altitude. Nonoperating 12,190 m (40,000 ft )
1 2 3 4 5

For TLA7012 instruments, the operating temperature is +5 C to +45 C, 11 C/hr maximum gradient, noncondensing (derated 1 C per 1000 ft above 5000 ft (1524 m) altitude) TLA7Axx series module operating temperature is +40 C maximum. TLA7Axx series module operating humidity is 5% to 90% up to +30 C, 75% from +30 to +40 C, noncondensing. Maximum wet-bulb temperature is +29.4 C. TLA7NAx series module operating humidity is 5% to 90% up to +30 C, 75% from +30 to +40 C, 45 % from +40 to +50 C, noncondensing. Maximum wet-bulb temperature is +29.4 C. TLA7Axx/TLA7NAx series module nonoperating humidity is 5% to 90% limited by a wet bulb temperature of +40 C.

TLA Product Specications & Performance Verication

TLA7000 System Specications

TLA7000 System Specications

The following tables list the specications common to the TLA7000 series logic analyzers. Table 2: TLA7000 Backplane interface
Characteristic Number of Slots CLK10 Frequency Relative Time Correlation Error 1 2 (Typical) TLA7Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx "MagniVu" data TLA7Axx/TLA7NAx to TLA7AxxTLA7NAx "MagniVu" data TLA7Axx/TLA7NAx to TLA7Nx/Px/Qx "MagniVu" data TLA7Nx/Px/Qx to TLA7Nx/Px/Qx "normal" data using an internal clock TLA7Axx/TLA7NAx to TLA7Axx "normal" data using an internal clock TLA7Axx/TLA7NAx to TLA7Nx/Px/Qx "normal" data using an internal clock TLA7Nx/Px/Qx to TLA7Nx/Px/Qx "normal" data using an external clock TLA7Axx/TLA7NAx to TLA7Axx/TLA7NAx "normal" data using an external clock TLA7Axx/TLA7NAx to TLA7Nx/Px/Qx "normal" data using an external clock
1 2

Description Portable mainframe Benchtop mainframe 4 13 10 MHz 100 ppm 2 ns 2 ns -3 ns 1 TLA7Nx/Px/Qx sample 0.5 ns 1 TLA7Axx/TLA7NAx sample 0.5 ns 1 TLA7Nx/Px/Qx sample 0.5 ns 2 ns 2 ns 4 ns

Includes typical jitter, slot-to-slot skew, and probe-to-probe variations to provide a "typical" number for the measurement. Assumes standard accessory probes are utilized. For time intervals longer than 1 ms between modules, add 0.01% of the difference between the absolute time measurements to the relative time correlation error to account for the inaccuracy of the CLK10 source.

TLA Product Specications & Performance Verication

TLA7000 System Specications

Table 3: System trigger and external signal input latencies (Typical)

Logic analyzer source characteristic 1 External system trigger input to LA probe TLA7Nx/Px/Qx modules TLA7AAx/TLA7NAx modules TLA7BBx modules TLA7Sxx modules External Signal In to LA probe tip via Signals 3, 4 (TTLTRG TLA7Nx/Px/Qx modules TLA7AAx/TLA7NAx modules TLA7BBx modules TLA7Sxx modules External Signal In to LA probe tip via Signals 1, 2(ECLTRG TLA7Nx/Px/Qx modules TLA7AAx/TLA7NAx modules TLA7BBx modules TLA7Sxx modules
1 2 3

Same mainframe tip 2 266 ns 626 ns 1202 ns 958 ns 30 ns 0,1) 3 212 ns + Clk 535 ns + Clk 1190 ns + Clk 950 ns 30 ns 0,1) 3 4 208 ns + Clk 627 ns + Clk 1186 ns + Clk 950 ns 30 ns

To expansion frame 202 ns 562 ns 1143 ns 1221 ns 30 ns 148 ns + Clk 471 ns + Clk 1118 ns + Clk 1220 ns 30 ns 144 ns + Clk 556 ns + Clk 1043 ns + Clk 1116 ns 30 ns

All system trigger and signal input latencies were measured from a falling edge transition (active true low) with signals in the wired-OR conguration. In the Waveform window, triggers are always marked immediately except when delayed to the rst sample. In the Listing window, triggers are always marked on the next sample period following their occurrence. Clk represents the time to the next master clock at the destination logic analyzer module. With asynchronous clocking this represents the delta time to the next sample clock. With synchronous sampling this represents the time to the next master clock generated by the setup of the clocking state machine and the supplied SUT clocks and qualication data. Signals 1 and 2 (ECLTRG0, 1) are limited to a broadcast mode where only one source can drive the signal node at any one time. The signal source can be used to drive any combination of destinations.

TLA Product Specications & Performance Verication

TLA7000 System Specications

Table 4: System trigger and external signal output latencies (Typical)

Logic analyzer source characteristic 1 LA probe tip to external system trigger out TLA7Nx/Px/Qx modules TLA7AAx/TLA7NAx modules TLA7BBx modules TLA7Sxx modules LA probe tip to External Signal Out via Signal 3, 4 (TTLTRG OR function TLA7Nx/Px/Qx modules TLA7AAx/TLA7NAx modules TLA7BBx modules TLA7Sxx modules AND function TLA7Nx/Px/Qx modules TLA7AAx/TLA7NAx modules TLA7BBx modules TLA7Sxx modules LA probe tip to External Signal Out via Signals 1, 2 TLA7Nx/Px/Qx modules TLA7AAx/TLA7NAx modules TLA7BBx modules TLA7Sxx modules
1

Same mainframe (skid) 2 376 ns + Smpl 794 ns + Smpl 1332 ns + Smpl 1170 ns 30 ns 0,1) 3 366 ns + Smpl 793 ns + Smpl 1328 ns + Smpl 950 ns 30 ns 379 ns + Smpl 803 ns + Smpl 1340 ns + Smpl 950 ns 30 ns (ECLTRG0,1) 3 4 374 ns + Smpl 793 ns + Smpl 1330 ns + Smpl 950 ns 30 ns

To expansion frame 437 ns + Smpl 854 ns + Smpl 1392 ns + Smpl 1230 ns 30 ns

428 ns + Smpl 854 ns + Smpl 1390 ns + Smpl 1011 ns 30 ns 457 ns + Smpl 881 ns + Smpl 1418 ns + Smpl 1028 ns 30 ns 444 ns + Smpl 863 ns + Smpl 1399 ns + Smpl 1019 ns 30 ns

2 3 4

SMPL represents the time from the event to the next valid data sample at the probe tip of the LA module. With asynchronous sampling, this represents the delta time to the next sample clock. With MagniVu asynchronous sampling, this represents 500 ps or less. With synchronous sampling, this represents the time to the next master clock generated by the setup of the clocking state machine, the system-under-test supplied clocks, and the qualication data. Skid is commonly referred to as the system level system trigger and signaling output latency. This is the absolute time from when the event rst appears at the input probe tips of a module to when the corresponding event that it generates appears at the system trigger or external signal outputs. All signal output latencies are validated to the rising edge of an active (true) high output. Signals 1 and 2 (ECLTRG0, 1) are limited to a broadcast mode where only one source can drive the signal node at any one time. The signal source can be used to drive any combination of destinations.

TLA Product Specications & Performance Verication

TLA7000 System Specications

Table 5: Intermodule latencies for LA source (Typical)

Logic analyzer source characteristic LA to LA intermodule system trigger LA2: Trigger All Modules, LA1: Do Nothing TLA7Nx/Px/Qx modules TLA7AAx/TLA7ABx modules TLA7BBx modules TLA7Sxx modules LA to LA intermodule ARM (TTLTRG 2, 4 ,5, 6) 2 3 TLA7Nx/Px/Qx modules TLA7AAx/TLA7ABx modules TLA7BBx modules TLA7Sxx modules LA to LA intermodule Signals 1, 2 (ECLTRG 0, 1) 2 3 4 (LA2: Trigger, Then Set Signal 2; LA1: If Signal 2 Is True, Then Trigger) TLA7Nx/Px/Qx modules TLA7AAx/TLA7ABx modules TLA7BBx modules TLA7Sxx modules LA to LA intermodule Signals 3, 4 (TTLTRG0,1) 2 3 (LA2: Trigger, Then Set Signal 3; LA1: If Signal 3 Is True, Then Trigger) TLA7Nx/Px/Qx modules TLA7AAx/TLA7ABx modules TLA7BBx modules TLA7Sxx modules
1 2

Same mainframe

Frame to frame

(TTLTRG7) 1 2 66 ns + Smpl 108 ns + Smpl 82 ns + Smpl 105 ns 30 nsl 108 ns + Smpl + Clk 115 ns + Smpl + Clk 95 ns + Smpl + Clk 85 ns 30 ns 128 ns + Smpl 118 ns + Smpl 145 ns + Smpl 167 ns 30 ns 170 ns + Smpl +Clk 180 ns + Smpl + Clk 162 ns + Smpl +Clk 147 ns 30 ns

116 ns + Smpl + Clk 118 ns + Smpl + Clk 95 ns + Smpl + Clk 130 ns 30 ns

178 ns + Smpl + Clk 192 ns + Smpl + Clk 166 ns + Smpl + Clk 192 ns 30 ns

116 ns + Smpl + Clk 120 ns + Smpl + Clk 91 ns + Smpl + Clk 950 ns 30 ns

128 ns + Smpl + Clk 184 ns + Smpl + Clk 158 ns + Smpl + Clk 1012 ns 30 ns

In the Waveform window, triggers are always marked immediately except when delayed to the rst sample. In the Listing window, triggers are always marked on the next sample period following their occurrence. SMPL represents the time from the event to the next valid data sample at the probe tip of the LA module. With asynchronous sampling, this represents the delta time to the next sample clock. With MagniVu asynchronous sampling, this represents 500 ps or less. With synchronous sampling, this represents the time to the next master clock generated by the setup of the clocking state machine, the system-under-test supplied clocks, and the qualication data. Clk represents the time to the next master clock at the destination logic analyzer module. With ascynchronous clocking this represents the delta time to the next sample clock. With synchronous sampling this represents the time to the next master clock generated by the setup of the clocking state machine and the supplied SUT clocks and qualication data. Signals 1 and 2 (ECLTRG0, 1) are limited to a broadcast mode where only one source can drive the signal node at any one time. The signal source can be used to drive any combination of destinations.

TLA Product Specications & Performance Verication

TLA7000 System Specications

Table 6: TLA7000 External signal interface

Characteristic System Trigger Input Input levels Minimum input voltage swing Threshold range Threshold step size Input destination Input Mode Minimum Pulse Width Active Period Maximum Input Voltage External Signal Input Input Destination Input levels Minimum input voltage swing Threshold range Threshold step size Input Mode Input Bandwidth 1 Description TTL compatible input via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe) 0 V to 3.0 V 300 mV 0.5 V to 1.5 V 50 mV System trigger Falling edge sensitive, latched (active low) 12 ns Accepts system triggers during valid acquisition periods via real-time gating, resets system trigger input latch between valid acquisition periods 0 to+ 5 V peak TTL compatible input via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe) Signal 1, 2, 3, 4 0 V to 3.0 V 300 mV 0.5 V to 1.5 V 50 mV Active (true) low, level sensitive Signal 1, 2 50 MHz square wave minimum Active Period Maximum Input Voltage System Trigger Output Source selection Source Mode Active Period Output Levels VOH VOL 0 V to 5 V peak TTL compatible output via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe) System trigger Active (true) low, falling edge latched Outputs system trigger state during valid acquisition period, resets system trigger output to false state between valid acquisitions 50 back terminated TTL-compatible output 4 V into open circuit, 2 V into 50 to ground 0.7 V sinking 10 mA Short-circuit protected (to ground) Signal 3, 4 10 MHz square wave minimum

Accepts signals during valid acquisition periods via real-time gating

Output Protection

TLA Product Specications & Performance Verication

TLA7000 System Specications

Table 6: TLA7000 External signal interface (cont.)

Characteristic External Signal Output Source Selection Description TTL compatible outputs via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe) Signal 1, 2 Signal 3, 4 10 MHz clock User denable Active (true) low or active (true) high 50 back terminated TTL output 4 V into open circuit, 2 V into 50 to ground 0.7 V sinking 10 mA Signal 1, 2 50 MHz square wave minimum Active Period Output Protection Intermodule Signal Line Bandwidth Signal 3, 4 10 MHz square wave minimum

Output Modes Level Sensitive Output Levels VOH VOL

Output Bandwidth 2

Outputs signals during valid acquisition periods, resets signals to false state between valid acquisitions Outputs 10 MHz clock continuously Short-circuit protected (to ground) Minimum bandwidth up to which the intermodule signals are specied to operate correctly Signal 1, 2 50 MHz square wave minimum Signal 3, 4 10 MHz square wave minimum

1 2

The Input Bandwidth specication only applies to signals to the modules; it does not apply to signals applied to the External Signal Input and sent back to the External Signal Output. The Output Bandwidth specication only applies to signals from the modules; it does not apply to signals applied to the External Signal Input and sent back to the External Signal Output.

TLA Product Specications & Performance Verication

TLA7012 Portable Mainframe Specications

TLA7012 Portable Mainframe Specications

The following tables describe the specications for the TLA7012 Portable Mainframe. Table 7: TLA7012 Internal controller
Characteristic Operating system Motherboard Description Microsoft Windows XP Professional The AB915GM motherboard is an ATX-family board that meets the FlexATX and microATX form-factor specications. It is based around an Intel Mobil Celeron M or Pentium M processor and an Intel 915GM chipset, integrating video, system monitoring, and Ethernet controllers on a 9.0 X 7.5 inch board. Intel 2 GHz/533 Dothan microprocessor; 479-pin PGA socket for uFC-PGA processor package Intel 915GM GMCH with an Intel ICH6-M I/O hub. Supports dual channel memory for higher performance. Two 200 pin SO DIMM sockets for DDR2-400/533 (PC2-3200/4300) modules. Maximum 2 GB (two modules, Gbit technology), minimum 128 MB Installed Conguration 1 GB 2 MB Level 2 (L2) write-back cache > 5 years battery life, lithium battery Standard PC compatible IDE (Integrated Device Electronics) hard disk drive residing on an EIDE interface. Formatted capacity 80 GB Continually subject to change due to the fast-moving PC component environment. These storage capacities valid at product introduction. SATA, native Read 9 ms Write 10 ms Standard PC compatible IDE (Integrated Device Electronics) DVD-RW drive residing on an EIDE interface. Continually subject to change due to the fast-moving PC component environment.

Microprocessor Chip set Main memory

Cache memory RTC, CMOS setup, & PNP NVRAM retention time (Typical) Bootable replaceable hard disk drive

Interface Average seek time DVD-RW drive

TLA Product Specications & Performance Verication

TLA7012 Portable Mainframe Specications

Table 8: TLA7012 Display system

Characteristic Display selection Description The TLA7012 Portable Mainframe motherboard can drive 3 video displays. Two DVI connectors connect to the external world. One of the connectors has both the DVI digital signals and the analog signals while the other connector has only DVI digital signals available. The third display connector is available only as an internal connection. This connection is via LVDS. This port drives the internal 15-inch display. One of the external connectors and the internal connection are connected to the same video information. One VGA, SVGA, or XGA-compatible analog output port. Primary video port with DVI digital only Resolution (Pixels) 640 x 480 1024 x 768 1280 x 1024 1600 x 1200 Resolution (Pixels) 640 x 480 1024 x 768 1280 x 1024 1600 x 1200 Colors 256, 16-bit, 32-bit Refresh Rates 60, 75, 85 60, 75, 85 60, 75, 85 Refresh Rates 60, 75, 85 60, 75, 85 60, 75, 80

External display drive

Secondary video port with DVI digital and analog VGA signalling through an adapter

Colors 256, 16-bit, 32-bit

Maximum resolution on the analog VGA is 1600 x 1200 with 32-bit color at 75 Hz. Internal display Classication Color LCD (NEC TFT NL10276BC30-24D) Color LCD module NL10276BC30-24D is composed of the amorphous silicon thin lm transistor liquid crystal display (a-Si TFT LCD) panel structure with driver LSIs for driving the TFT (Thin Film Transistor) array and a backlight. This LCD display will be driven directly by the motherboard via LVDS signaling. 1024 pixels horizontal by 768 pixels vertical (1024X768) at 60 Hz refresh rate Area of 304 mm (11.7 in) by 228 mm (9 in) of viewing area. 262, 144 colors (6-bit RGB) with a color gamut of 42% at center to NTSC

Resolution/Refresh rate and area Color scale

10

TLA Product Specications & Performance Verication

TLA7012 Portable Mainframe Specications

Table 9: TLA7012 Front-panel interface

Characteristic Keypad Special function knobs Multi-function Knob Vertical position Vertical scale Horizontal position Horizontal scale USB Port Description 18 buttons allow user to perform the most common tasks required to operate theTLA Various increment, decrement functions dependent on screen/window selected. Scrolling and positioning dependent on display type. Scales waveform displays only. Scrolling and positioning dependent on display type. Scales waveform displays only. Front panel (lower Right on Front Panel) 3 each USB 2.0 connectors.

Table 10: TLA7012 Rear-panel interface

Characteristic TekLink interface bus Input signal characteristics Output signal characteristics Reference clock characteristics SVGA output ports External Trigger input External Signal input System Trigger output External Signal output USB 2.0 ports GBit LAN port Description Connector supports Reference Clock (10 MHz), Power On Signaling, Run event, System Trigger, General purpose events LVDS compatible inputs via rear-panel 40-pin connector LVDS compatible outputs via rear-panel 40-pin connector LVDS compatible inputs via rear-panel 40-pin connector Two DVI connectors Trigger input routed to the system trigger line Signal input routed to one of four internal signals Internal system trigger routed as TTL-compatible output One of four internal signals routed to the signal output connector. The internal 10 MHz reference clock can be routed to this output. Four USB 2.0 connections RJ-45 connector 10/100/1000 Mbps

Table 11: TLA7012 AC power source

Characteristic Source voltage and frequency Maximum power consumption Steady-state input current Inrush surge current Power factor correction Description 100 VRMS to 240 VRMS 10%, 50 Hz to 60 Hz 115 VRMS 10%, 400 Hz 750 W 6 ARMS maximum at 90 VACRMS, 60 Hz or 100 VACRMS, 400 Hz 70 A maximum Yes

TLA Product Specications & Performance Verication

11

TLA7012 Portable Mainframe Specications

Table 11: TLA7012 AC power source (cont.)

Characteristic On/Sleep indicator Description Green/yellow front panel LED located left of the On/Standby switch provides visual feedback when the switch is actuated. When the LED is green, the instrument is powered and the processor is not sleeping. When the LED is yellow, the instrument is powered, but the processor is sleeping. Front panel On/Standby switch allows users to turn the instrument on. A soft power down is implemented so that users can turn the instrument off without going through the Windows shutdown process; the instrument powers down normally. The power cord provides main power disconnect

On/Standby switch and indicator

Table 12: TLA7012 Portable mainframe transportation and storage

Characteristic Transportation Package Material Description Transportation Package material meets recycling criteria as described in Environmental Guidelines for Package Design (Tektronix part number 063-1290-00) and Environmentally Responsible Packaging Handbook (Tektronix part number 063-1302-00). The system can be shipped with or without modules installed. Only modules weighing less than 5lbs/slot which have been qualied to meet 60g shock (per Tektronix Standard part number 062-2858-00, Rev B, Class 5 subassembly requirement) can be shipped installed in this mainframe and its standard shipping package.

Conguration for Transportation

Table 13: TLA7012 Cooling

Characteristic Cooling system Pressurization Slot activation Description Forced air circulation system with no removable lters using eight fans operating in parallel Negative pressurization system in all chambers including modules Installing a module activates cooling for the corresponding occupied slots by opening the airow shutter mechanism. Optimizes cooling efciency by only applying airow to installed modules. Front sides and bottom Back rear 6 inches (152 mm) front, sides, top, and rear. Prevent blockage of airow to bottom of instrument by placing on a solid, noncompressable surface; can be operated on rear feet. All fans operational at half their rated potential and speed (12 VDC)

Air intake Air exhaust Cooling clearance

Fan speed and operation

12

TLA Product Specications & Performance Verication

TLA7012 Portable Mainframe Specications

Table 14: TLA7012 Mechanical

Characteristic Classication Overall dimensions Height (with feet) Width Depth Weight Description The portable mainframe is intended for design and development bench and lab-based applications. Dimensions are without front feet extended, front cover attached, pouch attached, nor power cord attached. 11.6 in (294.64 mm) 17.75 in (450.85 mm) 18.1 in (459.74 mm) 40 lbs 12 oz (18.45 kg) with no modules installed, two dual-wide slot covers, and empty pouch 5 lbs (2.27 kg) maximum per module slot 58 lbs (26.30 kg) minimum conguration (no modules), with all standard accessories 89 lbs 8 oz (41.6 kg) full conguration, with two TLA7P4 modules and standard accessories (including probes and clips) 43 dBA weighted (operator) 41 dBA weighted (bystander) Chassis parts are constructed of aluminum alloy; front panel and trim peaces are constructed of plastic; circuit boards are constructed of glass. Tektronix blue body and Tektronix silver-gray trim and front with black pouch, FDD feet, handle, and miscellaneous trim pieces

Shipping conguration

Acoustic noise level (Typical) Construction materials Finish type

Figure 1: Dimensions of the TLA7012 Portable mainframe

TLA Product Specications & Performance Verication

13

TLA7016 Benchtop Mainframe Characteristics

TLA7016 Benchtop Mainframe Characteristics

The following tables list the specications for the TLA7016 Benchtop Mainframe. The mainframe includes the interface module. The interface module provides the interface between an external controller and the mainframe. All communication between the controller and the mainframe is via GB LAN. Table 15: TLA7016 Benchtop mainframe AC power source (Serial numbers B020000 and higher)
Characteristic Source voltage & Maximum power consumption Description 100 VRMS to 120 VRMS, 50 Hz to 60 Hz; 1450 W line power 1 120 VRMS to 240 VRMS, 50 Hz to 60 Hz; 1900 W line power 1 115 VRMS, 440 Hz; 1450 W line power 1 70 A maximum 17.6 ARMS maximum at 108 VACRMS 10 ARMS maximum at 207 VACRMS 0.99 at 60 Hz operation and 0.95 at 400 Hz operation Front Panel On/Standby switch with integral power indicator. Switch allows users to turn the instrument on. A soft power down is implemented so that users can turn off the instrument without going through the Windows shutdown process; the instrument powers down normally.

Inrush surge current Steady state input current Power factor correction (Typical) ON/Standby switch and indicator

Maximum power consumed by a fully loaded six-module instrument.

Table 16: TLA7016 Benchtop mainframe AC power source (Serial numbers B01000 B019999)
Characteristic Source voltage Maximum power consumption Fuse rating (Current and voltage ratings and type of fuse used to fuse the source line voltage) 90 V - 132 VACRMS Operation High-power/Low line (159-0379-00) 103 V - 250 VACRMS Operation (159-0256-00) Description 100 VRMS to 240 VRMS 10%, 45 Hz to 66 Hz 100 VRMS to 120 VRMS, 360 Hz to 440 Hz 1450 W line power (the maximum power consumed by a fully loaded, 6-module instrument) Safety: UL198G/CSA C22.2 Size: 0.25 in 1.25 in Style: Slow acting Rating: 20 A/250 V Safety: UL198G/CSA C22.2 Size: 0.25 in 1.25 in Style: No. 59/Fast acting Rating: 15 A/250 V Safety: IEC 127/Sheet 1 Size: 5 mm 20 mm Style: Fast acting "F", high-breaking capacity Rating: 6.3 A/250 V

207 V - 250 VACRMS Operation (159-0381-00)

14

TLA Product Specications & Performance Verication

TLA7016 Benchtop Mainframe Characteristics

Table 16: TLA7016 Benchtop mainframe AC power source (Serial numbers B01000 B019999) (cont.)
Characteristic Inrush surge current Steady state input current Power factor correction (Typical) ON/Standby switch and indicator Description 70 A maximum 16.5 ARMS maximum at 90 VACRMS 6.3 ARMS maximum at 207 VACRMS 0.99 at 60 Hz operation and 0.95 at 400 Hz operation Front Panel On/Standby switch with integral power indicator. Switch allows users to turn the instrument on. A soft power down is implemented so that users can turn off the instrument without going through the Windows shutdown process; the instrument powers down normally.

Table 17: TLA7016 Benchtop mainframe transportation and storage

Characteristic Transportation Package Material Description Transportation Package material meets recycling criteria as described in Environmental Guidelines for Package Design (Tektronix part number 063-1290-00) and Environmentally Responsible Packaging Handbook (Tektronix part number 063-1302-01). The system can be shipped with or without modules installed. Only modules weighing less than 5lbs/slot which have been qualied to meet 60g shock (per Tektronix Standard part number 062-2858-00, Rev B, Class 5 subassembly requirement) can be shipped installed in this mainframe and its standard shipping package.

Conguration for Transportation

Table 18: TLA7016 Benchtop mainframe cooling

Characteristic Cooling system Description Forced air circulation system (positive pressurization) using a single low-noise centripetal (squirrel cage) fan conguration with no lters for the power supply and 13 module slots. Rear panel switch selects between full speed and variable speed. Slot exhaust temperature and ambient air temperature are monitored such that a constant delta temperature is maintained. Installing a module activates the cooling for the corresponding occupied slots by opening the air ow shutter mechanism. Optimizes cooling efciency by only applying airow to modules that are installed. Positive pressurization system, all chambers including modules P2 to P1, bottom of module to top of module Lower fan-pack rear face and bottom Top-sides and top-rear back. Top rear-back exhaust redirected to the sides by the fan pack housing to minimize reentry into the intake. 100 mV/ C with 0 C corresponding to 0 V output -10 C to +90 C, delta temperature 50 C 2 in (51 mm), rear, top, and sides

Fan speed control

Slot activation

Pressurization Slot airow direction Mainframe air intake Mainframe air exhaust D Temperature readout sensitivity (Typical) Temperature sense range (Typical) Clearance

TLA Product Specications & Performance Verication

15

TLA7016 Benchtop Mainframe Characteristics

Table 18: TLA7016 Benchtop mainframe cooling (cont.)

Characteristic Fan speed readout Description RPM = 20 (Tach frequency) or 10 (+Pulse Width) where (+Pulse Width) is the positive width of the TACH1 fan output signal measured in seconds 650 to 2250 RPM

Fan speed range

Table 19: Enhanced monitor

Characteristic Voltage readout Voltage readout accuracy (Typical) Current readout Current readout accuracy (Typical) RS-232 Connector Connector levels Passive monitor connector Description +24 V, -24 V, +12 V, -12 V, +5 V, -5.2 V, -2 V, +5 VStandby if present, and +5 VExternal via RS-232 3% maximum Readout of the present current on the +24 V, -24 V, +12 V, -12 V, +5 V, -2 V, -5.2 V rails via RS-232 5% of maximum power supply Imp Provides access for RS-232 host to enhanced monitor 25 VDC maximum, 1 A maximum per pin 25-pin connector provides access for monitoring the power supply, temperature, and fan speed.

Table 20: TLA7016 Benchtop mainframe Interface Module front panel characteristics
Characteristic TekLink interface bus Input signal characteristics Output signal characteristics Reference clock characteristics External Trigger input External Signal input System Trigger output External Signal output GBit LAN port Description Connector supports Reference Clock (10 MHz), Power On Signaling, Run event, System Trigger, General purpose events LVDS compatible inputs via rear-panel 40-pin connector LVDS compatible outputs via rear-panel 40-pin connector LVDS compatible inputs via rear-panel 40-pin connector Trigger input routed to the system trigger line Signal input routed to one of four internal signals Internal system trigger routed as TTL-compatible output One of four internal signals routed to the signal output connector. The internal 10 MHz reference clock can be routed to this output. RJ-45 connector 10/100/1000 Mbps

16

TLA Product Specications & Performance Verication

TLA7016 Benchtop Mainframe Characteristics

Table 21: TLA7016 Benchtop mainframe mechanical

Characteristic Classication Overall Dimensions Standard Height (with feet) Width Depth Rackmount Height Width Depth Interface module dimensions Weight Height Width Depth Mainframe with interface module and slot llers (Typical) Maximum per slot Rackmount kit added Shipping weight 13.25 in (33.66 cm) 18.9 in (48 cm) 28.9 in to 33.9 in (73.4 cm to 86.1 cm) in 0.5 in increments, user selectable 10.32 in (262.1 mm) 1.25 in (31.75 mm) 14.75 in (373.4 mm) 52 lbs 14 oz. (24 kg) minimum conguration with interface module and 6 dual-slot ller panels 5 lbs (2.27 kg) 20 lbs (9.1 kg) 60 lbs 11 oz (26.7 kg) minimum conguration with interface module (no other modules), with standard accessories 187 lbs (85 kg) fully congured instrument with the addition of ve logic analyzer modules and all module standard accessories including probes and clips Interface module Variable fan speed (at 860 RPM) Full speed fan (switched at rear) Construction materials One slot wide 43.2 dBA weighted (front) 43.8 dBA weighted (back) 66.2 dBA weighted (front) 66.2 dBA weighted (back) Chassis parts, aluminum alloy Front panel and trim pieces, plastic Circuit boards, glass laminate Mainframes are Tektronix silver gray with dark gray trim on fan pack and bottom feet support rails. 13.7 in (35 cm) including feet 16.7 in (42.4 cm) 26.5 in (67 cm) Description For lab benchtop or rackmount applications

Size Acoustic noise level (Typical)

Finish type

TLA Product Specications & Performance Verication

17

TLA7016 Benchtop Mainframe Characteristics

Figure 2: Dimensions of the TLA7016 Benchtop mainframe

Figure 3: Dimensions of the TLA7016 Benchtop mainframe with rackmount option

18

TLA Product Specications & Performance Verication

TLA7PC1 Controller Specications

TLA7PC1 Controller Specications

Tektronix has released different motherboards for the TLA7PC1 controllers. The motherboards are indicated by the following serial number ranges. B010000 to B019999 B020000 to B029999 B030000 to B039999 The following tables list the specications for the TLA7PC1 Controllers. The serial number ranges are designated by prexes, such as: B01, B02, and B03. NOTE. To access the BIOS Setups for TLA7PC1 controllers with serial numbers B020000 and higher, restart the instrument and hold down the Delete key. For controllers with serial numbers B010000 to B019999, restart the instrument and hold down function key F2. Table 22: TLA7PC1 Internal specications
Characteristic Operating system Motherboard B01 B02 B03 Microprocessor B01 B02, B03 Chip set Main memory B01 B02 B03 Cache memory RTC, CMOS setup, & PNP NVRAM retention time (Typical) B01 B02, B03 B01, B02 B03 Description Microsoft Windows XP Professional ATX-family board, integrating video, system monitoring, IDE and Ethernet controllers on a single board. AB915GM - Flex-ATX-family board, 9.0 X 8.0 in. AIMB-760G2 - RoHS compliant, ATX-family board, 12.0 X 9.6 in. AIMB-762G2 - RoHS compliant, ATX-family board, 12.0 X 9.6 in. Intel 2 GHz/533 MHz FSB Pentium M, 479-pin PGA socket for uFC-PGA processor package Intel 3.4 GHz/800 MHz FSB Pentium 4, LGA775 socket Intel 915G GMCH with an Intel ICH6 PCI Express I/O hub Intel 945G GMCH with an Intel ICH7R PCI Express I/O hub Maximum conguration: 4 GB (four 1 GB DIMMs) Installed conguration: 1 GB (two 512 MB DIMMs) Two 200-pin SO-DIMM sockets for DDR2-400/533 MHz (PC2-3200/4300) Two 240-pin DIMM sockets for DDR2-400/533 MHz (PC2-3200/4300) SDRAM Two 240-pin DIMM sockets for DDR2-533/667 MHz (PC2-4300/5400) SDRAM Level 2 (L2) write-back cache 1 MB >5 years battery life, lithium battery >3 years battery life, lithium battery

TLA Product Specications & Performance Verication

19

TLA7PC1 Controller Specications

Table 22: TLA7PC1 Internal specications (cont.)

Characteristic Hard disk drive Size Interface Average seek time DVD-ROM/CD-RW drive Description Standard PC compatible IDE hard disk drive residing on an EIDE interface. 80 GB, continually subject to change due to the fast-moving PC component environment. SATA, native Read 9 ms Write 10 ms Standard PC compatible IDE DVD/CD-RW drive residing on an EIDE interface. The initial drive was a Teac DV-W28E793 with +R/RW and R/RW. Continually subject to change due to the fast-moving PC component environment. B01 Can drive two external video displays via DVI connectors. One DVI port with DVI digital only, other port with DVI digital and analog VGA signaling via an adapter. DVI has maximum resolution of 1600 x 1200 pixels; with 256, 16-bit, or 32-bit colors; and refresh rates of 60 Hz, 75 Hz, or 85 Hz. Analog VGA has maximum resolution of 1600 x 1200 with 32-bit colors at 75 Hz refresh rate. One VGA, SVGA, or XGA-compatible analog output port, with maximum resolution of 2048 x 1536 pixels at 85 Hz refresh rate 100 VRMS to 240 VRMS 10%, 50 Hz to 60 Hz Internal 400 W 8 ARMS maximum at 100 VACRMS, 5 ARMS maximum at 240 VACRMS

External display drive

B02, B03 Source voltage and frequency Fuse Maximum power consumption Steady-state input current

Table 23: External controls and connectors

Characteristic USB ports PS2 ports B01 B02 On/Standby switch I/O Indicators CPU reset switch Alarm reset switch Video Ports LAN Ports Audio Ports B01 B02, B03 Description Four USB 2.0 ports None Keyboard and mouse connectors in rear; one common PS2 connector in front Switch used to power on the instrument LEDs for power on/off, HDD activity, and fan alarm Hardware reset for the PC Reset switch for the system fan and over temperature monitor circuitry One DVI-I connector and one DVI-D connector One analog SVGA connector Two RJ45 with integrated green and yellow/amber LEDs located above the USB connectors Two vertical 3.5 mm audio-jack stack. Line Output (top, lime) capable of driving headphones, Microphone Input (bottom, pink)

20

TLA Product Specications & Performance Verication

TLA7PC1 Controller Specications

Table 24: TLA7PC1 mechanical

Characteristic Dimensions Height Width Depth Description 3.5 in (88.9 mm) 17.1 in (434.3 mm) 24 in (609.6 mm) 24 lbs 12 oz (11.25 kg) 35 lbs (15.9 kg) Chassis parts are constructed of steel alloy and trim peaces are constructed of plastic; circuit boards are constructed of glass laminate. Tektronix silver-gray

Weight Shipping conguration Construction materials Finish type

Figure 4: Dimensions of the TLA7PC1 Benchtop PC Controller

TLA Product Specications & Performance Verication

21

TL708EX TekLink 8-Port Hub Characteristics

TL708EX TekLink 8-Port Hub Characteristics

Table 25: TL708 EX TekLink 8-Port Hub signal switching characteristics
Characteristic TekLink cable assembly delay characteristics (Typical) Shielded twisted pairs (EVT0, EVT1, EVT2) Non-shielded twisted pairs (EVT3, EVT4, EVT5, EVT6) TekLink Port In to Port Out delays (Typical) TekLink REF_CLK out to Run out delay (Typical) TekLink input signal characteristics (Typical) Input destination Input levels TekLink output signal characteristics (Typical) Output destination Output levels Vod (voltage out differential) Vos TekLink AUX_PWR (Typical) TekLink real-time interface bus REF_CLK (EVT0) delay Typical system trigger (EVT1) delay Description 9.5 ns 10.5 ns 5 ns 15 ns REF_CLK out leads Run out by 5 ns LVDS compatible inputs through the front-panel 40-pin connector EVT0_IN_POS/NEG to EVT6_IN_POS/NEG LVDS compatible input LVDS compatible outputs through the front-panel 40-pin connector EVT0_OUT_POS/NEG to EVT6_OUT_POS/NEG LVDS compatible output 247 mV minimum 454 mV maximum 1.125 V minimum 1.375 V maximum 4.3 V power bi-directional diode isolated 1.3 A maximum output available Connector supports Reference Clock (10 MHz), Local 10/100 LAN connection, Power On Signaling, Run event, System Trigger, General purpose events

Table 26: TL708EX TekLink 8-Port Hub AC power source characteristics

Characteristic Source voltage and frequency Maximum power consumption Steady state input current Inrush surge current Power factor correction Description 100 VRMS to 240 VRMS 10%, 47 Hz to 63 Hz 110 W 0.9 ARMS maximum at 120 VACRMS at 80 W At 120 VAC, 18 A maximum At 230 VAC, 35 A maximum Yes

22

TLA Product Specications & Performance Verication

TL708EX TekLink 8-Port Hub Characteristics

Table 27: TL708EX TekLink 8-Port Hub atmospherics

Characteristic Temperature Operating Non-operating Humidity Operating & Non-operating Operating Non-operating Description 0 C to +50 C, 11 C/hr maximum gradient, non-condensing (derated 1 C per 305m (1000 ft) above 1524 m (5000 ft) altitude) -40 C to +71 C, 15 C/hr maximum gradient, non-condensing 5% to 95% relative humidity, non-condensing 75% above 30 C 45% above 40 C To 3000 m (9843 ft) To 12,000 m (40,000 ft)

Altitude

Table 28: TL708EX TekLink 8-Port Hub miscellaneous

Characteristic Cooling system Transportation Package Material Description Forced-air circulation system with no removable lters using two fans operating in parallel Transportation Package material meets recycling criteria as described in Environmental Guidelines for Package Design (Tektronix part number 063-1290-00) and Environmentally Responsible Packaging Handbook (Tektronix part number 063-1302-00). 153 mm (6 in) on back for adequate cooling

Cooling clearance

Table 29: TL708EX TekLink 8-Port Hub mechanical

Characteristics Classication Dimensions Height Width Depth Weight Shipping weight Construction material Finish type Description Portable instrument intended for design and development bench and lab based applications Benchtop Conguration 50.8 mm (2.0 in) 444.5 mm (17.5 in) 317.5 mm (12.5 in) Rackmount Conguration 44.5 mm (1.75 in) 482.6 mm (19 in) 298.5 mm (11.75 in)

2.7 kg (5 lbs 14 oz) minimum conguration with power cord and accessories 4.66 kg (10 lbs 4 oz) minimum conguration Chassis parts are constructed of aluminum alloy; circuit boards constructed of glass laminate. Tektronix silver-gray

TLA Product Specications & Performance Verication

23

TLA700 System Specications

TLA700 System Specications

The following tables list the specications common to the TLA715 and TLA721 logic analyzers. Refer to the individual logic analyzers section for detailed specications. Table 30: TLA700 Backplane interface
Characteristic Slots Portable mainframe Benchtop mainframe Expansion mainframe CLK10 Frequency Relative Time Correlation Error 1 2(Typical) TLA7Lx/Mx/Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx "MagniVu" data TLA7Axx/TLA7NAx to TLA7AxxTLA7NAx "MagniVu" data TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx "MagniVu" data TLA7Lx/Mx/Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx "normal" data using asynchronous sampling TLA7Axx/TLA7NAx to TLA7Axx "normal" data using asynchronous sampling TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx "normal" data using asynchronous sampling TLA7Lx/Mx/Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx "normal" data using an external clock TLA7Axx/TLA7NAx to TLA7Axx/TLA7NAx "normal" data using an external clock TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx "normal" data using an external clock TLA7Lx/Mx/Nx/Px/Qx "MagniVu" to DSO data TLA7Axx/TLA7NAx "MagniVu" to DSO data TLA7Lx/Mx/Nx/Px/Qx to DSO "normal" data using asynchronous sampling 3 TLA7Axx/TLA7NAx to DSO "normal" data using asynchronous sampling 3 TLA7Lx/Mx/Nx/Px/Qx to DSO "normal" data using an external clock 3 TLA7Axx/TLA7NAx to DSO "normal" data using an external clock 3 DSO to DSO
1

Description 4 10 (three slots taken up by the controller module) 13 10 MHz 100 ppm 2 ns 2 ns -3 ns 1 TLA7Lx/Mx/Nx/Px/Qx sample 0.5 ns 1 TLA7Axx/TLA7NAx sample 0.5 ns 1 TLA7Lx/Mx/Nx/Px/Qx sample 0.5 ns 2 ns 2 ns 4 ns 3 ns 2 ns 1 TLA7Lx/Mx/Nx/Px/Qx sample + 2 ns 1 TLA7Axx/TLA7NAx sample + 2 ns 3 ns 2 ns 3 ns

Includes typical jitter, slot-to-slot skew, and probe-to-probe variations to provide a "typical" number for the measurement. Assumes standard accessory probes are utilized.

24

TLA Product Specications & Performance Verication

TLA700 System Specications

2 3

For time intervals longer than 1 s between modules, add 0.01% of the difference between the absolute time measurements to the relative time correlation error to account for the inaccuracy of the CLK10 source. The DSO module time correlation is measured at the maximum sample rate on one channel only.

Table 31: TLA700 Backplane latencies

Characteristic System trigger and external signal input latencies 2 (Typical) Portable mainframe and benchtop mainframe External system trigger input to TLA7Lx/Mx/Nx/Px/Qx probe tip External system trigger input to TLA7Axx probe tip
4 5 4

Description Expansion

-266 ns -653 ns -212 ns + Clk -212 ns + Clk

56 5

-230 ns -617 ns -176 ns + Clk -176 ns + Clk -596 ns + Clk -615 ns + Clk 11 ns 412 ns + SMPL 830 ns + SMPL 402 ns + SMPL 415 ns + SMPL 828 ns + SMPL 836 ns + SMPL 385 ns + SMPL 385 ns + SMPL 817 ns + SMPL 817 ns + SMPL 104 ns 101 ns 111 ns 89 ns 92 ns 394 ns + SMPL 808 ns + SMPL 102 ns + SMPL 515 ns + SMPL 152 ns + SMPL 396 ns + SMPL

External signal input to TLA7Lx/Mx/Nx/Px/Qx probe tip via Signal 3, 4 External signal input to TLA7Axx/TLA7NAx probe tip via Signal 3, 4 External signal input to TLA7Axx/TLA7NAx probe tip via Signal 1, 2 External system trigger input to DSO probe tip System trigger and external signal output
4

External signal input to TLA7Lx/Mx/Nx/Px/Qx probe tip via Signal 1, 2

-634 ns + Clk -636 ns + Clk -25 ns

56

latencies 1

(Typical) 376 ns + SMPL 794 ns + SMPL 366 ns + SMPL 379 ns + SMPL 792 ns + SMPL 800 ns + SMPL 364 ns + SMPL 364 ns + SMPL 796 ns + SMPL 796 ns + SMPL 68 ns 65 ns 75 ns 68 ns 71 ns 358 ns + SMPL 772 ns + SMPL 66 ns + SMPL 479 ns + SMPL 116 ns + SMPL 360 ns + SMPL

TLA7Lx/Mx/Nx/Px/Qx probe tip to external system trigger out TLA7Axx/TLA7NAx probe tip to external system trigger out TLA7Lx/Mx/Nx/Px/Qx probe tip to external signal out via Signal 3, 4 3 TLA7Axx/TLA7NAx probe tip to external signal out via Signal 3, 4 3 TLA7Lx/Mx/Nx/Px/Qx probe tip to external signal out via Signal 1, 2 3 6 TLA7Axx/TLA7NAx probe tip to external signal out via Signal 1, 2 3 6 DSO probe tip to external system trigger out DSO Probe tip to external signal out via Signal 3, 4 3 DSO probe tip to external signal out via Signal 1, 2 3 6 Inter-module latencies (Typical) TLA7Lx/Mx/Nx/Px/Qx to DSO inter-module system trigger TLA7Axx/TLA7NAx to DSO inter-module system trigger
14 14 14

OR function AND function OR function AND function normal function inverted logic on backplane normal function inverted logic on backplane OR function AND function normal function inverted logic on backplane

TLA7Lx/Mx/Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx inter-module system trigger TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx inter-module system trigger TLA7Axx/TLA7NAx to TLA7Axx/TLA7NAx inter-module system trigger TLA7Lx/Mx/Nx/Px/Qx to DSO inter-module ARM
1 14

14

TLA Product Specications & Performance Verication

25

TLA700 System Specications

Table 31: TLA700 Backplane latencies (cont.)

Characteristic TLA7Axx/TLA7NAx to DSO inter-module ARM
1 15

Description 779 ns + SMPL 108 ns + SMPL + Clk 479 ns + SMPL + Clk 111 ns + SMPL + Clk 116 ns + SMPL + Clk 113 ns + SMPL + Clk
156 15 15

815 ns + SMPL 144 ns + SMPL + Clk 533 ns + SMPL + Clk 147 ns + SMPL + Clk 137 ns + SMPL + Clk 134 ns + SMPL + Clk 555 ns + SMPL + Clk 152 ns + SMPL + Clk 160 ns + SMPL + Clk 581 ns + SMPL + Clk -251 ns + SMPL -204 ns -562 ns 86 ns -264 ns + SMPL + Clk -156 ns + Clk -564 ns + Clk 95 ns -158 ns + Clk -273 ns + SMPL + Clk -577 ns + Clk -258 ns + SMPL + Clk -148 ns + Clk -562 ns + Clk

TLA7Lx/Mx/Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx inter-module ARM TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx inter-module ARM TLA7Axx/TLA7NAx to TLA7Axx inter-module ARM
156 15

TLA7Lx/Mx/Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 1, 2 TLA7Axx/TLA7NAx to TLA7Axx inter-module via Signal 1, 2
156

TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 1, 2 TLA7AxxTLA7NAx to TLA7Axx inter-module via Signal 3, 4
15

534 ns + SMPL + Clk 116 ns + SMPL + Clk 124 ns + SMPL + Clk 545 ns + SMPL + Clk -287 ns + SMPL -240 ns -598 ns 50 ns

TLA7Lx/Mx/Nx/Px/Q to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 3, 4 TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 3, 4 TLA7Lx/Mx/Nx/Px/Qx to TLA7Axx/TLA7NAx inter-module System Trigger DSO to TLA7Lx/Mx/Nx/Px/Qx inter-module System Trigger DSO to TLA7Axx/TLA7NAx inter-module System Trigger DSO to DSO inter-module System Trigger
4 15 4 4

15 14

TLA7Lx/Mx/Nx/Px/Qx to TLA7Axx/TLA7NAx inter-module ARM DSO to TLA7Lx/Mx/Nx/Px/Qx inter-module ARM DSO to TLA7Axx/TLA7NAx inter-module ARM DSO to DSO inter-module ARM DSO to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 1, 2 DSO to TLA7Axx/TLA7NAx inter-module via Signal 1, 2
56 5 5

-300 ns + SMPL + Clk -192 ns + Clk -600 ns + Clk 59 ns -179 ns + Clk

156

TLA7Lx/Mx/Nx/Px/Qx to TLA7Axx/TLA7NAx inter-module via Signal 1, 2

56

-294 ns + SMPL + Clk -598ns + Clk -294 ns + SMPL + Clk -184 ns + Clk -598 ns + Clk

TLA7Lx/Mx/Nx/Px/Qx to TLA7Axx/TLA7NAx inter-module via Signal 3, 4 DSO to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 3, 4 DSO to TLA7Axx/TLA7NAx inter-module via Signal 3, 4
1

15

2 3 4 5

SMPL represents the time from the event at the probe tip inputs to the next valid data sample of the LA module. With Normal asynchronous sampling, this represents the delta time to the next sample clock. With MagniVu asynchronous sampling, this represents 500 ps or less. With synchronous sampling, this represents the time to the next master clock generated by the setup of the clocking state machine, the system-under-test supplied clocks, and the qualication data. All system trigger and external signal input latencies are measured from a falling-edge transition (active true low) with signals measured in the wired-OR conguration. All signal output latencies are validated to the rising edge of an active (true) high output. In the Waveform window, triggers are always marked immediately except when delayed to the rst sample. In the Listing window, triggers are always marked on the next sample period following their occurrence. "Clk" represents the time to the next master clock at the destination logic analyzer. With asynchronous sampling, this represents the delta time to the next sample clock beyond the minimum asynchronous rate of 4 ns. With the synchronous sampling, this represents the time to the next master clock generated by the setup of the clocking state machine and the supplied system under test clocks and qualication data. Signals 1 and 2 are limited to a "broadcast" mode of operation, where only one source is allowed to drive the signal node at any one time. That single source may be utilized to drive any combination of destinations.

26

TLA Product Specications & Performance Verication

TLA700 System Specications

Table 32: TLA700 External signal interface

Characteristic System Trigger Input Input Levels VIH VIL Input destination Input Mode Minimum Pulse Width Active Period Maximum Input Voltage External Signal Input Input Destination Input Levels VIH VIL Input Mode Input Bandwidth 1 Active Period Maximum Input Voltage System Trigger Output Source selection Source Mode Active Period Output Levels VOH VOL Output Protection Description TTL compatible input via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe) TTL compatible input 2.0 V 0.8 V System trigger Falling edge sensitive, latched (active low) 12 ns Accepts system triggers during valid acquisition periods via real-time gating, resets system trigger input latch between valid acquisition periods 0 to +5 V peak TTL compatible input via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe) Signal 1, 2 Signal 3, 4 TTL compatible input 2.0 V 0.8 V Active (true) low, level sensitive Signal 1, 2 50 MHz square wave minimum 0 to +5 V peak TTL compatible output via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe) System trigger Active (true) low, falling edge latched Outputs system trigger state during valid acquisition period, resets system trigger output to false state between valid acquisitions 50 back terminated TTL-compatible output 4 V into open circuit 2 V into 50 to ground 0.7 V sinking 10 mA Short-circuit protected (to ground) Signal 3, 4 10 MHz square wave minimum

Accepts signals during valid acquisition periods via real-time gating

TLA Product Specications & Performance Verication

27

TLA700 System Specications

Table 32: TLA700 External signal interface (cont.)

Characteristic External Signal Output Source Selection Description TTL compatible outputs via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe) Signal 1, 2 Signal 3, 4 10 MHz clock User denable Active (true) low or active (true) high 50 back terminated TTL output 4 V into open circuit 2 V into 50 to ground 0.7 V sinking 10 mA
2

Output Modes Level Sensitive Output Levels VOH VOL Output Bandwidth Active Period

Signal 1, 2 50 MHz square wave minimum

Signal 3, 4 10 MHz square wave minimum

Outputs signals during valid acquisition periods, resets signals to false state between valid acquisitions Outputs 10 MHz clock continuously Short-circuit protected (to ground) Minimum bandwidth up to which the intermodule signals are specied to operate correctly Signal 1, 2 50 MHz square wave minimum Signal 3, 4 10 MHz square wave minimum

Output Protection Intermodule Signal Line Bandwidth

1 2

The Input Bandwidth specication only applies to signals to the modules; it does not apply to signals applied to the External Signal Input and sent back to the External Signal Output. The Output Bandwidth specication only applies to signals from the modules; it does not apply to signals applied to the External Signal Input and sent back to the External Signal Output.

28

TLA Product Specications & Performance Verication

TLA715 Dual Monitor Portable Mainframe Specications

TLA715 Dual Monitor Portable Mainframe Specications

The following tables describe the specications for the TLA715 Dual Monitor Portable Mainframe. Table 33: TLA715 Internal controller
Characteristic Operating system Microprocessor Main memory Style Speed Available congurations Installed congurations Cache memory Flash BIOS Real-time clock and CMOS setups NVRAM RTC, CMOS setup, & PNP NVRAM retention time (Typical) Floppy disk drive Bootable replaceable hard disk drive Size Description Microsoft Windows 2000 Intel Pentium PC-AT conguration with an Intel 815E chip-set and a 733 MHz Pentium III processor SDRAM 144 pin SO DIMM, 2 sockets, gold plated, 1.25-inch (3.175 cm) maximum height 133 MHz 32, 64, 128, 256 MB per SO DIMM 512 MB with both sockets loaded 256 KByte Level 2 (L2) write-back cache 256 KByte Real-time clock/calendar, standard and advanced PC CMOS setups; see BIOS specication > 10 years battery life, lithium battery Standard 3.5 inch 1.44 MB PC compatible high-density, double-sided oppy disk drive, 500 Kb/sec transfer rate Standard PC compatible IDE (Integrated Device Electronics) hard disk drive residing on an EIDE interface. 40 GB Continually subject to change due to the fast-moving PC component environment. These storage capacities valid at product introduction. ATA -5/enhanced IDE (EIDE) Read, 12 ms 7/14 ms 33.3 Mbps maximum (U-DMA mode 2) 2 MB (30 GB) /512 KB (10 GB) Standard PC compatible IDE (Integrated device Electronics) 8x-8x-24x CD-RW drive residing on an IDE interface. Continually subject to change due to the fast-moving PC component environment.

Interface Average seek time Average latency I/O data transfer rate Cache buffer CD-RW drive

TLA Product Specications & Performance Verication

29

TLA715 Dual Monitor Portable Mainframe Specications

Table 34: TLA715 display system

Characteristic Classication Description Standard PC graphics-accelerator technology capable of supporting both internal color LCD display and two external color VGA, SVGA, or XGA monitors 4 MB SDRAM clocked up to 100 MHz, no external video memory Hardware sense of external SVGA monitor during BIOS boot sequence; defaults to internal color LCD display (indicated by two beeps); automatically switches to external SVGA monitor, if attached (indicated by one beep). Dual (simultaneous) display of external SVGA monitor and internal color LCD is possible via special CMOS "simulscan" setup, as long as internal and external displays operate at same resolution (limited to 800x600 on current LCD) and display rates (simulscan mode indicated by three beeps). Four beeps during the BIOS boot indicates a monochrome LCD was found (not supported). Five beeps indicates no recognizable LCD or external monitor was found. Dynamic Display Conguration 1 (DDC1) support for external SVGA monitor is provided. Two VGA, SVGA, or XGA-compatible analog output ports. Display size is selected via Win2000 display applet. Display Size (Primary video port with Silicon motion chip) Resolution (Pixels) 640 x 480 800 x 600 1024 x 768 1280 x 1024 1600 x 600 1600 x 1200 Resolution (Pixels) 640 x 480 800 x 600 1024 x 768 1280 x 1024 1600 x 1200 Colors 256, 64 K, 16.8 M 265, 64 K, 16.8 M 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256, 64 K 256, 64 K Colors 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256 Refresh Rates 60, 75, 85 60, 75, 85 60, 75, 85 60 60 60 Refresh Rates 60, 75, 85 60, 75, 85 60, 75, 85 60, 75, 80 60, 75

Display memory Display selection

External display drive

(Secondary video port with 815E chip set)

Internal display

Classication Resolution Color scale

TFT (Thin Film Transistor) 26 cm active-matrix color LCD display, CCFL backlight, intensity controllable via software 800 X 600, 262, 144 colors with 211.2 mm (8.3 in) by 158.4 mm (6.2 in) of viewing area 262, 144 colors (6-bit RGB) with a color gamut of 42% at center to NTSC

30

TLA Product Specications & Performance Verication

TLA715 Dual Monitor Portable Mainframe Specications

Table 35: TLA715 front-panel interface

Characteristic QWERTY Keypad HEX Keypad Special function knobs Multi-function knob Vertical position Vertical scale Horizontal position Horizontal scale Integrated pointing device USB port Mouse Port Keyboard Port Description 31-key ASCII to support naming of les, traces, and keyboard equivalents of pointing device inputs for menus 25-key HEX supporting standard DSO and LA entry functions Various increment/decrement functions dependent on screen or window type Scrolling and positioning dependent on display type Scales waveform displays only Scrolling and positioning dependent on display type Scales waveform displays only Vertically mounted Trackball with two control buttons (SELECT and MENU) Front panel (lower left-hand side) dual USB connector PS/2 compatible pointing device port PS/2 compatible keyboard port

Table 36: TLA715 rear-panel interface

Characteristic Parallel interface port Description 36-pin high-density connector supports Output only, Enhanced Parallel Port (EPP), or Microsoft high-speed mode (ECP) Complies with IEEE P1284-C/D2 for bi-directional Parallel Peripheral Interface for Personal Computers (draft) style 1284-C 9-pin male sub-D connector to support RS-232 serial port Two 15-pin sub-D SVGA connectors Standard Type I, II, III PC-compatible, PC card slot Complies with PCMCIA 2.1 and JEIDA 4.1

Serial interface port SVGA output Port 1 and Port 2 PC CardBus32 port

Table 37: TLA715 AC power source

Characteristic Source voltage and frequency Fuse rating 90 V to 250 V operation (159-0046-00) 90 V to 250 V operation (159-0381-00) Maximum power consumption Steady-state input current Inrush surge current Power factor correction Description 100 VRMS to 240 VRMS 10%, 45 Hz to 66 Hz 100 VRMS to 120 VRMS, 360 Hz to 440 Hz UL198/CSA C22.2 0.25 in 1.25 in, Fast Blow, 8 A, 250 V IEC 127/Sheet 1 5 mm 20 mm, Fast Blow, 6.3 A, 250 V 600 W 6 ARMS maximum at 90 VACRMS, 60 Hz or 100 VACRMS, 400 Hz 70 A maximum Yes

TLA Product Specications & Performance Verication

31

TLA715 Dual Monitor Portable Mainframe Specications

Table 37: TLA715 AC power source (cont.)

Characteristic On/Sleep indicator Description Green/yellow front panel LED located next to On/Standby switch provides visual feedback when the On/Off switch is actuated. When the LED is green, the instrument is powered and the processor is not sleeping. When the LED is yellow, the instrument is powered, but the processor is sleeping. Front panel On/Standby switch. Users can push the switch to power down the instrument without going through the Windows shutdown process; the instrument normally powers down. The power cord provides main power disconnect.

On/Standby switch and indicator

Table 38: TLA715 cooling

Characteristic Cooling system Pressurization Slot activation Description Forced air circulation system with no removable lters using six fans operating in parallel Negative pressurization system in all chambers including modules Installing a module activates the cooling for the corresponding occupied slots by opening the airow shutter mechanism. Optimizes cooling efciency by only applying airow to installed modules. Front sides and bottom Back rear 2 inches (51 mm) front, sides, top, and rear. Prevent blockage of airow to bottom of instrument by placing on a solid, noncompressable surface; can be operated on rear feet. All fans operational at half their rated potential and speed (12 VDC)

Air intake Air exhaust Cooling clearance

Fan speed and operation

Table 39: TLA715 mechanical

Characteristic Overall dimensions Height (with feet) Width Depth Weight Shipping conguration Description Dimensions are without front feet extended, front cover attached, pouch attached, nor power cord attached. 9.25 in (23.5 cm) 17 in (43.18 cm) 17.5 in (44.45 cm) 30 lbs 12 oz (13.9 kg) with no modules installed, two dual-wide slot covers, and empty pouch 60 lbs 13 oz (27.58 kg) minimum conguration (no modules), with all standard accessories 86 lbs 9 oz (39.26 kg) full conguration, with two TLA 7P4 modules and standard accessories (including probes and clips) 42.7 dBA weighted (operator) 37.0 dBA weighted (bystander)

Acoustic noise level (Typical)

32

TLA Product Specications & Performance Verication

TLA715 Dual Monitor Portable Mainframe Specications

Table 39: TLA715 mechanical (cont.)

Characteristic Construction materials Finish type Description Chassis parts are constructed of aluminum alloy; front panel and trim peaces are constructed of plastic; circuit boards are constructed of glass. Tektronix blue body and Tektronix silver-gray trim and front with black pouch, FDD feet, handle, and miscellaneous trim pieces

Figure 5: Dimensions of TLA715 Portable mainframe

TLA Product Specications & Performance Verication

33

Benchtop and Expansion Mainframe Specications

Benchtop and Expansion Mainframe Specications

The following tables list the specications for the TLA721 Benchtop mainframe and the TLA7XM expansion mainframe. Table 40: Benchtop and expansion mainframe AC power source
Characteristic Source Voltage Maximum Power Consumption Fuse Rating (Current and voltage ratings and type of fuse used to fuse the source line voltage) 90 V - 132 VACRMS Operation High-power/Low Line (159-0379-00) 103 V - 250 VACRMS Operation (159-0256-00) 207 V - 250 VACRMS Operation (159-0381-00) Inrush Surge Current Steady State Input Current Power Factor Correction (Typical) ON/Standby Switch and Indicator Description 100 VRMS to 240 VRMS 10%, 45 Hz to 66 Hz 100 VRMS to 120 VRMS, 360 Hz to 440 Hz 1450 W line power (the maximum power consumed by a fully loaded 13-slot instrument) Safety: UL198G/CSA C22.2 Size: 0.25 in 1.25 in Style: Slow acting Rating: 20 A/250 V Safety: UL198G/CSA C22.2 Size: 0.25 in 1.25 in Style: No. 59/Fast acting Rating: 15 A/250 V Safety: IEC 127/Sheet 1 Size: 5 mm 20 mm Style: Fast acting "F", high-breaking capacity Rating: 6.3 A/250 V 70 A maximum 16.5 ARMS maximum at 90 VACRMS 6.3 ARMS maximum at 207 VACRMS 0.99 at 60 Hz operation and 0.95 at 400 Hz operation Front Panel On/Standby switch with integral power indicator

Table 41: Benchtop and expansion mainframe cooling

Characteristic Cooling system Description Forced air circulation system (positive pressurization) using a single low-noise centripetal (squirrel cage) fan conguration with no lters for the power supply and 13 module slots. Rear panel switch selects between full speed and variable speed. Slot exhaust temperature and ambient air temperature are monitored such that a constant delta temperature is maintained. Installing a module activates the cooling for the corresponding occupied slots by opening the air ow shutter mechanism. Optimizes cooling efciency by only applying airow to modules that are installed. Positive pressurization system, all chambers including modules

Fan speed control

Slot activation

Pressurization

34

TLA Product Specications & Performance Verication

Benchtop and Expansion Mainframe Specications

Table 41: Benchtop and expansion mainframe cooling (cont.)

Characteristic Slot airow direction Mainframe air intake Mainframe air exhaust Temperature readout sensitivity Temperature sense range Clearance Fan speed readout Description P2 to P1, bottom of module to top of module Lower fan-pack rear face and bottom Top-sides and top-rear back. Top rear-back exhaust redirected to the sides by the fan pack housing to minimize reentry into the intake. 100 mV/ C with 0 C corresponding to 0 V output -10 C to +90 C, delta temperature 50 C 2 in (51 mm), rear, top, and sides RPM = 20 (Tach frequency) or 10 (+Pulse Width) where (+Pulse Width) is the positive width of the TACH1 fan output signal measured in seconds 650 to 2250 RPM

Fan speed range

Table 42: Enhanced monitor

Characteristic Voltage readout Voltage readout accuracy (Typical) Current readout Current readout accuracy (Typical) Rear panel connector levels Description +24 V, -24 V, +12 V, -12 V, +5 V, -5.2 V, -2 V, +5 VStandby if present, and +5 VExternal via RS232 3% maximum Readout of the present current on the +24 V, -24 V, +12 V, -12 V, +5 V, -2 V, -5.2 V rails via RS232 5% of maximum power supply Imp 25 VDC maximum, 1 A maximum per pin (Provides access for RS-232 host to enhanced monitor)

Table 43: Benchtop and expansion mainframe mechanical

Characteristic Overall Dimensions Standard Height Width Depth Height Width Depth Height Width Depth Height Width Depth Description 13.7 in (346.7 mm) including feet 16.7 in (424.2 mm) 26.5 in (673.1 mm) 13.25 in (336.6 mm) 18.9 in (480.1 mm) 28.9 in to 33.9 in (734.1 mm to 861.1 mm) in 0.5 in increments, user selectable 10.32 in (262.1 mm) 2.39 in (60.7 mm) 14.75 in (373.4 mm) 10.32 in (262.1 mm) 1.25 in (31.75 mm) 14.75 in (373.4 mm)

Rackmount

Benchtop controller dimensions

Expansion module dimensions

TLA Product Specications & Performance Verication

35

Benchtop and Expansion Mainframe Specications

Table 43: Benchtop and expansion mainframe mechanical (cont.)

Characteristic Weight Mainframe with benchtop controller and slot llers (Typical) Shipping conguration (Typical) Description 58 lbs 11 oz. (26.7 kg) 60 lbs 11 oz. (26.7 kg) minimum conguration with controller (only) and all standard accessories (two manuals, ve dual-wide and one single-wide slot ller panels, power cord, empty pouch, front cover, keyboard, software, and cables) 187 lbs (85 kg) fully congured, same as above with the addition of ve LA modules (four TLA7P4 modules, one TLA7N4 module) and all module standard accessories (probes and clips) 6 lbs 10 oz. (3.0 kg) 3 lbs (1.4 kg) 5 lbs (2.27 kg) 20 lbs (9.1 kg) Three slots wide Single slot wide 43.2 dBA weighted (front) 43.8 dBA weighted (back) 66.2 dBA weighted (front) 66.2 dBA weighted (back) Chassis parts, aluminum alloy Front panel and trim pieces, plastic Circuit boards, glass laminate Mainframes are Tektronix silver gray with dark gray trim on fan pack and bottom feet support rails. Benchtop controllers are Tektronix silver gray on front lexan and injector/ejector assemblies with a black FDD and PC card ejector buttons.

Benchtop controller Expansion module Maximum per slot Rackmount kit adder Size Acoustic noise level (Typical) Benchtop controller Expansion module Variable fan speed (at 860 RPM) Full speed fan (switched at rear) Construction materials Finish type

Figure 6: Dimensions of the benchtop and expansion mainframe

36

TLA Product Specications & Performance Verication

Benchtop and Expansion Mainframe Specications

Figure 7: Dimensions of the benchtop and expansion mainframe with rackmount option

TLA Product Specications & Performance Verication

37

TLA721 Dual Monitor Benchtop Controller Specications

TLA721 Dual Monitor Benchtop Controller Specications

The following tables list the specications for the TLA721 Dual Monitor Benchtop Controller. Table 44: TLA721 benchtop controller characteristics
Characteristic Operating system Microprocessor Main memory Available congurations Installed conguration Speed CAS latency RAS to CAS delay RAS precharge DRAM cycle time Cache memory Flash BIOS Description Microsoft Windows 2000 Intel 733 MHz Pentium III conguration with an Intel 815E chip-set Two 144 pin SODIMM sockets support one or two SDRAM modules. 16, 32, 64, 256 MB per SODIMM 512 MB maximum conguration 133 MHz 2, 3 2, 3 2, 3 5/7 or 7/9 512 KB, level 2 (L2) write-back cache 512 KB Provides PC plug-and-play services with and without Microsoft Windows operating system. Flash based BIOS eld upgradable via a oppy disk Forced recovery jumper is provided Real-time clock/calendar. Standard and advanced PC CMOS setups: see BIOS specications Battery life is typically > 7 years Standard 3.5 inch, 1.44 MB, high-density, double-sided, PC-compatible high-density oppy disk drive Transfer rate Access time (ave.) 500 Kb per second 194 ms

Real-time clock and CMOS setups NVRAM RTC, CMOS setup, & PnP NVRAM retention time (Typical) Floppy disk drive

38

TLA Product Specications & Performance Verication

TLA721 Dual Monitor Benchtop Controller Specications

Table 44: TLA721 benchtop controller characteristics (cont.)

Characteristic Bootable replaceable hard disk drive Size Description Standard PC compatible IDE (Integrated Device Electronics) hard disk drive residing on an EIDE interface 40 GB Continually subject to change due to the fast-moving PC component environment. This storage capacity valid at product introduction. ATA-5/Enhanced IDE (EIDE) Read 12 ms 33.3 MB/s maximum (U-DMA mode 2) 7/14 ms 512 KB Standard PC compatible IDE (Integrated device Electronics) 8x-8x-24x CD-RW drive residing on an IDE interface. Continually subject to change due to the fast-moving PC component environment. Applicable formats Interface Average access time Data-transfer rate (burst sustained) Display classication CD-DA; CE-ROM Mode 1, Mode 2; CD-ROM XA Mode 2 (Form 1, Form 2); Photo CD (single/multi session); Enhanced CD IDE (ATAPI) 130 ms 16.7 MB per second maximum, 1290-3000 KB per second Standard PC graphics accelerator technology (bitBLT based) residing on the Peripheral Component Interconnect (PCI) bus capable of supporting external color VGA, SVGA, or XGA monitors.

Interface Average seek time I/O data-transfer rate Average latency Cache buffer CD-RW Drive

TLA Product Specications & Performance Verication

39

TLA721 Dual Monitor Benchtop Controller Specications

Table 44: TLA721 benchtop controller characteristics (cont.)

Characteristic Display conguration Description Hardware automatically senses a missing at panel LCD in the benchtop mainframe and defaults to the external SVGA monitor output during the BIOS boot sequence (no internal TFT LCD display exists). This is indicated by a single beep during the boot sequence. Dynamic Display Conguration 1 (DDC1) support for the external monitor is provided. 4 MB SDRAM is on board the video controller; no external video memory Two VGA, SVGA, or XGA compatible analog output ports User selected via Microsoft Windows Plug and Play support for DDC1 and DDC2 A and B (Primary video port with Silicon Motion Chip) Resolution (Pixels) 640 x 480 800 x 600 1024 x768 1280 x 1024 1600 x 600 1600 x 1200 Resolution (Pixels) 640 x 480 800 x 600 1024 x768 1280 x 1024 1600 x 1200 Colors 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256, 64 K 256, 64 K Colors 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256 Refresh Rates 60, 75, 85 60, 75, 85 60, 75, 85 60 60 60 Refresh Rates 60, 75, 85 60, 75, 85 60, 75, 85 60, 75, 85 60, 75

Display memory Display drive Display size

(Secondary video port with 815E Chip set)

Table 45: Front panel characteristics

Characteristic SVGA output port (SVGA) Dual USB ports Mouse port Keyboard port Parallel interface port (LPT) Serial interface port (COM) PC CardBus32 port Type I, II, and III PC Card Port Description Two 15-pin sub-D SVGA connectors Two USB (Universal Serial Bus) compliant ports Front panel mounted PS2 compatible mouse port utilizing a mini DIN connector Front panel mounted PS2 compatible keyboard port utilizing a mini DIN connector 36-pin high-density connector supports standard Centronics mode, Enhanced Parallel Port (EPP), or Microsoft high-speed mode (ECP) 9-pin male sub-D connector to support an RS232 serial port Standard Type I and II PC compatible PC card slot Standard Type I, II, and III PC compatible PC card slot

40

TLA Product Specications & Performance Verication

TLA600 Series Specications

TLA600 Series Specications

The following tables list the specications for the TLA600 series logic analyzer. Table 46: TLA600 input parameters with probes
Characteristic Threshold Accuracy Threshold range and step size Threshold channel selection Description 100 mV Settable from +5 V to -2 V in 50 mV steps 16 threshold groups assigned to channels. P6417 and P6418 probes have two threshold settings, one for the clock/qualier channel and one for the data channels. P6434 probes have four threshold settings, one for each of the clock/qualier channels and two for the data channels (one per 16 data channels). 1.6 ns maximum 1.0 ns Asynchronous Sample period Probe input resistance (Typical) Probe input capacitance: P6417, P6434 (Typical) Probe input capacitance: P6418 (Typical) Minimum slew rate (Typical) Maximum operating signal Probe overdrive: P6417, P6418 P6434 20 k 2 pF 1.4 pF data channels 2 pF CLK/Qual channels 0.2 V/ns 6.5 Vp-p -3.5 V absolute input voltage minimum 6.5 V absolute input voltage maximum 250 mV or 25% of signal swing minimum required beyond threshold, whichever is greater 300 mV or 25% of signal swing minimum required beyond threshold, whichever is greater 4 V maximum beyond threshold 15 V 2 ns 7.33 ns Synchronous 500 ps

Channel-to-channel skew Channel-to-channel skew (Typical) Sample uncertainty

Maximum nondestructive input signal to probe Minimum input pulse width signal (single channel) (Typical) Delay time from probe tip to input probe connector (Typical)

Table 47: TLA600 timing latencies

Characteristic System Trigger and External Signal Input Latencies 1 (Typical) External System Trigger Input to LA Probe Tip 2 43 External Signal Input to LA Probe Tip via Signal 3, Description -266 ns -212 ns + Clk -208 ns + Clk

External Signal Input to LA Probe Tip via Signal 1, 2 3 4

TLA Product Specications & Performance Verication

41

TLA600 Series Specications

Table 47: TLA600 timing latencies (cont.)

Characteristic System Trigger and External Signal Output Latencies (Typical) LA Probe Tip to External System Trigger Out 5 LA Probe Tip to External Signal Out via Signal 3, 4 5 LA Probe Tip to External Signal Out via Signal 1, 2 4 5 normal function inverted logic on backplane
1 2 3

Description 376 ns + SMPL OR function AND function 364 ns + SMPL 364 ns + SMPL 366 ns + SMPL 379 ns + SMPL

All system trigger and external signal input latencies are measured from a falling-edge transition (active true low) with signals measured in the wired-OR conguration. In the Waveform window, triggers are always marked immediately except when delayed to the rst sample. In the Listing window, triggers are always marked on the next sample period following their occurrence. "Clk" represents the time to the next master clock at the destination logic analyzer. In the asynchronous (or internal) clock mode, this represents the delta time to the next sample clock beyond the minimum asynchronous rate of 4 ns. In the synchronous (or external) clock mode, this represents the time to the next master clock generated by the setup of the clocking state machine and the supplied system under test clocks and qualication data. Signals 1 and 2 (ECLTRG0, 1) are limited to a "broadcast" mode of operation, where only one source is allowed to drive the signal node at any one time. That single source may be utilized to drive any combination of destinations. SMPL represents the time from the event at the probe tip inputs to the next valid data sample. With asynchronous sampling, this represents the delta time to the next sample clock. With MagniVu asynchronous sampling, this represents 500 ps or less. With synchronous sampling, this represents the time to the next master clock generated by the setup of the clocking state machine, the system-under-test supplied clocks, and the qualication data.

4 5

Table 48: TLA600 external signal interface

Characteristic System Trigger Input Input Levels VIH VIL Input Mode Minimum Pulse Width Active Period Maximum Input Voltage External Signal Input Input Destination Input Levels VIH VIL Input Mode Input Bandwidth 1 Description TTL compatible input via rear panel mounted BNC connectors TTL compatible input 2.0 V 0.8 V Falling edge sensitive, latched (active low) 12 ns Accepts system triggers during valid acquisition periods via real-time gating, resets system trigger input latch between valid acquisition periods 0 to +5 V peak TTL compatible input via rear panel mounted BNC connectors Signal 1, 2, 3, 4 TTL compatible input 2.0 V 0.8 V Active (true) low, level sensitive Signal 1, 2 50 MHz square wave minimum Active Period Maximum Input Voltage 0 to +5 V peak Signal 3, 4 10 MHz square wave minimum

Accepts signals during valid acquisition periods via real-time gating

42

TLA Product Specications & Performance Verication

TLA600 Series Specications

Table 48: TLA600 external signal interface (cont.)

Characteristic System Trigger Output Source Mode Active Period Output Levels VOH VOL Output Protection External Signal Output Source Selection Output Modes Level Sensitive Output Levels VOH VOL Output Bandwidth 2 Active Period Description TTL compatible output via rear panel mounted BNC connectors Active (true) low, falling edge latched Outputs system trigger state during valid acquisition period, resets system trigger output to false state between valid acquisitions 50 back terminated TTL-compatible output 4 V into open circuit 2 V into 50 to ground 0.7 V sinking 10 mA Short-circuit protected (to ground) TTL compatible outputs via rear panel mounted BNC connectors Signal 1, 2, 3, 4, or 10 MHz clock User denable Active (true) low or active (true) high 50 Ohm back terminated TTL output 4 V into open circuit 2 V into 50 to ground 0.7 V sinking 10 mA Signal 1, 2 50 MHz square wave minimum Signal 3, 4 10 MHz square wave minimum

Outputs signals during valid acquisition periods, resets signals to false state between valid acquisitions Outputs 10 MHz clock continuously Short-circuit protected (to ground)

Output Protection
1 2

The Input Bandwidth specication only applies to signals to the modules; it does not apply to signals applied to the External Signal Input and sent back to the External Signal Output. The Output Bandwidth specication only applies to signals from the modules; it does not apply to signals applied to the External Signal Input and sent back to the External Signal Output.

Table 49: TLA600 channel width and depth

Characteristic Number of channels Description Product TLA601, TLA611, TLA621 TLA602, TLA612, TLA622 TLA603, TLA613, TLA623 TLA604, TLA614, TLA624 Acquisition memory depth Product TLA601, TLA602, TLA603, TLA604 TLA611, TLA612, TLA613, TLA614 TLA621, TLA622, TLA623, TLA624 Channels 32 data and 2 clock 64 data and 4 clock 96 data, 4 clock, and 2 qualier 128 data, 4 clock, and 4 qualier Memory depth 64 K or 256 K samples 1 64 K or 256 K samples 1 1 M samples

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TLA600 Series Specications

PowerFlex options

Table 50: TLA600 clocking

Characteristic Asynchronous sampling Sampling period 1 Minimum recognizable word 2 (across all channels) 4 ns to 50 ms in a 1-2-5 sequence Channel-to-channel skew + sample uncertainty Example: for a P6417, P6418, or P6434 Probe and a 4 ns sample period = 1.6 ns + 4 ns = 5.6 ns Product TLA601, TLA611, TLA621 TLA602, TLA612, TLA622 TLA603, TLA613, TLA623 TLA604, TLA614, TLA624 Number of qualier channels 5 Product TLA601, TLA611, TLA621 TLA602, TLA612, TLA622 TLA603, TLA613, TLA623 TLA604, TLA614, TLA624 Setup and hold window size (data and qualiers) Clock Channels 2 4 4 4 Qualier Channels 0 0 2 4 Description

synchronous sampling Number of clock channels 3

Maximum window size = Maximum channel-to-channel skew + (2 x sample uncertainty) + 0.4 ns Maximum setup time = User interface setup time + 0.8 ns Maximum hold time = User interface hold time + 0.2 ns Examples: for a P6417 or a P6418 probe and user interface setup and hold of 2.0/0.0 typical: Maximum window size = 1.6 ns + (2 x 500 ps) + 0.4ns = 3.0 ns Maximum setup time = 2.0 ns + 0.8 ns = 2.8 ns Maximum hold time = 0.0 ns + 0.2 ns = 0.2ns

Setup and hold window size (data and qualiers) (Typical) Setup and hold window range

Channel-to-channel skew (typical) + (2 x sample uncertainty) Example: for P6417 or P6418 Probe = 1 ns + (2 x 500 ps) = 2 ns For each channel, the setup and hold window can be moved from +8.5 ns (Ts) to -7.0 ns (Ts) in 0.5 ns steps (setup time). Hold time follows the setup time by the setup and hold window size. 200 MHz in full speed mode (5 ns minimum between active clock edges) 100 MHz (10 ns minimum between active clock edges)

Maximum synchronous clock rate 4 Demux clocking

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Table 50: TLA600 clocking (cont.)

Characteristic TLA603, TLA613, TLA623 TLA604, TLA614, TLA624 Description Channels multiplex as follows: A3(7:0) to A2(7:0) to A1(7:0) to A0(7:0) to Channels multiplex as follows: A3(7:0) to A2(7:0) to A1(7:0) to A0(7:0) to C3(7:0) C2(7:0) D1(7:0) TLA602, TLA612, TLA622 D0(7:0) TLA602, TLA612, TLA622 D3(7:0) D2(7:0) D1(7:0) D0(7:0)

TLA601, TLA611, TLA621 TLA602, TLA612, TLA622

Time between DeMux clock edges 4 (Typical) Time between DeMux store clock edges 4 (Typical) Data Rate
4

5 ns minimum between Demux clock edges in full-speed mode 10 ns minimum between Demux clock edges in half-speed mode 10 ns minimum between Demux master clock edges in full-speed mode 20 ns minimum between Demux master clock edges in half-speed mode 400 MHz (200 MHz option required) half channel. (Requires channels to be multiplexed.) These multiplexed channels double the memory depth. Each channel can be programmed with a pipeline delay of 0 through 3 active clock edges.

(Typical)

Clocking state machine Pipeline delays

1 2 3 4 5

It is possible to use storage control and only store data when it has changed (transitional storage). Applies to asynchronous sampling only. Setup and hold window specication applies to synchronous sampling only. Any or all of the clock channels may be enabled. For an enabled clock channel, either the rising, falling, or both edges can be selected as the active clock edges. The clock channels are stored. Full and half speed modes are controlled by PowerFlex options and upgrade kits. All qualier channels are stored. For custom clocking there are an additional 4 qualier channels on C2 3:0 regardless of channel width.

Table 51: TLA600 trigger system

Characteristic Triggering Resources Word/Range recognizers 16 word recognizers. The word recognizers can be combined to form full width, double bounded, range recognizers. The following selections are available: 16 word recognizers 13 word recognizers 10 word recognizers 7 word recognizers 4 word recognizers 0 range recognizers 1 range recognizer 2 range recognizers 3 range recognizers 4 range recognizers Description

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TLA600 Series Specications

Table 51: TLA600 trigger system (cont.)

Characteristic Range recognizer channel order Description From most-signicant probe group to least-signicant probe group: C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3 CK2 CK1 CK0 Missing channels for modules with fewer than 136 channels are omitted. Each channel group can be enabled to detect a glitch. 2.0 ns (single channel with P6417, P6418, or a P6434 probe) Each channel can be enabled to detect a setup and hold violation. The range is from 8 ns before the clock edge to 8 ns after the clock edge. The range can be selected in 0.5 ns increments. The setup and hold violation of each window can be individually programmed. Each channel group can be enabled or disabled to detect a transition between the current valid data sample and the previous valid data sample. This mode can be used to create transitional storage selections where all channels are enabled. 2 counter/timers, 51 bits wide, can be clocked up to 250 MHz. Maximum count is 251. Maximum time is 9.007 X 106 seconds or 104 days. Counters and timers can be set, reset, or tested and have zero reset latency. A backplane input signal A backplane input signal that causes the main acquisition and the MagniVu acquisition to trigger if they are not already triggered 16 maximum (excluding counter/timers) Word recognizers are traded off one-by-one as External Signal In, glitch detection, setup and hold detection, or transition detection resources are added. 16 Same rate as valid data samples received, 250 MHz maximum Triggers the main acquisition memory Trigger position is programmable to any data sample (4 ns boundaries) Triggering of MagniV memory is controlled by the main acquisition trigger The MagniV trigger position is programmable within 4 ns boundaries and separate from the main acquisition memory trigger position. Either of the two counter/timers used as counters can be increased. Either of the two counter/timers used as timers can be started or stopped. Either of the two counter/timers can be reset. When a counter/timer is used as a timer and is reset, the timer continues from the started or stopped state that it was in prior to the reset.

Glitch detector 1 2 Minimum detectable glitch pulse width (Typical) Setup and hold violation detector 1 3

Transition detector 1

Counter/Timers

External Signal In 1 External Trigger In Active trigger resources

Trigger States Trigger State sequence rate Trigger Machine Actions Main acquisition trigger Main trigger position MagniVu acquisition trigger MagniVu trigger position Increment counter Start/Stop timer Reset counter/timer

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Table 51: TLA600 trigger system (cont.)

Characteristic Signal out Trigger out Storage Control Global storage Storage is allowed only when a specic condition is met. This condition can use any of the trigger machine resources except for the counter/timers. Storage commands dened in the current trigger state will override the global storage control. Global storage can be used to start the acquisition with storage initially turned on (default) or turned off. Storage can be turned on or off; only the current sample can be stored. The event storage control overrides any global storage commands. When enabled, 31 samples are stored before and after the valid sample. Not allowed when glitch storage or setup and hold violation is enabled. The acquisition memory can be enabled to store glitch violation information with each data sample when asynchronous sampling is used. The probe data storage size is reduced by one half (the other half holds the violation information). The fastest asynchronous sampling rate is reduced to 10 ns. The acquisition memory can be enabled to store setup and hold violation information with each data sample when synchronous sampling is used. The probe data storage size is reduced by one half (the other half holds the violation information). The maximum clock rate is reduced by half. Description A signal sent to the backplane to be used by other instruments A trigger out signal sent to the backplane to trigger other instruments

By event Block storage Glitch violation storage

Setup and hold violation storage

1 2 3

Each use of External Signal In, glitch detector, setup and hold violation detector, or transition detector requires a trade-off of one word recognizer resource. Any glitch is subject to pulse width variation of up to the channel-to-channel skew specication + 0.5 ns. Any setup value is subject to variation of up to 1.8 ns; any hold value is subject to variation of up to 1.2 ns.

Table 52: TLA600 MagniVu feature

Characteristic MagniVu memory depth MagniVu sampling period Description 2016 samples per channel Data is asynchronously sampled and stored every 500 ps in a separate high resolution memory. There are no clocking options.

Table 53: TLA600 Data handling

Characteristic Nonvolatile memory retention time (Typical) Description Battery is integral to the NVRAM. Battery life is > 10 years.

Table 54: TLA600 internal controller

Characteristic Operating System Microprocessor Description Microsoft Windows Intel Celeron, 566 MHz

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TLA600 Series Specications

Table 54: TLA600 internal controller (cont.)

Characteristic Main Memory Style Speed Installed Congurations Real-Time Clock and CMOS Setups, Plug & Play NVRAM Retention Time Hard Disk Drive Size Description SDRAM 168 pin DIMM, 2 Sockets 100 MHz Minimum 256 MB loaded in one socket Maximum 512 MB with both sockets loaded Battery life is typically > 3 years when the logic analyzer is not connected to line voltage. When connected to line voltage the life of the battery is extended. Lithium battery, CR3032 Standard PC compatible IDE (Integrated Device Electronics) hard disk drive residing on an EIDE interface. Minimum 10 GB Maximum 30 GB Continually subject to change due to the fast-moving PC component environment. These storage capacities valid at product introduction. Standard PC compatible IDE (Integrated Device Electronics) 24x-10x-40x CD-RW drive residing on an EIDE interface. Continually subject to change due to the fast-moving PC component environment. Standard 3.5 inch 1.44 MB PC compatible high-density, double-sided oppy disk drive.

CD-RW Drive

Floppy Disk Drive

Table 55: TLA600 display system

Characteristic Classication Description Standard PC graphics accelerator technology (bitBLT-based); capable of supporting both internal color LCD display and external color SVGA/XGA monitor DRAM-based frame-buffer memory Size Display Selection External Display Drive Display Size 2 MB Both front panel and external displays can be used simultaneously, each with independent resolutions. Supports Windows dual-monitor capability. One SVGA/XGA-compatible analog output port Selected via Windows Plug and Play support for DDC1 and DDC2 A and B Resolution (Pixels) 640 x 480 800 x 600 1024 x 768 1280 x 1024 Colors 256, 64 K, 16.8 M 256, 64 K, 16.8 M 256, 64 K, 8 M 256, 64 K, 8 M

Display Memory

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Table 55: TLA600 display system (cont.)

Characteristic Internal Display Classication Description Thin Film Transistor (TFT) 10.4 inch active-matrix color LCD display; CCFL backlight; intensity controllable via software 800 x 600 pixels 262,144 colors (6-bit RGB)

Resolution Color Scale

Table 56: TLA600 front-panel interface

Characteristic QWERTY Special Function Knobs Description ASCII to support naming of les, traces, and keyboard equivalents of pointing device inputs for menus Various functions

Table 57: TLA600 rear-panel interface

Characteristic Parallel Interface Port (LPT) Serial Interface Port (COM 1) Single USB Ports SVGA Output Port (SVGA OUT) Mouse Port Keyboard Port Type I and II PC Card Port Type I, II, and III PC Card Port Description 36-pin high-density connector supports standard Centronics mode, Enhanced Parallel Port (EPP), or Microsoft high-speed mode (ECP) 9-pin male sub-D connector to support RS-232 serial port One USB (Universal Serial Bus) compliant port 15-pin sub-D SVGA connector PS/2 compatible mouse port utilizing a mini DIN connector PS/2 compatible keyboard port utilizing a mini DIN connector Standard Type I and II PC-compatible PC card slot Standard Type I, II, and III PC-compatible PC card slot

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TLA600 Series Specications

Table 58: TLA600 AC power source

Characteristic Source Voltage and Frequency Fuse Rating 90 V - 132 V Operation (2 required) 90 V - 250 V Operation (2 required) Maximum Power Consumption Steady-State Input Current Inrush Surge Current Power Factor Correction On/Standby Switch and Indicator Description 90-250 VRMS, 45-66 Hz, continuous range CAT II 100-132 VRMS, 360-440 Hz, continuous range CAT II UL198/CSA C22.2 0.25 in 1.25 in, Fast Blow, 8 A, 250 V IEC 127/Sheet 1 5 mm 20 mm, Fast Blow, 6.3 A, 250 V 600 Watts line power maximum 6 ARMS maximum 70 A maximum Yes Front Panel On/Standby switch, with indicator. The power cord provides main power disconnect.

Table 59: TLA600 cooling

Characteristic Cooling System Cooling Clearance Description Forced air circulation (negative pressurization) utilizing six fans operating in parallel 2 in (51 mm), sides and rear; unit should be operated on a at, unobstructed surface

Table 60: TLA600 mechanical characteristics

Characteristic Weight TLA614, TLA624, TLA613, and TLA623 TLA612, TLA622, TLA611, and TLA621 TLA604 and TLA603 TLA602 and TLA601 Description Includes empty accessory pouch and front cover 18.1 Kg (40 lbs) 18 Kg (39.75 lbs) 17.6 Kg (38.75 lbs) 17.5 Kg (38.5 lbs)

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TLA600 Series Specications

Figure 8: Dimensions of the TLA600 series logic analyzer

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TLA7Axx/TLANAx Series Logic Analyzer Module Specications

TLA7Axx/TLANAx Series Logic Analyzer Module Specications

The following tables list the specications of the TLA7Axx/TLA7NAx Series Logic Analyzer modules. Table 61: TLA7Axx/TLA7NAx input parameters (with probes)
Characteristic Threshold accuracy (Certiable parameter) Threshold range and step size Threshold channel selection Description (35 mV + 1% of the threshold voltage setting) Settable from +4.5 V to -2.0 V in 5 mV steps 16 threshold groups assigned to channels. Each probe has four threshold settings, one for each of the clock/qualier channels and one per group of 16 data channels. 400 ps maximum When merged, add the following for slave modules: 0.0 ns when data is acquired on the slave modules through local clocks 125 ps when data is acquired on the slave modules using the master modules clock and merge deskew has been performed. 375 ps when data is acquired on the slave modules using the master modules clock and merge deskew has NOT been performed. 300 ps When merged, add the following for slave modules: 0.0 ns when data is acquired on the slave modules through local clocks 125 ps when data is acquired on the slave modules via the master modules clock and merge deskew has been performed. 375 ps when data is acquired on the slave modules via the master modules clock and merge deskew has NOT been performed. Asynchronous Sample period Minimum slew rate (Typical) Input voltage range Maximum operating voltage swing Probe overdrive Single ended probes Differential probes Maximum nondestructive input signal to probe Minimum input pulse width (single channel) (Typical) 0.2 V/ns -2.5 V to +5 V 6.0 V peak-to-peak 150 mV or 25% of signal swing minimum required beyond threshold, whichever one is greater Vpos-Vneg is 150 mVp-p 15V P6860, P6880, P6960, and P6980 probes P6810 probes 500 ps 750 ps Synchronous 125 ps

Channel to channel skew

Channel to channel skew (Typical)

Sample uncertainty

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Table 61: TLA7Axx/TLA7NAx input parameters (with probes) (cont.)

Characteristic Delay time from probe tip to input probe connector (Typical) Description P6860, P6960, and P6980 probes P6810 and P6880 probes 7.7 ns 60ps 7.7 ns 80ps

Table 62: TLA7Axx analog output

Characteristic Number of outputs Attenuation Bandwidth (Typical) Accuracy (gain and offset) (Typical) Description Four analog outputs regardless of the module channel width. Any four of the modules channels can be mapped to the four analog outputs. 10X mode for normal operation 5X mode for small signals (-1.5 V to +2.5 V) 2 GHz (50 mV + 2% of signal amplitude)

Table 63: Channel width and depth

Characteristic Number of channels TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 TLA7AA3, TLA7AC3, TLA7NA3 TLA7AA2, TLA7AB2, TLA7AC2, TLA7NA2 TLA7AA1, TLA7NA1 Acquisition memory depth TLA7AAx, TLA7NAx series TLA7ABx series TLA7ACx series Description 128 data, 8 clock/qualier 96 data, 6 clock/qualier 64 data, 4 clock/qualier 32 data, 2 clock/qualier 32 M per channel, maximum 64 M per channel, maximum 128 M per channel, maximum

Table 64: Clocking

Characteristic Asynchronous sampling Sampling period 500 ps to 50 ms in a 1-2-5 sequence. Storage control can be used to only store data when it has changed (transitional storage) 2 ns minimum for all channels 1 ns minimum for half channels (using 2:1 Demultiplex mode) 0.5 ns minimum for quarter channels (using 4:1 Demultiplex mode) Channel-to-channel skew + sample uncertainty Example for a P6860 high-density probe and a 2 ns sample period: 400 ps + 2 ns = 2.4 ns Description

Minimum recognizable word 1 (across all channels)

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TLA7Axx/TLANAx Series Logic Analyzer Module Specications

Table 64: Clocking (cont.)

Characteristic synchronous sampling Master clock channels 2 Product 32+2 module 64+4 module 96+6 module 128+8 module Merged slave clock channels 2 (64+4 channel modules and 32+2 channel modules cannot be merged.) Qualier channels Note: Qualier channels are stored. Product 96+6 module 128+8 module Product 32+2 module 64+4 module 96+6 module 128+8 module 500 ps Maximum window size = Maximum channel-to-channel skew + (2 x sample uncertainty) + 100 ps Maximum setup time = User interface setup time + 75 ps Maximum hold time = User interface hold time + 50 ps Example using a P6800 series probe and user interface setup and hold of 625/0 typical: Maximum window size = 400 ps + 250 ps + 100 ps = 750 ps Maximum setup time = 625 ps + 75 ps = 700 ps Maximum hold time = 0.0 ps + 50 ps = 50 ps Typical window size = Typical channel-to-channel skew + (2 x sample uncertainty) + 75 ps Example using P6860 probe: 300 ps + 250 ps + 75 ps = 625 ps For each channel, the setup and hold window can be moved from +8.0 ns (Ts typical) to -8.0 ns (Ts typical) in 0.125 ns steps (setup time). The setup and hold window can be shifted toward the setup region by 0 ns, 4 ns, or 8 ns. With a 0 ns shift, the range is +8 ns to -8 ns; with a 4 ns shift, the range is +12 ns to -4 ns; with an 8 ns shift, the range is +16 ns to 0 ns. The sample point selection region is the same setup and hold window. Setup times are specied as typical gures. Hold time follows the setup time by the setup and hold window size. Clock channels 2 4 4 4 Clock channels 4 4 Qualier channels 0 0 2 4 Description

Single channel setup and hold window size (Typical) Single module setup and hold window size (data and qualiers)

Single module setup and hold window size (data and qualiers) (Typical) Setup and hold window range

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Table 64: Clocking (cont.)

Characteristic Maximum synchronous clock rate TLA7Axx series Description 450 MHz in full-speed mode (2.2 ns minimum between active clock edges) 235 MHz in half-speed mode (4.25 ns minimum between active clock edges) 120 MHz in quarter-speed mode (8.3 ns minimum between active clock edges) 800 MHz on half channels 3 Software controls the selection between full-speed and half-speed modes. 450 MHz in full-speed mode (2.2 ns minimum between active clock edges) 235 MHz in full-speed mode (4.25 ns minimum between active clock edges) 120 MHz in quarter-speed mode (8.3 ns minimum between active clock edges) Software controls the selection between full-speed and half-speed modes. Any individual channel can be demultiplexed with its partner channel. If multiplexing is enabled, all of the A and D channels are multiplexed; there is no individual selection. Channels demultiplex as follows: A3(7:0) to/from A2(7:0) to/from A1(7:0) to/from A0(7:0) to/from E3(7:0) to/from E2(7:0) to/from CK3 to/from CK2 to/from CK1 to/from CK0 to/from TLA7AA1, TLA7AA2, TLA7AB2, TLA7AC2, TLA7NA1, TLA7NA2 modules D3(7:0) D2(7:0) D1(7:0) D0(7:0) E1(7:0) TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 modules only E0(7:0) TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 modules only Q2 TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 modules only Q3 TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 modules only Q0 Q1

Maximum synchronous clock rate TLA7NAx series

Demultiplex clocking Demultiplex channels (2:1) TLA7AA3, TLA7AA4, TLA7AB4, TLA7AC3, TLA7AC4, TLA7NA3, TLA7NA4 modules

Any individual channel can be demultiplexed with its partner channel. If multiplexing is enabled, all of the A and D channels are multiplexed; there is no individual selection. Channels demultiplex as follows: A3(7:0) to/from A2(7:0) to/from A1(7:0) to/from A0(7:0) to/from C3(7:0) C2(7:0) D1(7:0) TLA7AA2, TLA7AB2, TLA7AC2, TLA7NA2 modules only D0(7:0) TLA7AA2, TLA7AB2, TLA7AC2, TLA7NA2 modules only

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TLA7Axx/TLANAx Series Logic Analyzer Module Specications

Table 64: Clocking (cont.)

Demultiplex clocking Demultiplex channels (4:1) TLA7AA3, TLA7AA4, TLA7AB4, TLA7AC3, TLA7AC4, TLA7NA3, TLA7NA4 modules Unlike the 2:1 Demultiplex, the channels within a group of four cannot arbitrarily drive the others. E3(7:0) to A3(7:0) to A1(7:0) to C3(7:0) to CK3 to CK1 to TLA7AA1, TLA7AA2, TLA7AB2, TLA7AC2, TLA7NA2, TLA7NA1 modules E2(7:0), E1(7:0), E0(7:0) TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 modules only A2(7:0), D3(7:0), D2(7:0) A0(7:0), D1(7:0), D0(7:0) C2(7:0), C1(7:0), C0(7:0) CK2, Q3, Q2 TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 modules only CK0, Q1, Q0

Unlike the 2:1 Demultiplex, the channels within a group of four cannot arbitrarily drive the others. A1(7:0) to C3(7:0) to A0(7:0), D1(7:0), D0(7:0) TLA7AA2, TLA7AB2, TLA7AC2 TLA7NA2 modules only C2(7:0), A3(7:0), A2(7:0)

Time between Demultiplex clock edges (Typical) Source synchronous sampling (TLA7Axx) Clocks per module Clocks with merged modules Clock groups Size of clock group valid FIFO

Same limitations as normal synchronous acquisition

Four When merged, the slave modules have two clocks available from the master module. Including the local clocks, the total is six clocks. Four for a single module and for a merged system Four stages when operated at 235 MHz or below (three stages when operated above 235 MHz); this allows four (source synchronous or other) clocks to occur before the clock that completes the Clock Group Valid signal for that group. Channel-to-channel skew only

Source synchronous clock alignment window

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Table 64: Clocking (cont.)

Demultiplex clocking Source synchronous clock reset The Clock Group Valid FIFO can be reset in one of the two ways: 1. By the overow of a presettable (0-255) 8-bit counter that counts one of the following clocks: 2ns Clock or the master heartbeat clock (synchronous or asynchronous). An active edge places the reset count to its preset value. An active clock edge will clear the Clock Group Valid reset before the clock gets to the FIFO so that no data is lost. 2. By enabling an external reset. In this mode, one of the clock channels must be traded on the master module to act as a level-sensitive reset input. Any one of the clocks can be selected. A polarity selection is available. This mode affects all Clock Group Complete circuits. Neither one of the above modes can be intermixed; one or the other must be selected. Channel groups can be programmed with a pipeline delay of 0 through 7 active clock changes.

Clocking state machine Pipeline delays

1 2 3

Specication only applies with asynchronous clocking. With synchronous sampling, the setup and hold window size applies. Any clock channel can be enabled. For enabled clock channels, either the rising, falling, or both edges can be selected as active clock edges; clock channels are stored. This is a special mode and has some limitations such as the clocking state machine and trigger state machine only running at 500 MHz.

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TLA7Axx/TLANAx Series Logic Analyzer Module Specications

Table 65: TLA7Axx/TLA7NAx module trigger system

Characteristic Trigger resources Word recognizers and range recognizers 16, word recognizers can be combined to form full width, double bounded range recognizers. The following selections are available: 16 word recognizers 13 word recognizers 10 word recognizers 7 word recognizers 4 word recognizers Range recognizer channel order 0 range recognizers 1 range recognizer 2 range recognizers 3 range recognizers 4 range recognizers Description

From most-signicant probe group to least-signicant probe group: C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3 CK2 CK1 CK0 Missing channels for modules with fewer than 136 channels are omitted. When merged, the range recognition extends across the modules. The master module contains the most-signicant groups. Channel groups can be enabled to detect glitches. Glitches are subject to pulse width variations of up to 125ps Minimum input pulse width (single channel) P6860, P6960 high density probe: P6880, P6980 differential probe: P6810 general purpose probe: 500 ps 500 ps 750 ps

Glitch detector (normal asynchronous clock mode) Minimum detectable glitch pulse width (Typical)

Setup and hold violation detector (normal synchronous clock mode)

Any channel can be enabled to detect a setup or hold violation. The range is from 8.0 ns before the clock edge to 8.0 ns after the clock edge in 0.125 ns steps. The channel setup and hold violation size can be individually programmed. The range can be shifted towards the positive region by 0 ns, 4 ns, or 8 ns. With a 0 ns shift, the range is +8 ns to -8 ns; with a 4 ns shift, the range is +12 ns to -4 ns; with an 8 ns shift, the range is +16 ns to 0 ns. The sample point selection region is the same as the setup and hold window. Any setup value is subject to variation of up to the channel skew specication. Any hold value is subject to variation of up to the channel skew specication. 16 transition detectors. Any channel group can be enabled or disabled to detect a rising transition, a falling transition, or both rising and falling transitions between the current valid data sample and the previous valid data sample. 2 counter/timers, 51 bits wide, can be clocked up to 500 MHz Maximum count is 2^50-1 (excluding sign bit) Maximum time is 4.5 X 106 seconds or 52 days Counters can be used as Settable, resettable, and testable ags. Counters can be reset, do nothing, increased, or decreased. Timers can be reset, started, stopped, or not changed. Counters and timers have zero reset latency and one clock terminal count latency. A backplane input signal.

Transition detector

Counter/timers

Signal In 1

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TLA7Axx/TLANAx Series Logic Analyzer Module Specications

Table 65: TLA7Axx/TLA7NAx module trigger system (cont.)

Characteristic Signal In 2 Trigger In Active trigger resources Description A backplane input signal. A backplane input signal that causes the main acquisition and the MagniVu acquisition to trigger if they are not already triggered. 16 maximum (excluding counter/timers) Word recognizers are traded off one-for-one as Signal In 1, Signal In 2, glitch detection, setup and hold detection, or transition detection resources are added. 16 Same rate as valid data samples received. 500 MHz maximum. Triggers the main acquisition memory Programmable to any data sample (2 ns boundaries) Main acquisition machine controls the triggering of the MagniVu memory Programmable within 2 ns boundaries and separate from the main acquisition memory trigger position Counter/timers used as counters can be increased or decreased. Either of the two counter/timers used as timers can be started or stopped. Either of the two counter/timers can be reset. When a counter/timer used as a timer is reset, the timer continues in the started or stopped state that it was prior to the reset. Loads the current acquired data sample into the reference value of the word recognizer via a trigger machine action. All data channels are loaded into their respective word recognizer reference register on a one-to-one manner. 378 ns A signal sent to the backplane to be used by other modules A signal sent to the backplane to trigger other modules Storage is allowed only if a specic condition is met. The condition can use any of the trigger resources except for counter/timers. Storage commands dened in the current trigger state will override the global storage control. Storage can be used to start the acquisition with storage initially turned on (default setting) or off. Storage can be turned on or off; only the current sample can be stored. Event storage control overrides any global storage commands. When enabled, 31 samples are stored before and after the valid sample. This allows the storage of a group of samples around a valid data sample when storage control is being used. This only has meaning when storage control is used. Block storage is disallowed when glitch storage or setup and hold violation storage is enabled.

Trigger states Trigger state sequence rate Trigger machine actions Main acquisition trigger Main trigger position MagniVu trigger MagniVu trigger position Increment/decrement counter Start/stop timer Reset counter/timer

Reloadable word recognizer (snapshot)

Reloadable word recognizer latency Signal Out Trigger Out Storage control Storage

By event Block storage (store stretch)

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TLA7Axx/TLANAx Series Logic Analyzer Module Specications

Table 65: TLA7Axx/TLA7NAx module trigger system (cont.)

Characteristic Glitch violation storage Description Glitch violation information can be stored to acquisition memory with each data sample when asynchronous sampling is used. The acquisition data storage size is reduced by half when this mode is enabled (the other half holds violation information). The fastest asynchronous clock rate is reduced to 4 ns. Setup and hold violation information can be stored to acquisition memory with each data sample when synchronous sampling is used. The acquisition data storage size is reduced by half when this mode is enabled (the other half holds violation information). The maximum synchronous clock rate in this mode is 235 MHz.

Setup and hold violation storage

Table 66: MagniVu acquisition

Characteristic MagniVu sampling period Description Data is asynchronously sampled and stored every 125 ps in a separate MagniVu (high-resolution) memory. The storage speed can be changed by software to 250 ps, 500 ps, or 1000 ps with no loss in memory depth so that the high resolution memory covers more time at a lower resolution. Approximately 16 K per channel. The MagniVu memory is separate from the main acquisition memory.

MagniVu memory depth

Table 67: Merged modules

Characteristic Number of merged modules Description 2, 3, 4, or 5 adjacent modules can be merged. Only 102-channel modules or 136-channel modules can be merged. Merged modules can have unequal channel widths and channel depths. The sum of all channels available on each of the merged modules including clocks and qualiers. No channels are lost when modules are merged. Channel depth is equal to that of the shallowest module. The qualier channels on the slave modules can only be used as data channels. They cannot inuence the actual clocking function of the logic analyzer (for example, log strobe generation). The clock channels on the slave TLA7Axx modules can capture data on those modules for source-synchronous applications. Each slave module contributes four additional clock channels to the merged set. All clock and qualier channels are stored to acquisition memory. The same as a single module except for word recognizer width, setup and hold violation detector width, glitch detector width, and transition detector width has increased to equal that of the merged channel width. Range recognizers will increase to the merged channel width up to three modules; range recognition is not supported on the two outside slave modules. Most signicant Master, Slave 1, Slave 2

Number of channels after merging Merged system acquisition depth Number of clock and qualier channels after merging

Merged system trigger resources

Merged range signicance

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TLA7Axx/TLANAx Series Logic Analyzer Module Specications

Table 68: Data placement

Characteristic Timestamp counter resolution and duration Description 125 ps resolution 3.25 days duration

Table 69: NVRAM

Characteristic Nonvolatile memory retention time (Typical) Description The battery life is integral to the NVRAM; battery life is > 10 years.

Table 70: Mechanical

Characteristic Material Description Chassis parts are constructed of aluminum alloy. The front panel is constructed of plastic laminated to steel front panel. Circuit boards are constructed of glass laminate. 136-channel module 102-channel module 68-channel module 34-channel module 5 lb 6 oz. (2.438 kg) 5 lb 4 oz. (2.381 kg) 5 lb 0.5 oz. (2.282 kg) 4 lb 15.5 oz. (2.254 kg) 7 lb 12 oz. (3.515 kg) for 136-channel module when packaged for domestic shipment Height Width Length Mainframe interlock 10.32 in (262 mm) 2.39 in (61 mm) with merge connector recessed, 0.41 in (10.41 mm) with merge connector extended 14.7 in (373 mm) 1.4 ECL keying is implemented

Weight

Shipping weight Overall dimensions

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TLA7Lx/Mx/Nx/Px/Qx Module Specications

TLA7Lx/Mx/Nx/Px/Qx Module Specications

The following tables list the specications of the TLALx/Mx/Nx/Px/Qx logic analyzer modules. Table 71: LA module channel width and depth
Characteristic Number of channels Description Product TLA7N1, TLA7L1, TLA7M1 TLA7N2, TLA7P2, TLA7Q2, TLA7L2, TLA7M2 TLA7N3, TLA7L3, TLA7M3 TLA7N4, TLA7P4, TLA7Q4, TLA7L4, TLA7M4 Acquisition memory depth Product TLA7L1, TLA7L2, TLA7L3, TLA7L4 TLA7M1, TLA7M2, TLA7M3, TLA7M4 TLA7N1, TLA7N2, TLA7N3, TLA7N4 TLA7P2, TLA7P4 TLA7Q2, TLAQP4
1

Channels 32 data and 2 clock 64 data and 4 clock 96 data, 4 clock, and 2 qualier 128 data, 4 clock, and 4 qualier Memory depth 32 K or 128 K samples 1 512 K samples 64 K or 256 K or 1 M or 4 M samples 16 M samples 64 M samples

PowerFlex options

Table 72: LA module clocking

Characteristic Asynchronous sampling Sampling period 1 Minimum recognizable channels) synchronous sampling Number of clock channels 3 Product TLA7N1, TLA7L1, TLA7M1 TLA7N2, TLA7P2, TLA7Q2, TLA7L2, TLA7M2 TLA7N3, TLA7L3, TLA7M3 TLA7N4, TLA7P4, TLA7Q4, TLA7L4, TLA7M4 Number of qualier channels Product TLA7N1, TLA7L1, TLA7M1 TLA7N2, TLA7P2, TLA7Q2, TLA7L2, TLA7M2 TLA7N3, TLA7L3, TLA7M3 TLA7N4, TLA7P4, TLA7Q4, TLA7L4, TLA7M4 Clock channels 2 4 4 4 Qualier channels 0 0 2 4 word 2 (across all 2 ns to 50 ms in a 1-2-5 sequence Channel-to-channel skew + sample uncertainty Example: for a P6417 or a P6418 Probe and a 4 ns sample period = 1.6 ns + 4 ns = 5.6 ns Description

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TLA7Lx/Mx/Nx/Px/Qx Module Specications

Table 72: LA module clocking (cont.)

Characteristic Setup and hold window size (data and qualiers) Description Maximum window size = Maximum channel-to-channel skew + (2 x sample uncertainty) + 0.4 ns Maximum setup time = User interface setup time + 0.8 ns Maximum hold time = User interface hold time + 0.2 ns Maximum setup time for slave module of merged pair = User Interface setup time + 0.8 ns Maximum hold time for slave module of merged pair = User Interface hold time + 0.7 ns Examples: for a P6417, P6418, or P6434 probe and user interface setup and hold of 2.0/0.0 typical: Maximum window size = 1.6 ns + (2 x 500 ps) + 0.4ns = 3.0 ns Maximum setup time = 2.0 ns + 0.8 ns = 2.8 ns Maximum hold time = 0.0 ns + 0.2 ns = 0.2ns Channel-to-channel skew (typical) + (2 x sample uncertainty) Example: for P6417 or P6418 Probe = 1 ns + (2 x 500 ps) = 2 ns For the TLA7Nx/Px/Qx logic analyzer modules, each channel of the setup and hold window can be moved from +8.5 ns (Ts) to -7.0 ns (Ts) in 0.5 ns steps (setup time). Hold time follows the setup time by the setup and hold window size. For the TLA7Lx and TLAMx logic analyzer modules, the user interface restricts the setup and hold window range to groups rather than individual channels. 200 MHz in full speed mode (5 ns minimum between active clock edges) 100 MHz in half speed mode (10 ns minimum between active clock edges) Channels multiplex as follows: A3(7:0) to A2(7:0) to A1(7:0) to A0(7:0) to D3(7:0) D2(7:0) D1(7:0) D0(7:0)

Setup and hold window size (data and qualiers) (Typical) Setup and hold window range

Maximum synchronous clock rate 4 Demux clocking Demux Channels TLA7N3, TLA7N4, TLA7P4, TLA7Q4, TLA7L3, TLA7L4, TLA7M3, TLA7M4

TLA7N1, TLA7N2, TLA7P2, TLA7Q2, TLA7L1, TLA7L2, TLA7M1, TLA7M2

Channels multiplex as follows: A3(7:0) to A2(7:0) to A1(7:0) to A0(7:0) to C3(7:0) C2(7:0) D1(7:0) TLA7N2, TLA7P2, TLA7Q2, TLA7L2, TLA7M2 only D0(7:0) TLA7N2, TLA7P2, TLA7Q2, TLA7L2, TLA7M2 only

Time between DeMux clock edges 4 (Typical) Time between DeMux store clock edges 4 (Typical) Data Rate (Typical) TLA7N1, TLA7N2, TLA7P2, TLA7Q2, TLA7N3, TLA7N4, TLA7P4, TLA7Q4,

5 ns minimum between DeMux clock edges in full-speed mode 10 ns minimum between DeMux clock edges in half-speed mode 10 ns minimum between DeMux master clock edges in full-speed mode 20 ns minimum between DeMux master clock edges in half-speed mode 400 MHz (200 MHz option required) half channel. (Requires channels to be multiplexed.) These multiplexed channels double the memory depth.

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TLA7Lx/Mx/Nx/Px/Qx Module Specications

Table 72: LA module clocking (cont.)

Demux clocking Clocking state machine Pipeline delays For the TLA7Nx/Px/Qx logic analyzer modules, each channel can be programmed with a pipeline delay of 0 through 3 active clock edges. For the TLA7Lx and TLAMx logic analyzer modules, the user interface restricts the programming to groups rather than individual channels.

1 2 3 4

It is possible to use storage control and only store data when it has changed (transitional storage). Applies to asynchronous sampling only. Setup and hold window specication applies to synchronous sampling only. Any or all of the clock channels may be enabled. For an enabled clock channel, the rising edge, falling edge, or both edges can be selected as the active clock edges. The clock channels are stored. Full and half speed modes are controlled by PowerFlex options and upgrade kits.

Table 73: LA module trigger system

Characteristic Triggering Resources Word/Range recognizers 16 word recognizers. The word recognizers can be combined to form full width, double bounded, range recognizers. The following selections are available: 16 word recognizers 13 word recognizers 10 word recognizers 7 word recognizers 4 word recognizers Range recognizer channel order 0 range recognizers 1 range recognizer 2 range recognizers 3 range recognizers 4 range recognizers Description

From most-signicant probe group to least-signicant probe group: C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3 CK2 CK1 CK0 Missing channels for modules with fewer than 136 channels are omitted. When merged, the range recognition extends across all the modules; the master module contains the most-signicant groups. The master module is to the left (lower-numbered slot) of a merged pair. The master module is in the center when three modules are merged. Slave module 1 is located to the right of the master module, and slave module 2 is located to the left of the master module. Each channel group can be enabled to detect a glitch 2.0 ns (single channel with a P6417, P6418, or P6434 probe) Each channel can be enabled to detect a setup and hold violation. The range is from 8 ns before the clock edge to 8 ns after the clock edge. The range can be selected in 0.5 ns increments. For the TLA7Lx and TLAMx logic analyzer modules, the user interface restricts the setup and hold violation detector to groups rather than individual channels. The setup and hold violation of each window can be individually programmed. Each channel group can be enabled or disabled to detect a transition between the current valid data sample and the previous valid data sample.

Glitch detector 1 2 Minimum detectable glitch pulse width (Typical) Setup and hold violation detector 1 3

Transition detector 1 4

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TLA7Lx/Mx/Nx/Px/Qx Module Specications

Table 73: LA module trigger system (cont.)

Characteristic Counter/Timers Description 2 counter/timers, 51 bits wide, can be clocked up to 250 MHz. Maximum count is 251. Maximum time is 9.007 X 106 seconds or 104 days. Counters and timers can be set, reset, or tested and have zero reset latency. A backplane input signal A backplane input signal A backplane input signal that causes the main acquisition and the MagniVu acquisition to trigger if they are not already triggered 16 maximum (excluding counter/timers) Word recognizers are traded off one-by-one as Signal In 1, Signal In 2, glitch detection, setup and hold detection, or transition detection resources are added. 16 Same rate as valid data samples received, 250 MHz maximum Triggers the main acquisition memory Trigger position is programmable to any data sample (4 ns boundaries) Either of the two counter/timers used as counters can be increased. Either of the two counter/timers used as timers can be started or stopped. Either of the two counter/timers can be reset. When a counter/timer is used as a timer and is reset, the timer continues in the started or stopped state that it was in prior to the reset. A signal sent to the backplane to be used by other modules A trigger out signal sent to the backplane to trigger other modules Storage is allowed only when a specic condition is met. This condition can use any of the trigger machine resources except for the counter/timers. Storage commands dened in the current trigger state will override the global storage control. Global storage can be used to start the acquisition with storage initially turned on (default) or turned off. Storage can be turned on or off; only the current sample can be stored. The event storage control overrides any global storage commands. When enabled, 31 samples are stored before and after the valid sample. Block storage is disallowed when glitch storage or setup and hold violation is enabled. The acquisition memory can be enabled to store glitch violation information with each data sample when asynchronous sampling is used. The probe data storage size is reduced by one half (the other half holds the violation information). The fastest asynchronous sampling rate is reduced to 10 ns.

Signal In 1 Signal In 2 Trigger In Active trigger resources

Trigger States Trigger State sequence rate Trigger Machine Actions Main acquisition trigger Main trigger position Increment counter Start/Stop timer Reset counter/timer

Signal out Trigger out Storage Control Global storage

By event Block storage Glitch violation storage

1 2 3

Each use of a glitch detector, setup and hold violation detector, or transition detector requires a trade-off of one word recognizer resource. Any glitch is subject to pulse width variation of up to the channel-to-channel skew specication + 0.5 ns. For TLA7N1, TLA7N2, TLA7N3, TLA7N4, TLA7P2, TLA7P4, TLA7Q2, and TLA7Q4 Logic Analyzer modules, any setup value is subject to variation of up to 1.8 ns; any hold value is subject to variation of up to 1.2 ns. For TLA7L1, TLA7L2, TLA7L3, TLA7L4, TLA7M1, TLA7M2, TLA7M3, and TLA7M4 Logic Analyzer modules, any setup value is subject to variation of up to 1.6 ns; any hold value is subject to variation of up to 1.4 ns.

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TLA7Lx/Mx/Nx/Px/Qx Module Specications

This mode can be used to create transitional storage selections where all channels are enabled.

Table 74: LA module MagniVu feature

Characteristic MagniVu memory depth MagniVu sampling period Description 2016 samples per channel Data is asynchronously sampled and stored every 500 ps in a separate high resolution memory.

Table 75: LA module data handling

Characteristic Nonvolatile memory retention time (Typical) Description Battery is integral to the NVRAM. Battery life is > 10 years.

Table 76: LA module input parameters with probes

Characteristic Threshold Accuracy Threshold range and step size Threshold channel selection Description 100 mV Settable from +5 V to -2 V in 50 mV steps 16 threshold groups assigned to channels. P6417 and P6418 probes have two threshold settings, one for the clock/qualier channel and one for the data channels. P6434 probes have four threshold settings, one for each of the clock/qualier channels and two for the data channels (one per 16 data channels). 1.6 ns maximum (When merged, add 0.5 ns for the slave module.) 1.0 ns typical (When merged, add 0.3 ns for the slave module.) Asynchronous Sample period Probe input resistance (Typical) Probe input capacitance: P6417, P6434 (Typical) Probe input capacitance: P6418 (Typical) Minimum slew rate (Typical) Maximum operating signal 20 k 2 pF 1.4 pF data channels 2 pF CLK/Qual channels 0.2 V/ns 6.5 Vp-p -3.5 V absolute input voltage minimum 6.5 V absolute input voltage maximum P6417, P6418 P6434 250 mV or 25% of signal swing minimum required beyond threshold, whichever is greater 300 mV or 25% of signal swing minimum required beyond threshold, whichever is greater 4 V maximum beyond threshold 15 V Synchronous 500 ps

Channel-to-channel skew Channel-to-channel skew (Typical) Sample uncertainty

Probe overdrive

Maximum nondestructive input signal to probe

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TLA7Lx/Mx/Nx/Px/Qx Module Specications

Table 76: LA module input parameters with probes (cont.)

Characteristic Minimum input pulse width signal (single channel) (Typical) Delay time from probe tip to input probe connector (Typical) Description 2 ns 7.33 ns

Table 77: LA module mechanical

Characteristic Slot width Weight (Typical) Overall dimensions Height Width Depth P6417 length P6418 length P6434 length Description Requires 2 mainframe slots 5 lbs 10 oz. (2.55 kg) for TLA7N4 and TLA7P4 8 lbs (3.63 kg) for TLA7N4 and TLA7P4 packaged for domestic shipping 262 mm (10.32 in) 61 mm (2.39 in) 373 mm (14.7 in) 1.8 m (6 ft) 1.93 m (6 ft 4 in) 1.6 m (5 ft 2 in) 1.4 ECL keying is implemented

Probe cables

Mainframe interlock

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TLA7PG2 Module Specications

TLA7PG2 Module Specications

The following tables list the specications for the pattern generator module. For information on the individual pattern generator probes, refer to TLA7PG2 Pattern Generator Probe Instruction Manual. Table 78: PG module electrical specication, operational mode
Characteristic Operational mode Normal Step Output pattern Maximum Data Output Rate Output level: 5 V Load: 1 M + 1 pF Series termination resistor: 75 W Maximum Clock Output Frequency Output level: 5 V Load: 1 M + 1 pF Series termination resistor: 75 Maximum Operating Frequency 134 MB/s in Full Channel Mode 268 MB/s in Half Channel Mode Pattern data output is synchronized by the internal/external clock input Pattern data output is synchronized by the software command Description

134 MHz in Full Channel Mode 134 MHz in Half Channel Mode

The maximum operating frequency of the module is a function of the output level, output pattern and the load condition, including the series termination resistor in the probe. Operating conditions exceeding this frequency may result in damage to the probe. 40 to 262,140 (218 - 4) in Full Channel Mode (standard) 80 to 524,280 (219 - 8) in Half Channel Mode (standard) 40 to 1,048,572 (220 - 4) in Full Channel Mode (option 1M or PowerFlex upgrade) 80 to 2,097,144 (221 - 8) in Half Channel Mode (option1M or PowerFlex upgrade)

Pattern length

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TLA7PG2 Module Specications

Table 78: PG module electrical specication, operational mode (cont.)

Characteristic Number of channels Description 64 channels in Full Channel Mode 32 channels in Half Channel Mode The pattern memory for the following data channel will be shared with strobe control/internal inhibit control Probe D data output channel D0:0 D0:1 D0:2 D0:3 D0:4 D0:5 D0:6 D0:7 Sequences Number of blocks Number of subsequences Subsequences Repeat count Maximum 4,000 Maximum 4,000 Maximum 50 Maximum 256 steps 1 to 65,536 or innite Control STRB0 STRB1 STRB2 STRB3 Inhibit probe A Inhibit probe B Inhibit probe C Inhibit probe D

Table 79: PG module clocking

Characteristic Internal clock Clock Period Period Resolution Frequency Accuracy External clock input Clock Rate Polarity Threshold Input Impedance Sensitivity Range Resolution DC to 134 MHz in Full Channel Mode DC to 267 MHz in Half Channel Mode Normal or Invert -2.56 V to +2.54 V 20 mV 1 k terminated to GND 500 mVp-p 2.0000000 s to 7.462865 ns in Full Channel Mode 1.0000000 s to 3.7313432 ns in Half Channel Mode 8 digits 100 ppm Description

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TLA7PG2 Module Specications

Table 80: PG module event processing

Characteristic Event Action Number of Event Inputs Number of Event Denitions Event Mode Event Filter for Advance for Jump Description Advance, Jump and Inhibit 8 External Event Inputs (2 per each probe) 8 (A maximum of 256 event input patterns can be ORd to dene an event) Edge or Level Edge or Level None or 50 ns

Table 81: PG module inter-module interactions

Characteristic Signal Input Description Input from backplane Selectable from Signal 1, 2, 3, and 4 Used to dene the Event Output to backplane Selectable from Signal 1, 2, 3, and 4 Specied as High or Low in each Sequence line

Signal Output

Table 82: PG module merged PG modules

Characteristic Number of modules that can be merged together External Event Input for merged module Description Five For Jump and Advance, only the External Event Input of the leftmost module is used. For Inhibit, each module uses its own External Event Input as a source

Table 83: PG module mechanical

Characteristic Slot width Weight(Typical) Overall dimensions (excluding connectors) Mainframe interlock Height Width Depth Description Requires two mainframe slots 2.5 kg (5 lbs. 4 oz.) 10.32 in (262 mm) 2.39 in (61 mm) 14.7 in (373 mm) 1.4 ECI keying is implemented

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DSO Module Specications

DSO Module Specications

The following tables list the specications for the DSO Module. Table 84: DSO module signal acquisition system
Characteristic Accuracy, DC gain Accuracy, internal offset 1 Description 1.5% for full scale ranges from 20 mV to 100 V 2.0% for full scale ranges <19.9 mV Full scale range setting 10 mV - 1 V 1.01 V - 10 V 10.1 V - 100 V Analog bandwidth, DC-50 coupled Full scale range setting 10.1 V - 100 V 100 mV - 10 V 50 mV - 99.5 mV 20 mV - 49.8 mV 10 mV - 19.9 mV Bandwidth, analog, selections Calculated rise time (Typical) 3 Typical full-bandwidth rise times are shown in the chart to the right Offset accuracy [(0.2% x offset) + 1.5 mV + (6% x full scale range)] [(0.25% x offset) + 15 mV + (6% x full scale range)] [(0.25% x offset) + 150 mV + (6% x full scale range)] Bandwidth 2 DC - 500 MHz (TLA7E1 and TLA7E2) DC - 500 MHz (TLA7D1 and TLA7D2) DC - 1 GHz (TLA7E1 and TLA7E2) DC - 500 MHz (TLA7D1 and TLA7D2) DC - 750 MHz (TLA7E1 and TLA7E2) DC - 500 MHz (TLA7D1 and TLA7D2) DC - 600 MHz (TLA7E1 and TLA7E2) DC - 500 MHz (TLA7D1 and TLA7D2) DC - 500 MHz (TLA7E1 and TLA7E2) DC - 500 MHz (TLA7D1 and TLA7D2) TLA7E1 and TLA7E2 900 ps 450 ps 600 ps 750 ps 900 ps TLA7D1 and TLA7D2 900 ps 900 ps 900 ps 900 ps 900 ps

20 MHz, 250 MHz, and FULL on each channel Full scale range setting 10.1 V - 100 V 100 mV - 10 V 50 mV - 99.5 mV 20 mV - 49.8 mV 10 mV - 19.9 mV

Crosstalk (channel isolation)

300:1 at 100 MHz and 100:1 at the rated bandwidth for the channels sensitivity (Full Scale Range) setting, for any two channels having equal sensitivity settings 8

Digitized bits

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DSO Module Specications

Table 84: DSO module signal acquisition system (cont.)

Characteristic Effective bits, real time sampling (Typical) Description Input frequency TLA7E1 and TLA7E2 5 GS/s (each channel) 6.2 bits 6.1 bits 6.0 bits 5.7 bits 5.2 bits TLA7D1 and TLA7D2 2.5 GS/s (each channel) 6.2 bits 6.1 bits 6.0 bits 5.7 bits N/A

10.2 MHz 98 MHz 245 MHz 490 MHz 990 MHz Frequency limit, upper, 20 MHz bandwidth limited (Typical) Frequency limit, upper, 250 MHz bandwidth limited (Typical) Input channels 20 MHz 250 MHz Product TLA7E2 TLA7D2 TLA7E1 TLA7D1 Input coupling Input impedance, DC-1 M coupled Input impedance selections Input resistance, DC-50 coupled Input VSWR, DC-50 W coupled Input voltage, maximum, DC-1 M , AC-1 M, or GND coupled Input voltage, maximum, DC-50 or AC-50 Coupled Lower frequency limit, AC coupled (Typical) Random noise DC, AC, or GND 4

Channels 4 4 2 2

1 M 0.5% in parallel with 10 pF 3 pF 1 M or 50 50 1% 1.3:1 from DC - 500 MHz, 1.5:1 from 500 MHz - 1 GHz 300 VRMS but no greater than 420 V peak, Installation category II, derated at 20 dB/decade above 1 MHz 5 VRMS, with peaks 25 V 10 Hz when AC-1 M Coupled; 200 kHz when AC-50 Coupled 5 Bandwidth selection Full 250 MHz 20 MHz RMS noise (350 V + 0.5% of the full scale Setting) (165 V + 0.5% of the full scale Setting) (75 V + 0.5% of the full scale Setting) Offset range 1 V 10 V 100 V

Range, internal offset

Full scale range setting 10 mV - 1 V 1.01 V - 10 V 10.1 V - 100 V

Range, sensitivity (full scale range), all channels

10 mV to 100 V 6

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DSO Module Specications

Table 84: DSO module signal acquisition system (cont.)

Characteristic Step response settling errors (Typical) 7 8 Description Full scale range setting 10 mV - 1 V 1.01 V - 10 V 10.1 V - 100 V
1 2 3 4 5 6 7 8

Step response

Maximum setting error (%) at 20 ns 100 ns 0.2% 0.5% 0.5% 20 ms 0.1% 0.2% 0.2% 0.5% 1.0% 1.0%

2 V 20 V 200 V

Net offset is the nominal voltage level at the digitizing oscilloscope input that corresponds to the center of the A/D Converter dynamic range. Offset accuracy is the accuracy of this voltage level. The limits given are for the ambient temperature range of 0 C to +30 C. Reduce the upper bandwidth frequencies by 5 MHz for each C above +30 C. The bandwidth must be set to FULL. Rise time (rounded to the nearest 50 ps) is calculated from the bandwidth when Full Bandwidth is selected. It is dened by the following formula: Rise Time (ns) = 450 BW (MHz) GND input coupling disconnects the input connector from the attenuator and connects a ground reference to the input of the attenuator. The AC Coupled Lower Frequency Limits are reduced by a factor of 10 when 10X passive probes are used. The sensitivity ranges from 10 mV to 100 V full scale in a 1-2-5 sequence of coarse settings. Between coarse settings, you can adjust the sensitivity with a resolution equal to 1% of the more sensitive coarse setting. For example, between the 500 mV and 1 V ranges, the sensitivity can be set with 5 mV resolution. The Full Bandwidth settling errors are typically less than the percentages from the table. The maximum absolute difference between the value at the end of a specied time interval after the mid-level crossing of the step, and the value one second after the mid-level crossing of the step, expressed as a percentage of the step amplitude. See IEEE std. 1057, Section 4.8.1, Settling Time Parameters.

Table 85: DSO module timebase system

Characteristic Range, Extended Real-time Sampling Rate Range, Real-time Sampling Rate Description 5 S/s to 10 MS/s in a 1-2.5-5 sequence Products TLA7E1 and TLA7E2 TLA7D1 and TLA7D2 Record Length Long Term Sample Rate Limits 25 MS/s to 5 GS/s on all channels simultaneously in a 1-2.5-5 sequence 25 MS/s to 2.5 GS/s on all channels simultaneously in a 1-2.5-5 sequence

512, 1024, 2048, 4096, 8192, and 15000 100 ppm over any 1 ms interval

Table 86: DSO module trigger system

Characteristic Accuracy (Time) for Pulse Glitch or Pulse Width Triggering Accuracy (DC) for Edge Trigger Level, DC Coupled Range (Time) for Pulse Glitch and Pulse Width Triggering Range, Trigger Level Description Time Range 2 ns to 500 ns 520 ns to 1 s Accuracy (20% of setting + 0.5 ns) (104.5 ns + 0.01% of setting)

( ( 2% | Setting) | ) + 0.03 of Full Scale Range + Offset Accuracy) for signals having rise and fall times 20 ns 2 ns to 1 s Source Any Channel Range 100% of full scale range

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DSO Module Specications

Table 86: DSO module trigger system (cont.)

Characteristic Range, Trigger Point Position Resolution, Trigger Level Resolution, Trigger Position Sensitivities, Pulse-Type Runt Trigger (Typical) Sensitivities, Pulse-Type Trigger Width and Glitch (Typical) Sensitivity, Edge-Type Trigger, DC Coupled Description Minimum: 0% Maximum: 100% 0.2% of full scale for any Channel source One Sample Interval at any Sample Rate 10% of full scale, from DC to 500 MHz, for vertical settings >100 mV full scale and 10 V full scale at the BNC input 10% of full scale for vertical settings >100 mV full scale and 10 V full scale at the BNC input The minimum signal levels required for stable edge triggering of an acquisition when the trigger source is DC-coupled Products TLA7E1 and TLA7E2 Trigger Source Any Channel Sensitivity 2.5% of Full Scale Range from DC to 50 MHz increasing to 10% of Full Scale Range at 1 GHz 2.5% of Full Scale Range from DC to 50 MHz increasing to 10% of Full Scale Range at 500 MHz

TLA7D1 and TLA7D2

Any Channel

Sensitivity, Edge-Type Trigger, Not DC Coupled (Typical)

Trigger Coupling AC

Typical Signal Level for Stable Triggering Same as the DC-coupled limits for frequencies above 60 Hz; attenuates signals below 60 Hz One and one-half times the DC-coupled limits from DC to 30 kHz; attenuates signals above 30 kHz One and one-half times the DC-coupled limits for frequencies above 80 kHz; attenuates signals below 80 kHz Three times the DC-coupled limits Minimum Pulse Width 1 ns 1 ns Minimum Rearm Width 2 ns + 5% of Glitch Width Setting 2 ns + 5% of Width Upper Limit Setting

High Frequency Reject

Low Frequency Reject

Noise Reject Time, Minimum Pulse or Rearm, and Minimum Transition Time, for Pulse-Type Triggering (Typical) Pulse Class Glitch Width Trigger Position Error, Edge Triggering (Typical)
1

For vertical settings >100 mV and 10 V at the BNC input

Acquisition Mode Sample

Trigger Position Error 1 (1 Sample Interval + 1 ns)

The trigger position errors are typically less than the values given here. These values are for triggering signals having a slew rate at the trigger point of 5% of full scale/ns.

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DSO Module Specications

Table 87: DSO module front-panel connectors

Characteristic Probe Compensator, Output Voltage The Probe Compensator output voltage in peak-to-peak Volts Description 0.5 V (base-top) 1% into a 50 load

Table 88: DSO module mechanical

Characteristic Slot width Weight (Typical) Description Requires 2 mainframe slots Products TLA7D1 and TLA7E1 TLA7D2 and TLA7E2 Shipping Weight (Typical) Products TLA7D1 and TLA7E1 TLA7D2 and TLA7E2 Overall Dimensions Height: 262.05 mm (10.32 in) Width: 60.66 mm (2.39 in) Depth: 373.38 mm (14.70 in) Weight 2.44 kg (5.38 lbs) 2.55 kg (5.63 lbs) Weight 6.35 kg (14 lbs) 7.71 kg (17 lbs)

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External Oscilloscope (iView) Characteristics

External Oscilloscope (iView) Characteristics

The following table lists the characteristics for iView (Integrated View) and for the Tektronix logic analyzer mainframe when connected to an external oscilloscope. For detailed information on the individual specications of the external oscilloscope, refer to the documentation that accompanies the oscilloscope. Table 89: External oscilloscope (Integrated View or iView) characteristics
Characteristic Supported Tektronix logic analyzer instruments Description TLA5000 and TLA5000B series TLA715, TLA721 TLA7012, TLA7016 V5.6 or greater RAM 1 512 MB TDS1000 and TDS2000 Series 2 3 TDS1000B and TDS2000B Series 3 4 TDS3000, TDS3000B, and TDS3000C Series (TDS3GM or TDS3GV GPIB/RS-232 communication module required) DPO3000 Series 4 DPO4000 and MSO4000 Series 4 5 TDS5000 and TDS5000B Series TDS6000, TDS6000B, and TDS6000C Series DPO7000 and DPO7000B Series DPO70000 and DSA70000 Series TDS7000 and TDS7000B Series CSA7000 and CSA7000B Series TDS654C, TDS684C, TDS694C TDS754C, TDS784C, TDS724D, TDS754D, TDS784D, TDS794D One per Tektronix logic analyzer mainframe 6.56 ft (2 m)

TLA application software version Minimum recommended TLA controller Supported external oscilloscopes as of May, 2008 (For the latest list of supported external oscilloscopes, visit our Web site at www.tektronix.com/la.)

Maximum number of external oscilloscopes iView cable length 6

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External Oscilloscope (iView) Characteristics

Table 89: External oscilloscope (Integrated View or iView) characteristics (cont.)

Characteristic Time correlation uncertainty 7 (Typical at system trigger) Description 3 ns Logic analyzer triggers external oscilloscope (2 ns + logic analyzer sample period + external oscilloscope sample period) External oscilloscope triggers logic analyzer (4 ns + logic analyzer sample period + external oscilloscope sample period)

5 ns

1 2 3 4 5 6

If RAM is less than 256 MB, the record length of the external oscilloscope may be limited to 1 M. A GPIB extender is needed to connect the iView cable to the oscilloscope. One end of a standard GPIB cable can be used. If you encounter possible alignment problems with the logic analyzer and oscilloscope waveform edges, refer to Aligning Logic Analyzer and Oscilloscope Waveform Edges. (See page 77, Aligning Logic Analyzer and Oscilloscope Waveform Edges.) A GPIB to USB adapter (TEK-USB-488) is required to connect the iView cable to the oscilloscope. There is a known timing offset between triggers when a TLA logic analyzer is triggered by the oscilloscope. Tektronix is correcting this problem. When used with a TLA7016 mainframe and an external PC (such as TLA7PC1), the instruments must be physically located close together so that the iView cable can span both instruments. Removing the sleeving from the iView cable assembly increases the spacing distance available between the external PC and the TLA7016 mainframe. Includes sampling uncertainty, typical jitter, slot-to-slot skew, and probe-to-probe variations to provide a typical number for the measurement.

Aligning Logic Analyzer and Oscilloscope Waveform Edges

The rst time that you take an acquisition after changing the horizontal scale setting on TDS1000B, TDS2000B, TDS1000 or TDS2000 series oscilloscopes, the logic analyzer and oscilloscope waveform edges may not be aligned within the listed specication. You can realign the waveform positions in the waveform window that contains the oscilloscope data (Menu bar > Data > Time Alignment). Make sure that the external oscilloscope is the data source and then adjust the time offset to align the waveforms. Use the following approximate offsets for various horizontal scale settings. (See Table 90.) Table 90: TDS1000B, TDS2000B, TDS1000, and TDS2000 Series oscilloscope waveform edge alignment
Horizontal scale 100 ns 250 ns 500 ns 1 s 2.5 s 5 s 10 s 25 s Time offset 5 ns 11 ns 18 ns 12 ns 50 ns 120 ns 250 ns 650 ns

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Performance Verication Procedures

Performance Verication Procedures

This chapter contains procedures for functional verication, certication, and performance verication procedures for the TLA7000 series logic analyzer mainframes. Refer to the individual service manuals for performance verication procedures for other Tektronix Logic Analyzer products. Generally, you should perform these procedures once per year or following repairs that affect certication.

Summary Verication
Functional verication procedures verify the basic functionality of the instrument inputs, outputs, and basic instrument actions. These procedures include power-on diagnostics, extended diagnostics, and manual check procedures. These procedures can be used for incoming inspection purposes. Certication procedures certify the accuracy of an instrument and provide a traceability path to national standards. Certication data is recorded on calibration data reports provided with this manual. The calibration data reports are intended to be copied and used for calibration/certication procedures. After completing the performance verication procedures or the certication procedures, you can ll out a calibration data report to keep on le with your instrument. Performance verication procedures conrm that a product meets or exceeds the performance requirements for the published specications documented in the Specications chapter of this manual.

Test Equipment
These procedures use external, traceable signal sources to directly test characteristics that are designated as checked in the Specications chapter of this manual. Always warm up the equipment for 30 minutes before beginning the procedures. Table 91: Test equipment
Item number and description 1. Benchtop Mainframe Minimum requirements TLA7016 Benchtop Mainframe with a logic analyzer module installed and an external computer with TLA application software installed. TLA7012 Portable Mainframe with a logic analyzer module installed Example -

2.

Portable Mainframe

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Performance Verication Procedures

Table 91: Test equipment (cont.)

Item number and description 3. 4. Frequency counter Cable, precision 50 coaxial Minimum requirements Frequency accuracy: <0.0025% Frequency range: 1 kHz to 100 MHz 50 , 36 in, male-to-male BNC connectors Example Hewlett Packard 5314A Tektronix part number 012-0482-XX

Functional Verication
The following table lists functional verication procedures for the benchtop and portable mainframes. If necessary, refer to the TLA7000 Series Logic Analyzer Installation Manual for installation instructions. Table 92: Functional verication procedures
Instrument Benchtop and portable mainframe Procedure Power-on and fan operation Power-up diagnostics Extended diagnostics TLA Mainframe diagnostics CheckIt Utilities diagnostics

Power-on and Fan Operation

Complete the following steps to check the power-on and fan operation of the logic analyzer: You will need a mainframe with an LA module installed in each mainframe. 1. Power on the instrument and observe that the On/Standby switch illuminates. 2. Check that the fans spin without undue noise. 3. If everything is properly connected and operational, you should see the modules in the System window of the logic analyzer application. 4. If there are no failures indicated in the System window, the power-on diagnostics pass when you power on the mainframe(s).

Extended Diagnostics

Do the following steps to run the extended diagnostics: NOTE. Running the extended diagnostics will invalidate any acquired data. If you want to save any of the acquired data, do so before running the extended diagnostics.

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Performance Verication Procedures

You will need a mainframe with an LA module installed in each mainframe.

Prerequisites

Warm-up time: 30 minutes

Perform the following tests to complete the functional verication procedure: NOTE. Installing a module in the mainframe provides a means of verifying connectivity and communication between the module and the mainframe. Try using a different module and repeat the tests to isolate the problem to the mainframe or to the module. 1. If you have not already done so, power on the instrument and start the logic analyzer application if it did not start by itself. 2. Go to the System menu and select Calibration and Diagnostics. 3. Verify that all power-on diagnostics pass. 4. Click the Extended Diagnostics tab. 5. Select All Modules, All Tests, and then click the Run button on the property sheet. All tests that displayed an "Unknown" status will change to a Pass or Fail status depending on the outcome of the tests. 6. Scroll through the tests and verify that all tests pass.

TLA Mainframe Diagnostics

The TLA Mainframe Diagnostics are a comprehensive software test that checks the functionality of the mainframes. To run these diagnostics, do the following steps: 1. Quit the logic analyzer application. 2. Click the Windows Start button. 3. Select All Programs Tektronix Logic Analyzer TLA Mainframe Diagnostics. 4. Select your instrument from the Connection dialog box (in most cases this will be the [Local] selection). 5. Run the mainframe diagnostics.

CheckIt Utilities

CheckIt Utilities is a comprehensive software application used to check and verify the operation of the PC hardware in the portable mainframe. To run the software, you must have either a keyboard, mouse, or other pointing device.

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Performance Verication Procedures

NOTE. To check the DVD drive, you must have a test CD installed before starting the CheckIt Utilities. The test CD needs to contain a le with a size between 5 MB and 15 MB. To run CheckIt Utilities, follow these instructions: 1. Quit the logic analyzer application. 2. Click the Windows Start button. 3. Select All Programs CheckIt Utilities. 4. Run the tests. If necessary, refer to the CheckIt Utilities online help for information on running the software and the individual tests.

Certication
The system clock of the controller is checked for accuracy. The instrument is certiable if this parameter meets specications. Complete the performance verication procedures and record the certiable parameters in a copy of the Calibration Data Report at the end of this chapter.

Performance Verication Procedures

This section contains procedures to verify that the TLA7012 Portable Mainframe and the TLA7016 Benchtop Mainframe perform as warranted. Verify instrument performance whenever the accuracy or function of your instrument is in question.

Tests Performed

Do the following tests to verify the performance of the TLA7012 Portable Mainframe and the TLA7016 Benchtop Mainframe. (See Table 93.) You will need test equipment to complete the performance verication procedures. (See Table 91.) If you substitute equipment, always choose instruments that meet or exceed the minimum requirements specied. Table 93: Performance verication procedures
Parameter System clock (CLK
1

Procedure 10) 1 10 MHz system clock test

Certiable parameter

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Performance Verication Procedures

Checking the 10 MHz System Clock (CLK10)

The following procedure checks the accuracy of the 10 MHz system clock:

Equipment required Prerequisites

Frequency counter (item 3) Precision BNC cable (item 4) Warm-up time: 30 minutes

1. Verify that all of the prerequisites above are met for the procedure. 2. Connect the frequency counter to the External Signal Out BNC connector on the instrument. 3. Go to the System window and select System Conguration from the System menu. 4. In the System Conguration dialog box, select 10 MHz Clock from the list of routable signals in the External Signal Out selection box and click OK. 5. Verify that the output frequency at the External Signal Out connector is 10 MHz 1 kHz. Record the measurement on a copy of the calibration data report and disconnect the frequency counter. 6. In the System Conguration dialog box, reset the External Signal Out signal to None.

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Calibration Data Report

Calibration Data Report

Photocopy this table and use it to record the performance test results for your instrument.

TLA7012 and TLA7016 Test Record

Instrument model number: Serial number: Certicate number: Verication performed by: Verication date:

System Clock Test Data

Characteristic Clock frequency Specication 10 MHz Tolerance 1 kHz (9.9990 MHz-10.0010 MHz) Incoming data Outgoing data

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