PAGE PDF

1
2
3
4
6
7
8
9
10
11
13*
14
16
17
18
21*
22
23
24
25*
26
27
28*
29
30
31
32
33
34
35
36
37*
38
40
44
45
46

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

CIRCUIT

BLOCK

TABLE OF CONTENTS
SYSTEM BLOCK DIAGRAM
POWER BLOCK DIAGRAM
REVISION HISTORY
FUNC TEST
POWER CONNECTOR / POWER ALIAS
SIGNAL ALIAS
2.5V VREG
1.2V VREG
3.3V/5V PWRON SWITCHING
SMU
CPU LOGIC ANALYZER CONNECTOR
CPU FAN 2 AND SYSTEM FAN CONTROL
CPU FAN 1 CONTROL
I2C CONNECTIONS
INDICATOR LED
U3LITE CORE
SHASTA CORE
U3LITE MISC
SHASTA SERIAL
PULSAR POWER
PULSAR CLOCKS
U3LITE APPLE PI
NEO APPLE PI
CPU STRAPS
NEO POWER & BYPASS
CPU BYPASS
CPU VREG
CPU VREG
CPU VREG OUTPUT CAPS
CPU DIODE CONDITIONER
U3LITE MEMORY
SERIES TERMINATION
DIMMS
PARALLEL TERMINATION
PARALLEL TERMINATION
VTT VREG

.
w
w
w

p
la

TOP

PAGE PDF
48
49
50
51
52
53
54
55
56
57
58
59
60*
62*
64
74*
75*
76
77*
80*
83
84*
87
88*
90
91*
92
94
95*
96*
97*
98*
99*

38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

m
e
h
c

s
p
to
PROCESSOR

MEMORY

* PAGES WHERE MASTER PAGE IS IN A DIFFERENT SCHEMATIC

m
o

CIRCUIT

c
.
s
it c

U3LITE AGP
GPU AGP
GPU VREG
EXTERNAL TMDS TRANSMITTER
GPU FRAME BUFFER
FRAME BUFFER TERMINATION
GRAPHICS DDR SDRAM A
GRAPHICS DDR SDRAM B
GPU STRAPS
GPU DAC & CLOCKS
GPU DVI & STRAPS
EXT VGA & TMDS
U3LITE HYPERTRANSPORT
SHASTA HYPERTRANSPORT
HYPERTRANSPORT LA CONNECTORS
SHASTA PCI
BOOT ROM
AIRPORT EXTREME
USB2 PCI
SHASTA DISK
DISK CONNECTORS
SHASTA ETHERNET
ETHERNET PHY & CONNECTORS
SHASTA FIREWIRE
FIREWIRE A PHY & CONNECTORS
USB HOST INTERFACE
USB DEVICE INTERFACE
MODEM CONNECTOR
AUDIO CODEC, LINE IN, MIC IN
HEADPHONE / LINE OUT
SPEAKER AMP
AUDIO CONNECTORS
AUDIO POWER SUPPLIES

BLOCK

GRAPHICS

HT

PCI
DISK
ETHERNET
FIREWIRE
USB
MODEM

AUDIO

U2900

CPU
NEO 10S

U1300

U1301

PAGE 29

SMU

J5900, J5901
J5902, J5903
17",20" INVERTER

PAGE 13

TMDS
EXT VGA

64-BIT
FRAME BUFFER
2.6V/540MHZ

MAIN MEMORY

PAGE 28

U4900

U3

GPU

AGP

32-BIT
8X AGP
0.8V/533MHZ

NV18B/NV34

PAGE 54

U3LITE

PAGE
48

CORE

4X = 1.5V
I/O = 1.5V

PAGE 37

J4000
J4001

APPLE PI

FRAME
BUFFER A

64-BIT
FRAME BUFFER
2.6V/540MHZ

POWER

MISC

HYPERTRANSPORT

PAGE 24

PAGE 60

PAGE 26

TERM

PAGE 38

PAGES 44&45

333MHZ SUPPORTED

I2C
PAGE 18

PAGE 27

HT
DEBUG
PAGE 64

U7500

AIRPORT
EXTREME
CONNECTOR

SATA/150

PCI

U2300

SATA2

SATA DEV
CONNECTOR

SATA

PAGE 80

J8302

SHASTA

1.2V/1.5GHZ
PAGE 83

EDUCATION: HARD DRIVE

GOOD,BETTER,BEST: OPTICAL

UATA
CONNECTOR

UATA/133

UATA

PAGE 80

J8301

p
la

3.3V/133MHZ

PAGE 23

PAGE 84

U8700

10/100 ETHERNET

BCM5221
PAGE 87

4 Diff pairs
J8700

PAGE 88

BLUETOOTH
CONNECTOR

USB

PAGE 92

PAGE 91

uPD720101
PCI
PAGE 77

PAGE 94

U9500

S/PDIF

AUDIO CODEC

OPTICAL OUT
J9803

COMBO OUT
CONNECTOR
LINE OUT
AMP

PAGE 95

PAGE 98
LINE OUT

PAGE 97
J9801

PAGE 90
0
1

SPEAKER
AMP

LINE IN
AMP

PAGE 97

J9000, J9001

J9800

SPEAKER

CONNECTOR
PAGE 98

PAGE 97

2 Diff pairs

PAGE 90

PAGE 94

J9240

CTL-LESS /
SOFT MODEM
CONNECTOR

SCCB
I2S2

FIREWIRE A
802A

PAGE 87

CONNECTOR

J9401

PCM3052

FIREWIRE A
CONNECTORS

To Shasta
SCCA

32-bit PCI (5V-3.3V/33MHz)

U9000

ETHERNET
CONNECTOR

MICRODASH MODEM

USB 2.0

PAGE 76

I2S

PAGE 25
SCCA
I2S0
I2S1

1394 OHCI (3.3V/98MHz)

8-bit TX/RX

GMII (3.3V/125MHz)
8-bit TX & 8-bit RX

.
w
w
w
8

PAGE 91

ETHERNET FIREWIRE

PAGE 83

NCs

CORE

PAGE 74

PAGE 62

PAGE 83

GPIO/PCI64

SATA/150

PAGE 92

J9400

PAGE 25

HYPERTRANSPORT

SATA1

SATA
CONNECTOR

1.2V/1.5GHZ

FOR DEVELOPMENT ONLY

s
p
to
PAGE 75

JXXXX

USB
CONNECTORS

U7700

J7600

BOOTROM

EDUCATION: NOT USED

GOOD,BETTER,BEST: HARD DRIVE

m
e
h
c

J6400
J6401
J6402

J9210/J9220/J9230

CONTROL = 2.5V

PAGE 55

c
.
s
it c

PARALLEL

TERM

8-BIT
HYPERTRANSPORT
1.2V/400MHZ

FRAME
BUFFER B

CLOCKS

DIMMS

SERIES

PAGE 40

U5500, U5501

PULSAR

64/128-BIT
MAIN MEMORY
2.6V/400MHZ

PAGE 22

PAGE 49

U2600

m
o

32-BIT
APPLE PI
ELASTIC INTERFACE
1.2V/900MHZ

PAGE 59

U5400, U5401

RTC
PAGE 13

J9802

LINE IN

MIC

CONNECTOR

CONNECTOR

PAGE 98

PAGE 98

1
SMU

SYS_POWERUP_L

POWER SEQUENCE PIN

SYS_POWERUP_L

J700
PAGE 7

POWER CONNECTOR

PP24V_RUN

PP12V_RUN

FW CONN
20" LCD INVERTER

PP5V_RUN

20" PANEL POWER

20" LCD INVERTER

PP5V_ALL

m
o

10

TURN_ON_SHASTA_CORE_L

SMU_PWRSEQ_P1_0

13

10

TURN_ON_PP1V2_L

SMU_PWRSEQ_P1_1

13

SMU_PWRSEQ_P9_5

13

(PWR_GOOD_SB_CORE)

SMU_PWRSEQ_P9_6

13

(PWR_GOOD_PP2V5)

SMU_PWRSEQ_P1_2

13

(TURN_ON_VTT)

PP3V3_RUN

HDD & OPTICAL

c
.
s
it c

PCI BUS
AUDIO CODEC

5V

PP3V3_ALL
LINEAR
PAGE 11

3.3V

PP5V_RUN_CPU

PP5V_RUN_AUDIO
LINEAR

CPU CORE
SWITCHER

PAGE 99

5V

PAGE 33
HP/LINEOUT AMP

CPU_AVDD_EN

31

LINEAR

PAGE 31

SC2643VX*1
SC1211*4

0.8~1.2V

m
e
h
c

6 7 30 31 36

PP2V5_RUN_CPU_AVDD
ALIAS

PP5V_PWRON
FET SWITCH
PAGE 11

CPU AVDD

2.5V

PP3V3_PWRON
FET SWITCH

PAGE 11

USB CONN
UDASH MODEM

5V

GPUL

FW PHY
SMU

ENET PHY
USB2 HOST
MODEM & BT

3.3V

PP2V5_PWRON
SWITCHER

4.5V

s
p
to
IRU3037CS

PAGE 9

PAGE 99

SHASTA HT
DDR DIMM

2.62V

AUDIO CODEC

PP2V5_RUN
FET SWITCH
PAGE 9

RAM TERM
GRAPHIC FB

p
la

.
w
w
w

PP1V25_RAM_VTT
LINEAR
IN

PAGE 46

1.25V

RAM VTT

46

SWITCHER

PAGE 10

1.5V

R331
10K

5%
1/16W
MF
2 402

PWR_GOOD_SB_CORE

IN

IRU3037ACS

1.2V

SHASTA CORE

NV18B/NV34

3
11
23 10 6

R330
1

IN

5%
1/16W
MF
402

PP2V5_PWRON

IN

PP1V2_PWRON
FET SWITCH IN

PP1V2_RUN
FET SWITCH

PAGE 10

14

GND
12

C330

0.01UF

20%
16V
2 CERM
402

IN

PAGE 10
PWRON_SD
PWRON_DISK_SB

HT BUS
API BUS

PP1V5_PWRON
LINEAR

PP5V_ALL
PP3V3_ALL

PAGE 50

1.5V

SOI

U1100

100K 2 COMPARE_SB_CORE

IRU3037CS

U3LITE CORE

LM339A

RAIL_CTL_NEG

V+

PP1V2_PWRON_SB_VCORE

U3LITE CORE
SWITCHER

PAGE 22

IRU3037CS

1.6/1.4V

PP4V5_RUN_AUDIO
LINEAR

PP3V3_ALL

PP1V2_SHASTA_CORE

GPU CORE
SWITCHER

PAGE 50

R342

PULSAR CORE

150K

PS_2V_REF

PP1V5_RUN
POWER SW

R341
10K

LM339A

V+

R340
1

PAGE 50
AGP BUS

5%
1/16W
MF
402

SOI

U1100

100K 2

COMPARE_PP2V5

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

PWR_GOOD_PP2V5

GND
12

C340

0.01UF

20%
16V
2 CERM
402

R343
100K

5%
1/16W
MF
2 402

TURN_ON_VTT

8
DATE

DESCRIPTION

10/08/03

PROTO RELEASE (REV 09)

10/13/03

CHANGED ALL 4 NB AVDDS TO PP1V5_PWRON_NB_AVDD RAIL

TERMINATION FOR VSP CLOCK NOW TRACKS PP1V2_HT RAIL
TERMINATION FOR NB CLOCK NOW TRACKS PP1V2_EI_NB RAIL
TERMINATION FOR CPU CLOCK NOW TRACKS PP1V2_EI_CPU RAIL
NO STUFFED R1303 BECAUSE WHITE LED IS ACTIVE HIGH
ADDED 5 PULLDOWNS FOR CPU VID SIGNALS
UNCONNECTED THERMAL PAD FOR U9600 HEADPHONE AMP
CHECKIN 09001

D
10/14/03

ADDED 4 SMT NUTS

U3600 PIN 6 TO PP5V_RUN
CHECKIN 09002

10/15/03

SWAPPED EI_CPU_TO_NB_AD17 WITH EI_CPU_TO_NB_AD24 ON J1400

BOM CHANGES FOR R2910, R5727, R9139, R9810
MAIN PROTO RELEASE (REV 10)

11/03/03

REPINNED J9240 BLUETOOTH CONNECTOR

MANY MIN_NECK_WIDTH UPDATES
DC-DC UPDATES ON PAGES 9,10,22,33,34,50
NEW CONNECTORS FOR MODEM AND PATA
ADDED GAP FILLER
CHANGED PART NUMBER OF NV18B
MOVED SERIES TERM FOR PULSAR CLOCKS TO LOGIC ANALYZER PAGE
ADDED NET_SPACING_TYPE=PROC_DIFF TO TDIODE_POS, TDIODE_NEG, KPVDD2, AND KPGND2
CHANGED PULSAR 2.2UF CAPS TO 10%
MASTER PAGE SYNC
CHECKIN 10001

11/04/03

NEW AIRPORT CONNECTOR

ADDED LEDS FOR 5V ALL RAIL AND PANEL POWER
CHANGED DS870X TO LED870X TO FOLLOW CONVENTION
REPLACED POWER CONNECTOR
MASTER PAGE SYNC
RELEASE REV 11

11/10/03

J8301 PATA CONNECTOR ROTATED 180 DEGREES

MIN_LINE_WIDTH AND MIN_NECK_WIDTH UPDATES THROUGHOUT
ADDED EMI-SPRING AND TIED TO GND_CHASSIS_MODEM
UPDATED CRYSTAL CONSTRAINTS
FIREWIRE NET NAME CHANGES TO MATCH NAMING CONVENTION
CHANGED Q1001 TO NTD60N02R
CHANGED PULSAR SERIES TERM R2707, R2719, R2701, R2761, R2779 TO 0 OHM
CHANGED ZH700 AND ZH701 TO HOL-315R138
CHANGED 20" INVERTER TO 518-0141
CHANGED U3LITE P/N TO V1.1
MASTER PAGE SYNC
CHECKIN 11001

11/11/03

PLL-LOCK LED CHANGED TO GREEN

SMU PART# UPDATED
DC/DC NET NAME FIXES ON PAGES 9,10,22
ADDED SERIAL SIGNALS TO AIRPORT CARD FOR NEW MARTY CARD
PULSAR SERIES TERM - CHANGED R2705,R2711,R2702 TO 0 OHM.
CHANGED SHASTA P/N TO V1.1
UPDATED POWER SEQUENCING TO MATCH SMU PINOUT 1.4
NO_TEST UPDATES
ADDED 6 OUTPUT CAPS (124-0322) TO CPU VCORE VREG
MASTER PAGE SYNC
CHECKIN 11002 - EVT DESIGN REVIEW

11/13/03

CHANGED J8303 TO 5 PIN CONNECTOR

CHANGED MICRODASH MODEM HEIGHT AND CHANGED TO DEVELOPMENT BOM OPTION
PIN SWAPPED L5908 FOR ROUTING
STUFFED TMDS INDUCTORS AND NOSTUFFED 0 OHM RESISTORS
CHANGED MODEM STANDOFFS TO 862-0035 AND ADDED ELECTRICAL CONNECTIONS
ADDED TWO MORE SMT NUTS FOR CPU HEATSINK
CHANGED LED700,701,702,5900,8301,8700,8701,8702 AND D3001 TO 378S0045
MASTER PAGE SYNC
CHECKIN 12002

11/17/03

NO_TEST, FUNC_TEST UPDATES

CHECKIN 12003

11/18/03

CHASSIS MODEM NO LONGER TIES TO REST OF CHASSIS

ADDED CAPS TO GROUND FOR CPU HEATSINK SMT NUTS
CHANGED CRYSTAL FILTERING FOR PULSAR
MOVED RAM_CKE SIGNALS TO 62 OHM VTT PARALLEL TERM WITH 4.7K PULL-DOWN
ADDED POWER SEQUENCING FOR VTT VREG
MASTER PAGE SYNC
CHECKIN 12004

CHANGED R2700 TO 22OHM AND NOSTUFFED

CPU VID SET TO 1.475V
J1400 CHANGED TO NOSTUFF
CHANGED HALF OF DIMM AND VTT DECOUPLING TO 1UF
EVT1 RELEASE (REV 13)

p
la

m
o

m
e
h
c

.
w
w
w

11/15/03

11/20/03

CHANGED CRYSTAL Y5700 TO 197S0026

LED3002, LED3600, AND LED800 CHANGED TO D3002, D3610, AND D810 P/N 378S0042
CPU POWER SUPPLY FETS - VISHAY USED ON SAMSUNG BOMS AND ON SEMI ON HYNIX BOMS
CHANGED INPUT CAPS TO 124-0323
INPUT AND OUTPUT CERM CAPS MARKED AS CRITICAL
NEW LARGER CAP FOR VTT VREG. C4609 CHANGED TO 128S0022. C4608 NOSTUFFED
BOMOPTIONS AND SCHEMATIC CLEANUP TO AGP (BUSY, STOP, TYPEDET, GCDET)
CHANGED 20" INVERTER DECOUPLING TO TWO 1UF 1210 CAPS
ADDED MORE POWER AND GROUND SHORTS FOR AUDIO
ADDED NET_SPACING_TYPE=PROC_DIFF TO DIFF PAIRS THAT DIDNT HAVE IT
MASTER PAGE SYNC
RELEASE REV 12

CHANGED PCI_CLK33M_SB_EXT NET NAME ON PAGE 27 FOR REUSE. ALIAS ADDED ON PAGE 8
ADDED ECSET FOR PLS_EXTCLK NET. DROPPED PROP DELAY FROM OTHER CRYSTALS
ALIASED PP5V_AUDIO TO PP5V_RUN RAIL
ADDED CIRCUIT SO 5V RAIL TO 17" INVERTER COMES UP AFTER 12V
R2742 CHANGED TO 806 OHM
MASTER PAGE SYNC
CHECKIN 12001

STUFFING CHANGES FOR ETHERNET RESET

CHANGED XW3302 TO LAYER 6 SHORT
POWER BUTTON CONNECTOR SYMBOL UPDATED
UPDATED CRITICAL LIST
CHANGE Y5700 TO 4 PIN CRYSTAL
CHECKIN 12005

R2770 -> 20 OHM

11/14/03

11/17/03

11/19/03

c
.
s
it c

s
p
to

1
PP12V_RUN

I3
I4
I5
I6
I7
I8
I9
I10

I295
I296
I297
I298
I300
I299
I302

I307
I311
I314
I315
I316
I317

I320
I319
I322
I323
I321
I336
I337
I338
I340
I339
I342
I343

I341
I344
I345
I346
I347
I348
I350
I349
I352
I354
I355
I356
I357
I358
I360
I359
I362
I363
I361
I364
I365
I372
I373
I371
I374
I375

I376
I377
I378
I380
I379
I382
I383
I381
I384
I385
I386
I388
I387
I390
I389
I391
I393
I392
I395
I394
I396
I398
I397
I399
I401
I400

I403
I402
I404
I405
I406
I408
I407
I426
I429
I428
I431
I430
I432

NO_TEST=TRUE
NO_TEST=YES
NO_TEST=YES
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=YES
NO_TEST=TRUE
NO_TEST=YES
NO_TEST=YES
NO_TEST=TRUE
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=YES
NO_TEST=YES
NO_TEST=TRUE
NO_TEST=YES
NO_TEST=TRUE
NO_TEST=YES
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

TP_BUF_RST
TP_DFPCLK
TP_DFPCLK_L
TP_DFPD0
TP_DFPD1
TP_DFPD2
TP_DFPD3
TP_DFPD5
TP_DFPD6
TP_EXT_TMDS_CKM
TP_EXT_TMDS_CKP
TP_EXT_TMDS_D0M
TP_EXT_TMDS_D0P
TP_EXT_TMDS_D1M
TP_EXT_TMDS_D1P
TP_EXT_TMDS_D2M
TP_EXT_TMDS_D2P
TP_FBBCS1_L
TP_GPU_INTB_L
TP_GPU_THERMA
TP_GPU_THERMC
TP_IFP1VREF
TP_NVAGP_TDO
TP_TMDS_TXD3M
TP_TMDS_TXD3P
TP_TMDS_TXD7M
TP_TMDS_TXD7P
TP_VIPHCLK
TP_FRWRLPS
TP_AGP_MB_AGP8X_DET_L
TP_ATTENTION
TP_ENET_CLK125M_GTX
TP_ENET_TXD<7>
TP_ENET_TXD<4>
TP_ENET_TXD<5>
TP_FW_CLK98M_LCLK
TP_AFN
TP_PSRO1
TP_PSRO2
TP_PSYNCOUT
TP_USB2_PWREN<2>
TP_USB2_PWREN<3>
TP_USB2_PWREN<4>
TP_PROC_TRIGGER_OUT
TP_NEC_AMC
TP_NEC_NANDTEST
TP_NEC_NTEST1
TP_NEC_SMC
TP_NEC_SMI_L
TP_NEC_SRCLK
TP_NEC_SRDATA
TP_NEC_SRMOD
TP_NEC_TEB
TP_NEC_TEST
TP_PLS_CLK_66M_0
TP_PLS_CLK_66M_1
TP_PLS_REF_CML
TP_PLS_TEST1
TP_PLS_TEST2
TP_PLS_TEST3
TP_SB_FSTEST
TP_SB_PLLTEST
TP_VREF_CG
TP_SB_NC_P7
TP_SB_NC_P8
TP_SB_NC_R3
TP_SB_NC_R4
TP_SB_NC_R5
TP_SB_NC_R6
TP_SB_NC_R7
TP_SB_NC_R8
TP_SB_NC_T1
TP_SB_NC_T2
TP_SB_NC_T3
TP_SB_NC_T4
TP_SB_NC_T5
TP_SB_NC_T6
TP_SB_NC_T7
TP_SB_NC_T8
TP_SB_NC_U1
TP_SB_NC_U2
TP_SB_NC_U3
TP_SB_NC_U4
TP_SB_NC_U5
TP_SB_NC_U6
TP_SB_NC_V1
TP_SB_NC_V2
TP_SB_NC_V3
TP_SB_NC_V4
TP_SB_NC_W1
TP_SB_NC_W3
TP_SB_NC_Y1
TP_SB_NC_Y3
TP_SATA_CLK25M
TP_ENET_TCK
TP_USB2_PWREN<0>
TP_USB2_PWREN<1>
TP_DUMMY_A
TP_DUMMY_B
TP_RAM_CKE_R<2>

57

I434

58

I433

58

I436

58

I435

58

I437

58

I439

58

I438

58

I440

58

I441

58

I442

58

I444

58

I443

58

I445

58

I446

58

I781

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

TP_RAM_CKE_R<3>
37
TP_RAM_CKE_R<6>
37
TP_RAM_CKE_R<7>
37
TP_RAM_CS_L_R<10> 37
TP_RAM_CS_L_R<11> 37
TP_RAM_CS_L_R<2> 37
TP_RAM_CS_L_R<3> 37
TP_RAM_MUXEN0
37
TP_RAM_MUXEN4
37
TP_NB_PM_SLEEP0
24
TP_J4000_SJRESET_L 40
TP_J4001_SJRESET_L 40
TP_CMP_SPARE
36
TP_ENET_TXD<6>
87
U2100_UNUSED
21

90

IN

90

IN

90

IN

90

IN

90

IN

90

IN

90

IN

90

IN

90

IN

90

IN

90

IN

77 76 75 74

IN

77 76 74

IN

IN

58

76 74

IN

58

76 74

IN

76 25

IN

52

77 76 75 74 51 49

IN

49

77 76 74

IN

58

77 76 74

IN

58

77 76 74

IN

58

77 76 74

IN

49

77 76 74

IN

77 76 74

IN

58

76

IN

58

76 75 74

IN
IN

58

76 75 74

58

76 75 74

IN

57

76 75

IN

58

76

IN

FW_VP_PORT1
FW_TPO1P
FW_TPO1N
FW_TPI1P
FW_TPI1N
FW_VP_PORT2
FW_TPO2P
FW_TPO2N
FW_TPI2P
FW_TPI2N
FW_VGND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

PCI_AD<31..0>
PCI_CBE_L<3..0>
PCI_CLK33M_AIRPORT
PCI_SLOTA_REQ_L
PCI_SLOTA_GNT_L
PCI_SLOTA_INT_L
PCI_RESET_L
PCI_FRAME_L
PCI_TRDY_L
PCI_IRDY_L
PCI_STOP_L
PCI_DEVSEL_L
PCI_PAR
PCI_SLOTA_IDSEL
ROM_CS_L
ROM_OE_L
ROM_WE_L
ROM_ONBOARD_CS_L
AIRPORT_CLKRUN_L_PD

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

48
29

92

IN

87

92

IN

92

87
87

92

90

92

29

92

29

92

29

92

29

92

92

92

92

92

92
14 29

94 76 25

77

94 25

77

94 25

s
p
to
94 25

77

94 76 25

77

94 25

77

94 25

77

94 18

77

94 18

77

94

77

94

77

94 25

27

94 25

27
27

94

27
27
27
25

p
la

25
48
91
91
91
91
91

.
w
w
w

91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
27
87

IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59 7

IN

59

IN

59

IN

59

IN

59 57 56

IN

59 57 56

IN

59

IN

59

IN

59 58

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

33 8

IN

36

IN

36

IN

92

36

IN

24

36

IN

24

36 33

IN

37

36 33

IN

92

I2S1_DEV_TO_SB_DTI
I2S1_SYNC
I2S1_BITCLK
I2S1_MCLK
I2S1_SB_TO_DEV_DTO
I2S1_RESET_L
MODEM_RING2SYS_L
I2C_UDASH_SDA
I2C_UDASH_SCL
USB_UDASH_N
USB_UDASH_P
UDASH_SDOWN
UDASH_RESET_L
UDASH_I2C_A1_PU

2
2
2
2
2
2
2

TEST
TEST
TEST
TEST
TEST
TEST
TEST

POINTS
POINTS
POINTS
POINTS
POINTS
POINTS
POINTS

IN
IN
IN

5 TEST POINTS
5 TEST POINTS
5 TEST POINTS
5 TEST POINTS

m
o

5 TEST POINTS

IN

PP5V_DISK
PP12V_DISK
GND

12 TEST POINTS

IN

83 7

IN

83 7

IN
IN

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FILT_ANALOG_RED
FILT_ANALOG_GRN
FILT_ANALOG_BLU
ANALOG_HSYNC_L
ANALOG_VSYNC_L
VGA_IIC_CLK
VGA_IIC_DAT
MON_DETECT
DDC_VCC_5

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

PP24V_INV
GND_20_INV
INV_20_LCD_PWM_
INV_20_CUR_HI_F
PP12V_INV
GND_17_INV
PP5V_AGP_RL
INV_17_LCD_PWM_F
LAMP_STS_F
INV_17_CUR_HI_F

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

CPU_VID_R<5..0>
KPVDD2_FMAX
KPGND2_FMAX
TDIODE_POS_FMAX
TDIODE_NEG_FMAX
CORE_ISNS_M
CORE_ISNS_P

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

18 11

IN

27 18 11

IN
IN

23 10 3

IN
IN

36 31 30 7 3

IN

22 7

IN

36 35 34 33 32 31 29 7

IN

34 33

IN

33

IN

33

IN

13 8 7

IN

13 7

IN

IN

IN

13 8

IN

33 13 11 10 7

IN

50 46 27 11 10 9 8

IN

13 8

IN

13

IN

IN

22

IN

59 57

IN

59 57

IN

59 57

IN

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

PPVCC_TMDS
PP3V3_DDC
TD0M
TD0P
TD1M
TD1P
TD2M
TD2P
TCKM
TCKP
TMDS_DDC_DAT
TMDS_DDC_CLK
GND_CHASSIS_TMDS

11

PP12V_RUN
PP5V_ALL
PP5V_RUN
PP3V3_RUN
PP24V_RUN

5 TEST POINTS

c
.
s
it c

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

USB2_PORT1_N_F
USB2_PORT1_P_F
USB2_PORT2_N_F
USB2_PORT2_P_F
USB2_PORT3_N_F
USB2_PORT3_P_F
PP5V_USB2_PORT1_F
PP5V_USB2_PORT2_F
PP5V_USB2_PORT3_F

IN

11

FUNC_TEST=TRUE
FUNC_TEST=TRUE

USB_BT_N
USB_BT_P

m
e
h
c

87

IN
11 7

10 TEST POINTS

IN
98 25

IN

75

IN

83 80

IN

83 80

IN

83 80

IN

83 80

IN

83 80

IN

83

IN

83 80

IN

83 806 6
83 80
83

IN

83 80

IN

83

IN

IN

83

IN

83

IN

36 31

IN

76

IN

76

IN

PP2V5_RUN
PP1V5_RUN
PP5V_PWRON
PP3V3_PWRON
PP1V2_PWRON
PP1V2_PWRON_SB_VCORE
PP3V3_ALL_SMU
PP5V_RUN_CPU
PPVCORE_NB
PPVCORE_CPU
PP12V_CPU
VCORE_SENSE_GND
VCORE_SENSE_VOUT
SMU_MANUAL_RESET_L
SYS_POWER_BUTTON_L
POWER_BUTTON_L
RESET_BUTTON_L
SMU_RESET_L
SYS_POWERUP_L
SYS_SLEEP
SYS_POWERFAIL_L
EXT_POWER_BUTTON_L
U900_FEEDBACK
U2200_FEEDBACK
ANALOG_RED
ANALOG_GRN
ANALOG_BLU
AUDIO_LI_DETECT_L
AUDIO_LO_DET_L
ROM_WP_L

2 TEST POINTS
2 TEST POINTS

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

PP5V_RUN

PP5V_ALL

PP24V_RUN

PP3V3_RUN

FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE

PP2V5_RUN PP5V_PWRON
PP1V5_RUN

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

UATA_DD<15..0>
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_RESET_L
UATA_DSTROBE_R
UATA_HSTROBE
UATA_STOP
UATA_DMARQ_R
UATA_DMACK_L
UATA_INTRQ_R
UATA_IOCS16_PU
UATA_CSEL_PD

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

TDIODE_NEG
TP_AIRPORT_PME_L
TP_AIRPORT_RF_DISABLE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

PP1V2_PWRON

PP3V3_PWRON

7
PP12V_RUN

PP5V_RUN

PP5V_ALL

PP3V3_RUN

PP12V_RUN

PP5V_RUN

ONLY ON IN RUN

J700

VOLTAGE=24V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

43215-0012
F-RT-TH

D
POWER_GOOD

12

13

14

15

16

17

18

19

20

10

21

11

22

PP24V_FW

ALIAS

PP24V_GRAPHICS

ALIAS

PWRON RAILS

ALL RAILS

ON IN RUN AND SLEEP

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)

90

PP1V5_PWRON

59

VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE
PP1V5_PWRON_NB_AVDD
ALIAS
VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=8MIL

PP3V3_PATA

83

ALIAS

PP2V5_PWRON
ALIAS

PP5V_PATA

83

ALIAS

PP5V_DISK

6 83

PP3V3_ALL

74LCX125

33 13 11 10 6

SYS_POWERUP_L

20%
10V
2 CERM
402

PP12V_RUN

SYS_POWERUP_L_BUF
VOLTAGE=12V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

PP2V5_RUN_RAM

44 45 46

ALIAS

PP2V5_RUN_CPU

31

ALIAS

PP3V3_PWRON

R710
330

2 ITS_PLUGGED_IN

5%
1/16W
MF
603

R701
330

ITS_ALIVE

5%
1/16W
MF
603

LED702

VOLTAGE=12V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

DEVELOPMENT

GREEN
2.0X1.25

GREEN
2.0X1.25
2

5%
1/16W
MF
603

LED700

LED701

FERR-EMI-100-OHM
SYS_POWER_BUTTON_L

2 SYS_PWR_BTN_FILT

PP3V3_RUN

SW703

SM

PWR-BUTT
ST-SM
1

C703

1
3

20%
10V
2 CERM
402

L701

FERR-EMI-100-OHM
2

GND_SYS_PWR_BTN_FILT

p
la

PP1V5_RUN

R714
10K

5%
1/16W
MF
2 402

R713
1

R712
13

SYS_RESET_BUTTON_L

1K

5%
1/16W
MF
402

1K

5%
1/16W
MF
402

.
w
w
w
POWER_BUTTON_L
RESET_BUTTON_L

DEVELOPMENT

DEVELOPMENT

SW701

SW702

SPST

SPST

SM
1

SM
2

C705
0.1UF

20%
10V
2 CERM
402

13 8 6

POWER

SMU_MANUAL_RESET_L

SW700
SPST
SM
1

C704
0.1UF

20%
10V
2 CERM
402

35 31 30 29 18

ALIAS

98

48 49 50 51 52 56 57 58 59

33

22 6

5%
1/10W
FF
805 2

SMU RESET

XW703
SM
99 97

GND_AUDIO_SPKRAMP

80

25

CHASSIS GND
ZH700
315R138
98

94

PP5V_PWRON_CPU

36

ALIAS

PP3V3_PWRON_CPU

36

_PP3V3_PWRON_MODEM 94
_PP3V3_PWRON_USB 91
PP3V3_PWRON_ENET 87
_PP3V3_PWRON_BT 92
_PP3V3_PWRON_UDASH 94
_PP5V_PWRON_USB 92

ALIAS

XW707
SM

59
92

GND_CHASSIS_AUDIO_EXTERNAL
MIN_NECK_WIDTH=15MIL
MAKE_BASE=TRUE
VOLTAGE=0
MIN_LINE_WIDTH=25MIL

GND_CHASSIS_VGA
GND_CHASSIS_USB
GND_CHASSIS_FIREWIRE

ALIAS
1

ZH701

EMI700
EMI-SPRING
SC57

315R138
59 6

GND_CHASSIS_TMDS
MIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

ZH702
160R138
87

ALIAS

PP2V5_PWRON_RAM

ALIAS

PP2V5_HT

40

98
60 64
21

GND_CHASSIS_RJ45
MIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

SH700

GND_CHASSIS_AUDIO_INTERNAL
MAKE_BASE=TRUE
GND_CHASSIS_LED

ALIAS

SHLD-IO-CONN
Q45-TH
3

ZH703

6.00MM-PTH
59

83

59

48 49

GND_CHASSIS_17_INCH_INVERTER
MIN_NECK_WIDTH=20MIL
MIN_LINE_WIDTH=20MIL
VOLTAGE=0
GND_CHASSIS_20_INCH_INVERTER
MIN_NECK_WIDTH=20MIL
MIN_LINE_WIDTH=20MIL
VOLTAGE=0

ZH704

225R125
1

26

RTC BATTERY
2

ALWAYS ON (TRICKLE)

5%
1W
FF
2512

PP1V2_RUN

CRITICAL

DS700
SM

VOLTAGE=1.2V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

NOSTUFF

XW702
SM

25 74 75 76 77

R7081

R706
0

5%
1/10W
FF
2 805

5%
1/10W
FF
805 2

13

ALIAS

PP1V2_HT

24 60

ALIAS

PP1V2_PULSAR

26

PPVCORE_CPU

R7051

IN

GND RAILS

GND_AUDIO

R707
1

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP5V_ALL

11 6

PP1V5_PWRON

NOSTUFF

PPVCORE_NB

J702

R702

BB10209-A5

1K 2 PP3V3_ALL_BATT
2
1PP3V3_ALL_BATT_SAFETY 1
1
2
_PP3V3_ALL_RTC
VOLTAGE=3.3V
VOLTAGE=3.3V
VOLTAGE=3.3V
5%
MIN_LINE_WIDTH=25MIL
MIN_LINE_WIDTH=25MIL
MIN_LINE_WIDTH=25MIL
1/16W
MIN_NECK_WIDTH=10MILMBR0530 MIN_NECK_WIDTH=10MIL
MIN_NECK_WIDTH=10MIL TH
MF
402

NOSTUFF
1

R709
0

5%
1/10W
FF
2 805

R703
1

PP1V2_EI_CPU

PP1V2_EI_NB

5%
1/10W
FF
805

VOLTAGE=1.2V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

VOLTAGE=1.2V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

18 28

R704
0

5%
1/10W
FF
805

8 13

62

74

PPVCORE_PULSAR

ALIAS

_PP3V3_ALL_SMU

PP5V_ALL

62

90

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

95 97 98 99

PP1V5_AGP

ALIAS

ALIAS

90

XW706
SM

77

PP3V3_DISK

ALIAS

99

PP2V5_PWRON

PP3V3_AUDIO
PP3V3_RUN_CPU

_PPVIO_PCI_USB2

23

_PP5V_PWRON_UDASH

PP3V3_FW

ALIAS

3 6 30 31 36

PP3V3_AGP

_PP3V3_PCI

PP5V_AUDIO

ALIAS

VOLTAGE=1.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

36 35 34 33 32 31 29 6

RESET

97

s
p
to
ALIAS

_PPPCI32_PWRON_SB

MAKE_BASE=TRUE

PP3V3_ALL

SYS_POWER_BUTTON_L

ALIAS

PP3V3_ALL
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

23 25 74 88

23

_PP1V2_PWRON_DISK_SB
_PP1V2_PWRON_SB

49 50 59

PP5V_RUN_CPU

_PP3V3_SB_PCI

SM

13 7 6

PP5V_AGP

ALIAS

ALIAS

PP3V3_RUN

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=8MIL
MAKE_BASE=TRUE

SILKSCREEN:POWER

0.1UF

PP12V_AUDIO_SPKRAMP

ALIAS

_PP2V5_PWRON_SB

_PP2V5_PWRON_HT
_PP1V2_PWRON_HT

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

L700

99

PP5V_PWRON

XW705
SM

PP5V_RUN

SILKSCREEN:RUN

m
e
h
c

PP12V_AUDIO_CODEC

23 25

_PPPCI64_PWRON_SB

MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=1.2V

6 83

PP1V2_PWRON

33

PP12V_DISK

13 7 6

50 59

XW701
SM

GREEN
2.0X1.25

SILKSCREEN:2

PP12V_AGP

XW704
SM

ITS_RUNNING
DEVELOPMENT

SILKSCREEN:1

26 37

XW700
SM

PP3V3_RUN

R700
330

PP2V5_RAM

PP12V_RUN_CPU

ALIAS
ALIAS

PP12V_RUN
PP5V_ALL

52 54 55

ALIAS

ALIAS

125
1 TSSOP

PP2V5_GPU

ALIAS

0.1UF

U700

14
2

MAKE_BASE=TRUE
VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C700

c
.
s
it c

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

PP2V5_RUN

26

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE
_PP3V3_PWRON_SB

MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

P/N 518-0137

PPVCORE_PWRON_PULSAR

11 7

28 37 48 60

PP3V3_PWRON

PP5V_RUN

PIN 13,19,11,22 ARE DIFFERENCE FROM ATX .

CRITICAL

m
o

PP3V3_RUN

VOLTAGE=0V
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=10MIL

11 7

RUN RAILS

PP24V_RUN

CRITICAL

PP24V_RUN

1
MISC PARTS

PCI CLOCKS

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

TP_NB_THMI
MAKE_BASE=TRUE
TP_THMO
MAKE_BASE=TRUE

NB_THMI
NB_THMO

ALIAS
ALIAS

PCI_CLK33M_USB2
MAKE_BASE=TRUE

24

PCI_CLK_GP0
_PCI_CLK33M_USB2
PCI_CLK_GP1

24

TP_PCI_CLK_GP1
MAKE_BASE=TRUE
PCI_CLK33M_AIRPORT
MAKE_BASE=TRUE

ALIAS

TABLE_11_HEAD

27

PART #

QTY

DEVICE

PACKAGE

DESCRIPTION

VALUE

VOLT.

WATT.

TOL.

REFERENCE DESIGNATOR(S)

BOM OPTION

337S2784

27

PROCESSOR CBGA-576-1MM IC,MPU,NEO,10S,REV2,1.8GHZ,70C

1.8GHZ

1.15V

45W

U2900

NEO_REV2_1_8GHZ

337S2785

27

PROCESSOR CBGA-576-1MM IC,MPU,NEO,10S,REV2,2.0GHZ,70C

2.0GHZ

1.15V

65W

U2900

NEO_REV2_2_0GHZ

76

337S2786

PROCESSOR CBGA-576-1MM IC,MPU,NEO,10S,REV3,1.8GHZ,70C

1.8GHZ

1.15V

45W

U2900

27

337S2787

PROCESSOR CBGA-576-1MM IC,MPU,NEO,10S,REV3,2.0GHZ,70C

2.0GHZ

1.15V

65W

U2900

PCI_CLK_P1

NEO_REV3_1_8GHZ

R870
4.7K

SMU_CHARGE_BATT 13
NO_TEST=TRUE
ALS0_OUT
13
24 13

ALS1_OUT

ALIAS
ALIAS

ALS_GAIN_BOOST

13

ALIAS

SMU_ADAPTER_ID

13

ALIAS

ACCEL_LOWPWR_L

13

ALIAS

SMU_PWRSEQ_P1_3

ALIAS

SMU_PWRSEQ_P1_4

ALIAS

SMU_SPARE_P10_0

ALIAS

ACCEL_INT_L

U700
14

74LCX125

125
10 TSSOP

SMU_WARM_RESET_L

13

14

74LCX125

125
4 TSSOP

SMU_SLEEP

13

11
7

m
e
h
c
DOWNLOAD
CONNECTOR

NOSTUFF

R819

CPU_VID<0>

13

CPU_VID<1>

13

13

10K

10K

10K

10K

10K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

13

6 33

CPU_VID_R<4>

6 33

CPU_VID_R<5>

6 33

R824

NOSTUFF
1

13

12

11

10

R832

F-ST-SM
14

BM12B-SRSS-TB

J803

NOSTUFF

6 33

NOSTUFF
1

R831

NOSTUFF
1

R830

NOSTUFF
1

R829

R827

10K

10K

10K

10K

20K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

p
la

.
w
w
w

NOSTUFF

D800
1N914

1K

NOSTUFF

R810

13 8 7 6

SMU_MANUAL_RESET_L

5%
1/16W
MF
402

5%
1/16W
MF
2 402

SOT23

SMU_RESET_L

NOSTUFF
1

C800
1UF

10%
2 6.3V
CERM
402

R8011
5%
1/16W
MF
402 2

6 13

27

LBL,SER #,INP DEV

LBL1

CLOCK_ERROR_L

R826

10

DEVELOPMENT
998-0269
1

R807
10K
5%

1/16W
MF
2 402

J802_2 2
J802_6

NOSTUFF
1

R805
0

5%
1/16W
MF
402 2

100

5%
1/16W
MF
402

U7500
BT700

875-1614

GAP FILLER

341T1395

PURCH ASSY, SMU BIG

CRITICAL 875-1752

GPU GAP PAD

CRITICAL 452-0678

CPU HEATSINK SCREW

SRW800,SRW801,SRW802,SRW803,SRW804,SRW805

CRITICAL 870-1177

CPU HEATSINK SPRING

SPR800,SPR801,SPR802,SPR803,SPR804,SPR805

CRITICAL 730-0291

CPU HEATSINK

TABLE_5_ITEM

GAP2900

13
13

(SMU_BOOT_EPM)
SMU_MANUAL_RESET_L
SMU_BOOT_TXD

TABLE_5_ITEM

PAD4900
TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

HS2900

NEED TO ADD THERMAL GREASE TO MLB BOM

ALTERNATE FOR SERIAL NUMBER LABEL

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:

825-2808

825-2029

COMMON

LBL1

BAR CODE LABEL

TABLE_ALT_ITEM

POWER_FAIL_L
CONNECTION

PP3V3_ALL_SMU_AVCC

PP3V3_ALL

NOSTUFF

13

R812

R818

10K

200

5%
1/16W
MF
2 402

1%
1/16W
MF
2 402

SYS_POWERFAIL_L

13

NOSTUFF

C801

20%
10V
CERM 2
805

NOSTUFF

R803
10K
5%

6 13

R813

R802

2.2UF

6 7 8 13

U1300

SMU ANALOG VREF

13

TABLE_5_ITEM

_PPVREF_SMU

SMU_BOOT_BUSY
SMU_BOOT_RXD

2 PPVREF_SMU_ADC_REF

POWER_GOOD

36

47

5%
1/16W
MF
402

5%
1/16W
MF
402

NOSTUFF
1

C802

0.47UF

1/16W
MF
2 402

20%
10V
2 CERM
603

GND_SMU_AVSS

13 33 36

R828
1

2 GND_SMU_AVSS_DAGND

5%
1/16W
MF
402

36

CPU HEATSINK SMT NUTS

SDF800

SDF801

SDF802

HSK-NUT-6.5MM HSK-NUT-6.5MM HSK-NUT-6.5MM

TH

HS_SDF800 1

TH

HS_SDF801

C880

0.01UF

TH

HS_SDF802

C881

0.01UF

20%
16V
2 CERM
402

C883
0.01UF

20%
16V
2 CERM
402

C882
0.01UF

20%
16V
2 CERM
402

20%
16V
2 CERM
402

SDF804

SDF805

TH

HS_SDF804

C884
0.01UF

20%
16V
2 CERM
402

TH

HS_SDF805

C885
0.01UF

20%
16V
2 CERM
402

R825
10K

5%
1/16W
MF

DEVELOPMENT

J800

2 402

U.FL-R_SMT

ERROR_LED

TABLE_5_ITEM

5%
1/16W
MF
2 402

SM

TABLE_5_ITEM

IC,FLASH,1MX8,3.3V,90NS

JTAG_SB_TRST_L

330

RED

SCH1

BAT,COIN,3V,220MAH,CR2032

c
.
s
it c

SHASTA JTAG
PULL DOWN

R800

D810

TABLE_5_ITEM

PCB,SCHEM,MLB

HS_SDF803 1

DEVELOPMENT

TH

DEVELOPMENT

051-6482

SDF803

25

4.7K

HSK-NUT-6.5MM HSK-NUT-6.5MM HSK-NUT-6.5MM

PP3V3_RUN

DEVELOPMENT

R815

5%
1/16W
MF
402 2

PULSAR ERROR_L LED

_PP3V3_ALL_SMU

NOSTUFF

R811

10K

NOTE:PULL UP CPU_VID<5>TO
2.2V FOR CPU VRM10.

s
p
to
10K

CPU_VID_R<3>

NOSTUFF

SMU_BOOT_CNVSS

R8061

5%
1/16W
MF
402

SMU_BOOT_SCLK
SMU_BOOT_CE

6 33

CPU_VID_R<2>

DEVELOPMENT

TH

13

CHEAPER SMU RESET

13 7

J802

ST-HDR-HI-TEMP

13

5%
1/16W
MF
402

PP3V3_ALL
DEVELOPMENT

6 33

R822

5%
1/16W
MF
402

CPU_VID<5>

10K

NOSTUFF

R823
CPU_VID<4>

R804

CPU_VID_R<1>

5%
1/16W
MF
402

NOSTUFF

13

R820

5%
1/16W
MF
402

CPU_VID<3>

R809

NOSTUFF

5%
1/16W
MF
402

R821
CPU_VID<2>

R808

CPU_VID_R<0>

NOSTUFF

13

125
13 TSSOP

PP3V3_RUN

R817

6 9 10 11 27 46 50

74LCX125

12

VID SET TO 1.475V TO ACHIEVE 1.45V AT PROCESSOR

SYS_SLEEP

U700

13

24 25 74 77 87

13

14

CPU VID<0:5>

SYS_WARM_RESET_L

U700
13

13

825-2029

5%
1/16W
MF
2 402

2.5V

ALIAS

TP_ACCEL_LOWPWR_L
MAKE_BASE=TRUE
TP_SMU_PWRSEQ_P1_3
MAKE_BASE=TRUE
TP_SMU_PWRSEQ_P1_4
MAKE_BASE=TRUE
TP_SMU_SPARE_P10_0
MAKE_BASE=TRUE
TP_ACCEL_INT_L
MAKE_BASE=TRUE

NOSTUFF

MLB1

SSOT-23

ALIAS

TP_ALS1_OUT
MAKE_BASE=TRUE
TP_ALS_GAIN_BOOST
MAKE_BASE=TRUE
TP_SMU_ADAPTER_ID
MAKE_BASE=TRUE

R816

PCB,FAB,MLB

2
3

TP_SMU_CHARGE_BATT
MAKE_BASE=TRUE
TP_ALS0_OUT
MAKE_BASE=TRUE

341T1366

27

SMU

R814

820-1540

CRITICAL 742-0048

NEO_REV3_2_0GHZ

VR801

ALIAS

VPP1

m
o

TABLE_11_HEAD

TABLE_11_HEAD

PCI_CLK_P4

ALIAS

PCI_CLK33M_SB_EXT
MAKE_BASE=TRUE

13

SPEC,VENDOR PACKAGING PROCEDURE

TABLE_5_ITEM

PCI_CLK_P3
_PCI_CLK33M_AIRPORT

PP2V5_PWRON

TABLE_11_HEAD

TABLE_11_HEAD

TP_PCI_CLK_P4
MAKE_BASE=TRUE
74 27

062-2082

TABLE_5_ITEM

77

THESE PINS HAVE INTERNAL PULLUPS

TP_JTAG_SB_TCK
JTAG_SB_TCK
ALIAS
MAKE_BASE=TRUE
TP_JTAG_SB_TDI
JTAG_SB_TDI
ALIAS
MAKE_BASE=TRUE
TP_JTAG_SB_TDO
JTAG_SB_TDO
MAKE_BASE=TRUE ALIAS
TP_JTAG_SB_TMS
JTAG_SB_TMS
ALIAS
MAKE_BASE=TRUE

F-ST-SM
3

25
25

24

NB_PMR_OBSV

25

25

518S0104

m
o

2.5V VOLTAGE REGULATOR

PP5V_PWRON
PP5V_PWRON

D900
2

R900

U900_VC_R

C904

20%
2 25V
CERM
805

VCC

VC

IRU3037CS
SOI
8

U900_COMP

HD

LD

U900_VC_D

U900_GATE_H

R902
1

Q901
1

Q901_GATE

5%
1/10W
FF
805

SS
U900_GATE_L

NTD70N03R

CASE369

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

Q902_DRAIN

U900_FEEDBACK

GND

27.4K

C915
0.1UF

20%
2 16V
CERM
603

R901_P2
1

C914
3900PF

C913
56PF

C906
220PF

5%
2 50V
CERM
402

5%
2 25V
CERM
402

p
la

.
w
w
w
8

C917
1UF

20%
2 10V
CERM
603

CRITICAL

L901

s
p
to

NOSTUFF

NTD70N03R

C905

0.022UF

10%
50V
2 CERM
603

CASE369

PEAK CURRENT OF TOTAL RAILS

12.68A WITH DIMM TERMINATION
9.24A WITHOUT DIMM TERMINATION

20%
2 6.3V
ELEC
8X11.5-TH

NOSTUFF

C907
3300PF

10%
50V
2 CERM
603

Q903
SO-8

8
3
2

7
6

1
1

R903

11K

1%
1/16W
MF
2 402

OMIT
1

C908

1800UF

NOSTUFF

C912

20%
25V
2 CERM
1206

PP2V5_RUN

IRF7410
VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

R904_P2

1UF

PP2V5_PWRON

TH

5%
1/8W
FF
2 1206

NOTE:
SET OUTPUT=2.62V FOR FRAMEBUFFER.
IRU3037CS VREF=1.25VDC
VOUT=VREF*(R903+R905)/R905=2.62VDC

C903
390UF

c
.
s
it c

1.1K

Q902

5%
50V
2 CERM
603

R904

4
1

20%
2 6.3V
ELEC
8X11.5-TH

FB
1%
1/16W
MF
2 402

390UF

20%
2 6.3V
CERM
1206

NOSTUFF

C902

1.6UH

COMP

R901

m
e
h
c

C916
1UF

U900

U900_SS

MBR0520L
SM

C901
10UF

D901

U900_VC

20%
25V
2 CERM
805

SM

1UF

CRITICAL

D902
MBR0520L

4.7

5%
1/10W
FF
2 805

MBR0520L
SM

R905

20%
2 6.3V
ELEC
TH-KZJ

LOW TO ENABLE

C909

1800UF

20%
2 6.3V
ELEC
TH-KZJ

10K
1%
1/16W
MF
2 402

SYS_SLEEP

6 8 10 11 27 46 50

U900_FEEDBACK

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

124-0324

CAP,AL ELEC,1500UF,6.3V

C909

17_INCH_LCD

124-0322

CAP,AL ELEC,1800UF,6.3V

C909

20_INCH_LCD

TABLE_5_ITEM

SHASTA CORE VOLTAGE REGULATOR

m
o

D
PP5V_ALL

PP5V_ALL

D1000
2

1
1

R1002

1
2

VCC

U1000_GATE_L

FB

U1000_FEEDBACK

5%
1/16W
MF
402

C1013

C1014

m
e
h
c

5%
25V
2 CERM
402

100K

5%
1/16W
MF
402 2

33 13 11 10 7 6

TURN_ON_PP1V2_L

SYS_POWERUP_L

TH

R1004

NOSTUFF

1.1K

5%
1/8W
FF
2 1206

1
C1007 R1003
5.11K

3300PF

10%
2 50V
CERM
603

1%
1/16W
MF
2 402
1

R1004_P2

C1012
1UF

R1005

20%
25V
2 CERM
1206

C1008
1800UF

NOSTUFF

20%
2 6.3V
ELEC
TH-KZJ

U1000_FEEDBACK

SOI

RDSON=0.016 OHM
@ VGS=2.5 V

R1008
2

2N7002DW

Q1005

Q1005_G

Q1004
D

2N7002DW

SOT-363
5

SM

SOT-363

2N7002

5%
1/16W
MF
402

Q1004

3
D

100K 1 Q1003_G
5%
1/16W
MF
402

Q1006_G

5%
1/16W
MF
402

PP5V_ALL

R1009
100K 1
2

PP1V2_RUN

Q1003

PP1V2_PWRON_SB_VCORE

23 10 6 3

SI9426DY

RDSON=0.06 OHM
@ VGS=2.5 V

TSOP

1800UF

1%
1/16W
MF
2 402

Q1006

SI3446DV

R1012
0

PP1V2_PWRON

C1009

10K

PEAK CURRENT 4.43A

PP1V2_PWRON_SB_VCORE

20%
2 6.3V
ELEC
TH-KZJ

PEAK CURRENT 0.6A

PP5V_ALL

NOSTUFF

VOLTAGE=1.2V
MIN_LINE_WIDTH=100
MIN_NECK_WIDTH=15MIL

.
w
w
w
R10141

NOSTUFF

PP1V2_PWRON_SB_VCORE

23 10 6 3

1.6UH

PP1V2_RUN FET SWITCH

PP3V3_ALL

s
p
to

CASE369

L1001

PP1V2_PWRON FET SWITCH

p
la

C1005

10%
50V
2 CERM
603

5%
1/16W
MF
402-1

23 10 6 3

NTD70N03R

NOSTUFF

0.022UF

5%
2 50V
CERM
603

R1011

C1006
220PF

5%
50V
2 CERM
603

3900PF

Q1002

68PF

R1001_P2

20%
16V
2 CERM
603

SM

0.1UF

1UF

20%
10V
2 CERM
603

Q1000_G

C1015

C1017

1 2

PEAK CURRENT OF TOTAL RAILS

5.96A

20%
2 6.3V
ELEC
8X11.5-TH

I70

NOSTUFF

LD

390UF

20%
2 6.3V
ELEC
8X11.5-TH

2N7002

CASE369

S 3

NOTE:
SET OUTPUT=1.2V
IRU3037ACS VREF=0.8VDC
VOUT=VREF*(R1003+R1005)/R1005=1.206VDC

C1003

7 8

TURN_ON_SHASTA_CORE_L

Q1000

R1010

1%
1/16W
MF
2 402

NTD60N02R

1
G

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL Q1002_DRAIN

GND

27.4K

COMP

R1001

SYS_POWERUP_L

U1000_GATE_H

5%
1/16W
MF
402 2

33 13 11 10 7 6

U1000_COMP

Q1001_GATE

390UF

20%
2 6.3V
CERM
1206

100K

SS

Q1001

R10071

U1000_SS

D 4

5%
1/10W
FF
805

SOI

HD

IRU3037ACS
8

U1000_VC_D

C1000
1UF
20%
R1000
25V

2 CERM
805

VC

U1000

PP3V3_ALL

MBR0520L
SM

U1000_VC

1UF

20%
25V
2 CERM
805

D1001
U1000_VC_R

C1001 1 C1002
10UF

SM

5%
1/10W
FF
2 805

C1004

MBR0520L

4.7

c
.
s
it c
D1002

MBR0520L
SM

SYS_SLEEP

6 8 9 11 27 46 50

R1013
1

5%
1/16W
MF
402-1

11 7 6

m
o

PP5V_ALL

D
CRITICAL

Q1100

SI4467DY
6

2
1

11 7

R1104
33 13 10 7 6

50 46 27 10 9 8 6

SYS_POWERUP_L

SYS_SLEEP

5%
1/16W
MF
402

100K 2

LM339A

Q1102

SI4467DY

GND

RAIL_RUN_FET
MIN_LINE_WIDTH=20MIL

RUN -> LOW

SLEEP -> FLOAT
SHUTDOWN -> FLOAT

FET ON IN RUN
4

V+
3

U1100

RAIL_CTL_NEG

LM339A

GND

12

R11021

FET ON IN SLEEP

RAIL_SLEEP_FET
MIN_LINE_WIDTH=20MIL

1%
1/16W
MF
603 2

RUN -> FLOAT

SLEEP -> LOW
SHUTDOWN -> FLOAT

Q1101

SI4467DY
SM-1

G
S

5
6

7
8

P-CHANNEL
Ron=11mOhm

CRITICAL

s
p
to
VR1100

Vpwr >= Vout+0.35V

Vctrl >= Vout+1.25V

CS5253
SM
VPWR VOUT
VCTRL VOUT
TAB
ADJ

3
6

R1

2
3_3V_ALL_ADJ
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

C1102
100UF

20%
2 6.3V
ELEC
SM

.
w
w
w

6
7
8

PP3V3_ALL

7 11

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PROCESS SWING
3.30V - 3.45V

SENSE

p
la

SM-1

P-CHANNEL
Ron=11mOhm

m
e
h
c

CRITICAL

FET ON IN SLEEP

PP5V_ALL

6 18 27

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SI4467DY

1
11 7 6

MIN_NECK_WIDTH=10MIL

47.0K

Q1103

SOI
2

MIN_NECK_WIDTH=10MIL

12

PP3V3_PWRON

SM-1
8
7

13

U1100
11

PP3V3_RUN

1%
1/16W
MF
2 402

SOI

V+

5%
1/16W
MF
402
RAIL_CTL_POS

1K

1%
1/16W
MF
2 402

CRITICAL

10

100K 2

1K

R1103

5%
1/16W
MF
402

R1107 1R1101

FET ON IN RUN

100K 2
1

PP3V3_ALL

R1100

6 18

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP5V_PWRON

3
7

c
.
s
it c
PP5V_PWRON

SM-1

PP5V_RUN

C1101
0.1UF

N20P80%
16V
2 CERM
603

R2

Vout=Vref(1+R2/R1)+Iadj(R2)

Vref=1.250V typ
Iadj=50uA typ

R1105
124

1%
1/16W
MF
2 603

C1100
150UF

20%
2 10V
ELEC
SM

R1106
210

1%
1/16W
MF
2 603

ELECTRICAL_CONSTRAINT_SET

NET_SPACING_TYPE

SMU_CLK10M_XTAL

15 MIL SPACING
15 MIL SPACING
15 MIL SPACING

SMU_CLK10M_XIN
SMU_CLK10M_XOUT
SMU_CLK10M_XOUT_R

15 MIL SPACING
15 MIL SPACING

RTC_CLK32K_X1
RTC_CLK32K_X2

RTC_CLK32K_XTAL

Real Time Clock

13
13
13

7
13 8 7

System Management Unit

13

13 8 7

10uF
20%

0.1uF
20%

0.1uF
20%

10V
CERM 2
402

6.3V 2
CERM
805

C1303
1uF

10%
6.3V
2 CERM
402

10V
CERM 2
402

GND_SMU_AVSS

33 13
33
36 13
30 29 13
8
8
8
8

NOTE: All analog inputs to SMU should have

a 100pF capacitor to the SMU AVSS
signal (GND_SMU_AVSS). None of
those capacitors are provided on
this page.

3
3
3
8

NOTE: Some primary and alternate functions

reuire pull-ups that are not.
provided on this page. Please.
review the latest SMU specification
to ensure missing pull-ups are
provided on another page.

8
13 8 6
13
13

18
18

NOTE: Pinout matches SMU pinout v1.4.

16
16
17
13
13

Undervoltage Reset Circuit

13

18
18 14

NO_SMU_I2C_D

18

R1399
25

_PP3V3_ALL_SMU

SMU_TO_SB_INT_L

18 14

18

5%
1/16W
MF
402

R1322

18
8
36 27 25 16

1K

5%
1/16W
MF
402 2

PP3V3_ALL_SMU_RESET
VOLTAGE=3.3V
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil

C1310 1

13

MAX6804
SOT143
MR* RSET*

NO STUFF

R1316
10M

GND

.
w
w
w
1

R13171
0

5%
1/16W
MF
402 2

13

SMU_CLK10M_XOUT

5%
1/16W
MF
402

78

VCC

U1300
QFP-80

Y
Y
Y
Y
S
S
S
S

Y
Y
Y
Y
Y
Y
Y
Y

N
S
N
N
S
S
S
S

S
S
N
N
S
S
S
S

67
66
65
64
63
62
61
60

P0[0]
P0[1]
P0[2]
P0[3]
P0[4]
P0[5]
P0[6]
P0[7]

AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07

SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_1
SMU_PWRSEQ_P1_2
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P1_4
SYS_POWERFAIL_L
SYS_DRIVE_BAY_INT_L
SYS_DOOR_AJAR

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
N
N
N

Y
Y
Y
Y
Y
Y
S
Y

Y
Y
Y
Y
Y
Y
Y
Y

59
58
57
56
55
54
53
52

P1[0]
P1[1]
P1[2]
P1[3]
P1[4]
P1[5]
P1[6]
P1[7]

AN20
AN21
AN22
AN23
INT3*
INT4*
INT5*

I2C_SMU_E_SDA
I2C_SMU_E_SCL
FAN_TACH0
FAN_TACH1
FAN_TACH2
FAN_TACH3
FAN_TACH4
FAN_TACH5

Y
Y
Y
Y
Y
N
N
N

Y
Y
Y
Y
Y
S
S
S

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
Y
Y

51
50
49
48
47
46
45
44

P2[0]
P2[1]
P2[2]
P2[3]
P2[4]
P2[5]
P2[6]
P2[7]

SDAmm
SCLmm
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7

I2C_SMU_A_SDA_IN
I2C_SMU_A_SDA_OUT
I2C_SMU_A_SCL_IN
I2C_SMU_A_SCL_OUT
I2C_SMU_D_SDA
I2C_SMU_D_SCL
SMU_CHARGE_BATT
SYS_OVERTEMP_L

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
Y
S
S

39
38
37
36
35
34
33
32

P3[0] CLK3
P3[1] Sin3
P3[2] Sout3
P3[3]
P3[4]
P3[5]
P3[6]
P3[7]

OMIT

PCNVSS
RESET*
XOUT
XIN
VREF

R13251
10K

5%
1/16W
MF
402 2

N
N
N
S
S
S
Y
Y

N
N
N
S
S
S
Y
Y

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
SMU_BOOT_RXD
SMU_BOOT_TXD

SDA
SCL
TA1out
TA1in
TA2out
TA2in
TA3out
TA3in

P7[0] 27
P7[1] 26
P7[2] 25
P7[3] 24
P7[4] 23
P7[5] 22
P7[6] 21
P7[7] 20

Y
Y
Y
Y
Y
Y
S
Y

Y
Y
Y
Y
Y
Y
N
Y

Y
Y
N
Y
N
Y
Y
Y

Y
Y
N
Y
N
Y
Y
Y

I2C_SMU_B_SDA
I2C_SMU_B_SCL
I2C_SMU_CPU_SDA_IN
FAN_RPM0
I2C_SMU_CPU_SCL_IN
FAN_RPM1
EXT_LED_L
FAN_RPM2

TA4out
TA4in
INT0*
INT1*
INT2*
NMI*
CE*

P8[0] 19
P8[1] 18
P8[2] 17
P8[3] 16
P8[4] 15
P8[5] 14
P8[6] 8
P8[7] 7

Y
Y
Y
S
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
S
Y
S
Y
Y

Y
Y
Y
S
Y
S
Y
Y

SYS_LED
SYS_COLD_RESET_L
SYS_PME_L
ACCEL_INT_L
SYS_SLEWING_L
I2C_SMU_CPU_SDA_OUT
SYS_POWERUP_L
MAKE_BASE=TRUE
SMU_SLEEP

P9[0] 5
P9[1] 4
P9[2] 3
P9[3] 2
P9[5] 1
P9[6] 80
P9[7] 79

Y
Y
Y
Y
Y
Y
S

Y
Y
Y
Y
Y
Y
Y

Y
S
Y
Y
Y
Y
S

Y
S
Y
Y
Y
Y
S

CLOCK_RESET_L
CPU_HRESET_L
SB_TO_SMU_INT_L
SB_STOPXTALS_L
SMU_PWRSEQ_P9_5
SMU_PWRSEQ_P9_6
ACCEL_LOWPWR_L

AN0 P10[0] 76
AN1 P10[1] 74
AN2 P10[2] 73
AN3 P10[3] 72
KI0* P10[4] 71
KI1* P10[5] 70
KI2* P10[6] 69
KI3* P10[7] 68

S
Y
Y
Y
Y
Y
Y
Y

S
Y
Y
Y
Y
Y
Y
Y

S
Y
Y
Y
Y
Y
Y
N

S
Y
Y
Y
Y
Y
Y
N

TP_SMU_SPARE_P10_0
SMU_WARM_RESET_L
NB_SUSPENDACK_L
SB_SUSPENDACK_L
SMU_SUSPENDREQ_L
SYS_POWER_BUTTON_L
SYS_RESET_BUTTON_L
I2C_SMU_CPU_SCL_OUT

VSS

8
8

8 13

I2C_RTC_SDA

18

I2C_RTC_SCL

6
NC

SDA

MSOP

X1
X2
SCL
SQW/ VBAT
OUT GND

13

Y1301
SM-1

1
2
4

32.768K

3
RTC_CLK32K_X2

4
1

13

C1309
0.1uF

20%
2 10V
CERM
402

8 13
8 13
8
8
8
8
8

18
18

13 18

16

13 18
16

SMU Pull-ups / pull-down

_PP3V3_ALL_SMU

7 8 13

13

R1300
10K

17

21

13 25 77

5%
1/16W
MF
402

R1302
10K

13 24

SYS_POWERUP_L

6 7 10 11 13 33

SYS_POWER_BUTTON_L

6 7 13

SYS_PME_L

13 25 77

SYS_SLEWING_L

13 25 27 33

SMU_SUSPENDREQ_L

13 24 25

SYS_COLD_RESET_L

13 24

SMU_SLEEP

8 13

5%
1/16W
MF
402

13 25 27 33
18
6 7 10 11 13 33

PP3V3_PWRON

R1304
10K

8 13

27

5%
1/16W
MF
402

14 29 30
25

PP3V3_RUN

25

R1312
100K

5%
1/16W
MF
402

PP2V5_PWRON

R1311
100K

8
8 24

24

13 24 25

6 7 13

5%
1/16W
MF
402

R1313
100K

25

5%
1/16W
MF
402

7
13 18

R1310

10K

75

RTC_CLK32K_X1

U1301
DS1338

18

R1327

5%
1/16W
MF
2 402

XW1300
SM
1

VCC

10V
CERM 2
402

AVSS

11

c
.
s
it c

Y
Y
Y
Y
Y
Y
Y
Y

100K2
5%
1/16W
MF
402

Y1300
8X4.5MM-SM

ALIAS

Y
Y
Y
Y
Y
Y
Y
Y

CRITICAL

10.0000M
1
2

ALIAS

SMU_BOOT_BUSY
SMU_BOOT_SCLK
SMU_BOOT_CE

RTS0*/
CTS0* P6[0] 43
CLK0 P6[1] 42
RXD0 P6[2] 41
TXD0 P6[3] 40
RTS1*
(BUSY) P6[4] 31
CLK1 P6[5] 30
RXD1 P6[6] 29
TXD1 P6[7] 28

TB0in
TB1in
TB2in
AN24
AN25
AN26
AN27

_PPVREF_SMU

6
9
10
12
77

ALIAS

m
e
h
c

s
p
to

SMU_BOOT_CNVSS
SMU_RESET_L
SMU_CLK10M_XOUT_R
SMU_CLK10M_XIN

AVCC

M30280F8

CPU_SENSE_I
CPU_SENSE_V
CPU_TEMP
CPU_BYPASS_L
ALS0_OUT
ALS1_OUT
ALS_GAIN_BOOST
SMU_ADAPTER_ID

p
la

U1302

SMU_MANUAL_RESET_L

13

VCC

10V
CERM 2
402

8 7 6

8 6

0.1uF
20%

13

8 13 33 36

Consumer
Portable
Tower
Server

Y = Primary function
N = Alternate function
(see aliases below)
S = Spare

NOTE: CPU current/voltage monitoring

(CPU_SENSE_I/CPU_SENSE_V) requires
100K/10uF RC filter at SMU pins.
Caps should connect to GND_SMU_AVSS.
SMU_VREF should be same signal or
reference used by monitoring
circuit, but be aware that this will
affect other analog inputs such as
AC adapter ID.

Consumer
Portable
Tower
Server

BOM options provided by this page:

(NONE)

m
o

PP3V3_ALL_SMU_AVCC 8
VOLTAGE=3.3V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil

5%
1/16W
MF
402

C1300 1 C1301 1 C1302 1

C1308 1
0.1uF
20%

R1315
4.7

_PP3V3_ALL_SMU

Power aliases required by this page:

- _PP3V3_ALL_SMU
- _PP3V3_ALL_RTC
- _PP3V3_PWRON_SMU
- _PPVREF_SMU (SMU AVCC or 2.5V reference)

13 8 7

_PP3V3_ALL_RTC
_PP3V3_ALL_SMU

13

Signal aliases required by this page:

(NONE)

DIFFERENTIAL_PAIR

Page Notes
D

Keep crystal subcircuit close to SMU.

GND_SMU_AVSS 8 13 33 36
VOLTAGE=0V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil

Y1300s load capacitance is 12pF

C1304 1 C1305 1
12pF
5%

50V
CERM 2
402

12pF
5%

50V
CERM 2
402

Alternate Functions

Consumer
13
13
13

FAN_TACH3
FAN_TACH4
FAN_TACH5

Port
2.5 ALIAS
2.6 ALIAS
2.7 ALIAS

SYS_LED_RED
SYS_LED_GREEN
SYS_LED_BLUE

Portable

21

13 8 6

21

13

21

13
13

SYS_POWERFAIL_L
SYS_DRIVE_BAY_INT_L
SYS_DOOR_AJAR
EXT_LED_L

Port
1.5 ALIAS
1.6 ALIAS
1.7 ALIAS
7.6 ALIAS

SMU_ACIN
SMU_BATT_DET_L
SYS_LID_OPEN
SYS_KBDLED

Tower & Server

33 13
36 13
30 29 13
13 8
13 8
13 8
18 13
18 13
18 13

Port
CPU_SENSE_I
0.0 ALIAS
CPU_TEMP
0.2 ALIAS
CPU_BYPASS_L
0.3 ALIAS
CPU_VID<0>
6.0 ALIAS
CPU_VID<1>
6.1 ALIAS
CPU_VID<2>
6.2 ALIAS
I2C_SMU_CPU_SDA_IN
7.2 ALIAS
I2C_SMU_CPU_SCL_IN
7.4 ALIAS
I2C_SMU_CPU_SCL_OUT 10.7 ALIAS

SYS_SLOT_PWR
FAN_TACH6
FAN_TACH7
FAN_RPM3
FAN_RPM4
FAN_RPM5
FAN_PWM6
FAN_PWM7
EXT_POWER_BUTTON_L

R1400
EI_CPU1_CLK_P_R

27

1
5%
MF

EI_CPU1_CLK_P

14 27

EI_CPU1_CLK_N

14 27

1/16W
402

m
o

R1401
EI_CPU1_CLK_N_R

27

1
5%
MF

CPU1_HTBEN_R

27

EI_CPU1_SYNC_R

27

2
1/16W
402

0 R1402
1

5% 402
0 R1403
1

CPU1_HTBEN

14

EI_CPU1_SYNC

14 27

5% 402

NOSTUFF

J1400
YFS-30-03-H-08-SB
F-ST-BGA
27 14
30 29

H1

EI_CPU1_SYNC
CHKSTOP_L

H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12

H13
H14
H15
H16
29 28
29 28
29 28
29 28
29 28
29 28
29 28
29 28
29 28
29 28
29 28
29 28
30 29
30 29 28

H17

EI_NB_TO_CPU_AD<13>
EI_NB_TO_CPU_AD<15>
EI_NB_TO_CPU_AD<17>
EI_NB_TO_CPU_AD<21>
EI_NB_TO_CPU_AD<20>
EI_NB_TO_CPU_AD<25>
EI_NB_TO_CPU_AD<29>
EI_NB_TO_CPU_AD<28>
EI_NB_TO_CPU_AD<40>
EI_NB_TO_CPU_AD<10>
EI_NB_TO_CPU_AD<39>
EI_NB_TO_CPU_AD<36>
RI_L
EI_QREQ_L

H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30

H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30

G1 G1
G2 G2
G3 G3 NC
G4 G4
G5 G5
G6 G6
G7 G7
G8 G8
G9 G9
G10 G10
G11 G11
G12 G12 NC
G13 G13
G14 G14
G15 G15
G16 G16
G17 G17
G18 G18
G19 G19
G20 G20
G21 G21
G22 G22
G23 G23
G24 G24
G25 G25
G26 G26
G27 G27
G28 G28
G29 G29
G30 G30

EI_CPU1_CLK_P

14 27

EI_CPU1_CLK_N

27 14

F3
F4

EI_CPU_TO_NB_AD<3> 28 29
EI_CPU_TO_NB_AD<4> 28 29
EI_CPU_TO_NB_AD<7> 28 29
EI_CPU_TO_NB_AD<11> 28 29
EI_CPU_TO_NB_CLK_N 28 29
EI_CPU_TO_NB_CLK_P 28 29
EI_CPU_TO_NB_SR_N<1> 28 29
EI_CPU_TO_NB_SR_P<1> 28 29

F5
F6
F7
F8
F9
F10
F11
F12

EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<28>
EI_NB_TO_CPU_AD<14>
EI_NB_TO_CPU_AD<12>
EI_NB_TO_CPU_AD<18>
EI_NB_TO_CPU_AD<19>
EI_NB_TO_CPU_AD<27>
EI_NB_TO_CPU_AD<26>
EI_NB_TO_CPU_AD<30>
EI_NB_TO_CPU_AD<42>
EI_NB_TO_CPU_AD<41>

28 29

F13

28 29

F14
F15

28 29

F16

28 29
28 29

EI_NB_TO_CPU_AD<5>

29 28

F18

28 29

F19

28 29

F20

28 29

F21

28 29

F22

28 29

F24

28 29

F25

28 29

F26
F27

EI_NB_TO_CPU_SR_N<0> 28 29
EI_NB_TO_CPU_SR_P<0> 28 29
I2C_SMU_A_SCL_OUT 13 18

EI_NB_TO_CPU_AD<37>
EI_NB_TO_CPU_SR_N<1>
EI_NB_TO_CPU_SR_P<1>

29 28
29 28
29 28

.
w
w
w
7

F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30

E1 E1
E2 E2 NC
E3 E3 NC
E4 E4 NC
E5 E5 NC
E6 E6
E7 E7
E8 E8 NC
E9 E9
E10 E10
E11 E11
E12 E12
E13 E13
E14 E14
E15 E15
E16 E16
E17 E17
E18 E18
E19 E19
E20 E20
E21 E21
E22 E22 NC
E23 E23
E24 E24
E25 E25
E26 E26
E27 E27
E28 E28
E29 E29
E30 E30

30 29 25

F28
F29
F30

D1

CPU_INT_L

D2
D3
D4
D5
D6

EI_CPU_TO_NB_AD<8> 28 29
EI_CPU_TO_NB_AD<13> 28 29

D7
D8

EI_CPU_TO_NB_AD<12> 28 29
EI_CPU_TO_NB_AD<5> 28 29
EI_CPU_TO_NB_AD<36> 28 29
EI_CPU_TO_NB_AD<35> 28 29
EI_CPU_TO_NB_AD<18> 28 29
EI_CPU_TO_NB_AD<43> 28 29
EI_CPU_TO_NB_AD<42> 28 29
EI_CPU_TO_NB_AD<38> 28 29
EI_CPU_TO_NB_AD<40> 28 29
EI_NB_TO_CPU_AD<9> 28 29
EI_NB_TO_CPU_AD<11> 28 29
EI_NB_TO_CPU_AD<0> 28 29
EI_NB_TO_CPU_AD<1> 28 29

D9

D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30

C1 C1
C2 C2 NC
C3 C3 NC
C4 C4 NC
C5 C5 NC
C6 C6
C7 C7
C8 C8
C9 C9
C10 C10
C11 C11
C12 C12
C13 C13
C14 C14
C15 C15
C16 C16
C17 C17
C18 C18
C19 C19
C20 C20
C21 C21
C22 C22
C23 C23
C24 C24
C25 C25
C26 C26
C27 C27
C28 C28
C29 C29
C30 C30

m
e
h
c
D10
D11
D12
D13
D14
D15
D16

29 28

EI_CPU_TO_NB_AD<15>

D17
D18
D19
D20
D21
D22

s
p
to
F23

p
la

F17

28 29

F1
F2

EI_NB_TO_CPU_AD<22> 28 29
EI_NB_TO_CPU_AD<33> 28 29
EI_NB_TO_CPU_AD<43> 28 29
EI_NB_TO_CPU_AD<2> 28 29
EI_NB_TO_CPU_AD<38> 28 29
SYNCENABLE 29 30
TP_PROC_TRIGGER_OUT 6 29

D23
D24

NCD25

29 28
29 28
29 28

29 28
29 28

EI_NB_TO_CPU_AD<8>
EI_NB_TO_CPU_AD<24>
EI_NB_TO_CPU_AD<7>
EI_NB_TO_CPU_AD<6>
EI_QACK_L

D26
D27
D28
D29
D30

c
.
s
it c

EI_CPU_TO_NB_AD<6> 28 29
EI_CPU_TO_NB_AD<21> 28 29
EI_CPU_TO_NB_AD<20> 28 29
EI_CPU_TO_NB_AD<25> 28 29
EI_CPU_TO_NB_AD<26> 28 29
EI_CPU_TO_NB_SR_P<0> 28 29
EI_CPU_TO_NB_SR_N<0> 28 29
EI_CPU_TO_NB_AD<27> 28 29
EI_CPU_TO_NB_AD<23> 28 29
EI_CPU_TO_NB_AD<39> 28 29
EI_CPU_TO_NB_AD<16> 28 29
EI_CPU_TO_NB_AD<19> 28 29 29

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16

29 28

EI_NB_TO_CPU_AD<4>
EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_AD<16>

29 28

EI_NB_TO_CPU_AD<35>

28

29 28

B17
B18
B19

NC B20
B21

NC B22
29 28
29 28
29 28
29 28
29 28
29 28

EI_SE

28 29 30

29

18 13

EI_NB_TO_CPU_AD<34>
EI_NB_TO_CPU_AD<31>
EI_NB_TO_CPU_AD<32>
EI_NB_TO_CPU_AD<23>
EI_NB_TO_CPU_CLK_N
EI_NB_TO_CPU_CLK_P
MCP_L
I2C_SMU_A_SDA_OUT

B23
B24
B25
B26
B27
B28
B29
B30

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30

A1 A1
A2 A2
A3 A3
A4 A4
A5 A5
A6 A6
A7 A7
A8 A8
A9 A9
A10 A10
A11 A11
A12 A12
A13 A13
A14 A14
A15 A15
A16 A16
A17 A17
A18 A18
A19 A19
A20 A20
A21 A21
A22 A22
A23 A23
A24 A24
A25 A25
A26 A26
A27 A27
A28 A28
A29 A29
A30 A30

CPU_HRESET_L
CPU1_HTBEN
EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<29>

13 29 30
14
28 29
28 29

28 29
28 29
28 29
28 29
28 29
28 29

28 29
28 29
28 29
28 29
28 29
28 29

FAN 0 - Q37 STYLE CPU FAN CONTROL CIRCUIT

CPU FAN 2

SYSTEM TEMP SENSOR

PP12V_RUN

m
o

R1645
1

R1640

C1614
10UF

10K

1%
1/16W
MF
2 402

R1641
100K

R1642
100K

1%
1/16W
MF
402

1%
1/16W
MF
402

R1605
13

FAN_RPM0

Q1600
2N7002

FAN_0_CNTL

5%
1/16W
MF
402

R1639

1/16W
MF

2 16V
CERM

10K
1%

SM

2 402

C1601
0.47UF

R1644

1
C1619
47UF

5%
1/16W
MF
402 2

100PF
1

FAN_0_OPM

U1600

D1604
1N914
3

FAN_0_GT

Q1601

1
1

IRF5505

SM

SOT23

FAN_0_OPP

5%
1/16W
MF
402

R16011

R1603
0

10K

5%
1/16W
MF
2 402

PP3V3_PWRON

C1616

C1617 1

4700PF
1

1%
1/16W
MF
402 2

FAN_TACH0

C1618

2 CRITICAL

D1605
SM

10UF

MBR0530

10%

10%
16V
CERM 2
1210

10%
50V
CERM
603

2 16V
CERM

1210

m
e
h
c

1%
1/16W
MF
2 402

10UF

10K

13

LM75

A0
A1
A2

18

I2C_TEMP_B_SDA

SDA

18

I2C_TEMP_B_SCL

SCL
GND

CRITICAL

R1621

3
1
OS TEMP_SENSOR_OS

2 SYS_OVERTEMP_L

13 25
27 36

5%
1/16W
MF
402

HF28040-B

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

R1604

R1606
0

FAN_0_PWR

U1602
SOP

IIC ADDR:90(1001000)

M-ST-TH

10K 2

1%
1/16W
MF
402

NOSTUFF
1

D
8

VS+

J1600

MAX FAN CURRENT=0.5A

R1643

c
.
s
it c

PP3V3_PWRON

CRITICAL

NOSTUFF

R1600
1

C1600
10UF

10%
2 16V
CERM
1210

20%
16V 2
ELEC
SM

LM358-SOI

20%

FAN_0_GATE

5%
50V
CERM
402

CRITICAL

0.1UF
603

NOSTUFF

4.7K

C1615

C1613

5%
1/16W
MF
402

20%
16V
2 CERM
805

20%
16V 2
ELEC
SM

FAN_0_DRV_F

FAN_0_DRV

4.7 2

PP12V_FAN_0_ANALOG
VOLTAGE=12V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

FAN_0_TACH

5%
1/16W
MF
402

s
p
to

2
3
4

FAN 1 - Q37 STYLE CPU FAN CONTROL CIRCUIT

SYSTEM FAN 1
R1611
1

R1616

C1610
10UF

R1615
1

13

FAN_RPM1

FAN_1_CNTL

R1620
10K
1%

SM

1/16W
MF
2 402

R1619
0
2

5%
1/16W
MF
402

.
w
w
w
1

2N7002

NOSTUFF

Q1602

5%
1/16W
MF
402

R1614

100K 2
1%
1/16W
MF
402

R1635
0

20%
603

R1618
0

5%
1/16W
MF
2 402

R1623
10K

R1636
13

FAN_TACH1

1%
1/16W
MF
2 402

FAN_1_TACH

5%
1/16W
MF
402

1%
1/16W
MF
402

0.47UF

R1610

NOSTUFF

C1604 1
47UF

20%
16V 2
ELEC
SM

C1605

U1601

10K

0.01UF

C1603

20%
16V
2 CERM
402

10UF

10%
2 16V
CERM
1210

1N914
3

FAN_1_GT

Q1603

1
1

IRF5505

SM

SOT23

CRITICAL

R16171

D1602

FAN_1_OPP

J1601

D
MAX FAN CURRENT=0.5A
4

R1613
10K
1

FAN_1_PWR

C1608
4700PF
1

1%
1/16W
MF
402 2

10%
50V
CERM
603

L1600

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

C1607 1
10UF

10%
16V
CERM 2
1210

C1606

M-ST-TH

D1601
SM
MBR0530
1

PP12V_RUN_FAN_1_LCL

FAN_1_PWR_FILT

SM

2 CRITICAL

10UF

10%
2 16V
CERM
1210

10-89-7062

FERR-EMI-100-OHM

1%
1/16W
MF
402

C1602

FAN_1_GATE

5%
50V
CERM
402

LM358-SOI
1

1
SM

4.7K

100PF

L1603

FERR-EMI-100-OHM
PP12V_RUN_FAN_1_LC

SM

5%
1/16W
MF
402 2

20%
2 16V
CERM
805

FAN_1_OPM

L1602

FERR-EMI-100-OHM

5%
1/16W
MF
402

C1609

CRITICAL

0.1UF

2 16V
CERM

100K 2

C1611

NOSTUFF

PP3V3_PWRON

20%
16V 2
ELEC
SM

FAN_1_DRV_F

FAN_1_DRV

p
la

10K

1%
1/16W
MF
2 402

4.7

PP12V_FAN_1_ANALOG
VOLTAGE=12V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

PP12V_RUN

L1601

FERR-EMI-100-OHM
1

FAN_1_TACH_FILT

SM

L1604

FERR-EMI-100-OHM
1

FAN_1_GND_FILT

SM

m
o

c
.
s
it c

FAN 2 - Q37 STYLE SYSTEM FAN CONTROL CIRCUIT

PP12V_RUN

R1740

PP12V_FAN_2_ANALOG
VOLTAGE=12V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

1
C1714
10UF

10K

1%
1/16W
MF
2 402

13

R1705
0
1

FAN_RPM2

Q1700
2N7002

FAN_2_CNTL

5%
1/16W
MF
402

R1742
100K

1%
1/16W
MF
402

1%
1/16W
MF
402

R1739

10K
1%

SM

R1741
100K
1

FAN_2_DRV

1/16W
MF
2 402

NOSTUFF

NOSTUFF
1

R1703
0

5%
1/16W
MF
2 402

PP3V3_PWRON

R1704
10K

13

FAN_TACH2

1%
1/16W
MF

2 402

p
la

FAN_2_TACH

5%
1/16W
MF
402

.
w
w
w

m
e
h
c

5%
1/16W
MF
402 2

CRITICAL
8

U1700

FAN_2_GATE

5%
50V
CERM
402

D1704

LM358-SOI
1

20%

603

4.7K

100PF

FAN_2_OPM

0.1UF

16V
2 CERM

R17441

C1715

C1713

C1701
0.47UF

FAN_2_GT

s
p
to
R17011
10K

1%
1/16W
MF
402 2

C1716
4700PF
1

C1717 1
10UF

10%
16V
CERM 2
1210

10%
50V
CERM
603

10UF
10%

1210

SM

CRITICAL

J1700

D
MAX FAN CURRENT=0.5A
4

10-89-7062
M-ST-TH
1

1%
1/16W
MF
402

C1700

2 16V
CERM

IRF5505

R1743
10K
1

20%
16V 2
ELEC
SM

Q1701

NOSTUFF

1
C1719
47UF

1N914
SOT23

FAN_2_OPP

5%
1/16W
MF
402

R1706
0

5%
1/16W
MF
402

20%
16V
2 CERM
805

R1700
0
1

20%
16V 2
ELEC
SM

FAN_2_DRV_F

R1745
4.7

FAN_2_PWR
MIN_LINE_WIDTH=20MIL

C1718

MIN_NECK_WIDTH=10MIL
2 CRITICAL

10%

1210

D1705
SM

10UF

2 16V
CERM

MBR0530
1

11 6

27 18 11 6

I2C A BUS

14 13

13

14 13

R1801

2K

4.7K

20%
10V
CERM 2
402

5%
1/16W
MF
2 402

200

5%
1/16W
MF
2 402

2K

5%
1/16W
MF
402 2

R18081

R1809

0.1UF

R18001

13

PP1V2_EI_NB

C1800 1

PP3V3_PWRON

SMU
MASTER
U1300
I2C_SMU_A_SDA_IN
MAKE_BASE=TRUE
I2C_SMU_A_SDA_OUT
MAKE_BASE=TRUE
I2C_SMU_A_SCL_IN
MAKE_BASE=TRUE
I2C_SMU_A_SCL_OUT
MAKE_BASE=TRUE
PINS 36-39

PP5V_PWRON

5%
1/16W
MF
402 2

PP3V3_PWRON

R1810
200

5%
1/16W
MF
2 402

I2C B BUS

V+

U1800
GND

NET_SPACING_TYPE=I2C

Q1800

12

NET_SPACING_TYPE=I2C

U3

SOT-363

I2C_NB_A_SDA
I2C_NB_A_SCL

NET_SPACING_TYPE=I2C

24
24

1
3

LM339A

SOI
1

PINS A20, B20

V+

U1800
GND

3
7

Q1800

D
12

PP3V3_PWRON

2N7002DW

2K

5%
1/16W
MF
402 2

R1818

5%
1/16W
MF
2 402

LM339A

R18161

11

12

5%

SMU_CPU_JTAG_OR_I2C

I2C

I2C_CPU_A_SCL
I2C_CPU_A_SDA_TO_SMU

I2C

LM339A
SOI
2

CPU

5%
1/16W
MF
2 402

U2900

m
e
h
c

U1800
GND

NOSTUFF

RP1801

I2C_0V546_REF

CPU JTAG

5%

8
7

JTAG_CPU_TDO
JTAG_CPU_TDI
JTAG_CPU_TMS
JTAG_CPU_TCK

29 30

29 30
29 30

PP2V5_PWRON

R1805
2K

5%
1/16W
MF
402 2

R1804

p
la

U3LITE

2K
5%
1/16W
MF
2 402

MASTER
U3
I2C_NB_C_SDA
MAKE_BASE=TRUE

NET_SPACING_TYPE=I2C

.
w
w
w

NET_SPACING_TYPE=I2C

I2C_NB_C_SCL
MAKE_BASE=TRUE
PINS C21, E21

24

24

DIMMS

J4000 = A0
J4001 = A2

I2C_DIMM_SDA
I2C_DIMM_SCL

ALIAS
ALIAS

40

U3LITE B
U3

I2C_NB_B_SDA
I2C_NB_B_SCL

24
24

s
p
to
576

1%
1/16W
MF
2 402

29

40

PP2V5_PWRON

R18121
2K

5%
1/16W
MF
402 2

13

13

R1813

R1807

2K

5%
1/16W
MF
2 402

2K

5%
1/16W
MF
402 2

I2C_SMU_B_SDA
MAKE_BASE=TRUE
I2C_SMU_B_SCL
MAKE_BASE=TRUE
PINS 26, 27

NET_SPACING_TYPE=I2C

PULSAR
U2600

27
27

I2C_CLOCK_SDA
I2C_CLOCK_SCL

ALIAS
ALIAS

PINS C1, B1

U1602
16
16

I2C_TEMP_B_SDA
I2C_TEMP_B_SCL

ALIAS
ALIAS

PINS 1, 2

PP3V3_RUN

R18151

SHASTA

1K

MASTER
U2300

5%
1/16W
MF
402 2

R1814
1K

5%
1/16W
MF
2 402

NET_SPACING_TYPE=I2C

I2C_SB_SDA
MAKE_BASE=TRUE
I2C_SB_SCL
MAKE_BASE=TRUE
PINS Y9, AB7

25

NET_SPACING_TYPE=I2C

25

B
94 6
94 6

I2C_UDASH_SDA
I2C_UDASH_SCL

ALIAS
ALIAS

PINS 21, 24
1

R1806
2K

5%
1/16W
MF
2 402

RTC
AUDIO

U1301

U9500
I2C_RTC_SDA
I2C_RTC_SCL

13
13

95
95

I2C_AUDIO_SDA
I2C_AUDIO_SCL

ALIAS
ALIAS

PINS 18, 19

NOSTUFF
1

R1823
0

5%
1/16W
MF
2 402

NOSTUFF

R1824
2

SMU E

R1826
2

5%
1/16W
MF
402

MASTER
U1300

SMU D

5%
1/16W
MF
402

MASTER
U1300

NOSTUFF
13

I2C_SMU_E_SDA

I2C

13

I2C_SMU_E_SCL

I2C

NET_SPACING_TYPE=I2C

I2C SB BUS

PINS 5, 6

5%
1/16W
MF
2 402

PP3V3_ALL

I2C
I2C

5%
1/16W
MF
402 2

2K

SYSTEM TEMP SENSOR

NOSTUFF

R1802

J9400

I2C
I2C

R18221

MICRODASH

PINS C20, B21

PINS 91, 92
OF EACH DIMM

29

c
.
s
it c

I2C D & E BUS

I2C C BUS
1

C1801 1R1811
0.1UF

20%
10V
2 CERM
402

29 30

1/16W
SM1

I2C_CPU_A_SCL
I2C_CPU_A_SDA

PINS AA20, Y21

V+

12

1.2K

NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C

1/16W
SM1

5%
1/16W
MF
2 402

7 29 30 31 35

0K

R1817

5%
1/16W
MF
402 2

0K
8

R1821

1.2K

RP1800

V+

U1800
GND

I2C

5%
1/16W
MF
402 2

PP1V2_EI_CPU

10

SOI

R1820

2K

13

I2C

NOSTUFF
1

SMU
MASTER
U1300
I2C_SMU_CPU_SCL_IN
13
MAKE_BASE=TRUE
I2C_SMU_CPU_SCL_OUT
13
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_IN
13
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_OUT
13
MAKE_BASE=TRUE
PINS 14,25,23,68

NOSTUFF

SOT-363

2K
5%
1/16W
MF
402 2

MASTER
U1300

2N7002DW

R18031

SMU

U3LITE

6
9
D

R18191

m
o

SOI
14

7 28

LM339A

NET_SPACING_TYPE=I2C

27 18 11 6

R1825
2

5%
1/16W
MF
402

PINS 50, 51

R1827
2

I2C
I2C

5%
1/16W
MF
402

I2C_SMU_D_SDA

13

I2C_SMU_D_SCL

13

PINS 34, 35

TOTAL CURRENT EXCLUDING LEDS CURRENT < 170 MICRO AMPS

RGB_LED

C2105

RGB_LED

220PF

+
-

13

400-OHM-EMI

SM-1

G_DRV
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

11TSSOP

RGB_LED

2N3904

R2105

0.47UF

200K

20%
10V
CERM 2
603

1%
1/16W
MF
402 2

G_DRV_FB
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

RGB_LED

R2112
1K

G_IN_OFFSET

RGB_LED

1
1

C2109

RGB_LED

220PF

R2100

1%
1/16W
MF
402

5MV INPUT OFFSET

25.5

1%
1/16W
MF
2 402

m
e
h
c

C
PLACE THESE PARTS CLOSE TO SMU IC
PP5V_PWRON

R_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
1

RGB_LED

RGB_LED

L2101

R21021

400-OHM-EMI

953K

5%
1/16W
MF
402

RGB_LED

U2100

R_PWM_IN_H

RGB_LED

R21101
953K
1%
1/16W
MF
402 2

R_PWM_DC

SM-1

1%
1/16W
MF
402 2

R2115
SYS_LED_RED
MAKE_BASE=TRUE
PWM INPUT FROM SMU
13

R_BASE_DRV

RGB_LED

11TSSOP

Q2108

RGB_LED

2N3904

C2101

SM

0.022UF
2

R_DRV_FB
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

RGB_LED 1

RGB_LED

C2112

0.47UF

20%
10V
CERM 2
603

R2111

20%
16V
CERM
402

200K
1%
1/16W
MF
402 2

RGB_LED

R2114
2

R_IN_OFFSET

1K

RGB_LED

R2113

1%
1/16W
MF
402

25.5

1%
1/16W
MF
2 402

p
la

B
PLACE THESE PARTS CLOSE TO SMU IC

.
w
w
w

PP5V_PWRON

RGB_LED

R21181
953K

1%
1/16W
MF
402 2

RGB_LED

R2130
2

5%
1/16W
MF
402

RGB_LED

U2100

B_PWM_IN_H

RGB_LED 1

R2116
953K

1%
1/16W
MF
402 2

B_PWM_DC

SYS_LED_BLUE
13
MAKE_BASE=TRUE
PWM INPUT FROM SMU

+
-

LP324
1

B_BASE_DRV

11TSSOP

RGB_LED

B_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2118
0.47UF

RGB_LED 1

20%
10V
CERM 2
603

20%
16V
CERM
402

R2117
200K

1%
1/16W
MF
402 2

RGB_LED

R2127

B_IN_OFFSET

1K

1%
1/16W
MF
402

PWM INPUT FROM SMU

RGB_LED

1K

5%
1/16W
MF
402

WHITE_LED
1

1K

C2110
1

5%
25V
2 CERM
402

GND_CHASSIS_LED

7 21

5%
25V
CERM
402

SYS_GATE

SYS_LED_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

5%
1/16W
MF
402

WHITE_LED

1WHITE_LED

R2103

5%
1/16W
MF
402 2

100
1%
1/16W
MF
2 402

SYS_LED_DRV_C
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SYS_LED_IN
3

WHITE_LED

R2107

WHITE_LED

Q2101

FDV301N

SM-1

5%
1/16W
MF
402

C2111
220PF

WHITE_LED

R2106

4.7K

2
SM-1

SM-1

WHITE_LED
SYS_LED_H

R2129

L2105

400-OHM-EMI

WHITE_LED

PP5V_PWRON

WHITE_LED

SM6

400-OHM-EMI

SOT-23

U2100_UNUSED

L2103

R2132
SYS_LED

8
11TSSOP

SYS_DRV_A
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

WHITE

NOSTUFF

13

LP324

NOSTUFF

400-OHM-EMI

SM
2

(STUFF WHEN SYS_LED_L = ACTIVE HIGH)

(AND NO STUFF R2132, R2119 & Q2100)

B_DRV
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

RGB_LED

Q2114
2N3904

0.022UF

RGB_LED

LED2101

Q2100

1%
1/16W
MF
402

+
-

NOSTUFF

953K 1

10

c
.
s
it c

FDV302P

20%
10V
CERM 2
402

R2119

U2100

0.1UF

220PF

PP3V3_PWRON

RGB_LED

C2103 1

PLACE THESE PARTS CLOSE TO SMU IC

L2102

C2102

s
p
to

R_DRV
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

LP324

+
-

5%
25V
CERM
402

CHANGE R2100 VALUE

TO SET LED CURRENT
MAX LED CURRENT = 0.5 / R

100% DUTY CYCLE OF 3V-PP PWM = 0.5V

RGB_LED

7 21

5%
25V
CERM
402

20%
16V
CERM
402

RGB_LED 1

GND_CHASSIS_LED

220PF

SM

RGB_LED

220PF

C2108

RGB_LED

Q2102

C2107

RGB_LED

C2104

RGB_LED
1

5%
25V
2 CERM
402

0.022UF

C2106 1

5
BLUE

G_BASE_DRV

m
o

2
GRN

LP324
14

SM-1

SYS_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

1%
1/16W
MF
402 2

953K

12

RGB_LED_A
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

RGB_LED

RGB_LED 1

R2104

AMB

L2100

U2100
4

G_PWM_IN_H

RGB_LED

L2104

5%
1/16W
MF
402

G_PWM_DC

SYS_LED_GREEN
MAKE_BASE=TRUE
PWM INPUT FROM SMU

13

RGB_LED

1%
1/16W
MF
402 2

RGB_LED

400-OHM-EMI

953K

R2101

PP5V_PWRON

AMB-GRN-BLUE
PLCC

G_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

R21091
RGB_LED

PP5V_PWRON

LED2100
LATBG66B

7 21

5%
25V
CERM
402

PP5V_PWRON

RGB_LED

GND_CHASSIS_LED

PLACE THESE PARTS CLOSE TO SMU IC

SM
2

B_DRV_FB
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
RGB_LED

R2126
25.5

1%
1/16W
MF
2 402

1
TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

343S0284

IC,U3LITE,V1.1,300MM,PBGA

U3
TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

343S0282

343S0284

BOM OPTION

REF DES

COMMENTS:

U3

U3L,V1.1,200MM,PBGA

TABLE_ALT_ITEM

m
o

NOTE:
SET OUTPUT=1.5VDC FOR U3LITE CORE
IRU3037CS VREF=1.25VDC
VOUT=VREF*(R2203+R2205)/R2205=1.5VDC

7.73A OF PEAK CURRENT DRAW ON PCORE_NB

SM

U2200_VC_R

C2204

1UF

20%
2 25V
CERM
805

C2216

VCC

VC

U2200

IRU3037CS
HD
U2200_SS
U2200_COMP

U2200_GATE_H

SS
LD

FB

Q2201
S

R2201

C2214
0.1UF

20%
16V
2 CERM
603

R2201_P2

C2215
3900PF

NTD60N02R

1
G
1

68PF

C2206

CASE369

S3

5%
25V
2 CERM
402

C2205

0.022UF

p
la

C2222
0.1UF

20%
10V
2 CERM
402

C2223

0.1UF

20%
10V
2 CERM
402

.
w
w
w
C2225
0.1UF

20%
10V
2 CERM
402

C2227
0.1UF

20%
10V
2 CERM
402

C2228
0.1UF

20%
10V
2 CERM
402

C2229
0.1UF

20%
10V
2 CERM
402

R2203
2K

20%
10V
2 CERM
603

C2212

20%
2 25V
CERM
1206

R2205

C2208

1800UF

C2209

0.1UF

C2231
0.1UF

20%
10V
2 CERM
402

C2232
0.1UF

20%
10V
2 CERM
402

C2233
0.1UF

20%
10V
2 CERM
402

C2234
0.1UF

20%
10V
2 CERM
402

C2235
0.1UF

20%
10V
2 CERM
402

C2236
0.1UF

20%
10V
2 CERM
402

0.1UF

20%
10V
2 CERM
402

P16

U3

AE10

PBGA
(SYM 6 OF 7)

P19
N4
N8
N9
N14

AC7

N17

AC13
AC16

N23
N27

AC22
AB2

M12
M15

AB6

M20

AB23
AB27

L10
L13

AA10

L18

AA19
Y12

K2
K6

Y15

20%
2 6.3V
ELEC
TH-KZJ

GND K16
K21

W8
W13

K25
J9

W18

J14

W21
W25

H10
H19

V11

G4

V16
V19

G23
G27

U9

F13
F16
F22

T2
T6

C2238
0.1UF

20%
10V
2 CERM
402

C2239
0.1UF

20%
10V
2 CERM
402

C2240
0.1UF

20%
10V
2 CERM
402

C2242
0.1UF

20%
10V
2 CERM
402

C2243
0.1UF

20%
10V
2 CERM
402

D2
D7

T12

D10

T15
T20

D19
D25

T23

B4

T27
R10

B13
B16

R13

B22

C2244
0.1UF

20%
10V
2 CERM
402

K11

Y20
W4 GND

U14
U17

K15

K12

L14
L17

M16

N13

P12
P15

N18
M11

R18
P11

U3LITE
V1.0-300MM

AE19
AE25

10K

C2237

R14
R17

AG16

1%
1/16W
MF
2 402

T16

VDD

OMIT

AG22
AE4

1800UF

20%
2 6.3V
ELEC
TH-KZJ

AG7
AG13

s
p
to

C2230

20%
10V
2 CERM
402

1%
1/16W
MF
2 402

1UF

10%
50V
2 CERM
603

CHECK FETS

PPVCORE_NB

1UF

1%
1/16W
MF
2 402

NOSTUFF

U2200_FEEDBACK

C2207

R2204_P2

NOSTUFF

220PF

5%
50V
2 CERM
603

NOSTUFF

1.1K

Q2202

C2213

m
e
h
c
NOSTUFF

5%
50V
2 CERM
603

22 7 6

TH

R2204

GND
1

U2200_FEEDBACK
D 4

27.4K

L2201
1.6UH

COMP
6

20%
2 6.3V
ELEC
8X11.5-TH

C2217

20%
25V
2 CERM
805

MIN_LINE_WIDTH=25MIL Q2202_DRAIN
MIN_NECK_WIDTH=10MIL

U2200_GATE_L

20%
2 6.3V
ELEC
8X11.5-TH

C2203
390UF

1UF

CASE369

1%
1/16W
MF
2 402

NTD60N02R

Q2201_GATE

5%
1/10W
FF
805

SOI
8

R2202
1

C2202
390UF

20%
6.3V
2 CERM
1206

U2200_VC_D

MBR0520L
SM

20%
2 25V
CERM
805

10UF

1UF

C2201

D2201

U2200_VC
1

D2202
MBR0520L

5%
1/10W
FF
2 805

U18
T11

4.7

U13

R2200

V15
U10

V12

MBR0520L
SM

6 7 22

VOLTAGE=1.2V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

D2200
1

c
.
s
it c

PPVCORE_NB

PP5V_PWRON

W14
W17

PP5V_PWRON

PP5V_PWRON

C2245
0.1UF

20%
10V
2 CERM
402

C2246
0.1UF

20%
10V
2 CERM
402

C2247
0.1UF

20%
10V
2 CERM
402

8
VOLTAGE

MIN_LINE_WIDTH

3.3V
3.3V
3.3V
2.5V
1.2V

7
25MIL
25MIL
25MIL
25MIL
100

MIN_NECK_WIDTH
10MIL
10MIL
10MIL
10MIL
15MIL

_PPPCI64_PWRON_SB
_PPPCI32_PWRON_SB
_PP3V3_PWRON_SB
_PP2V5_PWRON_SB
PP1V2_PWRON_SB_VCORE

7 23
7 23
7 23 25
7 23 25 74 88
TABLE_5_HEAD

3 6 10 23

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

m
o

TABLE_5_ITEM

343S0283

Page Notes
Power aliases required by this page:
- _PPPCI64_PWRON_SB (to 5V or 3.3V)
- _PPPCI32_PWRON_SB (to 5V or 3.3V)
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB
NOTE: PCI pads use the VIO supply to meet
different drive timing
characteristics required by the PCI
spec for 5V vs. 3.3V operation.
Connect _PPPCI32_PWRON_SB to
appropriate PCI bus voltage and
_PPPCI64_PWRON_SB to same if 64-bit
PCI, otherwise 3.3V.

23 10 6 3

U2300

PP1V2_PWRON_SB_VCORE

c
.
s
it c
1

C2350

VDDC
AA1

neoBorg Implementation

C2305
0.1uF

20%
2 10V
CERM
402

Master power enable signal (from PMU)

connects directly to SBVCORE supply
(SBVCORE_RUN). Supply asserts PGOOD
(SBVCORE_PGOOD) when ready, which acts as
the power enable signal for the rest of
the neoBorg components.

C2306
0.1uF

20%
2 10V
CERM
402

C2307
0.1uF

20%
10V
2 CERM
402

C2308
0.1uF

20%
2 10V
CERM
402

C2309

AB2

0.1uF

AB6
B1

20%
10V
2 CERM
402

B2
B5

C2310
0.1uF

20%
10V
2 CERM
402

C2311
0.1uF

20%
10V
2 CERM
402

C2312
0.1uF

20%
10V
2 CERM
402

C2313
0.1uF

20%
10V
2 CERM
402

SHASTA
V1.0
BGA
(1 OF 8)

VIO1

POWER

m
e
h
c
D1

C2314
0.1uF

20%
10V
2 CERM
402

F4
F8
H1
L7
M1
R2

U12
U9
V7
W4

20%
2 10V
CERM
402

C2330
0.1uF

20%
2 10V
CERM
402

0.1uF

20%
2 10V
CERM
402

C2331
0.1uF

20%
2 10V
CERM
402

20%
10V
2 CERM
402

.
w
w
w

C2336
0.1uF

20%
10V
2 CERM
402

C2324

s
p
to

20%
10V
2 CERM
402

C2327
0.1uF

20%
10V
2 CERM
402

C2332
0.1uF

20%
10V
2 CERM
402

p
la

C2335
0.1uF

C2326

C2323

C2337
0.1uF

20%
10V
2 CERM
402

0.1uF

20%
2 10V
CERM
402

C2328
0.1uF

20%
2 10V
CERM
402

C2333
0.1uF

20%
2 10V
CERM
402

C2338
0.1uF

20%
10V
2 CERM
402

0.1uF

20%
2 10V
CERM
402

C2329
0.1uF

20%
10V
2 CERM
402

C2334
0.1uF

20%
2 10V
CERM
402

C2339
0.1uF

20%
10V
2 CERM
402

A1
A2

mA
mA
mA
mA
mA

(1175
( 760
( 250
( 60
( 770

VIO2

Total:

A5
AA10

0.1uF

_PPPCI64_PWRON_SB

K21

C2355
0.1uF

L21

20%
10V
2 CERM
402

C2356
0.1uF

20%
2 10V
CERM
402

mW)
mW)
mW)
mW)
mW)

W22
Y19

For PCI_AD<63..32>

C
_PPPCI32_PWRON_SB

C2360
0.1uF

20%
10V
2 CERM
402

C2361
0.1uF

20%
10V
2 CERM
402

7 23

C2362
0.1uF

20%
10V
2 CERM
402

For PCI_AD<31..0>
W5
W19

_PP2V5_PWRON_SB

U13
U10

AA6

T12

AB1
AB22

R19
P9

C19
D2 GND
E22

C2357
0.1uF

U22

3015 mW

7 23

20%
2 10V
CERM
402

VDDP_KL V8

A22

7 23 25 74 88

C2365
0.1uF

20%
10V
2 CERM
402

P4
GND P14
P13

F3
F7

P12
P10

H2

N9

H9
J10

N22
N13

J11

N12

J13
J14

N11
N10

M2

J16
GND
L9

0.1uF

0.1uF

950
600
100
20
220

L14
L16

C2325

20%
2 10V
CERM
402

C2322

L13

0.1uF

1.2V
1.2V
2.5V
2.5V
3.3V

L11
L12

20%
2 10V
CERM
402

C2321

K7

0.1uF

K9
L10

C2320

K12
K13

DIGITAL
ANALOG12
VDDPs
I/O 2.5
I/O 3.3

K11

_PP3V3_PWRON_SB

C2351

20%
10V
2 CERM
402

H18
H17

Shasta max (est 06/30/03) current:

J22
K10

25 23 7

7 23 25 74 88

D19
VDDO25 G15

OMIT

U2300

AA3
AB10
1

_PP2V5_PWRON_SB

M13
M14

Must power Shasta VCore rail before any

other Shasta supplies.

M12

20%
2 10V
CERM
402

AA2

20%
10V
2 CERM
402

T15

0.1uF

R9
T10

0.1uF

20%
2 10V
CERM
402

C2304

R12

N8

0.1uF

20%
10V
2 CERM
402

C2303

P15
R10

L8
M15

0.1uF

20%
2 10V
CERM
402

C2302

M10
M11

Power Sequencing:

K8
L15

0.1uF

20%
2 10V
CERM
402

C2301

J15

H8
J12

Signal aliases required by this page:

- (NONE)

C2300

H15

0.1uF

IC,ASIC,SHASTA,V1.1,PBGA

VDDO33

DRAWING

TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Fri Nov 21 11:24:04 2003

PP1V2_HT

60 7

PP2V5_PWRON

R2400
100

U3LITE REQUIRES ALL JTAG SIGNALS

HIGH FOR NORMAL OPERATION

1%
1/16W
MF
2 402

NOSTUFF
1

C2401

NB_VSP_CLK_VREF
VOLTAGE=0.6V

1000PF

R2424 R2426 R2429 R2431 R2433 R2436

10K

10K

10K

10K

10K

10K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
25V
2 CERM
603

R2403
100

1%
1/16W
MF
2 402

20%
2 10V
CERM
402

121

121

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

PP3V3_PWRON

PBGA

27

JTAG_NB_TCK
JTAG_NB_TDI
JTAG_NB_TDO
JTAG_NB_TMS
JTAG_NB_TRST_L

10K

10K

10K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

SUSPENDACK*
SUSPENDREQ*

D20
D21

TP_NB_PM_SLEEP0

SYS_ISCA0 B21
SYS_ISCL1 C21
SYS_ISCA1 E21

D15 PM_SLEEP0

IRQ0 E9

NOSTUFF

R2435

5%
1/16W
MF
2 402
NB_PU_RESET

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

NB_PU_RST_L

6 NOSTUFF

24 13

SYS_COLD_RESET_L

SOT-363

13 8

p
la

B
R2406
0

5%
1/16W
MF
402

ELECTRICAL_CONSTRAINT_SET
I109
I110

SMU_RESET
SMU_RESET

NET_SPACING_TYPE
10 MIL SPACING
10 MIL SPACING

NB_THMI
NB_THMO

.
w
w
w
DIFFERENTIAL_PAIR

SYS_COLD_RESET_L
SYS_WARM_RESET_L

13 24

SMU_WARM_RESET_L

18
18
18
18

SMU_SUSPENDREQ_L

PP2V5_PWRON

R2422

6 NOSTUFF

3 NOSTUFF

NB_SUSPEND_REQ_L

Q2404
2N7002DW
5

R2408
0

5%
1/16W
MF
402

R2421

R2418

10K
5%

5%
1/16W
MF
2 402

100

5%
1/16W
MF
2 402

1/16W
MF
2 402
NB_SUSPEND_ACK

24

NB_SUSPENDACK_L

3 NOSTUFF

2N7002DW

SOT-363

Q2407

SOT-363

13

Q2409

SOT-363

24

Q2404
2N7002DW

SOT-363

4.7K

NB_RST_L

5%
1/16W
MF
2 402

100

5%
1/16W
MF
2 402
PMU_SUSPEND_REQ

PP3V3_PWRON

NOSTUFF
1

Q2409
2N7002DW

18

c
.
s
it c
25 13

18

25

5%
1/16W
MF
2 402
NB_RESET

24

6 NOSTUFF

Q2412
2N7002DW

SOT-363

24

3 NOSTUFF

Q2412
2N7002DW

10K

24

NB_PMR_OBSV

R2423

4.7K

24

NB_INT_L

NOSTUFF
1

24

m
e
h
c

s
p
to
PP3V3_PWRON

NOSTUFF

10K

TP_DUMMY_A
TP_DUMMY_B

THMI J17
THMO J18

PP2V5_PWRON

4.7K

I2C_NB_A_SCL
I2C_NB_A_SDA
I2C_NB_B_SCL
I2C_NB_B_SDA
I2C_NB_C_SCL
I2C_NB_C_SDA

PMR_OBSV Y9

PP3V3_PWRON

R2405 1R2438

NB_RST_L
NB_PU_RST_L
NB_SUSPEND_ACK_L
NB_SUSPEND_REQ_L

DUMMY_A AC28
DUMMY_B AB28

E20

API0_ISCL A20
API_ISCA B20
SYS_ISCL0 C20

AH3 CEO_TEST
AD5 CE0_MC
AD3 CE0_RE
6

R2444 1R2443 1R2442

A21

M26 CE1_DI1_TMS
F20 CE1_DI2_TRST
AC2 CE1_RI

NB_TEST_PD
NB_MC_PD
NB_RE_PD
1

HRESET*
PURESET*

OMIT

R25 CE1_LT_TCK
V25 CE1_A_TDI
AA25 CE1_B_TDO

JTAG_NB_TCK
JTAG_NB_TDI
JTAG_NB_TDO
JTAG_NB_TMS
JTAG_NB_TRST_L
NB_RI_PU

R2419

10K

(SYM 7 OF 7)

P4 VSP_CLKP
R4 VSP_CLKN

NOSTUFF
1

R2420

U3

VSP_NB_CLK_P
VSP_NB_CLK_N

PP2V5_PWRON

NOSTUFF
1

U3LITE
V1.0-300MM
27

m
o

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2400 1R2402 1R2401

0.1UF

Q2408

24

2N7002

SI2302DS

NB_SUSPEND_ACK_L 1

SM

SM

R2407
1

NOSTUFF

R2409

5%
1/16W
MF
402

5%
1/16W
MF
402

8 25 74 77 87

I2S1_TO_SB
I2S1_TO_DEV
I2S1_TO_DEV
I2S1_BIDIR
I2S1_BIDIR

I2S1_DEV_TO_SB_DTI
I2S1_SB_TO_DEV_DTO
I2S1_MCLK
I2S1_BITCLK
I2S1_SYNC
I2S2_DEV_TO_SB_DTI
I2S2_SB_TO_DEV_DTO
I2S2_MCLK
I2S2_BITCLK
I2S2_SYNC

I2S2_TO_SB
I2S2_TO_DEV
I2S2_TO_DEV
I2S2_BIDIR
I2S2_BIDIR

SB_CLK18M_XTALI
SB_CLK18M_XTALO
SB_CLK18M_XTALO_R
SB_CLK25M_ATA

SPACING
SPACING
SPACING
SPACING

25 13

25 95

6 25 76 94
6 25 94
6 25 94

PP1V2_PWRON_SB_PLL45VDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

6 25 94

25 99
25 99

25 99

25
25

L2500

25
25 27

88 74 23 7

_PP2V5_PWRON_SB

PP2V5_PWRON_SB_XTAL18VDD
VOLTAGE=2.5V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

FERR-EMI-600-OHM
2

C2500

20%
6.3V
2 CERM
1206

Power aliases required by this page:

- _PP3V3_PCI
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB
- _PP1V2_PWRON_SB

PP1V2_PWRON_SB_PLL49VDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

C2501

L2510

0.001uF

C2531

SM

C2510
10uF

20%
6.3V
2 CERM
1206

m
e
h
c

C2511

0.001uF

10%
50V
2 CERM
402

XTAL
VDD

XTAL_18 PLL_45 PLL_49

VDD
VDD
VDD

SM
2

99 25
99 25
99 25
99 25
99

MPIC_SB

From SouthBridge <SB_INT_L

25

(I2S1_RESET_L)

I2S2_DEV_TO_SB_DTI
I2S2_SB_TO_DEV_DTO
I2S2_MCLK
I2S2_BITCLK
I2S2_SYNC
I2S2_RESET_L
AUDIO GPIO - see note

4
3
2
1

RP2530

25 23 7

p
la

18

18

4.7K

R2551
1

10K

5%
1/16W
MF
402

.
w
w
w

10K

10K

5%
1/16W
MF
402

R2556

R2557

5%
1/16W
MF
402

10K

5%
1/16W
MF
402

10K

PCI_SLOTA_INT_L

PCI_SLOTD_INT_L

25

25

6 25 76

25

R2558
1

R2559
1

10K

PCI_SLOTF_REQ_L

PCI_SLOTF_GNT_L

5%
1/16W
MF
402

25

R2552

R2553
1

PCI_SLOTE_GNT_L

(Internal pull-up)

25

10K

5%
1/16W
MF
402

PCI_SLOTE_INT_L

25

PCI_SLOTG_INT_L

25 77

5%
1/16W
MF
402

87 77 74 24 8
13

24 13
13

PCI_64BIT

77 13

R25011

1 = 32-bit PCI & GPIOs

0 = 64-bit PCI & XGC

PCI_SLOTE_REQ_L

(I2S2_RESET_L)

on right

NO STUFF

R2550
2

_PP3V3_PWRON_SB

PCI 32-bit select

5%
1/16W
MF
402

R25001

7 74 75 76 77

10K

33
5%
1/16W
SM1

4.7K

5%
1/16W
MF
402 2

8
8
8
8
8

R2580

4.7K

5%
1/16W
MF
402 2

25
25

27 25

I2S0

AA5 I2S2DTI_H
Y8 I2S2DTO_H
Y7 I2S2MCLK_H

AB4 I2S2BITCLK_H
W9 I2S2SYNC_H
Y2 GPIO_H_1

SB_INT_L
MODEM_RING2SYS_L
SB_PCI_SEL32BIT

AB3 GPIO_H_2
W8 GPIO_H_3
W6 PCI_SEL32BIT_H

I2C_SB_SCL
I2C_SB_SDA

Y9 I2CCLK_H
AB7 I2CDATA_H

SYS_WARM_RESET_L
SB_STOPXTALS_L
SMU_SUSPENDREQ_L
SB_SUSPENDACK_L
SYS_PME_L
TP_SB_WATCHDOG
JTAG_SB_TDI
JTAG_SB_TDO
JTAG_SB_TCK
JTAG_SB_TMS
JTAG_SB_TRST_L

SB_TEST_MODE_PD
TP_SB_PLLTEST
TP_SB_FSTEST
SB_CLK18M_XTALI
SB_CLK18M_XTALO_R
SB_CLK25M_ATA

R2590

I2S1

(SCCA)

V5 GPIO_H_0

(I2S2_DEV_TO_SB_DTI)
I2S2_SB_TO_DEV_DTO_R
I2S2_MCLK_R
I2S2_BITCLK_R
I2S2_SYNC_R

5%
1/16W
MF
402 2

94 25 6

5%
1/16W
MF
402

_PP3V3_PCI

25

R2578
1

s
p
to
8

33
5%
1/16W
SM1

E9
W10

RESET_L

U11

STOPXTALS_L
SUSPENDREQ_L

V11
W18

SUSPENDACK_L

V12

PCI

2N3904

99 25

RP2520

I2S2

94 25 6

(SCCB)

94 25 6

GPIO

94 25 6

PCI1PME_L
INTRWD_H

AA11 TDI
W11 TDO
AB11 TCK
Y11 TMS
W12 TRST_L
A3 TEST_MODE_H
U14 PLLTEST
V14 FSTEST
W13 XTAL_18_I
V13 XTAL_18_O
U15 XTALI
NC V15 XTALO

200
CRITICAL

Y2590

18.432M
1

C2590 1
22pF

5%
50V
CERM 2
402

1%
1/16W
MF
2 402
SB_CLK18M_XTALO

25

XGI

94 25 6

(I2S1_DEV_TO_SB_DTI)
I2S1_SB_TO_DEV_DTO_R
I2S1_MCLK_R
I2S1_BITCLK_R
I2S1_SYNC_R

I2C

Q2576

94 76 25 6

I2S1_DEV_TO_SB_DTI
I2S1_SB_TO_DEV_DTO
I2S1_MCLK
I2S1_BITCLK
I2S1_SYNC
I2S1_RESET_L

V10 I2S1DTI_H
AB5 I2S1DTO_H
V9 I2S1MCLK_H
AA8 I2S1BITCLK_H
AA7 I2S1SYNC_H

PWR_MGT

R2579

29 14
30

MPIC_SB
NB_INT_L_R

94 76 25 6

U8 I2S0MCLK_H
AA4 I2S0BITCLK_H
Y6 I2S0SYNC_H

TEST

<- To CPU
CPU_INT_L

5%
1/16W
MF
402

MPIC_NB

5%
1/16W
MF
402 2

95 25

V1.0 GPIO

BGA
(2 OF 8)

XTALS

95 25

8X4.5MM-SM
1

C2591
22pF

5%
50V
2 CERM
402

OMIT

SHASTA

W7 I2S0DTI_H
Y5 I2S0DTO_H

XTAL_18
GND

PLL_45
GND
AB13

24

10K

95 25

I2S2: S/P-DIF

MPIC_SB

R2575

95 25

Re-pin within each RPAK as necessary

DO NOT swap between RPAKs
I2S0_DEV_TO_SB_DTI
(I2S0_DEV_TO_SB_DTI)
4
5
I2S0_SB_TO_DEV_DTO
I2S0_SB_TO_DEV_DTO_R
RP2510 6
3
I2S0_MCLK
I2S0_MCLK_R
33
5%
1
8
I2S0_BITCLK
I2S0_BITCLK_R
1/16W
SM1
2
7
I2S0_SYNC
I2S0_SYNC_R

AB12

I2S1: Soft Modem

I2S0: Audio DAC

To SouthBridge ->
NB_TO_SB_INT 25

95 25

PP2V5_PWRON_SB_XTALVDD
VOLTAGE=2.5V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

U2300

-> From NorthBridge

NB_INT_L

C2530

0.001uF

W17

BOM options provided by this page:

- PCI_64BIT
Configures Shasta for 64-bit PCI
NOTE: XGC required for Shasta GPIOs

L2530

FERR-EMI-600-OHM
1

VIO
PME

6
7

PCI1REQ_3_L

8
9

PCI1REQ_4_L

PCI1GNT_3_L

PCI1GNT_4_L

20%
6.3V
CERM 2
1206

_PP3V3_PWRON_SB

36 27 25 16 13

SYS_OVERTEMP_L

94 25 6

UDASH_RESET_L

33 27 25 13

SYS_SLEWING_L

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

PCI1AD_32_H D18
PCI1AD_33_H A20
PCI1AD_34_H F18

Y20

94 25 6

PCI1AD_38_H A21
PCI1AD_39_H B21
PCI1AD_40_H C20
PCI1AD_41_H G17
PCI1AD_42_H G18
PCI1AD_43_H E19
PCI1AD_44_H F19
PCI1AD_45_H D20
PCI1AD_46_H E20
PCI1AD_47_H C21
PCI1AD_48_H F20
PCI1AD_49_H G19
PCI1AD_50_H C22
PCI1AD_51_H D21
PCI1AD_52_H G20
PCI1AD_53_H D22
PCI1AD_54_H K18
PCI1AD_55_H H19
PCI1AD_56_H J17
PCI1AD_57_H F21
PCI1AD_58_H G21
PCI1AD_59_H H20
PCI1AD_60_H J19
PCI1AD_61_H F22
PCI1AD_62_H G22
PCI1AD_63_H H21
J20
H22

44
45
46
47

PCI1C_BE_4_L

PCI1C_BE_7_L

K20

48
49
50

PCI1REQ64_L
PCI1ACK64_L

K17
L17

PCI1PAR64_H

E18

K22

XGI_CLK_H Y4
XGI_DTO0_H U7
XGI_DTO1_H T9
XGI_DTI_H W2

1K

1K

25

REDUNDANT - NEED TO ADDRESS THIS

90 25

FW_LOWPWR

87 25

87 25

ENET_ENERGYDET

I2S0_RESET_L
SB_GPIO45
SB_GPIO46
SB_GPIO47

13 16 25 27 36
25

SB_GPIO12

PCI_SLOTC_INT_L

49

10K

25

25

SB_GPIO23

25

25
25

R2565
1

10K

10K

_PP3V3_PWRON_SB

10K

RP2550
2

25

SB_GPIO25

25
25

25

25

SB_GPIO45

5%
1/16W
SM1

10K

25

SB_GPIO46

25

SB_GPIO47

25

SB_GPIO49

25 87

25 87

RP2550

5%
1/16W
SM1

10K

10K

10K

25

25

25 13

SB_GPIO50

SMU_TO_SB_INT_L

10K

5%
1/16W
SM1

RP2552
4

10K

5%
1/16W
SM1

RP2553

RP2553

5%
1/16W
SM1

10K

5%
1/16W
SM1

5%
1/16W
SM1

SB_GPIO51

SB_GPIO52

10K

RP2552

5%
1/16W
SM1

10K

5%
1/16W
SM1

5%
1/16W
SM1

10K

RP2551

5%
1/16W
SM1

RP2553
25

RP2551

RP2552

25

10K

5%
1/16W
SM1

25 77
25 90

5%
1/16W
SM1

RP2552

25

10K

RP2551

SB_GPIO30

25

10K

10K

RP2553
1

10K

5%
1/16W
SM1

25
25

SYS_SLEWING_L
SB_GPIO49
SB_GPIO50

13 25 27 33
25
25

SB_GPIO51
SB_GPIO52
NB_TO_SB_INT
SMU_TO_SB_INT_L

25
25
25
13 25

PLL_49
GND

LAST_MODIFIED=Fri Nov 21 11:24:05 2003

10K

DRAWING

5%
1/16W
MF
402

TITLE=FIZZY
ABBREV=DRAWING

10K

RP2551

25

25

NO STUFF

5%
1/16W
SM1

SB_GPIO24

25

95

5%
1/16W
SM1

6 25 76

98

R2568

PCI_SLOTF_INT_L

6 25 94

99

10K

5%
1/16W
MF
402

PCI_SLOTB_INT_L

6 94

99

R2567

25

97

R2563

RP2550

25 29 30

99

5%
1/16W
MF
402

RP2550

13 25

96

5%
1/16W
MF
402

25

99

10K

5%
1/16W
MF
402

ENETFW_RESET

25

99

R2566

25

99

R2561

5%
1/16W
MF
402

SB_SATABR_RESET_L

25

98

5%
1/16W
MF
402

25 23 7

6 98

5%
1/16W
MF
402

R2564
I2S1_RESET_L

25

98

10K

5%
1/16W
MF
402

25

PCI1AD_35_H F17
PCI1AD_36_H G16
PCI1AD_37_H F16

MODEM_RING2SYS_L

C2540

SB_GPIO12
SYS_OVERTEMP_L
UDASH_SDOWN
UDASH_RESET_L
AGP_INT_L
PCI_SLOTA_INT_L
PCI_SLOTB_INT_L
PCI_SLOTC_INT_L
PCI_SLOTD_INT_L
PCI_SLOTE_INT_L
PCI_SLOTF_INT_L
SB_GPIO23
SB_GPIO24
SB_GPIO25
SB_SATABR_RESET_L
PCI_SLOTG_INT_L
FW_LOWPWR
ENETFW_RESET
SB_GPIO30
ENET_ENERGYDET
AUDIO_LO_DET_L
AUDIO_LO_METAL_PLUG_L
AUDIO_LI_DET_L
AUDIO_LI_METAL_PLUG_L
AUDIO_HP_DET_L
AUDIO_SPKR_DET_L
AUDIO_LO_MUTE_L
AUDIO_HP_MUTE_L
AUDIO_SPKR_MUTE_L
AUDIO_EXT_MCLK_SEL
AUDIO_GPIO_11
AUDIO_GPIO_12

5%
1/16W
MF
402

7 23 25

SB_TO_SMU_INT_L
CPU_SRESET_L

R2555

R2562

94 25 6

20%
10V
2 CERM
402

NO STUFF

NO STUFF

25

U16

REDUNDANT - NEED TO ADDRESS THIS

0.1uF

R2560

10uF

"Slot E" - AD21

PCI_SLOTE_REQ_L
AA19 PCI_SLOTE_GNT_L
"Slot F" - AD22
AB21 PCI_SLOTF_REQ_L
AA20 PCI_SLOTF_GNT_L

PCI1REQ_5_L
PCI1GNT_5_L

51
52
53
54

CPU_SRESET_L

U17

10
11

PCI1C_BE_5_L
PCI1C_BE_6_L

30 29 25

1K

5%
1/16W
MF
402

AA12

FERR-EMI-600-OHM

5%
1/16W
MF
2 402

SM

10%
50V
2 CERM
402

Y12

Signal aliases required by this page:

(NONE)

20%
6.3V 2
CERM
1206

10%
50V
CERM 2
402

10K

10uF

10%
50V
CERM 2
402

10uF

R2576

_PP1V2_PWRON_SB

c
.
s
it c
C2520

0.001uF

25 99

Page Notes

L2520

FERR-EMI-600-OHM
SM

C2521

25 99

PP3V3_RUN

m
o

6 25 76 94

SM

NorthBridge / SouthBridge MPIC Routing

SB_TO_SMU_INT_L

25 95

_PP3V3_PWRON_SB

R2554

AA13

SB_CLK25M_ATA

MIL
MIL
MIL
MIL

25 23 7

25 95

Y13

15
15
15
15

25 95

25 95

AUDIO GPIOS

I2S0_DEV_TO_SB_DTI
I2S0_SB_TO_DEV_DTO
I2S0_MCLK
I2S0_BITCLK
I2S0_SYNC

SB_CLK18M_XTAL

DIFFERENTIAL_PAIR

I2S0_TO_SB
I2S0_TO_DEV
I2S0_TO_DEV
I2S0_BIDIR
I2S0_BIDIR

NOTE: It is the responsibility of

the audio circuit to provide the
necessary pull-ups & pull-downs.

NET_SPACING_TYPE

W14

ELECTRICAL_CONSTRAINT_SET

7
L2601

26 7

26 7

FERR-250-OHM

PPVCORE_PWRON_PULSAR

SYM 2 OF 2

PPVCORE_PWRON_PULSAR
F1 C1_VDD
L3 C2_VDD
E12 C3_VDD

2
SM

5%
1/16W
MF

C2645
2.2UF

402
C2611

10%
6.3V
2 CERM1
603

0.1UF
20%

10V
2 CERM
402

0.1UF

FERR-250-OHM
SM

5%
1/16W
MF
402

C2669

PP1V5_PSL_PLL2
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
1
MIN_NECK_WIDTH=10MIL

C2617

C2613

10%
6.3V
2 CERM1
603

0.1UF

20%
2 10V
CERM
402

26 7

0.1UF
20%

2.2UF

10V
2 CERM
402

26 7

PLACE NEAR PIN D2 D1

L2605
FERR-250-OHM
1

26 7

2
SM

R2603
4.7
1

PP1V5_PSL_PLL3

5%
1/16W
MF
402

C2603
2.2UF

C2615

10%
6.3V
2 CERM1
603

0.1UF
20%

10V
2 CERM
402

L2607 PLACE

m
e
h
c

VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2601
0.1UF

20%
10V
2 CERM
402

NEAR PIN L8 K8

FERR-250-OHM
1

PP3V3_PWRON

SM

R2605
4.7
1

PP1V5_PSL_PLL4

5%
1/16W
MF
402

C2607

C2619

10%
6.3V
2 CERM1
603

0.1UF

L2609 PLACE

VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2605
0.1UF
20%

2.2UF

20%
10V
2 CERM
402

PP3V3_PWRON

10V
2 CERM
402

NEAR PIN M3 M2

FERR-250-OHM
1

2
SM

R2607
4.7
1

5%
1/16W
MF
402

PP3V3_PSL_XTAL
1

C2621
2.2UF

C2620

10%
6.3V
2 CERM1
603

0.1UF
20%

10V
2 CERM
402

C2622
0.1UF
20%

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

p
la

10V
2 CERM
402

IF 603 CAN BE PLACED CLOSE TO PULSAR

PART#

QTY
1

DESCRIPTION
PULSAR, PBGA

.
w
w
w
REFERENCE DESIGNATOR(S)

s
p
to

2 10V
CERM
402

37 26 7

26 7

PPVCORE_PULSAR

PP1V2_PULSAR

B2 VDD_I2C
G12 VDD_NBSYNC
M12 VDD_PCLK

VSS_PLL4 M2

VSS_CML A6
VSS_I2C C2
VSS_NBSYNC F11
VSS_PCLK L12

H3 VDD25
K1 VDD25

E1 VDD33
L5 VDD33_BC
M9 VDD33_BC1

VSS25 L2
VSS25 H2
VSS33 E2
VSS33_BC L7
VSS33_BC1 M5

A11 VDD_HCLK0
A9 VDD_HCLK0
A8 VDD_HCLK1
C5 VDD_HCLK2
B4 VDD_HCLK2

VSS_HCLK0 C10
VSS_HCLK0 B11

K10 VDD_HSYNC
H12 VDD_HSYNC

VSS_HSYNC H10
VSS_HSYNC K12

VSS_HCLK1 B7
VSS_HCLK2 A4
VSS_HCLK2 A7

PPVCORE_PULSAR

J11 VDD15_HSYNC
M11 VDD15_PCLK
A1 VDD_VCLK
A12 VDD_XTAL

VSS_VCLK A3
VSS_XTAL C12

PINS G12, M12, H3, K1, L5, M9, A11, A9

A8, C5, B4, K10, H12 J11, M11, A1
CAN BE TURNED OFF IN SLEEP

PP3V3_RUN

C2665 1 C2667
0.1UF
20%

0.1UF
20%

C2651 1 C2671
0.1UF

20%
10V
2 CERM
402

10V
2 CERM
402

0.1UF

20%
2 10V
CERM
402

PP2V5_RAM

C2639
0.1UF
20%

2 10V
CERM

402

26 7

402 CAPS NOT NEEDED

359S0076

PP2V5_RAM

PP3V3_PWRON
PP3V3_RUN

R2609
1

PP1V2_PULSAR

c
.
s
it c

37 26 7

4.7 2

C4_VSS C9
VSS_PLL1 D12
VSS_PLL2 D1
VSS_PLL3 K8

M3 VDD_PLL4

PP3V3_PWRON

PLACE NEAR PIN D10 D12

FSBGA

m
o

C2609

20%
10V
2 CERM
402

C1_VSS G1
C2_VSS M4
C3_VSS E10

PULSAR

D10 VDD_PLL1
D2 VDD_PLL2
L8 VDD_PLL3

PP1V5_PSL_PLL1
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

26 7

L2603

OMIT

U2600

B9 C4_VDD

R2601
4.7

C2640
0.1UF
20%

2 10V
CERM

402

PPVCORE_PULSAR
1

C2631 1 C2632 1 C2633 1 C2634 1 C2635 1 C2636 1 C2637 1 C2638

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
10V
2 CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
10V
2 CERM
402

0.1UF

20%
10V
2 CERM
402

0.1UF

20%
2 10V
CERM
402

PPVCORE_PWRON_PULSAR
1

C2627 1 C2628 1 C2629 1 C2630

0.1UF

20%
2 10V
CERM
402

26 7

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
10V
2 CERM
402

0.1UF

20%
2 10V
CERM
402

PP1V2_PULSAR

C2623 1 C2624 1 C2625 1 C2626

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
10V
2 CERM
402

0.1UF

20%
2 10V
CERM
402

TABLE_5_HEAD

BOM OPTION

TABLE_5_ITEM

U2600

7
ELECTRICAL_CONSTRAINT_SET

29 27
29 27
14
14
28 27
28 27
29 27
28 27

14

27 24
27 24

48 27
49 27

60 27
62 27

EI_CPU_CLK_P
EI_CPU_CLK_N
EI_CPU1_CLK_P
EI_CPU1_CLK_N
EI_NB_CLK_P
EI_NB_CLK_N
EI_CPU_SYNC
EI_NB_SYNC
EI_CPU1_SYNC

EI_CPU_CLK
EI_CPU_CLK
EI_CPU1_CLK
EI_CPU1_CLK
EI_NB_CLK
EI_NB_CLK
EI_SYNC

NET_PHYSICAL_TYPE

NET_SPACING_TYPE

DIFFERENTIAL_PAIR
EI_CPU_CLK
EI_CPU_CLK
EI_CPU1_CLK
EI_CPU1_CLK
EI_NB_CLK
EI_NB_CLK

EI_CPU1_SYNC

CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS

VSP_NB_CLK_P
VSP_NB_CLK_N

VSP_NB_CLK
VSP_NB_CLK

CLOCKS
CLOCKS

VSP_NB_CLK
VSP_NB_CLK

AGP_CLK66M_NB
AGP_CLK66M_GPU

AGP_NB_CLK
AGP_GPU_CLK

CLOCKS
CLOCKS

HT_CLK66M_NB
HT_CLK66M_SB

HT_NB_CLK
HT_SB_CLK

CLOCKS
CLOCKS

PCI_CLK66M_SB_INT
PCI_CLK33M_SB_EXT

CLOCKS_PCI
CLOCKS_PCI

CLOCKS
CLOCKS

R2701
5%

I86
I87

74 8

27

PLS_EXTCLK

PLS_XTAL

I117

m
o
1

I97

5% 402

I98
I99

I95

I102
I103

I90
I91

I119

DIFFERENTIAL SIGNALS SHOULD HAVE 5 MIL SPACING TO EACH OTHER

ALL SPACING GROUPS SHOULD HAVE 15 MIL SPACING TO SIGNALS NOT IN THEIR GROUP

NET
SPACING
TYPE

EI_NB_SYNC IS PART OF EI_CPU_SYNC TOPOLOGY

SYM 1 OF 2
GPCLK33_0 L4
GPCLK33_1 K4

OMIT

U2600

PULSAR
FSBGA
18

I2C_CLOCK_SCL

C1 SCLK

18

I2C_CLOCK_SDA

B1 SDATA

PLS_RESET_L

D3

PLS_X_IN

C11 XIN

PLS_X_OUT

B12 XOUT

RESET*

5% 402

NOSTUFF
R2738
1K

0=IIC ADDR D2/D3

5% 402

1=IIC ADDR D4/D5

6
6
6

TP_PLS_TEST1
TP_PLS_TEST2
TP_PLS_TEST3

PCI_CLK_GP0_R
PCI_CLK_GP1_R

CLOCKS
CLOCKS

VSP_NB_CLK_N_C
VSP_NB_CLK_P_C

CLOCKS
CLOCKS

EI_CPU_CLK_N_C
EI_CPU1_CLK_N_R
EI_NB_CLK_N_C
EI_CPU_CLK_P_C
EI_CPU1_CLK_P_R
EI_NB_CLK_P_C

CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS

GPCLK25_0 J3
GPCLK25_1 J1

PLS_CLK_66M_0_R
PLS_CLK_66M_1_R

CLOCKS
CLOCKS

PCLK25_0 K2
PCLK25_1 L1

HT_CLK66M_NB_R
RAM_CLK66M_NB_R

CLOCKS
CLOCKS

m
e
h
c

VCLKN A2
VCLKP B3

HCLKN_0 B10
HCLKN_1 C8
HCLKN_2 C4
HCLKP_0 A10
HCLKP_1 B8
HCLKP_2 B5

s
p
to

PLS_X_ADDRSEL

E3 ADDRSEL

K3 TEST1
E11 TEST2
D11 TEST3

PCLK33_0 K5
PCLK33_1 L6
PCLK33_2 M7
PCLK33_3 L9

PCLK33_4 M10

R2706 249
18 11 6

PP3V3_PWRON

R2722

PLS_SCAN_MODE

1%

402 1%
2 402 1%
2 402 1%

R2744 681 1
R2740 1K 1
R2746 1K 1

402

PLS_REF15
PLS_REF25
PLS_REF33

1K

5%
1/16W
MF
2 402

NOSTUFF

R2748

SYS_OVERTEMP_L

36 25 16 13

R2742

806 1

SYS_SLEEP
(SLEEP)

NO STUFF

NOSTUFF

J2700

U.FL-R_SMT
F-ST-SM
3

PLS_EXTCLK
NOSTUFF
1

27

24

1
2

NOSTUFF
1

NO STUFF

R2758
1

330K2
5%
1/16W
MF
402

R2764
24

5%
1/16W
MF
2 402

CRITICAL

Y2701

25.0000M
1

PLS_X_IN_B

R2724 1K

NOSTUFF
2

R2754
0
1

5%
1/16W
MF
402

R2756
0
1

5%
1/16W
MF
402

402 5%

402 5%

c
.
s
it c

PLS_PRES_CML

B6 PRES_CML

F2

FORCESPO*

HTBEN_0 K11
HTBEN_1 J12
NBSYNC F12

HSYNC_0 J10
HSYNC_1 H11

REFCLK_0 G2
REFLCK_1 H1
SLEWING*
ERROR*

C3 PD

K9
M8

PCLK12 L11
PCLK15 L10

PCI_CLK66M_SB_INT_R
PCI_CLK_P1_R
AGP_CLK66M_GPU_R
PCI_CLK_P3_R
PCI_CLK_P4_R

CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS

CPU_HTBEN_R
CPU1_HTBEN_R

CLOCKS
CLOCKS

EI_NB_SYNC_R

CLOCKS

EI_CPU_SYNC_R
EI_CPU1_SYNC_R

CLOCKS
CLOCKS

SB_CLK25M_ATA_R
SATA_CLK25M_R

CLOCKS
CLOCKS

SLEWING_L_R
CLOCK_ERROR_L

14

VSP_NB_CLK_P
VSP_NB_CLK_N

C2710
1

10%

402

0.001UF
1

10%

2 CERM
402

EI_CPU_CLK_P
EI_CPU_CLK_N

C2715

0.001UF
10%

2 CERM

C2700
0.001UF
2 CERM
402

EI_NB_CLK_P
EI_NB_CLK_N

C2702

0.001UF
50V 1
10%
2

5% 402

5% 402
20 R2709
2

5% 402

0 R2711
1

5% 402

0 R2702
1

5% 402

0 R2779
1

TP_PLS_CLK_66M_0
TP_PLS_CLK_66M_1

2.5V
2.5V

66MHZ
66MHZ

HT_CLK66M_NB
RAM_CLK66M_NB

3.3V
3.3V
3.3V
3.3V

66MHZ
33MHZ
66MHZ
33MHZ

PCI_CLK66M_SB_INT
PCI_CLK_P1
AGP_CLK66M_GPU
PCI_CLK_P3
PCI_CLK_P4

1.2V

66MHZ

CPU_HTBEN

29 30

1.2V

EI_NB_SYNC

27 28

1.2V

EI_CPU_SYNC

27 29

5% 402

0 R2715
1

66MHZ
66MHZ

0 R2705

0 R2707
5% 402

5% 402

2
1

2.5V
2.5V
20 R2703
1

5% 402

0 R2768
1
1

5% 402

27 60
37

27 74
8
27 49
8
8

5% 402

14

20 R2770
NOSTUFF
22 R2700
1

0 R2720
1

SYS_SLEWING_L

5% 402

2.5V
2.5V

25MHZ
25MHZ

SB_CLK25M_ATA
TP_SATA_CLK25M

1.2V
1.5V

66MHZ
66MHZ

HT_CLK66M_SB
AGP_CLK66M_NB

25

5% 402
13 25 33

5% 402

HT_CLK66M_SB_R
AGP_CLK66M_NB_R

5% 402

14

0 R2772

CLOCKS

27 28

402

0 R2776
1

27 28

2 CERM

0 R2775

27 29
27 29

402

10%

24 27

2 CERM

C2713

50V 1

14

24 27

0 R2717

CLOCKS
CLOCKS

5% 402

0 R2719
1

27 62
27 48

5% 402

PLS_POWER_DOWN

PLS_X_OUT_B

8X4.5MM-SM

C2707 1

33PF
5%

C2705
33PF
5%

50V
CERM 2
402

5%
1/16W
MF
402

R2762

5%
1/16W
MF
2 402
PLS_INTERM

.
w
w
w

R2752
1

R2750 0

G11 REF15
J2 REF25
M6 REF33

A5 REF_CML

p
la

5%
1/16W
MF
402

50 46 11 10 9 8 6

402 1%

M1 SCAN_MODE

TP_PLS_REF_CML

PLS_FORCE_P0_L_R

PCI_CLK_GP1

402

0.001UF

50V 1

33MHZ

2 CERM

10%

50V

I101

3.3V

PCI_CLK_GP0

0.001UF

50V 1
I94

I100

CLOCK_RESET_L

33MHZ

C2708

I118

R2704
0

3.3V
R2761
0

I96

CLOCKS

13

I116

50V

74 27

50V
2 CERM
402

ELECTRICAL_CONSTRAINT_SET
29 28 14
29 28 14
29 28 14
29 28 14

29 28 14

R2800

29 28 14

PP1V5_PWRON_EI_NB_AVDD
VOLTAGE=1.5V

29 28 14

29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14

29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14
29 28 14

29 28 14
29 28 14
29 28 14

PLACE R2805 AND R2806

NEAR U3LITE

29 28 14

29 14

0.1UF

20%
10V
2 CERM
402

29 28 14

EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_CLK_N

F15 API0_BCLKIP
E15 API0_BCLKIN

EI_NB_TO_CPU_AD<0>
EI_NB_TO_CPU_AD<1>
EI_NB_TO_CPU_AD<2>
EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_AD<4>
EI_NB_TO_CPU_AD<5>
EI_NB_TO_CPU_AD<6>
EI_NB_TO_CPU_AD<7>
EI_NB_TO_CPU_AD<8>
EI_NB_TO_CPU_AD<9>
EI_NB_TO_CPU_AD<10>
EI_NB_TO_CPU_AD<11>
EI_NB_TO_CPU_AD<12>
EI_NB_TO_CPU_AD<13>
EI_NB_TO_CPU_AD<14>
EI_NB_TO_CPU_AD<15>
EI_NB_TO_CPU_AD<16>
EI_NB_TO_CPU_AD<17>
EI_NB_TO_CPU_AD<18>
EI_NB_TO_CPU_AD<19>
EI_NB_TO_CPU_AD<20>
EI_NB_TO_CPU_AD<21>
EI_NB_TO_CPU_AD<22>
EI_NB_TO_CPU_AD<23>
EI_NB_TO_CPU_AD<24>
EI_NB_TO_CPU_AD<25>
EI_NB_TO_CPU_AD<26>
EI_NB_TO_CPU_AD<27>
EI_NB_TO_CPU_AD<28>
EI_NB_TO_CPU_AD<29>
EI_NB_TO_CPU_AD<30>
EI_NB_TO_CPU_AD<31>
EI_NB_TO_CPU_AD<32>
EI_NB_TO_CPU_AD<33>
EI_NB_TO_CPU_AD<34>
EI_NB_TO_CPU_AD<35>
EI_NB_TO_CPU_AD<36>
EI_NB_TO_CPU_AD<37>
EI_NB_TO_CPU_AD<38>
EI_NB_TO_CPU_AD<39>
EI_NB_TO_CPU_AD<40>
EI_NB_TO_CPU_AD<41>
EI_NB_TO_CPU_AD<42>
EI_NB_TO_CPU_AD<43>

F11 API0_ADI0
F12 API0_ADI1

EI_NB_SYNC

C2800
0.1UF

20%
10V
2 CERM
402

API0_ADO20 H6
API0_ADO21 J7
API0_ADO22 F3

E12 API0_ADI23
A13 API0_ADI24
A14 API0_ADI25

API0_ADO23 J8
API0_ADO24 F6
API0_ADO25 E5

B14 API0_ADI26
C14 API0_ADI27
A16 API0_ADI28
A15 API0_ADI29
B15 API0_ADI30

API0_ADO26 D5
API0_ADO27 E4

C15 API0_ADI31
H15 API0_ADI32
G15 API0_ADI33

API0_ADO31 C3
API0_ADO32 C5
API0_ADO33 C6

F17 API0_ADI34
G17 API0_ADI35
G18 API0_ADI36

API0_ADO34 B2
API0_ADO35 D1
API0_ADO36 B1

H18 API0_ADI37
F18 API0_ADI38
E18 API0_ADI39
A17 API0_ADI40
A18 API0_ADI41

API0_ADO37 C1
API0_ADO38 A6

B17 API0_ADI42
C17 API0_ADI43

API0_ADO42 A7
API0_ADO43 B8

EI_NB_TO_CPU_SR_P<0>
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_SR_N<1>

D17 API0_SRIP0
A19 API0_SRIN0
E17 API0_SRIP1
B18 API0_SRIN1

API0_SROP0 A3
API0_SRON0 A4
API0_SROP1 B5
API0_SRON1 B6

EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_N<1>

EI_QACK_L

D14 API_QACK0

NB_APSYNC

API0_ADO6 J4
API0_ADO7 H4
API0_ADO8 G1

API0_ADO17 F4
API0_ADO18 E2
API0_ADO19 F5

API0_ADO28 D8
API0_ADO29 A5
API0_ADO30 C2

API0_ADO39 C8
API0_ADO40 A2
API0_ADO41 B3

p
la

API_QREQ0 E14

.
w
w
w
E8 API0_APSYNC
H17 API0_SE

API_APCLK_AVSS

C2802
0.1UF

20%
10V
2 CERM
402

C2803
0.1UF

20%
2 10V
CERM
402

C2804
0.1UF

20%
2 10V
CERM
402

C2805
0.1UF

20%
2 10V
CERM
402

C2806
0.1UF

20%
2 10V
CERM
402

C2807
0.1UF

20%
2 10V
CERM
402

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

EI_CPU_TO_NB_AD<0..43>
EI_NB_TO_CPU_AD<0..43>

EI_CPU_TO_NB_CAD
EI_NB_TO_CPU_CAD

EI_CPU_TO_NB_AD
EI_NB_TO_CPU_AD

EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_N<1>

EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CAD

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK

EI_CPU_TO_NB_SR0
EI_CPU_TO_NB_SR0
EI_CPU_TO_NB_SR1
EI_CPU_TO_NB_SR1

EI_NB_TO_CPU_SR_P<0>
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_SR_N<1>

EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_CAD

EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

EI_NB_TO_CPU_SR0
EI_NB_TO_CPU_SR0
EI_NB_TO_CPU_SR1
EI_NB_TO_CPU_SR1

14 28 29

OMIT

ZT2847

14 28 29
14 28 29

ZT2858

HOLE-VIA-20R10
1

ZT2860

HOLE-VIA-20R10
1

m
e
h
c

OMIT

14 28 29
14 28 29
14 28 29

14 28 29

C2809
0.1UF

20%
2 10V
CERM
402

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

ZT2801

ZT2811

ZT2821

ZT2831

OMIT

ZT2840

HOLE-VIA-20R10
1

OMIT

ZT2841

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2862

ZT2802

ZT2812

ZT2822

ZT2832

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2863

ZT2803

ZT2813

ZT2823

ZT2833

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2854

ZT2864

ZT2804

ZT2814

ZT2824

ZT2834

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2855

HOLE-VIA-20R10
1

PP1V2_EI_NB

ZT2865

HOLE-VIA-20R10
1

ZT2805

HOLE-VIA-20R10
1

ZT2815

ZT2835

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

ZT2806
1

NOSTUFF

ZT2825

HOLE-VIA-20R10

HOLE-VIA-20R10

7 18 28

ZT2816

HOLE-VIA-20R10
1

ZT2826

HOLE-VIA-20R10
1

ZT2842

HOLE-VIA-20R10
1

OMIT

ZT2843

HOLE-VIA-20R10
1

OMIT

ZT2844

HOLE-VIA-20R10
1

OMIT

ZT2845

HOLE-VIA-20R10
1

OMIT

ZT2836

HOLE-VIA-20R10
1

R2802

OMIT

100

NOSTUFF

C2821

ZT2846

1%
1/16W
MF
2 402

HOLE-VIA-20R10
1
EI_APCLK_VREF
VOLTAGE=0.6V
NOSTUFF
NOSTUFF
1

0.001UF
NOSTUFF
1

R2801

100

14 28 29

0.1UF

1%
1/16W
MF
2 402

14 28 29
14 28 29

C2820

20%
10V
2 CERM
402

OMIT

OMIT

ZT2856

HOLE-VIA-20R10

ZT2866

HOLE-VIA-20R10

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
NOSTUFF

R2803 1R2804
121

121

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

14 29 30

CPU_CHKSTOP_L

20%
2 10V
CERM
402

HOLE-VIA-20R10

HOLE-VIA-20R10

EI_NB_CLK_P
EI_NB_CLK_N

EI_NB_CLK_N

0.1UF

HOLE-VIA-20R10

HOLE-VIA-20R10

EI_NB_CLK_P

C2808

ZT2830

HOLE-VIA-20R10

HOLE-VIA-20R10

10%
50V
2 CERM
402

14 28 29

ZT2820

HOLE-VIA-20R10

14 28 29

14 28 29

ZT2810

HOLE-VIA-20R10

14 28 29

14 28 29

ZT2861

ZT2800

OMIT

ZT2839

HOLE-VIA-20R10

HOLE-VIA-20R10

14 28 29

ZT2829

HOLE-VIA-20R10

ZT2853

14 28 29

ZT2819

OMIT

OMIT

ZT2838

HOLE-VIA-20R10
1

OMIT

OMIT

OMIT

14 28 29

ZT2809

OMIT

ZT2837

HOLE-VIA-20R10

1
OMIT

OMIT

ZT2852

14 28 29

ZT2869

ZT2828

HOLE-VIA-20R10

OMIT

14 28 29

OMIT

OMIT

ZT2851

14 28 29

ZT2818

HOLE-VIA-20R10

OMIT

ZT2859

OMIT

14 28 29

ZT2808

HOLE-VIA-20R10

HOLE-VIA-20R10

14 28 29

ZT2868

HOLE-VIA-20R10

HOLE-VIA-20R10

ZT2850

14 28 29

OMIT

ZT2827

HOLE-VIA-20R10

HOLE-VIA-20R10

14 28 29

OMIT

ZT2817

HOLE-VIA-20R10

14 28 29

14 28 29

I225

HOLE-VIA-20R10

14 28 29

I224

HOLE-VIA-20R10

14 28 29

14 28 29

OMIT

14 28 29

14 28 29

I223

OMIT

ZT2849

14 28 29

I222

OMIT

14 28 29

14 28 29

I221

OMIT

OMIT

14 28 29

I220

OMIT

14 28 29

I219

OMIT

14 28 29

14 28 29

I218

OMIT

14 28 29

14 28 29

I217

HOLE-VIA-20R10

ZT2848

14 28 29

I216

HOLE-VIA-20R10

HOLE-VIA-20R10

14 28 29

I215

HOLE-VIA-20R10

14 28 29

14 28 29

ZT2807

I214

HOLE-VIA-20R10

14 28 29

OMIT

ZT2867

I213

HOLE-VIA-20R10

14 28 29

14 28 29

c
.
s
it c
OMIT

ZT2857

m
o

I212

HOLE-VIA-20R10

14 28 29

s
p
to

EI_QREQ_L

API_APCLKP D18
API_APCLKN C18
API_CSTP F14

EI_SE

H14 API0_ADI6
G14 API0_ADI7
D9 API0_ADI8

APPLE PI
INTERFACE

API0_ADO2 J1
API0_ADO3 K1
API0_ADO4 E1
API0_ADO5 F2

G20

G11 API0_ADI2
H11 API0_ADI3
G12 API0_ADI4
H12 API0_ADI5

DIFFERENTIAL_PAIR

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

14 28 29

OMIT

API0_ADO0 J2
API0_ADO1 H1

B12 API0_ADI20
C12 API0_ADI21
D12 API0_ADI22

C2801

20%
2 10V
CERM
402

OMIT

EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK_N

API0_ADO15 J6
API0_ADO16 E3

7 18 28

0.1UF

(SYM 1 OF 7)

API0_BCLKOP D6
API0_BCLKON E6

B9 API0_ADI15
C11 API0_ADI16
B11 API0_ADI17
A11 API0_ADI18
A12 API0_ADI19

402

PBGA

API0_ADO12 H3
API0_ADO13 J3
API0_ADO14 J5

NOSTUFF

PP1V2_EI_NB

U3LITE
V1.0-300MM

29 28 14

A10 API0_ADI12
A9 API0_ADI13
A8 API0_ADI14

R2806

30 29 14

29 28 14

API0_ADO9 H2
API0_ADO10 F1
API0_ADO11 H5

EI_SYNC_FROM_NB

29 28 14

VDD_API

U3

C9 API0_ADI9
D11 API0_ADI10
E11 API0_ADI11

402

29

29 28 14

EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<4>
EI_CPU_TO_NB_AD<5>
EI_CPU_TO_NB_AD<6>
EI_CPU_TO_NB_AD<7>
EI_CPU_TO_NB_AD<8>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<11>
EI_CPU_TO_NB_AD<12>
EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<15>
EI_CPU_TO_NB_AD<16>
EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<18>
EI_CPU_TO_NB_AD<19>
EI_CPU_TO_NB_AD<20>
EI_CPU_TO_NB_AD<21>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<23>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<25>
EI_CPU_TO_NB_AD<26>
EI_CPU_TO_NB_AD<27>
EI_CPU_TO_NB_AD<28>
EI_CPU_TO_NB_AD<29>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<35>
EI_CPU_TO_NB_AD<36>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<38>
EI_CPU_TO_NB_AD<39>
EI_CPU_TO_NB_AD<40>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<42>
EI_CPU_TO_NB_AD<43>

R2805
27

7 18 28
29 28 14

API
APCLK_AVDD

29 28 14

29 28 14

PP1V2_EI_NB
B19

10%
6.3V
2 CERM
402

C2819
B7
B10

1UF

D16

C2818

29 28 14

D4
D13

F10

5%
1/16W
MF
603

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

G2
F7

H16

2.2

K4
K8

J13
H13

PP1V5_PWRON_NB_AVDD

F21

60 48 37 7

NET_SPACING_TYPE

EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK_N
EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_CLK_N

27
27

29

C2820, R2803, R2804 CHANGED TO 603 FOR FMAX

C2810

0.1UF

20%
2 10V
CERM
402

C2811
0.1UF

20%
2 10V
CERM
402

C2812
0.1UF

20%
2 10V
CERM
402

C2813
0.1UF

20%
2 10V
CERM
402

C2814
0.1UF

20%
2 10V
CERM
402

C2815
0.1UF

20%
2 10V
CERM
402

C2816
0.1UF

20%
2 10V
CERM
402

C2817
0.1UF

20%
2 10V
CERM
402

PLACE NEAR PROCESSOR.

PLACE AT PROCESSOR PINS.

35 31 30 29 18 7

NOSTUFF
1

R2909

R2903

27

EI_CPU_CLK_P

NOSTUFF

EI_CPU_CLK_N

46.4 2
1%
1/16W
MF
402

PPVCORE_CPU

MORE PROCESSOR DECOUPLING ON PAGES 31 & 32

1%
1/16W
MF
2 402

1%
1/16W
MF
402

27

36 35 34 33 32 31 7 6

100

46.4 2

R2901

SYSCLK_TERM
VOLTAGE=0.6V

NOSTUFF
1

NOSTUFF

100

0.22UF

1%
1/16W
MF
2 402

20%
6.3V
2 X5R
402

c
.
s
it c

10%
6.3V
2 CERM
402

R2907

C2901

C2953
1UF

C2954

10%
6.3V
2 CERM
402

T22
R22

SYSCLK*

28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28

14 EI_NB_TO_CPU_AD<0>
14 EI_NB_TO_CPU_AD<1>
14 EI_NB_TO_CPU_AD<2>
14 EI_NB_TO_CPU_AD<3>
14 EI_NB_TO_CPU_AD<4>
14 EI_NB_TO_CPU_AD<5>
14 EI_NB_TO_CPU_AD<6>
14 EI_NB_TO_CPU_AD<7>
14 EI_NB_TO_CPU_AD<8>
14 EI_NB_TO_CPU_AD<9>
14 EI_NB_TO_CPU_AD<10>
14 EI_NB_TO_CPU_AD<11>
14 EI_NB_TO_CPU_AD<12>
14 EI_NB_TO_CPU_AD<13>
14 EI_NB_TO_CPU_AD<14>
14 EI_NB_TO_CPU_AD<15>
14 EI_NB_TO_CPU_AD<16>
14 EI_NB_TO_CPU_AD<17>
14 EI_NB_TO_CPU_AD<18>
14 EI_NB_TO_CPU_AD<19>
14 EI_NB_TO_CPU_AD<20>
14 EI_NB_TO_CPU_AD<21>
14 EI_NB_TO_CPU_AD<22>
14 EI_NB_TO_CPU_AD<23>
14 EI_NB_TO_CPU_AD<24>
14 EI_NB_TO_CPU_AD<25>
14 EI_NB_TO_CPU_AD<26>
14 EI_NB_TO_CPU_AD<27>
14 EI_NB_TO_CPU_AD<28>
14 EI_NB_TO_CPU_AD<29>
14 EI_NB_TO_CPU_AD<30>
14 EI_NB_TO_CPU_AD<31>
14 EI_NB_TO_CPU_AD<32>
14 EI_NB_TO_CPU_AD<33>
14 EI_NB_TO_CPU_AD<34>
14 EI_NB_TO_CPU_AD<35>
14 EI_NB_TO_CPU_AD<36>
14 EI_NB_TO_CPU_AD<37>
14 EI_NB_TO_CPU_AD<38>
14 EI_NB_TO_CPU_AD<39>
14 EI_NB_TO_CPU_AD<40>
14 EI_NB_TO_CPU_AD<41>
14 EI_NB_TO_CPU_AD<42>
14 EI_NB_TO_CPU_AD<43>

28 14 EI_NB_TO_CPU_SR_P<0>
28 14 EI_NB_TO_CPU_SR_N<0>
28 14 EI_NB_TO_CPU_SR_P<1>
28 14 EI_NB_TO_CPU_SR_N<1>

E24 EI_CLKI
D24
EI_CLKI*
H21
J21
H22
J22
C13
A13
K22
H23
J24
G20
F23
G21
D22
G24
G19
B15
A14
C15
D15
A16
C22
E20
E21
B23
B24
F21
B17
B19
C14
C17
D18
B21
D20
A22
C19
C18
A21
A23
A20
A18
A15
A17
C16
A19

L24
K24
L21
L22

EI_ADI0
EI_ADI1
EI_ADI2
EI_ADI3
EI_ADI4
EI_ADI5
EI_ADI6
EI_ADI7
EI_ADI8
EI_ADI9
EI_ADI10
EI_ADI11
EI_ADI12
EI_ADI13
EI_ADI14
EI_ADI15
EI_ADI16
EI_ADI17
EI_ADI18
EI_ADI19
EI_ADI20
EI_ADI21
EI_ADI22
EI_ADI23
EI_ADI24
EI_ADI25
EI_ADI26
EI_ADI27
EI_ADI28
EI_ADI29
EI_ADI30
EI_ADI31
EI_ADI32
EI_ADI33
EI_ADI34
EI_ADI35
EI_ADI36
EI_ADI37
EI_ADI38
EI_ADI39
EI_ADI40
EI_ADI41
EI_ADI42
EI_ADI43

28 14

EI_QACK_L

V21

QACK*

CHKSTOP_L

R20

CHKSTOP*

CPU_HTBEN

30 14 13

CPU_HRESET_L

AD17

TBEN

AD14

APSYNCOUT

V20

U2900
GPUL
(1 OF 3)

CBGA

EI_CLKO
EI_CLKO*

D3

EI_ADO0
EI_ADO1
EI_ADO2
EI_ADO3
EI_ADO4
EI_ADO5
EI_ADO6
EI_ADO7
EI_ADO8
EI_ADO9
EI_ADO10
EI_ADO11
EI_ADO12
EI_ADO13
EI_ADO14
EI_ADO15
EI_ADO16
EI_ADO17
EI_ADO18
EI_ADO19
EI_ADO20
EI_ADO21
EI_ADO22
EI_ADO23
EI_ADO24
EI_ADO25
EI_ADO26
EI_ADO27
EI_ADO28
EI_ADO29
EI_ADO30
EI_ADO31
EI_ADO32
EI_ADO33
EI_ADO34
EI_ADO35
EI_ADO36
EI_ADO37
EI_ADO38
EI_ADO39
EI_ADO40
EI_ADO41
EI_ADO42
EI_ADO43

N3

EI_SRO0
EI_SRO0*
EI_SRO1
EI_SRO1*

L3

CPU_SRESET_L

AB4

SRESET*

PROC_THERM_INT_L

V22

THERM_INT*

30
30
30

PROCID0
PROCID1
PROCID2

30
30
30
30
30

30
30
30
30
30
29 14

30
30
30
30
30 14
30 14

EI_SE
TP_PROC_TRIGGER_OUT
6 TP_AFN
AVPRESET_L
BIMODE_L
C1UNDGLOBAL
C2UNDGLOBAL
DI2_L

LSSDMODE
LSSDSCANENABLE
LSSDSTOPC2ENABLE
LSSDSTOPC2STARENABLE
LSSDSTOPENABLE
MCP_L
6 TP_PSRO1
6 TP_PSRO2
PULSESEL0
PULSESEL1
PULSESEL2
RAMSTOPENABLE
RI_L
SYNCENABLE

M19
M18

N21
N19

AA12
W23
AC24
AC16
AC15
U24

AB5
U19
AD8
AD7
AD11
AD18

V23
V5
AC9
AB11
AC10
AB6
AA5
AB24

L1
M3
K4
K2
H3
H1
G4
F2
F4
E2
G3
B8
D11
E12
A11
B10
C11
C1
C5
B2
D6
A5
A2
D2
D8
C12
A12
B6
B4
C4
C7
A7
C8
C6
A4
A9
C9
A10
C10
A8
A6

L2
G1
F1

PROCID0
PROCID1
PROCID2

EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_N<1>

14 28
14 28
14 28
14 28

14 28 30

CPU_INT_L

14 25 30

APSYNCIN

AA10

IIC_SCL
IIC_SDA

AA20

TRIGGER_IN
TRIGGER_OUT

ATTENTION
GPUL_DBG
JTAGMODE

AFN
AVPRESET*
BIMODE*
C1UNDGLOBAL
C2UNDGLOBAL
DI2*
LSSDMODE
LSSDSCANENABLE
LSSDSTOPC2ENABLE
LSSDSTOPC2STARENABLE
LSSDSTOPENABLE
MCP*
PSRO1
PSRO2
PULSESEL0
PULSESEL1
PULSESEL2
RAMSTOPENABLE
RI*
SYNCENABLE*

TCK
TDI
TDO
TMS
TRST*
BYPASS*
PLLLOCK
PLLMULT
PLLRANGE0
PLLRANGE1
PLLTEST
PLLTESTOUT

MATCH TO SYSCLK

10%
6.3V
2 CERM
402

a
1

10%
6.3V
2 CERM
402

N22

I2CGO

30

AA14

CKTERMDIS_L

30

P20

EI_DISABLE

30

BUSCFG0
BUSCFG1
BUSCFG2

AA19
AC19
AB16

AD12
AA22
W4

EI_CPU_SYNC

27

NOSTUFF

AB21
AD13
AD22
W20

TP_ATTENTION
GPUL_DBG
JTAGMODE_SPARE2

6
30
30

JTAG_CPU_TCK
JTAG_CPU_TDI
JTAG_CPU_TDO
JTAG_CPU_TMS
JTAG_CPU_TRST_L

18
18
18
18
30

CPU_BYPASS_L
PLLLOCK
PLLMULT
PLLRANGE0
PLLRANGE1
PLLTEST
PLLTESTOUT

V24
T20
AA8
AB7
AA9
W22
T19

.
w
w
w
SPARE

AA13

49.9 2
1

PLACE BY PROCESSOR PIN.

28

30
30
30
30

13 30
30
30
30
30
30
30
30

C2900
1UF

10%
6.3V
2 CERM
402

C2911
1UF

10%
6.3V
2 CERM
402

C2948

10%
6.3V
2 CERM
402

C2951

1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2952

1UF

10%
6.3V
2 CERM
402

C2950

C2960

C2959
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2910
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2909
1UF

10%
6.3V
2 CERM
402

C2940
1UF

10%
6.3V
2 CERM
402

C2943
1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

1UF

C2949

C2939
1UF

1UF

10%
6.3V
2 CERM
402

1UF

C2946

C2944

1UF

10%
6.3V
2 CERM
402

C2958
1UF

10%
6.3V
2 CERM
402

C2908
1UF

10%
6.3V
2 CERM
402

C2938

10%
6.3V
2 CERM
402

C2941
1UF

10%
6.3V
2 CERM
402

C2942

10%
6.3V
2 CERM
402

C2957
1UF

10%
6.3V
2 CERM
402

C2907
1UF

10%
6.3V
2 CERM
402

C2929

10%
6.3V
2 CERM
402

C2930
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2927

C2936

C2935
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2906
1UF

10%
6.3V
2 CERM
402

C2905
1UF

10%
6.3V
2 CERM
402

C2920
1UF

10%
6.3V
2 CERM
402

C2921

10%
6.3V
2 CERM
402

C2922
1UF

10%
6.3V
2 CERM
402

C2923

10%
6.3V
2 CERM
402

C2934
1UF

10%
6.3V
2 CERM
402

C2904
1UF

10%
6.3V
2 CERM
402

C2915

10%
6.3V
2 CERM
402

C2918
1UF

10%
6.3V
2 CERM
402

C2919

1UF

C2933
1UF

10%
6.3V
2 CERM
402

C2913
1UF

10%
6.3V
2 CERM
402

C2916
1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

C2912

10%
6.3V
2 CERM
402

1UF

1UF

10%
6.3V
2 CERM
402

C2914
1UF

1UF

1UF

10%
6.3V
2 CERM
402

1UF

C2926

10%
6.3V
2 CERM
402

C2931

1UF

1UF

C2925

1UF

10%
6.3V
2 CERM
402

C2924
1UF

1UF

1UF

10%
6.3V
2 CERM
402

C2928
1UF

1UF

1UF

10%
6.3V
2 CERM
402

C2937

C2917
1UF

10%
6.3V
2 CERM
402

C2932
1UF

10%
6.3V
2 CERM
402

EI_SYNC_FROM_NB

28

C2903 1C2902
1UF

1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

PROCESSOR IIC ADDRESS:

80,84

R2906
1K
5%
1/16W
MF

2 402

R2908
1K
5%
1/16W
MF

2 402

CHKSTOP_L 14

29 30

5%
1/16W
MF
402

CPU_CHKSTOP_L

NOSTUFF

R2904

MCP_L

14 29

5%
1/16W
MF
402

PROCESSOR LOGIC I/O

8

PP1V2_EI_CPU

R2902

1%
1/16W
MF
402

CPU_SPARE

5%
1/16W
MF
402

30
30
30

10%
6.3V
2 CERM
402

1UF

C2945

s
p
to
2

5%
1/16W
MF
402

p
la

AD21

m
e
h
c

R2910
1

18
18

Y21

C2956

1UF

10%
6.3V
2 CERM
402

1UF

CPU_APSYNC
I2C_CPU_A_SCL
I2C_CPU_A_SDA

C2955
1UF

28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28

EI_QREQ_L

BUSCFG0
BUSCFG1
BUSCFG2

NOSTUFF

14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14

AB19

EI_DISABLE

R2905
CPU_HTBEN

EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<4>
EI_CPU_TO_NB_AD<5>
EI_CPU_TO_NB_AD<6>
EI_CPU_TO_NB_AD<7>
EI_CPU_TO_NB_AD<8>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<11>
EI_CPU_TO_NB_AD<12>
EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<15>
EI_CPU_TO_NB_AD<16>
EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<18>
EI_CPU_TO_NB_AD<19>
EI_CPU_TO_NB_AD<20>
EI_CPU_TO_NB_AD<21>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<23>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<25>
EI_CPU_TO_NB_AD<26>
EI_CPU_TO_NB_AD<27>
EI_CPU_TO_NB_AD<28>
EI_CPU_TO_NB_AD<29>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<35>
EI_CPU_TO_NB_AD<36>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<38>
EI_CPU_TO_NB_AD<39>
EI_CPU_TO_NB_AD<40>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<42>
EI_CPU_TO_NB_AD<43>

AB12

35 31 30 29 18 7

30 29 27

14 28
14 28

INT*

I2CGO
L19

H2
K3

EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK_N

QREQ*

CKTERMDIS

30 28 14
14 6

E3

R2911

HRESET*

30

30 25

CRITICAL

EI_SRI0
EI_SRI0*
EI_SRI1
EI_SRI1*

30 29 27

TP_PSYNCOUT

(SEE TABLE)
OMIT

30 29 14

SYSCLK

C2947
1UF

1UF

28 14 EI_NB_TO_CPU_CLK_P
28 14 EI_NB_TO_CPU_CLK_N

m
o

PP1V2_EI_CPU

NOSTUFF

SELECT PROCESSOR CLOCK MULTIPLIER. PROCESSOR CLOCK(MHZ)= SYSTCLOCK * PLLMULT.

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

*
0

35 31 30 29 18 7

PP1V2_EI_CPU

1K

1K

R3009
29

C2UNDGLOBAL
NOSTUFF

R3079

R3069

1K

5%
1/16W
MF
402

1K

JTAG_CPU_TRST_L

1K

29

R3093
29 18

JTAG_CPU_TDO

1K

LSSDSTOPENABLE

29

29

BIMODE_L

DI2_L

1K

1K

CPU_INT_L

CPU_HRESET_L

CPU_BYPASS_L

PULSESEL0

R3057

5%
1/16W
MF
402
29

R3063

R3061

1K

I2CGO

R3075
1

1K

5%
1/16W
MF
402

29 27

CPU_HTBEN

5%
1/16W
MF
402

NOSTUFF

R3042
1

1K

1K

29 PROCID0

29 PROCID1

GPUL_DBG

1K

PULSESEL1

29 PROCID2

5%
1/16W
MF
402

114S1103

114S1103

c
.
s
it c
114S1103

114S1103

114S1103

114S1103

5%
1/16W
MF
2 402

QTY

NOSTUFF

RES,1K OHM,1/16W,5%,0402

R3024,R3010,R3028

NOSTUFF

RES,1K OHM,1/16W,5%,0402

R3024,R3010,R3012

NOSTUFF

RES,1K OHM,1/16W,5%,0402

R3008,R3026,R3028

NOSTUFF

RES,1K OHM,1/16W,5%,0402

R3008,R3026,R3012

NOSTUFF

RES,1K OHM,1/16W,5%,0402

R3008,R3010,R3028

NOSTUFF

RES,1K OHM,1/16W,5%,0402

R3008,R3010,R3012

NOSTUFF

1K

DESCRIPTION

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

BYPASS MODE

NOSTUFF

PART#

QTY

TABLE_5_HEAD

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

114S1103

RES,1K OHM,1/16W,5%,0402

R3030,R3032

NOSTUFF

114S1103

RES,1K OHM,1/16W,5%,0402

R3030,R3016

NOSTUFF

114S1103

RES,1K OHM,1/16W,5%,0402

R3014,R3032

114S1103

RES,1K OHM,1/16W,5%,0402

R3014,R3016

PART#

QTY

114S1103

900 TO 1800 MHZ

TABLE_5_ITEM

1.8 TO 3.6 GHZ

TABLE_5_ITEM

1.2 TO 2.4 GHZ

TABLE_5_ITEM

RESERVED

NOSTUFF

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

RES,1K OHM,1/16W,5%,0402

AVPRESET OFF

R3022
TABLE_5_ITEM

114S1103

RES,1K OHM,1/16W,5%,0402

R3038

AVPRESET ON

NOSTUFF

* STUFF THESE ON Q45.

SYSTEM CONFIGURATION
CPU SPEED:1.8GHZ, SYSCLK 225MHZ
2.0GHZ, SYSCLK 250MHZ
35 31 30 29 18 7

PP1V2_EI_CPU

1 OMIT

1 OMIT

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R3008
1K

R3010
1K

OMIT

R3012
1K

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

2 402

R3014
1K

R3016
1K

R3018
1K

R3020
1K

R3022
1K
5%
1/16W
MF

BUSCFG0
BUSCFG1
BUSCFG2
PLLRANGE0
PLLRANGE1
PLLMULT
EI_DISABLE
AVPRESET_L

29
29

29

B
1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

2 402

R3024
1K

36 31 30 7 6 3

R3026
1K

R3028
1K

R3030
1K

R3032
1K

R3034
1K

R3036
1K

R3038
1K
5%
1/16W
MF

PP5V_RUN_CPU

R3070
180 DEVELOPMENT
5%
Q3002
1/16W

MF
2 402

2N3906

DEVELOPMENT
1

R3054

180

SM
Q3002_B 1

5%
1/16W
MF
2 402

D3002_1

Q3002_E
DEVELOPMENT
1

R3046

5%
1/16W
MF
2 402

DEVELOPMENT

Q3001_C

R3044
29

PLLLOCK 1

180

5%
1/16W
MF
402

5%
1/16W
MF
402

DEVELOPMENT

R3048

180

5%
1/16W
MF
2 402

Q3004_D

5%
1/16W
MF
2 402

DEVELOPMENT

D3001_1
3

DEVELOPMENT

SM

2N7002

DEVELOPMENT
Q3004_G 1

GREEN
2.0X1.25

2N3904

Q3004

D3001

Q3001

2 Q3001_B 1

CHKSTOP_L 1

180

5%
1/16W
MF
402

R3050
29 14

SM

S
2

DEVELOPMENT

D3002
SM

R3052

180

DEVELOPMENT

RED

DEVELOPMENT

DEVELOPMENT

Q3003

2N3904

Q3003_B

SM
2

PROCESSOR PULL-UPS AND -DOWNS

8

TABLE_5_HEAD

DESCRIPTION

5%
1/16W
MF
402

PROC / 16
TABLE_5_ITEM

TABLE_5_ITEM

PP5V_RUN_CPU

R3004

1K

PROC / 12
TABLE_5_ITEM

DEVELOPMENT

R3006

PROC / 8
TABLE_5_ITEM

R3020

29

1K

1K

PROC / 6
TABLE_5_ITEM

RES,1K OHM,1/16W,5%,0402

29

5%
1/16W
MF
402

PROC / 4
TABLE_5_ITEM

R3002
1K

PROC / 3
TABLE_5_ITEM

114S1103

29

5%
1/16W
MF
402

TABLE_5_ITEM

R3036

R3007

PROC / 2

R3024,R3026,R3012

RES,1K OHM,1/16W,5%,0402

29

1K

TABLE_5_ITEM

R3024,R3026,R3028

29

BOM OPTION

RES,1K OHM,1/16W,5%,0402

114S1103

1K

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

RES,1K OHM,1/16W,5%,0402

5%
1/16W
MF
402

29 PULSESEL2

5%
1/16W
MF
402

5%
1/16W
MF
402

R3040

1K

R3089

R3073
1K

.
w
w
w
1

5%
1/16W
MF
402

CKTERMDIS_L
NOSTUFF

1K

5%
1/16W
MF
402

R3087

29

PLLTEST

5%
1/16W
MF
402

29

5%
1/16W
MF
402

NOSTUFF

29

1K

1K

10K

R3005

29

R3003

p
la

5%
1/16W
MF
402

NOSTUFF

R3059

R3068

5%
1/16W
MF
402

R3085
CPU_SRESET_L

114S1103

DESCRIPTION

7 18 29 30 31 35

5%
1/16W
MF
402

5%
1/16W
MF
402

29 25

1K

EI_SE

R3083
29 14 13

PP1V2_EI_CPU

R3081

29

1K

s
p
to
1K

5%
1/16W
MF
402

5%
1/16W
MF
402

29 28 14

PROC_THERM_INT_L

R3067
CPU_SPARE

29

R3065
29

5%
1/16W
MF
402
NOSTUFF

5%
1/16W
MF
402

1K

1K

PLLTESTOUT

5%
1/16W
MF
402

R3055
RAMSTOPENABLE

29

1K

m
e
h
c
29

5%
1/16W
MF
402

R3091
29 25 14

1K

5%
1/16W
MF
402

1K

10K

SYSCLK * 8

SELECT PLL FREQUENCY RANGE.

R3071

R3037
SYNCENABLE

29 14

R3035
RI_L

5%
1/16W
MF
402

29 14

NOSTUFF

114S1103

PART#

5%
1/16W
MF
402

5%
1/16W
MF
402

R3033
29

10K

29 18 JTAG_CPU_TMS

R3053
EI_QREQ_L

29 28 14

SYSCLK * 12

SELECT ELASTIC MODE OR BYPASS.

R3099

5%
1/16W
MF
402
NOSTUFF

5%
1/16W
MF
402

1K

1K

R3031
1K

5%
1/16W
MF
402

m
o

QTY

5%
1/16W
MF
402

R3051

5%
1/16W
MF
402

10K

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

29 13

1K

R3097
29 18 JTAG_CPU_TDI

R3049
LSSDSTOPC2STARENABLE

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

R3018

30 31 36

1K

RES,1K OHM,1/16W,5%,0402

NOSTUFF

R3043

1K

R3077

114S1103

NOSTUFF

29

LSSDSTOPC2ENABLE

29

C1UNDGLOBAL

10K

29 18 JTAG_CPU_TCK

R3047
29

R3095

5%
1/16W
MF
402

1K

R3041
LSSDSCANENABLE

R3001

5%
1/16W
MF
402

5%
1/16W
MF
402

29

NOSTUFF

R3000
JTAG_SEL

LSSDMODE

29

R3034

PART#

R3045
7 18 29 30 31 35

RES,1K OHM,1/16W,5%,0402

TABLE_5_ITEM

PP1V2_EI_CPU

5%
1/16W
MF
402

SELECT EI BUS DIVIDER. BUS DATA RATE(BPS)= (PROCESSOR CLOCK) / BUSCFG.

R3039
JTAGMODE_SPARE2

29

114S1103

36 35 34 33 32 31 29 7 6

PPVCORE_CPU

PP1V2_EI_CPU

7 18 29 30 35

PP2V5_RUN_CPU
7

NET_SPACING_TYPE=PROC_DIFF

NOSTUFF

L3101

R3132
1

VR3100
SOT-25A

CPU_AVDD_EN

VIN

VOUT

CONT NOISE

C3149
1UF

20%
10V
CERM
603

2
SM
0805

PP2V5_RUN_CPU_AVDD_R_L

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=2.5V
CPU_AVDD_NOISE

2.2

5%
1/16W
MF
603

C3148

0.01UF

2
1
1

C3102
10UF

20%
6.3V
2 CERM
805

C3150

C3100
0.22UF

20%
2 6.3V
X5R
402

10UF

20%
16V
2 CERM
402

20%
6.3V
2 CERM
805

A1
A24
B11
B13
B16
B20
B3
B7
C2
C20
C24
D13
D17
D19
D21
D23
D5
D7
D9
E1
E10
E14
E16
E18
E22
E4
E6
E8
F11
F13
F15
F17
F19
F3
F5
F7
F9
G10
G12
G14
G16
G18
G22
G6
G8
H11
H13
H15
H17
H19
H24
H5
H7
H9
J1
J10
J12
J14
J16
J18
J2
J20
J4
J6
J8
K11
K13
K15
K17
K19
K21
K23
K5
K7
K9
L10
L12
L14
L16
L18
L20
L4
L6
L8
M1
M11
M13
M15
M17
M21
M23
M5
M7
M9
N10
N12
N14
N16
N18
N2
N20
N24
N4
N6
N8

p
la

.
w
w
w

s
p
to

CBGA

VCORE

GND

X105

X105

KPGND1

R24

10UF

A3
B1
B12
B14
B18
B22
B5
B9
C21
C23
C3
D1
D10
D12
D14
D16
D4
E11
E13
E15
E17
E19
E23
E5
E7
E9
F10
F12
F14
F16
F18
F20
F22
F24
F6
F8
G11
G13
G15
G17
G2
G23
G5
G7
G9
H10
H12
H14
H16
H18
H20
H4
H6
H8
J11
J13
J15
J17
J19
J23
J3
J5
J7
J9
K1
K10
K12
K14
K16
K18
K20
K6
K8
L11
L13
L15
L17
L23
L5
L7
L9
M10
M12
M14
M16
M2
M20
M22
M24
M4
M6
M8
N1
N11
N13
N15
N17
N23
N5
N7
N9
P10
P12
P14
P16

GND_SPARE_GND

31

10UF

20%
6.3V
2 CERM
805

20%
6.3V
2 CERM
805

U2900

c
.
s
it c
P1
P11
P13
P15
P17
P19
P21
P23
P3
P5
P7
P9
R10
R12
R14
R16
R18
R4
R6
R8
T1
T11
T13
T15
T17
T21
T23
T3
T5
T7
T9
U10
U12
U14
U16
U18
U2
U20
U22
U4
U6
U8
V1
V11
V13
V15
V17
V19
V3
V7
V9
W10
W12
W14
W16
W18
W2
W24
W6
W8
Y11
Y13
Y15
Y17
Y19
Y22
Y23
Y3
Y5
Y7
Y9
AA16
AA18
AA2
AA24
AA4
AA6
AB1
AB13
AB15
AB17
AB23
AB3
AB9
AC12
AC14
AC18
AC2
AC20
AC22
AC4
AC6
AC8
AD1
AD15
AD19
AD23
AD3
AD5
AD9

GPUL
(3 OF 3)
CBGA

C3114

m
o
10UF

20%
6.3V
2 CERM
805

KPVDD2

U2900
GPUL
(2 OF 3)

AGND

C3117 1 C3116 1 C3115

R2

Y1

KPVDD1

m
e
h
c

DIFFERENTIAL_PAIR=P_TDD
MIN_LINE_WIDTH=10MIL
TDIODE_POS 36
MIN_NECK_WIDTH=8MIL

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MILP24
MIN_NECK_WIDTH=10MIL
AVDD

GND

PP2V5_RUN_CPU_AVDD_R

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP2V5_RUN_CPU_AVDD

5
4

35

R3101

MM1572FN
1

5%
1/16W
MF
603

CRITICAL

PP5V_RUN_CPU

2.2

60-OHM-EMI

VCORE

GND

X100

X99

P18
P2
P22
P4
P6
P8
R1
R11
R13
R15
R17
R19
R21
R23
R3
R5
R7
R9
T10
T12
T14
T16
T18
T24
T4
T6
T8
U1
U11
U13
U15
U17
U21
U23
U3
U5
U7
U9
V10
V12
V14
V16
V18
V2
V4
V6
V8
W1
W11
W13
W15
W17
W19
W21
W3
W5
W7
W9
Y10
Y12
Y14
Y16
Y18
Y2
Y20
Y24
Y4
Y6
Y8
AA11
AA15
AA17
AA21
AA23
AA3
AA7
AB10
AB14
AB18
AB2
AB20
AB22
AB8
AC1
AC11
AC13
AC17
AC21
AC23
AC3
AC5
AC7
AD10
AD16
AD2
AD20
AD24
AD4
AD6

10UF

20%
6.3V
2 CERM
805

1UF

10%
6.3V
2 CERM
402

C3112

GND_Z_OUT

31

GND_Z_SENSE

31

10%
2 6.3V
CERM
402

C3113
1UF

10%
6.3V
2 CERM
402

C3126

10%
6.3V
2 CERM
402

C3127
1UF

10%
6.3V
2 CERM
402

C3128

10%
2 6.3V
CERM
402

10%
6.3V
2 CERM
402

C3129
1UF

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3136

10%
2 6.3V
CERM
402

C3137
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

31 GND_Z_SENSE

C3138

10%
2 6.3V
CERM
402

C3145
1UF

10%
6.3V
2 CERM
402

C3146

10%
2 6.3V
CERM
402

R3129

10%
6.3V
2 CERM
402

R3131
31 GND_SPARE_GND1

C3124

10%
2 6.3V
CERM
402

C3107
1UF

10%
2 6.3V
CERM
402

1UF

10%
6.3V
2 CERM
402

C3104

1UF

10%
2 6.3V
CERM
402

1UF

10%
6.3V
2 CERM
402

C3118
1UF

10%
2 6.3V
CERM
402

C3119
1UF

10%
6.3V
2 CERM
402

C3122
1UF

10%
6.3V
2 CERM
402

C3125
1UF

10%
6.3V
2 CERM
402

C3131

1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3134
1UF

10%
6.3V
2 CERM
402

C3135

C3141
1UF

10%
6.3V
2 CERM
402

C3142

1UF

C3132
1UF

10%
6.3V
2 CERM
402

C3133
1UF

10%
2 6.3V
CERM
402

C3139
1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3130

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3123

C3140
1UF

10%
2 6.3V
CERM
402

C3147
1UF

5%
1/16W
MF
402

C3144
1UF

10%
6.3V
2 CERM
402

C3143
1UF

10%
6.3V
2 CERM
402

5%
1/16W
MF
402

36 35 34 33 32 31 29 7 6

NOSTUFF

R3103

PPVCORE_CPU

2
NOSTUFF

5%
1/16W
MF
402
NOSTUFF

0.22UF

R3105
1

5%
1/16W
MF
402

C3101

KPVDD2
MIN_LINE_WIDTH=10MIL

A
33 36

MIN_NECK_WIDTH=8MIL
DIFFERENTIAL_PAIR=P_KP2
NET_SPACING_TYPE=PROC_DIFF

20%
6.3V
2 X5R
402

KPGND2
MIN_LINE_WIDTH=10MIL

33 36

MIN_NECK_WIDTH=8MIL
DIFFERENTIAL_PAIR=P_KP2
NET_SPACING_TYPE=PROC_DIFF
PLACE ALL THESE PARTS VERY CLOSE TO U2900

C3103

C3108

PROCESSOR POWER PINS AND BYPASS CAPS

8

5%
1/16W
MF
402

NET_SPACING_TYPE=PROC_DIFF

10%
6.3V
2 CERM
402

1UF

1UF

R3127
0

C3121
1UF

1UF

1UF

1UF

1UF

31 GND_Z_OUT

C3120

C3105

C
1

T2

TDIODE_NEG 6 36
DIFFERENTIAL_PAIR=P_TDD
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL

C3110
1UF

1UF

10%
2 6.3V
CERM
402

C3109

1UF

1UF

10%
2 6.3V
CERM
402

C3106
1UF

1UF

KPGND2

AA1

C3111

m
o

D
36 35 34 33 31 29 7 6

PPVCORE_CPU

C3222
1UF

10%
6.3V
2 CERM
402

C3293

1UF

1UF

10%
2 6.3V
CERM
402

C3294
1UF

10%
6.3V
2 CERM
402

C3295

C3296
1UF

10%
6.3V
2 CERM
402

C3297

10%
2 6.3V
CERM
402

C3298
1UF

10%
6.3V
2 CERM
402

C3299

10%
6.3V
2 CERM
402

C3202
1UF

10%
6.3V
2 CERM
402

C3203
1UF

10%
2 6.3V
CERM
402

1UF

C3271

10%
2 6.3V
CERM
402

C3270
1UF

10%
6.3V
2 CERM
402

C3282

C3281
1UF

10%
6.3V
2 CERM
402

C3284

C3283
1UF

10%
6.3V
2 CERM
402

C3292
1UF

10%
2 6.3V
CERM
402

C3261

C3264

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3266

10%
6.3V
2 CERM
402

C3276

1UF

10%
2 6.3V
CERM
402

C3277

C3279

1UF

C3280

C3275

1UF

C3290
1UF

10%
2 6.3V
CERM
402

.
w
w
w

C3235

1UF

1UF

10%
2 6.3V
CERM
402

C3236
1UF

10%
6.3V
2 CERM
402

C3239

C3240
1UF

10%
6.3V
2 CERM
402

C3252

10%
2 6.3V
CERM
402

C3253
1UF

10%
6.3V
2 CERM
402

C3257

10%
6.3V
2 CERM
402

C3258

C3237

10%
2 6.3V
CERM
402

C3238
1UF

10%
6.3V
2 CERM
402

C3250

1UF

10%
6.3V
2 CERM
402

C3288
1UF

10%
2 6.3V
CERM
402

1UF

10%
6.3V
2 CERM
402

C3254

C3255
1UF

10%
6.3V
2 CERM
402

C3226

C3227

10%
6.3V
2 CERM
402

C3230

1UF

10%
2 6.3V
CERM
402

C3228

C3231

C3229
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C3243

1UF

10%
2 6.3V
CERM
402

1UF

C3241

1UF

C3245

C3287
1UF

10%
2 6.3V
CERM
402

C3244
1UF

10%
6.3V
2 CERM
402

C3248

1UF

10%
2 6.3V
CERM
402

C3246

C3256

C3201
1UF

10%
6.3V
2 CERM
402

C3206
1UF

10%
2 6.3V
CERM
402

C3249

C3247
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C3286
1UF

10%
2 6.3V
CERM
402

C3285
1UF

10%
2 6.3V
CERM
402

C3207
1UF

10%
6.3V
2 CERM
402

C3210
1UF

10%
2 6.3V
CERM
402

C3211
1UF

10%
6.3V
2 CERM
402

C3214
1UF

10%
2 6.3V
CERM
402

C3234

m
e
h
c

C3289

10%
2 6.3V
CERM
402

1UF

10%
6.3V
2 CERM
402

1UF

C3223

1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

1UF

C3242
1UF

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

1UF

C3200

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

1UF

10%
2 6.3V
CERM
402

1UF

1UF

10%
2 6.3V
CERM
402

1UF

C3225

C3212

10%
6.3V
2 CERM
402

1UF

1UF

10%
6.3V
2 CERM
402

C3224

10%
2 6.3V
CERM
402

1UF

1UF

10%
2 6.3V
CERM
402

1UF

10%
2 6.3V
CERM
402

C3215

10%
6.3V
2 CERM
402

s
p
to

C3251
1UF

1UF

1UF

10%
2 6.3V
CERM
402

C3216

10%
6.3V
2 CERM
402

1UF

1UF

10%
2 6.3V
CERM
402

C3233
1UF

1UF

10%
2 6.3V
CERM
402

C3232

1UF

1UF

10%
2 6.3V
CERM
402

C3217

10%
6.3V
2 CERM
402

p
la

10%
6.3V
2 CERM
402

C3291

1UF

1UF

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3274

10%
2 6.3V
CERM
402

1UF

C3273

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

1UF

1UF

1UF

10%
6.3V
2 CERM
402

C3272

10%
2 6.3V
CERM
402

1UF

C3263

C3218

10%
6.3V
2 CERM
402

1UF

1UF

10%
6.3V
2 CERM
402

C3262

10%
2 6.3V
CERM
402

1UF

C3260
1UF

C3265

1UF

1UF

C3259

10%
2 6.3V
CERM
402

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

1UF

1UF

C3219

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

1UF

10%
2 6.3V
CERM
402

1UF

1UF

1UF

10%
2 6.3V
CERM
402

C3269
1UF

1UF

10%
2 6.3V
CERM
402

C3268

C3220

10%
6.3V
2 CERM
402

1UF

1UF

10%
2 6.3V
CERM
402

C3221

10%
6.3V
2 CERM
402

C3267
1UF

10%
2 6.3V
CERM
402

C3278
1UF

10%
6.3V
2 CERM
402

c
.
s
it c

C3204
1UF

10%
2 6.3V
CERM
402

C3205
1UF

10%
6.3V
2 CERM
402

C3208
1UF

10%
2 6.3V
CERM
402

C3209
1UF

10%
6.3V
2 CERM
402

C3213
1UF

10%
2 6.3V
CERM
402

7
33 7

C3310

R3329
SC2643_VCC

33

C3319
1UF

8 6
8 6
8 6
8 6
8 6

14 VID0
13 VID1
12 VID2

CPU_VID_R<0>
CPU_VID_R<1>
CPU_VID_R<2>
CPU_VID_R<3>
CPU_VID_R<4>
CPU_VID_R<5>

11 VID3
10 VID4
15 VID5
3 OS1
2 OS2
1 OS3
24 OS4

OUT1
OUT2
OUT3
OUT4

OUT1 19
OUT2 20
OUT3 21

TSSOP

OUT4 22

PGOOD 16

GSENSE 6

C3300
0.1UF

20%
2 10V
CERM
402

SC2643_ERROUT

R3316

5%
1/16W
MF
2 402

34

R3312

C3302

10%
50V
2 CERM
402

1%
1/16W
MF
2 402

SC2643_VCC

C3304
0.01UF

10%
16V
CERM
402

NOSTUFF

R3314

20.5K

1
C3305 R3315
20.5K

0.01UF

1%
1/16W
MF
2 402

NOSTUFF

10%
16V
2 CERM
402

1%
1/16W
MF
2 402

5%
1/16W
MF
2 402

NOSTUFF

1
C3306 R3318
20.5K

0.01UF

1%
1/16W
MF
2 402

10%
16V
2 CERM
402

C3307 1R3319
0.01UF

SC2643_AGND

R3305
SC2643_VCC

4.99K2

SC2643_OS_HUB

1%
1/16W
MF
402

FOR REMOTE SENSE

261

34 33 6

1%
1/16W
MF
402

VCORE_SENSE_VOUT

R3326
1

301

NOSTUFF

1%
1/16W
MF
402

R3324
330

NOSTUFF

5%
1/16W
MF
2 402

R3325

1K

p
la

R3325_2

5%
1/16W
MF
402

PLACE R3325 CLOSE TO INDUCTOR OUTPUT LEAD.

NOSTUFF

C3309
0.015UF

.
w
w
w
SC2643_OUTSEN

1.5K 2

SC2643_OUTSEN_R

1%
1/16W
MF
402

33 32 31 29 7 6
36 35 34

PPVCORE_CPU

MIN_LINE_WIDTH=10MIL

MIN_NECK_WIDTH=8MIL
UNDER PROCESSOR

R3336
1

5%
1/16W
MF
402

R3337

R3339

NOSTUFF
FAR SIDE

NOSTUFF

5%
1/16W
MF
402
36 31

R3341

NOSTUFF

36 31

KPGND2

R3342
1

KPVDD2
CPU SENSE SIDE

5%
1/16W
MF
402

R3340
1

5%
1/16W
MF
402

33

PPVCORE_CPU

MIN_LINE_WIDTH=10MIL
DIFFERENTIAL_PAIR=P_SENSE_CORE

6 33

MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

VCORE_SENSE_GND

33 7

C3330
1UF

20%
16V
2 CERM
1206

C3317

1800UF

C3332
1800UF

20%
2 6.3V
ELEC
TH-KZJ

20%
2 6.3V
ELEC
TH-KZJ

R3311
1

SUD70N03
TO-252

5%
1/10W
FF
2 805

C3316_1

C3315

C3316
0.0047UF

10%
25V
2 CERM
402

C3320

34 33 6

PLACE NEXT TO SMU

36 35 34 33 32 31 29 7 6

PPVCORE_CPU

R3308
1

100K 2

CPU_SENSE_V 13

5%
1/16W
MF
402

PP12V_CPU

10UF

20%
6.3V
2 CERM
805

2
1

C3321

C3303

C3322

GND_SMU_AVSS

10UF

1000UF

8 13 33 36

10%
16V

20%
16V
ELEC
TH-KZJ

2 CERM
1210

U3320
SC1211

6 VIN

SOIC

4 CO

BG 8
D

VREG 7

1 DRN

TG 2

3 BST

VPN 5

SUD50N03
TO-252

R3351

THMPAD

5%
1/16W
MF
2 402

R3320
1

SOT23

33

VPN2

1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3326_1

0.0022UF

C3326

0.0047UF

10%
25V
2 CERM
402

0.001UF

PEAK CURRENT ON PPVCORE_CPU

20 54.17A
17 37.50A

20%
2 50V
CERM
402
33

6 7 29 31 32 33 34 35
36

C3333

5%
1/10W
FF
2 805

10%
50V
2 CERM
402

C3324

1800UF

20%
2 6.3V
ELEC
TH-KZJ

TO-252

C3325

C3327

R3321

S
1

SUD70N03

NOSTUFF

AUX2

C3328

SAMSUNG

Q3321
G

5%
1/16W
MF
2 402

1800UF

U3320_BG

100

PPVCORE_CPU

2
TH1

20%
2 6.3V
ELEC
TH-KZJ
D

R3322

33

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

1UF

PN2

5%
1/16W
MF
402

U3320_VREG

20%
16V
2 CERM
1206

L3320

0.6UH-24A

10K

C3323

SAMSUNG

Q3320

U3320_TG
G

U3320_BST

6 7 29 31 32 33 34 35 36

PN2

CRITICAL

L3300
PP12V_RUN_CPU 1UH-20A-4.5MOHM
1

PP12V_CPU

R3343

6 33 34

0.0152

2 PP12V_CPU_R

TABLE_5_HEAD

TH-VERT

2%
1W
MF
2512

6 33

DIFFERENTIAL_PAIR=P_SENSE_CORE
MIN_LINE_WIDTH=10MIL

PART#

PLACE R3344 AND C3331 BY SMU

OMIT

SOT23-5

OUT

CORE_ISNS_P

XW3303
SM

CPU_SENSE_I_R

R3345

100K 2
5%
1/16W
MF
402

CRITICAL

BOM OPTION

CRITICAL

376S0130

ON SEMI FETS

Q3310,Q3320

CRITICAL

HYNIX

CRITICAL

376S0146

ON SEMI FETS

Q3311,Q3321

CRITICAL

HYNIX

TABLE_5_ITEM

CPU_SENSE_I

SOT23

13

C3331
10UF

121K

20%
2 6.3V
CERM
805

1%
1/16W
MF
2 402

OMIT

REFERENCE DESIGNATOR(S)

D3300
BAS16

R3344

GND

DESCRIPTION

3 NOSTUFF

6 36

OMIT

U3301

V+

INA138_OUT

INA138
5

PP3V3_RUN_CPU

XW3304
SM

VIN+ VIN-

QTY

TABLE_5_ITEM

KEEP SHORTS NEXT TO U3301

GND_SMU_AVSS

XW3301
SM

1800UF

20%
2 6.3V
ELEC
TH-KZJ

0.001UF

D3320
BAS16

C3318

20%
50V
2 CERM
402

2.2

6 7 29 31 32 33 34 35 36

CRITICAL
1

Q3311

PPVCORE_CPU

2
TH1

CRITICAL
SAMSUNG

5%
1/16W
MF
603

CORE_ISNS_M

5%
1/16W
MF
402

20%
16V
CERM
1206

R3306
1

10%
50V
2 CERM
402

1UF

OUT2

6 33

PN1

NOSTUFF

C3314

PP12V_CPU

MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

NOSTUFF

5%
1/16W
MF
402

5%
1/16W
MF
402

R3338
1

NOSTUFF
NEAR SIDE

VCORE_SENSE_VOUT

5%
1/16W
MF
402
NOSTUFF

CONNECT BETWEEN THE INDUCTOR & BULK CAPS.

PLACE REGULATOR SENSE POINTS AT DESIGNATED LOCATIONS.

R3335

OMIT

XW3302
SM

10% 16V
X7R 402

R3327
1

PN1

33

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

U3320_DRN

s
p
to

6 33

10%
10V
CERM
402

XW3300
SM
1

0.068UF

OMIT

SC2643_AGND

DIFFERENTIAL PAIR

C3308
1

33

R3304

33

CRITICAL

L3310

0.6UH-24A

0.0022UF

U3320_BST_R

1%
1/16W
MF
2 402

VCORE_SENSE_GND

33

33

20.5K

10%
16V
2 CERM
402

m
e
h
c

R3302

AUX1

U3310_BG

33

33

SC2643_OS4
NOSTUFF

C3313

20%
16V
2 CERM
1206

TO-252

5%
1/16W
MF

5%
1/16W
MF
2 402

1UF

33

SUD50N03

2 402

100

2.7M 2

5%
1/16W
MF
402

VPN1

6 7 10 11 13

CRITICAL
SAMSUNG

10K

SOT23

1210

R3350

R3310

10%
2 6.3V
CERM
402

NOSTUFF

330PF

20.5K

1%
1/16W
MF
2 402

c
.
s
it c
1

1UF

C3302_1

R3323

20.5K

1%
1/16W
MF
2 402

SYS_POWERUP_L

VPN 5

10%
16V

2 CERM

Q3310

U3310_TG

THMPAD

5%
1/16W
MF
603

30K

33

R3317

20.5K

1%
1/16W
MF
2 402

NOSTUFF

R3301

20.5K

SM

TG 2

3 BST

D3310
BAS16

2N7002

C3301

SC2643_AGND

18

AUX4

U3310_BST

Q3312

R3303

34

5%
1/16W
MF
603

R3313

VRM_EN

FB 7

SC2643_AGND

1.5K 2

SC2643_DACSTEP

1%
1/16W
MF
2 402

5%
1/16W
MF
402

232K

AUX3

R3300

BG 8

VREG 7

1 DRN

U3310_VREG

AGND

33

1UF

20%
2 16V
CERM
1206

34

R3328

C3329 R3307
2.2

33

34

SOIC

4 CO
1

SC2643_PGOOD

DACSTEP 8

OUT1

33

ERROUT 5

SC2643_OSCREF 17 OSCREF

AUX2

SC1211

C3312
10UF

20%
16V
ELEC
TH-KZJ

m
o

U3310
6 VIN

U3300_BGOUT

BGOUT 4

PP12V_CPU

34 33 6

CRITICAL
1

C3311
1000UF

25 27

33

23 OUTSEN

33

SYS_SLEWING_L 13

U3300

SC2643_OS1
SC2643_OS2
SC2643_OS3

AUX1

U3310_DRN

5%
1/16W
MF
402

9
VCC

20%
16V
2 CERM
1206

SC2643VX

8 6

PP12V_CPU

20%
16V
CERM
1206

R3330
1

SC2643_AGND

CRITICAL

5%
1/16W
MF
2 402

34 33 6

1UF
U3310_BST_R

10

PP12V_RUN_CPU
1

33

8 13 33 36

6 36

PP12V_CPU

C3410

1UF
U3410_BST_R

C3411

1000UF

20%
16V
ELEC
TH-KZJ

20%
16V
ELEC
TH-KZJ

20%
16V
CERM
1206

C3412

1000UF

5
6 33 34

C3468
10UF
10%
16V

36 35 34 33 32 31 29 7 6

PPVCORE_CPU

2 CERM
1210

m
o

U3410_DRN

C3433
10UF

20%
6.3V
2 CERM
1206

U3410

34 33 6

33

SC1211

PP12V_CPU

6 VIN

OUT3

4 CO

R3423
1
1

C3470

2.2

20%
2 16V
CERM
1206

BG 8

1 DRN

TG 2

3 BST

VPN 5

Q3410

U3410_TG

SUD50N03

U3410_BST

TO-252

L3410

R3450
10K

THMPAD
9

D3410
BAS16

SOT23

0.6UH-24A

5%
1/16W
MF
2 402

R3410

SAMSUNG
D

VREG 7

5%
1/16W
MF
603

1UF

SOIC

34

PN3

PPVCORE_CPU

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

TH1

VPN3

C3417

1800UF

5%
1/16W
MF
402

U3410_VREG

20%
2 6.3V
ELEC
TH-KZJ

SAMSUNG

C3418

1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3472

1800UF

20%
2 6.3V
ELEC
TH-KZJ

R3412

C3473
1800UF

20%
2 6.3V
ELEC
TH-KZJ

100
1

U3410_BG

C3413
1UF

20%
16V
2 CERM
1206

33

R3411
1

SUD70N03

5%
1/16W
MF
2 402

Q3411
TO-252

5%
1/10W
FF
2 805

NOSTUFF
1

C3415

AUX3

10%
2 50V
CERM
402
1

C3416
0.0047UF

10%
2 25V
CERM
402

C3414
0.001UF

20%
50V
2 CERM
402
34

m
e
h
c

PN3

PP12V_CPU

C3420

1UF
U3420_BST_R

2
2

U3420
33

PP12V_CPU

6 VIN

OUT4

4 CO

R3424
1
1

1UF

BG 8

TG 2

3 BST

VPN 5

U3420_BST

SUD50N03

U3420_VREG
VPN4

34

2 402

5%
1/16W
MF
402

R3422
100

U3420_BG

1UF

33

C3424

10%
2 50V
CERM
402

0.001UF

20%
50V
2 CERM
402

C3425

0.0022UF

AUX4

34

TO-252

NOSTUFF

20%
16V
2 CERM
1206

SUD70N03

.
w
w
w

C3423

PN4

SAMSUNG

Q3421

5%
1/16W
MF
2 402

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

10UF

20%
16V
ELEC
TH-KZJ

10%
16V

2 CERM

s
p
to

PN4

p
la

C3469
1210

PPVCORE_CPU

TH1

C3427
1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3428
1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3474
1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3434

C3443
10UF

20%
6.3V
2 CERM
1206

C3444

10UF

C3445
10UF

20%
6.3V
2 CERM
1206

C3446

C3455
10UF

20%
6.3V
2 CERM
1206

C3456

C3457
10UF

20%
6.3V
2 CERM
1206

C3458
10UF

20%
2 6.3V
CERM
1206

C3437

20%
6.3V
2 CERM
1206

10UF

C3438

20%
2 6.3V
CERM
1206

C3441

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

C3442

20%
2 6.3V
CERM
1206

C3449

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

C3450

20%
2 6.3V
CERM
1206

10UF

20%
6.3V
2 CERM
1206

C3440

C3447
10UF

20%
6.3V
2 CERM
1206

C3448

C3454
10UF

20%
2 6.3V
CERM
1206

C3451
10UF

20%
6.3V
2 CERM
1206

C3452
10UF

20%
2 6.3V
CERM
1206

C3462

C3465
10UF

20%
6.3V
2 CERM
1206

C3466

10UF

C3401
10UF

20%
6.3V
2 CERM
1206

C3402

10UF

C3405
10UF

20%
6.3V
2 CERM
1206

C3406

10UF

C3409
10UF

20%
6.3V
2 CERM
1206

C3419
10UF

20%
2 6.3V
CERM
1206

C3464
10UF

20%
2 6.3V
CERM
1206

C3467
10UF

20%
6.3V
2 CERM
1206

C3400
10UF

20%
2 6.3V
CERM
1206

C3403
10UF

20%
6.3V
2 CERM
1206

10UF

20%
2 6.3V
CERM
1206

C3463

20%
6.3V
2 CERM
1206

10UF

20%
2 6.3V
CERM
1206

C3460

20%
2 6.3V
CERM
1206

10UF

20%
2 6.3V
CERM
1206

C3459

20%
6.3V
2 CERM
1206

10UF

20%
2 6.3V
CERM
1206

10UF

20%
2 6.3V
CERM
1206

C3453

10UF

10UF

10UF

C3439

20%
2 6.3V
CERM
1206

10UF

C3436

C3461

20%
6.3V
2 CERM
1206

10UF

10UF

C3435

20%
2 6.3V
CERM
1206

10UF

C3430

10UF

10UF

C3429

20%
6.3V
2 CERM
1206

20%
2 6.3V
CERM
1206

10UF

10UF

20%
2 6.3V
CERM
1206

10UF

10UF

20%
2 6.3V
CERM
1206

C3432

20%
2 6.3V
CERM
1206

10UF

20%
2 6.3V
CERM
1206

C3431

20%
6.3V
2 CERM
1206

10UF

20%
2 6.3V
CERM
1206

0.6UH-24A

5%
1/16W
MF

R3420

6 33 34

L3420

R3451
10K

SOT23

TO-252

THMPAD

D3420
BAS16

SAMSUNG

Q3420

U3420_TG
G

VREG 7

1 DRN

5%
1/16W
MF
603

C3471

20%
16V
2 CERM
1206

2.2

SOIC

C3422
1000UF

20%
16V
ELEC
TH-KZJ

U3420_DRN

34 33 6

C3421
1000UF

20%
16V
CERM
1206

SC1211

C3416_1

0.0022UF

c
.
s
it c

6 7 29 31 32 33 34 35 36

D
1

C3404
10UF

20%
2 6.3V
CERM
1206

C3407
10UF

20%
6.3V
2 CERM
1206

C3408
10UF

20%
2 6.3V
CERM
1206

6 7 29 31 32 33 34 35 36

C3475

1800UF

20%
2 6.3V
ELEC
TH-KZJ

R3421
1

5%
1/10W
FF
2 805

C3426_1

TABLE_5_HEAD

PART#

C3426

0.0047UF

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

10%
2 25V
CERM
402

376S0130

ON SEMI FETS

Q3410,Q3420

CRITICAL

HYNIX

376S0146

ON SEMI FETS

Q3411,Q3421

CRITICAL

HYNIX

TABLE_5_ITEM

D
36 35 34 33 32 31 29 7 6

CRITICAL

C3500
10UF

20%
6.3V
2 CERM
1206

PPVCORE_CPU

20%
2 6.3V
CERM
1206

DS3502
SM
1

2
1

10BQ040

C3524
10UF

10BQ040

20%
6.3V
2 CERM
1206

NOSTUFF

DS3501
SM
2

C3513
10UF

31

NOSTUFF

DS3500
SM

C3512
10UF

20%
6.3V
2 CERM
1206

1
1

C3535
10UF

10BQ040

20%
2 6.3V
CERM
1206

C3511
10UF

20%
2 6.3V
CERM
1206

C3522
10UF

20%
6.3V
2 CERM
1206

10UF

20%
2 6.3V
CERM
1206

C3546
10UF

20%
6.3V
2 CERM
1206

C3557
10UF

20%
2 6.3V
CERM
1206

p
la

.
w
w
w
8

s
p
to

C3568
10UF

20%
6.3V
2 CERM
1206

C3579
10UF

20%
2 6.3V
CERM
1206

C3590
10UF

20%
6.3V
2 CERM
1206

C3544
10UF

20%
6.3V
2 CERM
1206

C3555
10UF

20%
2 6.3V
CERM
1206

C3566
10UF

20%
6.3V
2 CERM
1206

C3577
10UF

20%
2 6.3V
CERM
1206

C3588
10UF

20%
6.3V
2 CERM
1206

c
.
s
it c

C3523
10UF

20%
6.3V
2 CERM
1206

C3510
10UF

20%
2 6.3V
CERM
1206

C3521
10UF

20%
6.3V
2 CERM
1206

C3533

m
e
h
c

6 7 29 31 32 33 34 35 36

PP1V2_EI_CPU
PP2V5_RUN_CPU_AVDD_R

m
o

PPVCORE_CPU

31 30 29 18 7

C3532
10UF

20%
2 6.3V
CERM
1206

C3543
10UF

20%
6.3V
2 CERM
1206

C3554
10UF

20%
2 6.3V
CERM
1206

C3565
10UF

20%
6.3V
2 CERM
1206

C3576
10UF

20%
2 6.3V
CERM
1206

C3587
10UF

20%
6.3V
2 CERM
1206

C3534
10UF

20%
6.3V
2 CERM
1206

C3509
10UF

20%
2 6.3V
CERM
1206

C3520
10UF

20%
6.3V
2 CERM
1206

C3531
10UF

20%
2 6.3V
CERM
1206

C3542
10UF

20%
6.3V
2 CERM
1206

C3553
10UF

20%
2 6.3V
CERM
1206

C3564
10UF

20%
6.3V
2 CERM
1206

C3575
10UF

20%
2 6.3V
CERM
1206

C3586
10UF

20%
6.3V
2 CERM
1206

C3545
10UF

20%
6.3V
2 CERM
1206

C3508
10UF

20%
2 6.3V
CERM
1206

C3519
10UF

20%
6.3V
2 CERM
1206

C3530
10UF

20%
2 6.3V
CERM
1206

C3541
10UF

20%
6.3V
2 CERM
1206

C3552
10UF

20%
2 6.3V
CERM
1206

C3563
10UF

20%
6.3V
2 CERM
1206

C3574
10UF

20%
2 6.3V
CERM
1206

C3585
10UF

20%
6.3V
2 CERM
1206

C3501
10UF

20%
6.3V
2 CERM
1206

C3507
10UF

20%
2 6.3V
CERM
1206

C3518
10UF

20%
6.3V
2 CERM
1206

C3529
10UF

20%
2 6.3V
CERM
1206

C3540
10UF

20%
6.3V
2 CERM
1206

C3551
10UF

20%
2 6.3V
CERM
1206

C3562
10UF

20%
6.3V
2 CERM
1206

C3573
10UF

20%
2 6.3V
CERM
1206

C3584
10UF

20%
6.3V
2 CERM
1206

C3589
10UF

20%
6.3V
2 CERM
1206

C3506
10UF

20%
2 6.3V
CERM
1206

C3517
10UF

20%
6.3V
2 CERM
1206

C3528
10UF

20%
2 6.3V
CERM
1206

C3539
10UF

20%
6.3V
2 CERM
1206

C3550
10UF

20%
2 6.3V
CERM
1206

C3561
10UF

20%
6.3V
2 CERM
1206

C3572
10UF

20%
2 6.3V
CERM
1206

C3583
10UF

20%
6.3V
2 CERM
1206

C3578
10UF

20%
6.3V
2 CERM
1206

C3505
10UF

20%
2 6.3V
CERM
1206

C3516
10UF

20%
6.3V
2 CERM
1206

C3527
10UF

20%
2 6.3V
CERM
1206

C3538
10UF

20%
6.3V
2 CERM
1206

C3549
10UF

20%
2 6.3V
CERM
1206

C3560
10UF

20%
6.3V
2 CERM
1206

C3571
10UF

20%
2 6.3V
CERM
1206

C3582
10UF

20%
6.3V
2 CERM
1206

D
1

C3567
10UF

20%
6.3V
2 CERM
1206

C3504
10UF

20%
2 6.3V
CERM
1206

C3515
10UF

20%
6.3V
2 CERM
1206

C3526
10UF

20%
2 6.3V
CERM
1206

C3537
10UF

20%
6.3V
2 CERM
1206

C3548
10UF

20%
2 6.3V
CERM
1206

C3559
10UF

20%
6.3V
2 CERM
1206

C3570
10UF

20%
2 6.3V
CERM
1206

C3581
10UF

20%
6.3V
2 CERM
1206

C3556
10UF

20%
6.3V
2 CERM
1206

C3503
10UF

20%
2 6.3V
CERM
1206

C3514
10UF

20%
6.3V
2 CERM
1206

C3525
10UF

20%
2 6.3V
CERM
1206

C3536
10UF

20%
6.3V
2 CERM
1206

C3547
10UF

20%
2 6.3V
CERM
1206

C3558
10UF

20%
6.3V
2 CERM
1206

C3569
10UF

20%
2 6.3V
CERM
1206

C3580
10UF

20%
6.3V
2 CERM
1206

B
1

C3502
10UF

20%
2 6.3V
CERM
1206

C3599
10UF

20%
2 6.3V
CERM
1206

C3598
10UF

20%
2 6.3V
CERM
1206

C3597
10UF

20%
2 6.3V
CERM
1206

C3596
10UF

20%
2 6.3V
CERM
1206

C3595
10UF

20%
2 6.3V
CERM
1206

C3594
10UF

20%
2 6.3V
CERM
1206

C3593
10UF

20%
2 6.3V
CERM
1206

C3592
10UF

20%
2 6.3V
CERM
1206

C3591
10UF

20%
2 6.3V
CERM
1206

30 31 36

m
o

PP5V_RUN_CPU
7

PP5V_PWRON_CPU

R3602

DEVELOPMENT

36

R3600

2.2UF

2.2UF

C3605

2.2UF

20%
10V
2 CERM
805

20%
10V
2 CERM
805

C3600

30 31 36

C3603 1 C3604

XW3601
SM
1

DAVDD

MIN_LINE_WIDTH=15MIL

MIN_NECK_WIDTH=10MIL

5%
1/16W
MF
603

2.2UF

20%
10V
2 CERM
805

20%
10V
2 CERM
805

DAGND

36

MIN_NECK_WIDTH=10MIL

LED3600P1

PP5V_RUN_CPU

XW3600 MUST BE PLACED CLOSE TO SMU

100UA CURRENT SOURCE

DEVELOPMENT

DAGND 1

10K

THESE SIGNALS HAVE A MIN_LINE_WIDTH=10MIL

AND MIN_NECK_WIDTH=8MIL

LM393

10K

2 TD_CURRENT
TD11
10MIL 0.1%
8MIL 1/16W
FF
603

0.1%
1/16W
FF
603

36

36

U3601

36

ADC_REF 1

20K

DAGND

R3608
12.7K

36

U3602

R3607
DAGND 1

20K

10K
0.1%
1/16W
FF
2 603

0.1%
1/16W
FF
603

36

R3605
1
10MIL

8MIL

10K

36

MIN_LINE_WIDTH=10MIL
0.1%
1/16W
FF
603

C3607

MIN_NECK_WIDTH=8MIL

10UF
1

R3609
1

10K

R3611
158K 2

TD3

20%
6.3V
CERM
805

10MIL
0.1%
1/16W
FF
603

36

TDIODE_POS
1

C3610

0.0022UF

36 31 6

36.5K2

R3610

1K

1%
1/16W
MF
2 402

10%
50V
2 CERM
402

TDIODE_NEG

R3615
0

ADC_REF

36.5K2
1

DAGND

p
la
158K 2
1

TD4

10MIL

8MIL

1%
1/16W
MF
603

C3608
10UF
1

.
w
w
w
6

J3600

BM12B-SRSS-TB
F-ST-SM
14

1
2
3

4
5

7
8
9

10
11
12

13

ADC_REF

CPU_TEMP

SM
Q3600_B 1

SOURCE

VOLT SCALE

U21 TEMPERATURE
PROC TEMPERATURE
12V CURRENT
PROC VOLTAGE

50C/V
5A/V
1V/V

COUNT SCALE
0.25
C/CNT
0.125 C/CNT
0.01221A/CNT
0.00244V/CNT

13 36

MIN_LINE_WIDTH=10MIL

PP3V3_PWRON_CPU

MIN_NECK_WIDTH=8MIL

C3613
10UF

GND_SMU_AVSS

R3601

8 13 33

200

36

MIN_LINE_WIDTH=10MIL

R3690

PPVREF_SMU_ADC_REF 1

D3600

5%
1/16W
MF
402

2.5V

R3691
GND_SMU_AVSS_DAGND 1

0.47UF

DAGND

NOSTUFF

36 13

CPU_TEMP

51

5%
1/16W
MF
402

31 33

FMAXT_P
NO_TEST
DIFFERENTIAL_PAIR=P_FMAXT

NET_SPACING_TYPE=PROC_DIFF

36

36

DAGND

5%
1/16W
MF
402

TDIODE_NEG 6

R3619

5%
1/10W
FF
2 805

R3621
51

NOSTUFF
1

NOSTUFF

TDIODE_POS 31

36

NEEDED FOR FMAX

R3620

31 33

OMIT

C3602

20%
10V
2 CERM
603

5%
1/16W
MF
402

XW3614
SM

TDIODE_NEG_FMAX
DIFFERENTIAL_PAIR=TDIODE
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

SSOT-23

OMIT

2.2UF

20%
2 10V
CERM
805

ADC_REF

XW3613
SM
1

C3601

MIN_NECK_WIDTH=8MIL

KPGND2

1%
1/16W
MF
2 603

XW3612
SM
1

NEED TO CONNECT TO P65 OF 80PIN SMU OR PIN 49 OF 64PIN SMU

20%
2 6.3V
CERM
805

36

KPVDD2

POWER MONITOR

OMIT

TDIODE_POS_FMAX
DIFFERENTIAL_PAIR=TDIODE
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

100K 2

0
1
2
3

2N3906

XW3611
SM

KPGND2_FMAX
DIFFERENTIAL_PAIR=KP2_FMAX
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

CORE_ISNS_P
DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

CHANNEL

PLACE CLOSE
TO U2900
OMIT

KPVDD2_FMAX
DIFFERENTIAL_PAIR=KP2_FMAX
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

CORE_ISNS_M
DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

20%
6.3V
CERM
805

36

R3614

0.5%
1/16W
FF
603

NOSTUFF

s
p
to
R3628

CPU_TEMP_R

5%
1/16W
MF
402

R3613
36

5 LMV2011
SOT23-5

0.1%
1/16W
FF
603

5%
1/16W
MF
2 402

10K

DAVDD

U3603

0.5%
1/16W
FF
603

R3616

C3606

36

DAGND 1

1NOSTUFF

0.0022UF

10%
50V
2 CERM
402

1%
1/16W
MF
603

8MIL

R3612

34 33 32 31 29 7 6 PPVCORE_CPU
35
36 31

DAGND

DAGND
TD_BUFFERED

m
e
h
c

R3617

1K

Q3600

5%
1/16W
MF
402

1DEVELOPMENT

5 LMV2011
SOT23-5

36

GND

DAVDD

36

1%
1/16W
MF
2 603

DEVELOPMENT
1

TP_CMP_SPARE

1K

0.1%
1/16W
FF
2 603

TD23

0.1%
1/16W
FF
603

13 16 25 27

R3627

R3618

BUFFER

R3604

SYS_OVERTEMP_L

1DEVELOPMENT

5 LMV2011
SOT23-5

1
3

ADC_REF

DAVDD

LED3600P2

DEVELOPMENT

SOI

U3600P3

36

20%
2 10V
CERM
805

U3600

R3603

2
3

R3606

D3610
SM

C3609
2.2UF

V+

DEVELOPMENT

RED

DEVELOPMENT

c
.
s
it c
5%
1/16W
MF
2 402

MIN_LINE_WIDTH=15MIL

OMIT

100

FMAXT_M
NO_TEST
DIFFERENTIAL_PAIR=P_FMAXT

NET_SPACING_TYPE=PROC_DIFF

PLACE AT BOARD EDGE

31 36

6 33

6 33

U3LITES MAIN MEMORY INTERFACE CAN BE TURNED OFF IN SLEEP

PP2V5_RAM

R3702
PP1V5_PWRON_RAM_NB_AVDD

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

38
38
38
38
38
38
38
38
38
38
38

PP2V5_RAM

C3700
0.1UF

AB20 DDR_DQ4
AC21 DDR_DQ5
AD23 DDR_DQ6

DDR_DQ74 AD26
DDR_DQ75 AF27
DDR_DQ76 AC26

AG24 DDR_DQ13
AF23 DDR_DQ14
AH28 DDR_DQ15
U25 DDR_DQ16
AA23 DDR_DQ17

DDR_DQ77 AC25
DDR_DQ78 AC27

Y22 DDR_DQ18
AA22 DDR_DQ19
U24 DDR_DQ20

DDR_DQ82 AA24
DDR_DQ83 AA28
DDR_DQ84 Y26

DDR_DQ79 AD27
DDR_DQ80 AA27
DDR_DQ81 AA26

V23 DDR_DQ21
V22 DDR_DQ22
U22 DDR_DQ23

DDR_DQ85 Y25
DDR_DQ86 Y28
DDR_DQ87 Y24

P25 DDR_DQ24
R22 DDR_DQ25
R21 DDR_DQ26
U23 DDR_DQ27
P26 DDR_DQ28

DDR_DQ88 V26
DDR_DQ89 V27

R24 DDR_DQ29
P24 DDR_DQ30
P23 DDR_DQ31

DDR_DQ93 V28
DDR_DQ94 T28
DDR_DQ95 U26

M25 DDR_DQ32
M23 DDR_DQ33
P21 DDR_DQ34

DDR_DQ96 R27
DDR_DQ97 R26
DDR_DQ98 R28

P22 DDR_DQ35
M24 DDR_DQ36
L22 DDR_DQ37
L23 DDR_DQ38
J23 DDR_DQ39

DDR_DQ99 P27
DDR_DQ100 M28

D23 DDR_DQ40
D24 DDR_DQ41
C26 DDR_DQ42

DDR_DQ104 L25
DDR_DQ105 L26
DDR_DQ106 L27

C27 DDR_DQ43
A22 DDR_DQ44
A25 DDR_DQ45

DDR_DQ107 K28
DDR_DQ108 H27
DDR_DQ109 H28

C24 DDR_DQ46
C23 DDR_DQ47
B24 DDR_DQ48
B23 DDR_DQ49
A23 DDR_DQ50

DDR_DQ110 J27
DDR_DQ111 L24

A24 DDR_DQ51
A27 DDR_DQ52
A28 DDR_DQ53

DDR_DQ115 G28
DDR_DQ116 H25
DDR_DQ117 H24

B28 DDR_DQ54
A26 DDR_DQ55
F24 DDR_DQ56

DDR_DQ118 F27
DDR_DQ119 H26
DDR_DQ120 E28

J22 DDR_DQ57
E23 DDR_DQ58
H23 DDR_DQ59
J21 DDR_DQ60
H21 DDR_DQ61

DDR_DQ121 E27
DDR_DQ122 F26

DDR_DQ90 V24
DDR_DQ91 W28
DDR_DQ92 U27

DDR_DQ101 N28
DDR_DQ102 L28
DDR_DQ103 P28

DDR_DQ112 J25
DDR_DQ113 J24
DDR_DQ114 J26

C3702
0.1UF

20%
2 10V
CERM
402

C3703

20%
2 10V
CERM
402

A
PP2V5_RAM

C3715
0.1UF

20%
10V
2 CERM
402

7 26 37

C3716
0.1UF

20%
10V
2 CERM
402

C3717
0.1UF

20%
2 10V
CERM
402

C3718
0.1UF

20%
10V
2 CERM
402

.
w
w
w
DDR_DQ126 E25
DDR_DQ127 E24

0.1UF

20%
2 10V
CERM
402

C3719
0.1UF

20%
2 10V
CERM
402

C3704
0.1UF

C3720
0.1UF

20%
10V
2 CERM
402

C3705
0.1UF

20%
2 10V
CERM
402

C3721
0.1UF

20%
2 10V
CERM
402

C3706
0.1UF

20%
2 10V
CERM
402

38

DDR
CLK_AVDD

38

38

27

38

38

0.1UF

20%
10V
2 CERM
402

38
38

38
38
38
38
38
38
38
38

CLK<D..F>
GO TO J4001

38
38

38
38

38
38
38
38
38
38

38

CKE<1..0>
GO TO J4000

38

38
38

38
6
38
6
38

CKE<5..4>
GO TO J4001

38

38
38

AC20 DDR_CLKP

RAM_CLK_A_P_R
RAM_CLK_A_N_R
RAM_CLK_B_P_R
RAM_CLK_B_N_R
RAM_CLK_C_P_R
RAM_CLK_C_N_R
RAM_CLK_D_P_R
RAM_CLK_D_N_R
RAM_CLK_E_P_R
RAM_CLK_E_N_R
RAM_CLK_F_P_R
RAM_CLK_F_N_R

AA12 DDR_CK_A
AB12 DDR_CK_AN
AB14 DDR_CK_B
AA14 DDR_CK_BN

38

38
38
38
38

PP2V5_RAM

38
38

R37001

38

1K

1%
1/16W
MF
402 2

38
38
38

B25

D22
D27

F19

K27
G25

K19
K23

PBGA

(SYM 3 OF 7)

7 26 37

R37011

38

1K

38

s
p
to
1%
1/16W
MF
402 2

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

C3730

0.1UF

20%
10V
2 CERM
402

C3746

0.1UF

20%
2 10V
CERM
402

C3747

0.1UF

20%
10V
2 CERM
402

38

RAM_BA_R<0>
RAM_BA_R<1>

38

TP_RAM_MUXEN0
TP_RAM_MUXEN4

DDR_MAD0 AG12
DDR_MAD1 AH13
DDR_MAD2 AH14
DDR_MAD3 AH15

RAM_A_R<0>
RAM_A_R<1>
RAM_A_R<2>
RAM_A_R<3>
RAM_A_R<4>
RAM_A_R<5>
RAM_A_R<6>
RAM_A_R<7>
RAM_A_R<8>
RAM_A_R<9>
RAM_A_R<10>
RAM_A_R<11>
RAM_A_R<12>
RAM_A_R<13>

DDR_MAD4 AF12
DDR_MAD5 AE12
DDR_MAD6 AD12
DDR_MAD7 AC12
DDR_MAD8 AG15
DDR_MAD9 AF15

DDR_MAD10 AF14
DDR_MAD11 AG14

AA18 DDR_CKE7

DDR_MAD12 AH17
DDR_MAD13 AG17

Y21 DDR_VREF0
U21 DDR_VREF1
L21 DDR_VREF2
H20 DDR_VREF3

DDR_CS0 AF18
DDR_CS1 AE18
DDR_CS2 AG20

AA21 DDR_VREF4
M21 DDR_VREF5
V21 DDR_VREF6

RAM_CS_L_R<0>
RAM_CS_L_R<1>
TP_RAM_CS_L_R<2>
TP_RAM_CS_L_R<3>
RAM_CS_L_R<8>
RAM_CS_L_R<9>
TP_RAM_CS_L_R<10>
TP_RAM_CS_L_R<11>

DDR_CS3 AH20
DDR_CS8 AC18
DDR_CS9 AD18

J20 DDR_VREF7

DDR_CS10 AG18
DDR_CS11 AH19

VOLTAGE=1.25V

38

38

RAM_WE_L_R

DDR_MUXEN0 AH16
DDR_MUXEN4 AH18

AF17 DDR_CKE3
AB17 DDR_CKE4
AA17 DDR_CKE5
AB18 DDR_CKE6

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

38

RAM_CAS_L_R

DDR_BA0 AF21
DDR_BA1 AE20

AC17 DDR_CKE0
AD17 DDR_CKE1
AE17 DDR_CKE2

RAM_RAS_L_R

DDR_CAS AD20
DDR_WE AC23

MEMORY
CONTROL
INTERFACE

C3748
0.1UF

DDR_DQSP0 AC24
DDR_DQSP1 AG23

20%
2 10V
CERM
402

DDR_RAS AE21

OMIT

AD14 DDR_CK_DN
AD15 DDR_CK_E
AC15 DDR_CK_EN
AA15 DDR_CK_F
AB15 DDR_CK_FN

RAM_CKE_R<0>
RAM_CKE_R<1>
TP_RAM_CKE_R<2>
TP_RAM_CKE_R<3>
RAM_CKE_R<4>
RAM_CKE_R<5>
TP_RAM_CKE_R<6>
TP_RAM_CKE_R<7>

PP1V25_RAM_VREF_NB

U3LITE
V1.0-300MM

AE15 DDR_CK_C
AE14 DDR_CK_CN
AC14 DDR_CK_D

m
e
h
c

38

c
.
s
it c

RAM_CLK66M_NB

38

RAM_DQS_R<0>
RAM_DQS_R<1>
RAM_DQS_R<2>
RAM_DQS_R<3>
RAM_DQS_R<4>
RAM_DQS_R<5>
RAM_DQS_R<6>
RAM_DQS_R<7>
RAM_DQS_R<8>
RAM_DQS_R<9>
RAM_DQS_R<10>
RAM_DQS_R<11>
RAM_DQS_R<12>
RAM_DQS_R<13>
RAM_DQS_R<14>
RAM_DQS_R<15>

DDR_DQSP2 Y23
DDR_DQSP3 R23
DDR_DQSP4 M22
DDR_DQSP5 B26
DDR_DQSP6 B27
DDR_DQSP7 F23
DDR_DQSP8 AE23
DDR_DQSP9 AD28
DDR_DQSP10 Y27
DDR_DQSP11 U28
DDR_DQSP12 M27
DDR_DQSP13 J28
DDR_DQSP14 F28
DDR_DQSP15 F25

RAS / CAS / WE / BA<1..0>

GO TO BOTH DIMMS

38

6
6

38
38
38
38
38
38

ADDRESS LINES
GO TO BOTH DIMMS

38
38
38
38
38
38

38
38

38
38

CS<1..0>
GO TO J4000

6
6
38
38

CS<9..8>
GO TO J4001

6
6

38
38
38
38

DQS<7..0>

38

GO TO J4000
38
38
38
38
38
38
38

DQS<15..8>
GO TO J4001

38
38
38

38

DDR_CLK_AVSS

38
38

C3707

C3708
0.1UF

20%
2 10V
CERM
402

C3722

38

CLK<A..C>
GO TO J4000

38

0.1UF

20%
2 10V
CERM
402

m
o

VDD_DDR

U3

38

p
la

DDR_DQ123 E26
DDR_DQ124 D28
DDR_DQ125 C28

G21 DDR_DQ62
H22 DDR_DQ63

C3701

DDR_DQ71 AG28
DDR_DQ72 AF28
DDR_DQ73 AE28

AH24 DDR_DQ10
AH23 DDR_DQ11
AH27 DDR_DQ12

7 26 37

RAM_DQ_R<64>
RAM_DQ_R<65>
RAM_DQ_R<66>
RAM_DQ_R<67>
RAM_DQ_R<68>
RAM_DQ_R<69>
RAM_DQ_R<70>
RAM_DQ_R<71>
RAM_DQ_R<72>
RAM_DQ_R<73>
RAM_DQ_R<74>
RAM_DQ_R<75>
RAM_DQ_R<76>
RAM_DQ_R<77>
RAM_DQ_R<78>
RAM_DQ_R<79>
RAM_DQ_R<80>
RAM_DQ_R<81>
RAM_DQ_R<82>
RAM_DQ_R<83>
RAM_DQ_R<84>
RAM_DQ_R<85>
RAM_DQ_R<86>
RAM_DQ_R<87>
RAM_DQ_R<88>
RAM_DQ_R<89>
RAM_DQ_R<90>
RAM_DQ_R<91>
RAM_DQ_R<92>
RAM_DQ_R<93>
RAM_DQ_R<94>
RAM_DQ_R<95>
RAM_DQ_R<96>
RAM_DQ_R<97>
RAM_DQ_R<98>
RAM_DQ_R<99>
RAM_DQ_R<100>
RAM_DQ_R<101>
RAM_DQ_R<102>
RAM_DQ_R<103>
RAM_DQ_R<104>
RAM_DQ_R<105>
RAM_DQ_R<106>
RAM_DQ_R<107>
RAM_DQ_R<108>
RAM_DQ_R<109>
RAM_DQ_R<110>
RAM_DQ_R<111>
RAM_DQ_R<112>
RAM_DQ_R<113>
RAM_DQ_R<114>
RAM_DQ_R<115>
RAM_DQ_R<116>
RAM_DQ_R<117>
RAM_DQ_R<118>
RAM_DQ_R<119>
RAM_DQ_R<120>
RAM_DQ_R<121>
RAM_DQ_R<122>
RAM_DQ_R<123>
RAM_DQ_R<124>
RAM_DQ_R<125>
RAM_DQ_R<126>
RAM_DQ_R<127>

DDR_DQ68 AF26
DDR_DQ69 AD24
DDR_DQ70 AD25

MEMORY
DATA
INTERFACE

AD21 DDR_DQ7
AH26 DDR_DQ8
AH25 DDR_DQ9

0.1UF

20%
2 10V
CERM
402

DDR_DQ64 AG27
DDR_DQ65 AF24
DDR_DQ66 AE24
DDR_DQ67 AG26

OMIT

20%
2 10V
CERM
402

7 26 37

AA20

38

(SYM 2 OF 7)

PP2V5_RAM

C3744
0.1UF

10%
2 6.3V
CERM
402

PBGA

AF20 DDR_DQ0
AH22 DDR_DQ1
AH21 DDR_DQ2
AG21 DDR_DQ3

RAM_DQ_R<0>
RAM_DQ_R<1>
RAM_DQ_R<2>
RAM_DQ_R<3>
RAM_DQ_R<4>
RAM_DQ_R<5>
RAM_DQ_R<6>
RAM_DQ_R<7>
RAM_DQ_R<8>
RAM_DQ_R<9>
RAM_DQ_R<10>
RAM_DQ_R<11>
RAM_DQ_R<12>
RAM_DQ_R<13>
RAM_DQ_R<14>
RAM_DQ_R<15>
RAM_DQ_R<16>
RAM_DQ_R<17>
RAM_DQ_R<18>
RAM_DQ_R<19>
RAM_DQ_R<20>
RAM_DQ_R<21>
RAM_DQ_R<22>
RAM_DQ_R<23>
RAM_DQ_R<24>
RAM_DQ_R<25>
RAM_DQ_R<26>
RAM_DQ_R<27>
RAM_DQ_R<28>
RAM_DQ_R<29>
RAM_DQ_R<30>
RAM_DQ_R<31>
RAM_DQ_R<32>
RAM_DQ_R<33>
RAM_DQ_R<34>
RAM_DQ_R<35>
RAM_DQ_R<36>
RAM_DQ_R<37>
RAM_DQ_R<38>
RAM_DQ_R<39>
RAM_DQ_R<40>
RAM_DQ_R<41>
RAM_DQ_R<42>
RAM_DQ_R<43>
RAM_DQ_R<44>
RAM_DQ_R<45>
RAM_DQ_R<46>
RAM_DQ_R<47>
RAM_DQ_R<48>
RAM_DQ_R<49>
RAM_DQ_R<50>
RAM_DQ_R<51>
RAM_DQ_R<52>
RAM_DQ_R<53>
RAM_DQ_R<54>
RAM_DQ_R<55>
RAM_DQ_R<56>
RAM_DQ_R<57>
RAM_DQ_R<58>
RAM_DQ_R<59>
RAM_DQ_R<60>
RAM_DQ_R<61>
RAM_DQ_R<62>
RAM_DQ_R<63>

38

M19

U3
38

C3745
1UF

U3LITE
V1.0-300MM

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

VOLTAGE=1.5V

N21
N25

VDD_DDR

P20

5%
1/16W
MF
603

T21
T25

2.2

T19

PP1V5_PWRON_NB_AVDD

W27
V20

W23

AA16

Y16
Y19

AB25
AA13

AC19

AE22
AE27

AE13
AE16

AG25

AG19

60 48 28 7

AB21

37 26 7

U3TWINS DO NOT HAVE MASKS

C3709
0.1UF

20%
2 10V
CERM
402

C3710
0.1UF

20%
2 10V
CERM
402

C3711
0.1UF

20%
2 10V
CERM
402

C3712
0.1UF

20%
2 10V
CERM
402

C3713
0.1UF

20%
2 10V
CERM
402

C3714
0.1UF

20%
2 10V
CERM
402

C3731
0.1UF

20%
10V
2 CERM
402

20%
2 10V
CERM
402

C3732
0.1UF

C3733
0.1UF

20%
2 10V
CERM
402

C3734
0.1UF

20%
2 10V
CERM
402

C3735
0.1UF

20%
10V
2 CERM
402

20%
2 10V
CERM
402

C3736
0.1UF

20%
10V
2 CERM
402

C3737
0.1UF

20%
2 10V
CERM
402

A
1

C3724
0.1UF

20%
10V
2 CERM
402

C3725
0.1UF

20%
2 10V
CERM
402

C3726
0.1UF

C3727
0.1UF

20%
10V
2 CERM
402

20%
2 10V
CERM
402

C3728
0.1UF

20%
10V
2 CERM
402

C3729
0.1UF

20%
2 10V
CERM
402

C3743
0.1UF

20%
10V
2 CERM
402

C3742
0.1UF

20%
2 10V
CERM
402

C3740
0.1UF

20%
2 10V
CERM
402

C3739
0.1UF

20%
10V
2 CERM
402

C3738
0.1UF

20%
2 10V
CERM
402

38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37

38 37
38 37
38 37
38 37

RAM_DQ_R<7>
RAM_DQ_R<2>
RAM_DQ_R<0>
RAM_DQ_R<3>
RAM_DQ_R<1>
RAM_DQ_R<4>
RAM_DQ_R<6>
RAM_DQ_R<5>
RAM_DQ_R<9>
RAM_DQ_R<10>
RAM_DQ_R<11>
RAM_DQ_R<14>
RAM_DQ_R<12>
RAM_DQ_R<13>
RAM_DQ_R<15>
RAM_DQ_R<8>
RAM_DQ_R<17>
RAM_DQ_R<22>
RAM_DQ_R<19>
RAM_DQ_R<18>
RAM_DQ_R<20>
RAM_DQ_R<16>
RAM_DQ_R<21>
RAM_DQ_R<23>
RAM_DQ_R<30>
RAM_DQ_R<26>
RAM_DQ_R<24>
RAM_DQ_R<27>
RAM_DQ_R<28>
RAM_DQ_R<31>
RAM_DQ_R<29>
RAM_DQ_R<25>
RAM_DQ_R<32>
RAM_DQ_R<35>
RAM_DQ_R<38>
RAM_DQ_R<37>
RAM_DQ_R<39>
RAM_DQ_R<33>
RAM_DQ_R<34>
RAM_DQ_R<36>
RAM_DQ_R<47>
RAM_DQ_R<46>
RAM_DQ_R<43>
RAM_DQ_R<41>
RAM_DQ_R<45>
RAM_DQ_R<42>
RAM_DQ_R<40>
RAM_DQ_R<44>
RAM_DQ_R<51>
RAM_DQ_R<50>
RAM_DQ_R<49>
RAM_DQ_R<48>
RAM_DQ_R<52>
RAM_DQ_R<53>
RAM_DQ_R<54>
RAM_DQ_R<55>
RAM_DQ_R<56>
RAM_DQ_R<63>
RAM_DQ_R<59>
RAM_DQ_R<61>
RAM_DQ_R<57>
RAM_DQ_R<60>
RAM_DQ_R<58>
RAM_DQ_R<62>

RP3836
RP3836
RP3836
RP3836
RP3816
RP3816
RP3816
RP3816
RP3835
RP3801
RP3801
RP3801
RP3835
RP3801
RP3835
RP3835
RP3822
RP3822
RP3822
RP3822
RP3823
RP3823
RP3823
RP3823
RP3808
RP3824
RP3808
RP3824
RP3808
RP3808
RP3824
RP3824
RP3826
RP3807
RP3826
RP3807
RP3826
RP3807
RP3807
RP3826
RP3811
RP3811
RP3814
RP3814
RP3811
RP3814
RP3814
RP3811
RP3830
RP3830
RP3830
RP3830
RP3812
RP3812
RP3812
RP3812
RP3813
RP3831
RP3813
RP3831
RP3831
RP3831
RP3813
RP3813

ELECTRICAL_CONSTRAINT_SET
4

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

RAM_DQ<7>
RAM_DQ<2>
RAM_DQ<0>
RAM_DQ<3>
RAM_DQ<1>
RAM_DQ<4>
RAM_DQ<6>
RAM_DQ<5>
RAM_DQ<9>
RAM_DQ<10>
RAM_DQ<11>
RAM_DQ<14>
RAM_DQ<12>
RAM_DQ<13>
RAM_DQ<15>
RAM_DQ<8>
RAM_DQ<17>
RAM_DQ<22>
RAM_DQ<19>
RAM_DQ<18>
RAM_DQ<20>
RAM_DQ<16>
RAM_DQ<21>
RAM_DQ<23>
RAM_DQ<30>
RAM_DQ<26>
RAM_DQ<24>
RAM_DQ<27>
RAM_DQ<28>
RAM_DQ<31>
RAM_DQ<29>
RAM_DQ<25>
RAM_DQ<32>
RAM_DQ<35>
RAM_DQ<38>
RAM_DQ<37>
RAM_DQ<39>
RAM_DQ<33>
RAM_DQ<34>
RAM_DQ<36>
RAM_DQ<47>
RAM_DQ<46>
RAM_DQ<43>
RAM_DQ<41>
RAM_DQ<45>
RAM_DQ<42>
RAM_DQ<40>
RAM_DQ<44>
RAM_DQ<51>
RAM_DQ<50>
RAM_DQ<49>
RAM_DQ<48>
RAM_DQ<52>
RAM_DQ<53>
RAM_DQ<54>
RAM_DQ<55>
RAM_DQ<56>
RAM_DQ<63>
RAM_DQ<59>
RAM_DQ<61>
RAM_DQ<57>
RAM_DQ<60>
RAM_DQ<58>
RAM_DQ<62>

THE FOLLOWING IS A SWAPPABLE GROUP

RP3841 3
6
15
RAM_CKE_R<4>
RAM_CKE<4>
RP3841 4
5
15
RAM_CKE_R<5>
RAM_CKE<5>
RP3841
2
7
15
RAM_CKE_R<0>
RAM_CKE<0>
RP3841 1
8
15
RAM_CKE_R<1>
RAM_CKE<1>

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37
38 37

38 40 44
38 40 44

38 37

38 40 44

38 37
38 37

38 40 44
38 40 44

38 37
38 37

38 40 44

38 37

38 40 44
38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37
38 37

38 40 44
38 40 44

38 37
38 37

38 40 44
38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37
38 37

38 40 44

38 37

38 40 44
38 40 44

38 37

38 40 44

38 37
38 37

38 40 44
38 40 44

38 37

38 40 44

38 37
38 37

38 40 44
38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 37
38 37
38 37

RAM_CS_L_R<8>
RAM_CS_L_R<9>
RAM_CS_L_R<1>
RAM_CS_L_R<0>

RP3842
RP3842
RP3842
RP3842

15
15
15
15

38 40 44

38 37
38 40 44

38 40 45

38 37

38 40 45

38 37

38 40 44

38 37

38 40 44

38 37

38 37

38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37
38 37
38 37

38 37
38 37

THE FOLLOWING IS A SWAPPABLE GROUP

RP3832 3
6
15
RAM_A_R<11>
RAM_A<11>
RP3832 4
5
15
RAM_A_R<1>
RAM_A<1>
RP3832
2
7
15
RAM_A_R<10>
RAM_A<10>
RP3800 4
5
15
RAM_WE_L
RAM_WE_L_R
RP3833 3
6
15
RAM_A_R<4>
RAM_A<4>
RP3833
2
7
15
RAM_A_R<6>
RAM_A<6>
RP3833
1
8
15
RAM_A_R<7>
RAM_A<7>
1

RAM_A_R<12>
RAM_A_R<2>
RAM_A_R<0>
RAM_A_R<5>
RAM_A_R<13>
RAM_A_R<3>

RP3834
RP3800
RP3834
RP3833
RP3832
RP3800
RP3800

RAM_CAS_L_R
RAM_BA_R<0>

RP3804
RP3804

RAM_BA_R<1>
RAM_RAS_L_R
RAM_A_R<9>
RAM_A_R<8>

RP3804
RP3804
RP3834
RP3834

15
15
15
15
15
15
15

RAM_A<12>
RAM_A<2>
RAM_A<0>
RAM_A<5>
RAM_A<13>
RAM_A<3>

15
15

RAM_CAS_L
RAM_BA<0>

15
15
15
15

RAM_BA<1>
RAM_RAS_L
RAM_A<9>
RAM_A<8>

38 37

38 40 44

38 37

38 40 44

38 37

38 40 45

38 37

38 37

38 40 45

38 40 44

38 37

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 45

38 37

38 40 45

38 37
38 37

38 37
38 37
38 37
38 37

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

RAM_DQ<68>
RAM_DQ<65>
RAM_DQ<70>
RAM_DQ<66>
RAM_DQ<71>
RAM_DQ<64>
RAM_DQ<67>
RAM_DQ<69>
RAM_DQ<74>
RAM_DQ<73>
RAM_DQ<72>
RAM_DQ<75>
RAM_DQ<78>
RAM_DQ<79>
RAM_DQ<77>
RAM_DQ<76>
RAM_DQ<87>
RAM_DQ<86>
RAM_DQ<81>
RAM_DQ<80>
RAM_DQ<84>
RAM_DQ<85>
RAM_DQ<83>
RAM_DQ<82>
RAM_DQ<91>
RAM_DQ<93>
RAM_DQ<94>
RAM_DQ<90>
RAM_DQ<88>
RAM_DQ<89>
RAM_DQ<92>
RAM_DQ<95>
RAM_DQ<98>
RAM_DQ<96>
RAM_DQ<103>
RAM_DQ<97>
RAM_DQ<100>
RAM_DQ<99>
RAM_DQ<102>
RAM_DQ<101>
RAM_DQ<111>
RAM_DQ<106>
RAM_DQ<105>
RAM_DQ<108>
RAM_DQ<107>
RAM_DQ<110>
RAM_DQ<104>
RAM_DQ<109>
RAM_DQ<119>
RAM_DQ<112>
RAM_DQ<117>
RAM_DQ<118>
RAM_DQ<113>
RAM_DQ<115>
RAM_DQ<116>
RAM_DQ<114>
RAM_DQ<121>
RAM_DQ<124>
RAM_DQ<120>
RAM_DQ<123>
RAM_DQ<125>
RAM_DQ<122>
RAM_DQ<126>
RAM_DQ<127>

38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38

RAM_CLK_A_P_R
RAM_CLK_A_N_R
RAM_CLK_B_P_R
RAM_CLK_B_N_R
RAM_CLK_C_P_R
RAM_CLK_C_N_R
RAM_CLK_D_P_R
RAM_CLK_D_N_R
RAM_CLK_E_P_R
RAM_CLK_E_N_R
RAM_CLK_F_P_R
RAM_CLK_F_N_R

38 40 45
38 37
38 40 45
38 37
38 40 45
44 40 38
38 40 45
38 40 45

45 40 38
38 40 45

45 40 38
38 40 45

38 37
38 40 45

38 37
38 40 45

44 40 38

m
e
h
c
38 40 45

44 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45
38 40 45

38 37

38 40 45

38 37

38 40 45

45 44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38
45 40 38
45 40 38

15
15
15
15
15
15
15
15
15
15
15
15

RAM_CLK_A_P
RAM_CLK_A_N
RAM_CLK_B_P
RAM_CLK_B_N
RAM_CLK_C_P
RAM_CLK_C_N
RAM_CLK_D_P
RAM_CLK_D_N
RAM_CLK_E_P
RAM_CLK_E_N
RAM_CLK_F_P
RAM_CLK_F_N

45 40 38
45 40 38
38 40

45 40 38

38 40

45 40 38

38 40

45 40 38

38 40

45 40 38

38 40 45

38 37

38 40 45

38 37

38 40 44

38 37

38 40 44

38 37

R3800
R3801
R3802
R3803
R3804
R3805
R3806
R3807
R3808
R3809
R3810
R3811
R3812
R3813
R3814
R3815

38 40

38 37

38 40

38 37

38 40

38 37

38 40

38 37

38 40

38 37

38 40

45 44 40 38

38 40

45 40 38
45 40 38

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

RAM_DQS<0>
RAM_DQS<1>
RAM_DQS<2>
RAM_DQS<3>
RAM_DQS<4>
RAM_DQS<5>
RAM_DQS<6>
RAM_DQS<7>
RAM_DQS<8>
RAM_DQS<9>
RAM_DQS<10>
RAM_DQS<11>
RAM_DQS<12>
RAM_DQS<13>
RAM_DQS<14>
RAM_DQS<15>

RAM_DQS_R<15..0>
RAM_DQ_R<127..0>
RAM_DQ<127..0>
RAM_DQS<0>
RAM_DQ<7..0>
RAM_DQS<1>
RAM_DQ<15..8>
RAM_DQS<2>
RAM_DQ<23..16>
RAM_DQS<3>
RAM_DQ<31..24>
RAM_DQS<4>
RAM_DQ<39..32>
RAM_DQS<5>
RAM_DQ<47..40>
RAM_DQS<6>
RAM_DQ<55..48>
RAM_DQS<7>
RAM_DQ<63..56>
RAM_DQS<8>
RAM_DQ<71..64>
RAM_DQS<9>
RAM_DQ<79..72>
RAM_DQS<10>
RAM_DQ<87..80>
RAM_DQS<11>
RAM_DQ<95..88>
RAM_DQS<12>
RAM_DQ<103..96>
RAM_DQS<13>
RAM_DQ<111..104>
RAM_DQS<14>
RAM_DQ<119..112>
RAM_DQS<15>
RAM_DQ<127..120>

NET_SPACING_TYPE
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK

m
o

RAM_CKECS0
RAM_CKECS0
RAM_CKECS1
RAM_CKECS1

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_DQS0
RAM_DQS0
RAM_DQS1
RAM_DQS1
RAM_DQS2
RAM_DQS2
RAM_DQS3
RAM_DQS3
RAM_DQS4
RAM_DQS4
RAM_DQS5
RAM_DQS5
RAM_DQS6
RAM_DQS6
RAM_DQS7
RAM_DQS7
RAM_DQS8
RAM_DQS8
RAM_DQS9
RAM_DQS9
RAM_DQS10
RAM_DQS10
RAM_DQS11
RAM_DQS11
RAM_DQS12
RAM_DQS12
RAM_DQS13
RAM_DQS13
RAM_DQS14
RAM_DQS14
RAM_DQS15
RAM_DQS15

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_A_CTL
RAM_A_CTL
RAM_A_CTL
RAM_A_CTL
RAM_A_CTL

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_CKECS0
RAM_CKECS0
RAM_CKECS1
RAM_CKECS1

1
DIFFERENTIAL_PAIR
RAM_CLK_A_R
RAM_CLK_A_R
RAM_CLK_B_R
RAM_CLK_B_R
RAM_CLK_C_R
RAM_CLK_C_R
RAM_CLK_D_R
RAM_CLK_D_R
RAM_CLK_E_R
RAM_CLK_E_R
RAM_CLK_F_R
RAM_CLK_F_R
RAM_CLK_A
RAM_CLK_A
RAM_CLK_B
RAM_CLK_B
RAM_CLK_C
RAM_CLK_C
RAM_CLK_D
RAM_CLK_D
RAM_CLK_E
RAM_CLK_E
RAM_CLK_F
RAM_CLK_F

I206
I207
I208
I209
I210
I211
I212
I213
I214
I215
I216

I217
I218
I219
I220
I221
I222
I223
I224
I225
I226
I227
I228
I229

I230
I232
I234
I236
I235
I237
I238
I241
I243
I242
I245
I244
I305

I294
I293
I246
I248
I251
I252
I253
I254
I255
I256
I257
I258
I259
I260
I261
I262
I263
I264
I265
I267
I266
I268
I270
I269
I272
I271

I273
I275
I274
I277
I276
I278
I280
I279

38 40

45 40 38

RAM_DQS_R<0>
RAM_DQS_R<1>
RAM_DQS_R<2>
RAM_DQS_R<3>
RAM_DQS_R<4>
RAM_DQS_R<5>
RAM_DQS_R<6>
RAM_DQS_R<7>
RAM_DQS_R<8>
RAM_DQS_R<9>
RAM_DQS_R<10>
RAM_DQS_R<11>
RAM_DQS_R<12>
RAM_DQS_R<13>
RAM_DQS_R<14>
RAM_DQS_R<15>

RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK1
RAM_CLK1
RAM_CLK1
RAM_CLK1
RAM_CLK1
RAM_CLK1

NET_PHYSICAL_TYPE

c
.
s
it c

RAM_CKE_R<1..0>
RAM_CKE_R<5..4>
RAM_CKE<0>
RAM_CKE<1>
RAM_CKE<4>
RAM_CKE<5>
RAM_CS_L_R<1..0>
RAM_CS_L_R<9..8>
RAM_CS_L<0>
RAM_CS_L<1>
RAM_CS_L<8>
RAM_CS_L<9>

44 40 38

s
p
to

R3816
R3817
R3818
R3819
R3820
R3821
R3822
R3823
R3824
R3825
R3826
R3827

RAM_CLK_A_P_R
RAM_CLK_A_N_R
RAM_CLK_B_P_R
RAM_CLK_B_N_R
RAM_CLK_C_P_R
RAM_CLK_C_N_R
RAM_CLK_D_P_R
RAM_CLK_D_N_R
RAM_CLK_E_P_R
RAM_CLK_E_N_R
RAM_CLK_F_P_R
RAM_CLK_F_N_R
RAM_CLK_A_P
RAM_CLK_A_N
RAM_CLK_B_P
RAM_CLK_B_N
RAM_CLK_C_P
RAM_CLK_C_N
RAM_CLK_D_P
RAM_CLK_D_N
RAM_CLK_E_P
RAM_CLK_E_N
RAM_CLK_F_P
RAM_CLK_F_N

38 40 45

38 40 44

38 37

38 37

RP3818
RP3805
RP3818
RP3805
RP3818
RP3805
RP3805
RP3818
RP3817
RP3802
RP3817
RP3817
RP3802
RP3817
RP3802
RP3802
RP3806
RP3821
RP3821
RP3821
RP3806
RP3806
RP3821
RP3806
RP3819
RP3819
RP3803
RP3819
RP3803
RP3819
RP3803
RP3803
RP3820
RP3820
RP3820
RP3820
RP3825
RP3825
RP3825
RP3825
RP3809
RP3809
RP3809
RP3829
RP3829
RP3829
RP3809
RP3829
RP3828
RP3815
RP3815
RP3828
RP3815
RP3828
RP3828
RP3815
RP3827
RP3827
RP3827
RP3810
RP3827
RP3810
RP3810
RP3810

THE FOLLOWING ARE 0402 5% RESISTORS

38 40 45

.
w
w
w

RAM_CS_L<8>
RAM_CS_L<9>
RAM_CS_L<1>
RAM_CS_L<0>

RAM_DQ_R<68>
RAM_DQ_R<65>
RAM_DQ_R<70>
RAM_DQ_R<66>
RAM_DQ_R<71>
RAM_DQ_R<64>
RAM_DQ_R<67>
RAM_DQ_R<69>
RAM_DQ_R<74>
RAM_DQ_R<73>
RAM_DQ_R<72>
RAM_DQ_R<75>
RAM_DQ_R<78>
RAM_DQ_R<79>
RAM_DQ_R<77>
RAM_DQ_R<76>
RAM_DQ_R<87>
RAM_DQ_R<86>
RAM_DQ_R<81>
RAM_DQ_R<80>
RAM_DQ_R<84>
RAM_DQ_R<85>
RAM_DQ_R<83>
RAM_DQ_R<82>
RAM_DQ_R<91>
RAM_DQ_R<93>
RAM_DQ_R<94>
RAM_DQ_R<90>
RAM_DQ_R<88>
RAM_DQ_R<89>
RAM_DQ_R<92>
RAM_DQ_R<95>
RAM_DQ_R<98>
RAM_DQ_R<96>
RAM_DQ_R<103>
RAM_DQ_R<97>
RAM_DQ_R<100>
RAM_DQ_R<99>
RAM_DQ_R<102>
RAM_DQ_R<101>
RAM_DQ_R<111>
RAM_DQ_R<106>
RAM_DQ_R<105>
RAM_DQ_R<108>
RAM_DQ_R<107>
RAM_DQ_R<110>
RAM_DQ_R<104>
RAM_DQ_R<109>
RAM_DQ_R<119>
RAM_DQ_R<112>
RAM_DQ_R<117>
RAM_DQ_R<118>
RAM_DQ_R<113>
RAM_DQ_R<115>
RAM_DQ_R<116>
RAM_DQ_R<114>
RAM_DQ_R<121>
RAM_DQ_R<124>
RAM_DQ_R<120>
RAM_DQ_R<123>
RAM_DQ_R<125>
RAM_DQ_R<122>
RAM_DQ_R<126>
RAM_DQ_R<127>

p
la

38 40 45

38 37

38 37

ALL R PACKS ARE 15 OHM 1/16W 5%

38 40 44

45 40 38

RAM_A_R<13..0>
RAM_BA_R<1..0>
RAM_RAS_L_R
RAM_CAS_L_R
RAM_WE_L_R
RAM_A<13..0>
RAM_BA<1..0>
RAM_RAS_L
RAM_CAS_L
RAM_WE_L

I295
I296
I297
I298
I299
I300
I304
I303
I302
I301

38 40 44
38 40 44
38 40 44

RAM_CLK PRIMARY SPACING SET TO 5MIL

RAM_CLK LINE-LINE SPACING SET TO 15MIL
TOTAL LENGTH TOLERENCE = 20PS = 2.82MM

38 40 44
38 40 44
38 40 44
38 40 44

RAM_CAD SPACING IS 10MIL

38 40 45
38 40 45
38 40 45
38 40 45
38 40 45
38 40 45
38 40 45
38 40 45

40
44 38

44 38

44 38

RAM_DQ<15>

44 38

PP1V25_RAM_VREF_DIMM
RAM_DQ<14>
RAM_DQ<10>
RAM_DQS<1>
RAM_DQ<9>

44 38

2
3
4
5
6
7
8

NC
6

44 38
44 38
44 38

38
38

44 38
44 38
44 38

44 38
44 38
44 38

44 40 38
44 38
44 40 38

TP_J4000_SJRESET_L

9
10
11
12

RAM_DQ<2>
RAM_DQ<0>
RAM_DQS<0>

13
14
15
16

RAM_CLK_A_P
RAM_CLK_A_N

17
18
19

RAM_DQ<6>
RAM_DQ<5>
RAM_CKE<0>

20
21
22
23

RAM_DQ<19>
RAM_DQ<18>
RAM_DQS<2>

24
25
26
27

RAM_A<9>
RAM_DQ<23>
RAM_A<7>

28
29
30

44 38
44 40 38
44 38

44 38
44 38
44 40 38

31
32

RAM_DQ<16>
RAM_A<5>
RAM_DQ<27>

33
34
35

RAM_DQ<29>
RAM_DQS<3>
RAM_A<4>

36
37
38

44 40 38

RAM_DQ<31>
RAM_DQ<28>
RAM_A<2>

44 40 38

RAM_A<1>

44 38
44 38

39
40
41
42
43

NC 44
NC 45
46

NC 47
44 40 38

44 38

44 38
44 38
44 38

44 38

44 38

45 40 38
44 38
45 40 38

44 38
44 38

44 38

38
38

44 38
44 38

50
51

RAM_BA<1>

52

RAM_DQ<34>

53
54
55

RAM_DQ<37>
RAM_DQS<4>
RAM_DQ<38>

56
57
59
60

RAM_BA<0>
RAM_DQ<32>
RAM_DQ<61>

61
62
63

RAM_WE_L
RAM_DQ<57>
RAM_CAS_L

64
65
67
68

RAM_DQS<7>
RAM_DQ<59>
RAM_DQ<56>

69
70
71
72

RAM_DQ<43>
RAM_DQ<41>

73
74
75
76

RAM_CLK_B_N
RAM_CLK_B_P

78
79

RAM_DQS<5>
RAM_DQ<47>
RAM_DQ<44>

80
81

44 38

44 38
44 38
44 38

RAM_DQ<50>
RAM_DQ<51>

83

RAM_DQS<6>
RAM_DQ<53>
RAM_DQ<52>

86
87

84
85

88

NC
40 18
40 18

I2C_DIMM_SDA
I2C_DIMM_SCL

OMIT

VSS
DQ1
DQS0

DQ5
VDDQ
DM0/DQS9
DQ6
DQ7

DQ2
VDD
DQ3
NC

VSS
NC

NC

NC

VSS
DQ8

A13
VDDQ

DQ9

DQ12

DQS1
VDDQ

DQ13
DM1/DQS10

CK1

VDD

CK1*
VSS

DQ14
DQ15

DQ10
DQ11

CKE1
VDDQ

CKE0

BA2

VDDQ
DQ16

DQ20
A12

DQ17

VSS

DQS2
VSS

DQ21
A11

A9

DM2/DQS11

DQ18
A7

VDD
DQ22

VDDQ
DQ19

A8
DQ23

A5

VSS

DQ24
VSS

A6
DQ28

DQ25

DQ29

DQS3
A4

VDDQ
DM3/DQS12
A3

VDD
DQ26
DQ27

DQ30
VSS

A2
VSS

DQ31
NC

A1

NC

NC
NC

VDDQ
CK0

VDD

CKO*

A10

NC 82
44 38

DQ4

VSS
NC

77
44 38

VSS

NC

NC
44 38

TOP SIDE

NC
A0

66
44 38

SYM_VER1

VREF SX64 DIMM

DQ0

48

58
45 40 38

BOT SIDE

89
90
91
92

VSS
NC

NC
VDDQ

BA1

NC
VSS
DQ36

DQ32
VDDQ
DQ33

DQ37

DQS4
DQ34

VDD
DM4/DQS13

VSS

DQ38

BA0
DQ35

DQ39
VSS

DQ40
VDDQ

DQ44
RAS*

WE*

DQ45

DQ41
CAS*

VDDQ
S0*

VSS

S1*

DQS5
DQ42

DM5/DQS14
VSS

DQ43

DQ46

VDD
NC,S2*

VDDQ
DQ52

VSS

DQ53

CK2*
CK2

NC,FETEN
VDD

VDDQ

DM6/DQS15

DQS6
DQ50

DQ54
DQ55

DQ51

VDDQ

VSS
VDDID

NC
DQ60

DQ56
DQ57

DQ61
VSS

VDD

DM7/DQS16

DQS7
DQ58

DQ62
DQ63

DQ59

VDDQ

VSS
WP

SA0
SA1

SDA

SA2

SCL

VVDDSPD
186

7 40

RAM_DQ<11>
RAM_DQ<13>

95
96

45 38

38 44

97

45 38

98
99

45 38

45 38

RAM_DQ<77>

45 38

105

RAM_DQ<3>
RAM_DQ<7>

38 40 44
45 38

106
107

45 38
38 44
45 38

108
109
110

RAM_DQ<1>
RAM_DQ<4>
RAM_CKE<1>

111
112
113 NC
114
115

38

45 38
38 44

38 44

38 40 44

116

RAM_DQ<22>
RAM_A<11>

45 38
7 40

C4036

45 38

10UF

45 38

20%
6.3V
2 CERM
1206

38 44

45 38

44 40 38

C4039
1UF

RAM_DQ<21>
RAM_A<8>
RAM_DQ<20>

122
123
124

38 44
38 40 44

C4037
1UF

C4023

45 38

1UF

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

44 40 38

45 38

38 44
44 40 38

125
126

RAM_A<6>
RAM_DQ<26>
RAM_DQ<25>

127

C4040
0.1UF

38 40 44

20%
10V
2 CERM
402

38 44
38 44

128
129

C4038
0.1UF

20%
2 10V
CERM
402

RAM_A<3>
RAM_DQ<24>

131
132
133

RAM_DQ<30>

C4044
0.1UF

38 40 44

20%
2 10V
CERM
402

38 44

45 38

0.1UF

136
137

10%
2 6.3V
CERM
402

C4045
1UF

138
139
140 NC
141

38
38

45 38
45 38

10%
2 6.3V
CERM
402

38 40 45

142 NC
143
144 NC

0.1UF

20%
2 10V
CERM
402
1

RAM_DQ<35>
RAM_DQ<33>

C4031

147

20%
10V
402

38 44

10%
2 6.3V
CERM
402
1

150

RAM_DQ<36>
RAM_DQ<39>

0.1UF

20%
10V
2 CERM
402

151
152
153

RAM_DQ<60>
RAM_RAS_L
RAM_DQ<63>

154
155
156
157

RAM_CS_L<0>
RAM_CS_L<1>

158

RAM_DQ<62>
RAM_DQ<58>

162
163 NC
164
165
166

RAM_DQ<40>
RAM_DQ<42>

10%
2 6.3V
CERM
402

38 44
38 44

38 44
38 44

38 44
38 44

169

RAM_DQ<46>
RAM_DQ<45>

C4028
1UF

38 44

167 NC FETEN
168
170
171

C4025
1UF

38 44
38 44

0.1UF

RAM_DQ<49>
RAM_DQ<48>

175

20%
10V
2 CERM
402

RAM_DQ<54>
RAM_DQ<55>

C4029
0.1UF

20%
10V
2 CERM
402

C4030
1UF

C4049

10%
6.3V
2 CERM
402

32
33

RAM_DQ<89>
RAM_DQS<11>
RAM_A<4>

RAM_A<1>

10%
6.3V
402

45 40 38

45 38

45 38

45 38
45 38

C4032

38
39
40
41
42
43

46
47
48

RAM_A<0>

49
50
52

RAM_BA<1>

53
54

RAM_DQ<98>

55
56

RAM_DQ<103>
RAM_DQS<12>
RAM_DQ<101>

57
58
59

0.1UF

20%
10V
2 CERM
402

45 40 38
45 38
45 38

C4022
0.1UF

45 40 38

20%
2 10V
CERM
402

45 38
45 40 38

45 38
45 38
45 38

RAM_BA<0>
RAM_DQ<102>
RAM_DQ<106>

60
61
62
63

RAM_WE_L
RAM_DQ<111>
RAM_CAS_L

64
65
66
67

RAM_DQS<13>
RAM_DQ<107>
RAM_DQ<110>

68
69
70
71

NC
45 38
45 38

72
73

RAM_DQ<114>
RAM_DQ<113>

74
38
38

45 38
45 38
45 38

75
76

RAM_CLK_E_N
RAM_CLK_E_P

77
78

RAM_DQS<14>
RAM_DQ<115>
RAM_DQ<118>

79
80
81

NC 82
45 38

38 44

45 38

83
84

RAM_DQ<124>
RAM_DQ<125>

85
45 38

38 44

45 38

38 44

45 38

86
87

RAM_DQS<15>
RAM_DQ<127>
RAM_DQ<126>

88
89

NC 90
40 18
40 18

10K 2
1

QTY

37

NC 51

38 44

PART#

35
36

NC

R4014

5%
1/16W
MF
ADDR=0(A0/A1) 402

91
92

I2C_DIMM_SDA
I2C_DIMM_SCL

516-0032

CONN,DDR DIMM 30 DEG

J4000,J4001

17_INCH_LCD

516-0067

CONN,DDR DIMM REVERSE 30 DEG

J4000,J4001

20_INCH_LCD

DQ7
VSS
NC

A9
DQ18
A7
VDDQ

DQ19
A5
DQ24

VSS

DQ25
DQS3
A4

NC
A13

150

RAM_DQ<74>
RAM_DQ<72>

38 45

97
98

m
o

RAM_DQ<76>
RAM_DQ<78>

99
100
101 NC
102 NC
103

RAM_A<13>

c
.
s
it c
VDDQ

DQ12
DQ13

DM1/DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
BA2
DQ20

A12

VSS
DQ21
A11

DM2/DQS11
VDD
DQ22
A8

DQ23

VSS
A6

DQ28

DQ29
VDDQ

DM3/DQS12

VDD
DQ26

A3
DQ30

DQ27
A2

VSS
DQ31
NC

VSS
A1
NC

NC
VDDQ

NC

CK0
CKO*
VSS

VDD
NC

NC

A0
NC
VSS

A10
NC

NC
BA1

VDDQ
NC

1%
1/16W
MF
2 402

38 45

96

104
105
106

RAM_DQ<65>
RAM_DQ<64>

107
108
109

RAM_DQ<69>
RAM_DQ<68>
RAM_CKE<5>

110
111
112

113 NC
114

RAM_DQ<81>
RAM_A<12>

115
116
117

RAM_DQ<86>
RAM_A<11>

118

38 45
38 45

121

RAM_DQ<85>
RAM_A<8>
RAM_DQ<84>

122
123
124
125

RAM_A<6>
RAM_DQ<91>
RAM_DQ<93>

126
127
128

PP1V25_RAM_VREF_DIMM
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
1

C4035 R4010
1UF

10%
6.3V
2 CERM
603

VSS

VDDQ

DQ36

DQ33
DQS4

DQ37
VDD

DQ34

DM4/DQS13

VSS
BA0

DQ38
DQ39

DQ35

VSS

DQ40
VDDQ

DQ44
RAS*

WE*
DQ41

DQ45
VDDQ

CAS*

S0*

VSS
DQS5

S1*
DM5/DQS14

DQ42

VSS

DQ43
VDD

DQ46
DQ47

NC,S2*

NC,S3*

DQ48
DQ49

VDDQ
DQ52

VSS
CK2*

DQ53
NC,FETEN

CK2

VDD

VDDQ
DQS6

DM6/DQS15
DQ54

DQ50

DQ55

DQ51
VSS

VDDQ
NC

VDDID

DQ60

DQ56
DQ57

DQ61
VSS

VDD
DQS7

DM7/DQS16
DQ62

DQ58

DQ63

DQ59
VSS

VDDQ
SA0

WP
SDA
SCL

SA1
SA2
VVDDSPD

150
1%
1/16W
MF
2 402

38 45
38 45

38 45

38 45

38 45

PP2V5_PWRON_RAM

7 40

38 45

38 40 44

C4008
10UF

20%
6.3V
2 CERM
1206

38 45
38 40 44

C4011
1UF

38 45

10%
6.3V
2 CERM
402

38 40 44
38 45

38 40 44

C4014
0.1UF

38 45

20%
10V
2 CERM
402

38 45

C4010

0.1UF

20%
10V
2 CERM
402
1

C4012

1UF

10%
6.3V
402

1UF

10%
6.3V
2 CERM
402

C4009

2 CERM

C4033
1UF

10%
6.3V
402

2 CERM

129
130
131

RAM_A<3>
RAM_DQ<92>

38 40 44

C4000
20%

2 10V
CERM

133
134 NC
135 NC
136

RAM_DQ<95>

137

RAM_CLK_D_P
RAM_CLK_D_N

402

38 45

C4020
0.1UF

138
139
140 NC
141
142 NC

20%
2 10V
CERM
402

38
38

RAM_A<10>

0.1UF

38 45

132

C4017
0.1UF

38 40 45

20%
2 10V
CERM
402

143

C4013

0.1UF
20%

10V
2 CERM
402

C4015

0.1UF
20%

10V
2 CERM
402

0.1UF

20%
10V
2 CERM
402
1

C4016

C4001
0.1UF
20%

2 10V
CERM

402

0.1UF

20%
10V
2 CERM
402

C4042

C4027
1UF
10%

2 6.3V
CERM

402

144 NC
1

DQ32

40

38 40 44

119
120

145
146

C4019

1UF
RAM_DQ<96>
RAM_DQ<97>

147
148

38 45
38 45

150
151

RAM_DQ<99>
RAM_DQ<100>

152
153
154

RAM_DQ<104>
RAM_RAS_L
RAM_DQ<105>

155
156
157

RAM_CS_L<8>
RAM_CS_L<9>

158
159

C4021

10%
6.3V
2 CERM
402

38 45

1UF

2 CERM

1UF

38 45

C4051

10%
6.3V
402

2 CERM

149

C4004
1UF

10%
6.3V
402

2 CERM

10%
6.3V
402

C4018

1UF

10%
6.3V
2 CERM
402

C4005
0.1UF
20%
10V
402

2 CERM

38 45
38 40 45

C4052
0.1UF

38 45

20%
10V
2 CERM
402

38 45

C4002
0.1UF

20%
10V
2 CERM
402

C4003

10%
6.3V
2 CERM
402

38 45

161
162

RAM_DQ<108>
RAM_DQ<109>

163 NC
164
165

RAM_DQ<112>
RAM_DQ<117>

166

38 45
38 45

38 45
38 45

167 NC FETEN
168
169
170

RAM_DQ<119>
RAM_DQ<116>

171
172
173 NC
174

RAM_DQ<120>
RAM_DQ<121>

175
176

38 45
38 45

38 45
38 45

177
178
179
180
181
182
183
184

RAM_DQ<122>
RAM_DQ<123>
SA0
SA1
SA2

38 45

38 45

SD_B_SA2

R4006
10K 2

5%
1/16W
MF
402
ADDR=1(A2/A3)

CRITICAL

V
V
R
R
V

CRITICAL

1UF

160

BOM OPTION

TABLE_5_ITEM

VDDQ
DM0/DQS9
DQ6

7 40

R4008

94
95

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

PP2V5_PWRON_RAM

93

186
DESCRIPTION

7 40

TABLE_5_ITEM

30
31

SD_A_SA0

SA1
SA2

VSS

29

RAM_DQ<87>
RAM_A<5>
RAM_DQ<90>

44 40 38

44 40 38

180

184

DQ17
DQS2

27
28

NC

176
177
178
179

DQ16

24
25

NC 44
NC 45

172

173 NC
174

CKE0
VDDQ

23

RAM_A<9>
RAM_DQ<82>
RAM_A<7>

44 40 38

45 38

C4026

2 CERM

1UF

DQ11

21
22

RAM_DQ<83>
RAM_DQ<80>
RAM_DQS<10>

RAM_DQ<88>
RAM_DQ<94>
RAM_A<2>

45 38

10%
2 6.3V
CERM
402

20%
10V
402

C4050

p
la

38 44
38 40 45

159
160
161

0.1UF

10%
2 6.3V
CERM
402

38 44

C4047

2 CERM

1UF

38 44

C4046

2 CERM

38 44

148
149

C4043
1UF

0.1UF

145
146

C4041

s
p
to

C4048
1UF

RAM_A<10>

VSS
DQ10

19
20

RAM_DQ<71>
RAM_DQ<70>
RAM_CKE<4>

34

20%
10V
2 CERM
402

38 44

134 NC
135 NC

RAM_CLK_C_P
RAM_CLK_C_N

CK1
CK1*

m
e
h
c

C4024

44 40 38

130

VDDQ

26

38 40 44

119
120
121

DQ9
DQS1

18

38 44

45 38

117
118

DQ8

16
17

RAM_CLK_F_P
RAM_CLK_F_N

38 44

PP2V5_PWRON_RAM
RAM_DQ<17>
RAM_A<12>

12

NC
VSS

15
38

DQ4
DQ5

NC

13
14

38 44

VSS

VDD
DQ3

10
11

RAM_DQ<66>
RAM_DQ<67>
RAM_DQS<8>

TOP SIDE

OMIT

DQS0
DQ2

8
9

TP_J4001_SJRESET_L

SYM_VER1

VREF SX64 DIMM

DQ0
VSS
DQ1

5
6

NC

RAM_A<13>

183

38 44

101 NC
102 NC

181
182

2
3

38 44

100

103
104

BOT SIDE

PP1V25_RAM_VREF_DIMM
RAM_DQ<75>

38 44

RAM_DQ<79>
RAM_DQS<9>
RAM_DQ<73>

RAM_DQ<8>
RAM_DQ<12>

PP2V5_PWRON_RAM

F-30DEG-TH
185

40

94

DDR-DIMM

PP2V5_PWRON_RAM

40 7

93

.
w
w
w

DQ47
NC,S3*

DQ48
DQ49

PIN 82:
NC: VDD & VDDQ ARE THE SAME
GND: VDD & VDDQ ARE DIFFERENT

516-0032

NC 49

RAM_A<0>

NC
45 40 38

PP2V5_PWRON_RAM

F-30DEG-TH
185

J4001

DDR-DIMM

PP2V5_PWRON_RAM

40 7

J4000

RS ADJACENT TO VS OR GS
VS ADJACENT TO GS FORBIDDEN

46 45 44

RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5 RAM_VTT

RP4400
62

RP4400
62

RP4401
62

RP4401
62

RP4401
62

RP4401
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38

46 45 44

0.1UF

46 45 44

PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

C4400

RP4400
62

1
40 38

RAM_VTT

RP4400
62

C4412
1UF

10%
6.3V
2 CERM
402

RAM_DQ<7>
RAM_DQ<0>
RAM_DQ<3>
RAM_DQ<2>
RAM_DQ<5>
RAM_DQ<4>
RAM_DQ<1>
RAM_DQ<6>

40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

RP4416
62

RP4416
62

RP4416
62

RP4417
62

RP4417
62

RP4417
62

RP4417
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

0.1UF

62

0.1UF

40 38
40 38
40 38
40 38
40 38

RAM_VTT 5RAM_VTT

RP4404
62

RP4404
62

RP4405
62

RP4405
62

RP4405
62

RP4405
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

10%
2 6.3V
CERM
402

40 38
40 38
40 38

40 38
40 38
40 38
40 38

46 45 44

40 38

46 45 44 7

10%
2 6.3V
CERM
402

40 38

40 38
40 38
40 38
40 38
40 38

PP1V25_RAM_VTT

46 45 44

40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5

RAM_VTT

RP4408
62

RP4408
62

RP4408
62

RP4409
62

RP4409
62

RP4409
62

RP4409
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

40 38

40 38
40 38
40 38
40 38

C4416
0.1UF

20%
2 10V
CERM
402

40 38

40 38
40 38
40 38

40 38
40 38

5RAM_VTT 8
RAM_VTT

RP4412
62

RP4412
62

RP4412
62

RP4412
62

RP4413
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

RAM_DQ<30>
RAM_DQ<28>
RAM_DQ<31>
RAM_DQ<24>
RAM_DQ<29>
RAM_DQ<25>
RAM_DQ<26>
RAM_DQ<27>

.
w
w
w

7RAM_VTT 6

RAM_VTT

5 RAM_VTT

RP4413
62

RP4413
62

RP4413
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

RAM_VTT

RAM_DQ<51>
RAM_DQ<48>
RAM_DQ<50>
RAM_DQ<49>
RAM_DQ<52>
RAM_DQ<55>
RAM_DQ<53>
RAM_DQ<54>

p
la
40 38

46 45 44

0.1UF

RP4421
62

RP4421
62

RP4421
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

10%
2 6.3V
CERM
402

C4405

RP4424
62

RP4424
62

RP4424
62

RP4425
62

RP4425
62

RP4425
62

RP4425
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

10%
2 6.3V
CERM
402

20%
2 10V
CERM
402

1UF

40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

150
5%
1/16W
SM1

40 38
40 38

40 38

40 38
40 38
40 38
40 38
40 38

SM1

46 45 44 7

10%
2 6.3V
CERM
402

150
5%
1/16W
SM1

RAM_VTT

C4404

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

RAM_DQ<58>
RAM_DQ<62>
RAM_DQ<56>
RAM_DQ<59>
RAM_DQ<57>
RAM_DQ<63>
RAM_DQ<60>
RAM_DQ<61>

0.1UF

0.1UF

20%
10V
2 CERM
402

40 38
40 38
40 38

C4409

RP4436
150

RP4436
150

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

10%
2 6.3V
CERM
402

1UF

C4421
0.1UF

20%
2 10V
CERM
402

C
6

RP4438
150

RP4438
150

RP4438
150

RP4439
150

RP4439
150

RP4439
150

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

1/16W
MF
2 402

5%
1/16W
MF
2 402

RP4439
150
5%
1/16W
SM1
4

RP4441
150

RP4441
150

5%
1/16W
SM1

5%
1/16W
SM1

RP4441 R4416
150
150
5%
5%
1/16W
SM1

RP4442
150

RP4442
150

RP4442
150

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

R4417
150

C4410
0.1UF

20%
10V
2 CERM
402

C4422
1UF

10%
6.3V
2 CERM
402

5%
1/16W
MF
2 402

2 402

R4420
150

R4421
150
5%
1/16W
MF

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R4409
62

R4410
150

R4411
150

7 44 45 46

C4411
0.1UF

20%
10V
2 CERM
402

RAM_CKE<0>
RAM_CKE<1>
RAM_CS_L<0>
RAM_CS_L<1>

5%
1/16W
MF
2 402

R4412
4.7K

0.1UF

20%
2 10V
CERM
402

PP2V5_RUN_RAM
R4408
62

C4418

40 38

PP1V25_RAM_VTT

RAM_VTT
1

10%
2 6.3V
CERM
402

RP4436
150

5%
1/16W
MF
2 402

C4420

SM1

RP4429
62

62

RP4436
150

150
5%
1/16W

RP4429
62

5%
1/16W
MF
2 402

RP4441_NC
RAM_A<8>
RAM_A<9>
RAM_A<11>
RAM_A<12>
RAM_A<13>

RP4442

RP4429
62

62

5%
1/16W
MF
2 402

RAM_VTT
1

1UF

RP4437
150

RP4441

1UF

RP4429
62

62

C4408

RP4437
150

C4419

40 38

RP4428
62

5%
1/16W
MF
2 402

RAM_VTT
1

PP2V5_RUN_RAM

RAM_VTT

40 38

RP4428
62

62

5%
1/16W
MF
2 402

40 38

RP4428
62

RAM_VTT

RP4437
150

150
5%
1/16W

40 38

RP4428
62

RAM_VTT

RAM_A<0>
RAM_A<1>
RAM_A<2>
RAM_A<3>
RAM_A<4>
RAM_A<6>
RAM_A<5>
RAM_A<7>

46 45 44

1UF

RP4437

40 38

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

PP2V5_RUN_RAM

RP4438

RAM_VTT

m
o

RAM_DQS<0>
RAM_DQS<1>
RAM_DQS<2>
RAM_DQS<3>
RAM_DQS<4>
RAM_DQS<5>
RAM_DQS<6>
RAM_DQS<7>

C4415
0.1UF

RAM_VTT

RP4424
62

RAM_VTT

1UF

m
e
h
c

s
p
to

C4417

10%
6.3V
2 CERM
402

RP4421
62

PP1V25_RAM_VTT

RAM_VTT

C4403

RP4420
62

40 38

40 38

RAM_DQ<22>
RAM_DQ<18>
RAM_DQ<19>
RAM_DQ<17>
RAM_DQ<20>
RAM_DQ<16>
RAM_DQ<21>
RAM_DQ<23>

8RAM_VTT 7RAM_VTT 6RAM_VTT

40 38

0.1UF

RP4420
62

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

C4402

RP4408
62

PP1V25_RAM_VTT

40 38

RAM_VTT

RP4420
62

RAM_DQ<43>
RAM_DQ<42>
RAM_DQ<40>
RAM_DQ<41>
RAM_DQ<44>
RAM_DQ<45>
RAM_DQ<47>
RAM_DQ<46>

PP1V25_RAM_VTT

RAM_VTT

C4406

RP4420
62
1

40 38

1UF

40 38

RAM_VTT

46 45 44

C4413

RAM_DQ<10>
RAM_DQ<13>
RAM_DQ<11>
RAM_DQ<14>
RAM_DQ<15>
RAM_DQ<12>
RAM_DQ<8>
RAM_DQ<9>

1UF

RAM_VTT

62

5%
1/16W
MF
2 402

c
.
s
it c
40 38

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

C4401

RP4404
62

1
40 38

RAM_VTT

RP4404
62

62

5%
1/16W
MF
2 402

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6

RAM_VTT

62

5%
1/16W
MF
2 402
40 38

46 45 44

RAM_VTT

R4400 1R4401 1R4402 1R4403 1R4404 1R4405 1R4406 1R4407

20%
10V
2 CERM
402

PP1V25_RAM_VTT

PP1V25_RAM_VTT

RAM_VTT
1

C4414

RAM_DQ<33>
RAM_DQ<37>
RAM_DQ<35>
RAM_DQ<34>
RAM_DQ<32>
RAM_DQ<39>
RAM_DQ<36>
RAM_DQ<38>

PP1V25_RAM_VTT

RAM_VTT

C4407

RP4416
62
1

40 38

PP1V25_RAM_VTT

46 45 44

R4413
4.7K

5%
1/16W
MF
402

R4414
150

5%
1/16W
MF
402

R4415
150

5%
1/16W
MF
402

46 45 44

PP1V25_RAM_VTT
46 45 44

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

40 38

40 38
40 38
40 38
40 38
40 38

C4500

RP4500
62

RP4500
62

RP4500
62

RP4501
62

RP4501
62

RP4501
62

RP4501
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

10%
6.3V
2 CERM
402

1
40 38

RAM_VTT

RP4500
62
2

1UF

46 45 44

PP1V25_RAM_VTT

RAM_VTT
1

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

C4510
0.1UF

20%
10V
2 CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38

RP4516
62

RP4516
62

RP4516
62

RP4517
62

RP4517
62

RP4517
62

RP4517
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

0.1UF

46 45 44

PP1V25_RAM_VTT
46 45 44

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RP4504
62

RP4504
62

RP4504
62

RP4505
62

RP4505
62

RP4505
62

RP4505
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

40 38
40 38
40 38

40 38
40 38
40 38
40 38

0.1UF

40 38
40 38

40 38
40 38

40 38
40 38
40 38
40 38
40 38
40 38
40 38

46 45 44

PP1V25_RAM_VTT
46 45 44

7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

40 38
40 38
40 38
40 38

40 38
40 38
40 38

C4502

RP4508
62

RP4508
62

RP4508
62

RP4509
62

RP4509
62

RP4509
62

RP4509
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

10%
2 6.3V
CERM
402

1UF

1UF

10%
2 6.3V
CERM
402

40 38
40 38
40 38
40 38
40 38

40 38
40 38

40 38
40 38
40 38

.
w
w
w
RAM_VTT

C4503

RP4512
62

RP4512
62

RP4512
62

RP4512
62

RP4513
62

RP4513
62

RP4513
62

RP4513
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

RAM_DQ<95>
RAM_DQ<94>
RAM_DQ<92>
RAM_DQ<88>
RAM_DQ<93>
RAM_DQ<89>
RAM_DQ<91>
RAM_DQ<90>

RP4521
62

RP4521
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

10%
6.3V
2 CERM
402

0.1UF

46 45 44

RP4524
62

RP4524
62

RP4524
62

RP4525
62

RP4525
62

RP4525
62

RP4525
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

10%
6.3V
2 CERM
402

1UF

RAM_VTT

RAM_VTT

RAM_VTT

RAM_VTT

5%
1/16W
MF
2 402

62

62

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

62
5%
1/16W
MF
2 402

62

62

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

62
5%
1/16W
MF
2 402

RAM_VTT
1

C4508
1UF

10%
6.3V
2 CERM
402

RAM_VTT
1

C4518
1UF

10%
6.3V
2 CERM
402

RAM_VTT

C4513
1UF

10%
6.3V
2 CERM
402

C
1

C4509

0.1UF

20%
10V
2 CERM
402

46 44 7

RAM_VTT

C4505

RP4524
62

1UF

m
e
h
c

s
p
to

C4519
1UF

10%
6.3V
2 CERM
402

46 45 44

PP2V5_RUN_RAM

PP1V25_RAM_VTT

RAM_VTT
1

C4516

0.1UF

RAM_VTT

20%
10V
2 CERM
402

RP4530

RP4530

RP4531

RP4531

RP4532

RP4532

RP4533

RP4533

150

150

150

150

150

150

150

150

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

2
40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

R4508
62

5%
1/16W
MF
2 402

RAM_VTT
1

R4509
62

5%
1/16W
MF
2 402

RAM_RAS_L
RAM_BA<0>
RAM_CAS_L
RAM_WE_L
RAM_CS_L<9>
RAM_CS_L<8>
RAM_BA<1>
RAM_A<10>
RAM_CKE<4>
RAM_CKE<5>

RP4530

RP4530

RP4531

RP4531

RP4532

RP4532

RP4533

RP4533

150
5%

150
5%

150
5%

150
5%

150
5%

150
5%

150
5%

150
5%

1/16W
SM1

1/16W
SM1

1/16W
SM1

1/16W
SM1

1/16W
SM1

1/16W
SM1

1/16W
SM1

1/16W
SM1

R4510 1R4511
4.7K

5%
1/16W
MF
2 402

4.7K

5%
1/16W
MF
2 402

PP1V25_RAM_VTT

RAM_VTT

RAM_DQ<117>
RAM_DQ<112>
RAM_DQ<113>
RAM_DQ<114>
RAM_DQ<118>
RAM_DQ<116>
RAM_DQ<115>
RAM_DQ<119>

p
la
40 38

40 38

40 38

RP4521
62

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

C4514

RAM_DQ<84>
RAM_DQ<87>
RAM_DQ<85>
RAM_DQ<82>
RAM_DQ<86>
RAM_DQ<80>
RAM_DQ<83>
RAM_DQ<81>

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

40 38

RP4521
62

PP1V25_RAM_VTT

40 38

RP4520
62

PP1V25_RAM_VTT

40 38

46 45 44

RP4520
62

RAM_DQ<111>
RAM_DQ<105>
RAM_DQ<106>
RAM_DQ<104>
RAM_DQ<109>
RAM_DQ<108>
RAM_DQ<110>
RAM_DQ<107>

RAM_VTT

RAM_VTT

RP4508
62
1
40 38

RP4520
62

1
40 38

RAM_VTT

C4506

RP4520
62

RAM_VTT

m
o

RAM_DQS<8>
RAM_DQS<9>
RAM_DQS<10>
RAM_DQS<11>
RAM_DQS<12>
RAM_DQS<13>
RAM_DQS<14>
RAM_DQS<15>

c
.
s
it c
40 38

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

62

5%
1/16W
MF
2 402

40 38

20%
2 10V
CERM
402

RAM_DQ<79>
RAM_DQ<72>
RAM_DQ<74>
RAM_DQ<75>
RAM_DQ<77>
RAM_DQ<78>
RAM_DQ<76>
RAM_DQ<73>

62

10%
6.3V
2 CERM
402

40 38

0.1UF

RAM_VTT

R4500 1R4501 1R4502 1R4503 1R4504 1R4505 1R4506 1R4507

1UF

PP1V25_RAM_VTT

RAM_VTT

C4501 1 C4511

RP4504
62
1
40 38

RAM_VTT

RAM_VTT
1

C4512

RAM_DQ<97>
RAM_DQ<103>
RAM_DQ<96>
RAM_DQ<98>
RAM_DQ<102>
RAM_DQ<100>
RAM_DQ<99>
RAM_DQ<101>

PP1V25_RAM_VTT

RAM_VTT
1

40 38

40 38

RAM_VTT

C4507

RP4516
62
1

RAM_DQ<64>
RAM_DQ<67>
RAM_DQ<65>
RAM_DQ<66>
RAM_DQ<70>
RAM_DQ<71>
RAM_DQ<68>
RAM_DQ<69>

40 38

C4515

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

1UF

10%
6.3V
2 CERM
402

1
40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

C4504

RP4528
62

RP4528
62

RP4528
62

RP4528
62

RP4529
62

RP4529
62

RP4529
62

RP4529
62

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

0.1UF

RAM_VTT
1

C4517
1UF

10%
2 6.3V
CERM
402

RAM_DQ<126>
RAM_DQ<123>
RAM_DQ<127>
RAM_DQ<122>
RAM_DQ<125>
RAM_DQ<124>
RAM_DQ<121>
RAM_DQ<120>

m
o

45 44 7

PP2V5_RUN_RAM
NOSTUFF

RAM_VTT
1

C4601

U4700_REFOUT

VDD
REFOUT

RAM_VTT
1

10K

0.1UF
10%
16V
X7R
603

R4603

5%
1/16W
MF
402

C4610

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=1.25V

VTT 1

RAM_VTT
1

C4606

SHTDWN 4

VR4700_SHTDWN

RAM_VTT

0.1UF

C4609

NOSTUFF
1

220UF

VSS

20%
2 2V
TANT
7343

VSS
U4700

10%
16V
X7R
603

NE57811

C4608
10UF

20%
6.3V
CERM
1206

SPAK-5

RAM_VTT

m
e
h
c

C
R4610
3

TURN_ON_VTT

5%
1/16W
MF
402

c
.
s
it c

PP1V25_RAM_VTT

10UF
20%
6.3V
CERM
805

44 45

3 NOSTUFF

Q4600

2N7002

50 27 11 10 9 8 6

SYS_SLEEP

SM

s
p
to
2

NOTE: U4700 PIN 4 IS LOW ACTIVE.

p
la

.
w
w
w

ELECTRICAL_CONSTRAINT_SET

R4800
4.99
1

1%
1/16W
MF
402

49 48

PP1V5_AGP

PP1V5_PWRON_AGP_NB_AVDD
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
1
1

C4811 C4816
2.2UF
20%

10V
2 CERM
805

0.01UF
20%

16V
2 CERM
402

49 48

49 48
49 48
49 48
49 48

VDD_AGP

AGP
REFCLK_AVDD

49 48

OMIT

49 48

U3

AG8 AGP_CBE0
AF8 AGP_CBE1

AGP_CBE<0>
AGP_CBE<1>

49 48
49 48

49 48

49 48
49 48

U3LITE
V1.0-300MM

AGP_AD0 AB11
AGP_AD1 AA11

PBGA

AGP_AD2 AG11

(SYM 4 OF 7)

AGP_DBI_LO

AA6 AGP_DBI_LO

AGP_AD_STBF<0>
AGP_AD_STBS<0>

AE8 AGP_AD_STBF0
AD8 AGP_AD_STBS0

AGP_AD5

AGP_AD8
AGP_AD9
AGP_AD10

AGP
INTERFACE

AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15

49 48

Y8 AGP_CBE2
AA5 AGP_CBE3

49 48

AGP_DBI_HI

AA4 AGP_DBI_HI

AGP_AD19

AGP_AD_STBF<1>
AGP_AD_STBS<1>

AA3 AGP_AD_STBF1
AA2 AGP_AD_STBS1

AGP_AD20
AGP_AD21

49 48
49 48

AGP_AD22

AGP_AD25

AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_SBA0

AD1 AGP_SB_STBF
AE1 AGP_SB_STBS

AGP_SB_STBF
AGP_SB_STBS

49 48

AGP_SBA1
AGP_SBA2
AGP_SBA3

AGP_SBA6
AGP_SBA7

49
49
49

49
49
49
49
49
49

AH7 AGP_PAR

AGP_PAR

49

AGP_ST<0>
AGP_ST<1>
AGP_ST<2>

AC4 AGP_ST0
AC1 AGP_ST1
AB1 AGP_ST2

AGP_RBF
AGP_WBF
AGP_TRDY
AGP_IRDY
AGP_GNT
AGP_FRAME
AGP_DEVSEL

AC6
AD6
AH5
AG6
AC3
AH6
AF6

p
la

AGP_FRAME
AGP_DEVSEL

AGP_PVTREF1
AGP_PVTREF2

AGP_VREFCG AC5

PP1V5_AGP

2 10V
CERM
402

AGP_SB_STBS
AGP_SB_STBS
AGP_AD_STB_0
AGP_AD_STB_0
AGP_AD_STB_1
AGP_AD_STB_1

AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE

AGP_DBI_LO
AGP_DBI_HI

AGP_AD_0
AGP_AD_STB_1

AGP_MB_AGP8X_DET AA8

AGP_SBA

48 49

DIFFERENTIAL_PAIR
I46
I48

AGP_SB_STB
AGP_SB_STB
AGP_AD_STB0
AGP_AD_STB0
AGP_AD_STB1
AGP_AD_STB1

I49
I50
I51
I52
I53
I54

AGP_DATA
AGP_DATA

I55

AGP_DATA
AGP_DATA

I57

AGP_DATA

I59

I56

I58

DBI_HI IS NOT A STROBE BUT SHARES THE SAME TOPOLOGY AS A STROBE

48 49
48 49
48 49
48 49
48 49
48 49

48 49

48 49
48 49
48 49
48 49
48 49
48 49

m
e
h
c
48 49
48 49

48 49

48 49

48 49
48 49

48 49

48 49

LEVEL SHIFTER FOR U3LITE & NVIDIA AGP BUS.

AGP BUSY AND STOP NOT USED IN THIS DESIGN

59 58 57 56 52 51 50 49 48 7

PP3V3_AGP

49 48 7

PP1V5_AGP

AGP_BUSYSTOP

R4811

R4807

10K

R4812

10K

5%
1/16W
MF
2 402

10K

5%
1/16W
MF
2 402

48 49

5%
1/16W
MF
2 402

NB_AGP_BUSY_L

AGP_BUSY_L_F
6

48 49

AGP_BUSYSTOP

AGP_BUSYSTOP

Q4801

2N7002DW

48 49

48 49

49

AGP_BUSY_L

48 49

2N7002DW

SOT-363

48

Q4801

48 49

SOT-363

48 49

48 49
48 49

27

48
48

U3LITE AGP I/O REFERENCE

59 58 57 56 52 51 50 49 48 7

(PLACE CLOSE TO GPU AGP BALL)

59 58 57 56 52 51 50 49 48 7

49 48 7

1%
1/16W
MF
402

49 48 7

PP1V5_AGP

R4802

48

R4803 1 C4818
1.02K

1%
1/16W
MF
2 402

0.01UF

1K

0.01UF

Q4803

AGP_BUSYSTOP

Q4802

2 STOP_AGP_L_R 1

2N3904

5%
1/16W
MF
402

20%
16V
2 CERM
402

NB_STOP_AGP_L

49

3 AGP_BUSYSTOP

R4813

48

STOP_AGP_L

STOP_AGP_L_F

AGP_BUSYSTOP
AGP_VREF_GC

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

1%
1/16W
MF
2 402

C4817

10K

10K

10K

3.32K

48

R4810

R4808

R4809

AGP_BUSYSTOP
1
1

PP3V3_AGP

PP3V3_AGP

PP1V5_AGP

NOSTUFF
1

AGP_SBA_L<7..0>

48 49

TP_AGP_MB_AGP8X_DET_L

AGP_REFCLK_AVSS

49 48

48 49

m
o

c
.
s
it c
AGP_AD_0
AGP_AD_1

48 49

TP_VREF_CG
AGP_VREF_GC

2N7002

SM

SM
2

20%
16V
2 CERM
402

7 48 49

C4800 1 C4801 1 C4802 1 C4803 1 C4804 1 C4805 1 C4806 1 C4807 1 C4808

0.1UF
20%

.
w
w
w

AC9 AGP_TYPEDET
AB8 AGP_GC_AGP8X_DET

AGP_TYPEDET_L
NB_AGP_GCDET_L

AGP_SB_STBF
AGP_SB_STBS
AGP_AD_STBF<0>
AGP_AD_STBS<0>
AGP_AD_STBF<1>
AGP_AD_STBS<1>

AGP_AD<15..0>
AGP_AD<31..16>

49 48

R4801
182

AE5

49

AGP_DATA
AGP_DATA

49 48

48 49

NB_AGP_BUSY_L
NB_STOP_AGP_L

AGP_VREFGC AA9

49

AGP_AD_0
AGP_AD_1

48 49

PVTREF RESISTOR

AGP_IRDY
AGP_GNT

AB9 AGP_REQ
AH4 AGP_STOP

AGP_REQ
AGP_STOP

48 49

AGP_CLK66M_NB

AC8
AD4

AGP_PVTREF2 AF5

49

49 48

AGP_SBA_L<0>
AGP_SBA_L<1>
AGP_SBA_L<2>
AGP_SBA_L<3>
AGP_SBA_L<4>
AGP_SBA_L<5>
AGP_SBA_L<6>
AGP_SBA_L<7>

AGP_BUSY*
AGP_STP_AGP*

AGP_TRDY

48 49

AG2
AF3
AH1
AG3
AD2
AF2
AG1
AF1

AGP_PVTREF1 AG5

49

AGP_CBE<1..0>
AGP_CBE<3..2>

48 49

Y5
AA1
Y2
Y1
Y7
V5
V6
V4
V3
V8
V7
W1
AA7

AGP_REFCLK AH2

AGP_RBF
AGP_WBF

49 48

s
p
to
AGP_SBA4
AGP_SBA5

49

48 49

AGP_AD<16>
AGP_AD<17>
AGP_AD<18>
AGP_AD<19>
AGP_AD<20>
AGP_AD<21>
AGP_AD<22>
AGP_AD<23>
AGP_AD<24>
AGP_AD<25>
AGP_AD<26>
AGP_AD<27>
AGP_AD<28>
AGP_AD<29>
AGP_AD<30>
AGP_AD<31>

AGP_AD17 Y3
AGP_AD18 Y6

AGP_AD23
AGP_AD24

49 48

AD11
AE11
AF11
AH8
AH9
AH10
AH11
AG9
AF9
AE9
AD9

AGP_AD16 Y4

AGP_CBE<2>
AGP_CBE<3>

49 48

AGP_AD<0>
AGP_AD<1>
AGP_AD<2>
AGP_AD<3>
AGP_AD<4>
AGP_AD<5>
AGP_AD<6>
AGP_AD<7>
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
AGP_AD<13>
AGP_AD<14>
AGP_AD<15>

AGP_AD3 AH12
AGP_AD4 AC11
AGP_AD6
AGP_AD7

DBIHI AND DBILO

GROUPS WITH STROBE1
FOR CONSTRAINTS

NET_SPACING_TYPE

7 48 49

AG4
AG10
AE2
AE7
AC10
AB4
Y11
W2
W6
W10
V9

PP1V5_PWRON_NB_AVDD

AE6

60 37 28 7

NET_PHYSICAL_TYPE

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

10V
2 CERM
402

C4810 1 C4812 1 C4813 1 C4814 1 C4815

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

10V
2 CERM
402

NVIDIA RECOMMENDS A WIDER RANGE OF CAP VALUES, EMC LIKES ONE VALUE
TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
49 48 7

PP1V5_AGP

OUTPUT DRIVER BYPASS

TABLE_5_ITEM

338S0155

IC,NV18B,GRAPHIC CTRL

U4900

NV18B

338S0113

IC,NV34,GRAPHIC CTRL

U4900

NV34

TABLE_5_ITEM

AGP_AD<0>
AGP_AD<1>
AGP_AD<2>
AGP_AD<3>
AGP_AD<4>
AGP_AD<5>
AGP_AD<6>
AGP_AD<7>
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
AGP_AD<13>
AGP_AD<14>
AGP_AD<15>
AGP_AD<16>
AGP_AD<17>
AGP_AD<18>
AGP_AD<19>
AGP_AD<20>
AGP_AD<21>
AGP_AD<22>
AGP_AD<23>
AGP_AD<24>
AGP_AD<25>
AGP_AD<26>
AGP_AD<27>
AGP_AD<28>
AGP_AD<29>
AGP_AD<30>
AGP_AD<31>

48
48
48

48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48

48
48
48

48
48
48
48

R4912
PCI_RESET_L

27

5%
1/16W
MF
402

48
48

48
48

PP3V3_AGP

7 48 49 50 51 52 56 57 58 59

48
48

R4908
4.99K
1

48
48

AGP_INT_L

49 25
6
48
48

48
48
48

NB_AGP_GCDET_L

48

AGP_TYPEDET_L

48
48

48

R4913 1R4909
0

5%
1/16W
MF
2 402

48

10K

5%
1/16W
MF
2 402

48
48

48
48

48
48
48
48
48

DOES HOOP UP AGP_BUSY_L &

STOP_AGP_L TO 3.3V OR 1.5V?

48

48

48

49

GPU_AGP_VREF

AG12 PCICLK
AF15 PCIRST*

: CLK
: RST*

AGP_GNT
AGP_REQ

AE15 PCIGNT*
AF13 PCIREQ*

: GNT
: REQ

AGP_FRAME
AGP_IRDY
AGP_TRDY
AGP_DEVSEL
AGP_STOP
AGP_PAR

AK16
AG16
AJ17
AJ16
AH17
AK18

:
:
:
:
:
:

AGP_INT_L
TP_GPU_INTB_L
AGP_RBF
AGP_WBF
AGP_DBI_HI
AGP_DBI_LO
AGP_ST<0>
AGP_ST<1>
AGP_ST<2>
AGP_AD_STBF<0>
AGP_AD_STBS<0>
AGP_AD_STBF<1>
AGP_AD_STBS<1>

AG15
AE10
AG14
AG17
AJ18
AJ19
AG13
AE16
AE13
AK24
AJ25
AG21
AF21

INTA
INTB
RBF
WBF
DBI_HI
DBI_LO
ST0
ST1
ST2

.
w
w
w

AGP_SB_STBF
AGP_SB_STBS

AGP_SBA_L<0>
AGP_SBA_L<1>
AGP_SBA_L<2>
AGP_SBA_L<3>
AGP_SBA_L<4>
AGP_SBA_L<5>
AGP_SBA_L<6>
AGP_SBA_L<7>

AK13 AGPSBSTBF
AJ13 AGPSBSTBS*
AJ11 AGPSBA0
AH11 AGPSBA1
AJ12 AGPSBA2
AH12 AGPSBA3
AJ14 AGPSBA4
AH14 AGPSBA5
AJ15 AGPSBA6
AH15 AGPSBA7
AF16 <RESRVD>
AF12 AGPBUSY*
AG11 AGPSTOP*
AK29 AGPVREF

:
:
:
:
:
:
:
:

: MBDET*
: BUSY*
: STOP*
: AGPVREF

NO_TEST

5%
1/16W
MF
2 402

NO_TEST

TP_GPU<0>
TP_GPU<1>
TP_GPU<2>
TP_GPU<3>
TP_GPU<4>

(LOW = AGP V3.X)

(HIGH = AGP V2.X)

NO_TEST

AGP VERSION SELECT

R4903

NO_TEST

A1
AK30
G6
R7
T7

NC

C4916
1 0.1UF

10%
16V
CERM
402

C4926
1 0.01UF

10%
16V
CERM
402

C4961

20%
10V
CERM
402

C4960
10UF

20%
6.3V
CERM
805

20%
6.3V
CERM
805

C4902
10UF

20%
6.3V
CERM
805

20%
10V
CERM
402

C4907
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4908
1 0.1UF
2

C4909
1 0.1UF

C4900
10UF

20%
6.3V
CERM
805

C4929
1 0.1UF
2

C4919
1 0.1UF

20%
10V
CERM
402

C4903
10UF

20%
6.3V
CERM
805

C4920
1 0.1UF
2

C4930
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

C4901
10UF

20%
6.3V
CERM
805

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

C4922
1 0.1UF
2

C4923
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4924
1 0.1UF
2

20%
10V
CERM
402

C4932
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

PP3V3_AGP
59 58 57 56 52 51 50 49 48 7

C4933
1 0.1UF
2

20%
10V
CERM
402

C4921
1 0.1UF

C4931
1 0.1UF
2

C4910
1 0.1UF

m
o

20%
10V
CERM
402

c
.
s
it c
C4918
1 0.1UF
2

a
2

20%
10V
CERM
402

C4928
1 0.1UF

20%
10V
CERM
402

C4913
1 0.1UF
2

C4917
1 0.1UF

20%
10V
CERM
402

C4927
1 0.1UF

10%
16V
CERM
402

10UF

C4934
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4935
1 0.1UF
2

1000-OHM-EMI
1

2
SM

PP5V_AGP

PP3V3_AGP

NV34
1

7 48 49 50 51 52 56 57 58 59

NV34

4.7UF
2

NV34

1 C4956
0.1UF
20%
2 10V
CERM

C4959
20%
6.3V
CERM
805

1 C4955
0.001UF
10%
2 50V
CERM

402

402

I/O BYPASS

C4936
1 0.01UF
2

10%
16V
CERM
402

C4942
1 0.01UF
2

10%
16V
CERM
402

C4938
1 0.1UF
2

20%
10V
CERM
402

C4939
1 0.1UF
2

C4941
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4937
1 0.1UF
2

20%
10V
CERM
402

B
7 50 59

C4953
1 0.1UF

C4954
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4943
10UF

20%
6.3V
CERM
805

C4944
1 0.01UF
2

10%
16V
CERM
402

C4945
1 0.01UF
2

10%
16V
CERM
402

C4946
1 0.1UF
2

20%
10V
CERM
402

C4947
1 0.1UF
2

C4949
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4950
1 0.1UF
2

20%
10V
CERM
402

C4951
1 0.1UF
2

20%
10V
CERM
402

C4952
1 0.1UF
2

20%
10V
CERM
402

GPU_50PULLUP
GPU_50PULLDWN

AGPCALPU AA14
10K OHM
TO GND

TESTMODE AE5

PP1V5_AGP

GPU_TMODE

1 R4901
10K
5%
1/16W
2 MF
402

7 48 49

1 R4902
49.9

1 R4900
49.9

1%
1/16W

1%
1/16W
2 MF
402

2 MF

402

49 48 7

PP1V5_AGP

1
PP3V3_AGP 7

48 49 50 51 52 56 57 58

59

NV34

NVAGP_TRST_L
TP_NVAGP_TDO
TP_NVAGP_TDI
TP_NVAGP_TMS

R4905
1
2
1K

R4910
10K

5%
1/16W
2 MF
402

R4911
10K

5%
1/16W
2 MF
402

3.32K

GPU AGP I/O REFERENCE

(PLACE CLOSE TO U3LITE AGP BALLS)

GPU_AGP_VREF

VOLTAGE=0.35V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

49

R4907 1 C4957
1.02K

1%
1/16W
MF
2 402

R4904
1
2
1K

NVAGP_TCLK

R4906

1%
1/16W
MF
2 402

NV34

0.01UF

20%
16V
2 CERM
402

BOUNDRY SCAN AVAILABLE ONLY ON NV3X SERIES

NV34

L4901

20%
10V
CERM
402

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

s
p
to
50 OHM
TO GND

C4906
1 0.1UF

20%
10V
CERM
402

m
e
h
c
1

C4915
1 0.01UF

10%
16V
CERM
402

C4925
1 0.01UF

50 OHM
TO VDDQ

C4905
1 0.1UF

20%
10V
CERM
402

CORE BYPASS

AGPCALPD AA13

SBA0*
SBA1*
SBA2*
SBA3*
SBA4*
SBA5*
SBA6*
SBA7*

C4914
1 0.01UF

VD50CLAMP0 N4
VD50CLAMP1 AE9
AGP_PLLVDD AE12

: SBSTBF
: SBSTBS

C4904
1 0.1UF

10%
16V
CERM
402

PPVCORE_GPU

H6
AC6
U7
G14
U6
AD15
VDD33 H7
AD16
AD19
AD22
AC7
AD12
P24

p
la

AGPADSTBF0 : ADSTBF0
AGPADSTBS0* : ADSTBS0
AGPADSTBF1 : ADSTBF1
AGPADSTBS1* : ADSTBS1

58 50

AGP_PLLVDD

FRAME
IRDY
TRDY
DEVSEL
STOP
PAR

PCIINTA*
:
NC_PCIINTB*:
AGPRBF*
:
AGPWBF*
:
AGPPIPE*
:
<RESRVD>
:
AGPST0
:
AGPST1
:
AGPST2
:

C4911
1 0.01UF

10%
16V
CERM
402

AA17
AA18
L20
Y20
L13
Y13
N20
P20
U20
V20
VDD L11
N11
P11
U11
V11
Y11
L14
Y14
L17
Y17
L18
Y18

AGP 8X
C0*/BE0
C1*/BE1
C2*/BE2
C3*/BE3

AGP_CLK66M_GPU
NV_PCIRST_L

NO_TEST

:
:
:
:
:

AJ24
AH19
AF25
AG22

GPU_MBDET_L
AGP_BUSY_L
STOP_AGP_L

48

OMIT

AGP_CBE<0>
AGP_CBE<1>
AGP_CBE<2>
AGP_CBE<3>

PCIFRAME*
PCIIRDY*
PCITRDY*
PCIDEVSEL*
PCISTOP*
PCIPAR

AE14
AE11
AE17
AE20
AGPVDDQ AE23
AD11
AD14
AD23
AD20
AD17

25 49

1%
1/16W
MF
402

48

PCIAD0
PCIAD1
PCIAD2
PCIAD3
PCIAD4
PCIAD5
PCIAD6
PCIAD7
PCIAD8
PCIAD9
PCIAD10
PCIAD11
PCIAD12
PCIAD13
PCIAD14
PCIAD15
PCIAD16
PCIAD17
PCIAD18
PCIAD19
PCIAD20
PCIAD21
PCIAD22
PCIAD23
PCIAD24
PCIAD25
PCIAD26
PCIAD27
PCIAD28
PCIAD29
PCIAD30
PCIAD31
AGP 2X,4X
PCIC0/BE0*
PCIC1/BE1*
PCIC2/BE2*
PCIC3/BE3*

C4912
1 0.01UF

C2 TCLK
C1 TMS
D1 TDI
E2 TDO
D2 TRST*

77 76 75 74 51 6

AJ28
AK28
AH27
AK27
AJ27
AH26
AJ26
AH25
AH23
AJ23
AH22
AJ22
AJ21
AK21
AH20
AJ20
AG26
AE24
AG25
AG24
AF24
AG23
AE22
AF22
AE21
AG20
AG19
AF19
AE19
AF18
AG18
AE18

U4900
NV18B
BGA
(1 OF 5)

1
TABLE_5_HEAD

PPVOCRE_GPU

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

1.60VDC

114S2803

RES,2.8K OHM,1/16W,1%,0402

R5003

NV18B

1.40VDC

114S1213

RES,1.21K OHM,1/16W,1%,0402

R5003

NV34

TABLE_5_ITEM

m
o

GPU VCORE VREG

59 7

59 49 7

PP12V_AGP

PP3V3_AGP

PP5V_AGP

R5000

C5004
1UF

20%
25V
CERM 2
805

20%
25V
2 CERM
805

5%
1/10W
FF
2 805

C5016
1UF

4.7

R5002

HD

U5000_COMP

1%
1/16W
MF
2 402

C5014

0.1UF

68PF

C5023

C5006

CASE369

220PF

5%
50V
2 CERM
603

NTD70N03R

NOSTUFF

5%
2 25V
CERM
402

20%
2 50V
CERM
1206

10%
50V
2 CERM
603

5%
2 50V
CERM
603

C5012
0.1UF

0.022UF

3900PF

10%
50V
2 CERM
603

R5004_P2

C5005

3300PF

5%
1/4W
FF
2 1206

PPVCORE_GPU

VOLTAGE=1.65V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

OMIT

C5007 R5003
2.8K

m
e
h
c

Q5002

R5001_2

20%
16V
2 CERM
603

C5013

0.51

NOTE:
SET OUTPUT=1.60V FOR NV18B
SET OUTPUT=1.40V FOR NV34
IRU3037CS VREF=1.25VDC
VOUT=VREF*(R5004+R5005)/R5005=1.60(OR 1.40) VDC
PEAK CURRENT OF TOTAL RAILS
7.2A WITH NV34

NOSTUFF

R5004

U5000_FEEDBACK

GND
1

2
TH

U5000_GATE_L

COMP

27.4K

1.6UH

FB

L5001

U5000_GATE_H

R5001

390UF

20%
2 6.3V
ELEC
8X11.5-TH

CASE369

Q5002_DRAIN
3

C5003

NTD70N03R

SS
LD

20%
2 6.3V
ELEC
8X11.5-TH

Q5001
Q5001_GATE

5%
1/10W
FF
805

SOI

VC

IRU3037CS
8

C5002
390UF

20%
2 6.3V
CERM
1206

U5000

U5000_SS

10UF

U5000_VC

VCC

C5001

c
.
s
it c

7 48 49 51 52 56
57 58 59

49 50 58

1%
1/16W
MF
2 402

C5008
1800UF

20%
2 6.3V
ELEC
TH-KZJ

R5005
10K

C5009
1800UF

20%
2 6.3V
ELEC
TH-KZJ

1%
1/16W
MF
2 402

U5000_FEEDBACK

s
p
to

AGP 1.5V VREG

C5000
10UF

GND
8

20%
6.3V
CERM
1206

NC
THM
PAD

1
4
5

VR5001_ADJ
NC
NC
NC

SC4215
SOIC ADJ 7

EN

R5015

R5017

C5020
10UF

20%
6.3V
CERM
1206

C5022

330UF
20%
2 6.3V
ELEC
SM-2

5%
1/10W
FF
805

SI3446DV

PP5V_PWRON

RDSON=0.06 OHM
@ VGS=2.5 V

TSOP

200

1%
1/10W
FF
2 805

Q5006

R5007
0

SM

Q5006_D

NOSTUFF
1

R5021
2

100K

Q5006G

5%
1/16W
MF
402

NOTE:CONNECT VR5001 PIN 9 TO GND PLANE.

5%
1/8W
FF
1206

174

1%
1/10W
FF
2 805

10BQ040

R5010

NOTE:
SET OUTPUT=1.5V
SC4215 VREF=0.8VDC
VOUT=VREF*(R5015+R5017)/R5017=1.5 VDC
PEAK CURRENT OF TOTAL RAILS
0.95A

VO 6

NOSTUFF

PP1V5_RUN

VR5001

PPVCORE_GPU

D5001

VIN

58 50 49

.
w
w
w
3

PP1V5_PWRON

PP2V5_PWRON

p
la

3
D

Q5007
2N7002
SM

SYS_SLEEP

6 8 9 10 11 27 46

TMDS_XMIT_SI

PP3V3_AGP

TMDS_XMIT_SI

L5102

PP3V3_SI_VCC

FERR-EMI-100-OHM
1

PP3V3_SI_AVCC

VOLTAGE=3.3V

VOLTAGE=3.3V

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

10UF
20%
6.3V
CERM
805

C5106

TMDS_XMIT_SI

C5104

100PF

100PF

5%
50V
CERM
402

5%
50V
CERM
402

TMDS_XMIT_SI

C5103

100PF

5%
50V
CERM
402

5%
50V
CERM
402

TMDS_XMIT_SI

TMDS_XMIT_SI

L5100
VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL

TMDS_XMIT_SI

3V_SI_PLLVCC

MIN_NECK_WIDTH=10MIL

C5100

10UF

10UF
20%
6.3V
CERM
805

20%
6.3V
CERM
805

TMDS_XMIT_SI

C5108

C5105

100PF
2

5%
50V
CERM
402

5%
50V
CERM
402

C5101
10UF

20%
6.3V
CERM
805

TMDS_XMIT_SI

TMDS_XMIT_SI

c
.
s
it c

330OHM HI SWING
RESISTOR MAY NEED TO BE
HIGHER

100PF

TMDS_XMIT_SI

NOTE:

SM

C5109

C5102

100PF
2

FERR-EMI-100-OHM

7 48 49 50 51 52 56 57 58
59

m
o

SM

C5107

PP3V3_AGP

L5101

FERR-EMI-100-OHM

51

SM

TMDS_XMIT_SI

TMDS_XMIT_SI

TMDS_XMIT_SI

PLL NOISE SHOULD BE LESS THAN 100MV PEAK-TO-PEAK

R5127
330

57 51
57 51
57 56
57 51

57

57 56
57
57

R5120
10K

R5119

5%
1/16W
MF
2 402

10K

p
la

.
w
w
w
1

R5118
10K

5%
1/16W
MF
2 402

R5124
10K

10K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R5123
1
10K

5%
1/16W
MF
2 402

5%
1/16W
MF
402

57 51
57 51
57 51

57 51
57 51
57 51
57 51

57 51
57 51

DVOD11
DVOD10
DVOD9
DVOD7
DVOD6
DVOD5
DVOD4
DVOD1
DVOD0

R5121

DVOD0
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11
DVODE
DVOHSYNC
DVOVSYNC
DVOCLKOUT

18
17
16
15
14
13
10
9
8
7

s
p
to
57 51

57 51

44

NOSTUFF

R5104 1

6
5

19
20
21
12
11

PD*
EDGE/HTPLG

NC

SI_TMDS_CKP
SI_TMDS_CKM

TXC+ 33
TXC- 32
U5100
D0
SIL1162
D1
TX0+ 36
TSSOP
D2
TX0- 35
TMDS_XMIT_SI
D3
TX1+ 39
D4
TX1- 38
D5
CRITICAL
TX2+ 42
D6
D7
TX2- 41
D8
D9
D10
D11
DE
HSYNC
EXT_SWING 30
VSYNC
IDCK+
VREF 2
IDCK-

57 51

PP3V3_AGP

m
e
h
c
25

47

MSEN 48

22
22

NOSTUFF

22

SI_TMDS_D1P
SI_TMDS_D1M

22

SI_TMDS_D2P
SI_TMDS_D2M

22

NOSTUFF

R5112

R5105

TMDS_CKP

58 59

TMDS_CKM

58 59

NOSTUFF R5110

TMDS_D0P
TMDS_D0M

NOSTUFF R5108

TMDS_D1P
TMDS_D1M

R5107
22

NOSTUFF

R5109
22

NOSTUFF

NOSTUFF

R5111
22

SI_TMDS_D0P
SI_TMDS_D0M

NOSTUFF R5106
2

TMDS_D2P
TMDS_D2M

58 59
58 59

58 59
58 59

58 59
58 59

5%
1/16W
MF
402

PLACE TMDS RESISTORS ON OPPOSITE SIDE TO TMDS

RESISTORS ON PAGE 25

SI_EXT_SWING_SET

PP3V3_SI_VCC

51

TMDS_XMIT_SI

R5116

49

57 51

SCL/DK1
IPD
SDA/DK0
IPD
CTL3/A2
ISEL/RST* IPD

57 56

24

23

57 51

57 56

59 58 57 56 52 51 50 49 48 7

26

SI_PCI_RESET_L
SI_EDGE

57 51

27

37

51

51

5%
1/16W
MF
402

SI_SCL
SI_SDA

43

2 SI_PCI_RESET_L

5%
1/16W
MF
402
2

PGND
PGND
AGND
AGND
AGND
GND
GND
GND
THRML
PAD

5%
1/16W
MF
402 2

4.7K

29

PCI_RESET_L

5%
1/16W
MF
402 2

SI_I2C_OFF

R5130
77 76 75 74 49 6

5%
1/16W
MF
402 2

R5129

NC

TMDS_XMIT_SI

4.7K

31

58

NOSTUFF
1

R5113 1

4.7K

45

58

NOSTUFF

R5128 1

4.7K

28

R5100 1

PVCC1 46
PVCC2 40
AVCC 34
AVCC
22
VCC
3
VCC

NOSTUFF

TMDS_XMIT_SI

5%
1/16W
MF
402

0
5%
1/16W
MF

2 402

SI_VREF

TMDS_XMIT_SI

NOSTUFF

R5103 1

R5102 1

TMDS_XMIT_SI

R5101 1

4.7K

4.7K

4.7K

4.7K

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

NOSTUFF
1

R5117
1K

1%
1/16W
MF
402

SILICON IMAGE 1162 TMDS

R5126
10K

5%
1/16W
MF
2 402

R5122
10K

5%
1/16W
MF
2 402

R5125
10K

5%
1/16W
MF
2 402

UNDEFINED RESET CONFIGURATION STRAPS

DRAWING

H
55 54 52 7 PP2V5_GPU

EVENLY DISTRIBUTE 0.01UF & 0.1 UF CAPS

NVIDIA RECOMMENDS WIDER RANGE OF CAP VALUES, EMC LIKE ONE VALUE

C5208
0.01UF

10%
16V
CERM
402

C5215
2

C5216
2

0.01UF

C5217
2

0.1UF

C5218
2

0.1UF

C5221
2

0.1UF

C5219
2

0.01UF

C5220
2

0.1UF

C5213
2

0.01UF

C5212
2

0.1UF

C5211
2

0.1UF

C5210
2

0.1UF

0.1UF

10%

20%

20%

20%

10%

20%

10%

20%

20%

20%

20%

1 16V
CERM

1 10V
CERM

1 10V
CERM

1 10V
CERM

1 16V
CERM

1 10V
CERM

1 16V
CERM

1 10V
CERM

1 10V
CERM

1 10V
CERM

1 10V
CERM

402

402

402

402

402

402

402

402

402

402

402

PP2V5_GPU

F17

U4900

C5222
2

1 C5201
10UF
2

20%
6.3V
CERM
805

0.1UF

C5224
2

C5225
2

0.1UF

53

FBD<1>

N27

53

FBD<2>

53

FBD<3>

N26
M25

53

FBD<4>

53

FBD<5>

K26
K27

FBD<6>
FBD<7>

J27
H27
N29

53

FBD<8>
FBD<9>

53

FBD<10>

M28

53

FBD<11>

53

FBD<12>

L29
J29

53

FBD<13>

J28

53

FBD<14>

H29

53

FBD<15>

53

FBD<16>

G30
K25

53

FBD<17>

J26

53

FBD<18>

J25

53

FBD<19>

G26

53
53
53

53

FBD<20>

F28

53

FBD<21>

53

FBD<22>

F26
E27

53
53
53
53
53
53
53
53
53
53
53
53
53
53

FBD<25>
FBD<26>

G29
F29

H28

E29

FBD<27>
FBD<28>

C30
C29

FBD<29>
FBD<30>

B30
A30

FBD<31>
FBD<32>

AJ29
AJ30

FBD<33>
FBD<34>

AH29
AH30

FBD<35>
FBD<36>

AF29
AE29

FBD<37>
FBD<38>
FBD<39>

53

FBD<40>

53

FBD<41>

AG28
AF27

53

FBD<42>
FBD<43>

AE26
AE28

53

FBD<44>

AD25

53

FBD<45>

53

FBD<46>

AB25
AB26

53

FBD<47>

53

FBD<48>

AA25
AD30

53

FBD<49>

AC29

53

FBD<50>

AB28

53

FBD<51>

53

FBD<52>

AB29
Y29

53

FBD<53>

53

FBD<54>

53

FBD<55>

53

FBD<56>

V29
AC27

FBD<57>
FBD<58>

AB27
AA27

FBD<59>
FBD<60>

AA26

53

FBD<61>
FBD<62>

V26

53

FBD<63>

V27
V25

54

FBDQM<0>

L27

FBDQM<1>
FBDQM<2>

K29
G25

FBDQM<3>
FBDQM<4>

E28

53
53
53
53
53

54
54
54
54

54

FBDQM<5>
FBDQM<6>

54

FBDQM<7>

54

54
54
54
54
54
54
54
54

D27

53

53

FBD<23>
FBD<24>

53

53

M29

54
54
54

U28
U29
T28

20%

1 10V
CERM

402

402

402

402

402

402

402

402

U4900

P29
R28

FBAWE_L
FBACS0_L
TESTPOINT

56

ROMA14
ROMA15
TP_ROMCS_L

U27
P27

TESTPOINT
TESTPOINT

FBVREF

R2

ROMA14
ROMA15
ROMCS*

R1
AF2

F8

53

FBD<65>

L25

53

FBD<66>

Y25

53

F11

53

FBD<67>
FBD<68>

F14

53

FBD<69>

D10

F20

53

FBD<70>

F23

53

FBD<71>

D9
D8

Y24

53

FBD<72>

B13

L24

53

FBD<73>

B12

G20

53

FBD<74>

C12

53

FBD<75>

B11
B9

53

FBD<76>
FBD<77>

53

FBD<78>

53

FBD<79>

A7

53

FBD<80>

F10

53

TP_VTT<0>

FBCAL_PU_GND

C9
B8

TP_VTT<1>

NO_TEST

53

FBD<81>

TP_VTT<2>
TP_VTT<3>

NO_TEST

53

FBD<82>

F9

G9

NO_TEST

53

FBD<83>

F7

TP_VTT<4>
TP_VTT<5>

NO_TEST

53

FBD<84>

C6

NO_TEST

53

FBD<85>

E6

53

FBD<86>

D5

FBD<87>
FBD<88>

C4

FBD<89>
FBD<90>

B7
B6

FBD<91>
FBD<92>

B5

G12
G15
G16
G19
G22
J24
M24
R24
T24
W24
AB24

TP_VTT<6>

NO_TEST

53

TP_VTT<7>
TP_VTT<8>

NO_TEST

TP_VTT<9>
TP_VTT<10>

NO_TEST

TP_VTT<11>

NO_TEST

53

53

53
53

U26
AD28
AH18
F25
C18
E14
AF8
Y8
K3
G3
F6
AF17

53

C27

53

FBD<97>

53

FBD<98>

53

FBD<99>

53

FBD<100>

B24
C23

FBD<104>
FBD<105>

E26
D26

FBD<106>
FBD<107>

E25

FBD<108>
FBD<109>

E24

53
53
53
53

1%
1/16W
MF
402

p
la

FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND
FBCAL_CLK_GND
52 FB_DLLVDD

FBACKE N30

54 FBACKE

FBACLK0 U21
FBACLK0* V21
FBACLK1 N21
FBACLK1* P21

FBACLK1
FBACLK1_L
FBACLK0
FBACLK0_L

M27

FBADQS0
K30
FBADQS1
G27
FBADQS2
D30
FBADQS3
AG30
FBADQS4
AD26
FBADQS5
AA29
FBADQS6
W27
FBADQS7

M26
L28
F27

D29
AG29
AE27
Y28

NC
NC

NC
NC
NC

53 54

FBDQS<1>
FBDQS<2>

53

FBDQS<7>

NC

53 54

53

FBDQS<5>
FBDQS<6>

NC

53 54

FBDQS<0>

FBDQS<3>
FBDQS<4>

NC

53 54

53

53
53

53

53
53

1
R5201
10K

1%
1/16W
MF
402

NOSTUFF

R5207

R5208

549

1%
1/16W
MF
402

5%
1/16W
MF
402

53
53
53
53
53
53

F22
E22

FBD<110>
FBD<111>

F21
A24

FBD<112>
FBD<113>

B23
C22

FBD<114>
FBD<115>

B22
B20

FBD<116>
FBD<117>

C19
B19

53
53

FBD<120>

53

FBD<121>

53

FBD<122>

53

FBD<123>

53

FBD<124>

E21
F19

53

FBD<125>

E18

53

FBD<126>

53

FBD<127>

D18
F18

55
55
55
55
55

B18
D23
D22
D21

FBDQM<8>

D11

FBDQM<9>
FBDQM<10>

B10
D7

FBDQM<11>
FBDQM<12>

C5
C26
F24

55

FBDQM<13>
FBDQM<14>

55

FBDQM<15>

55

FBBA<0>

55

FBBA<1>

A18
C17

FBBA<2>
FBBA<3>

B17
C16

FBBA<4>
FBBA<5>

B16

55

55

1%
1/16W
MF
402

55

C25

FBD<118>
FBD<119>

53

1 NV34
R5203
49.9

NOSTUFF

B26
B25

FBD<103>

53

1 NV34
R5202
49.9

B28
A28

FBD<101>
FBD<102>

53

s
p
to

B29
A29

53

53

7 52 54 55

A2
B2

53

53

W26

53

53

PP2V5_GPU

A3
B3

FBD<93>
FBD<94>
FBD<95>
FBD<96>

53

AF23
AH24
AH28
AG27
AF26
AF14
AH13
L8
P26
G28
K28
N28
V28
AA28
F30
J30
M30
W30
AB30
AE30
H26
L26
Y26
AC26
E17
D28
C7
E8
A9
C10
E11
C13
E20
C21
E23
C24
A6
A12
AH10
AK12
C3
D4
E5
AG4
AH3
AK6
AH7
AF5
AE6
AK9
N3
H11
AC11
H20
AC20
L23
Y23
F1
J1
M1
T1
W1
AB1
AE1
A19
AK19
A22
AK22
K5
J7
AE25

55

55
55
55
55
55

55

FBBA<12>

55

E16
F16

FBBA<8>
FBBA<9>

55

55

D16
A16

FBBA<6>
FBBA<7>

FBBA<10>
FBBA<11>

55

B21
D20

D15
F15
A15
G17

FBBBA<0>
FBBBA<1>

E15

FBBCLK1

K18

B15

WEAK PULL-DOWN

RECOMMANDED NY NVIDIA.

52

FBCD0 (4 BGA
OF 5)
FBCD1
OMIT
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
THERMAL GND
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

55 53

55 53

FBBCLK1_L
FBBCLK0

55 53

FBBCLK0_L

55 53

K17
K13
K14

N13
P13
U13
V13
M14
N14
P14
R14
T14
U14
V14
W14
M15
N15
P15
R15
T15
U15
V15

m
e
h
c

NO_TEST

53

E4

C8

NO_TEST

53

A25
AK25
AA5
AF20
AH16
AK15
AF11
AH21

FBCAL_CLK_GND E3

NC_FBADQS0*
NC_FBADQS1*
NC_FBADQS2*
NC_FBADQS3*
NC_FBADQS4*
NC_FBADQS5*
NC_FBADQS6*
NC_FBADQS7*

E10

E9

FBCAL_TERM_GND D3
FB_DLLVDD

NO_TEST

E13
F12

AC25

FBCAL_PD_VDDQ F5

FBARAS*
FBACAS*
FBAWE*
FBACS0*
FBACS1*

C28
TESTPOINT

NV18B

U25

0.1UF

10%

1 16V
CERM

F13
D13

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7
FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBCA12
FBCBA0
FBCBA1

FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7
NC_FBCDQS0*
NC_FBCDQS1*
NC_FBCDQS2*
NC_FBCDQS3*
NC_FBCDQS4*
NC_FBCDQS5*
NC_FBCDQS6*
NC_FBCDQS7*
FBCRAS*
FBCCAS*
FBCWE*
FBCCS0*
FBCCS1*
FBCCKE

W15
M16
N16
P16
R16
T16
U16
V16
W16
M17
N17
P17
R17
T17
U17

m
o

C5200
2

20%

1 10V
CERM

FBD<64>

P25

0.01UF

20%

1 10V
CERM

53

AC24
H25

C5229
2

10%

1 16V
CERM

7 52 54 55

G23
H24

0.1UF

20%

1 10V
CERM

G8

.
w
w
w

P28

GPU_FB_VREF
56

FBABA0
FBABA1

R25
R30

FBARAS_L
FBACAS_L

TP_FBACS1_L

R26
R29

T25
R27

FBA<9>
FBA<10>

FBABA<1>

U24

T30
T26

FBA<7>
FBA<8>

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12

T29
T27

FBA<5>
FBA<6>

FBABA<0>

54

AA30
Y27

FBA<3>
FBA<4>

54

54

AF28
AD27

FBA<1>
FBA<2>

54

54

W25

V30

54

54

W28
W29

FBA<0>

FBA<11>
FBA<12>

54

AD29
AC28

NV18B

FBAD0
BGA
FBAD1 (3 OF 5)
FBAD2
OMIT
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBVDDQ
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
NC_VTT
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
GND
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

48 49 50 51 56 57 58 59

N25

C5228
2

0.1UF

20%

1 10V
CERM

C5223

0.01UF

C5214

0.1UF

C5209
2

0.1UF

10%

20%

20%

1 16V
CERM

1 10V
CERM

1 10V
CERM

402

402

402

1 C5202
10UF
2

20%
6.3V
CERM
805

c
.
s
it c

V17
W17
M18
N18
P18
R18
T18
U18

V18
W18
M19
N19
P19
R19
T19
U19
V19
W19
P12
N12
V12
U12
M12
R12
T12
W12
M13
R13

T13
W13

D12

FBDQS<8>

53

A10
E7

FBDQS<9>

53

FBDQS<10>

53

A4

FBDQS<11>
FBDQS<12>

A27
D24
A21
D19
E12
C11
D6
B4
B27
D25
C20
E19

53
53

FBDQS<13>
FBDQS<14>

53
53

FBDQS<15>

53

NC
NC
NC
NC
NC
NC
NC
NC

C14

FBBRAS_L

55

B14
C15

FBBCAS_L
FBBWE_L

55

D17

FBBCS0_L
TP_FBBCS1_L

D14
A13

TESTPOINT

55

55
6

55 FBBCKE

1
R5200
10K

FBBCLK0
FBBCLK0*
FBBCLK1
FBBCLK1*

1%
1/16W
MF

WEAK PULL-DOWN

2 402
RECOMMENDED BY NVIDIA

FBBCLK 0 AND 1 SWAPPED FOR ROUTING REASONS

FBD<0>

C5227
2

0.01UF

20%

1 10V
CERM

G11
53

C5226
2

0.1UF

AMONGST FBVDDQ PINS ON NV ASIC

PP3V3_AGP
NV34

R5206

FB_DLLVDD

10
1

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

NV34
1

C5205

NV34

NV34

C5206

4.7UF

0.1UF

0.001UF

N20P80%
10V
CERM
805

20%
10V
CERM
402

10%
50V
CERM
402

2
1%
1/10W
FF
805

C5207

ALTERNATE STUFFING FOR 10 OHM R

IS FILTER APN 155S0052 PER NVIDIA SPEC

55 54 52 7 PP2V5_GPU

1
R5204
1K
1%
1/16W
MF

VOLTAGE=1.25V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

2 402

1
R5205
1K
1%
1/16W
MF

2 402

1 C5203
0.1UF
2

20%
10V
CERM
402

1 C5204
0.1UF
2

20%
10V
CERM
402

PLACE RS CLOSE TO MEMORY

52
52
52
52
52
52
52

52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52

C
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52

52
52
52
52
52
52
52

FBD<31>
FBD<30>
FBD<29>
FBD<28>
FBD<27>
FBD<26>
FBD<25>
FBD<24>
FBD<0>
FBD<1>
FBD<2>
FBD<3>
FBD<17>
FBD<16>
FBD<18>
FBD<19>
FBD<15>
FBD<14>
FBD<13>
FBD<12>
FBD<10>
FBD<11>
FBD<9>
FBD<8>
FBD<5>
FBD<6>
FBD<4>
FBD<7>
FBD<20>
FBD<21>
FBD<22>
FBD<23>

FBD<64>
FBD<65>
FBD<66>
FBD<67>
FBD<84>
FBD<85>
FBD<86>
FBD<87>
FBD<72>
FBD<73>
FBD<75>
FBD<74>
FBD<68>
FBD<70>
FBD<69>
FBD<71>
FBD<80>
FBD<81>
FBD<82>
FBD<83>
FBD<76>
FBD<77>
FBD<78>
FBD<79>
FBD<91>
FBD<90>
FBD<89>
FBD<88>
FBD<95>
FBD<94>
FBD<93>
FBD<92>

GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4

8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5

RP5320
RP5320
RP5320
RP5320
RP5321
RP5321
RP5321
RP5321
RP5322
RP5322
RP5322
RP5322
RP5323
RP5323
RP5323
RP5323
RP5324
RP5324
RP5324
RP5324
RP5325
RP5325
RP5325
RP5325
RP5326
RP5326
RP5326
RP5326
RP5327
RP5327
RP5327
RP5327

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

1
2
3
4
1
2
3
4
4
3
2
1
1
2
3
4
1
2
3
4
4
3
2
1
1
2
3
4
1
2
3
4

8
7
6
5
8
7
6
5
5
6
7
8
8
7
6
5
8
7
6
5
5
6
7
8
8
7
6
5
8
7
6
5

RP5310
RP5310
RP5310
RP5310
RP5309
RP5309
RP5309
RP5309
RP5319
RP5319
RP5319
RP5319
RP5308
RP5308
RP5308
RP5308
RP5307
RP5307
RP5307
RP5307
RP5317
RP5317
RP5317
RP5317
RP5318
RP5318
RP5318
RP5318
RP5303
RP5303
RP5303
RP5303

RFBD<31>
RFBD<30>
RFBD<29>
RFBD<28>
RFBD<27>
RFBD<26>
RFBD<25>
RFBD<24>
RFBD<0>
RFBD<1>
RFBD<2>
RFBD<3>
RFBD<17>
RFBD<16>
RFBD<18>
RFBD<19>
RFBD<15>
RFBD<14>
RFBD<13>
RFBD<12>
RFBD<10>
RFBD<11>
RFBD<9>
RFBD<8>
RFBD<5>
RFBD<6>
RFBD<4>
RFBD<7>
RFBD<20>
RFBD<21>
RFBD<22>
RFBD<23>

RFBD<64>
RFBD<65>
RFBD<66>
RFBD<67>
RFBD<84>
RFBD<85>
RFBD<86>
RFBD<87>
RFBD<72>
RFBD<73>
RFBD<75>
RFBD<74>
RFBD<68>
RFBD<70>
RFBD<69>
RFBD<71>
RFBD<80>
RFBD<81>
RFBD<82>
RFBD<83>
RFBD<76>
RFBD<77>
RFBD<78>
RFBD<79>
RFBD<91>
RFBD<90>
RFBD<89>
RFBD<88>
RFBD<95>
RFBD<94>
RFBD<93>
RFBD<92>

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52
52

55
55

52

55

52

FBD<96>
FBD<97>
FBD<98>
FBD<99>
FBD<100>
FBD<101>
FBD<102>
FBD<103>
FBD<104>
FBD<105>
FBD<106>
FBD<107>
FBD<108>
FBD<109>
FBD<110>
FBD<111>
FBD<112>
FBD<113>
FBD<114>
FBD<115>
FBD<116>
FBD<117>
FBD<118>
FBD<119>
FBD<120>
FBD<121>
FBD<122>
FBD<123>
FBD<124>
FBD<125>
FBD<126>
FBD<127>

p
la
52

55
55

52
52

55
55

52

55

52
52

55
55

FBD<32>
FBD<33>
FBD<34>
FBD<35>
FBD<36>
FBD<37>
FBD<38>
FBD<39>
FBD<40>
FBD<41>
FBD<42>
FBD<43>
FBD<44>
FBD<45>
FBD<46>
FBD<47>
FBD<48>
FBD<49>
FBD<50>
FBD<51>
FBD<52>
FBD<53>
FBD<54>
FBD<55>
FBD<56>
FBD<57>
FBD<58>
FBD<59>
FBD<60>
FBD<61>
FBD<62>
FBD<63>

.
w
w
w

52

GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

3
4
1
2
4
3
2
1
2
1
3
4
1
2
4
3
4
3
1
2
4
3
2
1
1
2
4
3
1
3
2
4

6
5
8
7
5
6
7
8
7
8
6
5
8
7
5
6
5
6
8
7
5
6
7
8
8
7
5
6
8
6
7
5

RP5328
RP5328
RP5328
RP5328
RP5316
RP5316
RP5316
RP5316
RP5329
RP5329
RP5329
RP5329
RP5330
RP5330
RP5330
RP5330
RP5331
RP5331
RP5331
RP5331
RP5300
RP5300
RP5300
RP5300
RP5301
RP5301
RP5301
RP5301
RP5302
RP5302
RP5302
RP5302

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

4
3
2
1
4
3
2
1
1
2
3
4
1
2
3
4
4
3
2
1
4
3
2
1
1
2
4
3
1
3
2
4

5
6
7
8
5
6
7
8
8
7
6
5
8
7
6
5
5
6
7
8
5
6
7
8
8
7
5
6
8
6
7
5

RP5315
RP5315
RP5315
RP5315
RP5314
RP5314
RP5314
RP5314
RP5312
RP5312
RP5312
RP5312
RP5313
RP5313
RP5313
RP5313
RP5311
RP5311
RP5311
RP5311
RP5306
RP5306
RP5306
RP5306
RP5304
RP5304
RP5304
RP5304
RP5305
RP5305
RP5305
RP5305

GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT

54
54
54

m
o

54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54

54
54
54
54
54
54

m
e
h
c

s
p
to
GPU128BIT

RFBD<32>
RFBD<33>
RFBD<34>
RFBD<35>
RFBD<36>
RFBD<37>
RFBD<38>
RFBD<39>
RFBD<40>
RFBD<41>
RFBD<42>
RFBD<43>
RFBD<44>
RFBD<45>
RFBD<46>
RFBD<47>
RFBD<48>
RFBD<49>
RFBD<50>
RFBD<51>
RFBD<52>
RFBD<53>
RFBD<54>
RFBD<55>
RFBD<56>
RFBD<57>
RFBD<58>
RFBD<59>
RFBD<60>
RFBD<61>
RFBD<62>
RFBD<63>

RFBD<96>
RFBD<97>
RFBD<98>
RFBD<99>
RFBD<100>
RFBD<101>
RFBD<102>
RFBD<103>
RFBD<104>
RFBD<105>
RFBD<106>
RFBD<107>
RFBD<108>
RFBD<109>
RFBD<110>
RFBD<111>
RFBD<112>
RFBD<113>
RFBD<114>
RFBD<115>
RFBD<116>
RFBD<117>
RFBD<118>
RFBD<119>
RFBD<120>
RFBD<121>
RFBD<122>
RFBD<123>
RFBD<124>
RFBD<125>
RFBD<126>
RFBD<127>

54

55
55
55
55

52

52

52

52

FBDQS<0>

FBDQS<1>

R5302
15

FBDQS<2>

FBDQS<3>

R5303
15

52

52

52

FBDQS<4>

FBDQS<5>

R5305
15

FBDQS<6>

FBDQS<7>

R5304
15

R5307
15

R5306
15
1%
1/16W
MF
402

RFBDQS<0>

RFBDQS<1>

RFBDQS<2>

RFBDQS<3>

1%
1/16W
MF
402

1%
1/16W
MF
402

R5300
15
1%
1/16W
MF
402

1%
1/16W
MF
402

52

1%
1/16W
MF
402

1%
1/16W
MF
402

RFBDQS<4>

RFBDQS<5>

RFBDQS<6>

RFBDQS<7>

54

54

54

54 52

FBACLK0

1%
1/16W
MF
402

54 52

FBACLK0_L

55 52

FBBCLK1

PLACE 100OHM TERM AT RAM

GPU128BIT

1
R5318
100
1%
1/16W
MF
402

PLACE 100OHM TERM AT RAM

55 52

FBBCLK1_L

55 52

FBBCLK0

55
55
55
55
55
55

GPU128BIT

1
R5319
100

55

55

1%
1/16W
MF
402

55
55

PLACE 100OHM TERM AT RAM

55
55 52

55

FBBCLK0_L

55
55
55

55
55
55
55
55
55
55

PLACE THESE R CLOSE TO SGRAM

GPU128BIT
52

FBDQS<8>
GPU128BIT

52

FBDQS<9>

52

52

FBDQS<10>

FBDQS<11>

52

52

52

52

R5314
15

R5315
15

FBDQS<12>

FBDQS<13>

R5312
15

R5309
15

R5310
15

1%
1/16W
MF
402

1%
1/16W
MF
402

FBDQS<14>

FBDQS<15>

R5313
15

1%
1/16W
MF
402

1%
1/16W
MF
402

R5308
15
1%
1/16W
MF
402

1%
1/16W
MF
402

GPU128BIT

1%
1/16W
MF
402

FBACLK1_L

55

GPU128BIT
54

54 52

PLACE 100OHM TERM AT RAM

55

GPU128BIT
54

1%
1/16W
MF
402

1
R5317
100

55

GPU128BIT
54

1
R5316
100

55

GPU128BIT
54

FBACLK1

55

GPU128BIT
54

54 52

55

PLACE THESE R CLOSE TO SGRAM

R5301
15

c
.
s
it c

PLACE RS CLOSE TO GPU

R5311
15
1%
1/16W
MF
402

RFBDQS<8>

55

RFBDQS<9>

55

RFBDQS<10>

55

RFBDQS<11>

55

RFBDQS<12>

55

RFBDQS<13>

55

RFBDQS<14>

55

RFBDQS<15>

55

1%
1/16W
MF
402

55 54 52 7

55 54 52 7

PP2V5_GPU

PP2V5_GPU

PLACE NEAR VDD PINS

55 54 52 7

PP2V5_GPU

PLACE NEAR VDD PINS

NVIDIA RECOMMENDS WIDER RANGE OF CAP VALUES

1 C5424
0.1UF
2

1 C5425
0.1UF

20%
10V
CERM
402

1 C5426
0.1UF

20%
10V
CERM
402

C5415

1 C5422
0.001UF

20%
10V
CERM
402

1 C5427
0.1UF

10%
50V
CERM
402

1 C5428
0.1UF

20%
10V
CERM
402

1 C5429
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5423
0.001UF
2

D
55 54 52 7

55 54 52 7

1 10UF
20%
6.3V
2 CERM
805

PP2V5_GPU
OMIT

OMIT

U5401
SDRAM_DDR_4MX32

U5400
SDRAM_DDR_4MX32

BGA

BGA
(2 OF 2)

C
54

SGRAVREF

VDD
VSS

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VDDQ

N13

VREF

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

OMIT

U5400
SDRAM_DDR_4MX32
54 52
54 52
54 52
54 52
54 52

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

54 52
54 52
54 52
54 52
54 52

53
53
53

52
52
52
52

54 52
54 52

1 C5434

0.1UF
2

20%
10V
CERM
402

VSSQ

53 52
54 52
54 52
54 52
54 52
54 52

B3
H12
H3
B12

DM0
DM1
DM2
DM3

FBABA<0>
FBABA<1>

N4
M5

BA0
BA1

M11
M12
N12
N2
M2
L2
L3

1 C5418
0.001UF
2

10%
50V
CERM
402

1 C5408
0.1UF

1 C5409
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5419
0.001UF
2

CK
CK
CKE
CS
RAS
CAS
WE

C4
C11
H4
H11
L12
L13
M3
M4
N3

55 54 52 7

10%
50V
CERM
402

1 C5411
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

NC

1 C5420
0.001UF
2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

p
la

PP2V5_GPU

.
w
w
w

1 C5410
0.1UF

BGA
(1 OF 2)

DQS0
DQS1
DQS2
DQS3

FBDQM<0>
FBDQM<3>
FBDQM<1>
FBDQM<2>

FBACLK0
FBACLK0_L
FBACKE
FBACS0_L
FBARAS_L
FBACAS_L
FBAWE_L

53 52

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

B2
H13
H2
B13

RFBDQS<0>
RFBDQS<3>
RFBDQS<1>
RFBDQS<2>

53

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

FBA<0>
FBA<1>
FBA<2>
FBA<3>
FBA<4>
FBA<5>
FBA<6>
FBA<7>
FBA<8>
FBA<9>
FBA<10>
FBA<11>

54 52

54 52

VSS_THERM

D7
D8
E4
E11
L4
L7
L8
L11

10%
50V
CERM
402

1 C5412
0.1UF

1 C5413
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

RFBD<7>
RFBD<5>
RFBD<6>
RFBD<4>
RFBD<2>
RFBD<3>
RFBD<1>
RFBD<0>
RFBD<31>
RFBD<30>
RFBD<29>
RFBD<28>
RFBD<27>
RFBD<26>
RFBD<25>
RFBD<24>
RFBD<15>
RFBD<14>
RFBD<13>
RFBD<12>
RFBD<10>
RFBD<11>
RFBD<8>
RFBD<9>
RFBD<23>
RFBD<22>
RFBD<21>
RFBD<20>
RFBD<19>
RFBD<16>
RFBD<18>
RFBD<17>

53
53
53
53
53
53
53
53
53
53
53
53

53
53
53
53
53
53
53
54

53
53

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VDDQ

SGRAVREF

N13

VREF

53

53
53
53

53
53
53

53

52 54

NO_TEST

55 54 52 7

DESCRIPTION

REFERENCE DES

333S0251

SDRAM,4MX32,DDR,300MHZ

U5400,U5401

CRITICAL

SAMSUNG

333S0252

SDRAM,4MX32,DDR,300MHZ

U5400,U5401

CRITICAL

HYNIX

QTY

CRITICAL

c
.
s
it c

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

RFBDQS<6>
RFBDQS<4>
RFBDQS<7>
RFBDQS<5>

B2
H13
H2
B13

DQS0
DQS1
DQS2
DQS3

FBDQM<6>
FBDQM<4>
FBDQM<7>
FBDQM<5>

B3
H12
H3
B12

DM0
DM1
DM2
DM3

FBABA<0>
FBABA<1>

N4
M5

BA0
BA1

FBACLK1
FBACLK1_L
FBACKE
FBACS0_L
FBARAS_L
FBACAS_L
FBAWE_L

M11
M12
N12
N2
M2
L2
L3

CK
CK
CKE
CS
RAS
CAS
WE

54 52
54 52
54 52

54 52
54 52
54 52
54 52
54 52
54 52

53
53
53
53

52
52
52
52

20%
10V
CERM
402

54 52

53 52
53 52
54 52
54 52
54 52
54 52
54 52

C5400
1 10UF
20%
6.3V
2 CERM
805

1 10UF
20%
6.3V
2 CERM
805

OMIT

U5401
SDRAM_DDR_4MX32

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

54 52

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

C5401

FBA<0>
FBA<1>
FBA<2>
FBA<3>
FBA<4>
FBA<5>
FBA<6>
FBA<7>
FBA<8>
FBA<9>
FBA<10>
FBA<11>

54 52

54 52

VSSQ

C4
C11
H4
H11
L12
L13
M3
M4
N3

BGA
(1 OF 2)

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

RFBD<48>
RFBD<49>
RFBD<50>
RFBD<51>
RFBD<53>
RFBD<52>
RFBD<54>
RFBD<55>
RFBD<32>
RFBD<33>
RFBD<35>
RFBD<34>
RFBD<37>
RFBD<36>
RFBD<38>
RFBD<39>
RFBD<57>
RFBD<56>
RFBD<58>
RFBD<59>
RFBD<62>
RFBD<60>
RFBD<61>
RFBD<63>
RFBD<41>
RFBD<40>
RFBD<42>
RFBD<43>
RFBD<44>
RFBD<47>
RFBD<45>
RFBD<46>

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

FBA<12> 52 54
TP_U5401_RFU2
NO_TEST

PP2V5_GPU

1 C5421
0.001UF

1 C5433
0.001UF

10%
50V
CERM
402

10%
50V
CERM
402

1 C5402
0.1UF

1 C5403
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5430
0.001UF
2

10%
50V
CERM
402

1 C5404
0.1UF

1 C5405
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5431
0.001UF
2

10%
50V
CERM
402

1 C5406
0.1UF

1 C5407
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5432
0.001UF
2

10%
50V
CERM
402

EVENLY PLACE 0.1UF CAP & 0.01UF CAPS

DDR SDRAM A VREF

PP2V5_GPU
55 54 52 7

1
R5400
1K
2

1%
1/16W
MF
402

1 C5416
0.1UF
2

20%
10V
CERM
402

SGRAVREF
1
R5401
1K

BOM OPTION

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

VSS_THERM

SGRAM0 & SGRAM1 MEMORY SUPPORT

PART NUMBER

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

54 52

0.1UF

s
p
to
2

VSS

1 C5435

53

FBA<12>
TP_U5400_RFU2

VDD

m
e
h
c

53

53

(2 OF 2)

C5414
1 10UF
20%
6.3V
2 CERM
805

m
o

10%
50V
CERM
402

PP2V5_GPU

D7
D8
E4
E11
L4
L7
L8
L11

1%
1/16W
MF
402

1 C5417
0.1UF
2

54

VOLTAGE=1.25V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

20%
10V
CERM
402

55 54 52 7

55 54 52 7

PP2V5_GPU

5
PP2V5_GPU

55 54 52 7

PLACE NEAR VDD PINS

PP2V5_GPU

PLACE NEAR VDD PINS

GPU128BIT

GPU128BIT

GPU128BIT

1 C5518
0.1UF
2

55 54 52 7

GPU128BIT

1 C5519
0.1UF

20%
10V
CERM
402

GPU128BIT

1 C5520
0.1UF

20%
10V
CERM
402

GPU128BIT

1 C5521
0.001UF

20%
10V
CERM
402

GPU128BIT

1 C5522
0.1UF

10%
50V
CERM
402

1 C5523
0.1UF

20%
10V
CERM
402

GPU128BIT

20%
10V
CERM
402

C5515

GPU128BIT

1 C5524
0.1UF

1 C5525
0.001UF

20%
10V
CERM
402

1 10UF
20%
6.3V
2 CERM
805

55 54 52 7

PP2V5_GPU
U5501

U5500

SDRAM_DDR_4MX32
BGA

SDRAM_DDR_4MX32
BGA

D7
D8
E4
E11
L4
L7
L8
L11

C
55

SGRBVREF

OMIT

VDD
VSS

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VDDQ

N13

VREF

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

U5500

55 52
55 52
55 52
55 52
55 52

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

55 52
55 52
55 52
55 52
55 52

53
53
53

52
52
52
52

B3
H12
H3
B12

DM0
DM1
DM2
DM3

FBBBA<0>
FBBBA<1>

N4
M5

BA0
BA1

55 52

GPU128BIT

0.1UF
2

20%
10V
CERM
402

VSSQ

M11
M12
N12
N2
M2
L2
L3

FBBCLK0
FBBCLK0_L
FBBCKE
FBBCS0_L
FBBRAS_L
FBBCAS_L
FBBWE_L

53 52
53 52
55 52
55 52
55 52
55 52
55 52

GPU128BIT

1 C5526
0.001UF
2

10%
50V
CERM
402

GPU128BIT

GPU128BIT

1 C5508
0.1UF
2

1 C5509
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

GPU128BIT

1 C5527
0.001UF
2

10%
50V
CERM
402

GPU128BIT

1 C5510
0.1UF
2

20%
10V
CERM
402

NC

20%
10V
CERM
402

GPU128BIT

1 C5528
0.001UF
2

10%
50V
CERM
402

GPU128BIT

1 C5512
0.1UF
2

20%
10V
CERM
402

OMIT

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

p
la

PP2V5_GPU

.
w
w
w
GPU128BIT

1 C5511
0.1UF

(1 OF 2)

CK
CK
CKE
CS
RAS
CAS
WE

C4
C11
H4
H11
L12
L13
M3
M4
N3

55 54 52 7

SDRAM_DDR_4MX32
BGA

DQS0
DQS1
DQS2
DQS3

FBDQM<8>
FBDQM<11>
FBDQM<9>
FBDQM<10>

55 52

1 C5534

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

B2
H13
H2
B13

RFBDQS<8>
RFBDQS<11>
RFBDQS<9>
RFBDQS<10>

53

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

FBBA<0>
FBBA<1>
FBBA<2>
FBBA<3>
FBBA<4>
FBBA<5>
FBBA<6>
FBBA<7>
FBBA<8>
FBBA<9>
FBBA<10>
FBBA<11>

55 52

55 52

VSS_THERM

GPU128BIT

1 C5513
0.1UF
2

20%
10V
CERM
402

GPU128BIT

RFBD<71>
RFBD<69>
RFBD<70>
RFBD<68>
RFBD<65>
RFBD<67>
RFBD<66>
RFBD<64>
RFBD<95>
RFBD<94>
RFBD<93>
RFBD<92>
RFBD<91>
RFBD<90>
RFBD<89>
RFBD<88>
RFBD<79>
RFBD<78>
RFBD<77>
RFBD<76>
RFBD<74>
RFBD<75>
RFBD<72>
RFBD<73>
RFBD<87>
RFBD<86>
RFBD<85>
RFBD<84>
RFBD<83>
RFBD<81>
RFBD<82>
RFBD<80>

DESCRIPTION

REFERENCE DES

333S0251

SDRAM,4MX32,DDR,300MHZ

U5500,U5501

CRITICAL

GPU128BIT_SAMSUNG

333S0252

SDRAM,4MX32,DDR,300MHZ

U5500,U5501

CRITICAL

GPU128BIT_HYNIX

QTY

CRITICAL

53
53
53
53
53
53
53
53
53
53
53
53

(2 OF 2)

OMIT

VDD

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VDDQ

N13

VREF

VSS

53
53
53
53
53
53
53
53

55

53

SGRBVREF

0.1UF

53

53

s
p
to
53
53
53
53

53

53

55

NO_TEST

20%
10V
CERM
402

VSSQ

55 54 52 7

55 52
55 52
55 52

55 52
55 52
55 52
55 52
55 52
55 52

53
53
53
53

52
52
52
52

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

55 52

53 52
53 52
55 52
55 52
55 52
55 52
55 52

GPU128BIT

C5501

C5500
1 10UF
20%
6.3V
2 CERM
805

U5501

SDRAM_DDR_4MX32
BGA

FBBA<0>
FBBA<1>
FBBA<2>
FBBA<3>
FBBA<4>
FBBA<5>
FBBA<6>
FBBA<7>
FBBA<8>
FBBA<9>
FBBA<10>
FBBA<11>

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

RFBDQS<14>
RFBDQS<12>
RFBDQS<15>
RFBDQS<13>

B2
H13
H2
B13

DQS0
DQS1
DQS2
DQS3

FBDQM<14>
FBDQM<12>
FBDQM<15>
FBDQM<13>

B3
H12
H3
B12

DM0
DM1
DM2
DM3

FBBBA<0>
FBBBA<1>

N4
M5

BA0
BA1

FBBCLK1
FBBCLK1_L
FBBCKE
FBBCS0_L
FBBRAS_L
FBBCAS_L
FBBWE_L

M11
M12
N12
N2
M2
L2
L3

CK
CK
CKE
CS
RAS
CAS
WE

C4
C11
H4
H11
L12
L13
M3
M4
N3

(1 OF 2)

OMIT

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

NO_TEST

RFBD<113>
RFBD<114>
RFBD<112>
RFBD<115>
RFBD<117>
RFBD<116>
RFBD<118>
RFBD<119>
RFBD<97>
RFBD<96>
RFBD<99>
RFBD<98>
RFBD<100>
RFBD<101>
RFBD<102>
RFBD<103>
RFBD<121>
RFBD<120>
RFBD<122>
RFBD<123>
RFBD<126>
RFBD<124>
RFBD<125>
RFBD<127>
RFBD<104>
RFBD<105>
RFBD<106>
RFBD<107>
RFBD<108>
RFBD<110>
RFBD<109>
RFBD<111>

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

FBBA<12> 52
TP_U5501_RFU2

DDR SDRAM B VREF

10%
50V
CERM
402

GPU128BIT

1 C5502
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5503
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5531
0.001UF
2

10%
50V
CERM
402

GPU128BIT

1 C5504
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5505
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5532
0.001UF
2

10%
50V
CERM
402

GPU128BIT

1 C5506
0.1UF

NO_TEST

20%
10V
CERM
402

20%
10V
CERM
402

GPU128BIT

1 C5533
0.001UF
2

10%
50V
CERM
402

EVENLY PLACE 0.1UF CAP & 0.01 UF CAPS

PP2V5_GPU

1GPU128BIT
R5500
1K
1%
1/16W
MF

2 402

GPU128BIT

1 C5516
0.1UF
2

20%
10V
CERM
402

SGRBVREF
GPU128BIT

1
R5501
1K
1%
1/16W
MF

2 402

55

GPU128BIT

1 C5507
0.1UF

GPU128BIT

1 C5517
0.1UF
2

55

VOLTAGE=1.25V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

20%
10V
CERM
402

BOM OPTION

53

GPU128BIT

1 C5530
0.001UF

10%
50V
CERM
402

55 54 52 7

55 52

GPU128BIT

1 10UF
20%
6.3V
2 CERM
805

PP2V5_GPU

1 C5529
0.001UF
2

c
.
s
it c
55 52

55 52

1 C5535

53

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

VSS_THERM

GPU128BIT

53

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

55 52

m
e
h
c

53

FBBA<12> 52
TP_U5500_RFU2

SGRAM0 & SGRAM1 MEMORY SUPPORT

PART NUMBER

D7
D8
E4
E11
L4
L7
L8
L11

GPU128BIT

C5514
1 10UF
20%
6.3V
2 CERM
805

m
o

10%
50V
CERM
402

PP2V5_GPU

(2 OF 2)

PP3V3_AGP

PART NUMBER
NOSTUFF

2
R5616
10K
1

5%
1/16W
MF
402

2 OMIT
R5625
10K

2
R5626
10K

2 OMIT
R5624
10K

2 OMIT
R5623
10K

1%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

1
57

VIPHCTL

57

1
R5638
10K

2
57

VIPD7

57

NOSTUFF

57

2
R5617
1K
1

57

2
R5618
1K

5%
1/16W
MF
402

57 51

5%
1/16W
MF
402

57 51

OMIT

2
R5643
10K

R5644
10K
5%
1/16W
MF
1 402

2 NOSTUFF
R5629
1K

5%
1/16W
MF
402

5%
1/16W
MF
402

2 OMIT
R5628
1K

2 OMIT
R5627
1K

5%
1/16W
MF
402

5%
1/16W
MF
402

OMIT

2 NOSTUFF
R5648
1K

R5647
1K
5%
1/16W
MF
1 402

0 = ENABLE AGP SIDEBAND

1 = AGP MODE
1 = DISABLE AGP SIDEBAND

REFERENCE DES

m
o

CRITICAL

BOM OPTION

116S1104

RES,10K-OHM,1/16W,5%

R5625,R5623

270MHZ_SAM_18

116S1104

RES,10K-OHM,1/16W,5%

R5644

270MHZ_SAM_18

116S1103

RES,1K-OHM,1/16W,5%

R5628

270MHZ_SAM_18

c
.
s
it c
116S1104

RES,10K-OHM,1/16W,5%

R5625,R5644

270MHZ_HYN_18

116S1103

RES,1K-OHM,1/16W,5%

R5628,R5627

270MHZ_HYN_18

111101 = 270MHZ SAMSUNG (NV34)

5%
1/16W
MF
402

[0] = [VIPD7]

DESCRIPTION

110011 = 270MHZ HYNIX (NV18B)

(6) AGP SIDEBAND

0 = PCI MODE

QTY

110111 = 270MHZ SAMSUNG (NV18B)

5%
1/16W
MF
402

NV_HSYNC
NV_VSYNC
GPU_STRAP<3>
GPU_STRAP<2>
DVOD3
DVOD2

2 OMIT
R5630
1K
(5) HOST MODE
[0] = [VIPHCTL]

(8) FRAME BUFFER MEMORY SPEED

[5..0] = [NV11_HSYNC,NV11_VSYNC,GPU_STRAP<3>,GPU_STRAP<2>,DVOD3,DVOD2]

PP3V3_AGP

PP3V3_AGP

116S1104

RES,10K-OHM,1/16W,5%

R5625,R5624

116S1104

RES,10K-OHM,1/16W,5%

R5623

270MHZ_SAM_34

116S1103

RES,1K-OHM,1/16W,5%

R5647

270MHZ_SAM_34

270MHZ_SAM_34

111100 = 270MHZ HYNIX (NV34)

PP3V3_AGP

2
R5663
10K
1

1%
1/16W
MF
402

NOSTUFF

2
R5631
10K

1%
1/16W
MF
402

5%
1/16W
MF
402

1%
1/16W
MF
402

52

57 51

NOSTUFF

NOSTUFF

2
R5665
1K

2
R5666
1K

5%
1/16W
MF
402

5%
1/16W
MF
402

1
57

DVOD8

1 = ADAPTER CARD VGA BIOS (VENDOR & SUBSYSTEM ID=0X54-0X57)

01 = SERIAL AT25F

p
la

10 = SERIAL SST45VF
11 = SERIAL FUTURE

PP3V3_AGP

.
w
w
w

NOSTUFF
NOSTUFF

2
R5667
10K

1
R5635
10K

5%
1/16W
MF

1 402

1%
1/16W
MF

57

57
57

57

VIPD6
VIPD2

57
57

NOSTUFF

2
R5601
1K
5%
1/16W
MF

1 402

5%
1/16W
MF
402

5%
1/16W
MF
402

2
R5614
1K
5%
1/16W
MF

1 402

2
R5611
1K
5%
1/16W
MF

1 402

2
R5610
1K
5%
1/16W
MF

1 402

THESE BITS ARE UNDEFINED BUT THEY

MUST BE KEPT LOW DURING RESET

1
R5636
10K

5%
1/16W
MF
402

1%
1/16W
MF
402

57 51
57
57
57

NOSTUFF

1
R5637
10K

5%
1/16W
MF

(10) PCI ADDRESS BUS

[0] = [GPU_STRAP<0>]
0 = REVERSED

1 = NORMAL

B
PP3V3_AGP

1%
1/16W
MF

2 402

2
R5605
10K

ANALOG_HSYNC_L
ANALOG_VSYNC_L

NOSTUFF

5%
1/16W
MF

1 402

2
R5607
1K

5%
1/16W
MF

5%
1/16W
MF

1 402

1 402

5%
1/16W
MF

1402

59 57 6

2
R5603
1K

NOSTUFF

2
R5620
10K

1 402

59 57 6

NOSTUFF

NOSTUFF

2
R5619
10K
5%
1/16W
MF

5%
1/16W
MF
402

DVOHSYNC
VIPD3
VIPD5
VIPD4

2
R5604
1K

1 402

NOSTUFF

2
R5602
10K

270MHZ_HYN_34

NOSTUFF

TMDS_XMIT_GPU

(4) USER DEFINED STRAPS

[3..0] = [VIPHAD1,VIPHAD0,VIPD1,VIPD0]

01 = 14.38MHZ

11 = {UNDEFINED}

2
R5609
10K

5%
1/16W
MF
402

VIPHAD1
VIPHAD0
VIPD1
VIPD0

00 = 13.5MHZ

10 = 27MHZ

2
R5608
10K

5%
1/16W
MF
402

2
R5615
1K

[1..0] = [VIPD6,VIPD2]

2
R5613
10K

5%
1/16W
MF
402

(2) CRYSTAL FREQUENCY SELECT

TMDS_XMIT_SI

1%
1/16W
MF
402

2
R5600
1K
1

NOSTUFF

2
R5612
10K
1

2 402

NOSTUFF

270MHZ_HYN_34

R5630,R5647

2
R5634
1K

PP3V3_AGP

PP3V3_AGP

R5624,R5623

RES,1K-OHM,1/16W,5%

GPU_STRAP<0>

0 = SYSTEM BIOS (VENDOR & SUBSYSTEM ID=0X0000)

00 = PARALLEL

s
p
to

(9) SUB-VENDOR

[0] = [GPU_STRAP<1>]

[1..0] = [ROMA15,ROMA14]

57

1 402

RES,10K-OHM,1/16W,5%

5%
1/16W
MF

5%
1/16W
MF

5%
1/16W
MF
402

116S1103

1 402

2
R5632
1K

FAST WRITE SUPPORT

0=ENABLE
1=DISABLE

(1) ROM TYPE (OVERRIDDEN IF STRAP1 = 0)

2
R5633
10K

GPU_STRAP<1>

2
R5658
1K
1

PP3V3_AGP

NOSTUFF

2
R5653
10K

ROMA15
ROMA14

52

PP3V3_AGP

2
R5664
10K

m
e
h
c

PP3V3_AGP

116S1104

NOSTUFF

NOSTUFF

2
R5622
1K

2
R5621
1K

5%
1/16W
MF

2
R5606
1K

1 402

5%
1/16W
MF

1 402

5%
1/16W
MF

1 402
(7) TV MODE
[1..0] = [ANALOG_HSYNC*,ANALOG_VSYNC*]

00 = SECAM

(3) PCI DEVICE ID

[3..0] = [DVOHSYNC,VIPD3,VIPD5,VIPD4]

01 = NTSC
10 = PAL

0010 = 0X112 GEFORCE2 GO

11 = DISABLED
0011 = 0X113 QUADRO2 GO

(THESE RESISTORS ARE ALL NOSTUFF)

0100 = 0X114 NV17M

0000 = 0X110 GEFORCE2GO MX (NV11B)

* 1001

= NV18B,NV31,NV34

U4900
59
59

L5702
1000-OHM-EMI

PP3V3_AGP

59 58 57 56 52 51 50 49 48 7

59

59

AG6
AG7

I2CC_SCL
I2CC_SDA

MON_I2C_SCL
MON_I2C_SDA

AG5
AF7

I2CA_SCL
I2CA_SDA

6
56

1 C5704
0.1UF

C5710
4.7UF

20%
6.3V
CERM
805

20%
10V
CERM
402

ANALOG_VSYNC_L

1 C5705
0.001UF
2

R5709
10

MF

56

10%
50V
CERM
402

56

TP_VIPHCLK
VIPHCTL

M5
M4

VIPHAD0
VIPHAD1

P3
P2

AK7

PPP3V3_NV_PLL

OMIT

L4

VIPCLK

VIPD0
VIPD1
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7

J3
J2
K2
K1
L3
L2
N2
N1

VIPD0
VIPD1
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7

VIPVDDQ0
VIPVDDQ1
VIPVDDQ2

L6
L7
M7

TESTPOINT
TESTPOINT

VIPHCLK
VIPHCTL

TESTPOINT

VIPHAD0
VIPHAD1

TESTPOINT

TESTPOINT

TESTPOINT

PLLVDD

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=3.3V

5%
402
1/16W

VIPPCLK

BGA

(2 OF 5)

2
SM

59 56 6

NV18B

GRAPH_DDC_SCL
GRAPH_DDC_SDA

VIPCAL_PD_VDDQ
VIPCAL_PU_GND

5%
1/16W
MF

56

2 402

56

c
.
s
it c
56
56
56
56

56

NOSTUFF

R5723

P6
VIPCAL_PD_VDDQ
P7 VIPCAL_PU_GND

NO_TEST

49.9

NO_TEST

R5710

ANALOG_HSYNC_L

59 56 6

MF

59 58 57 56 52 51 50 49 48 7

PP3V3_AGP

1C5702
0.1UF

C5711
4.7UF

59 6

20%
6.3V
CERM
805

ROUTE THE RGB LINES

AS 37.5 OHM TRACES.

1/16W

5%

R5724
49.9

402

2
SM

59 6

NOSTUFF

L5700
1000-OHM-EMI
1

59 6

10

20%
10V
CERM
402

10%
50V
CERM
402

AE3
AF3

VSYNC_L
HSYNC_L

1 C5701
0.001UF

PP3V3_NV_DACB

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

(GND)

ANALOG_BLU
ANALOG_GRN
ANALOG_RED
NOSTUFF
C5707 1
27PF
5%
50V
CERM
402

1
R5702
75

2
2

1%
1/16W
MF
402

5%
50V
CERM
402

NOSTUFF
C5708 1
27PF
5%
50V
CERM
402

R5704
75

1%
1/16W
MF
402

1
R5703
75

2
2

DAC2RSET
DAC2VREF

NOSTUFF
C5709 1
27PF

NOSTUFF
1

NOSTUFF
1

R5730
75

R5729

NOSTUFF
1

75

1%
1/16W
MF
402

DVOVREF
51 DVODE
DVOCLKOUT
TP_DVOCLKOUT_L
DVOCLKIN
DVOHSYNC
DVOVSYNC

1 C5703
0.01UF

1%
1/16W
MF
402

1%
1/16W
MF
402

10%
50V
X7R
603

51

56 51

PLACE CLOSE TO GPU

NV34

R5740
130

1%
1/16W
MF
2 402

NV18B
R5708
95.3

1%
1/16W
MF
402

NV34

NV18B1
R5700

5%
1/16W
MF
402

R5741
124

51

56 51

1%
1/16W
MF
2 402

51

56 51

121
1%
1/16W
MF
402

51
51

CVBS_D
D

51 50 49 48 7
59 58 57 56 52

CRITICAL

51

PP3V3_AGP

51

56 51

Q5700
58

CVBS_CNT

56
IRLML2502
48 7
52 51 50 49
SOT23
59 58 57

G
S

R5720
1K

5%
1/16W
MF
402

PP3V3_AGP

1
R5707
10K
5%
1/16W
MF
402

p
la
2

NOSTUFF
R5721

.
w
w
w
C5713
20%
16V
CERM
402

51

51

1
R5701
10K
5%
1/16W
MF
402

DVOD0
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11

1%
1/16W
MF
402

AD1
AD2
AE2

DACB_BLUE
DACB_GREEN
DACB_RED

AD3
AB5

DACB_RSET
DACB_VREF

AF4
AE4
AJ2
AK2
AG1
AD5
AD6

AG2
AH1
AG3
AJ1
AH2
AK1
AJ3
AK3
AH4
AK4
AJ4
AH5
AE8
AD8
AD9

DVOCAL_PD_VDDQ
DVOCAL_PU_GND

AB6
AB7

C5718

0.1UF

0.01UF

51

49.9

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

DACB_VDD
DACB_IDUMP

20%
10V
CERM
402

1 R5734
10K

TESTPOINT
TESTPOINT

TP_BUF_RST
TESTPOINT

B1

DACA_VSYNC
DACA_HSYNC
DACA_VDD
DACA_IDUMP

AJ8
AH9

NV_VSYNC
NV_HSYNC

AG9
AG10

m
e
h
c

DVOVREF
DVODE TESTPOINT
DVOCLKOUT TESTPOINT
DVOCLKOUT* TESTPOINT
DVOCLKIN
DVOHSYNC
DVOVSYNC TESTPOINT

DACA_BLUE
DACA_GREEN
DACA_RED

AJ9
AJ10
AK10

NC_DACC_BLUE
NC_DACC_GREEN
NC_DACC_RED

W7
Y7
AA6

NC_DACC_RSET AC5

DVOD0 STRAPS
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11

XTALSSIN

XTALIN

1%
1/16W
MF
402

1%
1/16W
MF
402

PP3V3_AGP

7 48 49 50 51 52 56 57 58 59

1C5706
0.1UF
20%
10V
CERM
402

C5716

0.1UF
20%
10V
CERM
402

NV34

R5727
1

56

NOSTUFF

1 C5720
0.1UF

C5712
4.7UF

VOLTAGE=6.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

20%
6.3V
CERM
805

1 C5721
0.001UF

20%
10V
CERM
402

AH6

10%
50V
CERM
402

5%
1/16W
MF
402

(GND)

DACRSET1
DACVREF1

NOSTUFF
1
1

NC

NC

C5717

20%
10V
CERM
402

NOSTUFF
1

R5733
75

121

0.1UF

NC

R5725
1%
1/16W
MF
402

NOSTUFF
1

R5732
75

1%
1/16W
MF
402

R5731
75

1%
1/16W
MF
402

1%
1/16W
MF
402

NC

GPU_XTALSSIN
1

R5726
10K

GPU_CLK27M_XIN

5%
1/16W
MF
402

PROPAGATION_DELAY=L:S::6.35 MM

XTALOUT

48 49 50 51 52 56 57 58

59

NOSTUFF

AJ7

AJ6

PP3V3_AGP 7

0
1
NOSTUFF

56

PP3V3_NV_DACA

DACA_BLUE
DACA_GREEN
DACA_RED

DACA_RSET AG8
DACA_VREF AH8

s
p
to
51

1
R5711
10K

PLACE CLOSE TO VGA CONNECTOR

AB4
AC4

R5728
75

1%
1/16W
MF
402

DACB_VSYNC
DACB_HSYNC

m
o

1
R5735
10K
56

GPU_CLK27M_XOUT
PROPAGATION_DELAY=L:S::6.35 MM

DVOVDD

XTALOUTBUFF
STRAP0
STRAP1
NC_STRAP2
NC_STRAP3

DVOCAL_PD_VDDQ
DVOCAL_PU_GND
BUFRST*

AJ5
G1
G2
F2
F3

TP_GPU_XTALOUTBUFF
GPU_STRAP<0>
GPU_STRAP<1>
GPU_STRAP<2>
GPU_STRAP<3>

56
56
56
56
NOSTUFF

NOSTUFF
R5722

R5706
5.1M

49.9

5%
1/16W
MF
603

1%
1/16W
MF
402

NOTE: KEEP STUB SHORT ->

Y5700
SM-3

5%
1/16W
MF
402

27.000M
CRITICAL
1 C5719
22PF
2

5%
50V
CERM
402

1 C5700
22PF
2

5%
50V
CERM
402

59 58 57 56 52 51 50 49 48 7

5
PP3V3_AGP

1
R5805
10K

1
R5804
10K

1%
1/16W
MF
402

1%
1/16W
MF
402

59 58 57 56 52 51 50 49 48 7

PP3V3_AGP

m
o
1
R5818
2K

U4900
NV18B
59

LAMP_STS

[IN]

47 1

MON_DETECT

[IN]

47

R5802

R5820

NV_GPIOD0

G5

MON_DETECT_R

F4

59 6

BGA

GPIOD0

402
1

GPIOD1

(5 OF 5)

[OUT]

LCD_PWM

47 1

R5803

G4

NV_GPIOD2

OMIT

GPIOD2

402

FPD_PWR_ON

59

57

[OUT]

CVBS_CNT

R5809

NV_GPIOD4

H5

GPIOD3

H4

GPIOD4

INV_CUR_HI

59

59

[IN]

TMDS_EN

47 1
1

R5830

NV_GPIOD5

J4

GPIOD5

R5808

NV_GPIOD6

J5

GPIOD6

1
R5806
10K
1%
1/16W
MF

2 402

59 58 57 56 52 51 50 49 48 7

402

10K 1

402

402

R5817

10K 1
10K 1

NV_GPIOD7

J6

R5816

NV_GPIOD8

K4

GPIOD8

R5815

NV_GPIOD9

K6

GPIOD9

TP_GPU_THERMC

H3

THERMD-

TP_GPU_THERMA

H2

THERMD+

10K 1
10K 1

402

10K 1

R5846 NV34

R5812

PPVCORE_GPU

PP3V3_AGP

C5810
0.1UF

20%
10V
CERM
402

PP3V3_AGP

L5800
1000-OHM-EMI
2

s
p
to

TP_FRWRLNKON
TP_FRWRLPS

p
la

20%
10V
CERM
402

OMIT
R5807
1K
1%
1/16W
MF
402

.
w
w
w
2

C5811
4.7UF
20%
6.3V
CERM
805

1 C5801
0.1UF
2

20%
10V
CERM
402

1 C5803
4.7UF

1 C5805
0.001UF
2

10%
50V
CERM
402

20%
6.3V
CERM
805

1 C5802
0.1UF
2

20%
10V
CERM
402

AF10
N6
M6
L5
N5

IFP0VREF

AA4

IFP0RSET

V6

IFP0PLLVDD

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SM

Y5
G24

TP_GPU_STEREO
GPU_TESTMECLK
TP_FRWR_PME_L

59 58 57 56 52 51 50 49 48 7

AF9
AD4

GPU_SWAP_A
GPU_SWAP_B

2
2

FPBCLKOUT
FPBCLKOUT*

m
e
h
c

NV34
R5845

C
50 49

M3
M2

TP_GPU_FPBCLKOUT
TP_GPU_FPBCLKOUT_L

402

NOSTUFF
1 C5800
0.1UF

58

58

GPU_TMDS_CKP
GPU_TMDS_CKM

R5833

U4
T4

58

58

GPU_TMDS_D0P
GPU_TMDS_D0M

SWAPRDY_A
SWAPRDY_B

STEREO
TESTMEMCLK

IFPATXD1
IFPATXD1*

Y2
AA1

IFPATXD2
IFPATXD2*

V3
W3

IFPATXD3
IFPATXD3*

U5
V4

TP_TMDS_TXD3P
TP_TMDS_TXD3M

IFPBTXC
IFPBTXC*

AA2
Y3

TP_EXT_TMDS_CKP
TP_EXT_TMDS_CKM

IFPBTXD4
IFPBTXD4*

W4
V5

TP_EXT_TMDS_D0P
TP_EXT_TMDS_D0M

IFPBTXD5
IFPBTXD5*

AB3
AB2

TP_EXT_TMDS_D1P
TP_EXT_TMDS_D1M

IFPBTXD6
IFPBTXD6*

Y6
W6

TP_EXT_TMDS_D2P
TP_EXT_TMDS_D2M

IFPBTXD7
IFPBTXD7*

AC3
AC2

TP_TMDS_TXD7P
TP_TMDS_TXD7M

IFPCTXC
IFPCTXC*

P5
P4

TP_DFPCLK
TP_DFPCLK_L

IFPCTXD0
IFPCTXD0*

R3
T2

TP_DFPD0
TP_DFPD1

IFPCTXD1
IFPCTXD1*

U2
T3

TP_DFPD2
TP_DFPD3

58

58

GPU_TMDS_D1P
GPU_TMDS_D1M

NC_FRWR_PME*
NC_FRWR_VAUXC
NC_FRWR_VAUXP
NC_FRWRLNKON
NC_FRWRLPS

IFPABVPROVE

IFPCTXD2
IFPCTXD2*

U3
V2

58

58

GPU_TMDS_D2P
GPU_TMDS_D2M

R5831
0 MF 5%

R5835

0 MF 5%

R5837

0 MF 5%

0 MF 5%

1/16W 402

TMDS_XMIT_GPU

R5840

1/16W 402

R5838

0
1

0
1

TMDS_XMIT_GPU

R5839

0
1

0 MF

SI_SDA
5%
2 R5832 SI_SCL

1/16W 402

0 MF 5%

TMDS_XMIT_GPU

R5836

1/16W 402

1/16W 402

TMDS_CKP

51 59
51 59

402
1/16W
MF
5%

TMDS_D0P

51 59

2 TMDS_D0M

51 59

TMDS_D1P
2 TMDS_D1M

1/16W
MF
5%

51 59
51 59

402
1/16W
MF
5%

1/16W

TMDS_D2P
2 TMDS_D2M

51 59
51 59

402

WHAT IS THE FREQUENCY OF THE Q27 PIXEL CLOCK?

BETH: 96.21MHZ

6
6

58

R5847

6
58

IFPCRSET

TP_IFP1VREF

R4

IFP1RSET

U10

IFPABPLLVDD

IFPCPLLVDD

P10

V10

IFPABPLLGND

IFPCPLLGND

N10

T5

IFPAIOVDD

IFPCIOVDD

R5

IFPCIOGND

R6

T6

IFPAIOGND
IFPBIOVDD

W5

IFPBIOGND

GPU_TMDS_CKP

49.9

6
1%
1/16W
MF 402

NOSTUFF

R5848

6
58

GPU_TMDS_CKM

49.9

6
1%
1/16W
MF 402

NOSTUFF

R5849

6
58

GPU_TMDS_D0P

49.9

6
1%
1/16W
MF 402

NOSTUFF

R5850

6
58

TP_DFPD5
TP_DFPD6

AA3

IFP0AVCC

NOSTUFF

GPU_TMDS_D0M

49.9

6
1%
1/16W
MF 402

NOSTUFF

MAKE TP AS SHORT AS POSSIBLE

IFPCVPROBE

IFPABRSET

Y4

51

402

R5851

6
58

GPU_TMDS_D1P

49.9

1%
1/16W
MF 402

GPU_IFB1IOVDD

NOSTUFF

R5852
58

IFP0AVCC

51

NOSTUFF

2 TMDS_CKM

TMDS_XMIT_GPU

R5834

NOSTUFF

MF 5%

1/16W 402

TMDS_XMIT_GPU

GPIOD7

PP3V3_AGP

402

W2
V1

5%
1/16W
MF

2 402

TMDS_XMIT_GPU

402

59 58 57 56 52 51 50 49 48 7

GRAPH_IIC_SDA2
GRAPH_IIC_SCL2

c
.
s
it c
IFPATXC
IFPATXC*

IFPATXD0
IFPATXD0*

402

AF6
AE7

TMDS_XMIT_GPU

402
[OUT]

I2CB_SDA
I2CB_SCL

1
R5819
2K

5%
1/16W
MF
402

TMDS_XMIT_GPU

402
59

GPU_TMDS_D1M

GPU_IFP1PLLVDD

49.9

1%
1/16W
MF 402

R5800
10K
1%
1/16W
MF
402

1
R5801
10K

1%
1/16W
MF
402

NOSTUFF

R5853

R5821
1K
5%
1/16W
MF
402

58

GPU_TMDS_D2P

49.9

1%
1/16W
MF 402

NOSTUFF

R5854

1 C5804
0.1UF
2

58

20%
10V
CERM
402

GPU_TMDS_D2M

49.9

1%
1/16W
MF
402

L5801
FERR-EMI-100-OHM
1

SM

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

IFP0AVCC

58

GPU TMDS SWING

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

114S1003

RES,1K OHM,1%,1/16W,0402

R5807

17_INCH_LCD

114S1503

RES,1.5K OHM,1%,1/16W,0402

R5807

20_INCH_LCD

TABLE_5_ITEM

1
NOSTUFF

D5900

EXTERNAL VGA CONNECTOR

PP5V_AGP

BAV99DW

R5926

INTERNAL TMDS CONNECTOR

7 49 50 59

TMDS_D2M

58 51

SOT-363

5%
MF
1/16W 402

SDF5900

STDOFF-118OD-181H-TH
57 56 6

ANALOG_HSYNC_L

R5904
200

m
o

1
5

57 56 6

ANALOG_VSYNC_L

53307-3091
GND_CHASSIS_VGA

F-ST-SM

7 59

CRITICAL

5%
50V
CERM
402

J5902

1 C5908
22PF

CRITICAL

(516S0096)

NOSTUFF

(514-0096)

J5903
MINI-VGA

SM-220MHZ

F-ST-TH
59 6

15
57 6

ANALOG_RED 1

CHECK RGB RETURN PINS

1
2

FL1701

LCFILTER

(RED_RTN)

(GRN_RTN)

8
9

10 6

11

SM-220MHZ

12

ANALOG_GRN 1

PP5V_USB2 92

DDC_VCC_5
VGA_IIC_DAT

1 C5905
0.01UF
10%
16V
CERM
402

18

GND_CHASSIS_VGA

FL1700

1 C5904
0.01UF
2

1 C5903
0.01UF

10%
16V
CERM
402

7 6

10%
16V
CERM
402

SM-220MHZ

57 6

57

VGA_IIC_CLK

GND_CHASSIS_VGA

7 59

D5902
BAV99DW

3 4

SOT-363

PP5V_AGP
MON_DETECT

1
R5911
2K

1
R5910
2K

5%
1/16W
MF
402

5%
1/16W
MF
402

ROUTE THE ANALOG RGB TRACES AT 37.5 OHMS.

R5908
33

MON_I2C_SCL

R5909
33

49 50 59

5%
50V
CERM
402

20_INCH_LCD

49 50 59

5%
50V
CERM
402

PP12V_RUN

17_INCH_LCD
NOSTUFF

NOSTUFF

SENSE

TO263-5

VPWR VOUT
VCTRL VOUT 6
ADJTAB

R5923

NOSTUFF

R5917

C5923

102

EZ1583

330UF

1%
1/16W
MF
402

20%
2 6.3V
POLY
SM-2

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

R5922

5%
1/8W
FF
2 1206

5%
1/8W
FF
2 1206

Q5900

10UF

C5925
10%
16V
CERM
1210

NOSTUFF

NOSTUFF

C5926

R5934

182

10%
50V
CERM
805
2

1%
1/16W
MF
402

5%
1/8W
FF
1206

.
w
w
w
0.0022UF
402

R5925
1

100K
5%
1/16W
MF
402

FPD_PWR_SW_G

20%
16V
CERM
402

OMIT

R5913
10K

10%
50V
CERM

5%
1/16W
MF
402

7 59

Q5901

58

5%
1/16W
MF
402

20_INCH_LCD

58

FPD_PWR_ON

1N5227B

A
PART#

DZ5900
SOT23

R5915
100K
5%
1/16W
MF
402

SM

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

RES,10K OHM,1/16W,5%,0402

R5913

17_INCH_LCD

116S1105

RES,100K OHM,1/16W,5%,0402

R5913

20_INCH_LCD

RES,330 OHM,1/16W,5%,0603

R5912

RES,1.2K OHM,1/16W,5%,0603

R5912

Q5903_GATE 3

6 59

2
R5907
2K

5%
1/16W
MF
402

5%
1/16W
MF

L5901
FERR-220-OHM

R5900
33

TMDS_D0P

58 51

TMDS_CKM

TD2P

6 59

MF
1/16W 402

R5928

0
2

L5908

SYM_VER-1

90-OHM

1%
1/16W
MF

2 402

3
NOSTUFF

TD1M

6 59

TD1P

6 59

TD0M

6 59

TD0P

6 59

TCKM

6 59

TCKP

6 59

2
MF
2 1/16W 402

NOSTUFF

R5930

0
2

5%
MF
1/16W 402

L5909
90-OHM

R5902
200

SYM_VER-1

SM

2
NOSTUFF

0 5%

R5931

MF
2 1/16W 402

NOSTUFF

10%
16V
CERM
402

R5932

0
2

5%
MF
1/16W 402

L5910
SYM_VER-1

90-OHM

R5901
200

SM

1%
1/16W
MF
2 402

2
NOSTUFF

0 5%

R5933
TMDS_CKP

58 51

MF
2 1/16W 402

1 C5901
0.01UF

TMDS_DDC_CLK

10%
16V
CERM
402

6 59

5%
1/16W
MF
402

INVERTER INTERFACE
20" LCD INVERTER NEED +24V.
17" LCD INVERTER NEED +12V.
17_INCH_LCD
CRITICAL

L5904

J5900

17_INCH_LCD

42375

FERR-220-OHM

59 50 7

PP12V_AGP

M-ST-TH

0805

L5905
1

100K 2

VOLTAGE=0V
MIN_LINE_WIDTH=100MIL
VOLTAGE=5V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=100MIL
MIN_NECK_WIDTH=10MIL

L5906

17_INCH_LCD

R5921

L5907

59 58

LCD_PWM

17_INCH_LCD

2
0805

L5911

17_INCH_LCD

Q5902
SM

58

LAMP_STS

2
0805

L5912

17_INCH_LCD
2

C5920

17_INCH_LCD

FERR-220-OHM

17_INCH_LCD

FERR-220-OHM
59 58

20%
10V
2 CERM
402

INV_CUR_HI

2
0805

17_INCH_LCD
17_INCH_LCD

330

5%
1/16W
MF
2 603

C5921

17_INCH_LCD
1

10UF

10UF

20%
16V
ELEC
SM

20%
16V
ELEC
SM

C5922

C5910

17_INCH_LCD
1

0.01UF
2

20%
50V
CERM
603

C5913

17_INCH_LCD
1

0.01UF
2

20%
50V
CERM
603

C5911

17_INCH_LCD
1

0.01UF
2

20%
50V
CERM
603

C5912

17_INCH_LCD
1

0.01UF
2

20%
50V
CERM
603

C5914

17_INCH_LCD
1

0.01UF
2

20%
50V
CERM
603

C5915
0.01UF

20%
50V
CERM
603

GND_CHASSIS_17_INCH_INVERTER

LED5900

20_INCH_LCD

GREEN
2.0X1.25

CRITICAL

L5913
7

J5901
53048

20_INCH_LCD

FERR-220-OHM

PP24V_GRAPHICS
1

RT-S-TH

2
0805

L5914

VOLTAGE=24V
MIN_LINE_WIDTH=100MIL
MIN_NECK_WIDTH=10MIL

1
2

VOLTAGE=0V
MIN_LINE_WIDTH=100MIL
MIN_NECK_WIDTH=10MIL

2
0805

L5915

PP24V_INV

20_INCH_LCD

FERR-220-OHM

GND_20_INV

INV_20_LCD_PWM_
INV_20_CUR_HI_F

20_INCH_LCD

FERR-220-OHM
59 58

LCD_PWM

518-0141

2
0805

TABLE_5_HEAD

L5916

NOTE:REMOVED 2 PINS:LAMP_STATUS &

ON/OFF FOR 20" LCD INVETER.

20_INCH_LCD

TABLE_5_ITEM

FERR-220-OHM
TABLE_5_ITEM

59 58

INV_CUR_HI

C5947

20_INCH_LCD

1UF

20%
50V
CERM 2
1210

20_INCH_LCD

2
0805

NOSTUFF
TABLE_5_ITEM

17_INCH_LCD

518-0135

C5942

20_INCH_LCD

1UF

20%
50V
2 CERM
1210

C5943

20_INCH_LCD

0.01UF
2

20%
50V
CERM
603

C5944

20_INCH_LCD

0.01UF
2

20%
50V
CERM
603

C5945

20_INCH_LCD

0.01UF
2

20%
50V
CERM
603

C5946
0.01UF

20%
50V
CERM
603

GND_CHASSIS_20_INCH_INVERTER

1N914
SOT23

FERR-220-OHM

0.1UF

5%
1/16W
MF
2 402

0805

MIN_LINE_WIDTH=100MIL
MIN_NECK_WIDTH=10MIL

2N7002

100K

17_INCH_LCD

PP5V_AGP_P_SEQ

10K

NOSTUFF

PP12V_INV
GND_17_INV
PP5V_AGP_RL
INV_17_LCD_PWM_F
LAMP_STS_F
INV_17_CUR_HI_F

FERR-220-OHM

Q5902_DRAIN

Q5902_GATE

D5901

5%
1/16W
MF
2 402

VOLTAGE=12V
MIN_LINE_WIDTH=100MIL
MIN_NECK_WIDTH=10MIL

17_INCH_LCD

FERR-220-OHM

5%
1/16W
MF
2 402
3

6 59

0805

PP12V_AGP

SM

0 5%

R5929

5%
1/16W
MF
402

5%
MF
1/16W 402

R5903
200

0805

R5920

R5916

R5912

58 51

3
5%
0
2

17_INCH_LCD

R5927

6 59

PP3V3_DDC

17_INCH_LCD

OMIT

C5900

200K

TABLE_5_ITEM

113S1123

PP5V_AGP

BOM OPTION

113S1332

TSOP

R5919

PPVCC_TMDS

TMDS_D0M

2
NOSTUFF

1%
1/16W
MF
2 402

0.01UF

TMDS_DDC_DAT

2
1

58 51

6 59

Q5903

17_INCH_LCD

SI3433DV

SILKSCREEN: 3

116S1104

R5906
33

17_INCH_LCD

0805

PPVCC_FPD

10%
16V
2 CERM
1210

TMDS_EN

2N7002

C5917

59 50 7

L5900
FERR-220-OHM

10UF

R5914
10K

FPD_PWR_ON_D

R5935

5%
1/8W
FF
1206

C5918

C5919

0.01UF

R5918

NOSTUFF

FPD_PWR_SW_S

0.022UF
2

PP12V_RUN

p
la

SO-8
1

NOSTUFF
1

10UF
2

FDS4465

NOSTUFF
1

FP_ADJ
NOSTUFF

6 7

PP3V3_RUN

10%
16V
CERM
1210

1 C5906
47PF

59 50 49 7

VR5900

C5909 1
47PF

VOLTAGE=3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

s
p
to
GND_CHASSIS_VGA

PP3V3_RUN

C5924

NOSTUFF

5%
1/16W
MF
402

TMDS_D1P

TD2M

NOSTUFF

GND_CHASSIS_TMDS

1 402

GRAPH_DDC_SCL

57

SOT-363

5%
1/16W
MF
402

BAV99DW

C5916

10%
16V
2 CERM
1210

1
R5905
2K

NOSTUFF

D5902
1

MON_I2C_SDA

PP5V_AGP
PP5V_AGP

7 49 50 59

5%
1/16W
MF
402

57

PP5V_AGP

PP3V3_AGP

58 51

57

58 57 56 52 51 50 49 48 7

7 49 50 59

6
58 6

GRAPH_DDC_SDA

m
e
h
c

7 59

LCFILTER
ANALOG_BLU 1

30

10%
16V
CERM
402

TMDS_D1M

6 59

10UF

1 C5902
0.01UF

14

58 51

28

29

17

6 59

TMDS_D2P

26

27

(BLU_RTN)

6 59

TMDS_DDC_CLK

24

25

13

3 4

22

23

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

6 59

TD1M
TD1P

20

21

TMDS_DDC_DAT

59 6

6 59

18

17

0805

6 59

TCKM
TCKP

16

15

19

FILT_ANALOG_RED
FILT_ANALOG_GRN
FILT_ANALOG_BLU

59 6

PP3V3_DDC

14

13

TD2M
TD2P

59 6

VOLTAGE=3.3V

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

12

11

16

L5903
FERR-220-OHM

PPVCC_TMDS

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

10

2
3 4

57 6

TD0M
TD0P

59 6

59 6

FL1702

LCFILTER

c
.
s
it c
4

3
5

58 51

SYM_VER-1

SM

1%
1/16W
MF
2 402

SDF5901
STDOFF-118OD-181H-TH

BAV99DW
SOT-363

90-OHM

D5900

5%
50V
CERM
402

NOSTUFF

L5902

1 C5907
22PF

0
2

ELECTRICAL_CONSTRAINT_SET

R6000
C6013

C6012

PP1V2_HT

64 62 60

20%
10V
2 CERM
402

10%
2 6.3V
CERM
402

64 62 60

HT_CLK
AVDD
27

64 62 60
64 62 60

64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60

64 60 7

64 62 60

PP2V5_HT

64 62 60
64 62 60

R6005 R6004 R6003 R6002

1K

1K

5%
1/16W
MF
2 402

C
64 62 60
64 62 60
64 62 60
64 62 60

1K

5%
1/16W
MF
2 402

1K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

64 62 60
64 62 60

64 62 60
64 62 60

7 24 60

0.1UF

H9 HT_CLK

HT_SB_TO_NB_CLK_P
HT_SB_TO_NB_CLK_N

N1 HT_CLK_RXP0
P1 HT_CLK_RXN0

PBGA
(SYM 5 OF 7)

HT
INTERFACE
OMIT

64 62 60

64 62 60

HT_CAD_TXP0 U8
HT_CAD_TXN0 U7

M2 HT_CAD_RXP3
M1 HT_CAD_RXN3
P2 HT_CAD_RXP4

HT_CAD_TXP3 R5
HT_CAD_TXN3 R6
HT_CAD_TXP4 P8

P3 HT_CAD_RXN4
R3 HT_CAD_RXP5
R2 HT_CAD_RXN5

HT_CAD_TXN4 P7
HT_CAD_TXP5 P6
HT_CAD_TXN5 P5

R1 HT_CAD_RXP6
T1 HT_CAD_RXN6
U1 HT_CAD_RXP7

HT_CAD_TXP6 M5
HT_CAD_TXN6 M6
HT_CAD_TXP7 M7

U2 HT_CAD_RXN7

HT_CAD_TXN7 M8

HT_PVTREF0 L7
HT_PVTREF1 L8

60 24 7

C6010
0.1UF

20%
2 10V
CERM
402

C6011
0.1UF

20%
2 10V
CERM
402

PP1V2_HT

C6000
0.1UF

20%
2 10V
CERM
402

C6001
0.1UF

20%
2 10V
CERM
402

C6002
0.1UF

20%
2 10V
CERM
402

0.1UF

20%
10V
2 CERM
402

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64
60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

60 62 64
60 62 64
60 62 64
60 62 64
60 62 64

60 62 64
60 62 64

R6001
200

1%
1/16W
MF
2 402

C6005
0.1UF

20%
2 10V
CERM
402

60 62 64

s
p
to

C6004

p
la

.
w
w
w

64 62 60

60 62 64

HT_NB_PVTREF0
HT_NB_PVTREF1

G8

PP2V5_HT

64 62 60

m
e
h
c

HT_NB_TO_SB_CTL_P
HT_NB_TO_SB_CTL_N

HT_CLK_AVSS

64 60 7

64 62 60

60 62 64

HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_N<7>

HT_CTL_TXP0 L6
HT_CTL_TXN0 L5

HT_LDTREQ*

60 62 64

64 62 60

HT_CAD_TXP1 U6
HT_CAD_TXN1 U5
HT_CAD_TXP2 U4
HT_CAD_TXN2 U3

H7

HT_NB_TO_SB_CLK_P
HT_NB_TO_SB_CLK_N

C6006
0.1UF

20%
2 10V
CERM
402

C6007
0.1UF

20%
2 10V
CERM
402

64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60

64 62 60
64 62 60
64 62 60
64 62 60

C6008

NET_SPACING_TYPE

DIFFERENTIAL_PAIR

HT_NB_TO_SB_CLK_P
HT_NB_TO_SB_CLK_N
HT_NB_TO_SB_CTL_P
HT_NB_TO_SB_CTL_N
HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_N<7>

HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB

HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2

HT_NB_TO_SB_CLK
HT_NB_TO_SB_CLK
HT_NB_TO_SB_CTL
HT_NB_TO_SB_CTL
HT_NB_TO_SB_CAD0
HT_NB_TO_SB_CAD0
HT_NB_TO_SB_CAD1
HT_NB_TO_SB_CAD1
HT_NB_TO_SB_CAD2
HT_NB_TO_SB_CAD2
HT_NB_TO_SB_CAD3
HT_NB_TO_SB_CAD3
HT_NB_TO_SB_CAD4
HT_NB_TO_SB_CAD4
HT_NB_TO_SB_CAD5
HT_NB_TO_SB_CAD5
HT_NB_TO_SB_CAD6
HT_NB_TO_SB_CAD6
HT_NB_TO_SB_CAD7
HT_NB_TO_SB_CAD7

HT_SB_TO_NB_CLK_P
HT_SB_TO_NB_CLK_N
HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N
HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<7>

HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB

HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2
HT_1V2

HT_SB_TO_NB_CLK
HT_SB_TO_NB_CLK
HT_SB_TO_NB_CTL
HT_SB_TO_NB_CTL
HT_SB_TO_NB_CAD0
HT_SB_TO_NB_CAD0
HT_SB_TO_NB_CAD1
HT_SB_TO_NB_CAD1
HT_SB_TO_NB_CAD2
HT_SB_TO_NB_CAD2
HT_SB_TO_NB_CAD3
HT_SB_TO_NB_CAD3
HT_SB_TO_NB_CAD4
HT_SB_TO_NB_CAD4
HT_SB_TO_NB_CAD5
HT_SB_TO_NB_CAD5
HT_SB_TO_NB_CAD6
HT_SB_TO_NB_CAD6
HT_SB_TO_NB_CAD7
HT_SB_TO_NB_CAD7

HT_PWROK
HT_RESET_L
HT_LDTSTOP_L
HT_LDTREQ_L

HT_PWROK
HT_CTL
HT_CTL
HT_CTL

HT_2V5
HT_2V5
HT_2V5
HT_2V5

m
o

c
.
s
it c
64 62 60

HT_CLK_TXP0 R7
HT_CLK_TXN0 R8

L3 HT_CAD_RXP1
L4 HT_CAD_RXN1
M4 HT_CAD_RXP2
M3 HT_CAD_RXN2

F9 HT_PWROK
G9 HT_RESET*
H8 HT_LDTSTOP*

HT_PWROK
HT_RESET_L
HT_LDTSTOP_L
HT_LDTREQ_L

64 62 60

U3LITE
V1.0-300MM

V2 HT_CTL_RXP0
V1 HT_CTL_RXN0

HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N

64 62 60

U3

L1 HT_CAD_RXP0
L2 HT_CAD_RXN0

HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<7>

64 62 60

VDD_HT
1_2

VDD_HT
2_5

HT_CLK66M_NB

N10

1UF

64 62 60
64 62 60

L9

7 60 64

N2
N6

5%
1/16W
MF
603

64 62 60

PP2V5_HT

PP1V5_PWRON_HT_NB_AVDD
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

R9

2.2

T4
T8

J10
G6

PP1V5_PWRON_NB_AVDD

F8

48 37 28 7

64 62 60

I46
I47
I83
I82
I51
I50
I52
I53

I54
I55
I56
I57
I58
I59
I60
I61
I62
I63
I64
I65

I48
I49
I84
I85
I66
I67
I68
I69
I70
I71
I72
I73
I74
I75

I76
I77
I78
I79
I80
I81

I86
I87
I88
I89

HT_1V2

HT_2V5

5 MIL SPACING FOR DIFF PAIR

10 MIL SPACING TO ANYTHING ELSE

4 MIL SPACING IN GROUP

8 MIL SPACING TO ANYTHING ELSE

LENGTH TOLERENCE DOES NOT NEED TO BE SPECIFIED

MATCHED GROUP CONSTRAINT IS TIGHT ENOUGH

0.1UF

20%
2 10V
CERM
402

8
ELECTRICAL_CONSTRAINT_SET

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR
HT_CLK66M_SB_C

15 MIL SPACING

62

Page Notes
Power aliases required by this page:
- _PP2V5_PWRON_HT
- _PP1V2_PWRON_HT

m
o

Signal aliases required by this page:

(NONE)
BOM options provided by this page:
(NONE)

_PP2V5_PWRON_HT

62 7

_PP1V2_PWRON_HT

FERR-EMI-600-OHM
1

20%
10V
2 CERM
402

SM
1

C6200
10uF

C6201
0.001uF

20%
6.3V
2 CERM
1206

_PP1V2_PWRON_HT

10%
50V
2 CERM
402

C6230

0.1uF

L6210

20%
2 10V
CERM
402

PP1V2_PWRON_HT_PLLAVDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

FERR-EMI-600-OHM
2

C6231

C6210

G11

B12

B9

B17
G13

B15

B19

C7

10%
50V
2 CERM
402

0.1uF

20%
10V
2 CERM
402

SHASTA
V1.0

64 60
64 60
64 60
64 60
64 60
64 60
64 60
64 60

64 60
64 60

64 60
64 60

C6255

64 60

0.1uF
1

HT_CLK66M_SB

332

1%
1/16W
MF
402 2

.
w
w
w

62

20%
10V
CERM
402

R62551

62 7

F13 HT_CTLIN_P
E13 HT_CTLIN_N

B14 HT_CADIN_7_P
A14 HT_CADIN_7_N

C18
E17

HT_CADOUT_5_N D12
HT_CADOUT_6_P E12
HT_CADOUT_6_N F12
HT_CADOUT_7_P A13
HT_CADOUT_7_N B13
HT_CTLOUT_P C13
HT_CTLOUT_N D13

HT_RESET_L
HT_LDTSTOP_L

HT_LDTREQ_L

C8 HT_REFCLK
D8 HT_S100M66M
V6 SEL_HT00_H

HT_CLK66M_SB_C
SB_HT_S100M66M
SB_SELHT100

AC coupled
1.0V pk-pk

C14 HT_CADIN_5_N
E14 HT_CADIN_6_P
F14 HT_CADIN_6_N

HT_CADOUT_4_P A11
HT_CADOUT_4_N B11
HT_CADOUT_5_P C12

_PP1V2_PWRON_HT

7 62

C6242
0.1uF

20%
10V
2 CERM
402

60 64
60 64

HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<7>

60 64

HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N

60 64

60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64

60 64

E16 HT_PWROK_H

HT_PWROK
HT_RESET_L
HT_LDTSTOP_L

p
la

B
27

HT_NB_TO_SB_CTL_P
HT_NB_TO_SB_CTL_N

s
p
to
B16 HT_CADIN_4_P
A16 HT_CADIN_4_N
D14 HT_CADIN_5_P

HT_CADOUT_2_N F11
HT_CADOUT_3_P D11
HT_CADOUT_3_N C11

HT_SB_TO_NB_CLK_P
HT_SB_TO_NB_CLK_N

HT_PLL
AGND DGND

A19 HT_LDTREQ_L

HT_R100P E10
HT_R100N F10

SB_HT_R100_P
SB_HT_R100_N

HT_RXGND

HT_TXGND

C6250 1
47pF

5%
50V
CERM 2
402

60 64

R6250
1

G10

64 60

HT_CADOUT_1_N A8
HT_CADOUT_2_P E11

A9

64 60

HT_CADOUT_0_P D10
HT_CADOUT_0_N C10
HT_CADOUT_1_P B8

A12

64 60

A18 HT_CADIN_1_N
F15 HT_CADIN_2_P
E15 HT_CADIN_2_N
D16 HT_CADIN_3_P
C16 HT_CADIN_3_N

HYPERTRANSPORT

64 60

D17 HT_CADIN_0_P
C17 HT_CADIN_0_N
B18 HT_CADIN_1_P

G12

64 60

HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_N<7>

A17

64 60
64 60

D15 HT_CLKIN_P
C15 HT_CLKIN_N

BGA
B10
(3 OF 8) HT_CLKOUT_P
HT_CLKOUT_N A10

A15

64 60

HT_NB_TO_SB_CLK_P
HT_NB_TO_SB_CLK_N

A6

64 60

C6

64 60

C6241

m
e
h
c
20%
10V
2 CERM
402

U2300

C6240
0.1uF

AVDD DVDD VDDP HT_RXVDD HT_TXVDD

HT_PLL
HT OMIT

C6232

20%
2 10V
CERM
402

C6211

7 62

0.1uF

20%
10V
2 CERM
402

0.001uF

20%
6.3V
2 CERM
1206

B6

10uF

0.1uF

SM
1

C6220
0.1uF

PP1V2_PWRON_HT_PLLDVDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

c
.
s
it c
1

L6200

82.5 2
1%
1/16W
MF
402

C6251
47pF

5%
50V
2 CERM
402

_PP1V2_PWRON_HT

NO STUFF

R62521

4.7K

5%
1/16W
MF
402 2

NO STUFF

R62531

R62511

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

4.7K

1K

HT RefClk

HT I/F Speed

1 = 100MHz
0 = 66MHz

1 = 100MHz
0 = 200MHz
(Internal Pull-Up)

DRAWING

TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Fri Nov 21 11:24:31 2003

m
o

SAME CONNECTORS & PINOUT AS

Q37 HYPERTRANSPORT BETWEEN GOLEM AND K2

NOSTUFF

NOSTUFF

J6400

J6401

P6860

P6860

ST-SM-DF

ST-SM-DF

SYM_VER1

SYM_VER1

HT_NB_TO_SB_CLK_N

A14

CLK-

HT_NB_TO_SB_CLK_P

A13

GND

62 60

62 60

HT_NB_TO_SB_CAD_P<6>

A12

62 60

B12
D15

B11

GND

B10

CLK+

A11

GND

62 60

HT_NB_TO_SB_CAD_N<6>

A10

62 60

HT_NB_TO_SB_CAD_N<4>

A9
A8

D9

HT_NB_TO_SB_CAD_P<4>

GND

62 60

A7

62 60

HT_NB_TO_SB_CAD_N<2>

A6
A5

D5

HT_NB_TO_SB_CAD_P<2>

A4

GND

62 60

B9
D11

B8

GND

B7

D7

B5

GND

B4

B3
B2

GND

B1

A3

62 60

HT_NB_TO_SB_CAD_P<0>

A1

A2

60 62

HT_NB_TO_SB_CAD_P<5>

60 62

HT_SB_TO_NB_CAD_N<0>

A13

62 60

HT_SB_TO_NB_CAD_N<2>

A12

HT_NB_TO_SB_CAD_P<3>

60 62

HT_NB_TO_SB_CAD_N<3>

60 62

62 60

B10

A11

D13

HT_SB_TO_NB_CAD_P<2>

A10

GND
D11

B8

GND

B7

HT_SB_TO_NB_CAD_P<4>

A9

HT_SB_TO_NB_CAD_N<4>

A7

B6

GND
D7

B5

GND

B4

62 60

HT_SB_TO_NB_CAD_P<6>

A6
A5

D5

A4

GND

62 60

HT_SB_TO_NB_CAD_N<6>

60 62

D6

B3
D3

D4

60 62

GND

62 60

HT_SB_TO_NB_CTL_P

62 60

HT_SB_TO_NB_CTL_N

A3
A2

GND

p
la

.
w
w
w
6

60 62

HT_SB_TO_NB_CAD_N<1>

60 62

B2
B1

D2
D1

HT_SB_TO_NB_CAD_P<3>

60 62

HT_SB_TO_NB_CAD_N<3>

60 62

HT_SB_TO_NB_CAD_N<5>

60 62

HT_SB_TO_NB_CAD_P<5>

60 62

HT_SB_TO_NB_CAD_N<7>

60 62

HT_SB_TO_NB_CAD_P<7>

c
.
s
it c
62 60

62 60

GND

NOSTUFF

P6860
ST-SM-DF
SYM_VER1

NOSTUFF

R6400

HT_SB_TO_NB_CLK_P

A15

A14

CLK-

A13

GND

TEK_HT_A12
TEK_HT_A10
TEK_HT_A9

NOSTUFF

5%
1/10W
MF
603
62 60

HT_LDTSTOP_L

B10

TEK_HT_B10

B9

HT_RESET_L

A10

D13

GND

A9
A8

TEK_HT_A7

D11

B8

GND

B7

A7

HT_PWROK

D10

B6

GND
D7

B5

GND

B4

D8

A6

HT_LDTREQ_L

60 62

D6

A5

D5

A4

GND

A3

62 60

60 62

D9

B3
D3

B2

GND

B1

D4

60 62

D14

D12

R6404
1

B11

GND

5%
1/10W
MF
603

TEK_HT_B12

D15

A12
A11

5%
1/10W
603

B12

CLK+

NOSTUFF

J6402

HT_SB_TO_NB_CLK_N

R6403

s
p
to
A1

D0

HT_SB_TO_NB_CAD_P<1>

m
e
h
c

D10
D9

D8

D1

B11

GND

D14

A8

D0

D15

D12

D2

B12

B9
62 60

HT_NB_TO_SB_CAD_N<1>

CLK-

GND

CLK+

HT_NB_TO_SB_CAD_N<5>

HT_NB_TO_SB_CAD_P<1>

A14
62 60

D6

D3

A15

60 62

62 60

B6

D4

HT_NB_TO_SB_CAD_N<0>

HT_NB_TO_SB_CAD_P<7>

HT_SB_TO_NB_CAD_P<0>

60 62

D10

D8

62 60

HT_NB_TO_SB_CAD_N<7>

D14
D13

D12

A15

62 60

HT_NB_TO_SB_CTL_N

60 62

HT_NB_TO_SB_CTL_P

60 62

D2

A2

D1

A1

GND

D0

PP2V5_HT
DEVELOPMENT

7 60

R6401

10K

5%
1/16W
MF

2 402

HT_VREF_DEBUG
VOLTAGE=1.25V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

DEVELOPMENT

R6402

10K

5%
1/16W
MF

2 402

8
ELECTRICAL_CONSTRAINT_SET

7
NET_SPACING_TYPE

PCI_AD<31..28>
PCI_AD<27>
PCI_AD<26..24>
PCI_AD<23>
PCI_AD<22>
PCI_AD<21>
PCI_AD<20>
PCI_AD<19..18>
PCI_AD<17>
PCI_AD<16..0>

PCI
PCI
PCI_CTL
PCI_CTL
PCI_CTL
PCI_CTL
PCI_CTL

PCI_CBE_L<3..0>
PCI_PAR
PCI_DEVSEL_L
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L

6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 76 77
6 74 76 77

m
o

6 74 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77

6 74 76 77
6 74 76 77
6 74 76 77
6 74 76 77
6 74 76 77
6 74 76 77
6 74 76 77

Page Notes
7

_PP3V3_SB_PCI

Signal aliases required by this page:

(NONE)

NO STUFF

0.1uF

C7402
0.1uF

C7403
0.1uF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

m
e
h
c

NO STUFF

10uF

20%
6.3V
2 CERM
805

C7405
0.1uF

C7406
0.1uF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C7407
0.1uF

20%
10V
2 CERM
402

C7408
0.1uF

C7409

C7420 1 C7421

0.1uF

20%
10V
2 CERM
402

0.1uF

20%
10V
2 CERM
402

20%
10V
CERM 2
402

H16
J21

C7411

E21

PCI1)
PCI0 or 2)
PCI0 or 2)
PCI0 or 2)
PCI0)

C7404
0.1uF

20%
2 10V
CERM
402

VDDOPC

c
.
s
it c
_PP2V5_PWRON_SB

C7422

20%
10V
CERM 2
402

PCIVDDP

U2300

0.1uF

N20
U20

C7401

20%
2 10V
CERM
402

J18

B20

0.1uF

U21
V19

C7400

20%
10V
2 CERM
402

AA22
B22

(0x106B/0x004F,
(0x1166/0x0240,
(0x106B/0x0050,
(0x106B/0x0052,
(0x106B/0x0051,

N21
R20

10uF

20%
2 6.3V
CERM
805

PCI Devices implemented on this page:

AD11 - PCI0
(0x106B/0x0053)
AD11 - PCI1
(0x106B/0x0054)
AD11 - PCI2
(0x106B/0x0055)
KeyLargo
SATA 150
UATA 133
FireWire
Ethernet

C7410

M16

BOM options provided by this page:

(NONE)

DIFFERENTIAL_PAIR

PCI_AD
PCI_AD27
PCI_AD
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD
PCI_AD17
PCI_AD

Power aliases required by this page:

- _PP3V3_PCI
- _PP3V3_SB_PCI (can be _PP3V3_PCI)
- _PP2V5_PWRON_SB

AD23
AD28
AD29
AD30
AD31

0.1uF

20%
10V
CERM 2
402

C7423

7 23 25 88

0.1uF

20%
10V
CERM 2
402

OMIT

SHASTA
V1.0

27

25 74 75 76 77

76 74 6
76 74 6

RP7400
4.7K
2

PCI_SLOTA_REQ_L

5%
1/16W
SM1

4.7K
1

p
la

6 74 76

74 77

RP7400
3

4.7K

PCI_SLOTG_GNT_L

74 77

.
w
w
w

5%
1/16W
SM1

RP7401
5%
1/16W
SM1

PCI_SLOTA_GNT_L

PCI_SLOTG_REQ_L

5%
1/16W
SM1

4.7K

77 74

5%
1/16W
SM1

RP7400

77 74

RP7400

B
4.7K
4

6 74 76

PCI_SLOTD_REQ_L

74

RP7401
4

4.7K

PCI_SLOTD_GNT_L

74

5%
1/16W
SM1

AB9 PCIBR_CLK_H

s
p
to

27 8

_PP3V3_PCI 7

PCI_CLK66M_SB_INT

74
74

76 75 6
76 75 6
76 75 6

PCI_CLK33M_SB_EXT

"Slot A" - AD17

PCI_SLOTA_REQ_L
PCI_SLOTA_GNT_L
"Slot G" - AD27
PCI_SLOTG_REQ_L
PCI_SLOTG_GNT_L
"Slot D" - AD20
PCI_SLOTD_REQ_L
PCI_SLOTD_GNT_L

U19 PCI1CLK_H

AB18

PCI1REQ_0_L

AA18

PCI1GNT_0_L

AB20
AB19

PCI1REQ_1_L
PCI1GNT_1_L

V17

PCI1REQ_2_L

V18

PCI1GNT_2_L

BGA
(4 OF 8)

PCI

PCI1AD_0_H L18
PCI1AD_1_H K19
PCI1AD_2_H L22
PCI1AD_3_H M22
PCI1AD_4_H M18
PCI1AD_5_H L20
PCI1AD_6_H M21
PCI1AD_7_H N16
PCI1AD_8_H M20
PCI1AD_9_H P22

PCI1AD_10_H M17
PCI1AD_11_H N18
PCI1AD_12_H M19
PCI1AD_13_H N19
PCI1AD_14_H P21
PCI1AD_15_H R22
PCI1AD_16_H P20
PCI1AD_17_H V21
PCI1AD_18_H P18
PCI1AD_19_H T20
PCI1AD_20_H R16
PCI1AD_21_H R17
PCI1AD_22_H W21
PCI1AD_23_H Y22
PCI1AD_24_H R18
PCI1AD_25_H T19
PCI1AD_26_H T18
PCI1AD_27_H Y21
PCI1AD_28_H W20

PCI1AD_29_H T16
PCI1AD_30_H AA21
PCI1AD_31_H T17
PCI1C_BE_0_L

L19

PCI1C_BE_1_L

P16
V22

PCI1C_BE_2_L
PCI1C_BE_3_L

AB8
AA9

ROM_CS_L
ROM_OE_L
ROM_WE_L

Y10

ROMCS_L
ROMOE_L
ROMRW_L

V20

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>

6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
77 76 75 74 25 7

_PP3V3_PCI

RP7402

6 74 75 76 77
6 74 75 76 77
77 76 74 6

PCI_DEVSEL_L

4.7K
5%
1/16W
SM1

RP7402

6 74 76 77
6 74 76 77
77 76 74 6

PCI_FRAME_L

4.7K

6 74 75 76 77

5%
1/16W
SM1

6 74 75 76 77
6 74 75 76 77
77 76 74 6

RP7402
2

PCI_IRDY_L

4.7K
5%
1/16W
SM1

RP7402

6 74 75 76 77
6 74 75 76 77
77 76 74 6

PCI_TRDY_L

4.7K

6 74 75 76 77

5%
1/16W
SM1

6 74 75 76 77

PCI_CBE_L<0>
PCI_CBE_L<1>
PCI_CBE_L<2>
PCI_CBE_L<3>

6 74 76 77

77 76 74 6

PCI_STOP_L

RP7401
7

4.7K

6 74 76 77
6 74 76 77

PCI1DEVSEL_L

T22

PCI1FRAME_L
PCI1IRDY_L

T21
R21

PCI1TRDY_L

P19

PCI1STOP_L
PCI1PAR_H

P17
N17

PCI_DEVSEL_L
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_PAR

PCI1RST_L

U18

SB_PCI_RESET_L

6 74 76 77
6 74 76 77
6 74 76 77
6 74 76 77
6 74 76 77

R7410

6 74 76 77

3.32K2

PCI_RESET_L 6

A
49 51 75 76 77

1%
1/16W
MF
402

Shasta drives PCI RESET, but its output

may not be valid during power-up, so
it is diode-ORed with output from SMU.

D7410
87 77 25 24 8

SYS_WARM_RESET_L

1N914
SOT23

5%
1/16W
SM1

6 74 76 77

LAST_MODIFIED=Fri Nov 21 11:24:32 2003

6 74 75 76 77

DRAWING

6 74 76 77

TITLE=LINK
ABBREV=DRAWING

6 74 75 76 77

Page Notes
Power aliases required by this page:
- _PP3V3_PCI
Signal aliases required by this page:
(NONE)

m
o

BOM options provided by this page:

(NONE)

NOTE: This page does not specify a BootROM

part number. Must use a TABLE_x_ITEM
symbol to declare U7500 part number.

77 76 75 74 25 7

_PP3V3_PCI

C7500 1 C7501
2.2uF

0.1uF

20%
10V
CERM 2
402

20%
10V
CERM 2
402

m
e
h
c
30

11

VPP

31

VCC

U7500

77 76 74 6
77 76 74 6
77 76 74 6
77 76 74 6
77 76 74 6
77 76 74 6
77 76 74 6
77 76 74 6

s
p
to
77 76 74 6
77 76 74 6
77 76 74 6
77 76 74 6
77 76 74 6
77 76 74 6

77 76 75 74 25 7

77 76 74 6

_PP3V3_PCI

77 76 74 6
77 76 74 6

R75001

76 74 6

ROM_CS_L

R7501

R7502
1

1K

p
la

5%
Allows ROM override module
1/16W
MF
to intercept ROM chip select

402

.
w
w
w

77 76 74 6

10K

5%
1/16W
MF
402 2

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>

10K

77 76 74 6

5%
1/16W
MF
2 402

77 76 74 6
77 76 74 6

76 6

76 74 6
76 74 6
6

77 76 74 51 49 6

C7502 1

0.1uF

20%
10V
CERM 2
805

ROM_ONBOARD_CS_L
ROM_OE_L
ROM_WE_L
ROM_WP_L
PCI_RESET_L

21
20
19
18
17
16
15
14

8
7

36

6
5
4
3
2
1

40
13
37
38

22
24
9
12
10

FEPR-1MX8
90.0ns
TSOP
DQ0
A0
A1 OMIT DQ1
DQ2
A2
DQ3
A3
DQ4
A4
DQ5
A5
DQ6
A6
DQ7
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20

25
26
27
28
32
33
34
35

PCI_AD<24> 6
PCI_AD<25> 6
PCI_AD<26> 6
PCI_AD<27> 6
PCI_AD<28> 6
PCI_AD<29> 6
PCI_AD<30> 6
PCI_AD<31> 6

c
.
s
it c

74 76 77
74 76 77
74 76 77
74 76 77
74 76 77
74 76 77
74 76 77
74 76 77

CE
OE
WE
WP
PWD

B
GND
23

39

DRAWING

TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Fri Nov 21 11:24:32 2003

8
ELECTRICAL_CONSTRAINT_SET
PCI_CLK_AIRPORT

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR
_PCI_CLK33M_AIRPORT

CLOCKS

8 76

Page Notes
Power aliases required by this page:
- _PP3V3_PCI

m
o

Signal aliases required by this page:

- _PCI_CLK33M_AIRPORT (33MHz PCI clock)

BOM options provided by this page:

(NONE)
PCI Devices implemented on this page:
AD17 (Slot "A") - AirPort (0x????/0x????)
NOTE: This AirPort implementation does
not support PME#.
77 75 74 25 7

_PP3V3_PCI
NO STUFF
1

NO STUFF

C7600

10UF

C7601
10UF

20%
2 6.3V
CERM
1206

20%
2 6.3V
CERM
1206

C7602
0.1UF

20%
2 10V
CERM
402

C7603
0.1UF

20%
2 10V
CERM
402

CRITICAL

J7600
RCPT-CARD-EDGE

F-ST-TH1

SIDE-A
77 75 74 51 49 6
6
74 6

77 75 74 6

PCI_RESET_L
TP_AIRPORT_RF_DISABLE
PCI_SLOTA_REQ_L

SIDE-B

8
10

11
77 75 74 6

77 75 74 6
77 75 74 6

12

13

PCI_AD<29>
PCI_AD<27>
PCI_AD<25>

14

15
17

18

20

21

PCI_CBE_L<3>

22

23
77 74 6
77 74 6
77 75 74 6

24

25

PCI_AD<23>
PCI_AD<21>
PCI_AD<19>

27

28

29

30

32

33

PCI_AD<17>

34

35

77 74 6

37

PCI_CBE_L<2>
PCI_IRDY_L

39

41

43

AIRPORT_CLKRUN_L_PD

45

77 74 6
77 75 74 6

47

PCI_CBE_L<1>
PCI_AD<14>

49

51

77 75 74 6
77 75 74 6
75 74 6
77 75 74 6
77 75 74 6

77 75 74 6

p
la

75 6

77 75 74 6

77 75 74 6
75 74 6

.
w
w
w
94 25 6

94 25 6

I2S1_DEV_TO_SB_DTI
SCC_RXDA

I2S1_SB_TO_DEV_DTO
SCC_TXDA

DEVELOPMENT

R7610
1

5%
1/16W
MF
402

53

PCI_AD<12>
PCI_AD<10>
ROM_WE_L
PCI_AD<8>
PCI_AD<7>

55
57

PCI_AD<5>
ROM_ONBOARD_CS_L
PCI_AD<3>

PCI_AD<1>
ROM_CS_L

RESERVED FOR RADIO_IO

NC

R76011

10K
5%
1/16W
MF
402 2

5%
1/16W
MF
402

42

44

46

50

52

54

58

63

64

65

66

67

68

69

70

71

72

73

74

75
77

76 NC
78 NC

79

80

81

82 NC

83

84 NC
86 NC
88 NC
90 NC

91

92 NC

93

94 NC
96 NC

97
99

6 74 75 77

6 74 75 77
6 74 75 77
6 74 75 77

PCI_AD<22>
PCI_AD<20>
PCI_PAR
PCI_AD<18>
PCI_AD<16>

6 74 77

R7600
1

22

PCI_AD<17> 6

74 75 76 77

5%
1/16W
MF
402

6 74 75 77
6 74 77

6 74 75 77
6 74 75 77

PCI_FRAME_L
PCI_TRDY_L
PCI_STOP_L
PCI_DEVSEL_L

6 74 77
6 74 77
6 74 77
6 74 77

PCI_AD<15>
PCI_AD<13>
PCI_AD<11>

6 74 75 77
6 74 75 77
6 74 75 77

56

60

95

PCI_AD<28>
PCI_AD<26>
PCI_AD<24>
PCI_SLOTA_IDSEL

48

62

89

NC
NC
NC
NC
NC

KEY

40

59

87

6 25

c
.
s
it c

38

61

85

I2S1_SB_TO_DEV_DTO_J

R7611
0

NC
NC
NC
NC

I2S1_DEV_TO_SB_DTI_J

DEVELOPMENT

36

s
p
to

77 74 6

26

31
77 76 75 74 6

6 74

16

19
77 74 6

PCI_SLOTA_GNT_L
TP_AIRPORT_PME_L
PCI_SLOTA_INT_L
PCI_AD<30>

8 76

m
e
h
c

PCI_AD<31>

_PCI_CLK33M_AIRPORT

PCI_AD<9>
PCI_CBE_L<0>
ROM_OE_L
PCI_AD<6>
PCI_AD<4>
PCI_AD<2>
PCI_AD<0>

6 74 75 77
6 74 77
6 74 75
6 74 75 77

6 74 75 77
6 74 75 77
6 74 75 77

RESERVED FOR USB_DP AND USB_DN

RESERVED FOR RADIO_IO

98 NC
100 NC

516-0069

PLACE R7610 AND R7611 CLOSE TO J9400

DRAWING

TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Fri Nov 21 11:24:33 2003

8
ELECTRICAL_CONSTRAINT_SET
PCI_CLK_USB2

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR
_PCI_CLK33M_USB2

CLOCKS

8 77

Page Notes
Power aliases required by this page:
- _PPVIO_PCI (to 3.3V or 5V)

m
o

Signal aliases required by this page:

- _PCI_CLK33M_USB2 (33MHz PCI clock)

BOM options provided by this page:

(NONE)
7

_PPVIO_PCI_USB2

PCI Devices implemented on this page:

AD27 (Slot "G") - USB2 (0x1033/0x0035)

C7703 1

NOTE: This USB2 implementation supports

D3cold.

0.1uF

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>

M5

(PCI_AD<27>)
6 PCI_AD<28>
6 PCI_AD<29>
6 PCI_AD<30>
6 PCI_AD<31>

C4

76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6

76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 74 6
76 74 6
76 74 6
76 75 74 6
76 75 74 6
76 75 74 6
76 75 74 6

PCI_AD<27>
76 75 74
76 75 74
76 75 74
76 75 74

76 74 6

R77141

76 74 6

22

76 74 6

5%
1/16W
MF
402 2

76 74 6

76 74 6

76 75 74 25 7

76 74 6

_PP3V3_PCI

76 74 6
76 74 6

B
RP7703
25

PCI_SLOTG_INT_L

47

.
w
w
w
3

47

5%
1/16W
SM1

76 75 74 51 49 6

47

5%
1/16W
SM1

RP7702
47

RP7702

SYS_WARM_RESET_L

47

5%
1/16W
SM1

PCI_RESET_L

5%
1/16W
MF
402 2

5%
1/16W
SM1

RP7703

SYS_PME_L

5%
1/16W
MF
402 2

RP7703
2

25 13

10K

5%
1/16W
SM1

87 74 25 24 8

10K

RP7702
2

47

74
74

77 8

P4
N4
M3
N3
M1
L2
L1
K2
L3
K1
K3
J2
J1
F2
E3
E1
D3
D1
D2
C2
C1
B4
A4
B5

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C5
B6
A6

M2
J3
F1
C3

C8

NEC_uPD720101_USB2
FBGA

m
e
h
c

s
p
to
A5

M4

CRITICAL

U7700

CBE0
CBE1
CBE2
CBE3

c
.
s
it c

J4

PCI_PAR
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_SLOTG_IDSEL
PCI_DEVSEL_L
PCI_SLOTG_REQ_L
PCI_SLOTG_GNT_L
NEC_PERR_L_PU
NEC_SERR_L_PU
NEC_INTA_L
NEC_INTB_L
NEC_INTC_L
_PCI_CLK33M_USB2

PAR
F3
FRAME
F4
IRDY
G1
TRDY
G3
STOP
B3 IDSEL
G2
DEVSEL
C6
REQ
D6
GNT
H2
PERR
H1
SERR OD
C7
INTA OD
B7
INTB OD
A7
INTC OD
A8
PCLK

NEC_VBBRST_L
NEC_CRUN_L_PD
NEC_PME_L
NEC_VCCRST_L
TP_NEC_SMI_L

B8
N6
D9
C9
L6

L7

NEC_LEGC_PD

VBBRST (CHIP RESET)

CRUN
PME OD
VCCRST (PCI RESET)
SMI OD

LEGC

B
IPD NTEST1 M8

TP_NEC_NTEST1

IPD

SMC M7

TP_NEC_SMC

IPD
IPD

TEB N7
AMC P7

TP_NEC_TEB
TP_NEC_AMC

IPD

TEST L8

NANDTEST
SRCLK
SRDTA
IPD SRMOD

M10
M9
N9
P9

TP_NEC_TEST

TP_NEC_NANDTEST
TP_NEC_SRCLK
TP_NEC_SRDATA
TP_NEC_SRMOD

6
6

6
6
6
6

5%
1/16W
SM1

RP7702 & RP7703 required to

facilitate NAND-tree testing

76 74 6

N5

PCI_CBE_L<0>
PCI_CBE_L<1>
PCI_CBE_L<2>
PCI_CBE_L<3>

p
la
76 74 6

R77161 R77131

P5

VDD_PCI

H3

20%
10V
CERM 2
402

R77151

RP7703

4.7K

5%
1/16W
MF
402 2

47
5%
1/16W
SM1
1

DRAWING

TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Fri Nov 21 11:24:33 2003

8
ELECTRICAL_CONSTRAINT_SET

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR

SATA_RXD1
SATA_RXD1

SATA
SATA

SATA_RXD1_C
SATA_RXD1_C

SATA_RXD_P1_C
SATA_RXD_N1_C

SATA_TXD1
SATA_TXD1

SATA
SATA

SATA_TXD1
SATA_TXD1

SATA_TXD_P1
SATA_TXD_N1

SATA_RXD2
SATA_RXD2

SATA
SATA

SATA_RXD2_C
SATA_RXD2_C

SATA_RXD_P2_C
SATA_RXD_N2_C

SATA_TXD2
SATA_TXD2

SATA
SATA

SATA_TXD2
SATA_TXD2

SATA_TXD_P2
SATA_TXD_N2

80 83

80 83

RP8000

80 83

80

80 83

80 83

80

80 83

6 80 83
6 80 83

80

6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
80 83
80 83
80 83

Page Notes

SATA_VDD x 5

_PP1V2_PWRON_DISK_SB

BOM options provided by this page:

(NONE)

C8000
0.1uF

20%
2 10V
CERM
402

Net Spacing Type: SATA

C8001
0.1uF

20%
10V
2 CERM
402

C8002
0.1uF

20%
2 10V
CERM
402

C8003

0.1uF

C8004

m
e
h
c

0.1uF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

AB14

Line To Line:
15 mils
Length Tolerance:
50 mils
Primary Max Sep:
10 mils outer
Primary Max Sep:
9 mils inner
Secondary Max Sep: 100 mils
Secondary Length: 500 mils

W15
Y18

AB17
T14

Signal aliases required by this page:

(NONE)

SATA_VDD

U2300

OMIT

c
.
s
it c

80

80

80

80

UATA_DD_R<1>

UATA_DD_R<3>

UATA_DD_R<5>

UD_IDEDD_2_H H6
UD_IDEDD_3_H E2
UD_IDEDD_4_H C1

s
p
to

UATA

UD_IDEDD_5_H C2
UD_IDEDD_6_H E3
UD_IDEDD_7_H G6

UD_IDEDD_8_H G5
UD_IDEDD_9_H D4
UD_IDEDD_10_H G7
UD_IDEDD_11_H F6
UD_IDEDD_12_H C3
UD_IDEDD_13_H F5
UD_IDEDD_14_H E5
UD_IDEDD_15_H D5

DSTROBE aka:
IORDY/HDMARDY*

UD_IDEDA0_H E6
UD_IDEDA1_H C4

STOP aka:
DIOW*

UD_IDEDA2_H D6

UATA_DSTROBE

F9 UD_IDECHRDY_H

UD_IDECS1FX_L
UD_IDECS3FX_L

B3
B4

83 80

UATA_DMARQ

D7 UD_IDEDMARQ_H

UD_IDEDMACK_L

E8

UATA_INTRQ

C5 UD_IDEINTRQ_H

UD_IDERD_L

83 80

E4
D3

80

83 80
83 80

83 80
83 80

SATA_RXD_P1_C
SATA_RXD_N1_C

Y17 RXDP1
Y16 RXDN1

SATA_RXD_P2_C
SATA_RXD_N2_C

AB15 RXDP2
AA15 RXDN2

AC coupling required for any SATA pair used.

Recommend 0.1uF cap placed close to Shasta.
(Caps provided by device page)

UD_IDEWR_L
UD_IDERST_L

E7

UATA_DD_R<0>
UATA_DD_R<1>
UATA_DD_R<2>
UATA_DD_R<3>
UATA_DD_R<4>
UATA_DD_R<5>
UATA_DD_R<6>
UATA_DD_R<7>
UATA_DD_R<8>
UATA_DD_R<9>
UATA_DD_R<10>
UATA_DD_R<11>
UATA_DD_R<12>
UATA_DD_R<13>
UATA_DD_R<14>
UATA_DD_R<15>
UATA_DA_R<0>
UATA_DA_R<1>
UATA_DA_R<2>
UATA_CS0_L_R
UATA_CS1_L_R

UATA_DMACK_L_R
UATA_HSTROBE_R
UATA_STOP_R
UATA_RESET_L_R

SATA 0
SATA 1

TXDP2 Y15
TXDN2 Y14

SATA_TXD_P2
SATA_TXD_N2

33

80

80

UATA_DD_R<12>

33

UATA_DD_R<13>

33

80

80

80

80

UATA_DD_R<15>

33

80
80

80

80

80

UATA_DA_R<1>

33

80
80

80

80

UATA_RESET_L_R

33

UATA_DD<8>

6 80 83

UATA_DD<9>

6 80 83

33

UATA_DD<10>

6 80 83

UATA_DD<11>

6 80 83

UATA_DD<12>

6 80 83

UATA_DD<13>

6 80 83

UATA_DD<14>

6 80 83

UATA_DD<15>

6 80 83

UATA_DA<0>

6 80 83

UATA_DA<1>

6 80 83

UATA_DA<2>

6 80 83

UATA_RESET_L

6 80 83

UATA_CS0_L

6 80 83

UATA_CS1_L

6 80 83

UATA_HSTROBE

6 80 83

UATA_STOP

6 80 83

UATA_DMACK_L

6 80 83

33

33

33

5%
1/16W
SM1

33

5%
1/16W
SM1

RP8004

80

6 80 83

RP8004

UATA_DA_R<2>

80

5%
1/16W
SM1

80

UATA_DD<7>

5%
1/16W
SM1

RP8001

80

6 80 83

RP8004

UATA_DA_R<0>

80

33

5%
1/16W
SM1

80

UATA_DD<6>

5%
1/16W
SM1

RP8003

80

6 80 83

RP8004

UATA_DD_R<14>

80

5%
1/16W
SM1

80

UATA_DD<5>

RP8001
3

6 80 83

5%
1/16W
SM1

RP8002
80

33

5%
1/16W
SM1

80

UATA_DD<4>

5%
1/16W
SM1

RP8002
UATA_DD_R<11>

6 80 83

RP8000

UATA_DD_R<10>

80

5%
1/16W
SM1

80

5%
1/16W
SM1

80

80

80

R8000
1

UATA_CS0_L_R

80

80
80

UATA_CS1_L_R

80

80 83
80

UATA_STOP_R

80 83
80 83

SATA_GND

80

UATA_DMACK_L_R

R8002

R8003

5%
1/16W
MF
402

UATA_HSTROBE_R

80 83

5%
1/16W
MF
402

80
80

33

33

5%
1/16W
MF
402

R8001

80

TXDP1 AA16 SATA_TXD_P1

TXDN1 AB16 SATA_TXD_N1

UATA_DD<3>

RP8002

UATA_DD_R<8>

UATA_DD_R<9>

6 80 83

5%
1/16W
SM1

RP8003
80

33

5%
1/16W
SM1

5%
1/16W
MF
402 2

W16

83 80

AA17
T13

.
w
w
w

HSTROBE aka:
DIOR*

AA14

p
la

UD_IDEDD_0_H J6
UD_IDEDD_1_H H7

33

UATA_DD<2>

RP8003
3

5%
1/16W
SM1

UATA_DD_R<6>

UATA_DD_R<7>

6 80 83

5%
1/16W
SM1

RP8001

RP8002
80

UATA_DD<1>

RP8001
1

33

33

5%
1/16W
SM1

6 80 83

5%
1/16W
SM1

RP8003
33

UATA_DD<0>

RP8000
2

5%
1/16W
SM1

R80051
10K

33

UATA_DD_R<4>

V1.0

BGA
(5 OF 8)

33

5%
1/16W
SM1

RP8000

UATA_DD_R<2>

SHASTA

NOTE: Target differential impedance for

SATA data pairs is 100 ohms.

UATA_DD_R<0>

m
o

80 83

UATA_DD<15..8>
UATA_DD<7>
UATA_DD<6..0>
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_HSTROBE
UATA_STOP
UATA_DMACK_L
UATA_RESET_L
UATA_DSTROBE
UATA_DMARQ
UATA_INTRQ

UATA_DD
UATA_DD7
UATA_DD
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST_R
UATA_HOST_R
UATA_DEV_R_C
UATA_DEV_R
UATA_DEV_R

UATA Termination

80 83

Power aliases required by this page:

- _PP1V2_PWRON_DISK

22

5%
1/16W
MF
402

22

R8004
1

22

5%
1/16W
MF
402

DRAWING

TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Fri Nov 21 11:24:34 2003

ELECTRICAL_CONSTRAINT_SET
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6

83 80
83 80

PATA CONNECTOR
C8304

PP3V3_DISK

PP12V_DISK

2
3
4
5

518-0144

.
w
w
w
7

6 7

PP5V_DISK

6 7

M-RT-TH

82

5%
1/16W
MF
402

C8301 1
10pF

5%
50V
CERM 2
402

UATA_CSEL_PD
NC

R8320

UATA_DMARQ

82

NC
NC

1K

5%
1/16W
MF
2 402

Obsolete

UATA_DD<8>
UATA_DD<9>
UATA_DD<10>
UATA_DD<11>
UATA_DD<12>
UATA_DD<13>
UATA_DD<14>
UATA_DD<15>
UATA_HSTROBE
UATA_DMACK_L
UATA_IOCS16_PU

6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83

6 80 83

6 80 83
6

NC
UATA_DA<2>
UATA_CS1_L

6 80 83
6 80 83

NC

51

S05B-XA

UATA_INTRQ

CRITICAL

J8303

83 80

R8316

p
la

HD POWER

83 80 6

83 80

83 80 6

s
p
to

5%
1/16W
MF
402

83 80 6

518-0070

20%
10V
CERM
402

82

12

80

10

SATA_RXD_P2_C

R8315

UATA_DSTROBE

SATA_RXD_P2

83 80

UATA_STOP
UATA_DSTROBE_R
UATA_INTRQ_R
UATA_DA<1>
UATA_DA<0>
UATA_CS0_L
UATA_DASP_L

20%
10V
CERM
402

0.1UF
1
2

80

C8306

5
6

SATA_RXD_N2_C

DEVELOPMENT

83 80 6

11

SATA_RXD_N2

0.1UF
1
2

16

80

C8300

20%
10V
CERM
402

14

15

83 80 6

SATA_TXD_N2
DEVELOPMENT

13

20%
10V
CERM
402

22

0.1UF
1
2

83 80 6

18

SATA_TXD_N2_C

83 80 6

20

M-ST-TH

83 80 6

R8312

17

CA-07SAHP-C-1

80

19

C8303

SATA_TXD_P2

26

J8302

0.1UF
1
2

21

SATA_TXD_P2_C
DEVELOPMENT

DEVELOPMENT

Sourced by drive
Terminate near connector

83 80 6

28

C8302

24

DEVELOPMENT

25

83 80 6

Per ATA Spec

UATA_RESET_L
UATA_DD<7>
UATA_DD<6>
UATA_DD<5>
UATA_DD<4>
UATA_DD<3>
UATA_DD<2>
UATA_DD<1>
UATA_DD<0>

27

83 80 6

NC

23

83 80 6

5%
1/16W
MF
2 402

F-ST-SM

4.7K

32

83 80 6

KX14

R8314

30

518-0070

J8301

29

m
e
h
c

20%
10V
CERM
402

36

80

10K

5%
1/16W
MF
402 2

CRITICAL

34

SATA_RXD_P1_C

5%
1/16W
MF
402 2

31

0.1UF
1
2

SATA_RXD_P1

80

35

NO STUFF

33

20%
10V
CERM
402

DIFFERENTIAL_PAIR

R83111

42

C8308

10K

38

R8313
SATA_RXD_N1_C

40

0.1UF
1
2

41

SATA_RXD_N1

NO STUFF

37

NET_SPACING_TYPE

ATA-6 spec does not call out R8180 or R8182

C8307

20%
10V
CERM
402

PP3V3_PATA

39

46

80

48

SATA_TXD_N1

0.1UF
1
2

44

SATA_TXD_N1_C

43

M-ST-TH

PP5V_PATA

50

20%
10V
CERM
402

C8305

CA-07SAHP-C-1

83 7

45

80

47

SATA_TXD_P1

52

J8300

0.1UF
1
2

49

SATA_TXD_P1_C

NET_PHYSICAL_TYPE

UATA_DD
UATA_DD7
UATA_DD
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST_R
UATA_HOST_R
UATA_DEV_R_C
UATA_DEV_R
UATA_DEV_R

m
o

c
.
s
it c
83 80

SATA CONNECTORS

UATA_DD<15..8>
UATA_DD<7>
UATA_DD<6..0>
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_HSTROBE
UATA_STOP
UATA_DMACK_L
UATA_RESET_L
UATA_DSTROBE
UATA_DMARQ
UATA_INTRQ

UATA_DMARQ_R

5%
1/16W
MF
402

518S0077
J8301 DOES NOT MATCH NORMAL ATA PINOUT
CONNECTOR IS ROTATED 180 DEGREES

ATA-6 spec does not call out C8177

83 7

R83191

PP5V_PATA

R8318 1R8317

5.6K

R8321

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

499

1%
1/16W
MF
402 2

10K

5%
1/16W
MF
2 402
Per ATA Spec

Per ATA Spec

Per ATA Spec

LED8301

UATA_DASP_L_DS

GREEN
2.0X1.25

"UATA ACTIVE"

8
ELECTRICAL_CONSTRAINT_SET
ENET_RX_CLK
ENET_RX_CLK
ENET_GBE_REF
ENET_TX_CLK

7
NET_SPACING_TYPE
10
10
15
15
15

DIFFERENTIAL_PAIR
ENET_CLK25M_TX
ENET_CLK125M_RX
ENET_CLK125M_GBE_REF
ENET_CLK125M_GTX
ENET_CLK125M_GTX_R

MIL
MIL
MIL SPACING
MIL SPACING
MIL SPACING

ENET_RX
ENET_RX_CTL
ENET_RX_CTL

ENET_RXD<7..0>
ENET_RX_DV
ENET_RX_ER

ENET_TX
ENET_TX_CTL
ENET_TX_CTL

ENET_TXD<7..0>
ENET_TX_EN
ENET_TX_ER

ENET_RX_CTL
ENET_RX_CTL
ENET_MDC
ENET_MDIO

ENET_CRS
ENET_COL
ENET_MDC
ENET_MDIO

84 87
84 87
84 87
84 87
84

m
o

84 87
84 87
84 87

84 87
84 87
84 87

84 87
84 87
84 87
84 87

Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

m
e
h
c

OMIT

U2300
SHASTA
V1.0

87 84

87 84
87 84
87 84
87 84
87 84
87 84
87 84
87 84

87 84
87 84

ENET_CLK25M_TX
ENET_CLK125M_RX
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RXD<4>
ENET_RXD<5>
ENET_RXD<6>
ENET_RXD<7>
ENET_RX_DV
ENET_RX_ER

.
w
w
w

ETH_TXD_0_H G4
ETH_TXD_1_H E1
ETH_TXD_2_H H4

J2 ETH_RXD_6_H
G1 ETH_RXD_7_H

ETH_TXD_6_H J4
ETH_TXD_7_H K6

ENET_TXD_R<0>
ENET_TXD_R<1>
ENET_TXD_R<2>
ENET_TXD_R<3>
ENET_TXD_R<4>
ENET_TXD_R<5>
ENET_TXD_R<6>
ENET_TXD_R<7>

K4 ETH_RX_DV_H
G2 ETH_RX_ER_H

ETH_TX_EN_H H3
ETH_TX_ER_H F1

ENET_TX_EN_R
ENET_TX_ER_R

s
p
to
J1 ETH_RXD_3_H
L4 ETH_RXD_4_H
K3 ETH_RXD_5_H

ETH_TXD_3_H J5
ETH_TXD_4_H G3
ETH_TXD_5_H F2

87 84

ENET_CLK125M_GBE_REF

M5 ETH_REFCLK_H

87 84

ENET_CRS

L6 ETH_CRS_H

ETH_MDC_H M4

87 84

ENET_COL

L5 ETH_COL_H

ETH_MDIO_H M6

p
la

K1 ETH_RXD_0_H
L3 ETH_RXD_1_H
K2 ETH_RXD_2_H

ETHERNET

87 84

BGA
(6 OF 8)
H5 ETH_TX_CLK_H
J3 ETH_RX_CLK_H

ETH_GTX_CLK_H K5

84

ENET_CLK125M_GTX_R
ENET_MDC

84 87

ENET_MDIO

84 87

c
.
s
it c
RP8400
2

0K

84 87

ENET_TXD<3>

84 87

0K

ENET_TXD<4>

84 87

ENET_TXD<5>

84 87

0K

ENET_TXD<6>

84 87

ENET_TXD<7>

84 87

ENET_TX_EN

84 87

ENET_TX_ER

84 87

ENET_CLK125M_GTX

84 87

5%
1/16W
SM1

RP8401
6

5%
1/16W
SM1

R8400
1

5%
1/16W
MF
402

R8401
0

ENET_TXD<2>

RP8401
1

5%
1/16W
MF
402

5%
1/16W
SM1

84 87

5%
1/16W
SM1

RP8401

0K

ENET_TXD<1>

RP8401
2

0K

5%
1/16W
SM1

0K

84 87

5%
1/16W
SM1

RP8400

ENET_TXD<0>

RP8400
1

0K

5%
1/16W
SM1

0K

5%
1/16W
SM1

RP8400
4

R8402
1

5%
1/16W
MF
402

DRAWING

TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Fri Nov 21 11:24:35 2003

ELECTRICAL_CONSTRAINT_SET

NET_SPACING_TYPE

DIFFERENTIAL_PAIR

ETHERNET ROUTING PRIORITY:

ENET_MDI_TX
ENET_MDI_TX

ENET
ENET

ENET_MDI_TD
ENET_MDI_TD

ENET_TDP
ENET_TDN

ENET_MDI_RX
ENET_MDI_RX

ENET
ENET

ENET_MDI_RD
ENET_MDI_RD

ENET_RDP
ENET_RDN

1. DECOUPLING CAPS
87

2. TX TERMINATION - LOCATE NEAR PHY

87

3. RX TERMINATION - LOCATE NEAR PHY

m
o

87
87

PP2V5_ENET

D
1

87 7

ENET_DVDD

0.1UF
20%
10V
CERM
402

C8704

C8702

0.01UF
20%
16V
CERM
402

0.1UF
20%
10V
CERM
402

C8705

0.01UF
20%
16V
CERM
402

C8712
2.2UF
20%
10V
CERM
805

0.01UF
20%
16V
CERM
402

22

NC
46

28

C8709

0.1UF
20%
10V
CERM
402

27

C8715

0.01UF
20%
16V
CERM
402

55

C8708

0.1UF
20%
10V
CERM
402

C8716

2.2UF
20%
10V
CERM
805

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

20

C8711

PP3V3_PWRON_ENET

C8703

84
84
84
84

84

CLK_ENET_LINK_RX
NET_SPACING_TYPE=10 MIL

84

SM1

84

33

RP8701

33

1/16W

5%

1/16W

5%

RP8701

62
61

ETHPHYRESET_L

33

1/16W

SYS_WARM_RESET_L

ENET_PHY_CRS
ENET_PHY_COL

51

D8700
77 74 25 24 8

49

RP8701

ENET_RX_ER
ENET_CRS
ENET_COL

ENET_PHY_RX_DV
ENET_PHY_RX_ER

84

5%

ENET_MDC

42
41

NET_SPACING_TYPE=10 MIL

6
5

1N914
SOT23

ENET_MDIO

84

ENETFW_RESET_L
3

Q8700

2N7002

R8711
0

NC

R8719
1K

NC

90

87

SHASTA SIGNAL IS ACTIVE HIGH

NC

5%
1/16W
MF
402

PP3V3_PWRON_ENET

R8708

NC

1.5K

NC

SM
1

C8723
1UF
20%
10V
CERM
603

5%
1/16W
MF
402

(PLACE Y8700 CRYSTAL

25
87

14

Y8700

FOR ALTERNATE CRYSTAL

25.0000M
1
2

87

ENET_CLK25M_XOUT

8X4.5MM-SM

C8701

C8700
27PF
5%
50V
CERM
603

87

27PF
5%
50V
CERM
603

PP3V3_PWRON_ENET

A
C8720
4.7UF
20%
10V
CERM
1206

C8719
0.1UF
20%
10V
CERM
402

C8718
0.1UF
20%
10V
CERM
402

C8717
0.1UF
20%
10V
CERM
402

87

OGND3_JTAG_EN

C8713
10UF
20%
6.3V
CERM
1206

84

84

84

84

BIASVDD

OVDD2

REFCLK

OVDD1

AVDD2

OVDD/NC

39
37
38
15
18
16

LNKLED/JTAG_TDI*
SPDLED/JTAG_TMS*
XMTLED*
RCVLED/JTAG_TDO*

17

35

36
34

33

1%
1/16W
MF
402

5%
1/16W
MF
402

ENET_ENERGYDET

23

R8713

25

ENET_TDI
ENET_TMS
XMIT_LED
TP_ENET_TDO

R8702
49.9

1%
1/16W
MF
402

10K

5%

ENET_5221_FDX 87
1/16W
MF
TP_ENET_TCK 6
402
ANEN
ENET_5221_TESTEN 87
MII_EN
ENET_5221_LOW_PWR 87

s
p
to
ENERGY_DET
RDAC

p
la

.
w
w
w

ENET_CLK25M_XIN

CRITICAL

13

ADD DUAL LAYOUT SUPPORT

12

1%
1/16W
MF
603

CLOSE TO PHY)

ENETFW_RESET

11

PHY ADDRESS 00000

NOSTUFF
2

10

R8703

PP3V3_PWRON_ENET

NC

C8706
0.01UF
20%
16V
CERM
402

J8700
RJ45
MJ-R0018
F-ST-TH

PRIMARY

10

SYM_VER-3

ENET_TDP

SECONDARY
1CT:1CT

J1

J2
J3

J4

ENET_TDN
ENET_RDP
ENET_RDN

TX-SIDE

J5
J6

1CT:1CT

J7

J8

RJ45
CABLE SIDE
11
12

C8707

0.01UF
20%
16V
CERM
402

C8714

RX-SIDE
RJ45
CHIP SIDE

GND_CHASSIS_RJ45

0.01UF
20%
16V
CERM
402

75
OHM

C8721
0.1UF
20%
10V
CERM
402

SHIELD

75
OHM

75
OHM

75
OHM

1000PF, 2000V

87

PP3V3_PWRON_ENET

87

PP3V3_PWRON_ENET

PP3V3_PWRON_ENET

87

DEVELOPMENT

DEVELOPMENT
DEVELOPMENT

1
1

ENET_RDAC_PD

84

43

1/16W

5%
1/16W
MF
402
84

44

BIASGND

19

CRITICAL

R8704
10K
5%
1/16W
MF
402

R8718
4.7K
5%
1/16W
MF
603

R8717
330
5%
1/16W
MF
603

DS3P1
1

R8704 PULLDOWN ENABLES

AUTO-MDI/MDIX

R8716
330
5%
1/16W
MF
603

DS1P1

DEVELOPMENT

DEVELOPMENT

LED8702

LED8701

GREEN
2.0X1.25

GREEN
2.0X1.25

10/100

XMIT

R8715
330
5%
1/16W
MF
603

R8714
4.7K
5%
1/16W
MF
603

DS2P1
1

DEVELOPMENT

LED8700
GREEN
2.0X1.25
2

LINK

24

PLLGND

47

ENET_PHY_RXD<0>
ENET_PHY_RXD<1>
ENET_PHY_RXD<2>
ENET_PHY_RXD<3>

RXC
RXD0
RXD1
RXD2
RXD3
RXDV
RXER
CRS
COL
RESET*
MDC
MDIO
XTALI
XTALO
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4

AGND2

48

32

NET_SPACING_TYPE=10 MIL

FDX
F100/JTAG_TCK
ANEN/JTAG_TRST
TESTEN
MII_EN
LOW_PWR

AGND1

33

ENET_RX_DV

21

10K

50

CLKENET_PHY_RX

29

84

2
402
5%

m
e
h
c

25

49.9

DGND2

84

TXEN
TXER

63

84

52

DGND1

1
MF
1/16W

5%

84

56

CRITICAL

30
26

R8712

33

33

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
R8709

ENET_TX_EN
ENET_TX_ER

TRANSC_BCM5221

49.9
1%
1/16W
MF
402

31

R8707

RP8700
84

60

54

MAKE_BASE=TRUE

59

FLAS-1

OGND3/
JTAG_EN

I238

58

OGND2

ENET_CLK125M_RX

57

64

84

ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>

TD+
TDRD+
RDSD+
SD-

R8700

(514-0083)

0.1UF
20%
10V
CERM
402

87

NET_SPACING_TYPE=10 MIL
5%
1/16W
MF
402

U8700

TXC
TXD0
TXD1
TXD2
TXD3

OF TRANSFORMER AND CONNECTOR

NET_SPACING_TYPE=10 MIL

53

49.9
1%
1/16W
MF
402

VIA COUNT, AND SHORT IF POSSIBLE

CLEAR OUT ALL PLANES BETWEEN MIDDLE

C8722

CLKENET_PHY_TX

45

MAKE_BASE=TRUE

R8701 1

0.01UF
20%
16V
CERM
402

87

33

CLK_ENET_LINK_TX

OGND1

I237

40

ENET_CLK25M_TX

C8710

R8706
84

AVDD1

DVDD2

DVDD1

REGAVDD

REGDVDD

NOTE: PLACE R3128, R3100, RP 3101 CLOSE TO PHY

(PLACE R3126, R3127

R3117, R3118
CLOSE TO PHY)

PARALLEL, MATCHED LENGTHS, WITH MINIMUM

c
.
s
it c
1

ALL DIFFERENTIAL SIGNALS SHOULD BE CLOSE,

87

MIN_LINE_WIDTH=50MIL
MIN_NECK_WIDTH=10MIL

ROUTE RD OVER GROUND PLANE (TOP LAYER) ONLY

VOLTAGE=2.5V

ROUTE TD OVER 2.5V PLANE (BOTTOM LAYER) ONLY

87

ENET_CLK25M_XIN
ENET_CLK25M_XOUT

15 MIL SPACING
15 MIL SPACING

87

ENET_XTAL

87

1.27K
1%
1/16W
MF
402

87

ENET_TMS

87

XMIT_LED

87

ENET_TDI

RP8702

R8705 1

10K
5%
87

87
87
87

ENET_5221_FDX
ENET_5221_TESTEN
ENET_5221_LOW_PWR
OGND3_JTAG_EN

8
1/16W
SM1

NOTE: LINK SUPPORT FOR GIGABIT ETHERNET PULLED DOWN OR ALIASED TO TEST POINTS HERE.
I228
I232
ENET_RXD_PD
TP_ENET_TXD<4>
84 ENET_CLK125M_GBE_REF
84 ENET_TXD<4>
6
MAKE_BASE=TRUE
MAKE_BASE=TRUE
I229
I233
ENET_RXD<5>
TP_ENET_TXD<5>
84 ENET_TXD<5>
6
MAKE_BASE=TRUE
I230
I234
ENET_RXD<6>
TP_ENET_TXD<6>
84 ENET_TXD<6>
6
R87981
MAKE_BASE=TRUE
10K
I231
I235
ENET_RXD<7>
TP_ENET_TXD<7>
1%
84 ENET_TXD<7>
6
1/16W
MAKE_BASE=TRUE
MF
I236
TP_ENET_CLK125M_GTX
402
84 ENET_CLK125M_GTX
2
MAKE_BASE=TRUE
R87991
ENET_RXD<4>

10K
1%
1/16W
MF
402

A
6

KEEP ALL CAPS CLOSE TO TRANSCEIVER ON THIS PAGE

DRAWING

8
ELECTRICAL_CONSTRAINT_SET
FW
FW
FW_LPS
FW_LREQ
FW_PINT
FW_LCLK
FW_PCLK

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR
FW_DATA<7..0>
FW_CTL<1..0>
FW_LPS
FW_LREQ
FW_PINT
FW_CLK98M_LCLK
FW_CLK98M_PCLK
FW_CLK98M_LCLK_R

15 MIL SPACING
15 MIL SPACING
15 MIL SPACING

88 90
88 90
88 90
88 90
88 90

m
o

88 90
88 90
88

Page Notes

Power aliases required by this page:

- _PP2V5_PWRON_SB
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

_PP2V5_PWRON_SB

C8800
0.1uF

20%
2 10V
CERM
402

C8801
0.1uF

20%
2 10V
CERM
402

C8802
0.1uF

20%
2 10V
CERM
402

N5
J7

m
e
h
c

A4

74 25 23 7

FWVDDP

U2300

OMIT

SHASTA
V1.0

c
.
s
it c

BGA
(7 OF 8)

FIREWIRE

PHY_DATA_0_H N4
PHY_DATA_1_H P5

FW_CLK98M_PCLK

P2 PHY_SCLK_H

90 88

FW_PINT

P3 PHY_PINT_L

p
la

.
w
w
w

PHY_DATA_2_H N1
PHY_DATA_3_H M7
PHY_DATA_4_H N6

s
p
to

90 88

FW_DATA<0>
FW_DATA<1>
FW_DATA<2>
FW_DATA<3>
FW_DATA<4>
FW_DATA<5>
FW_DATA<6>
FW_DATA<7>

PHY_DATA_5_H L1
PHY_DATA_6_H M3
PHY_DATA_7_H L2
PHY_CTL_0_H N2
PHY_CTL_1_H N3

FW_CTL<0>
FW_CTL<1>

PHY_LPS_H P6
PHY_LREQ_H P1
PHY_LCLK_H R1

PHY_LINKON_L N7

FW_LPS
FW_LREQ

88

88 90
88 90
88 90
88 90
88 90
88 90
88 90
88 90

88 90
88 90

88 90

88 90

FW_CLK98M_LCLK_R
FW_LINKON

90

R8800
1

22

FW_CLK98M_LCLK

88 90

5%
1/16W
MF
402

DRAWING

TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Fri Nov 21 11:24:36 2003

1
VERTICAL

VOLTAGE=24V
MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=10MIL

7 90

L9001

D9000

FERR-160-OHM

SM

D9001
3

D
90

D9002

FW_TPA1N

FW_TPB1P

I DONT THINK THESE LEAKY PHYS EXIST ANY LONGER

D9002
BAV99DW
SOT-363

D9003

FW_TPB1N

BAV99DW
SOT-363

1
5

90

FW_TPA2P

D9003

BAV99DW
SOT-363

90

D9004

FW_TPA2N

BAV99DW
SOT-363

1
5

FW_TPB2P

D9004

SOT-363

390K
5%
1/16W
MF
402

90

FW_TPB2N

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP3V3_FW

m
e
h
c

NO STUFF

U9000

R9022 1

4.7K
5%
1/16W
MF
402

10K
5%
1/16W
MF
402

22

FW_LREQ

88

88
88
88
88
88
88

FW_LPS

88

2K
5%
1/16W
MF
402
88

59

22
22
22

FW_DATA<0>
FW_DATA<1>
FW_DATA<2>
FW_DATA<3>
FW_DATA<4>
FW_DATA<5>
FW_DATA<6>
FW_DATA<7>

R9001
RP9000
RP9000

22

29

22

22
22

22

22
22

22

FW_CLK98M_LCLK

3
4

p
la

.
w
w
w

TP_FW_CLK98M_LCLK
MAKE_BASE=TRUE

FW_PINT

63

FW_DATA_R<0>
FW_DATA_R<1>
FW_DATA_R<2>
FW_DATA_R<3>
FW_DATA_R<4>
FW_DATA_R<5>
FW_DATA_R<6>
FW_DATA_R<7>

C9034

R9025 1
510K
5%
1/16W
MF
402

0.1UF
20%
10V
CERM
402

NC

1K
5%
1/16W
MF
402

PP3V3_FW

AVDD BYPASS

C9033
0.1UF
20%
10V
CERM
402

C9032
0.1UF
20%
10V
CERM
402

C9031

0.001UF
20%
50V
CERM
402

10K
5%
1/16W
MF
402

C9030
0.001UF
20%
50V
CERM
402

C9029
0.001UF
20%
50V
CERM
402

6
8
9

10
11
12
13

15

C9007
10UF
20%
6.3V
CERM
1206

C9008
10UF
20%
6.3V
CERM
1206

MIN_NECK_WIDTH=8MIL

17
26

27
62

CPS
TPBIAS0
XI
TPBIAS1
XO
TPBIAS2
PD
TPA0+
SE
TPA0SM
TPB0+
RESET
TPB0ISO
TPA1+
LPS
TPA1LREQ
TPB1+
PLLVDD
TPB1SYSCLK
TPA2+
CTL0
TPA2CTL1
TPB2+
TPB2-

37

D0
D1
D2
D3
D4
D5
D6
D7

54

R0
R1
PC2
PC1
PC0

PLLVSS
C/LKON

MIN_NECK_WIDTH=8MIL

42
48

NC

36

90

35

90

34

90

33

90

41

90

40

90

39

90

38

90

47

NC

46

NC

45

NC

44

NC

FW_R0
FW_R1

55

DGND0
DGND1
DGND2
DGND3
DGND4

14
25
56
64

AGND0
AGND1
AGND2
AGND3

FW_VGND

c
.
s
it c

R9015
56.2
1%
1/16W
MF
402

SYM_VER-1

R9014
56.2
1%
1/16W
MF
402

21
20

58

18

FW_LINKON 88

56.2
1%
1/16W
MF
402

49
52

FW_TPI1N

FW_VP_PORT1

0.47UF
20%
10V
CERM
603

R9010
56.2
1%
1/16W
MF
402

56.2
1%
1/16W
MF
402

TPI
TPI#
VP

VGND

SM
VOLTAGE=24V

10

MIN_LINE_WIDTH=35MIL

MIN_NECK_WIDTH=10MIL

C9018 1

0.01UF
10%
16V
CERM
402

C9024
0.01UF
10%
50V
CERM
805

C9010

FL9002

100PF

165-OHM
SM

GND_CHASSIS_FIREWIRE

PORT 2

GND_CHASSIS_FIREWIRE

514-0097

SYM_VER-1

5%
50V
CERM
402

CRITICAL

J9001
1394
F-ST-TH
90 6

FW_TPO2P

90 6

FW_TPO2N

90 6

FW_TPI2P

90 6

FW_TPI2N

6 FW_VP_PORT2

TPO

FL9003
165-OHM
SM

TPO#

SYM_VER-1

F9000
2

MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=8MIL

TPI

C9000

0.01UF
10%
50V
CERM
805

C9005

TPI#
VP

VGND
7

8 WATTS MAX
24 VOLTS

R9009

TPO
TPO#

SM

10

GND_CHASSIS_FIREWIRE

0.01UF
10%
16V
CERM
402

GND_CHASSIS_FIREWIRE

C9011
100PF
1

2
5%
50V
CERM
402

R9016
56.2
1%
1/16W
MF
402

FW_TPB2

32

53

R9018

90 6

C9016

R9019
2.49K
1%
1/16W
MF
402

FW_TPI1P

0.5AMP

ELECTRICAL_CONSTRAINT_SET
1

22

90 6

F9002

1.5AMP-33V

FW_TPO1N

1
4

90 6

165-OHM
SM

C9015
0.47UF
20%
10V
CERM
603

FL9001

FW_TPA1P
FW_TPA1N
FW_TPB1P
FW_TPB1N
FW_TPA2P
FW_TPA2N
FW_TPB2P
FW_TPB2N

CNA

R9013
56.2
1%
1/16W
MF
402

R9011
56.2
1%
1/16W
MF
402

FW_TPB1

NET_SPACING_TYPE

DIFFERENTIAL_PAIR

FW_TPA1
FW_TPA1
FW_TPB1
FW_TPB1
FW_TPA1
FW_TPA1
FW_TPB1
FW_TPB1

FW
FW
FW
FW
FW
FW
FW
FW

FW_TPA1
FW_TPA1
FW_TPB1
FW_TPB1
FW_TPO1
FW_TPO1
FW_TPI1
FW_TPI1

FW_TPA1P
FW_TPA1N
FW_TPB1P
FW_TPB1N
FW_TPO1P
FW_TPO1N
FW_TPI1P
FW_TPI1N

FW_TPA2
FW_TPA2
FW_TPB2
FW_TPB2
FW_TPA2
FW_TPA2
FW_TPB2
FW_TPB2

FW
FW
FW
FW
FW
FW
FW
FW

FW_TPA2
FW_TPA2
FW_TPB2
FW_TPB2
FW_TPO2
FW_TPO2
FW_TPI2
FW_TPI2

FW_TPA2P
FW_TPA2N
FW_TPB2P
FW_TPB2N
FW_TPO2P
FW_TPO2N
FW_TPI2P
FW_TPI2N

90

90
90
90
6 90
6 90
6 90
6 90

R9020
1

4.7K
5%
1/16W
MF
402

C9021
220PF
5%
25V
CERM
402

R9017
4.99K
1%
1/16W
MF
402

C9019

220PF
5%
25V
CERM
402
2

R9012
4.99K
1%
1/16W
MF
402

PW_LOWPWR SHOULD BE
PULLED DOWN ON SB

FW_XTAL

DESCRIPTION

15 MIL SPACING
15 MIL SPACING

90
90
90
90
6 90
6 90
6 90
6 90

X_TAL_IN
X_TAL_OUT

REFERENCE DESIGNATOR(S)

CRITICAL

U9000

CRITICAL

BOM OPTION
TABLE_5_ITEM

FIREWIRE PHY 802A

7 90

DVDD0
DVDD1
DVDD2
DVDD3
DVDD4

FW_TPO1P

TABLE_5_HEAD

QTY

338S0088

0.1UF
20%
10V
CERM
402

R9023 1

PART#

C9035

NOSTUFF

R9024 1

LREQ PULL-DOWN
ENSURES SIGNAL
LOW WHEN LUCENT
PHY POWERS UP

5%
1/16W
MF
2 402

23

FW_CLK98M_PCLK_R
FW_CTL_R<0>
FW_CTL_R<1>

RP9000
RP9001
RP9001
RP9001
RP9001
RP9002
RP9002
RP9002

10K

10UF
20%
6.3V
CERM
1206

19
28

FW_LREQ_R

OMIT

s
p
to
60

61

RP9000

R9026

C9006

24

16

CPS

FW_CLK25M_XOUT
25 FW_LOWPWR

FW_LPS

88 90

R9000

24.576M
SM

FW_PHY_ISO_L

NOT USED WITH 1394-A PHY

1

51

57

NOTE: 49M, NOT 98M CLK FOR 1394-A

NAMING KEPT FROM NEOBORG
88 FW_CLK98M_PCLK
88 FW_CTL<0>
88 FW_CTL<1>

88

50

FW_PHY_RST_L

90 88

88

CRITICAL

Y9000

5%
50V
CERM
603

R9099
1

43

27PF

NO STUFF

ENETFW_RESET_L

C9028
1

87

FW_CLK25M_XIN

5%
50V
CERM
603

1000pF
5%
25V
CERM
603

AVDD0
AVDD1
AVDD2
AVDD3
AVDD4

31
2

C9004

FLAS

30

27PF
1

VOLTAGE=1.8V
MIN_LINE_WIDTH=10MIL

VOLTAGE=1.8V
MIN_LINE_WIDTH=10MIL

FW803

C9027

7 90

PP1V8_FW_BIAS1
PP1V8_FW_BIAS2

R9098

R9021

BAV99DW

90 6

90 7

90

5%
1/8W
FF
1206

Q26 HAS A BOMOPTION FOR A PHY LEAKS 47 OHM PULL DOWN RESISTOR

90

m
o

R9007

BAV99DW
SOT-363

90

C9009
0.1UF
20%
50V
CERM
805

F-ST-TH

SYM_VER-1

SOT-363

1394

165-OHM
SM

1206

BAV99DW

J9000

FL9000

MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=24V

90 7

FW_CPS

SOT-363

90 7

BAV99DW

MIN_LINE_WIDTH=30MIL
MIN_NECK_WIDTH=25MIL

MURS320T3

D9001

FW_TPA1P

PORT 1
514-0097
CRITICAL

PP24V_FW

90 7

90

CONNECTORS

FW_VP

FIREWIRE IS ON WHEN UNIT IS OFF

PP3V3_FW

DVDD BYPASS

C9026
0.1UF
20%
10V
CERM
402

C9025
0.1UF
20%
10V
CERM
402

C9023
0.1UF
20%
10V
CERM
402

C9022
0.001UF
20%
50V
CERM
402

C9002
0.001UF
20%
50V
CERM
402

C9001
0.001UF
20%
50V
CERM
402

DRAWING

ELECTRICAL_CONSTRAINT_SET

NET_SPACING_TYPE

DIFFERENTIAL_PAIR

USB2_0
USB2_0

USB2
USB2

USB2_0
USB2_0

USB2_P<0>
USB2_N<0>

USB2_1
USB2_1

USB2
USB2

USB2_1
USB2_1

USB2_P<1>
USB2_N<1>

USB2_2
USB2_2

USB2
USB2

USB2_2
USB2_2

USB2_P<2>
USB2_N<2>

USB2_3
USB2_3

USB2
USB2

USB2_3
USB2_3

USB2_P<3>
USB2_N<3>

USB2_4
USB2_4

USB2
USB2

USB2_4
USB2_4

USB2_P<4>
USB2_N<4>

USB2_NEC_XTAL

15 MIL SPACING
15 MIL SPACING
15 MIL SPACING

91 92

91 92
91 92

m
o

91 92
91 92

91 94
91 94

91 92
91 92

L9135

91
91
91 7

_PP3V3_PWRON_USB

91

PP3V3_PWRON_NEC_AVDD
VOLTAGE=3.3V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil

FERR-EMI-100-OHM
1

2
SM

C9127 1

C9128 1

0.1uF

0.1uF

0.1uF

20%
10V
CERM 2
402

0.1uF

20%
10V
CERM 2
402

V1.0

10K

94
92

6
6
6

92

92

92

6
6

92

6
6

p
la
91 7

6
6
6
6
6
6
6
6

R91401
1.5K

USB_NEC_N<1>

K12

(USB2_N<1>)
(USB2_P<1>)
USB_NEC_P<1>

J14
J12

N12

D7

G12

D13

N10

RSDM3 H11
DM3 G11
DP3 G13
RSDP3 G14

C9145
27pF

5%
50V
CERM 2
402

36

USB2_N<2>
USB2_P<2>

91 92
91 92

R9105
36

R9106
36

RSDM4
DM4
DP4
RSDP4

F12

USB_NEC_N<3>

F14

(USB2_N<3>)
(USB2_P<3>)
USB_NEC_P<3>

E12
E14

1%
1/16W
MF
402

USB2_N<3>
USB2_P<3>

91 94
91 94

R9107
36

1%
1/16W
MF
402

P6 NC1
M6 NC2

R9108
36

DP5 C13
RSDP5 C14

L9 XT1/SCLK
P8 XT2

USB_NEC_N<4>
(USB2_N<4>)
(USB2_P<4>)
USB_NEC_P<4>

1%
1/16W
MF
402

USB2_N<4>
USB2_P<4>

91 92
91 92

R9109
36

1%
1/16W
MF
402

RREF P11

NEC_CLK30M_XT2

91

91 92

1%
1/16W
MF
402

5%
1/16W
MF
1 402

8X4.5MM-SM
1

91 92

1%
1/16W
MF
402

USB_NEC_N<2>
(USB2_N<2>)
(USB2_P<2>)
USB_NEC_P<2>

100

36

RSDM5 E13
DM5 D14

30.0000M

USB2_N<1>
USB2_P<1>

R9104

R9145

Y9145

1%
1/16W
MF
402

91

R9103

5%
1/16W
MF
2 402

NEC_CLK30M_XT1
NEC_CLK30M_XT2_R

1%
1/16W
MF
402

CRITICAL

36

1
K14

1.5K

91

91 92

R9102

R9141

NEC_NC1_PU
NEC_NC2_PU

91 92

1%
1/16W
MF
402

5%
1/16W
MF
402 2

36

C9146

VSS

AVSS

27pF

5%
2 50V
CERM
402

D8

.
w
w
w

USB2_N<0>
USB2_P<0>

R9101
1

A9 PPON5

F11

_PP3V3_PWRON_USB

1%
1/16W
MF
402

USB_NEC_N<0>

(USB2_N<0>)
(USB2_P<0>)
USB_NEC_P<0>

C10 PPON4

G4

C11 PPON3

J11

A11 PPON2

D12

C12 PPON1

H12

B9 OCI5

L12

A10 OCI4

M11

B10 OCI3

USB2_PWREN<0>
USB2_PWREN<1>
USB2_PWREN<2>
USB2_PWREN<3>
USB2_PWREN<4>

RSDM1 M14
DM1 M13

RSDM2
DM2
DP2
RSDP2

s
p
to
92

B11 OCI2

B13

B12 OCI1

(USB2_OC<0>)
(USB2_OC<1>)
(USB2_OC<2>)
(USB2_OC<3>)
(USB2_OC<4>)

N2

NC27 W3
NC28 Y1
NC29 Y3

USB2_OC<0>
USB2_OC<1>
USB2_OC<2>
USB2_OC<3>
USB2_OC<4>

N13

NC24 V3
NC25 V4
NC26 W1

92

B2

NC21 U6
NC22 V1
NC23 V2

92

A2

NC19 U4
NC20 U5

92

B14

NC16 U1
NC17 U2
NC18 U3

H14

NC13 T6
NC14 T7
NC15 T8

2 3

N14

NC10 T3
NC11 T4
NC12 T5

5%
1/16W
SM1

N1

NC8 T1
NC9 T2

N8

m
e
h
c

B1

NC5 R6
NC6 R7
NC7 R8

J13

CRITICAL

U7700

RP9110

5%
1/16W
MF
402 1

BGA
(8 OF 8)

7 6

10K

SHASTA

NC2 R3
NC3 R4
NC4 R5

L13

AVDD

20%
10V
CERM 2
402

_PP3V3_PWRON_USB

R91102

TP_SB_NC_P7
TP_SB_NC_P8
TP_SB_NC_R3
TP_SB_NC_R4
TP_SB_NC_R5
TP_SB_NC_R6
TP_SB_NC_R7
TP_SB_NC_R8
TP_SB_NC_T1
TP_SB_NC_T2
TP_SB_NC_T3
TP_SB_NC_T4
TP_SB_NC_T5
TP_SB_NC_T6
TP_SB_NC_T7
TP_SB_NC_T8
TP_SB_NC_U1
TP_SB_NC_U2
TP_SB_NC_U3
TP_SB_NC_U4
TP_SB_NC_U5
TP_SB_NC_U6
TP_SB_NC_V1
TP_SB_NC_V2
TP_SB_NC_V3
TP_SB_NC_V4
TP_SB_NC_W1
TP_SB_NC_W3
TP_SB_NC_Y1
TP_SB_NC_Y3

E2

0.1uF

FBGA

U2300

NC0 P7
NC1 P8

36

DP1 L14
RSDP1 K13

NEC_uPD720101_USB2

91 7

c
.
s
it c

R9100

VDD

20%
10V
CERM 2
402

C9129 1 C9130

20%
10V
CERM 2
402

20%
10V
CERM 2
402

0.1uF

20%
10V
CERM 2
402

20%
10V
CERM 2
402

R9139
2

5%
1/16W
MF
603

AVSS(R)

0.1uF

0.1uF

20%
10V
CERM 2
402

N11

C9126

C9124 1 C9125

A3

20%
10V
CERM 2
402

0.1uF

A12

C9123 1

20%
10V
CERM 2
402

0.1uF

P3

C9122 1

20%
10V
CERM 2
402

A13

0.1uF

M12

mils
mils
mils
mils
mils

C9121

NOTE: Target differential impedance for

USB2 data pairs is 90 ohms.

OMIT

0.1uF

20%
6.3V
CERM
805

C9137

P13

20%
6.3V 2
CERM
805

P2

10uF

P12

C9120

P10

10uF

5%
1/16W
MF
603

Signal aliases required by this page:

(NONE)

Line To Line:
19.5
Length Tolerance:
50
Primary Max Sep:
7.5
Secondary Max Sep: 100
Secondary Length: 500

4.7

F13

C9136

H4

R9135

C9135

H13

Page Notes
Power aliases required by this page:
- _PP3V3_PWRON_USB

Net Spacing Type: USB2

91 92

NEC_CLK30M_XT1
NEC_CLK30M_XT2
NEC_CLK30M_XT2_R

BOM options provided by this page:

(NONE)

NEC_RREF_PD

R91381
9.09K

1%
1/16W
MF
402 2
Tie to GND at ball N11

GND_NEC_AVSS_R
VOLTAGE=0V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil

Y9145 LOAD CAPACITANCE IS 16pF

DRAWING

TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Fri Nov 21 11:24:39 2003

ELECTRICAL_CONSTRAINT_SET

NET_SPACING_TYPE

PROVIDED
BY
USB
CONTROLLER

USB2
USB2

USB2_PORT1_F
USB2_PORT1_F

USB2_PORT1_P_F
USB2_PORT1_N_F

USB2
USB2

USB2_PORT2_F
USB2_PORT2_F

USB2_PORT2_P_F
USB2_PORT2_N_F

USB2
USB2

USB2_PORT3_F
USB2_PORT3_F

USB2_PORT3_P_F
USB2_PORT3_N_F

I526
I527

DIFFERENTIAL_PAIR
6 92
6 92

6 92
6 92

m
o

6 92
6 92

External USB Ports

D

Page Notes

L9210

FERR-250-OHM

Power aliases required by this page:

- _PP5V_PWRON_USB
- _PP5V_PWRON_UDASH
- _PP3V3_PWRON_UDASH
- _PP3V3_PWRON_BT

59

PP5V_USB2

VOLTAGE=5V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=20MIL

91

USB2_PWREN<2>

ALIAS

91

USB2_PWREN<3>

ALIAS

91

USB2_PWREN<4>

ALIAS

C9213 1

0.01uF

0.01uF

20%
16V
CERM 2
402

L9212
165-OHM

CRITICAL

J9210

20%
16V
CERM 2
402

USB
F-ST-TH
5
6

SYM_VER-1

91

USB2_N<0>

ALIAS

USB2_PORT1_N
MAKE_BASE=TRUE

91

USB2_P<0>

ALIAS

USB2_PORT1_P
MAKE_BASE=TRUE
1

92 6

USB2_PORT1_N_F
USB2_PORT1_P_F

R9210

R9211

15K

NO STUFF

5%
1/16W
MF
2 402

SM

NOSTUFF
1

20%
2 6.3V
POLY
SMD

s
p
to
FERR-250-OHM

C9220
150uF

L9221

SM

GND_USB2_PORT2
VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=25MIL

L9222
165-OHM
SM

SYM_VER-1

91

USB2_N<1>

ALIAS

USB2_PORT2_N
MAKE_BASE=TRUE

92 6

91

USB2_P<1>

ALIAS

USB2_PORT2_P
MAKE_BASE=TRUE

R92201

p
la

F9200

.
w
w
w

2AMP-6V
1

_PP5V_PWRON_USB

SM-1

R9200
160

5%
1/16W
MF
2 603

ALIAS

91

USB2_OC<2>

ALIAS

ALIAS

3
4

5%
50V
2 CERM
402

514-0080

MIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

L9220

FERR-250-OHM

USB2_OC<1>

C9215

33pF

5%
50V
CERM 2
402

USB2_OC<0>

33pF

91

c
.
s
it c

GND_CHASSIS_USB

91

VDD
DD+
GND
NO STUFF

m
e
h
c
C9214 1

15K

5%
1/16W
MF
402 2

4
92 6

PORT 1

C9212 1

SM

TP_USB2_PWREN<0>
MAKE_BASE=TRUE
TP_USB2_PWREN<1>
MAKE_BASE=TRUE
TP_USB2_PWREN<2>
MAKE_BASE=TRUE
TP_USB2_PWREN<3>
MAKE_BASE=TRUE
TP_USB2_PWREN<4>
MAKE_BASE=TRUE

10%
2 16V
X5R
1210

USB_OC
MAKE_BASE=TRUE

R9201

91

USB2_N<2>

10uF

10%
16V
2 X5R
1210

C9222 1

C9223 1

0.01uF

0.01uF

20%
16V
CERM 2
402

CRITICAL

J9220

20%
16V
CERM 2
402

USB

F-ST-TH
5
6

USB2_PORT2_N_F
USB2_PORT2_P_F

R9221

NO STUFF

C9224 1

15K

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

33pF

VDD
DD+
GND
NO STUFF

C9225

2
3
4

33pF

5%
50V
CERM 2
402

91

SM

NOSTUFF

C9230
150uF

L9231

FERR-250-OHM
1

20%
2 6.3V
POLY
SMD

20%
6.3V
CERM 2
805

7 92

91

ALIAS

C9240

L9230

USB2_N<4>
USB2_P<4>

PP5V_USB2_PORT3_F
VOLTAGE=5V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=20MIL

ALIAS
ALIAS

6
6

R9240

10uF

10%
16V
2 X5R
1210

C9241
0.1uF

J9240
1

20%
10V
CERM 2
402

53353
M-ST-SM

USB_BT_N
MAKE_BASE=TRUE
USB_BT_P
MAKE_BASE=TRUE
1

C9231

CRITICAL

USB2_OC<4>

10uF

7
9

NC
NC
NC
8 NC
10 NC
6

R9241

15K

15K

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

516S0097

SDF9201
STDOFF-197OD-283H-TH
1

SM

GND_USB2_PORT3
VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=25MIL

C9232

0.01uF

C9233

CRITICAL

0.01uF

20%
16V
CERM 2
402

J9230

20%
16V
CERM 2
402

USB
F-ST-TH
5
6

SM
SYM_VER-1

USB2_PORT3_P
MAKE_BASE=TRUE

92 6
92 6

ALIAS

_PP3V3_PWRON_BT

514-0080
GND_CHASSIS_USB

SDF9200

STDOFF-197OD-283H-TH

91

5%
50V
2 CERM
402

L9232
165-OHM
ALIAS

Q37 BlueTooth Connector

FERR-250-OHM

5%
1/16W
MF
2 603

USB2_P<2>

C9221

15K

300

91

92 6

7 92

PP5V_USB2_PORT2_F
VOLTAGE=5V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=20MIL

PORT 2

ALIAS

10uF

USB2_PORT3_N
MAKE_BASE=TRUE
1

R9230

R9231

15K

15K

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

USB2_PORT3_P_F
USB2_PORT3_N_F

NO STUFF

C9234
33pF

5%
50V
CERM 2
402

VDD
DD+
GND
NO STUFF

C9235

33pF

5%
50V
2 CERM
402

2
3
4

PORT 3

USB2_PWREN<1>

PP5V_USB2_PORT1_F
VOLTAGE=5V
MIN_LINE_WIDTH=20MIL

C9211MIN_NECK_WIDTH=20MIL

SM

neoBorg Implementation

91

20%
2 6.3V
POLY
SMD

GND_USB2_PORT1
VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=25MIL

NOTE: This design does not provide power

control on USB ports 2-4. Rename
USB controller outputs to indicate
single-pin connections.
ALIAS

C9210
150uF

L9211

NOTE: USB pairs are NOT constrained on

this page. It is assumed that the
USB Host Controller page will
provide the appropriate constraints
to apply to entire USB D+/D- XNets.

USB2_PWREN<0>

NOSTUFF
1

FERR-250-OHM

BOM options provided by this page:

(NONE)

91

SM

Signal aliases required by this page:

(NONE)
NOTE: This page is expected to contain the
necessary aliases to map the
USB pairs to their appropriate
destinations and/or to properly
terminate unused signals.

514-0080
GND_CHASSIS_USB

7 92

DRAWING

TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Fri Nov 21 11:23:57 2003

Page Notes
Power aliases required by this page:
- _PP3V3_PWRON_MODEM
Spec Load: 0.5 A active, 3 mA auxiliary

NEED TO PICK A MODEM TO STUFF FOR EVT

AND THE CORRESPONDING STANDOFF

Signal aliases required by this page:

(NONE)

m
o

BOM options provided by this page:

(NONE)

SOFT MODEM IS PLAN OF RECORD

MICRODASH MODEM CONNECTOR LEFT ON FOR DEVELOPMENT PURPOSES ONLY

c
.
s
it c

MicroDash Modem Connector

Q52 Modem Connector

NOSTUFF

SDF9400

SDF9402

STDOFF-4MM-9MMH-TH

STDOFF-5MM-5.5MMH-TH

CRITICAL

J9401

91

C104A-H9.0

USB2_OC<3>

ALIAS

_PP3V3_PWRON_UDASH

35 F-ST-SM

_PP3V3_PWRON_MODEM

NC
NC 31

DEVELOPMENT

32 NC

C9400 1
4.7uF

NC

NC
7
NC
9
NC
11
NC
NC 13

94 25 6

94 25 6

22

23

24

25

26

27

28

29

30

I2S1_SB_TO_DEV_DTO
I2S1_RESET_L
I2S1_MCLK

NC 33
NC 36

I2S1_SYNC
I2S1_DEV_TO_SB_DTI

I2S1_BITCLK

6 25 94
6 25 76 94

6 25 94

34 NC

516S0116

SDF9401
STDOFF-4MM-9MMH-TH
GND_CHASSIS_MODEM

NOSTUFF

EMI9400

1 EMI-SPRING
S8-10OG

p
la

.
w
w
w
From Intel Mobile Audio/Modem
Daughter Card Specification
Rev 1.0, February 22, 1999

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

MONO_OUT/PC_BEEP
GND
AUXA_RIGHT
AUXA_LEFT
CD_GND
CD_RIGHT
CD_LEFT
GND
3.3Vaux
GND
3.3Vmain
AC97_SDATA_OUT
AC97_RESET#
GND
AC97_MSTRCLK

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

20%
10V
CERM 2
402

NOSTUFF

R94002

R9401

10K

10K

5%
1/16W
MF
402 1

m
e
h
c

18 NC
20

19

0.1uF

5%
1/16W
MF
2 402

DEVELOPMENT

s
p
to

R9402

DEVELOPMENT

10K

5%
1/16W
MF
2 402

J9400
5047

F-ST-SM

1
(+3.3V)
3
(GND)
5
25 6 UDASH_SDOWN
(SDOWN)
Default to Modem On
7
(GND)
9
94 76 25 6 I2S1_DEV_TO_SB_DTI
(RXD)
11
94 25 6 I2S1_SYNC
(GPIO*)
13
(GND)
15
94 25 6 MODEM_RING2SYS_L
(RING*)
MODEM_RING2SYS_L SHOULD BE PULLED UP ON SB
(HOOK)
NC 17
19
(GND)
21
18 6 I2C_UDASH_SCL
(SCL)
23
(GND)
25
(A0)
(SNDIN) NC 27
(SNDOUT) NC 29

14 NC
16 NC

NC 21

C9401 1

6 25 94

17

94 76 25 6

MODEM_RING2SYS_L

10 NC
12 NC

15

20%
10V
CERM 2
1206

NC
NC

DEVELOPMENT DEVELOPMENT

(+3.3V)
(RST*)
(RTS*)
(DTR*)
(GND)
(TXD*)
(TRXC)
(GND)
(D-)
(D+)
(GND)
(SDA)
(A1)
(+5V)
(+5V)

4
6
8

10
12
14
16
18
20
22
24
26
28
30

UDASH_RESET_L
I2S1_MCLK
I2S1_RESET_L

6 25
6 25 94
6 25 94

I2S1_SB_TO_DEV_DTO
I2S1_BITCLK

6
6

6 25 76 94

6 25 94

USB_UDASH_N
MAKE_BASE=TRUE
USB_UDASH_P
MAKE_BASE=TRUE
I2C_UDASH_SDA
UDASH_I2C_A1_PU

ALIAS
ALIAS

6 18

DEVELOPMENT

R94041

_PP5V_PWRON_UDASH

USB2_N<3>
USB2_P<3>

91
91

DEVELOPMENT
1

R9403

15K

15K

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

516S0121
DEVELOPMENT DEVELOPMENT
1

C9402
0.1uF

20%
10V
2 CERM
402

C9403
10uF

20%
2 6.3V
CERM
1206

NOSTUFF

J9402

013-0001-333
RJ11-ST-TH

1
2

AUDIO_PWRON
MONO_PHONE
RESERVED
GND
5Vmain
RESERVED
RESERVED
PRIMARY_DN
5Vd
GND
AC97_SYNC
AC97_SDATA_INB
AC97_SDATA_INA
GND
AC97_BITCLK

AUDIO CODEC
APPLE P/N 353S0655
MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
VOLTAGE=3.3V

L9500

1000-OHM-200MA
99 98 97 7

PP3V3_AUDIO

PP4V5_AUDIO_ANALOG

PPV_3V3_AUDIO_CODEC

95 99

0603

C9500 1

AUDI2S0OUT
AUDSPDIFOUT
I2S0_SB_TO_DEV_DTO

18

I2C_AUDIO_SCL
I2C_AUDIO_SDA

25

I2S0_RESET_L

25

I2S0_MCLK

18

NET_SPACING_TYPE=AUDIO

NET_SPACING_TYPE=AUDIO

PDWN*

17

SCKI
ATEST

NC

47K
5%
1/16W
MF
2 402

33

99 96 95

26

AUD_PCM_VCOM

AUD_PCM_REF1
AUD_PCM_REF2

5
3

AUD_CODEC_LI_SHDN_L
AUD_PSEUDO_VREF

32
27

AUD_PCM_MBIAS
AUD_MICIN_N
AUD_MICIN_P

28
29

C9504

AGND

10UF

R9500

10UF
2

AUD_LI_L

AUD_LI_L1

AUD_LI_L2

s
p
to
1

1%
1/16W
MF
402

20%
16V
ELEC
SM

C9515

R9502

0.47UF

100K

20%
10V
CERM 2
603

1%
1/16W
MF
2 402

D9500

10

BAV99T

V+

SOT-523-3
1
3
2

GND_AUDIO_CODEC
1

R9514
100

5%
1/10W
FF
2 805
98

AUD_LI_GND

C9516

R9503

10UF

.
w
w
w
2

AUD_LI_GNDL1

1%
1/16W
MF
402

20%
16V
ELEC
SM

C9517

99 96 95

NOSTUFF

R95201
5%
1/16W
MF
402 2

NOSTUFF

R9521
AUD_CODEC_LI_SHDN_L

AUD_LI_GNDR1

R9519
47K

5%
1/16W
MF
2 402

1%
1/16W
MF
402

R9515
100K

1%
1/16W
MF
2 402

C9518
2

AUD_LI_R

20%
16V
ELEC
SM

99 95

C9506 1

C9508 1

20%
6.3V 2
CERM
805

10%
16V 2
X7R
603

AUD_CODEC_IN_L

0.1UF

C9510
0.1UF

10UF

95

95

95

95
95
95

C9513

10%
16V 2
X7R
603

MICROPHONE IMPEDANCE MATCHING CIRCUIT

AUD_PCM_MBIAS

98

R9522

R9512
1K

1%
1/16W
MF
2 402

R9509
1

AUD_MIC_IN_P

C9519

165

1%
1/16W
MF
402

10%
25V
X7R 2
402

98

AUD_PSEUDO_VREF

AUD_MIC_IN_N
NOSTUFF

95

R9523

165

1%
1/16W
MF
402

R95101
100K

AUD_LI_GNDR2

10K

1%
1/16W
MF
402 2

C9521
0.1UF
1

AUD_MIC_M1
DIFFERENTIAL_PAIR=AUDIO_MIC_1
NET_SPACING_TYPE=AUDIO

2
99 98

DIFFERENTIAL_PAIR=AUDIO_MIC_2
NET_SPACING_TYPE=AUDIO
AUD_MICIN_P 95

R9513

DIFFERENTIAL_PAIR=AUDIO_MIC_2
NET_SPACING_TYPE=AUDIO
AUD_MICIN_N 95

10%
16V
X7R
603

1K

1%
1/16W
MF
2 402

1%
1/16W
MF
402

2
10%
16V
X7R
603

1K

R9506

0.1UF

AUD_MIC_P1

R9511
1

C9520

DIFFERENTIAL_PAIR=AUDIO_MIC_1
NET_SPACING_TYPE=AUDIO

1000PF
DIFFERENTIAL_PAIR=AUDIO_MIC
NET_SPACING_TYPE=AUDIO

95

NOSTUFF

1%
1/16W
MF
402

97

0.1UF

DIFFERENTIAL_PAIR=AUDIO_MIC
NET_SPACING_TYPE=AUDIO

R9504
1

96 97

1%
1/16W
MF
2 402

APPLE P/N 353S0642

10K

96 97

1K

V4

95

20%
2 16V
ELEC
SM

C9512

10%
16V 2
X7R
603

95

10UF

20%
2 16V
ELEC
SM

C9511

1%
1/16W
MF
2 402

GND_AUDIO_MIC

NOSTUFF
4

D9501

BAV99T
SOT-523-3
1

AUD_LI_R1

20.5K2

V-

U9501
8
3

V+
10

MAX4253
UMAX

AUD_CODEC_IN_R

95

R9507

10UF

98

20.5K2
1

AUD_LI_GNDL2

10UF

AUDLISHDNL

5%
1/16W
MF
402

20%
16V
ELEC
SM

47K

95

R9505

10UF

GND_AUDIO_CODEC

20.5K2
1

C9509

MAX4253
UMAX

U9501

p
la

B
99 96 95

1%
1/16W
MF
402

NOSTUFF

10K

20%
2 16V
ELEC
SM

20%
2 16V
ELEC
SM

m
e
h
c

R9501

20.5K2

C9507
10UF

20%
2 16V
ELEC
SM

GND_AUDIO_CODEC

C9514
98

C9505

10UF

20%
6.3V
CERM 2
805

10UF

AV= 0.49

c
.
s
it c

AUD_CODEC_OUT_L
AUD_CODEC_OUT_R

PP4V5_AUDIO_ANALOG

95 96 99

25
24

LINE IN PSEUDO-DIFFERENTIAL AMP

99 95

GND_AUDIO_CODEC

AUD_CODEC_IN_L
AUD_CODEC_IN_R

5%
1/16W
MF
402

1UF

R9517
NET_SPACING_TYPE=AUDIO

m
o

C9503

10%
10V
2 CERM
805

MBIAS
MINM
MINP

DGND

5%
1/16W
MF
402

R9518

AUD_SPDIF_OUT

33

NET_SPACING_TYPE=AUDIO

15

I2S0_DEV_TO_SB_DTI
1

98

14
12

21
NC 20
19

R9516
25

18

13

25

PCM3052
VQFN
BCK
VINL
LRCK
VINR
DOUT
VOUTL
DOUTS
VOUTR
DIN
VCOM
I2CEN
VREF1
ADR
VREF2
SCL
VREFS
SDA
REFO

11
10

NET_SPACING_TYPE=AUDIO

1UF

VCC

22
30

25

I2S0_BITCLK
I2S0_SYNC

C9502

10%
10V
2 CERM
805

23
31

U9500

VDD

25

10%
10V
2 CERM
805

16

20%
6.3V
CERM 2
805

C9501
1UF

10UF

R9508
1

AUD_LI_R2

1%
1/16W
MF
402

10K

1%
1/16W
MF
402

PP4V5_AUDIO_ANALOG

CODEC OUTPUT LOW-PASS FILTER

FC = 37 KHZ, HO = -1.4

R9601
1

14K

m
o

1%
1/16W
MF
402

C9600

R9600

10UF

97 95

AUD_CODEC_OUT_L

AUDCODECOUTL

10K

270PF

3.92K2

1%
1/16W
MF
402

1%
1/16W
MF
402

20%
16V
ELEC
SM-1

C9601

R9602
AUDCODECOUTL1

AUD_LOAMP_OUT_L

96

5%
50V
CERM
603

AUD_LOAMP_IN_L_M

96

AUD_LOAMP_IN_L_P

96

C9602
1.5NF

5%
25V
2 CERM
0603
98

R9603

AUD_LO_GND_PRB

14K

1%
1/16W
MF
402

R9604
10K

1%
1/16W
MF
2 402

R9605

m
e
h
c
14K

C9604
1.5NF

C9603

R9607

10UF
AUD_CODEC_OUT_R

AUDCODECOUTR

10K

1%
1/16W
MF
402

20%
16V
ELEC
SM-1

96

AUD_LOAMP_IN_R_M

96

AUD_LOAMP_OUT_R

96

270PF

3.92K2

AUDCODECOUTR1

AUD_LOAMP_IN_R_P

C9605

R9608

1%
1/16W
MF
402

5%
25V
2 CERM
0603

97 95

1%
1/16W
MF
2 402

R9606

GND_AUDIO_CODEC

1%
1/16W
MF
402

c
.
s
it c

GROUND NOISE
CANCELLATION
HEADPHONES/LINE OUT

10K
99 96 95

5%
50V
CERM
603

R9609

s
p
to
1

14K

1%
1/16W
MF
402

HEADPHONES/LINE OUT AMP

APPLE P/N 353S0697

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=5V
PPV_5V_AUDIO_LOAMP

R9610

99

PP5V_AUDIO_ANALOG

4.7

5%
1/10W
MF
603

p
la

C9607

10UF

10UF

R96151
47K

99 96 95

99

100PF

5%
50V
CERM 2
402

AUDIO_LO_MUTE_L_F

C9613

16

13

VDDR

VDDL

C1P 2
C1N 4

SHDN*

100PF

GND_AUD_LOAMP_CHGPMP

AUD_LOAMP_OUT_L

NC 17

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

R9612
1

1UF

14

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUD_LO_R

98

C9609

AUD_LOAMP_OUT_R

96

10%
10V
2 CERM
805

NOSTUFF

AUD_MAX9722_C1N

R9617

1%
1/16W
MF
2 402

NOSTUFF

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

R9618
1K

1%
1/16W
MF
2 402

R9613
1

14

AUD_LO_GND 98

1%
1/16W
MF
603

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_MAX9722_PVSS
1

98

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

1UF

10%
10V
2 CERM
805

1K

C9610

96

1%
1/16W
MF
603

AUD_MAX9722_C1P

C9608

AUD_LO_L

1%
1/16W
MF
603

C9611
10UF

1UF

10%
10V
CERM 2
805

20%
1 16V
ELEC
SM

R9614
1

GND_AUD_LOAMP

14

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

96 99

R9611

5%
50V
CERM 2
402

GND_AUDIO_CODEC

99 96

5%
1/16W
MF
402

C9612 1

5%
1/16W
MF
402 2

1K

ROUT 10

VSS

AUDIO_LO_MUTE_L

RINRIN+

MAX9722
QFN

11

R9616

TO SHASTA GPIO

25

8
7

LOUT 12

PVSS

AUD_LOAMP_IN_R_M
AUD_LOAMP_IN_R_P

B
GND_AUD_LOAMP_CHGPMP

U9600

LINLIN+

SGND

96

14
15

96

AUD_LOAMP_IN_L_M
AUD_LOAMP_IN_L_P

PGND

96

.
w
w
w
96

99 96

PVDD

N20P80%
16V
CERM 2
1210

GND_AUD_LOAMP_CHGPMP

C9606

20%
2 16V
ELEC
SM

14

1%
1/16W
MF
603

F9700

MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

1.5A-24V

PP12V_AUDIO_SPKRAMP

MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

SM
2

PP12V_AUDIO_SPKRAMP_F

XW9700
OMIT
SM

DIFFERENTIAL_PAIR=AUD_SPKRAMP_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

FERR-250-OHM

PP12V_AUDIO_SPKRAMP_F2

APPLE P/N 353S0680

PP12V_AUD_SPKRAMP_PLANE

2
SM-1

L9705

AUDSAMPINLN

2
1

C9705

AUD_PCM_VCOM

L9707

0.47UF

AUDSAMPINRP

0603

97

10%
16V
X7R
805

C9716

97

100PF

L9708

1000-OHM-200MA
1

AUD_CODEC_OUT_R

97

5%
50V
2 CERM
402

97

97

AUDSAMPINRN

25

TIE TO SHASTA GPIO

R9713

AUDIO_SPKR_MUTE_L

47K

AUDIO_SPKR_MUTE_L_F

5%
1/16W
MF
402

R97121
47K

C9720 1

C9721 1

100PF

100PF

5%
1/16W
MF
402 2

5%
50V
CERM 2
402

11

2N7002DW

SOT-363

S
4

10%
2 16V
X7R
805

XW9701
OMIT

MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL

DIFFERENTIAL_PAIR=AUD_SPKRAMP_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL

p
la

SM

99 7

GND_AUDIO_SPKRAMP

XW9702
OMIT
SM
1

99 97

GND_AUDIO_SPKRAMP_PLANE

.
w
w
w
99 98 95 7

97
97

97

97

99 97

PGND

L9701

97 99

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

AUD_SPKR_OUTL_P

98

L9702

98

C9708
0.1UF

10%
50V
2 X7R
603

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

L9703

180-OHM-1.5A
2

AUD_SPKR_OUTR_P

98

0603

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

L9704

180-OHM-1.5A
1

AUD_SPKR_OUTR_N

98

0603

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUDSAMPCSS

AUD_SPKR_OUTL_N

0603

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOUTRN

CSS 12

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

180-OHM-1.5A

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOURTP

ROUT- 25
ROUT- 26

THM
AGND PAD

C9714

m
e
h
c

SHDN*

0.47UF

XC9700
50R28

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUDSAMPCPM

s
p
to
1

5%
50V
CERM 2
402

CP- 5

ROUT+ 27
ROUT+ 28

8 NC

10UF

10%
16V
2 CERM
1210

180-OHM-1.5A

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOUTLN

CP+ 6

QFN

14 VREG

AUD_MAX9714_VREG
MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL

Q9700

SOT-363

19 FS1
20 FS2

U9700

C9723

10%
16V
2 CERM
1210

0603

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUDSAMPCPP

MAX9714

Q9700

2N7002DW

AUD_SAMP_FS1
AUD_SAMP_FS2

NC

10%
16V
X7R
805

17 G1
18 G2

2 AUDIO_SPKR_MUTE_L_INV

1%
1/16W
MF
402

16 RIN-

AUD_SAMP_G1
AUD_SAMP_G2

0.47UF

2
0603

10K

AUD_SAMP_INR_N

C9707

R9715
PP3V3_AUDIO_SPKR

15 RIN+

AUD_SAMP_INR_P

C9706

1000-OHM-200MA

LOUT- 29
LOUT- 30

C9703
10UF

20%
16V
2 CERM
603

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOUTLP

LOUT+ 31
LOUT+ 32

10 LIN+

AUD_SAMP_INL_P

c
.
s
it c
1

0.1UF

GND_AUDIO_SPKRAMP_PLANE

24

10%
16V
X7R
805

C9719

CHOLD 7

9 LIN-

AUD_SAMP_INL_N

23

AUDSAMPINLP

22

VDD

0.47UF

0603

21

1%
1/16W
MF
2 402

10K
4

C9715

5%
50V
2 CERM
402

L9706

1000-OHM-200MA

R9714

10%
16V
X7R
805

100PF

97

20%
16V
2 CERM
1206

33

AUD_CODEC_OUT_L

C9702
1UF

20%
16V
CERM 2
603

0.47UF

96 95

0.1UF

PP3V3_AUDIO_SPKR

C9704

0603

95

C9718 1

10%
16V
CERM 2
1210

20%
16V 2
ELEC
SM-2

GND_AUDIO_SPKRAMP_PLANE

1000-OHM-200MA
96 95

10UF

220UF

20%
16V 2
ELEC
SM-2
99 97

C9701

C9700 1

220UF

AUD_MAX9714_CHOLD

C9717

SM

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL

XW9703
OMIT

m
o

SPEAKER AMP

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

L9700

13

C9710
1000PF

5%
2 25V
CERM
603

C9711
1000PF

5%
2 25V
CERM
603

C9712

1000PF

5%
25V
2 CERM
603

C9713
1000PF

5%
2 25V
CERM
603

C9709
0.47UF

10%
16V
2 X7R
805

GAIN SETTINGS: +16DB

MODULATION SETTING: LOW EMI

GAIN AND SWITCHING FREQUENCY STUFF OPTIONS

L9709

L9710

1000-OHM-EMI

PP3V3_AUDIO

1000-OHM-EMI
PP3V3_AUDIO_SPKR_EMI

SM

PP3V3_AUDIO_SPKR

97

SM
8 7

6 5

C9722 1

RP9700

100PF

47K

5%
50V
CERM 2
402

5%
1/16W
SM1
1

3 4

AUD_SAMP_G1
AUD_SAMP_G2
AUD_SAMP_FS1
AUD_SAMP_FS2
NOSTUFF

NOSTUFF

R9708
0

5%
1/16W
MF
2 402

R9709
0

5%
1/16W
MF
2 402

NOSTUFF
1

R9710
0

5%
1/16W
MF
2 402

NOSTUFF
1

R9711
0

5%
1/16W
MF
2 402

GND_AUDIO_SPKRAMP_PLANE

TABLE_5_HEAD

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

SPEAKER CABLE CONNECTOR

TABLE_5_ITEM

APPLE P/N 514-0098

155S0169

FLTR,EMI,FERR BD,180 OHM,1.5A

R9822,R9823,R9824,R9825,R9837

155S0093

31

FLTR,EMI,FERR BD,100 OHM.0603

R9814,R9815,R9816,R9817,R9818,R9819,R9820,R9821,R9826,R9827,R9828,R9829,R9830,R9831,R9843,R9844,R9832,R9833,R9834,R9835,R9836,R9845,R9846,R9838,R9839,R9840,R9841,R9842,R9810,R9848,R9849

OMIT

J9800

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_L_JACK

AUDIO_JACK
F-ST-TH
5

R9814
0

5%
1/16W

OMIT

R9818

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_L_EMI

MF
603

5%
1/16W

OMIT
MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_DET_JACK

1
3
4

MF
603

MF
603

MF
603

99 98 97 95 7

C9800
100PF

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_GND_EMI

5%
2 50V
CERM
402

C9801
100PF

5%
2 50V
CERM
402

C9802
100PF

C9803

100PF

5%
1/16W
MF
2 402

25

SPEAKER TYPE DETECT

TO SHASTA GPIO

14V-15A

98 7

LINE IN PLUG DETECT

AUDIO_IN_DET0_L = LOW: PLUG INSERTED
AUDIO_IN_DET0_L = HIGH: PLUG NOT INSERTED
99 95

PP3V3_AUDIO

R9800

5%
1/16W
MF
2 402

100K

5%
1/16W
MF
2 402

OMIT

R9829

95

AUD_MIC_IN_P

5%
1/16W

25

AUD_LI_DET_H

47K

AUDLINDETH

SM

95

AUD_MIC_IN_N

5%
1/16W
1

C9808

5%
1/16W

5%
1/16W

MF
603

5%
1/16W

MF
603

5%
1/16W

p
la

AUD_LO_DET1_EMI

MF
603

R9833
AUD_LO_R

5%
1/16W

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_LO_R_EMI

2
MF
603

OMIT

R9834
AUD_LO_L

96

5%
1/16W

2
MF
603

OMIT

98

5%
1/16W

AUD_LO_DET2_EMI

MF
603

OMIT

R9836
AUD_LO_GND

96

5%
1/16W

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_LO_GND_EMI

2
MF
603

OMIT

R9837

96

AUD_LO_GND_PRB

5%
1/16W

.
w
w
w

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_LO_L_EMI

R9835
AUD_LO_DET2

AUD_LO_GND_PRB_EMI

MF
603
1

C9823

C9811

100PF

100PF

C9824
100PF

5%
50V
2 CERM
402

100PF

5%
50V
2 CERM
402

5%
1/16W

MF
603

5%
1/16W

NOSTUFF
1

C9807
1000PF

5%
25V
2 CERM
603

2
3

LINE OUT PLUG DETECTS

AUDIO_LO_DET_L = LOW: PLUG INSERTED
AUDIO_LO_DET_L = HIGH: PLUG NOT INSERTED

99 98 97 95 7

PP3V3_AUDIO
1

R9804
47K

R9803

5%
1/16W
MF
2 402

100K
5%
1/16W
MF
2 402

AUDIO_LO_DET_L
3
D

R9805
AUD_LO_DET1

47K

F-ST-TH
9
10

MF
603

AUD_LO_GND_JACK
AUD_LO_DET1_JACK
AUD_LO_R_JACK
AUD_LO_L_JACK

AUD_LO_DET2_JACK

AUD_LO_DET1_1

5%
1/16W
MF
402

5%
1/16W

99 98 97 95 7

C9809
0.1UF

B
1

R9807
47K

R9806

5%
1/16W
MF
2 402

100K

5%
1/16W
MF
2 402

MF
603

SOT-363

PP3V3_AUDIO

4
2

VIN
VDD
GND

98

AUD_LO_DET2
NOSTUFF

12

NOT USED: R9811, R9848, R9849.

R9808

11

OMIT

2N7002DW

20%
2 10V
CERM
402

R9842

R9809

47K

AUD_LO_DET2_1

5%
1/16W
MF
402

2N7002DW
SOT-363

S
1

20%
2 10V
CERM
402

5%
1/16W
MF
2 402

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_SPDIF_GND

Q9801

0.1UF

100K

MF
603

C9810

TO SHASTA GPIO

NOTE: NET NAME WILL CHANGE TO

AUDIO_LO_OPTICAL_PLUG_L
AUDIO_LO_METAL_PLUG_L 25

5%
1/16W
1

C9815
AUD_LI_GND_EMI

5%
50V
2 CERM
402

100PF

XC9801
50R28

GND_CHASSIS_AUDIO_INTERNAL

DZ9801

C9816

14V-15A

0.01UF

10%
16V
2 CERM
402

PLACE NEAR
J700

98

98 7

5%
50V
2 CERM
402

XC9800
50R28

MF
603

100PF

C9814

PLACE NEAR
J9801

5%
1/16W
MF
402 2

R9810

0405
2

GND_CHASSIS_AUDIO_EXTERNAL

6 25

Q9801

OMIT

R9841
1

TO SHASTA GPIO

AUDIO-JCK-SPDIF

MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL
MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL

1000PF

HF28

CRITICAL

MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL

R9840

C9827

5%
25V
2 CERM
603

AUDIO_LO_OPTICAL_PLUG_L = LOW: OPTICAL DIGITAL AUDIO PLUG INSERTED

AUDIO_LO_OPTICAL_PLUG_L = HIGH: ANALOG AUDIO PLUG INSERTED

OMIT

M-ST-TH

APPLE P/N 518-0034

R9839
0

5%
25V
2 CERM
603

C9806

J9803

OMIT

1000PF

5%
25V
2 CERM
603

APPLE P/N 514-0116

1UF

C9826

1000PF

10%
2 10V
CERM
805

97

CRITICAL

C9822

C9818

AUD_SPKR_OUTL_P

2
MF
603

J9802

10%
2 25V
X7R
402

1000PF

5%
25V
2 CERM
603

98

0.1UF

MF
603

5%
25V
2 CERM
603

97

R98121

C9813

C9812

20%
2 10V
CERM
402

AUD_SPKR_OUTR_N

OMIT

5%
1/16W

NOSTUFF

C9805
1000PF

MF
603

OMIT

5%
50V
2 CERM
402

5%
1/16W

1000PF

2
MF
603

R9825

AUD_SPKR_OUTL_P_CONN

LINE OUT JACK

C9817

R9838

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL

NOSTUFF

C9804

MIC CABLE CONNECTOR

MF
603

5%
1/16W

100PF

5%
50V
2 CERM
402

5%
50V
2 CERM
402

98 7

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
PP5V_AUDIO_SPDIF_JACK

10%
2 25V
X7R
402

OMIT

OMIT

96

NOSTUFF

AUD_LO_DET1

5%
1/16W

AUD_SPDIF_OUT_JACK

MF
603

R9846

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
PP5V_AUDIO_SPDIF_EMI

R9832
98

OMIT

OMIT

s
p
to
1

AUD_SPDIF_OUT_EMI

C9821
1000PF

R9845

OMIT

R9844
1

C9820

GND_CHASSIS_AUDIO_INTERNAL

5%
1/16W

10%
2 25V
X7R
402

OMIT

PP5V_AUDIO

MF
603

1000PF

R9843
1

AUD_MIC_IN_N_EMI

OMIT

AUD_SPDIF_OUT

R9831

0.1UF

98 7

MF
603

5%
1/16W

20%
10V
2 CERM
402

95

1000PF

GND_AUDIO_MIC_CONN
AUD_MIC_IN_P_CONN
AUD_MIC_IN_N_CONN

OMIT

c
.
s
it c

C9825

m
e
h
c

AUD_MIC_IN_P_EMI

2
MF
603

R9828

2N7002

5%
1/16W
MF
402

5%
2 25V
CERM
603

2
MF
603

R9830

OMIT

Q9800

5%
1/16W

OMIT

R9802

GND_AUDIO_MIC_EMI

R9827

TO SHASTA GPIO
AUDIO_LI_DET_L

2
MF
603

OMIT

47K

OMIT

5%
1/16W

R9801

98

C9819

GND_CHASSIS_AUDIO_INTERNAL

R9826
1

GND_AUDIO_MIC

5%
2 25V
CERM
603

0603

1000PF

0405

AUD_SPKR_OUTL_N_CONN

MF
603

GND_CHASSIS_AUDIO_EXTERNAL

98 7

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL

OMIT

R9824

5%
1/16W

M-ST-TH

L9800

AUDIO_GPIO_12

m
o

AUD_SPKR_OUTR_N_CONN

10-89-7082

1000-OHM-200MA

MF
603

DZ9800

5%
2 50V
CERM
402

5%
2 50V
CERM
402

R9813
47K

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_GND 95

5%
1/16W

PP3V3_AUDIO

95

99 98 97 95 7

AUD_SPKR_OUTL_N

MF
603

5%
1/16W

GND_CHASSIS_AUDIO_EXTERNAL

98

97

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_R

J9801

AUD_SPKR_OUTR_P_CONN

2
MF
603

R9823

R9821

5%
1/16W

98 7

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL

CRITICAL

OMIT

OMIT

R9817
0

5%
1/16W

MF
603

5%
1/16W

AUD_SPKR_OUTR_P

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_DET_H 98

R9820

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_R_EMI

OMIT
MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_GND_JACK

97

OMIT

R9816
5%
1/16W

5%
1/16W

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL

OMIT

R9822

95

MF
603

R9819

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_DET_EMI

OMIT
MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_R_JACK

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_L

OMIT

R9815
5%
1/16W

LED

CRITICAL

APPLE P/N 518-0138

TABLE_5_ITEM

LINE IN JACK

QTY

AUDIO_GPIO_12_CONN

PART#

5V POWER SUPPLY FOR THE HEADPHONES/LINE OUT AMP

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=12MIL
VOLTAGE=12V

L9900

PP12V_AUDIO_CODEC

VR9900

R9900

FERR-250-OHM
1

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=12MIL
VOLTAGE=12V

AUD_12V_CODEC

SM-1

10

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=5V

99 98 97 95 7

LM1117
3

AUD_12V_CODEC2

5%
1W
FF
2512

SOT223-4

VOUT 4
OUT 2
ADJ/GND

PP5V_AUDIO_ANALOG

IN

C9900

1UF

C9901
220UF

20%
16V
2 CERM
1206

20%
2 16V
ELEC
SM-2

1%
1/16W
MF
402 2

220UF

25

634

1%
1/16W
MF
402 2

20%
16V 2
ELEC
SM

25

GND_AUDIO_CODEC

APPLE P/N 353S0733

VR9901
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V

MAX8510
99 96

PP5V_AUDIO_ANALOG

R99031

SHDN*

PP4V5_AUDIO_ANALOG

BP 4

100K 2

C9904
10UF

C9905
0.1UF

NOT USED: R9904,R9905

p
la

.
w
w
w

AUDIO GROUND RETURNS

XW9900
OMIT
SM
1

XW9901
OMIT
SM
1

XW9902
OMIT
SM
1

XW9903
OMIT
SM

50R28

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V

GND_AUDIO_CODEC

95 96 99

MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=6MIL
VOLTAGE=4.5V

GND_AUDIO_MIC

10%
2 10V
CERM
805

NOT USED: C9906

10%
16V
2 X7R
603

GND_AUDIO_CODEC

XC9901

C9907
1UF

20%
6.3V
2 CERM
805

GND_AUDIO

s
p
to

AUD_4V5_FB

AUD_4V5_SHDN*

DIFFERENTIAL_PAIR=AUD_CODEC_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=12MIL

C9910

10%
16V
2 CERM
402

GND

1%
1/16W
MF
402

99 96 95

OUT 5

0.01UF

1%
1/16W
MF
402 2

R9911
PP3V3_AUDIO

SC70-5

100K

NOSTUFF

99 98 97 95 7

IN

m
e
h
c

4.5V POWER SUPPLY FOR CODEC AND LINE IN AMP

20%
2 16V
ELEC
SM

R99021

100UF

C9903
100UF

AUD_V5_REF
FC=7HZ

20%
2 16V
ELEC
SM-2

C9902 1
99 96 95

m
o

c
.
s
it c
25

R99011

C9909

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
PP3V3_AUDIO

NOTE: NET NAME WILL CHANGE TO

AUDIO_LI_OPTICAL_PLUG_L

96 99

205

25

25

AUDIO_LI_METAL_PLUG_L

47K

5%
1/16W
MF
402

R9907
1

AUDIO_HP_DET_L

47K

5%
1/16W
MF
402

R9908

AUDIO_SPKR_DET_L

47K

5%
1/16W
MF
402

R9909
1

I2S2_DEV_TO_SB_DTI

47K

5%
1/16W
MF
402

R9910

AUDIO_GPIO_11

47K

5%
1/16W
MF
402

95

R9916
25

I2S2_BITCLK

47K

5%
1/16W
MF
402

R9917

C9908

25

I2S2_SYNC

10UF

47K

5%
1/16W
MF
402

20%
2 16V
ELEC
SM-1

GND_AUDIO_SPKRAMP_PLANE

R9906

R9912
25

AUDIO_HP_MUTE_L

47K

5%
1/16W
MF
402

R9913
25

AUDIO_EXT_MCLK_SEL

47K

5%
1/16W
MF
402

R9914
25

I2S2_RESET_L

PLACE ACROSS GROUND SPLIT

AT RIGHT SIDE OF C9707

97

UNUSED GPIO TERMINATIONS

APPLE P/N 353S0539

DIFFERENTIAL_PAIR=AUD_CODEC_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=12MIL
VOLTAGE=12V

47K

5%
1/16W
MF
402

NOSTUFF

R9918
1

GND_AUDIO_CODEC

95 96 99

5%
1/10W
FF
805

PLACE NEAR ENTRY TO SPEAKER

AMP GROUND PLANE

MAKE_BASE=TRUE
TP_I2S2_SB_TO_DEV_DTO

I88

MAKE_BASE=TRUE
TP_I2S2_MCLK

I89

I2S2_SB_TO_DEV_DTO

I2S2_MCLK

25

25

NOSTUFF

R9919
97 7

GND_AUDIO_SPKRAMP

5%
1/10W
FF
805

95 98

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V

GND_AUD_LOAMP

96

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V
GND_AUD_LOAMP_CHGPMP

PLACE ACROSS GROUND SPLIT

AT CODEC U9500

96

NOSTUFF

R9915
99 96 95

GND_AUDIO_CODEC

5%
1/10W
MF
603