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Outline: 1. Overview On Sequential Circuit

The document discusses sequential circuit design and covers the following key points: 1. It provides an overview of sequential circuits and basic memory elements like D latches and flip-flops. 2. It explains the principles of synchronous sequential circuits using a global clock signal and the advantages this approach provides for timing analysis and design. 3. It warns about the dangers of directly synthesizing asynchronous circuits like latches instead of using pre-designed library elements, and provides examples of correctly specifying basic memory elements in VHDL. 4. It presents several examples of simple sequential circuit designs like counters and shift registers to demonstrate applying the synchronous design methodology.

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40 views

Outline: 1. Overview On Sequential Circuit

The document discusses sequential circuit design and covers the following key points: 1. It provides an overview of sequential circuits and basic memory elements like D latches and flip-flops. 2. It explains the principles of synchronous sequential circuits using a global clock signal and the advantages this approach provides for timing analysis and design. 3. It warns about the dangers of directly synthesizing asynchronous circuits like latches instead of using pre-designed library elements, and provides examples of correctly specifying basic memory elements in VHDL. 4. It presents several examples of simple sequential circuit designs like counters and shift registers to demonstrate applying the synchronous design methodology.

Uploaded by

bennettmatthew
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© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
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Outline Sequential Circuit Design: Principle

1. 2. 3. 4. 5. 6. 7. 8.
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Overview on sequential circuits Synchronous circuits Danger of synthesizing asynchronous circuit Inference of basic memory elements Simple design examples Timing analysis Alternative one-segment coding style Use of variable for sequential circuit
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1. Overview on sequential circuit


Combinational vs sequential circuit
Sequential circuit: output is a function of current input and state (memory)

D latch: level sensitive D FF: edge sensitive

Basic memory elements


D latch D FF (Flip-Flop) RAM

Synchronous vs asynchronous circuit


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Problem wit D latch: Can the two D latches swap data?

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Timing of a D FF:
Clock-to-q delay Constraint: setup time and hold time

Synch vs asynch circuits


Globally synchronous circuit: all memory elements (D FFs) controlled (synchronized) by a common global clock signal Globally asynchronous but locally synchronous circuit (GALS). Globally asynchronous circuit
Use D FF but not a global clock Use no clock signal

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2. Synchronous circuit
One of the most difficult design aspects of a sequential circuit: How to satisfy the timing constraints The Big idea: Synchronous methodology
Group all D FFs together with a single clock: Synchronous methodology Only need to deal with the timing constraint of one memory element
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Basic block diagram


State register (memory elements) Next-state logic (combinational circuit) Output logic (combinational circuit)

Operation
At the rising edge of the clock, state_next sampled and stored into the register (and becomes the new value of state_reg The next-state logic determines the new value (new state_next) and the output logic generates the output At the rising edge of the clock, the new value of state_next sampled and stored into the register

Glitches has no effects as long as the state_next is stabled at the sampling edge
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Sync circuit and EDA


Synthesis: reduce to combinational circuit synthesis Timing analysis: involve only a single closed feedback loop (others reduce to combinational circuit analysis) Simulation: support cycle-based simulation Testing: can facilitate scan-chain
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Types of sync circuits


Not formally defined, Just for coding Three types:
Regular sequential circuit Random sequential circuit (FSM) Combined sequential circuit (FSM with a Data path, FSMD)

3. Danger of synthesizing asynchronous circuit


D Latch/DFF
Are combinational circuits with feedback loop Design is different from normal combinational circuits (it is delay-sensitive) Should not be synthesized from scratch Should use pre-designed cells from device library

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E.g., a D latch from scratch

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4. Inference of basic memory elements


VHDL code should be clear so that the pre-designed cells can be inferred VHDL code
D Latch Positive edge-triggered D FF Negative edge-triggered D FF D FF with asynchronous reset

D Latch
No else branch D latch will be inferred

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Pos edge-triggered D FF No else branch Note the sensitivity list

Neg edge-triggered D FF

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D FF with async reset No else branch Note the sensitivity list

Register Multiple D FFs with same clock and reset

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5. Simple design examples


Follow the block diagram
Register Next-state logic (combinational circuit) Output logic (combinational circuit)

D FF with sync enable


Note that the en is controlled by clock Note the sensitivity list

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T FF

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Free-running shift register

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Universal shift register


4 ops: parallel load, shift right, shift left, pause

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Arbitrary sequence counter

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Free-running binary counter


Count in binary sequence With a max_pulse output: asserted when counter is in 1111 state

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Binary counter with bells & whistles

Wrapped around automatically Poor practice:

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Decade (mod-10) counter

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Programmable mod-m counter

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6. Timing analysis
Combinational circuit:
characterized by propagation delay

Sequential circuit:
Has to satisfy setup/hold time constraint Characterized by maximal clock rate (e.g., 200 MHz counter, 2.4 GHz Pentium II) Setup time and clock-to-q delay of register and the propagation delay of next-state logic are embedded in clock rate
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state_next must satisfy the constraint Must consider effect of


state_reg: can be controlled synchronized external input (from a subsystem of same clock) unsynchronized external input First 2: adjust clock rate to prevent violation Last: use synchronization circuit to resolve violation

Setup time violation and maximal clock rate

Approach

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E.g., shift register; let Tcq=1.0ns Tsetup=0.5ns

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E.g., Binary counter; let Tcq=1.0ns Tsetup=0.5ns

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Hold time violation

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Output delay

7. Alternative one-segment coding style


Combine register and next-state logic/output logic in the same process May appear compact for certain simple circuit But it can be error-prone

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10

D FF with sync enable

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Interpretation: any left-hand-side signal within the clkevent and clik=1 branch infers a D FF
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T FF

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Binary counter with bells & whistles

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Free-running binary counter


Count in binary sequence With a max_pulse output: asserted when counter is in 1111 state

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Programmable mod-m counter

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Two-segment code
Separate memory segment from the rest Can be little cumbersome Has a clear mapping to hardware component

One-segment code
Mix memory segment and next-state logic / output logic Can sometimes be more compact No clear hardware mapping Error prone

Two-segment code is preferred


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