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Stopwatch Using Logic Gates

1) Students Anwer Alsomaily and Abdullah Al-Karairi designed a stopwatch circuit for their digital logic design project that uses 4 BCD counters and other ICs to count up to 99 minutes and 59 seconds and then reset itself. 2) The circuit uses 4-hexadecimal displays, 4-74161 BCD counters, 1-7408 AND gate, 1-7400 NAND gate, and 1-7432 OR gate. 3) The students faced difficulties with the initial 7493 BCD counter not resetting properly and instead found that the 74161 BCD counter worked better for their design needs.

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akarairi
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12K views

Stopwatch Using Logic Gates

1) Students Anwer Alsomaily and Abdullah Al-Karairi designed a stopwatch circuit for their digital logic design project that uses 4 BCD counters and other ICs to count up to 99 minutes and 59 seconds and then reset itself. 2) The circuit uses 4-hexadecimal displays, 4-74161 BCD counters, 1-7408 AND gate, 1-7400 NAND gate, and 1-7432 OR gate. 3) The students faced difficulties with the initial 7493 BCD counter not resetting properly and instead found that the 74161 BCD counter worked better for their design needs.

Uploaded by

akarairi
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of Electrical Engineering

EE 200 DIGITAL LOGIC CIRCUIT DESIGN

Design Project

StopWatch Done by
Anwer Alsomaily 200841680 & Abdullah Al-Karairi 200923910 For Dr. K QURESHI

Introduction:
Due to importance of time in exams competition and other situations in our life, we found that stopwatch is the most useful project we may do. This stopwatch should have START/STOP/RESET functions and it counts up to 100 minutes (99:59) then it rests itself.

Equipment & ICs:


4- Hexadecimal display 4- BCD counter (74-161) 1- 7408 AND Gate 1- 7400 NAND Gate 1- 7432 OR Gate

Reset Clock Start/Stop

Circuit logic work implantation:

Lab Work
+5 V (RED) We used it as a power supply for all IC's 0V "ground" (Blue) We use it to set the initial value of the inputs (A,B,C,D) to be 0 To Ground All IC's. Load (Orange) We Connect it As Shown in the logic work Diagram; By that way 1st Counter will count up to 9 and rest it self at the same moment it gives a clock pulse to 2nd Counter 2nd Counter Will count up to 5 then repeat it self, Once It is be came 5 & 1st Counter 9 they will give a clock pulse to the 3rd Counter which will count up to 9 and by the same way 4th counter will be pulsed. Clock (white) Connected with SWETCH using And Gate to deactivate it when we want to stop counting and the output of this and is connected to this clock of 1st counter. Output "QA,QB,QC,QD" (Green) The output of the counters are connected to hexadecimal display. Clear (Black) We connected all the clear together and connect it to active high pulser.

The stopwach was working duo to this table:

ClK up up up

Clear (invert) 1 0 1

Load 1 x 0

Display Next state 0 Intial state (ABCD)

Defficalies:
At the beginning of our project we used 7493 BCD counter but we faced a problem that 7493 counter before it goes to the next state it go back to the initial state and start counting up to the needed state. So we tride to make the Counter using JK FF But when we did the simulation on logicworks we found the the connection was very complicated and it is very difficuat to do it on minilab. By searching on the Internet we found BCD counter 74_161 (Fig 2 Last PIG) wich is fuction well with our project. 7-segment displayer needs to be connected to a 7-segment decoder in order to reduce the number of ICs and the cost of the circuit we used HexDicimal Diplayer. (Fig1 Last PG)

Conclusion:
At the end of our work the stopwatch was working as we planned. In this project we touched the exciting part of digital design every issue was exciting challenge. The most important part of this project that we covered what we have studied experimentally and practice a new experience; also we had a good review for the final Exam.

74-161 connection

74-161 Internal structure

Hexadecimal Display connection

49
3

7 10
BI
4 2 1 5

P T 161 15 2 CLK RCO


3 2

R02 R01

93

D C B A

G 12 F 13 E 6 D8 9 C B 10 A 11

CLKB CLKA

QD QC QB QA

11 8 9 12

dot g

6 5 4 3
14

D C B A
49
3

QD QC QB QA
BI

11 12 13 14

9
+5V
4 D 2 C 1 B 5 A

LOAD
G 12 13 F E 6 D8 C9 B 10 A 11

CLR

dot g

49
3

7 10
4 2 1 5

BI D C B A

P T 161 15 2 CLK RCO


3 2

G 12 F 13 E 6 D8 C9 B 10 A 11

dot g

R02 R01 QD QC QB QA
11 8 9 12

93
49
3

6 5 4 3
1

D C B A
CLKB CLKA
4 2 1 5

QD QC QB QA
14

11 12 13 14
BI

9
D C B A

LOAD

CLR

G 12 13 F E 6 D8 C9 B 10 A 11

dot g

7 10

P T 161 15 CLK RCO


3 2

6 5 4 3
R02 R01
11 8 9 12

D C B A
93
1

QD QC QB QA
CLKB CLKA QD QC QB QA
14

11 12 13 14

LOAD

CLR

3 2

7 10

P T 161 15 CLK RCO


3 2

6 5 4 3

D C B A

QD QC QB QA

11 12 13 14

R02 R01

93
QD QC QB QA
1 14 11 8 9 12

CLKB CLKA

LOAD

CLR

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