IA - DLC - 1 v1
IA - DLC - 1 v1
UNITED INSTITUTE OF TECHNOLOGY Periyanaickenpalayam, Coimbatore- 641 020. Internal Assessment I Degree & Branch: B.E. & EEE Date: .01.2012 Semester : IV Time: 08.50 AM 10.20 AM Subject Code with Title: EE2255 Part A Digital Logic Circuit Max. Marks: 50 (Answer all the Questions) 5 X 2 = 10 Marks
1) Give the Boolean Expression used for the following gates (a) AND (b) NOR (c) EX-OR (d) OR (e) NOT (f) EX-NOR. 2) 3) 4) 5) Show how Y ABC can be implemented with one 2 input NOR and one 2-input NAND gates. State and prove the consensus theorem in Boolean algebra. Implement Y ABCD using 2 inputs NAND Gates. Convert the given expression in Standard POS form (i) f ( A, B, C ) ( A B)( B C ) (ii) f ( P, Q, R ) ( P Q )( P R )
Part B
f ( A, B, C, D, E) m(1, 4,6,10, 20, 22, 24, 26) d (0,11,16, 27) using Karnaugh Map method. Draw the
circuit of the minimal expression using only NAND gates. (OR) Simplify the following Boolean function by using a Quine-McCluskey method
F ( A, B, C, D) m(0, 2,3,6,7,8,10,12,13)
2) (1) Express the Boolean function F XY XZ in product of Maxterms. (2)Reduce the following function using Karnaugh Map technique
(16)
3) (1)Using Graphical procedure ,obtain a NOR Gate realization of the Boolean expression
f ( a, b, c, d ) ad ad (b c )
(2)Implement F ( AB AB)(C D) with only NOR gates
( x1 x2 )( x1 x3 x3 )( x2 x1 x3 )