Scribd
Upload
29 views

D Flip-Flop JK Flip-Flop SR-latch T Flip-Flop D Q J K Q S R Q T Q 0 0 0 0 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1

This document contains an exam for a digital computers course. It includes questions about filling in truth tables for latches and flip-flops, drawing timing diagrams, modifying a counter circuit, drawing state diagrams and tables, implementing state machines using flip-flops, writing logic equations from a partial product of sums table, and properties of read-only memory (ROM) modules including size and whether they are combinational or sequential.

Uploaded by

Mộc Sầu
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
29 views

D Flip-Flop JK Flip-Flop SR-latch T Flip-Flop D Q J K Q S R Q T Q 0 0 0 0 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1

This document contains an exam for a digital computers course. It includes questions about filling in truth tables for latches and flip-flops, drawing timing diagrams, modifying a counter circuit, drawing state diagrams and tables, implementing state machines using flip-flops, writing logic equations from a partial product of sums table, and properties of read-only memory (ROM) modules including size and whether they are combinational or sequential.

Uploaded by

Mộc Sầu
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

EE 18 Introduction to Digital Computers Exam 2 Fall, 1998 Prof.

Traver
1. (14 points) a. Fill in the function tables for the following latches and flip-flops.

D flip-flop D Qn 0 1

JK flip-flop J K Qn 0 0 0 1 1 0 1 1

SR-latch S R Qn 0 0 0 1 1 0 1 1

T flip-flop T Qn 0 1

b. Fill in the timing diagram for the JK flip-flop output.


J_in

J_in K_in clk

J K

Q_out

K_in clk

Q_out

2. (14 points) Give the sequence generated by the following circuit after all the flip-flops are reset to zero. A B C
A B C

Q Q

Q Q

Q Q

clk

3. (14 points) Modify the following 3-bit counter so that it is a mod 7 counter that counts in the repeating sequence 000, 001, 010, 011, 100, 101, 110, 000 The function table of the counter is given. Additional logic will be needed. Be sure to define all inputs. load clk 0 1 function count up load inputs

D0 D1 D2 load

Q0 Q1 Q2

3-bit counter

4. (14 points) a. Given the state diagram below, draw the corresponding state table. The input is X and the output is Z.
1/0 0 1/0 0/0 1 0/1

b. Is this a Mealy or Moore state diagram?__________

5. (14 points) A state diagram and the corresponding state table are given below. Find the circuit that implements these. Use a D flip-flop. Be sure to label all inputs, outputs and state values.
0/1 1/0 0/1

1/1 1

current next state input state Q x Qn 0 0 0 0 1 0 1 0 0 1 1 1

output Z 1 0 1 1

6. (14 points) Given the partial PLA table below, write equations for F and G. (T) F 1 1 0 0 1 (C) G 0 1 1 1 0

A 0 1 1 0 1

B 1 0 1

C 1 0 -

7. (14 points) a. Give the size of a ROM with 8 address lines and 4 data lines._____________

b. What size ROM is required to implement a 4-bit adder? ______________

c. Give the number of address lines and data lines for a 1K x 4 ROM.______________

d. Is a ROM a combinational or sequential module?______________ (hint: it can be used to implement a 4-bit adder)

8. (5 points extra credit) Show how 256 x 4 RAMs would be connected to form a 1M x 8 memory module. Be sure to label all inputs and outputs of the module, and all inputs and outputs of the individual RAMs.

You might also like