8051 PROGRAMS

EXP NO: 01

DATE:

ADDITION OF 8 BIT AND 16 BIT

AIM

PROGRAMS ;************ Program description ;8 bit unsigned addition using register addressing ;R2 = NUM1; R3 = NUM2 ;R4 = LSB, R5 = MSB ;************ Constants ;************ variable declaration ORG LJMP ORG START: CLR MOV MOV MOV MOV ADD JNC INC NOOFLOW: MOV SJMP END 0x0000 START 0X0040 A R4,A R2,#20 R3,#30 A,R2 A,R3 NOOFLOW R5 R4,A $ ;Control stays here ;LOAD VALUES IN REGISTER ;clear result vars

PROGRAMS ;************ Program description ;8 bit unsigned addition using register addressing ;R2 = NUM1; R3 = NUM2 ;R4 = LSB, R5 = MSB ;************ Constants ;************ variable declaration ORG LJMP ORG START: CLR MOV MOV MOV MOV ADD JNC INC NOOFLOW: MOV 0x0000 START 0X0040 A R4,A R2,#20 R3,#30 A,R2 A,R3 NOOFLOW R5 R4,A ;LOAD VALUES IN REGISTER ;CLEAR RESULT

SJMP END

;CONTROL STAYS HERE

;************ Program description ;16 bit Add ;************ Constants ;************ variable declaration ORG 0x0000

LJMP ORG START:

START 0X0040 MOV R6,#1Ah MOV R7,#44h MOV R4,#22h MOV R5,#0DBh LCALL ADD16_16 SJMP $ ;Call the 16-bit addition routine ;Control stays here ;Load the first value into R6 and R7 ;Load the second value into R4 and R5

ADD16_16: ;Step 1 of the process MOV A,R7 ADD A,R5 accumulator MOV R3,A the answer to the low-byte of the result ;Step 2 of the process MOV A,R6 ;Move the high-byte into the accumulator ADDC A,R4 `to the accumulator, plus carry. MOV R2,A ;Step 3 of the process MOV A,#00h ADDC A,#00h MOV R1,A RET END ;By default, the highest byte will be zero. ;Add zero, plus carry from step 2. ;Move the answer to the highest byte of the result ;Return - answer now resides in R1, R2, and R3. ;Move the answer to the high-byte of the result ;Add the second high-byte ;Move ;Move the low-byte into the accumulator ;Add the second low-byte to the

RESULT

EXP NO: 02

DATE:

SUBTRACTION OF 8 BIT AND 16 BIT

AIM

PROGRAMS ;************ Program description ;8 bit unsigned addition using register addressing ;R2 = NUM1; R3 = NUM2 ;R4 = LSB, R5 = MSB ;************ Constants ;************ variable declaration ORG LJMP ORG START: CLR MOV MOV MOV MOV SUBB 0x0000 START 0X0040 A R4,A R2,#20 R3,#30 A,R2 A,R3 ;LOAD VALUES IN REGISTER ;clear result vars

JNC INC NOOFLOW: MOV SJMP END

NOOFLOW R5 R4,A $ ;Control stays here

************ Program description ;16 bit SUB ;************ Constants ;************ variable declaration ORG LJMP ORG START: 0x0000 START 0X0040

MOV R6,#22h MOV R7,#0DBh MOV R4,#1Ah MOV R5,#0F9h LCALL SUBB16_16 SJMP $

;Load the first value into R6 and R7 ;Load the second value into R4 and R5

;Call the 16-bit SUb routine ;Control stays here

SUBB16_16: ;Step 1 of the process MOV A,R7 CLR C ;Move the low-byte into the accumulator ;Always clear carry before first subtraction SUBB ;Subtract the second low-byte from the accumulator MOV R3,A ;Step 2 of the process ;Move the answer to the low-byte of the result

MOV A,R6 SUBB A,R4 MOV R2,A RET END

;Move the high-byte into the accumulator ;Subtract the second high-byte from the accumulator ;Move the answer to the low-byte of the result ;Return - answer now resides in R2, and R3.

RESULT

EXP NO: 03

DATE:

MULTIPLICATION OF 16 BIT
AIM

PROGRAMS *********** Program description ;16 bit Multiplication ;************ Constants ;************ variable declaration ORG LJMP ORG START: MOV R6,#62h MOV R7,#30h ;Load the first value into R6 and R7 0x0000 START 0X0040

MOV R4,#43h MOV R5,#2Eh LCALL MUL16_16 SJMP $ MUL16_16: ;Multiply R5 by R7 MOV A,R5 MOV B,R7 MUL AB MOV R2,B MOV R3,A ;Multiply R5 by R6 MOV A,R5 MOV B,R6 MUL AB ADD A,R2 MOV R2,A MOV A,B ADDC A,#00h MOV R1,A MOV A,#00h ADDC A,#00h MOV R0,A ;Multiply R4 by R7 MOV A,R4 MOV B,R7 MUL AB

;Load the first value into R4 and R5 ;Call the 16-bit subtraction routine

;Move the R5 into the Accumulator ; Move R7 into B ;Multiply the two values ; Move B (the high-byte) into R2 ;Move A (the low-byte) into R3

;Move R5 back into the Accumulator ;Move R6 into B ;Multiply the two values ;Add the low-byte into the value already in R2 ;Move the resulting value back into R2 ;Move the high-byte into the accumulator ;Add zero (plus the carry, if any) ;Move the resulting answer into R1 ;Load the accumulator with zero ;Add zero (plus the carry, if any) ;Move the resulting answer to R0.

;Move R4 into the Accumulator ;Move R7 into B Multiply the two values ADD A,R2 ;Add the low-byte into the value already in R2

MOV R2,A MOV A,B

; Move the resulting value back into R2 ;Move the high-byte into the accumulator ADDC A,R1 ;Add the current value of R1 (plus any carry)

MOV R1,A

;Move the resulting answer into R1.

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MOV A,#00h

;Load the accumulator with zero ADDC A,R0 ;Add the current value of R0 (plus anycarry)

MOV R0,A ;Multiply R4 by R6 MOV A,R4 MOV B,R6 MUL AB

; Move the resulting answer to R1.

;Move R4 back into the Accumulator ;Move R6 into B ;Multiply the two values ADD A,R1 Add the low-byte into the value already in R1

MOV R1,A MOV A,B

;Move the resulting value back into R1 ;Move the high-byte into the accumulator ADDC A,R0 ;Add it to the value already in R0 (plus any carry)

MOV R0,A ; RET END;

Move the resulting answer back to R0 ;Return - answer is now in R0, R1, R2, and R3

11

RESULT

EXP NO: 04

DATE:

DIVISION OF 8 BIT
AIM

PROGRAMS ;************ Program description ;8 bit Division using register addressing ;R2 = NUM1; R3 = NUM2 ;R4 = LSB, R5 = MSB ;************ Constants ;************ variable declaration ORG LJMP 0x0000 START

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ORG START: MOV MOV MOV MOV MOV LOOP2: SUBB JC INC

0X0040

R2,#4 R3,#2 A,R3 R4,A A,R2 A,R3 LOOP1 R5 ;LOAD VALUES IN REGISTER

DJNZ R4, LOOP2 SJMP LOOP3 LOOP1: LOOP3: INC R5 MOV SJMP END R6,A $ ;Control stays here

13

RESULT

EXP NO: 05

DATE:

SMALLEST AND LARGEST NUMBER

AIM

PROGRAM ;************ Program description ;8 bit unsigned addition of series of numbers using indirect addressing ;INPUT LOCATION 41 to 4F,40 -number of digits, OUTPUT LOCATION 50 & 51 ;;************ Constants Input Result Big EQU EQU EQU 0x40 0x50 0x30

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;************ variable declaration ORG LJMP ORG START: MOV MOV MOV MOV 0x0000 START 0X0040 A,#0 Big,A R0,#Input R1,#Result ;INITIALISE MEMORY LOCATION ;INITIALISE COUNTER, R2 IS USED AS COUNTER ;INITIALISE TEMP VARIABLES ;INITIALISE POINTERS

ACALL InitInputs MOV MOV INC CLR CHK_AGAIN: MOV SUBB JC MOV OOFLOW: INC DJNZ MOV A,@R0 R2,A R0 C A,@R0 A,Big OOFLOW Big,@R0 R0

;Small = A, if carry occurs

R2,CHK_AGAIN @R1,Big ;STORE LSB IN RESULT LOCATION

SJMP

;Control stays here

;FUNCTION TO LOAD VALUE AT MEMORY LOCATION InitInputs: MOV MOV MOV INC MOV @R0,#8 A,@R0 R2,A R0 A,#20 ;8 numbers to be processed ;INITIALISE COUNTER

15

DO_AGAIN:

MOV INC INC DJNZ MOV RET END

@R0,A ;LOAD 20,21... IN TO MEMORY LOCATION A R0 R2,DO_AGAIN R0,#Input ;INITIALISE POINTERS

16

RESULT

EXP NO: 06

DATE:

COUNT THE NUMBER OF EVEN AND ODD NUMBERS

AIM

PROGRAM ;************ Program description

17

;8 bit unsigned addition of series of numbers using indirect addressing ;INPUT LOCATION 41 to 4F,40 -number of digits, OUTPUT LOCATION 50 & 51 ;50 - even numbers, 51 - oddnumbers ;R3 - even numbers,R4 - odd nubers ;************ Constants Input Result EQU EQU EQU 0x40 0x50 0x30 0x31

EvenNum EQU OddNum

;************ variable declaration ORG LJMP ORG START: MOV MOV MOV MOV MOV MOV MOV INC CLR CHK_AGAIN: MOV A,@R0 RRC JNC INC SJMP EVEN: AGAIN: INC INC DJNZ MOV INC MOV A EVEN OddNum AGAIN EvenNum R0 R2 ,CHK_AGAIN @R1,EvenNum ;STORE LSB IN RESULT LOCATION R1 @R1,OddNum ;STORE LSB IN RESULT LOCATION ;EVEN COUNT INCREMENTED ;ODD COUNT INCREMENTED A,#0 EvenNum,A OddNum,A R0,#Input R1,#Result ;INITIALISE MEMORY LOCATION ;INITIALISE COUNTER, R2 IS USED AS COUNTER A,@R0 R2,A R0 C ;INITIALISE POINTERS ;INITIALISE TEMP REGISTERS 0x0000 START 0X0040

ACALL InitInputs

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SJMP

;Control stays here

;************ FUNCTION TO LOAD VALUE AT MEMORY LOCATION ********************** InitInputs: MOV MOV MOV INC MOV DO_AGAIN: MOV INC INC DJNZ MOV RET END @R0,#8 A,@R0 R2,A R0 A,#20 @R0,A ;LOAD 20,21... IN TO MEMORY LOCATION A R0 R2,DO_AGAIN R0,#Input ;INITIALISE POINTERS ;8 numbers to be processed ;INITIALISE COUNTER

19

RESULT

EXP NO:07

DATE:

20

TO FIND THE POSITIVE AND NEGATIVE NUMBER

AIM

PROGRAM ;************ Program description ;CHECKS THE GIVEN NUMBER IS ODD OR EVEN using indirect addressing ;INPUT LOCATION 40,OUTPUT LOCATION 41 = 0, if POSITIVE else 41 = 1 ;************ Constants Input EQU 0x40 ORG LJMP ORG START: MOV R0,#Input MOV CLR MOV INC RLC JC MOV SJMP NEGATIVE: DONE: MOV SJMP END ;INITIALISE POINTERS ;LOAD DATA IN MEMORY 0x0000 START 0X0040 ;************ variable declaration

@R0,#31 C A,@R0 R0 A NEGATIVE @R0,#0 DONE @R0,#1 $

;NUMBER IS POSITIVE ;NUMBER IS NEGATIVE ;Control stays here

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RESULT

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EXP NO:08

DATE:

SORTING OF NUMBER
AIM

PROGRAM ASCENDING ORG 00h ;-----------------------------------Data Required for the Program-----------------------------------MOV R4,#04h MOV 50h,#0x05 MOV 51h,#0x03 MOV 52h,#0x02 MOV 53h,#0x04 ;----------------------------Sort in Ascending Order Using Bubble Sort------------------------------LOOP1: MOV R0, #03h MOV R1,#50h MOV A, R0 ;Point to beginning of array ;Initialize R0 - the counter for LOOP2 MOV R3, A ;to the value of R0 - the number of iterations in each pass is same ;as the number of elements minus serial number of the current pass. LOOP2: MOV A, @R1 MOV R3, A INC R1 MOV A, @R1 SUBB A, R3 ;Inner Loop - Handles each pass. ;Copy a number of the array to the accumulator ;and store it in R3. ;Move to the net number ;and store that in the accumulator. ;Subtract the first from the second. JNC Continue2 ;If no carry is generated the second ;Outer Loop - Handles number of passes ;Counter for LOOP1

is greater and the numbers are ;in order with respect to each other. Otherwise they must be swapped. MOV A, @R1 ;Move the second number to the accumulator.

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XCH A, R3 and R1 the second.

;Exchange contents of the

accumulator and R3. This makes A contain the first number MOV @R1, A ;Store the first number at the place where the second one was stored. DEC R1 MOV A, R3 MOV @R1, A INC R1 Continue2: DJNZ R0, LOOP2 Continue1: DJNZ R4, LOOP1 Here: SJMP Here END ;---------------------------------------------------------------------------------------------------DESENDING ;---------------------------------------------------------------------------------------------------ORG 00h ;-----------------------------------Data Required for the Program-----------------------------------MOV R4,#04h MOV 50h,#0x02 MOV 51h,#0x04 MOV 52h,#0x03 MOV 53h,#0x05 ;----------------------------Sort in Desending Order Using Bubble Sort------------------------------LOOP1: MOV R0, #03h MOV R1,#50h MOV A, R0 ;Point to beginning of array ;Initialize R1 - the counter for LOOP2 MOV R3, A ;to the value of R0 - the number of iterations in each pass is same as the number of elements minus serial number of the current pass. ;Outer Loop - Handles number of passes ;Counter for LOOP1 ;Move on to the next pass. ;End of program - Loop here indefinitely. ;Move on to the next iteration of the current pass. ;Move to the previous memory location. ;Copy the second number to the accumulator ;and store it in the first number's place. ;Move to the next memory location.

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LOOP2: MOV A, @R1 MOV R3, A INC R1 MOV A, @R1 SUBB A, R3

;Inner Loop - Handles each pass. ;Copy a number of the array to the accumulator ;and store it in R2. ;Move to the net number ;and store that in the accumulator. ;Subtract the first from the second. JC Continue2 ;If no carry is generated the second is greater and the numbers are in order with respect to each other. Otherwise they must be swapped. MOV A, @R1 ;Move the second number to the accumulator. XCH A, R3 ;Exchange contents of the accumulator and R2. This makes A contain the first number and R2 the second. MOV @R1, A DEC R1 MOV A, R3 MOV @R1, A INC R1 ;Store the first number at the place where the second one was stored. ;Move to the previous memory location. ;Copy the second number to the accumulator ;and store it in the first number's place. ;Move to the next memory location.

Continue2: DJNZ R0, LOOP2 Continue1: DJNZ R4, LOOP1 Here: SJMP Here END ;End of program - Loop here indefinitely. ;Move on to the next pass. ;Move on to the next iteration of the current pass.

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26

RESULT

VLSI PROGRAMS

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EXP NO:01

DATE:

DEGIN OF HALF ADDERS

AIM To develop the VHDL code for Half adder and obtain the simulation

VHDL CODE Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hadd is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end hadd; architecture dataflow of hadd is begin sum <= a xor b; carry <= a and b; end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity haddbehavioral is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic);

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end haddbehavioral; architecture Behavioral of haddbehavioral is begin p1:process (a,b) begin sum<= a xor b; carry<= a and b; end process p1; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity haddstructural is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end haddstructural; architecture structural of haddstructural is component xor2 port(a,b:in std_logic; z:out std_logic); end component; component and2 port(a,b:in std_logic; z:out std_logic); end component; begin x1: xor2 port map (a,b,sum); a1: and2 port map (a,b,carry); end structural; and2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end and2; architecture dataflow of and2 is begin z<= a and b; end dataflow; xor2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

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use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end xor2; architecture dataflow of xor2 is begin z<= a xor b; end dataflow;

Simulation output:

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Synthesis RTL Schematic:

31

32

RESULT Thus the half adders is designed using VHDL code and obtained its simulated.

EXP NO:02

DATE:

DEGIN OF FULL ADDERS

AIM To develop the VHDL code for full adder and obtain the simulation

VHDL CODE Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_dataflow is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd_dataflow; architecture dataflow of fadd_dataflow is signal p,q,r,s:std_logic; begin

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p<= a xor b; q<= a and b; r<= b and c; s<= c and a; sum<= p xor c; carry<= q or r or s; end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_behv is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd_behv; architecture Behavioral of fadd_behv is begin p1:process(a,b,c) variable r,s,t:std_logic; begin r:= a and b; s:= b and c; t:= c and a; sum<= a xor b xor c; carry<= r or s or t; end process p1; end Behavioral;

Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_structural is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd_structural; architecture structural of fadd_structural is component xor2 port(a,b:in std_logic; z:out std_logic); end component; component and2

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port(a,b:in std_logic; z:out std_logic); end component; component or3 port(a,b,c:in std_logic; z:out std_logic); end component; signal p,q,r,s:std_logic; begin x1: xor2 port map (a,b,p); x2: xor2 port map (p,c,sum); a1: and2 port map (a,b,q); a2: and2 port map (b,c,r); a3: and2 port map (c,a,s); o1: or3 port map (q,r,s,carry); end structural; and2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end and2; architecture dataflow of and2 is begin z<= a and b; end dataflow; or3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end or3; architecture dataflow of or3 is begin z<= a or b or c; end dataflow; xor2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2 is Port ( a : in std_logic;

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b : in std_logic; z : out std_logic); end xor2; architecture dataflow of xor2 is begin z<= a xor b; end dataflow;

Simulation output:

36

Synthesis RTL Schematic:

37

38

RESULT Thus the full adders is designed using VHDL code and obtained its simulated.

EXP NO:03

DATE:

DEGIN OF HALF SUBTRACTOR

AIM To develop the VHDL code for Half subtractor and obtain the simulation

VHDL CODE

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Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hsub is Port ( a : in std_logic; b : in std_logic; brw : out std_logic; diff : out std_logic); end hsub; architecture dataflow of hsub is signal a1:std_logic; begin a1<= not a; brrw <= a xor b; diff <= a1 and b; end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hsubbehavioral is Port ( a : in std_logic; b : in std_logic; diff : out std_logic; brrw : out std_logic); end hsubbehavioral; architecture Behavioral of hsubbehavioral is signal a1: std_logic; begin p1:process (a,b) begin a1<= not a; diff <= a xor b; brrw <= a1 and b; end process p1; end Behavioral;

Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hsubstructural is Port ( a : in std_logic; b : in std_logic; diff : out std_logic;

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brrw: out std_logic); end hsubstructural; architecture structural of hsubstructural is component xor2 port(a,b:in std_logic; z:out std_logic); end component; component and2 port(a,b:in std_logic; z:out std_logic); end component; component not1 port(a:in std_logic; z:out std_logic); end component; signal a1: std_logic; begin x1: xor2 port map (a,b,diff); y1:not1 portmap(a,a1); z1: and2 port map (a1,b,brrw); end structural; and2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end and2; architecture dataflow of and2 is begin z<= a and b; end dataflow; xor2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end xor2; architecture dataflow of xor2 is begin z<= a xor b; end dataflow; not1 component source code:

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is Port ( a : in std_logic; z : out std_logic); end not1; architecture dataflow of not1 is begin z<= not a; end dataflow;

Simulation output:

42

43

RESULT Thus the half subtractor is designed using VHDL code and obtained its simulated.

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EXP NO:04

DATE:

DEGIN OF FULL SUBTRACTOR

AIM To develop the VHDL code for full subtractor and obtain the simulation VHDL CODE Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsub_dataflow is Port ( a : in std_logic; b : in std_logic; c : in std_logic; diff : out std_logic; brrw : out std_logic); end fsub_dataflow; architecture dataflow of fsub_dataflow is signal a1:std_logic; begin a1<= not a ; diff<= a xor b xor c; brrw<= (a1 and b) or (a1 and c) or (b and c); end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsub_be is Port ( a : in std_logic; b : in std_logic; c : in std_logic; diff : out std_logic; brrw : out std_logic); end fsub_be; architecture behavioral of fsub_be is signal a1:std_logic; begin p1: process(a,b,c) begin a1<= not a ; diff<= a xor b xor c; brrw<= (a1 and b) or (a1 and c) or (b and c); end process p1; end behavioral;

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Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsubstructural is Port ( a : in std_logic; b : in std_logic; c : in std_logic; diff : out std_logic; brrw: out std_logic); end fsubstructural; architecture structural of fsubstructural is component xor3 port(a,b,c:in std_logic; z:out std_logic); end component; component and2 port(a,b:in std_logic; z:out std_logic); end component; component not1 port(a:in std_logic; z:out std_logic); end component; component or3 port(a,b,c:in std_logic; z:out std_logic); end component; signal a1,p,q,r: std_logic; begin x1: xor3 port map (a,b,c, diff); y1: not1 port map(a,a1); z1: and2 port map (a1,b,p); z2: and2 port map (a1,c,q); z3: and2 port map (b,c,r); w1: or3 port map (p,q,r, brrw); end structural; and2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end and2; architecture dataflow of and2 is begin z<= a and b; end dataflow;

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xor3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end xor3; architecture dataflow of xor3 is begin z<= a xor b xor c; end dataflow; or3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end or3; architecture dataflow of or3 is begin z<= a or b or c; end dataflow; not1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is Port ( a : in std_logic; z : out std_logic); end not1; architecture dataflow of not1 is begin z<= not a; end dataflow;

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Simulation output:

48

49

RESULT Thus the full subtractor is designed using VHDL code and obtained its simulated.

EXP NO:05

DATE:

DEGIN OF FULL ADDER USING HALF ADDER

AIM To develop the vhdl code for full adder using half adder and obtain the simulation VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full_half_add is Port ( ha : in std_logic; hb : in std_logic; hc : in std_logic; hsum : out std_logic; hcarry : out std_logic); end full_half_add; architecture full_half_add_st of full_half_add is component or2 port(a,b:in std_logic; z:out std_logic); end component; component hadd port(a,b:in std_logic; sum,carry:out std_logic); end component; signal a1,hc1,hc2 : std_logic; begin H1: hadd port map(ha,hb,a1,hc1); H2: hadd port map(a1,hc,hsum,hc2); H3: or2 port map(hc1,hc2,hcarry); end full_half_add_st;

or2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

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use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end or2; architecture dataflow of or2 is begin z<= a or b; end dataflow; hadd component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hadd is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end hadd; architecture dataflow of hadd is begin sum <= a xor b; carry <= a and b; end dataflow;

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Simulation output:

52

53

RESULT Thus the full adder using half adder is designed using VHDL code and obtained its simulated.

EXP NO: 06

DATE:

DEGIN OF 4:1 MULTIPLEXER

AIM To develop the VHDL source code for 4: 1 multiplexer and obtain the simulation.

VHDL CODE Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_struct is Port ( d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic); end mux_struct; architecture structural of mux_struct is component not1 port(a:in std_logic; z:out std_logic); end component; component and3 port(a,b,c:in std_logic; z:out std_logic); end component; component or4

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port(a,b,c,d:in std_logic; z:out std_logic); end component; signal s0bar,s1bar,p,q,r,st:std_logic; begin n1:not1 port map (s(0),s0bar); n2:not1 port map (s(1),s1bar); a1:and3 port map (d(0),s0bar,s1bar,p); a2:and3 port map (d(1),s0bar,s(1),q); a3:and3 port map (d(2),s(0),s1bar,r); a4:and3 port map (d(3),s(0),s(1),st); o1:or4 port map (p,q,r,st,y); end structural; and3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end and3; architecture dataflow of and3 is begin z<=a and b and c; end dataflow; not1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is Port ( a : in std_logic; z : out std_logic); end not1; architecture dataflow of not1 is begin z<= not a; end dataflow; or4 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or4 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic);

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end or4; architecture dataflow of or4 is begin z<=a or b or c or d; end dataflow;

Simulation output:

56

Synthesis RTL Schematic:

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58

RESULT Thus the 4: 1 multipliexer r is designed using VHDL code and obtained its simulated.

EXP NO: 07

DATE:

DEGIN OF 1:4 DEMULTIPLEXER

AIM To develop the VHDL source code for 1:4 demultiplexer and obtain the simulation.

VHDL CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux_behv is Port ( d : in std_logic; s : in std_logic_vector(1 downto 0);

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z : out std_logic_vector(3 downto 0)); end demux_behv; architecture Behavioral of demux_behv is begin p1:process(d,s) begin if (s(0)<='0' and s(1)<='0') then z(0)<=d; z(1)<='Z'; z(2)<='Z'; z(3)<='Z'; elsif (s(0)<='0' and s(1)<='1') then z(0)<='Z'; z(1)<=d; z(2)<='Z'; z(3)<='Z'; elsif (s(0)<='1' and s(1)<='0') then z(0)<='Z'; z(1)<='Z'; z(2)<=d; z(3)<='Z'; else z(0)<='Z'; z(1)<='Z'; z(2)<='Z'; z(3)<=d; end if; end process p1; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux1 is Port ( Din : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (0 to 3)); end demux1; architecture Behavioral of demux1 is begin with s select y<= Din &"000"when "00", '0'& Din&"00"when "01", "00"& Din&'0' when "10", "000"&Din when others; end Behavioral;

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Simulation output:

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Synthesis RTL Schematic:

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63

RESULT Thus the 1: 4 demultipliexer is designed using VHDL code and obtained its simulated

EXP NO: 08

DATE:

DEGIN OF 2:4 DECODERS

AIM

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To develop the VHDL source code for 2:4 decoders and obtain the simulation.

VHDL CODE

Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder_dataflow is Port ( a : in std_logic; b : in std_logic; e : in std_logic; z : out std_logic_vector(3 downto 0)); end decoder_dataflow; architecture dataflow of decoder_dataflow is signal abar,bbar:std_logic; begin abar<= not a; bbar<= not b; z(0)<= not (abar and bbar and e); z(1)<= not (abar and b and e); z(2)<= not (a and bbar and e); z(3)<= not (a and b and e); end dataflow;

Simulation output:

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66

Synthesis RTL Schematic:

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RESULT Thus the 2: 4 Decoder is designed using VHDL code and obtained its simulated

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EXP NO: 09

DATE:

DEGIN OF 4:2 ENCODER

AIM To develop the VHDL source code for 2:4 decoders and obtain the simulation.

VHDL CODE Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder_struct is Port ( d : in std_logic_vector(7 downto 0); z : out std_logic_vector(2 downto 0)); end encoder_struct; architecture structural of encoder_struct is component or4 port(a,b,c,d:in std_logic; z:out std_logic); end component; begin o1:or4 port map (d(4),d(5),d(6),d(7),z(0)); o2:or4 port map (d(2),d(3),d(6),d(7),z(1)); o3:or4 port map (d(1),d(3),d(5),d(7),z(2)); end structural; or4 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or4 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic); end or4; architecture dataflow of or4 is begin z<=a or b or c or d; end dataflow;

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Simulation output:

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Synthesis RTL Schematic:

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72

RESULT Thus the 4: 2 Encoder is designed using VHDL code and obtained its simulated

EXP NO: 10

DATE:

DEGIN OF FLIP FLOPS

AIM To develop the VHDL source code for a. RS flip flop b. JK flip flop c. D flip flop d. T flip flop and obtain the simulation. RS FLIPFLOP: VHDL CODE library ieee,work; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rsflipflop is port (r,s:in std_logic; q,qbar:inout std_logic); end rsflipflop; architecture rs of rsflipflop is component nand2 port (a,b:in std_logic; c:out std_logic); end component; begin x1:nand2 port map(r,qbar,q); x2:nand2 port map(s,q,qbar) ; end rs; nand2 as component library ieee,work; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nand2 is port (a,b:in std_logic; c:out std_logic); end nand2;

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architecture dataflow of nand2 is begin c <= a nand b; end dataflow;

Simulation output:

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JK FLIPFLOP: VHDL CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff is Port ( j : in std_logic; k : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end jkff; architecture Behavioral of jkff is begin process(j,k,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (j='0' and k='0') then q<=q; qbar<=qbar; elsif (j='0' and k='1') then q<='0'; qbar<='1'; elsif (j='1' and k='0') then q<='1'; qbar<='0'; else q<=not q; qbar<=not qbar;

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end if; end if; end process; end Behavioral;

Simulation output:

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Synthesis RTL Schematic:

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D FLIPFLOP: VHDL CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end dff; architecture Behavioral of dff is begin process(d,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (d='0') then q<='0'; qbar<='1'; else q<='1'; qbar<='0'; end if;

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end if; end process; end Behavioral;

Simulation output:

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Synthesis RTL Schematic:

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81

RESULT Thus the RS, JK and D Flip Flops are designed and simulated the VHDL code.

EXP NO: 11

DATE:

SHIFT REGISTERS
AIM To develop the VHDL source code for shift register and obtain the simulation.

SERIAL-IN SERIAL-OUT SHIFT REGISTER: VHDL CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity siso is

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Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : out std_logic); end siso; architecture Behavioral of siso is signal x:std_logic_vector(7 downto 0); begin process(d,clk,rst) begin if (rst='1') then q<='X'; elsif (clk='1' and clk'event) then x(0)<=d; x(1)<=x(0); x(2)<=x(1); x(3)<=x(2); x(4)<=x(3); x(5)<=x(4); x(6)<=x(5); x(7)<=x(6); q<=x(7); end if; end process; end Behavioral;

Simulation output:

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Synthesis RTL Schematic:

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SERIAL IN PARALLEL OUT SHIFT REGISTER: VHDL CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sipo is Port ( d : in std_logic; clk : in std_logic;

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rst : in std_logic; q : inout std_logic_vector(7 downto 0)); end sipo; architecture Behavioral of sipo is begin process(d,clk,rst) begin if (rst='1') then q<="ZZZZZZZZ"; elsif (clk='1' and clk'event) then q(0)<=d; q(1)<=q(0); q(2)<=q(1); q(3)<=q(2); q(4)<=q(3); q(5)<=q(4); q(6)<=q(5); q(7)<=q(6); end if; end process; end Behavioral;

Simulation output:

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Synthesis RTL Schematic:

87

88

PARALLEL-IN PARELLEL-OUT SHIFT REGISTER: VHDL CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pipo is Port ( d : in std_logic_vector(7 downto 0); clk : in std_logic; rst : in std_logic; q : out std_logic_vector(7 downto 0)); end pipo; architecture Behavioral of pipo is begin process(d,clk,rst) begin if (rst='1') then q<="ZZZZZZZZ"; elsif (clk='1' and clk'event) then q(0)<=d(0); q(1)<=d(1); q(2)<=d(2); q(3)<=d(3); q(4)<=d(4); q(5)<=d(5); q(6)<=d(6); q(7)<=d(7); end if; end process; end Behavioral;

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Simulation output:

90

Synthesis RTL Schematic:

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PARALLEL-IN SERIAL-OUT SHIFT REGISTER: VHDL CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity piso is Port ( d : in std_logic_vector(7 downto 0); clk : in std_logic; rst : in std_logic; load : in std_logic; q : out std_logic); end piso; architecture Behavioral of piso is begin process(d,clk,rst,load) variable x:std_logic_vector(7 downto 0); begin if (clk='1' and clk'event) then if (rst='1') then q<='Z'; else if (load='0') then x:=d; else q<=x(0); x(0):=x(1); x(1):=x(2); x(2):=x(3); x(3):=x(4); x(4):=x(5); x(5):=x(6); x(6):=x(7); x(7):='Z'; end if; end if; end if; end process; end Behavioral;

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Simulation output:

93

RTL Schematic:

94

95

RESULT Thus the OUTPUTs of 8-bit shift register are verified and simulating the VHDL code.

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