ECP2036 Microprocessors System and Interfacing

Chapter 3: The 8051 Instruction Set

3.1

ADDRESSING MODES

The 8051 instructions use eight addressing modes. These are: 1. Register 2. Direct 3. Indirect 4. Immediate 5. Relative 6. Absolute 7. Long 8. Indexed

1. Register Addressing In this mode the data, which the instruction operates on, is in one of eight registers labeled R0 to R7 (Rn, in general). These registers are to be found in one of four register banks, only one of which can be active at any one time. The active bank may be selected by using bit 3 and bit 4 of the PSW (rs0 & rs1). On power-up or reset, the default register bank is bank 0. The format of an instruction using register addressing: Op code n

For example, to logically OR the contents of accumulator A with that of register R3, the following instruction is used: ORL A, R3 and the op-code is 01001011B. The upper five bits, 01001, indicate the instruction, and the lower three bits, 011, the register.

2. Direct Addressing Instructions using direct addressing consists of two bytes: op-code and address. Op code Direct address

Such instructions can access any on-chip variable or hardware register. Note that the most significant bit of the direct address determines which area in the on-chip is to be accessed. An address between 00H and 7FH accesses a location in the low-order on-chip RAM. Any address with bit 7 = 1 refers to one of the special function registers. It is not necessary to remember the addresses of these special function registers. The assembler usually understands and converts the mnemonic of a special function register, e.g. P2 for Port 2, into the appropriate address. An example of a direct addressing instruction is MOV P1, A which transfer the content of the accumulator to Port 1. The direct address of Port 1 (90H) is determined by the assembler and inserted as byte 2 of the instruction. The source of the data, the accumulator, is specified implicitly in the op-code. The complete encoding of this instruction is 10001001 10010000

3. Indirect Addressing In this mode of addressing the instruction performs an operation on the data whose address is contained in register R0 or R1. Instructions using indirect addressing are single byte instructions. In 8051 assembly language the symbol @ before R0 or R1 denotes indirect addressing. An example of an indirect addressing instruction is SUBB A, @R0 This instruction performs the operation: (A) (A) (C) ((R0)).

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ECP2036 Microprocessors System and Interfacing

Chapter 3: The 8051 Instruction Set

4. Immediate Addressing In an instruction that uses immediate addressing, the operand of the instruction is given as the byte that follows the op-code. The operand may be a numeric constant, a symbolic variable, or an arithmetic expression using constants, symbols, and operators. In assembly language we use the symbol # before an operand to denote immediate addressing. An example of an instruction using immediate addressing is ANL A, #77 which performs the operation: (A) (A) #77.

5. Relative Addressing Sometimes this is also called program counter relative addressing. This addressing mode is used only with certain jump instructions. A relative address (or offset) is an 8-bit signed value, which is added to the program counter to form the address of the next instruction executed. The range for such a jump instruction is 128 to +127 locations. Although the range is rather limited, relative addressing does offers the advantage of providing position-independent code (since absolute addresses are not used). For example, the instruction JZ rel performs the following operations: (PC) (PC) + 2 IF (A) = 0 THEN (PC) (PC) + rel ELSE continue The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice.

6. Absolute Addressing There are only two instructions that use this addressing: ACALL (absolute call) and AJMP (absolute jump). These instructions perform branching within the current 2K page of program memory. The branch address is obtained by successively concatenating the five high-order bits of the program counter, bits 5 7 of the op-code, and the second byte of the instruction. The diagram illustrate how this is done: Incremented PC: A 15 A 14 A 13 A 12 A 11 x x x x x x x x x x x Instruction 2nd byte A7 A6 A5 A4 A3 A2 A1 A0

Instruction op code A 10 A 9 A 8 -

Branch address: A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0

Note that the branch destination address is within the same 2K page of program memory because the highest most five address bits are the same as those in the program counter before the branch is taken.

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ECP2036 Microprocessors System and Interfacing

Chapter 3: The 8051 Instruction Set

7. Long Addressing Only two instructions use this addressing mode. These instructions are LCALL addr16 and LJMP addr16. Both of these are three byte instructions with the op-code being the first byte and the following two bytes are the address high-byte and address low-byte respectively. These instructions enable the program to branch to anywhere within the full 64 K-bytes of program memory address space.

8. Indexed Addressing In this mode the 16-bit address in a base register is added to a positive offset to form an effective address for the jump indirect instruction JMP @A+DPTR, and the two move code byte instructions MOVC A,@A+DPTR and MOVC A,@A+PC. The base register in the jump instruction is the data pointer and the positive offset is held in the accumulator. For the move instructions the base register can either be the data pointer or the program counter, and again the positive offset is in the accumulator. The operations of these three instructions are as follows: JMP @A+DPTR MOVC A,@A+DPTR MOVC A,@A+PC (PC) (A) +(DPTR) (A) ((A) + (DPTR)) (PC) (PC) + 1 (A) ((A) + (PC))

3.2

INSTRUCTION TYPES

The 8051 instructions are divided among five functional groups: 1. Arithmetic 2. Logical 3. Data transfer 4. Boolean variable 5. Program branching

1. Arithmetic Instructions With the arithmetic instructions four addressing modes may be used. These modes are direct, indirect, register and immediate. For instance the add-with-carry instruction ADDC A, operand2 has the following four forms:

Instruction ADDC ADDC ADDC ADDC A, Rn A, direct A, @Ri A, #data

Operation Add register to accumulator with carry Add direct byte to accumulator with carry Add indirect RAM to accumulator with carry Add immediate data to accumulator with carry

Comments Rn = register R0 to R7 from currently selected register bank. Direct = 8-bit internal datas location address. @Ri = 8-bit internal data RAM location addressed indirectly through R0 or R1. #data = 8-bit constant included in the instruction.

Most of the arithmetic instructions execute in twelve oscillator clock periods with the following three exceptions: Instruction INC MUL DIV DPTR AB AB Operation Increment data pointer Multiply A and B Divide A by B Oscillator periods 24 48 48

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ECP2036 Microprocessors System and Interfacing

Chapter 3: The 8051 Instruction Set

2. Logical Instructions The logical instructions can perform Boolean operations on the data contained either in the accumulator or in an internal RAM location. Those logical instructions that use the accumulator as one of the operands have the same addressing modes as those found in arithmetic instruction. Examples of such instructions are:

Instruction ORL ORL ORL ORL A, Rn A, direct A, @Ri A, #data

Operation OR register to accumulator OR direct byte to accumulator OR indirect RAM to accumulator OR immediate data to accumulator

Comments Rn = register R0 to R7 from currently selected register bank. Direct = 8-bit internal datas location address. @Ri = 8-bit internal data RAM location addressed indirectly through R0 or R1. #data = 8-bit constant included in the instruction.

Note that in addition to the ORL A, direct instruction we also have the equivalent mirror instruction ORL direct, A (OR the accumulator to the direct byte). All such instructions execute in twelve oscillator clock periods. Apart from the logical instructions that use the accumulator as one of the operands, there are three logical instructions that perform Boolean operations directly on any byte in the internal data memory without going through the accumulator. The table below gives a summary of these instructions.

Instruction ANL direct, #data ORL direct, #data XRL direct, #data

Operation AND immediate data to direct byte Or immediate data to direct byte Exclusive OR immediate data to direct byte

Comments Example: ANL P2,#0FFH Example: ORL P2,#0FFH Example: XRL P2,#0FFH

These three instructions take 24-oscillator clock period to execute. Note that these instructions perform what is known as read-modify-write operation. In a read-modify-write instruction the datum in the direct address location is first read, then the logical operation is performed on the read datum with the immediate byte, and finally the result of the logical operation is written back to the direct address location. The logical group of instructions also contains four rotate instructions, which operate on the contents of the accumulator, and a swap instruction (SWAP A). The swap instruction is useful in BCD arithmetic manipulations.

3. Data Transfer Instructions This group contains the largest number of instructions that enable us to move data within the internal RAM, move data between the internal RAM and external RAM, and three instructions that allow us to manipulate look-up tables. The following table contains some examples of data transfer instructions. Note that the stack in the 8051 is implemented in the on-chip RAM. Unlike the stack implementations in other microprocessors the stack grows upwards in memory, i.e. towards higher memory addresses. The execution of the PUSH instruction first increments the stack pointer, and then copies the indicated byte into the stack.

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Chapter 3: The 8051 Instruction Set

Instruction MOV A, Rn MOV direct, A MOV Rn, #data MOV @Ri, A MOV direct, @Ri MOV DPTR, #data16 MOVX @DPTR, A MOVC A, @A+PC PUSH direct

Operation Move register to accumulator Move accumulator to direct byte Move immediate data to register Move accumulator to indirect RAM Move from indirect RAM to direct byte Load data pointer with a 16-bit constant Move accumulator to external RAM Move Code byte relative to PC to ACC Push direct byte into stack

Comments Register addressing. Direct addressing. Immediate addressing. Indirect addressing. Move to internal RAM. Indirect addressing. Move from external RAM to internal RAM. Immediate address. Indirect addressing. Index addressing. Direct addressing. Stack itself is accessed using indirect addressing through the stack pointer. Indirect addressing.

XCH A, @Ri

Exchange indirect RAM with accumulator

Caution: For any system using the 8051/8031 do not allow the stack pointer to increment beyond 7FH. This is because the upper 128 bytes of internal RAM are not implemented in the 8051/8031. If the stack pointer advances beyond 7FH and any data saved onto the stack will be lost. The data transfer instructions generally execute in either 12 oscillator clock periods or 24 oscillator clock periods.

4. Boolean Instructions The 8051 has a range of Boolean variable manipulating instructions which enable us to set or reset individual bits within some of the locations in the internal RAM, and some of the special function registers. We give some examples of these instructions in the table below. Instruction CLR C CLR bit SETB C CPL bit ANL C, bit ORL C, bit MOV bit, C Operation Clear Carry bit Clear direct bit Set Carry Complement direct bit AND complement of direct bit to Carry OR direct bit to Carry Move Carry to direct bit Oscillator period 12 12 12 12 24 24 24

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ECP2036 Microprocessors System and Interfacing

Chapter 3: The 8051 Instruction Set

5. Program branching Instructions This group contains conditional and unconditional branch instructions. Some of the conditional branch instructions which test individual bits such as JC rel (jump if Carry is set) are found in the previous instruction group. The following is a list of some of the program branch instructions.

Instruction ACALL LCALL RETI SJMP rel JMP @A+DPTR addr11 addr16

Operation Absolute subroutine call Long subroutine call Return from interrupt Short jump Jump indirect relative to the data pointer Compare the immediate data to the accumulator and jump if not equal Compare immediate data to indirect and jump if not equal Decrement register and jump if not zero Decrement the direct byte and jump if not Zero Jump if Carry is not set Jump if direct bit is set and clear bit

Comments Absolute addressing Long addressing. Call to subroutine in external memory.

Relative addressing. Indexed addressing. Compare immediate Jump relative As above Register and relative addressing. As above

CJNE A, # data,rel

CJNE @Ri, # data,rel DJNZ Rn, rel DJNZ direct, rel

JNC JBC

rel bit, rel

Jump relative addressing As above

!!! Please refer to the 8051-instruction set for further details.

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