1.

Model a simple AND gate using dataflow modeling.

entity andgate is port(x,y: in bit; z: out bit); end entity; architecture and_gate of andgate is begin z <= x and y; end and_gate;

entity andtest is end entity; architecture and_test of andtest is component andgate is port(x,y: in bit; z: out bit); end component; signal tx,ty,tz : bit; begin inst: andgate port map (tx,ty,tz); process begin tx<='0'; ty<='0'; wait for 10 ns; tx<='0'; ty<='1'; wait for 10 ns; tx<='1'; ty<='0'; wait for 10 ns; tx<='1'; ty<='1'; wait for 10 ns; end process; end and_test;

2. Model a 1-bit Full Adder using data flow modeling. Use this to build an 8-bit ripple carry adder using structural modeling.
entity fa1bit is port (x,y,cin: in bit; s,cout: out bit); end entity; architecture fa_1bit of fa1bit is begin s<= x xor y xor cin; cout<= (x and y) or (x and cin) or(y and cin); end fa_1bit; entity fa8bit is port(in1,in2: in bit_vector(7 downto 0); cin: in bit; s: out bit_vector(7 downto 0); cout: out bit); end entity; architecture fa_8bit of fa8bit is component fa1bit is port (x,y,cin: in bit; s,cout: out bit); end component; signal tcin: bit_vector( 6 downto 0); begin instf: fa1bit port map(in1(0),in2(0),cin,s(0),tcin(0)); loopl: for i in 1 to 6 generate instfl: fa1bit port map(in1(i),in2(i),tcin(i-1),s(i),tcin(i)); end generate; instf2: fa1bit port map(in1(7),in2(7),tcin(6),s(7),cout); end fa_8bit; entity testfa is end entity; architecture test_fa of testfa is component fa8bit is port(in1,in2: in bit_vector(7 downto 0); cin: in bit; s: out bit_vector(7 downto 0); cout: out bit);

end component; signal tin1,tin2,ts: bit_vector(7 downto 0); signal tcin,tcout: bit; begin inst: fa8bit port map(tin1,tin2,tcin,ts,tcout); process begin tin1<="10100101"; tin2<="00111100"; tcin<='1'; wait for 10 ns; tin1<="11100101"; tin2<="01111100"; tcin<='1'; wait for 10 ns; tin1<="10110101"; tin2<="10111010"; tcin<='0'; wait for 10 ns; end process; end test_fa;

3. Implement a 4-bit adder using '+' operator for std_logic_vector data types. Use this to build a 1 digit BCD Adder.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bcd is port( x,y: in std_logic_vector(3 downto 0); z: out std_logic_vector(4 downto 0)); end bcd; architecture arch_bcd of bcd is signal a: std_logic; signal s: std_logic_vector(4 downto 0); begin s<= ('0' & x) + y; a<='1' when s > 9 else '0'; z<=s when a='0' else s+6; end arch_bcd; entity test is end entity; architecture arch of test is component bcd is port( x,y: in std_logic_vector(3 downto 0); z: out std_logic_vector(4 downto 0)); end component; signal tx,ty: std_logic_vector(3 downto 0); signal tz: std_logic_vector(4 downto 0); begin inst: bcd port map (tx,ty,tz); process begin tx<="0111"; ty<="0110"; wait for 20 ns; tx<="1001"; ty<="1001"; wait for 20 ns; end process; end arch;

4.

Implement an array multiplier to multiply two 8-bit numbers.

entity arraymul is port( m,q: in bit_vector(7 downto 0); z: out bit_vector(15 downto 0)); end entity; architecture arch of arraymul is component toprowunit is port(mn,mo,q0,q1,cin: in bit; pp1,cout: out bit); end component; component other is port(pp,m: in bit_vector(7 downto 0); q: in bit; op: out bit_vector(7 downto 0); z: out bit); end component; signal cin: bit_vector(6 downto 0); signal pp1,pp2,pp3,pp4,pp5,pp6: bit_vector(7 downto 0); begin z(0)<= m(0) and q(0); top1: toprowunit port map (m(1),m(0),q(0),q(1),'0',z(1),cin(0)); toploop: for i in 2 to 7 generate topi: toprowunit port map (m(i),m(i-1),q(0),q(1),cin(i-2),pp1(i2),cin(i-1)); end generate; top8: toprowunit port map ('0',m(7),q(0),q(1),cin(6),pp1(6),pp1(7)); row1: other row2: other row3: other row4: other row5: other row7: other end arch; port port port port port port map map map map map map (pp1,m,q(2),pp2,z(2)); (pp2,m,q(3),pp3,z(3)); (pp3,m,q(4),pp4,z(4)); (pp4,m,q(5),pp5,z(5)); (pp5,m,q(6),pp6,z(6)); (pp6,m,q(7),z(15 downto 8),z(7));

entity fa1bit is port (x,y,cin: in bit; s,cout: out bit); end entity; architecture fa_1bit of fa1bit is

begin s<= x xor y xor cin; cout<= (x and y) or (x and cin) or(y and cin); end fa_1bit; entity toprowunit is port(mn,mo,q0,q1,cin: in bit; pp1,cout: out bit); end entity; architecture arch of toprowunit is component fa1bit is port (x,y,cin: in bit; s,cout: out bit); end component; signal fax,fay: bit; begin fax<= mn and q0; fay<= mo and q1; inst: fa1bit port map (fax,fay,cin,pp1,cout); end arch; entity otherrowunit is port(ppi,qj,m,cin: in bit; op,cout: out bit); end entity; architecture arch of otherrowunit is component fa1bit is port (x,y,cin: in bit; s,cout: out bit); end component; signal fay: bit; begin fay<= qj and m; inst: fa1bit port map (ppi,fay,cin,op,cout); end arch; entity other is port(pp,m: in bit_vector(7 downto 0); q: in bit; op: out bit_vector(7 downto 0); z: out bit);

end entity; architecture arch of other is component otherrowunit is port(ppi,qj,m,cin: in bit; op,cout: out bit); end component; signal cin: bit_vector(6 downto 0); begin other1: otherrowunit port map (pp(0),q,m(0),'0',z,cin(0)); otherloop: for i in 1 to 6 generate otheri: otherrowunit port map (pp(i),q,m(i),cin(i-1),op(i1),cin(i)); end generate; other8: otherrowunit port map (pp(7),q,m(7),cin(6),op(6),op(7)); end arch; entity test is end entity; architecture arch of test is component arraymul is port( m,q: in bit_vector(7 downto 0); z: out bit_vector(15 downto 0)); end component; signal m,q: bit_vector(7 downto 0); signal z: bit_vector(15 downto 0); begin inst: arraymul port map (m,q,z); process begin m <= "00000010"; q<= "00000011"; wait for 20 ns; m<= "00000100"; q<="00000010"; wait for 20 ns; end process; end arch;

5. Implement a 2-to-4 Decoder using conditional signal statement assignment statement with enable facilty. Use it to construct 4-to-16 Decoder.
library ieee; use ieee.std_logic_1164.all; entity dec2_4 is port(ip: in std_logic_vector(1 downto 0); en: in std_logic; op: out std_logic_vector(3 downto 0)); end entity; architecture arch of dec2_4 is begin with en & ip select op<= "0001" when "100", "0010" when "101", "0100" when "110", "1000" when "111", "0000" when others; end arch; entity dec4_16 is port(ip: in std_logic_vector(3 downto 0); en: in std_logic; op: out std_logic_vector(15 downto 0)); end entity; architecture arch of dec4_16 is component dec2_4 is port(ip: in std_logic_vector(1 downto 0); en: in std_logic; op: out std_logic_vector(3 downto 0)); end component; signal dop: std_logic_vector(3 downto 0); begin inst1: dec2_4 port map (ip(1 downto 0),dop(0),op(3 downto 0)); inst2: dec2_4 port map (ip(1 downto 0),dop(1),op(7 downto 4)); inst3: dec2_4 port map (ip(1 downto 0),dop(2),op(11 downto 8)); inst4: dec2_4 port map (ip(1 downto 0),dop(3),op(15 downto 12)); inst5: dec2_4 port map (ip(3 downto 2),en,dop(3 downto 0)); end arch; entity test is end entity;

architecture arch of test is component dec4_16 is port(ip: in std_logic_vector(3 downto 0); en: in std_logic; op: out std_logic_vector(15 downto 0)); end component; signal tip: std_logic_vector(3 downto 0); signal ten: std_logic; signal top: std_logic_vector(15 downto 0); begin inst: dec4_16 port map (tip,ten,top); process begin tip<="0101"; wait for 10 ns; ten<='1'; wait for 5 ns; ten<='0'; wait for 5 ns; tip<="0010"; wait for 10 ns; ten<='1'; wait for 10 ns; end process; end arch;

6. Implement a 1-bit comparator having 5 inputs (two 1-bit inputs being compared and three 1-bit comaprison result bits of previous stage) and 3 outputs(eq, lt,gt). Connect 8 such units to model an 8-bit comparator using generate statement. The 3 outputs of a stage go to next stage as its inputs.

entity onebit is port (x,y,pxly,pxey,pxgy: in bit; lt,eq,gt: out bit); end entity; architecture arch of onebit is begin lt<='1' when (((x='0') and (y='1')) or (((x xor y)='0') and (pxly='1'))) else '0'; eq<='1' when (((x xor y)='0') and pxey='1') else '0'; gt<='1' when (((x='1') and (y='0')) or (((x xor y)='0') and (pxgy='1'))) else '0'; end arch; entity bit8 is port (x,y: in bit_vector (7 downto 0); lt,eq,gt: out bit); end entity; architecture arch of bit8 is component onebit is port (x,y,pxly,pxey,pxgy: in bit; lt,eq,gt: out bit); end component; signal tlt,teq,tgt: bit_vector(6 downto 0); begin inst1: onebit port map(x(0),y(0),'0','1','0',tlt(0),teq(0),tgt(0)); loop1: for i in 1 to 6 generate inst2: onebit port map (x(i),y(i),tlt(i-1),teq(i-1),tgt(i1),tlt(i),teq(i),tgt(i)); end generate; inst3: onebit port map (x(7),y(7),tlt(6),teq(6),tgt(6),lt,eq,gt); end arch; entity test is end entity;

architecture arch of test is component bit8 is port (x,y: in bit_vector (7 downto 0); lt,eq,gt: out bit); end component; signal x,y: bit_vector (7 downto 0); signal lt,eq,gt: bit; begin inst: bit8 port map (x,y,lt,eq,gt); process begin x<="00001010"; y<="00000011"; wait for 20 ns; y<="11000011"; x<="00111100"; wait for 20 ns; x<="01010101"; y<="01010101"; wait for 20 ns; end process; end arch;

7. Model a 4-to-1 multiplexor using Selected Signal Assignment statement. Use it to build 16-to-1 multiplexor.

entity mux4x1 is port(inp: in bit_vector(3 downto 0); sel: in bit_vector(1 downto 0); op:out bit); end entity; architecture mux_4x1 of mux4x1 is begin with sel select op<= inp(0) when "00", inp(1) when "01", inp(2) when "10", inp(3) when "11"; end mux_4x1;

entity mux16x1 is port(inp: in bit_vector(15 downto 0); sel: in bit_vector(3 downto 0); f:out bit); end entity; architecture arch of mux16x1 is component mux4x1 is port(inp: in bit_vector(3 downto 0); sel: in bit_vector(1 downto 0); op:out bit); end component; signal tmo: bit_vector(3 downto 0); begin inst1: mux4x1 inst2: mux4x1 inst3: mux4x1 inst4: mux4x1 inst5: mux4x1 end arch; entity test is end entity;

port port port port port

map(inp(15 downto 12),sel(1 downto 0),tmo(3)); map(inp(11 downto 8),sel(1 downto 0),tmo(2)); map(inp(7 downto 4),sel(1 downto 0),tmo(1)); map(inp(3 downto 0),sel(1 downto 0),tmo(0)); map(tmo,sel(3 downto 2),f);

architecture arch of test is component mux16x1 is port(inp: in bit_vector(15 downto 0); sel: in bit_vector(3 downto 0); f:out bit); end component; signal inp: bit_vector(15 downto 0); signal sel: bit_vector(3 downto 0); signal f: bit; begin inst: mux16x1 port map (inp,sel,f); process begin inp<="0000101010101100"; sel<="0011"; wait for 20 ns; sel<="0101"; wait for 20 ns; sel<="1111"; wait for 20 ns; end process; end arch;

8. Implement an 8-bit Arithmetic Logic Unit to perform basic arithmetic(add, subtract, incerment, decrement) and logic(OR, AND, XOR, NOT) operations using structural modeling that uses a component of 1 bit Full Adder and Multiplexer.

entity mux4x1 is port(inp: in bit_vector(3 downto 0); sel: in bit_vector(1 downto 0); op:out bit); end entity; architecture mux_4x1 of mux4x1 is begin with sel select op<= inp(0) when "00", inp(1) when "01", inp(2) when "10", inp(3) when "11"; end mux_4x1;

entity fa1bit is port (x,y,cin: in bit; s,cout: out bit); end entity; architecture fa_1bit of fa1bit is begin s<= x xor y xor cin; cout<= (x and y) or (x and cin) or(y and cin); end fa_1bit; entity au1bit is port (a,b,cin: in bit; sel: in bit_vector(1 downto 0); s,cout: out bit); end entity; architecture au_1bit of au1bit is component fa1bit is port (x,y,cin: in bit; s,cout: out bit); end component; component mux4x1 is port(inp: in bit_vector(3 downto 0);

sel: in bit_vector(1 downto 0); op:out bit); end component; signal mi: bit_vector(3 downto 0); signal mo: bit; begin mi<='1' & '0' & (not b) & b ; inst1: fa1bit port map (a,mo,cin,s,cout); inst2: mux4x1 port map (mi,sel,mo); end au_1bit; entity airthmetic is port( inp1,inp2 : in bit_vector(7 downto 0); sel : in bit_vector(1 downto 0); cin : in bit; op : out bit_vector(7 downto 0); cout: out bit); end entity; architecture air of airthmetic is component au1bit is port (a,b,cin: in bit; sel: in bit_vector(1 downto 0); s,cout: out bit); end component; signal tcin: bit_vector(7 downto 0); begin inst1: au1bit port map(inp1(0),inp2(0),cin,sel,op(0),tcin(0)); loop1: for i in 1 to 6 generate inst2: au1bit port map(inp1(i),inp2(i),tcin(i1),sel,op(i),tcin(i)); end generate; inst3: au1bit port map(inp1(7),inp2(7),tcin(6),sel,op(7),cout); end air; entity lu1bit is port(a,b: in bit; sel: in bit_vector(1 downto 0); x: out bit); end entity; architecture arch of lu1bit is component mux4x1 is port(inp: in bit_vector(3 downto 0); sel: in bit_vector(1 downto 0);

op:out bit); end component; signal mi: bit_vector(3 downto 0); begin inst: mux4x1 port map (mi,sel,x); mi <= (not a) & (a xor b) & (a and b) & (a or b) ; end arch; entity lu is port( inp1,inp2 : in bit_vector(7 downto 0); sel : in bit_vector(1 downto 0); op : out bit_vector(7 downto 0)); end entity; architecture arch of lu is component lu1bit is port(a,b: in bit; sel: in bit_vector(1 downto 0); x: out bit); end component; begin loop1: for i in 0 to 7 generate inst: lu1bit port map (inp1(i),inp2(i),sel,op(i)); end generate; end arch; entity alu is port( a,b: in bit_vector(7 downto 0); sel: in bit_vector(2 downto 0); cin: in bit; op: out bit_vector(7 downto 0); cout: out bit); end entity; architecture arch of alu is component airthmetic is port( inp1,inp2 : in bit_vector(7 downto 0); sel : in bit_vector(1 downto 0); cin : in bit; op : out bit_vector(7 downto 0); cout: out bit); end component; component lu is

port( inp1,inp2 : in bit_vector(7 downto 0); sel : in bit_vector(1 downto 0); op : out bit_vector(7 downto 0)); end component; signal top1,top2: bit_vector(7 downto 0); begin inst1: airthmetic port map (a,b,sel(1 downto 0),cin,top1,cout); inst2: lu port map (a,b,sel(1 downto 0),top2); op<= top1 when sel(2)='0' else top2; end arch; entity test is end entity; architecture arch of test is component alu is port( a,b: in bit_vector(7 downto 0); sel: in bit_vector(2 downto 0); cin: in bit; op: out bit_vector(7 downto 0); cout: out bit); end component; signal a,b,op: bit_vector(7 downto 0); signal sel: bit_vector(2 downto 0); signal cin,cout: bit; begin inst: alu port map(a,b,sel,cin,op,cout); process begin a<="00101100"; b<="01011100"; sel<="000"; cin<='0'; wait for 10 ns; sel<="001"; cin<='1'; wait for 10 ns; sel<="010"; cin<='1'; wait for 10 ns; sel<="011"; cin<='0'; wait for 10 ns;

sel<="100"; wait for 10 sel<="101"; wait for 10 sel<="110"; wait for 10 sel<="111"; wait for 10 end process; end arch;

ns; ns; ns; ns;

9. Model a combinational circuit in VHDL that performs shift left or shift right or rotate left or rotate right by 1-bit operations on its input.

entity shift is generic(n: integer:=8); port( inp: in bit_vector(n-1 downto 0); sel: in bit_vector(1 downto 0); op: out bit_vector(n-1 downto 0)); end entity; architecture arch_shift of shift is begin process(sel) begin case sel is when "00"=> op(n-1 downto 0)<= inp(n-2 downto 0)&'0'; when "01"=> op(n-1 downto 0)<= inp(n-1) & inp(n-1 downto 1); op(n-1)<= inp(n-1); when "10"=> op(n-1 downto 0)<= inp(n-2 downto 0)& inp(n-1); when "11"=> op(n-1 downto 0)<= inp(0) & inp(n-1 downto 1); end case; end process; end arch_shift; entity test is end entity; architecture arch of test is component shift is generic(n: integer:=8); port( inp: in bit_vector(n-1 downto 0); sel: in bit_vector(1 downto 0); op: out bit_vector(n-1 downto 0)); end component; signal tinp,top: bit_vector(7 downto 0); signal tsel: bit_vector(1 downto 0); begin inst: shift generic map(n=>8) port map(tinp,tsel,top); process begin tinp <="10110010";

tsel<="01"; wait for 20 ns; tsel<="10"; wait for 20 ns; tsel<="11"; wait for 20 ns; tsel<="00"; wait for 20 ns; tinp <="00110110"; tsel<="01"; wait for 20 ns; tsel<="10"; wait for 20 ns; tsel<="11"; wait for 20 ns; tsel<="00"; wait for 20 ns; end process; end arch;

10. Model an S-r flip flop using structural modeling using programmer defined NAND gates an component.
entity sr is port( s,r,clk: in bit; q1,q2: out bit); end entity; architecture arch of sr is component nand1 is port( x,y: in bit; z: out bit); end component; component nand2 is port( x,y: in bit; z: out bit); end component; signal t1,t2,o1,o2: bit; begin inst1: nand1 inst2: nand1 inst3: nand1 inst4: nand2 q1<=o1; q2<=o2; end arch;

port port port port

map map map map

(s,clk,t1); (r,clk,t2); (t1,o2,o1); (t2,o1,o2);

entity nand1 is port( x,y: in bit; z: out bit); end entity; architecture arch of nand1 is begin z<= x nand y after 1 ns; end arch; entity nand2 is port( x,y: in bit; z: out bit); end entity; architecture arch of nand2 is

begin z<= x nand y after 2 ns; end arch; entity test is end entity; architecture arch of test is component sr is port( s,r,clk: in bit; q1,q2: out bit); end component; signal s,r,clk,q1,q2: bit; begin inst: sr port process begin clk<='0'; wait for 10 clk<= '1'; wait for 10 end process; process begin s<='0'; r<='1'; wait for 15 s<='1'; r<='0'; wait for 20 s<='0'; r<='1'; wait for 20 s<='1'; r<='0'; wait for 20 s<='0'; r<='0'; wait for 20 end process; end arch;

map (s,r,clk,q1,q2);

ns; ns;

ns;

ns;

ns;

ns;

ns;

11. Model an edge triggered D-flip flop with asynchronous reset facility. Use it to model 8bit Parallel-In-Parallel-Out register. Use it to model a Ring Counter(by adding a reset facility).

entity dff is port ( din,clk,reset: in bit; q: out bit); end entity; architecture d_ff of dff is begin process(clk,reset) begin if(reset = '1') then q<= '0'; elsif(clk 'event and clk='1') then q<=din; end if; end process; end d_ff; entity reg8bit is port( ip : in bit_vector (7 downto 0); reset,clk : in bit; op : out bit_vector ( 7 downto 0)); end entity; architecture arch_reg8bit of reg8bit is component dff is port ( din,clk,reset: in bit; q: out bit); end component; begin for1: for i in 0 to 7 generate inst: dff port map(ip(i),clk,reset,op(i)); end generate; end arch_reg8bit; entity testreg is end entity; architecture arch_testreg of testreg is component reg8bit is port( ip : in bit_vector (7 downto 0); reset,clk : in bit; op : out bit_vector ( 7 downto 0));

end component; signal tip,top: bit_vector(7 downto 0); signal treset,tclk: bit; begin inst: reg8bit port map (tip,treset,tclk,top); process begin tclk<= '0'; wait for 10 ns; tclk<= '1'; wait for 10 ns; end process; process begin treset<= '0'; wait for 5 ns; treset<= '1'; wait for 5 ns; treset <='0'; wait for 5 ns; tip<="00110011"; wait for 25 ns; treset<='1'; wait for 3 ns; treset<='0'; end process; end arch_testreg; entity dff_pre is port ( din,clk,preset,reset: in bit; q: out bit); end entity; architecture arch of dff_pre is begin process(clk,reset,preset) begin if(reset = '1') then q<= '0'; elsif(preset='1') then q<='1'; elsif(clk 'event and clk='1') then q<=din; end if; end process; end arch; entity ring is

port(start,clk: in bit; q: buffer bit_vector(0 to 7)); end entity; architecture arch of ring is component dff_pre is port ( din,clk,preset,reset: in bit; q: out bit); end component; begin inst1: dff_pre port map(q(7),clk,start,'0',q(0)); for1: for i in 1 to 7 generate insti: dff_pre port map(q(i-1),clk,'0',start,q(i)); end generate for1; end arch; entity testring is end entity; architecture arch of testring is component ring is port(start,clk: in bit; q: buffer bit_vector(0 to 7)); end component; signal start,clk: bit; signal q: bit_vector(0 to 7); begin inst: ring port map(start, clk, q); process begin clk<= '0'; wait for 10 ns; clk<= '1'; wait for 10 ns; end process; process begin start<='1'; wait for 2 ns; start<='0' ; wait for 80 ns; end process; end arch;

12.

Implement a serial adder using D flip flop and a full adder.

entity serialadder is port (x,y,clk,reset : in bit; sum : out bit); end entity; architecture arch_serialadder of serialadder is type state is (A,B); signal ps: state; signal ns: state; begin process (clk,reset) begin if (reset='1') then ps<= A; elsif(clk 'event and clk='1') then ps<=ns; end if; end process; process(x,y,ps) begin case ps is when A=> if (x='1' and y='1') then ns<= B; else ns<= A; end if; when B=> if (x='0' and y='0') then ns<= A; else ns<= B; end if; end case; if (ps=A) then sum <= x xor y; else sum <= x xor y xor '1'; end if; end process; end arch_serialadder; entity testserialadder is end entity;

architecture arch_testserialadder of testserialadder is component serialadder is port (x,y,clk,reset : in bit; sum : out bit); end component; signal tx,ty,tclk,treset,tsum: bit; begin inst: serialadder port map(tx,ty,tclk,treset,tsum); process begin tclk<= '0'; wait for 10 ns; tclk<= '1'; wait for 10 ns; end process; process begin treset <='1'; wait for 1 ns; treset<= '0'; wait for 1 ns; tx<='1'; ty<='0'; wait for 10 ns; tx<='1'; ty<='1'; wait for 20 ns; tx<= '0'; ty<= '1'; wait for 20 ns; treset <='1'; wait for 1 ns; treset<= '0'; wait for 1 ns; tx<= '1'; ty<= '1'; wait for 20 ns; tx<= '1'; ty<= '1'; wait for 20 ns; end process; end arch_testserialadder;

13.

Model a T flip flop. Use it to model a Mod-10 up down counter.

entity tff is port(t,clk,reset: in bit; q: inout bit); end entity; architecture arch of tff is begin process(clk,reset) variable tempv: bit; begin if(reset='1') then q<= '0'; elsif(clk 'event and clk='1') then if(t='1') then q<= not(q); end if; end if; end process; end arch; entity mod10ud is port( clk,reset: in bit; q: inout bit_vector(3 downto 0)); end entity; architecture arch of mod10ud is component tff is port(t,clk,reset: in bit; q: inout bit); end component; signal t0,t1,t2,t3: bit; begin inst1: tff port map(t0,clk,reset,q(0)); inst2: tff port map(t1,clk,reset,q(1)); inst3: tff port map(t2,clk,reset,q(2)); inst4: tff port map(t3,clk,reset,q(3)); t0<= '1' ; t1<=(not q(0))and(q(1) or q(2) or q(3)); t2<=(q(3)and(not q(0)))or(q(2) and (not q(1)) and (not q(0))); t3<=(not q(1)) and (not q(0))and (not q(2)); end arch; entity test is

end entity; architecture arch of test is component mod10ud is port( clk,reset: in bit; q: inout bit_vector(3 downto 0)); end component; signal clk,reset: bit; signal q: bit_vector(3 downto 0); begin inst: mod10ud port map(clk,reset,q); process begin clk<='0'; wait for 5 ns; clk<='1'; wait for 5 ns; end process; process begin reset<='1'; wait for 1 ns; reset<='0'; wait for 80 ns; end process; end arch;

14.

Implement an n-bit Shift-left register using generic facilty of VHDL.

entity mux2x1 is port( ip1,ip0,s: in bit; op: out bit); end entity; architecture arch of mux2x1 is begin op<=ip0 when s='0' else ip1; end arch; entity dff is port ( din,clk,reset: in bit; q: out bit); end entity; architecture d_ff of dff is begin process(clk,reset) begin if(reset = '1') then q<= '0'; elsif(clk 'event and clk='1') then q<=din; end if; end process; end d_ff;

entity shlreg is generic(n: integer:=4); port(ip: in bit_vector(n-1 downto 0); sel,clk,reset: in bit; op: buffer bit_vector(n-1 downto 0)); end entity; architecture arch of shlreg is component dff is port ( din,clk,reset: in bit; q: out bit); end component; component mux2x1 is port( ip1,ip0,s: in bit; op: out bit);

end component; signal regin: bit_vector(n-1 downto 0); begin loop1: for i in 0 to n-1 generate insti: dff port map(regin(i),clk,reset,op(i)); end generate loop1; instm0: mux2x1 port map (ip(0),'0',sel,regin(0)); loop2: for i in 1 to n-1 generate instmi: mux2x1 port map (ip(i),op(i-1),sel,regin(i)); end generate loop2; end arch; entity test is end entity; architecture arch of test is component shlreg is generic(n: integer:=4); port(ip: in bit_vector(n-1 downto 0); sel,clk,reset: in bit; op: buffer bit_vector(n-1 downto 0)); end component; signal ip,op: bit_vector(7 downto 0); signal sel,clk,reset: bit; begin inst: shlreg generic map (n=>8) port map (ip,sel,clk,reset,op); process begin clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns; end process; process begin reset<='1'; wait for 1 ns; reset<='0'; wait for 1 ns; sel<='1'; ip<="00110011"; wait for 20 ns; sel<= '0'; wait for 20 ns; sel<='1';

ip<="11001100"; wait for 20 ns; sel<= '0'; wait for 40 ns; end process; end arch;

15.

Implement Booth's Multiplication algorithm in VHDL.

library ieee; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all; entity boothmult is port ( mpcd, mplr : in std_logic_vector(7 downto 0); result : out std_logic_vector(15 downto 0)); end entity ; architecture booth_arch of boothmult is begin process(mpcd,mplr) variable br,nbr : std_logic_vector(7 downto 0); variable acqr : std_logic_vector(15 downto 0); variable qn1 : std_logic ; begin acqr(15 downto 8):= (others=>'0'); acqr(7 downto 0) := mpcd; br:= mplr ; nbr := (not mplr) + '1' ; qn1 := '0' ; loop1 : for i in 7 downto 0 loop if( acqr(0) = '0' and qn1 = '0') then qn1 := acqr(0); acqr(14 downto 0) := acqr(15 downto 1) ; elsif ( acqr(0) = '0' and qn1 = '1') then acqr(15 downto 8) := acqr(15 downto 8) + br; qn1 := acqr(0); acqr(14 downto 0) := acqr(15 downto 1) ; elsif ( acqr(0) = '1' and qn1 = '0') then acqr(15 downto 8) := acqr(15 downto 8) + nbr; qn1 := acqr(0); acqr(14 downto 0) := acqr(15 downto 1) ; elsif ( acqr(0) = '1' and qn1 = '1') then qn1 := acqr(0); acqr(14 downto 0) := acqr(15 downto 1) ; end if ; end loop loop1; result <= acqr ; end process ; end booth_arch; entity testbooth is end entity;

architecture test_arch of testbooth is component boothmult is port ( mpcd, mplr : in std_logic_vector(7 downto 0); result : out std_logic_vector(15 downto 0)); end component ; signal tmpcd, tmplr : std_logic_vector(7 downto 0); signal tresult : std_logic_vector(15 downto 0); begin inst: boothmult port map (tmpcd, tmplr, tresult); process begin tmpcd <= "11111110" ; tmplr <= "00000010" ; wait for 10 ns ; tmpcd <= "00000101" ; tmplr <= "00000010" ; wait for 10 ns ; end process; end test_arch ;

16.

Implement a Register file of 8- bit wide 16 registers with two read ports and a write port.

library ieee; use ieee.std_logic_1164.all; entity reg is port(wr_en,r1_en,r2_en,clk: in std_logic; addr: in integer range 0 to 15; ip1: in std_logic_vector(7 downto 0); op1: out std_logic_vector(7 downto 0); op2: out std_logic_vector(7 downto 0)); end entity; architecture arch of reg is type regfile is array(0 to 15) of std_logic_vector(7 downto 0); signal regfile1: regfile; begin process( clk ) begin if(clk 'event and clk='1') then if (wr_en='1') then regfile1(addr)<= ip1; elsif (r1_en='1') then op1<=regfile1(addr); op2<=(others=>'Z'); elsif (r2_en='1') then op2<=regfile1(addr); op1<=(others=>'Z'); end if; end if; end process; end arch; entity test is end entity; architecture arch of test is component reg is port(wr_en,r1_en,r2_en,clk: in std_logic; addr: in integer range 0 to 15; ip1: in std_logic_vector(7 downto 0); op1: out std_logic_vector(7 downto 0); op2: out std_logic_vector(7 downto 0)); end component;

signal wr_en,r1_en,r2_en,clk: std_logic; signal ip1,op1,op2: std_logic_vector(7 downto 0); signal addr: integer range 0 to 15; begin inst: reg port map (wr_en,r1_en,r2_en,clk,addr,ip1,op1,op2); process begin clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns; end process; process begin wr_en<='1'; r1_en<='0'; r2_en<='0'; addr<=3; ip1<="01100101"; wait for 12 ns; addr<=5; ip1<="01101001"; wait for 20 ns; addr<=12; ip1<="10111001"; wait for 20 ns; wr_en<='0'; r1_en<='1'; r2_en<='0'; addr<=3; wait for 20 ns; wr_en<='0'; r1_en<='0'; r2_en<='1'; addr<=5; wait for 20 ns; end process; end arch;

17.

Implement a 3-bit Gray Code counter using Finite State Modeling method.

entity graycounter is port (clk,reset: in bit; q: out bit_vector(2 downto 0)); end entity; architecture arch of graycounter is type state is (A,B,C,D,E,F,G,H); signal ps,ns: state; begin process(clk,reset) begin if (reset='1') then ps <= A; elsif(clk 'event and (clk='1')) then ps<=ns; end if; end process; process(ps) begin case ps is when A=> q<="000"; ns<=B; when B=> q<="001"; ns<=C; when C=> q<="011"; ns<=D; when D=> q<="010"; ns<=E; when E=> q<="110"; ns<=F; when F=> q<="111"; ns<=G; when G=> q<="101"; ns<=H; when H=>

q<="100"; ns<=A; end case; end process; end arch; entity test is end entity; architecture arch of test is component graycounter is port (clk,reset: in bit; q: out bit_vector(2 downto 0)); end component; signal clk,reset: bit; signal q: bit_vector(2 downto 0); begin inst: graycounter port map(clk,reset,q); process begin clk<='0'; wait for 5 ns; clk<='1'; wait for 5 ns; end process; process begin reset<='1'; wait for 1 ns; reset<='0'; wait for 80 ns; end process; end arch;

18. Model a Moore machine based circuit having a single serial input and a single output that gives an output 1 whenever it detects 0101 bit sequence in the input stream.
entity seq is port( ip,clk,reset: in bit; op: out bit); end entity; architecture arch of seq is signal ps,ns: integer range 0 to 15; begin process(clk,reset) begin if (reset='1') then ps<=0; elsif(clk 'event and (clk='1')) then ps<=ns; end if; end process; process(ip,ps) begin op<='0'; case ps is when 0 => if(ip='0') ns<=0; else ns<=8; end if; when 1 => if(ip='0') ns<=0; else ns<=8; end if; when 2 => if(ip='0') ns<=1; else ns<=9; end if; when 3 => if(ip='0') ns<=1;

then

then

then

then

else ns<=9; end if; when 4 => if(ip='0') ns<=2; else ns<=10; end if; when 5 => op<='1'; if(ip='0') ns<=2; else ns<=10; end if; when 6 => if(ip='0') ns<=3; else ns<=11; end if; when 7 => if(ip='0') ns<=3; else ns<=11; end if; when 8 => if(ip='0') ns<=4; else ns<=12; end if; when 9 => if(ip='0') ns<=4; else ns<=12; end if; when 10 => if(ip='0') ns<=5; else ns<=13;

then

then

then

then

then

then

then

end if; when 11 => if(ip='0') ns<=5; else ns<=13; end if; when 12 => if(ip='0') ns<=6; else ns<=14; end if; when 13 => if(ip='0') ns<=6; else ns<=14; end if; when 14 => if(ip='0') ns<=7; else ns<=15; end if; when 15 => if(ip='0') ns<=7; else ns<=15; end if; end case; end process; end arch; entity test is end entity;

then

then

then

then

then

architecture arch of test is component seq is port( ip,clk,reset: in bit; op: out bit); end component; signal ip,clk,reset,op : bit;

begin inst: seq port map (ip,clk,reset,op); process begin clk<='0'; wait for 5 ns; clk<='1'; wait for 5 ns; end process; process begin reset<='1'; wait for 1 ns; reset<='0'; wait for 1 ns; ip<='1'; wait for 5 ns; ip<='0'; wait for 10 ns; ip<='1'; wait for 10 ns; ip<='0'; wait for 10 ns; ip<='0'; wait for 10 ns; end process; end arch;

19.

Implement a 16 byte ROM with some pre defined data in its locations.

library ieee; use ieee.std_logic_1164.all; entity rom is port(clk,r_en : in std_logic; addr : in integer range 0 to 15; op : out std_logic_vector(7 downto 0)); end entity; architecture rom_arch of rom is type rom_array is array(0 to 15) of std_logic_vector(7 downto 0); signal memory: rom_array; begin memory(0)<="01011100"; memory(2)<="01101100"; memory(3)<="01011100"; memory(5)<="01011101"; memory(6)<="01000100"; memory(7)<="11011100"; memory(9)<="01111101"; memory(10)<="01011110"; memory(11)<="01011110"; memory(13)<="01011100"; memory(15)<="01011011"; process(clk) begin if(clk 'event and clk='1' and r_en ='1') then op<=memory(addr); end if; end process; end rom_arch; entity test is end entity; architecture arch of test is component rom is port(clk,r_en : in std_logic; addr : in integer range 0 to 15; op : out std_logic_vector(7 downto 0)); end component; signal clk,r_en : std_logic; signal addr : integer range 0 to 15; signal op : std_logic_vector(7 downto 0); begin inst: rom port map(clk,r_en,addr,op); process begin

clk<='0'; wait for 10 clk<='1'; wait for 10 end process; process begin r_en<='1'; addr<=3; wait for 13 r_en<='1'; addr<=6; wait for 20 r_en<='1'; addr<=10; wait for 20 r_en<='1'; addr<=13; wait for 20 r_en<='0'; addr<=15; wait for 20 r_en<='1'; addr<=2; wait for 20 end process; end arch;

ns; ns;

ns; ns; ns; ns; ns; ns;

20.

Implement a 1Kx8 RAM with bidirectional data lines.

library ieee; use ieee.std_logic_1164.all; entity RAM is port(clk,wr_en : in std_logic; addr : in integer range 0 to 511; bidir : inout std_logic_vector(7 downto 0)); end entity; architecture RAM_arch of RAM is type ram_array is array(0 to 511) of std_logic_vector(7 downto 0); signal memory: ram_array; begin process(clk,wr_en) begin if(wr_en = '0') then bidir <= memory(addr); else bidir <= (others => 'Z'); if(clk'event and clk='1') then memory(addr) <= bidir; end if; end if; end process; end RAM_arch; library ieee; use ieee.std_logic_1164.all; entity testbench is end entity; architecture test_ram_arch of testbench is component RAM is port(clk,wr_en : in std_logic; addr : in integer range 0 to 511; bidir : inout std_logic_vector(7 downto 0)); end component;

signal tclk,twr : std_logic; signal taddr : integer range 0 to 511; signal tbidir : std_logic_vector(7 downto 0); begin instance : ram port map(tclk,twr,taddr,tbidir); process begin tclk <= '0'; wait for 5 ns; tclk <= '1'; wait for 5 ns; end process; process begin tbidir<=(others => 'Z'); wait for 1 ns; twr <= '1'; taddr <= 5; tbidir <= "00000000"; wait for 13 ns; twr <= '1'; taddr <= 8; tbidir <= "00001110"; wait for 13 ns; tbidir<=(others => 'Z'); wait for 1 ns; twr <= '0'; taddr <= 16; wait for 15 ns; taddr <= 5; wait for 15 ns; taddr <= 8; wait for 15 ns; end process; end test_ram_arch;