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Packages Design Unit

Package declaration
Subprogram declarations Type declarations Component declarations Deferred constant declaration

Functions and Procedures

Package Body
Subprogram body Defered constant value

Packages declaration
Syntax:
package package_name is [exported_subprogram_declarations] [exported_constant_declarations] [exported_components] [exported_type_declarations] [attribut_declarations] [attribut_specifications] end package_name; package body package_name is [exported_subprogram_declarations] [internal_subprogram_declarations] [internal_subprogram_bodies] [internal_type_declarations] end package_name;

Packages declaration example

package MY_PACKAGE is type MY_TYPE1 is ... type MY_TYPE2 is ... function MY_MEAN (A, B, C: real) return real; procedureMY_PROC1 ( ); end MY_PACKAGE; package body MY_PACKAGE is function MY_MEAN (A, B, C : real) return real is begin return(A + B + C)/ 3; end MY_MEAN; ... end MY_PACKAGE;

Subprograms
There are two sorts of subprogram
Functions
One return value

Functions
Functions are used in place of component instantiations because they provide a way to write a concise, C-like code. Functions can have only one output. Functions can not have wait statements. All statements within the functions must be sequential statements and functions can not declare signals. Variables can be declared in the declarative region of a function.

Procedures
Zero or more retrun values

Subprogram can be defined in three places in the VHDL code :

Package Architecture Process

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Function declaration
Syntax :
function function_name (parameter_list) return type is types, constants, other functions, other declarations begin sequential_statements ... end function_name;

VHDL Functions
Functions execute a sequential algorithm and return a single value to calling program General form:

entity . . . is end . . . architecture . . . of . . . is begin process begin end process; end . . . ;

Function Declaration Function Calls Function-name(actual-parameter-list) 8

Essentials of functions

Placement of functions

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Function Example

Another function example

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Function Examples
Parameter list function PARITY_FUNC ( X : std_ulogic_vector ) return std_ulogic is variable TMP : std_ulogic ; Function name begin TMP := 0 ; for J in X range loop TMP := TMP xor X(J); end loop; return TMP; end PARITY_FUNC; Returned value

Function Examples
function bool2bit(a:BOOLEAN) return bit is begin if a then return 1; else return 0; end if; end bool2bit;

Function Examples
function majority(a,b,c: bit) return bit is begin return ((a and b) or (a and c) or (b and c)); end majority;

Full-Adder
entity full_add is port ( a,b,carry_in : in bit; sum,carry_out : out bit); end full_add; architecture a of full_add is function majority(a,b,c: bit) return bit is begin return ((a and b) or (a and c) or (b and c)); end majority; begin sum <= a xor b xor carry_in; carry_out <= majority(a,b,carry_in); end a;

Function Call
DATA_BYTE

Procedures
PARITY_BYTE PARITY_WORD

DATA_WORD16

function PARITY_FUNC ( X : std_ulogic_vector ) return std_ulogic is variable TMP : std_ulogic ; begin TMP := 0 ; for J in X range loop TMP := TMP xor X(J); end loop; return TMP; end PARITY_FUNC;

entity PARITY is port ( DATA_BYTE : in std_ulogic_vector(7 downto 0); DATA_WORD : in std_ulogic_vector(15 downto 0); PARITY_BYTE : out std_ulogic; PARITY_WORD : out std_ulogic ); end PARITY; Actual parameter architectureFUNC of PARITY is - - function declaration begin PARITY_BYTE <= PARITY_FUNC(DATA_BYTE); PARITY_WORD <= PARITY_FUNC(DATA_WORD); end FUNC;

The procedures can have more than one output. The procedures can have wait statements. All statements within the procedures must be sequential statements and procedures can not declare signals. Variables can be declared in the declarative region of a procedure.

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Procedure declaration
Syntax :
procedure procedure_name (parameter_list) is types, constants, other functions, other declarations begin sequential_statements ... end procedure_name;

VHDL Procedures
Facilitate decomposition of VHDL code into modules Procedures can return any number of values using output parameters General Form:
procedure procedure_name (formal-parameter-list) is [declarations] begin Sequential-statements end procedure_name;

entity . . . is end . . . architecture . . . of . . . is begin Procedure Declaration process Procedure Calls begin end process; end . . . ;

procedure_name (actual-parameter-list);

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Essentials of procedures

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Parameters for Subprogram Calls

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Procedure Examples
Procedure name procedure PARITY_PROC ( X : std_ulogic_vector; signal PARITY_BIT : out std_ulogic) is variable TMP : std_ulogic; begin TMP := 0 ; for J in X range loop TMP := TMP xor X(J); end loop; PARITY_BIT <= TMP; end PARITY_PROC; Assignment to out parameters Parameter list

Procedures
procedure dff ( signal d : bit_vector; signal clk,rst : bit; signal q,q_bar : out bit_vector) is begin if rst = 1 then q <= (others => 0); elsif clkevent and clk=1 then q <= d; q_bar <= not d; end if; end procedure;

Procedure Call
DATA_BYTE

Defining Subprograms
PARITY_BYTE

DATA_WORD16

PARITY_WORD

procedure PARITY_PROC ( X : std_ulogic_vector; signal PARITY_BIT : out std_ulogic) is variable TMP : std_ulogic; begin TMP := 0 ; for J in X range loop TMP := TMP xor X(J); end loop; PARITY_BIT <= TMP; end PARITY_PROC;

entity PARITY is port ( DATA_BYTE : in std_ulogic_vector(7 downto 0); DATA_WORD : in std_ulogic_vector(15 downto 0); PARITY_BYTE : out std_ulogic; PARITY_WORD : out std_ulogic ); end PARITY; Actual paramenter architecturePROC of PARITY is - - procedure declaration begin PARITY_PROC(DATA_BYTE, PARITY_BYTE); PARITY_PROC(DATA_WORD, PARITY_WORD); end PROC;

architecture FUNCTIONS of PARITY is Package function PARITY_FUNC ( X : std_ulogic_vector) Architecture return std_ulogic is variable TMP : std_ulogic; Process begin TMP : = 0 ; package P_FUNCS is for J in X range loop function PARITY_FUNC( x : std_ulogic_vector) TMP := TMP xor X(J); return std_ulogic ; end loop; end P_FUNCS; return TMP; package body P_FUNCS is end PARITY_FUNC; function PARITY_FUNC(x : std_ulogic_vector) begin return std_ulogic; variable TMP : std_ulogic; PARITY_BYTE <= PARITY_FUNC(DATA_BYTE); begin PARITY_WORD <= PARITY_FUNC(DATA_WORD); TMP : = 0 ; for J in X range loop end FUNCTIONS; TMP := TMP xor X(J); end loop; return TMP; end PARITY_FUNC; end P_FUNCS;

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Overloading
std_ulogic_vector

Subprogram Overloading
+
std_ulogic_vector

std_ulogic_vector

Re-define operators Different data types Called in context

package P_SUBP is function SINE (L : integer) function SINE (L : real) function SINE (L : std_logic_vector)

return real; return real; return real;

--1 --2 --3

std_ulogic_vector

+
integer integer

std_ulogic_vector

+
std_ulogic_vector

std_ulogic_vector

use work. P_SUBP.all; entity OVERLOADED is port ( A_BUS : in std_ulogic_vector (3 downto 0); B_INT : in integer range 0 to 15; C_REAL : in real; A, B, C : out real ); end OVERLOADED; architecture A of OVERLOADED is begin A <= SINE(A_BUS); Function 3 B <= SINE(B_INT); Function 1 C <= SINE(C_REAL); Function 2 end A;

Any subprogram can be overloaded

Argument Overloading
package P_AVERAGE is function AVERAGE (A, B : integer) return integer; function AVERAGE (A, B, C : integer) return integer; function AVERAGE (A, B, C, D : integer) return integer; end P_AVERAGE ; use work. P_AVERAGE.all; entity OVERLOADED is port ( A1, A1, C1 : in integer; V1, V2, V3 : out integer ); end OVERLOADED; architecture ARG_OVER of OVERLOADED is begin V1 <= AVERAGE(A1, B1, C1); V2 <= AVERAGE(A1, C1); V3 <= AVERAGE(A1, B1, C1, D1); end ARG_OVER; arguments --1 --2 --3

Operator Overloading
package P_ARITHMETIC is --1 function + (L: std_ulogic_vector; R: std_ulogic_vector) return integer; function + (L: std_ulogic_vector; R: std_ulogic_vector) return std_ulogic_vector; - - 2 function + (L: std_ulogic_vector; R: integer) return std_ulogic_vector; --3 function + (L: integer; R: std_ulogic_vector) return std_ulogic_vector; --4 use work.P_ARITHMETIC.all; entity OVERLOADED is port ( A_BUS, B_BUS : in std_ulogic_vector (3 downto 0); A_INT, B_INT : in integer range 0 to 15; Y_BUS, Z_BUS : out std_ulogic_vector (3 downto 0); Y_INT, Z_INT : out integer range 0 to 15 ); end OVERLOADED; architecture A of OVERLOADED is begin Y_INT <= A_INT + B_INT; Z_INT <= A_BUS + B_BUS; Z_BUS <= A_BUS + B_BUS; Y_BUS <= A_BUS + A_INT; Z_BUS <= A_BUS + B_INT; end A;

Function 2 Function 1 Function 3

Function 1 Function 2 Function 3 Function 4

Packages and Libraries

Provide a convenient way of referencing frequently used functions and components Package declaration

Accessing Library Components

To access the BITLIB
library BITLIB;

To use entire bit_pack package

use BITLIB.bit_pack.all;

To use a specific component

Package body [optional]
use BITLIB.bit_pack.Nand2;

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Essentials of packages

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