distinguishing synchronous & asynchronous transmission asynchronous has start bit & stop bit asynchronous: clock runs

uns unsynchronized with incoming signal synchronous: clock runs synchronized with incoming signal 3.3 Synchronous Transmission 2 general types of synchronous transmission: character oriented & bit oriented - both use same bit synchronization - major difference: byte & frame synchronization 3.3.1 Bit Synchronization: - each frame transmitted as contiguous bit stream - receiver obtains & maintains bit synchronization in 1 of 2 ways 1. Clock Encoding: clock timing information embedded in transmitted signal extracted by receiver 2. DPLL (digital phase locked loop): uses bit transitions in signal - receiver has local clock that is synchronized to signal by DPLL
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1. Clock Encoding & Extraction 3 methods (i) Bipolar Encoding: uses RZ (return to zero)signal - signal: 3 signal levels:+,0,- 1 encoded by + signal - 0 encoded by - signal - return to 0 after each bit 1 1 0 1 data tx clock +V 0 -V

RZ

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(ii) Manchester or phase encoding: uses NRZ (Non Return Zero) signal - binary 1 lo-hi transition - binary 0 hi-lo transition always a transition at center of bit cell - used by clock extraction ckt - produce clock pulse in center of 2nd half of bit cell received encoded signal is either high (1) or low (0) signal shifted into SIPO how terminating wires are connected 1 1 0 1 data tx clock (2) sample NRZ 1 1 0 1 (1) detect edge

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(iii) Differential Manchester Encoding always a signal transition at center of each bit cell transition at the start of a cell only if next bit = 0 encoded output takes on 1 of 2 forms, depending on assumed start level - either is just inverted form of the other - clock generated at end of each bit cell - transition determines if bit cell is 0 or 1 useful for TP links using differential drivers & receivers - doesnt matter how terminating wires are connected 1 1 0 1 data tx clock (2) edge transition indicates bit value

(1) detect center transition for bit synch

NRZ,D
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Manchester Schemes are balanced codes - no mean DC value - 000 or 111 will always have transitions (not constant DC signal) - important for AC coupling to receiver using transformer - receive electronics power supply isolated from transmission signal

2. DPLL (digital phase locked loop) alternative to clock encoding for bit synchronization requires a sufficient transitions in bit stream resynchronize receivers clock estimates bit timing in between edge transitions scramble data or NRZI (i) pass data through scrambler before transmission randomize bit stream remove contiguous 1s & 0s unscramble at receiver using inverse operation

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(ii) NRZI (non-return to zero, inverted) encodes data such that enough transitions always present differential encoding signal level changes for 0 doesnt change for 1 - 111 results in no transitions - 000 results in n transitions 1 1 0 0 1 1 1 data NRZ

NRZI 0 insertion bit used for every 5th 1 bit guaranteed number of transitions enables receiver to adjust clock to synchronize w/ bit stream

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DPLL circuit used to maintain bit synchronism clock (crystal oscillator) connected to DPLL - clock frequency 32 bit rate must hold its frequency sufficiently constant - require only small adjustments at irregular intervals
RxD 32x CLK Bit Decoder DPLL Receive SIPO

DPLL uses clock to derive timing interval to sample incoming bit stream assumes bit stream & local clock are synchronized state (1 or 0) on input signal will be sampled at center of each bit signal clocked onto SIPO register exactly 32 clock periods between each sample Input signal sampling pulse DPLL clock
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32 ticks
7

assume only small clock variations causes incoming bit stream &clock to drift out of synchronization adjust sampling instants in discrete increments (i) if no bit transition DPLL generates sampling pulse at 32 clock ticks (ii) if bit transition detected (at least every 5th bit) determine drift amount = position of actual signal transition relative to last DPLL sample: drift = tactual_transition - (t_sample + N/2) adjust time to next sampling pulse depending on amount of drift

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actual signal transition segments A B C D E tsample N/2

segment signal transition occurs in

next anticipated sampling actual next sampling pulse adjustment sample

t actual ? (N/2 = 16) drift Segment sample 60 20 +4 E too early 56 16 0 C OK 50 10 -6 A too late

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practically: divide each bit period into 5 segments adjust next sample interval based on drift successive adjustment keep sampling pulses close to center of bit cells 10
A

4
B

4
C

4
D

10
E

worst case: DPLL requires 10 bit transitions to converge to center of bit 5 bit transitions of coarse adjustments: 2 5 bit periods of fine adjustment: 1 normally perform coarse bit synchronization before frame starts before transmitting 1st frame or following idle periods between frames transmit bytes to provide minimum of 10 bit transitions ie: 00 = 16 bit transitions w/ NRZI ensures DPLL generates sampling pulses at nominal center at 1 st byte of frame once in synch (locked) only minor adjustments during frame transmission
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modulation rate: maximum rate encoded signal changes state if bit period = T - NRZI modulation rate encoding = 1/T - Manchester/Bipolar Encoding modulation rate = 2/T NRZI modulation rate = of Bipolar or Manchester worst case fundamental frequency component = modulation rate NRZI baud rate = 1: 1 signal/1 bit for given data rate Manchester & Bipolar require 2 * BW of NRZI (higher modulation rate higher BW) Manchester/Differential Manchester - used extensively in LANs: limited geographic span - attenuation, BW of transmission medium generally not a problem NRZI often used in WANs - TP cable over several km at high bit-rates - Each bit occupies full-width pulse

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Additional Encodings I. Modulation Format Schemes in principal to NRZI bit stuffing to force state changes AMI (alternative mark inversion): used in ISDN (Europe) B8ZS (bipolar w/ 8 bit substitution): used in N. American ISDN II. Baud Rate Reduction Codes: - used in ISDN access ckts: TP @ 160kbps up to several km - more than 1 bit represented in single pulse 4B3T (also MMS43) code - T = ternary 3 signal levels +V, 0, -V - 4 bits represented by 3 pulses each with 3 possible levels - baud rate = : 3 signals 4 bits(baud rate reduction = ) 2B1Q (Q = quaternary, 4 signal levels known as quats) - 2 bit input sequence transmitted as 1 quat - 4 levels represented by +3, +1, -1, -3: - 1 signal 2 bits: baud rate =
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III. Hybrid Schemes high bit rates & EMI difficult to obtain & maintain clock synchronization combined manchester & DPLL - DPLL keeps local clock in synch with incoming received signal - Manchester encoding at least 1 signal transition every bit cell - Local clock keeps synchronism more reliably - local (2x) clock in synch w/ incoming signal reliably decodes manchester signal - cost: increased BW for Manchester vs NRZI: baud = 2/1 4B5B: 4 bits 5 signals: - 32 possible signal combinations, only 16 used - guarantees signal transition w/ every 2 bits - baud/signal = 5/4

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3.3.2: Character Oriented Synchronous Transmission: used primarily for transmission of blocks of characters (ASCII files) no start & stop bits uses transmission control characters before each block known as SYN (synchronous idle) characters (i) 1st SYN allow receiver to obtain & maintain bit synchronization (ii) 2nd SYN provides byte synchronization (iii) Frame Synchronization ~ Asynchronous Transmission using STX & ETX 1. obtain bit synchronization with 1 st SYN starts receiving bits 2. enter hunt mode for byte synchronization: after each bit check last 8 bits 3. frame synchronization: process each byte looking for STX - after STX, read frame contents look for ETX 4. after ETX, transmitter can maintain synch by sending SYNs, otherwise receiver has to repeat hunt mode with new frame data transparency: same as with asynchronous (DLE) inefficiency: additional control characters: STX,ETX, DLE, SYN
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3.3.3: bit oriented synchronous transmission: preferred control scheme transparent to either printable characters or binary data 3 general schemes that vary on how SOF, EOF is signaled received stream searched on bit basis for SOF & EOF frame divided into sections that are often not multiples of 8 bits 1. flags (often used on point-point links) uses unique byte pattern (flag): 01111110 for SOF & EOF frame read on 8 bit boundaries until EOF detected reception terminated data transparency: ensure flag pattern isnt in frame data transmit circuit does bit stuffing: if 11111 detected insert 0 - flag pattern never present in frame data - performed at PISO output - enabled only during transmission of frame data (not SOF, EOF) receive circuit: if 111110 detected remove 0 - prior to input into SIPO - normally FCS data prior EOF subjected to same frame stuffing

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transmitter initial data stream transmitter detects illegal data pattern 01111110 10001111110 01100101001001001010 transmitter stuffs 0 into bit stream 100010111110 01100101001001001010

receiver EOF stripped and data recovered 10001111110 01100101001001001010 receiver detects 111110 and deletes 0 01111110 10001111110 01100101001001001010 frame received - SOF stripped 01111110 100010111110 01100101001001001010

transmitted frame with SOF and EOF and stuffed bit 01111110 100010111110 01100101001001001010 01111110

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2. SOF delimiter & length indicator (used in LANs, broadcast transmission media) destination node address precedes frame data clock synchronization: sender transmits preamble, string of 10 bit pairs (binary) allows other nodes obtain bit synchronization receiver searches for SOF delimiter 01111110 fixed header follows with address & length of data receiver counts number of bytes to determine EOF 3. bit-encoding violations ( also used w/ LANs) 1.5 bit manchester (3 signal pulses) no transition in 1st bit no signal transition illegal manchester code J: signal level remains same as previous for complete bit period K: signal level remains opposite level as previous for complete bit period
bit time bit time

SOF & EOF encoded as - SOF delimiter: JK0JK000 K J - EOF delimiter: JK1JK111 Illegal manchester codes: no signal state change over a bit time - frame payload cant contain J,K symbols

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SOF

EOF

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