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Project Report - VHDL MUX

This document describes a project to design an 8:1 multiplexer using VHDL. The objectives are to get familiar with VHDL coding and represent the multiplexer using both a behavioral and structural model. An 8:1 multiplexer has 8 inputs, 3 selection lines to choose one of the 8 inputs, and 1 output. The project will develop VHDL code for both models and verify the design using a test bench.

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293 views

Project Report - VHDL MUX

This document describes a project to design an 8:1 multiplexer using VHDL. The objectives are to get familiar with VHDL coding and represent the multiplexer using both a behavioral and structural model. An 8:1 multiplexer has 8 inputs, 3 selection lines to choose one of the 8 inputs, and 1 output. The project will develop VHDL code for both models and verify the design using a test bench.

Uploaded by

Msdmsd Msd
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Project Report On A VHDL Program for 8:1 Multiplexer

. Spring-12

2/16/2012

1. Introduction: Project Definition: A Multiplexer (MUX) is to be defined which takes eight 16 bit inputs and provides the 16 bit output based on the 3 bit select signal. Write down the VHDL program using (a) Behavioral Model (b) Structural Model The primary objective of the project is to get familiar with VHDL coding. VHDL stands for VHSIC HDL, where VHSIC means Very High Speed Integrated Circuit and HDL means Hardware Description Language. VHDL is a language used for design, simulation and synthesis for digital logic system. This digital logic system can be realized into gate level implementation, and then transformed to transistor level to create actual digital hardware of the logic. Processors, Microcontrollers and many more can be designed using this technique. In this project, fundamental goal is to design a Multiplexer. It should have eight 16 bit inputs and one 16 bit output. It has 3 bit selection line to accommodate eight different inputs. In VHDL, the digital system can be represented in different forms such as a behavioral model or a structural model. Behavior model describes the system as the way it behaves and it can be Register transfer level or sequential Boolean equations. On the other hand, Structural model describes system as gates or components interconnected to perform a defined logic. Here, we will explore both models to design a Multiplexer and simulate and validate results by creating appropriate test bench.

2. Theory. A Multiplexer is a device that selects one of the several digital or analog inputs and passes it to single line output. In binary system, it has 2n possible inputs and n selection lines which used to select which input needs to be sent to the output. It is basically works as analog or digital switch.

Fig.1 8:1 Multiplexer Truth Table: Selection Line S1 0 0 1 1 0 0 1 1 Input A,B,C,D,E,F,G,H A,B,C,D,E,F,G,H A,B,C,D,E,F,G,H A,B,C,D,E,F,G,H A,B,C,D,E,F,G,H A,B,C,D,E,F,G,H A,B,C,D,E,F,G,H A,B,C,D,E,F,G,H A,B,C,D,E,F,G,H Output Z A B C D E F G H

S2 0 0 0 0 1 1 1 1

S0 0 1 0 1 0 1 0 1

As shown in the table, S0, S1 & S2 are selection lines. A, B, C, D, E, F, G & H are eight different inputs and Z is a single output. So, the Boolean equation for the output is Schematic:

In this project definition, we have 16 bit inputs and 16 bit output. So, we cant perform And operation as shown in Boolean expression.

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