Sequential Statements

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Outline
1. 2. 3. 4. 5. 6. VHDL process Sequential signal assignment statement Variable assignment statement If statement Case statement Simple for loop statement

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1. VHDL Process
Contains a set of sequential statements to be executed sequentially The whole process is a concurrent statement Can be interpreted as a circuit part enclosed inside of a black box May or may not be able to be mapped to physical hardware
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 Two types of process

A process with a sensitivity list A process with wait statement

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A process with a sensitivity list

Syntax
process(sensitivity_list) declarations; begin sequential statement; sequential statement; ... end process;
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 A process is like a circuit part, which can be

active (known activated) inactive (known as suspended).

A process is activated when a signal in the sensitivity list changes its value Its statements will be executed sequentially until the end of the process

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 E.g, 3-input and circuit

signal a,b,c,y: std_logic; process(a,b,c) begin y <= a and b and c; end process;

How to interpret this:

process(a) begin y <= a and b and c; end process;

For a combinational circuit, all input should be included in the sensitivity list
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A process with wait statement

Process has no sensitivity list Process continues the execution until a wait statement is reached and then suspended Forms of wait statement:
wait on signals; wait until boolean_expression; wait for time_expression;
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 E.g, 3-input and circuit

process begin y <= a and b and c; wait on a, b, c; end process;

A process can has multiple wait statements Process with sensitivity list is preferred for synthesis
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2. Sequential signal assignment statement

Syntax
signal_name <= value_expression;

Syntax is identical to the simple concurrent signal assignment Caution:

Inside a process, a signal can be assigned multiple times, but only the last assignment takes effect
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 E.g.,
process(a,b,c,d) begin y <= a or c; y <= a and b; y <= c and d; end process; -- yentry := y -- yexit := a or c; -- yexit := a and b; -- yexit := c and d; -- y <= yexit

It is same as
process(a,b,c,d) begin y <= c and d; end process;

What happens if the 3 statements are concurrent statements?

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3. Varible assignment statement

Syntax
variable_name := value_expression;

Assignment takes effect immediately No time dimension (i.e., no delay) Behave like variables in C Difficult to map to hardware (depending on context)
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 E.g.,
process(a,b,c) variable tmp: std_logic; begin tmp := '0'; tmp := tmp or a; tmp := tmp or b; y <= tmp; end process;

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 interpretation: process(a,b,c) variable tmp0, tmp1, tmp2: std_logic; begin

tmp0 := '0'; tmp1 := tmp0 or a; tmp2 := tmp1 or b; y <= tmp2;

end process;

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 What happens if signal is used?

process(a,b,c,tmp) begin -- tmpentry := tmp tmp <= '0'; -- tmpexit := 0; tmp <= tmp or a; -- tmpexit := tmpentry or a; tmp <= tmp or b; -- tmpexit := tmpentry or b; end process; -- tmp <= tmpexit

Same as:
process(a,b,c,tmp) begin tmp <= tmp or b; end process;
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4. IF statement
Syntax Examples Comparison to conditional signal assignment Incomplete branch and incomplete signal assignment Conceptual Implementation

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Syntax
if boolean_expr_1 then sequential_statements; elsif boolean_expr_2 then sequential_statements; elsif boolean_expr_3 then sequential_statements; ... else sequential_statements; end if;
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E.g., 4-to-1 mux

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E.g., 2-to-22 binary decoder

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E.g., 4-to-2 priority encoder

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Comparison to conditional signal assignment

Two statements are the same if there is only one output signal in if statement If statement is more flexible Sequential statements can be used in then, elsif and else branches:
Multiple statements Nested if statements

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e.g., find the max of a, b, c

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e.g., 2 conditional sig assignment codes

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 2 conditional sig assign implementations

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e.g., sharing boolean condition

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Incomplete branch and incomplete signal assignment

According to VHDL definition:
Only the then branch is required; elsif and else branches are optional Signals do not need to be assigned in all branch When a signal is unassigned due to omission, it keeps the previous value (implying memory)

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Incomplete branch
E.g.,
It implies

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 fix

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Incomplete signal assignment

E.g.,

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 Fix #1:

Fix #2

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Conceptual implementation
Same as conditional signal assignment statement if the if statement consists of
One output signal One sequential signal assignment in each branch Multiple sequential statements can be constructed recursively

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e.g.

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e.g.

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5. Case statement
Syntax Examples Comparison to selected signal assignment statement Incomplete signal assignment Conceptual Implementation

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Syntax
case case_expression is when choice_1 => sequential statements; when choice_2 => sequential statements; ... when choice_n => sequential statements; end case;
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E.g., 4-to-1 mux

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E.g., 2-to-22 binary decoder

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E.g., 4-to-2 priority encoder

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Comparison to selected signal assignment

Two statements are the same if there is only one output signal in case statement Case statement is more flexible Sequential statements can be used in choice branches

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Incomplete signal assignment

According to VHDL definition:
Signals do not need to be assigned in all choice branch When a signal is unassigned, it keeps the previous value (implying memory)

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Incomplete signal assignment

E.g.,

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 Fix #1:

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 Fix #2:

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Conceptual implementation
Same as selected signal assignment statement if the case statement consists of
One output signal One sequential signal assignment in each branch Multiple sequential statements can be constructed recursively

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e.g.

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6. Simple for loop statement

Syntax Examples Conceptual Implementation

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 VHDL provides a variety of loop constructs Only a restricted form of loop can be synthesized Syntax of simple for loop:
for index in loop_range loop sequential statements; end loop;

loop_range must be static Index assumes value of loop_range from left to right
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 E.g., bit-wide xor

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 E.g., reduced-xor

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Conceptual implementation
Unroll the loop For loop should be treated as shorthand for repetitive statements E.g., bit-wise xor

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 E.g., reduced-xor

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Synthesis of sequential statements

Concurrent statements
Modeled after hardware Have clear, direct mapping to physical structures

Sequential statements
Intended to describe behavior Flexible and versatile Can be difficult to be realized in hardware Can be easily abused
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 Think hardware Designing hardware is not converting a C program to a VHDL program

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