DIGITAL CIRCUITS AND SYSTEMS - II

Course Code: Course Objective:

This course builds on the course Digital Circuits and Systems - Hardware development language VHDL is introduced; the usage of the same to implement the systems is dealt in detail.

BTE 501

Credit Units: 04

Course Contents:
Module I: Design of Sequential circuits SR, JK, T and D flip flops and their timing diagrams with delay, characteristic table, characteristic equation and excitation tables. Design of Finite State Machines: Mealy and Moore type using next state tables, state diagrams, state minimization, state encoding: minimum bit change and hot one encodings. Comparative cost and delays of different implementations and their optimization and timing diagrams, Asynchronous and synchronous sequential circuits Static Timing Analysis setup, hold time, clock skew, clock period Data paths, FSMs with datapaths, ASM charts Module II: Basics of VHDL Introduction and Basic Design Units of VHDL, Writing Entities for Digital circuits like decoders, registers etc, Scalar Data types and Operations: Object types: constants, variables, signal and files. Data Types: scalar, integer, floating, physical, enumeration, type declarations, subtypes, expressions and operators for various types. Sequential statements: If, case, Null, Loop, Exit, Next statements, while loops, For loops, Assertion and report statements Composite Arrays: arrays, Array aggregates, unconstrained array types, strings, Bit vectors, Standard Logic Arrays, array operations and records Module III: VHDL Programming Behavioral Modeling: process statements, variable and signal assignments, inertial and transport delay models, signal drivers, multiple and postponed processes Dataflow Modeling: Concurrent signal assignment, multiple drivers, block statement Structural Modeling: component declaration, component instantiation, resolving signal values, and configuration: basic configuration, configuration for structural modeling, mapping library entities. Generics, generic (AND, NAND, OR, NOR, XOR and XNOR) gates, functions and subprograms, packages and libraries Module IV: Synthesis: mapping statements to gates Writing a test bench, converting real and integers to time, dumping and reading from text file Vhdl modeling of basic gates, half and full adder AOI, IOA, OAI, multiplexes, decoders (dataflow, behavioral and structural modeling), three state driver, parity checker, D, T, JK and SR flip flops, flip flops with preset and clear, modeling for multiplexer, priority encoder, ALU etc, modeling regular structures, delays, conditional operations, synchronous logic, state machine modeling, Moore and Mealy machines, generic priority encoder, clock divider, shift registers, pulse counter etc Module V: Overview of the following PLD devices, PROM, PAL, PLA, CPLD, EPLD GAL, FPGA, DRAM etc and their applications, FPGA programming, Design exercises ASIC design using CAD tools

Examination Scheme:
Components Weightage (%) HA 7 V/S/Q 8 CT 10 AT 5 ESE 70

Text & References:

Daniel Gajski: Principles of Digital Design Bhasker: A VHDL Primer 3/e Pedroni: Circuit Design with VHDL Perry: VHDL: Programming by examples K. Skahill, VHDL for programmable Logic

MICROPROCESSOR SYSTEMS
Course Code: Course Objective:
This course deals with the systematic study of the Architecture and programming issues of 8085-microprocessor family. The aim of this course is to give the students basic knowledge of the above microprocessor needed to develop the systems using it.

BTE 502

Credit Units: 04

Course Contents:
Module I: Introduction to Microcomputer Systems Introduction to Microprocessors and microcomputers, Study of 8 bit Microprocessor, 8085 pin configuration, Internal Architecture and operations, interrupts, Stacks and subroutines, various data transfer schemes. Module II: ALP and timing diagrams Introduction to 8085 instruction set, advance 8085 programming, Addressing modes, Counters and time Delays, Instruction cycle, machine cycle, T-states, timing diagram for 8085 instruction. Module III: Memory System Design & I/O Interfacing Memory interfacing with 8085. Interfacing with input/output devices (memory mapped, peripheral I/O), Cache memory system. Study of following peripheral devices 8255, 8253, 8257, 8259, 8251. Module IV: Architecture of 16-Bit Microprocessor Difference between 8085 and 8086, Block diagram and architecture of 8086 family, pin configuration of 8086, minimum mode & maximum mode Operation, Bus Interface Unit, Register Organization, Instruction Pointer, Stack & Stack pointer, merits of memory segmentation, Execution Unit, Register Organization. Module V: Pentium Processors .Internal architecture of 8087, Operational overview of 8087, Introduction to 80186, 80286, 80386 & 80486 processors, Pentium processor (P-II, P-III, P-IV).

Examination Scheme:
Components A CT S/V/Q HA EE Weightage (%) 5 10 8 7 70 CT: Class Test, HA: Home Assignment, S/V/Q: Seminar/Viva/Quiz, EE: End Semester Examination; Att: Attendance

Text & References:

Ramesh. S. Gaonkar, Microprocessor architecture Programming and Application with 8085 Penram International Publishing, 4th Edition B. Ram, Fundamentals of microprocessors and microcomputer Dhanpat Rai, 5th Edition. ] Douglas V Hall. M. Rafiquzzaman, Microprocessor Theory and Application PHI 10th Indian Reprint. Naresh Grover, Microprocessor comprehensive studies Architecture, Programming and Interfacing Dhanpat Rai, 2003. Gosh, 0000 to 8085 PHI.

CONTROL SYSTEMS
Course Code: Course Objective:
The basic objective of this course is to provide the students the core knowledge of control systems, in which time & frequency domain analysis, concept of stability.

BTE 505

Credit Units: 04

Course Contents:
Module I: Input / Output Relationship Introduction of open loop and closed loop control systems, mathematical modeling and representation of physical systems (Electrical Mechanical and Thermal), derivation of transfer function for different types of systems, block diagram & signal flow graph, Reduction Technique, Masons Gain Formula. Module II: Time Domain Analysis Time domain performance criteria, transient response of first, second & higher order systems, steady state errors and static error constants in unity feedback control systems, error criteria, generalized error constants, performance indices, response with P, PI and PID Controllers. Module III: Frequency Domain Analysis Polar and inverse polar plots, frequency domain specifications, Logarithmic plots (Bode Plots),gain and phase margins, relative stability, Correlation with time domain, constant close loop frequency responses, from open loop response, Nyquist Plot. Module IV: Concept of Stability Asymptotic stability and conditional stability, Routh Hurwitz criterion, Root Locus plots and their applications. Compensation Techniques: Concept of compensation, Lag, Lead and Lag-Lead networks, design of closed loop systems using compensation techniques. P, PI, PID controllers.

Examination Scheme:
Components A CT S/V/Q HA EE Weightage (%) 5 10 8 7 70 CT: Class Test, HA: Home Assignment, S/V/Q: Seminar/Viva/Quiz, EE: End Semester Examination; Att: Attendance

Text & References:

Text: Dr. N.K Jain, 2005,Automatic Control System Engineering, Dhanpat Rai Publication. J. Nagrath & M. Gopal, 2000, Control System Engineering, New Age International. References: M, K. Ogata, 2002, Modern Control Engineering, PHI. B. C. Kuo, 2001, Automatic Control system, Prentice Hall of India.