ADSP-21161 SHARC Processor Hardware Reference

Revision 4.0, February 2005 Part Number 82-001944-01

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Copyright Information
2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA.

Disclaimer
Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, EZKit Lite, SHARC, the SHARC logo and VisualDSP++ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners.

CONTENTS

INTRODUCTION
Design Advantages ........................................................................ 1-1 Architecture Overview ................................................................... 1-5 Processor Core ......................................................................... 1-5 Processing Elements ............................................................ 1-6 Program Sequence Control .................................................. 1-7 Processor Internal Buses .................................................... 1-10 Processor Peripherals .............................................................. 1-11 Dual-Ported Internal Memory (SRAM) ............................. 1-11 External Port ..................................................................... 1-12 I/O Processor .................................................................... 1-14 JTAG Port ............................................................................. 1-16 Differences From Previous SHARC Processors ............................. 1-16 Processor Core Enhancements ................................................ 1-17 Processor Internal Bus Enhancements ..................................... 1-17 Memory Organization Enhancements .................................... 1-18 External Port Enhancements .................................................. 1-18 Host Interface Enhancements ............................................ 1-18 Multiprocessor Interface Enhancements ............................. 1-19

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IO Architecture Enhancements .............................................. 1-19 DMA Controller Enhancements ........................................ 1-19 Link Port Enhancements ................................................... 1-19 Instruction Set Enhancements ............................................... 1-20 For More Information About Analog Products ............................. 1-21 For Technical or Customer Support ............................................. 1-22 Whats New in This Manual ....................................................... 1-22 Related Documents .................................................................... 1-23 Conventions ............................................................................... 1-24

PROCESSING ELEMENTS
Setting Computational Modes ...................................................... 2-4 32-Bit (Normal Word) Floating-Point Format .......................... 2-4 40-Bit Floating-Point Format .................................................. 2-5 16-Bit (Short Word) Floating-Point Format ............................. 2-6 32-Bit Fixed-Point Format ....................................................... 2-6 Rounding Mode ...................................................................... 2-7 Using Computational Status ......................................................... 2-8 Arithmetic Logic Unit (ALU) ........................................................ 2-9 ALU Operation ....................................................................... 2-9 ALU Saturation ..................................................................... 2-10 ALU Status Flags ................................................................... 2-11 ALU Instruction Summary .................................................... 2-12 MultiplyAccumulator (Multiplier) ........................................... 2-15 Multiplier Operation ............................................................. 2-15

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Multiplier (Fixed-Point) Result Register ................................. 2-16 Multiplier Status Flags ........................................................... 2-19 Multiplier Instruction Summary ............................................ 2-20 Barrel-Shifter (Shifter) ................................................................. 2-23 Shifter Operation .................................................................. 2-23 Shifter Status Flags ................................................................ 2-27 Shifter Instruction Summary .................................................. 2-28 Data Register File ........................................................................ 2-30 Alternate (Secondary) Data Registers ........................................... 2-32 Multifunction Computations ...................................................... 2-34 Secondary Processing Element (PEy) ............................................ 2-37 Dual Compute Units Sets ...................................................... 2-39 Dual Register Files ................................................................. 2-42 Dual Alternate Registers ........................................................ 2-43 SIMD (Computational) Operations ....................................... 2-43 SIMD And Status Flags ......................................................... 2-46

PROGRAM SEQUENCER
Instruction Pipeline ...................................................................... 3-7 Instruction Cache ......................................................................... 3-8 Using the Cache .................................................................... 3-11 Optimizing Cache Usage ....................................................... 3-11 Branches and Sequencing ............................................................ 3-13 Conditional Branches ............................................................ 3-15 Delayed Branches .................................................................. 3-15

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Restrictions and Limitations When Using Delayed Branches .......................................................... 3-19 Loops and Sequencing ................................................................ 3-22 Restrictions on Ending Loops ................................................ 3-25 Restrictions on Short Loops .................................................. 3-26 Loop Address Stack ............................................................... 3-29 Loop Counter Stack .............................................................. 3-30 Interrupts and Sequencing .......................................................... 3-34 Sensing Interrupts ................................................................. 3-40 Masking Interrupts ............................................................... 3-41 Latching Interrupts ............................................................... 3-42 Stacking Status During Interrupts .......................................... 3-44 Nesting Interrupts ................................................................. 3-45 Reusing Interrupts ................................................................ 3-47 Interrupting IDLE ................................................................ 3-48 Multiprocessing Interrupts .................................................... 3-49 Timer and Sequencing ................................................................ 3-50 Stacks and Sequencing ................................................................ 3-52 Conditional Sequencing .............................................................. 3-53 SIMD Mode and Sequencing ...................................................... 3-57 Conditional Compute Operations ......................................... 3-58 Conditional Branches and Loops ........................................... 3-59 Conditional Data Moves ....................................................... 3-59 Case 1: Complementary Register Pair Data Move .............. 3-60

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Case 2: UncomplementedtoComplementary Register Move ................................................................ 3-63 Case 3: Complementary Register => Uncomplimentary Register .......................................................................... 3-64 Case 4: Data Move Involves External Memory or IOP Memory Space ........................................................ 3-65 Conditional DAG Operations ................................................ 3-66

DATA ADDRESS GENERATOR

Setting DAG Modes ...................................................................... 4-2 Circular Buffering Mode .......................................................... 4-4 Broadcast Loading Mode ......................................................... 4-5 Alternate (Secondary) DAG Registers ....................................... 4-6 Bit-reverse Addressing Mode .................................................... 4-8 Using DAG Status ........................................................................ 4-8 DAG Operations ........................................................................... 4-9 Addressing With DAGs ......................................................... 4-10 Addressing Circular Buffers ................................................... 4-12 Modifying DAG Registers ...................................................... 4-17 Addressing in SISD and SIMD Modes ................................... 4-18 DAGs, Registers, and Memory .................................................... 4-18 DAG Register-to-Bus Alignment ............................................ 4-19 DAG Register Transfer Restrictions ........................................ 4-21 DAG Instruction Summary ......................................................... 4-23

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MEMORY
Internal Memory .......................................................................... 5-2 External Memory .......................................................................... 5-2 Processor Architecture .................................................................. 5-4 Off-Chip Memory and Peripherals Interface .................................. 5-6 Buses ............................................................................................ 5-7 Internal Address and Data Buses .............................................. 5-7 Internal Data Bus Exchange .................................................. 5-10 ADSP-21161 Memory Map ........................................................ 5-16 Internal Memory ................................................................... 5-16 Multiprocessor Memory ........................................................ 5-19 External Memory .................................................................. 5-22 Shadow Write FIFO .............................................................. 5-24 Memory Organization and Word Size .................................... 5-25 Placing 32-Bit Words and 48-Bit Words ............................ 5-25 Mixing 32-Bit and 48-Bit Words ....................................... 5-26 Restrictions on Mixing 32-Bit and 48-Bit Words ............... 5-28 48-Bit Word Allocation .................................................... 5-31 Setting Data Access Modes .......................................................... 5-32 SYSCON Register Control Bits ............................................. 5-32 Mode 1 Register Control Bits ................................................ 5-34 Mode 2 Register Control Bits ................................................ 5-34 Wait Register Control Bits ..................................................... 5-34 Using Boot Memory .............................................................. 5-35

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Reading From Boot Memory ............................................. 5-35 Writing to Boot Memory ................................................... 5-36 Internal Interrupt Vector Table .............................................. 5-37 Internal Memory Data Width ................................................ 5-37 Memory Bank Size ................................................................ 5-38 External Bus Priority ............................................................. 5-39 Secondary Processor Element (PEy) ........................................ 5-39 Broadcast Register Loads ....................................................... 5-40 Illegal I/O Processor Register Access ....................................... 5-41 Unaligned 64-Bit Memory Access .......................................... 5-41 External Bank X Access Mode ................................................ 5-42 External Bank X Waitstates .................................................... 5-45 Using Memory Access Status ....................................................... 5-46 Accessing Memory ...................................................................... 5-46 Access Word Size ................................................................... 5-47 Long Word (64-Bit) Accesses ............................................. 5-48 Instruction Word (48-Bit) and Extended-Precision Normal Word (40-Bit) Accesses ...................................... 5-50 Normal Word (32-Bit) Accesses ......................................... 5-50 Short Word (16-Bit) Accesses ............................................ 5-51 SISD, SIMD, and Broadcast Load Modes ............................... 5-51 Single and Dual Data Accesses ............................................... 5-52 Data Access Options .............................................................. 5-52 Short Word Addressing of Single Data in SISD Mode ........ 5-54 Short Word Addressing of Single Data in SIMD Mode ....... 5-56 ADSP-21161 SHARC Processor Hardware Reference ix

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Short Word Addressing of Dual-Data in SISD Mode ......... 5-58 Short Word Addressing of Dual-Data in SIMD Mode ....... 5-60 32-Bit Normal Word Addressing of Single Data in SISD Mode ................................................................... 5-62 32-Bit Normal Word Addressing of Single Data in SIMD Mode .................................................................. 5-64 32-Bit Normal Word Addressing of Dual Data in SISD Mode ................................................................... 5-66 32-Bit Normal Word Addressing of Dual Data in SIMD Mode .................................................................. 5-68 Extended Precision Normal Word Addressing of Single Data .................................................................... 5-70 Extended Precision Normal Word Addressing of Dual Data in SISD Mode ....................................................... 5-72 Extended-Precision Normal Word Addressing of Dual Data in SIMD Mode ..................................................... 5-74 Long Word Addressing of Single Data ............................... 5-76 Long Word Addressing of Dual Data in SISD Mode .......... 5-78 Long Word Addressing of Dual Data in SIMD Mode ........ 5-80 Mixed Word Width Addressing of Dual Data in SISD Mode ................................................................... 5-82 Mixed Word Width Addressing of Dual Data in SIMD Mode .................................................................. 5-84 Broadcast Load Access ...................................................... 5-86 Shadow Write FIFO Considerations in SIMD Mode .............. 5-95 Arranging Data in Memory ....................................................... 5-100 Executing Instructions From External Memory .......................... 5-101

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32- to 48-Bit Packing Address Generation Scheme ............... 5-109 Total Program Size (32- to 48-Bit Packing) ...................... 5-110 16- to 48-Bit Packing Address Generation Scheme ............... 5-111 Total Program Size (16- to 48-Bit Packing) ...................... 5-111 8- to 48-Bit Packing Address Generation Scheme ................. 5-112 Total Program Size (8- to 48-Bit Packing) ........................ 5-113 No Packing (48- to 48-Bit) Address Generation Scheme ....... 5-113

I/O PROCESSOR
DMA Channel Allocation and Priorities ...................................... 6-16 DMA Interrupt Vector Locations ................................................. 6-18 Booting Modes ........................................................................... 6-20 DMA Controller Operation ........................................................ 6-20 Managing DMA Channel Priority .......................................... 6-22 Chaining DMA Processes ...................................................... 6-25 Transfer Control Block (TCB) Chain Loading ................... 6-26 Setting Up and Starting the Chain ..................................... 6-28 Inserting a TCB in an Active Chain ................................... 6-28 External Port DMA ..................................................................... 6-29 External Port Registers ........................................................... 6-30 External Port FIFO Buffers .................................................... 6-33 External Port DMA Data Packing .......................................... 6-34 32-Bit Bus Downloading ................................................... 6-37 16-Bit Bus Downloading ................................................... 6-38 8-Bit Bus Downloading ..................................................... 6-39

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Boot Memory DMA Mode .................................................... 6-42 External Port Buffer Modes ................................................... 6-42 External Port Channel Priority Modes ................................... 6-43 External Port Channel Transfer Modes ................................... 6-46 External Port Channel Handshake Modes .............................. 6-47 Master Mode .................................................................... 6-50 Paced Master Mode .......................................................... 6-54 Slave Mode ....................................................................... 6-55 Handshake Mode ............................................................. 6-57 DMA Handshake Idle Cycle .................................................. 6-64 External-Handshake Mode ................................................ 6-66 Setting Up External Port DMA .............................................. 6-68 Bootloading Through The External Port ................................ 6-70 Host Processor Booting ..................................................... 6-72 PROM Booting ................................................................ 6-74 External Port DMA Programming Examples .......................... 6-76 Link Port DMA .......................................................................... 6-81 Link Port Registers ................................................................ 6-81 Link Port Buffer Modes ......................................................... 6-83 Link Port Channel Priority Modes ......................................... 6-83 Link Port Channel Transfer Modes ........................................ 6-85 Setting Up Link Port DMA ................................................... 6-86 Bootloading Through The Link Port ..................................... 6-88 Link Port DMA Programming Examples ................................ 6-90

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Serial Port DMA ......................................................................... 6-95 Serial Port Registers ............................................................... 6-96 Serial Port Buffer Modes ........................................................ 6-97 Serial Port Channel Priority Modes ........................................ 6-99 Serial Port Channel Transfer Modes ....................................... 6-99 Setting Up Serial Port DMA ................................................ 6-100 SPORT DMA Programming Examples ................................. 6-102 SPI Port DMA .......................................................................... 6-108 SPI Port Registers ................................................................ 6-108 SPI Port Buffer .................................................................... 6-109 SPI DMA Channel Priority .................................................. 6-112 Setting up SPl Port DMA .................................................... 6-112 Bootloading Through the SPI Port ....................................... 6-113 SPI Port DMA Programming Examples ................................ 6-116 Using I/O Processor Status ........................................................ 6-121 External Port Status ............................................................. 6-127 Link Port Status .................................................................. 6-131 Serial Port Status ................................................................. 6-135 SPI Port Status .................................................................... 6-137 Optimizing DMA Throughput .................................................. 6-139 Internal Memory DMA ....................................................... 6-139 External Memory DMA ....................................................... 6-140 System-Level Considerations ................................................ 6-144

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EXTERNAL PORT
Setting External Port Modes .......................................................... 7-3 External Memory Interface ........................................................... 7-3 Banked External Memory ........................................................ 7-9 Boot Memory ....................................................................... 7-10 Idle Cycle ......................................................................... 7-10 Data Hold Cycle ............................................................... 7-12 Multiprocessor Memory Space Waitstates and Acknowledge ................................................................. 7-12 Timing External Memory Accesses ......................................... 7-13 Asynchronous Mode Interface Timing ............................... 7-14 Synchronous Mode Interface Timing ................................ 7-18 Synchronous Burst Mode Interface Timing ....................... 7-26 Using External SBSRAM ....................................................... 7-36 SBSRAM Restrictions ........................................................... 7-41 Host Processor Interface ............................................................. 7-42 Acquiring the Bus ................................................................. 7-44 Asynchronous Transfers ......................................................... 7-48 Host Transfer Timing ............................................................ 7-51 Host Interface Deadlock Resolution With SBTS .................... 7-54 Slave Reads and Writes .......................................................... 7-55 IOP Shadow Registers ....................................................... 7-55 Instruction Transfers ......................................................... 7-56 Slave Write Latency .......................................................... 7-56

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Slave Reads ....................................................................... 7-57 Broadcast Writes .................................................................... 7-57 Data Transfers Through the EPBx Buffers .............................. 7-58 DMA Transfers ...................................................................... 7-58 Host Data Packing ................................................................. 7-59 Packing Mode Variations For Host Accesses ........................... 7-61 IOP Register Host Accesses ............................................... 7-62 LINK Port Buffer Access ................................................... 7-63 EPBx Buffer Accesses ........................................................ 7-64 8- to 32-Bit Data Packing .................................................. 7-66 16- to 32-Bit Packing ........................................................ 7-69 48-Bit Instruction Packing ................................................ 7-74 Host Interface Status ............................................................. 7-76 Interprocessor Messages and Vector Interrupts ........................ 7-76 Message Passing (MSGRx) ................................................ 7-77 Host Vector Interrupts (VIRPT) ........................................ 7-78 System Bus Interfacing .......................................................... 7-78 Access to the Processor Bus Slave Processor ..................... 7-79 Access to the System Bus Master Processor ...................... 7-79 Processor Core Access to System Bus ................................. 7-82 Deadlock Resolution ......................................................... 7-82 DMA Access to System Bus ............................................... 7-84 Multiprocessing With Local Memory ................................. 7-85 ADSP-21161 to Microprocessor Interface .......................... 7-85

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Multiprocessor (MP) Interface .................................................... 7-87 Multiprocessing System Architectures .................................... 7-90 Data Flow Multiprocessing ............................................... 7-90 Cluster Multiprocessing .................................................... 7-91 Multiprocessor Bus Arbitration .............................................. 7-93 Bus Arbitration Protocol ................................................... 7-95 Bus Arbitration Priority (RPBA) ....................................... 7-98 Bus Mastership Timeout ................................................. 7-101 Priority Access ................................................................ 7-103 Bus Synchronization After Reset .......................................... 7-105 Booting Another processor .................................................. 7-108 Multiprocessor Writes and Reads ......................................... 7-109 Instruction Transfers ....................................................... 7-110 Bus Lock and Semaphores ................................................... 7-110 Multiprocessor Interface Status ....................................... 7-112

SDRAM INTERFACE
SDRAM Pin Connections ............................................................. 8-7 SDRAM Timing Specifications ..................................................... 8-8 SDRAM Control Register (SDCTL) ............................................. 8-9 SDRAM Configuration for Runtime ........................................... 8-10 Setting the Refresh Counter Value (SDRDIV) ....................... 8-13 Setting the SDRAM Clock Enables ........................................ 8-14 Setting the Number of SDRAM Banks (SDBN) ..................... 8-15 Setting the External Memory Bank (SDEMx) ........................ 8-16

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Setting the SDRAM Buffering Option (SDBUF) .................... 8-16 Selecting the CAS Latency Value (SDCL) ............................... 8-17 Selecting the SDRAM Page Size (SDPGS) .............................. 8-18 Setting the SDRAM Power-Up Mode (SDPM) ....................... 8-19 Starting the SDRAM Power-Up Sequence (SDPSS) ................ 8-19 Starting Self-Refresh Mode (SDSRF) ..................................... 8-20 Selecting the Active Command Delay (SDTRAS) ................... 8-20 Selecting the Precharge Delay (SDTRP) ................................. 8-21 Selecting the RAS-to-CAS Delay (SDTRCD) ......................... 8-21 SDRAM Controller Standard Operation ...................................... 8-22 Understanding DAG and DMA Operation ............................. 8-22 Multiprocessing Operation .................................................... 8-24 Accessing SDRAM ................................................................ 8-25 Address Mapping for SDRAM ........................................... 8-27 Understanding DQM Operation ............................................ 8-29 Executing a Parallel Refresh Command During Host Control ...................................................................... 8-29 Powering Up After Reset ........................................................ 8-30 Entering and Exiting Self-Refresh Mode ................................. 8-31 SDRAM Controller Commands .................................................. 8-31 Bank Activate (ACT) Command ............................................ 8-32 Mode Register Set (MRS) ...................................................... 8-32 Precharge Command (PRE) ................................................... 8-33 Read/Write Command ........................................................... 8-34 Read Commands ............................................................... 8-34 ADSP-21161 SHARC Processor Hardware Reference xvii

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Write Commands ............................................................. 8-36 DMA Transfers ................................................................. 8-37 Refresh (REF) Command ...................................................... 8-37 Setting the Delay Between Refresh Commands .................. 8-37 Understanding Multiprocessing Operation ........................ 8-38 Self Refresh Command (SREF) .............................................. 8-39 Programming Example .......................................................... 8-40

LINK PORTS
Link Port to Link Buffer Assignment ............................................. 9-3 Link Port DMA Channels ............................................................. 9-4 Link Port Booting ......................................................................... 9-5 Setting Link Port Modes ............................................................... 9-5 Link Port Control Register (LCTL) Bit Descriptions ................ 9-7 Link Data Path and Compatibility Modes ................................ 9-9 Using Link Port Handshake Signals ............................................. 9-10 Using Link Buffers ...................................................................... 9-12 Core Processor Access To Link Buffers ................................... 9-13 Host Processor Access To Link Buffers ................................... 9-14 Using Link Port DMA ................................................................ 9-16 Using Link Port Interrupts .......................................................... 9-17 Link Port Interrupts With DMA Enabled .............................. 9-18 Link Port Interrupts With DMA Disabled ............................. 9-19 Link Port Service Request Interrupts (LSRQ) ......................... 9-19 Detecting Errors on Link Transmissions ...................................... 9-22

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Link Port Programming Examples .......................................... 9-23 Using Token Passing With Link Ports .......................................... 9-27 Designing Link Port Systems ....................................................... 9-30 Terminations for Link Transmission Lines .............................. 9-30 Peripheral I/O Using Link Ports ............................................. 9-31 Data Flow Multiprocessing With Link Ports ........................... 9-33

SERIAL PORTS
Serial Port Pins ........................................................................... 10-3 SPORT Interrupts ...................................................................... 10-7 SPORT Reset .............................................................................. 10-8 SPORT Control Registers and Data Buffers ................................. 10-9 Serial Port Control Registers (SPCTLx) ................................ 10-14 Register Writes and Effect Latency ................................... 10-30 Transmit and Receive Data Buffers ....................................... 10-30 Clock and Frame Sync Frequencies (DIV) ............................ 10-33 Data Word Formats ................................................................... 10-35 Word Length ....................................................................... 10-36 Endian Format .................................................................... 10-36 Data Packing and Unpacking ............................................... 10-37 Data Type ....................................................................... 10-37 Companding ....................................................................... 10-39 Clock Signal Options ................................................................ 10-40 Frame Sync Options .................................................................. 10-41 Framed Versus Unframed ..................................................... 10-41

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Internal Versus External Frame Syncs ................................... 10-42 Active Low Versus Active High Frame Syncs ........................ 10-43 Sampling Edge for Data and Frame Syncs ............................ 10-43 Early Versus Late Frame Syncs ............................................. 10-44 Data-Independent Transmit Frame Sync .............................. 10-45 SPORT Loopback .................................................................... 10-46 SPORT Operation Modes ......................................................... 10-47 I2S Mode ............................................................................ 10-48 Setting Internal Serial Clock and Frame Sync Rates ......... 10-49 I2S Control Bits ............................................................. 10-49 Setting Word Length (SLEN) .......................................... 10-49 Selecting Transmit Receive Channel Order (L_FIRST) .... 10-49 Selecting the Frame Sync Options (FS_BOTH) ............... 10-50 Enabling SPORT Master Mode (MSTR) ......................... 10-50 Enabling SPORT DMA (SDEN) .................................... 10-51 Multichannel Operation ...................................................... 10-52 Frame Syncs in Multichannel Mode ................................ 10-54 Multichannel Control Bits in SPCTL .............................. 10-55 Channel Selection Registers ............................................ 10-57 Transferring Data to Memory ................................................... 10-58 DMA Block Transfers .......................................................... 10-59 Setting Up DMA on SPORT Channels ........................... 10-60 SPORT DMA Parameter Registers ....................................... 10-61 SPORT DMA Chaining ................................................. 10-65

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Single-Word Transfers .......................................................... 10-65 SPORT Pin/Line Terminations .................................................. 10-66 SPORT Programming Examples ................................................ 10-67

SERIAL PERIPHERAL INTERFACE (SPI)

Functional Description ............................................................... 11-2 SPI Interface Signals ................................................................... 11-3 SPICLK ................................................................................ 11-3 SPIDS ................................................................................... 11-4 FLAG ................................................................................... 11-5 MOSI ................................................................................... 11-6 MISO ................................................................................... 11-6 SPI Interrupts ............................................................................. 11-8 SPI IOP Registers ....................................................................... 11-9 SPI Control Register (SPICTL) .............................................. 11-9 Baud Rate Example ......................................................... 11-14 Seamless Operation ......................................................... 11-15 SPI Status Register (SPISTAT) ............................................. 11-15 SPI Transmit Data Buffer (SPITX) ....................................... 11-20 SPI Receive Data Buffer (SPIRX) ......................................... 11-20 SPI Shift Registers ............................................................... 11-21 SPI Data Word Formats ............................................................ 11-21 SPI Word Packing ............................................................... 11-24 SPI Operation Modes ................................................................ 11-24 Master Mode Operation ...................................................... 11-25

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Interrupt and DMA Driven Transfers .............................. 11-26 Core Driven Transfers ..................................................... 11-26 Automatic Slave Selection ............................................... 11-26 User Controlled Slave Selection ....................................... 11-27 Slave Mode Operation ......................................................... 11-28 Error Signals and Flags ............................................................. 11-29 Multi-Master Error (MME) ................................................. 11-30 Transmission Error (TXE) ................................................... 11-30 Reception Error (RBSY) ...................................................... 11-31 SPI/Link Port DMA ................................................................. 11-32 DMA Operation in SPI Master Mode .................................. 11-32 DMA Operation in Slave Mode ........................................... 11-33 SPI Booting .............................................................................. 11-34 32-Bit SPI Host Boot .......................................................... 11-38 16-Bit SPI Host Boot .......................................................... 11-39 8-Bit SPI Host Boot ............................................................ 11-41 Multiprocessor SPI Port Booting ..................................... 11-42 SPI Programming Example ....................................................... 11-44

JTAG TEST-EMULATION PORT

JTAG Test Access Port ................................................................ 12-3 Instruction Register .................................................................... 12-4 EMUPMD Shift Register ...................................................... 12-5 EMUPX Shift Register .......................................................... 12-6 EMU64PX Shift Register ...................................................... 12-7

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EMUPC Shift Register .......................................................... 12-7 EMUCTL Shift Register ........................................................ 12-8 EMUSTAT Shift Register .................................................... 12-11 BRKSTAT Shift Register ..................................................... 12-12 MEMTST Shift Register ...................................................... 12-13 PSx, DMx, IOx, and EPx (Breakpoint) Registers .................. 12-13 EMUN Register .................................................................. 12-16 EMUCLK and EMUCLK2 Registers ................................... 12-16 EMUIDLE Instruction ........................................................ 12-17 In Circuit Signal Analyzer (ICSA) Function ......................... 12-17 Boundary Register ..................................................................... 12-17 Device Identification Register .................................................... 12-28 Built-In Self-Test Operation (BIST) .......................................... 12-28 Private Instructions ................................................................... 12-28 References ................................................................................. 12-29

SYSTEM DESIGN
Pin Descriptions ......................................................................... 13-2 Input Synchronization Delay ............................................... 13-18 Pin States At Reset ............................................................... 13-19 Pull-Up and Pull-Down Resistors ......................................... 13-22 Clock Derivation ................................................................. 13-24 Timing Specifications ...................................................... 13-25 RESET and CLKIN ............................................................ 13-28 Reset Generators ................................................................. 13-31

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Interrupt and Timer Pins .................................................... 13-33 Core-Based Flag Pins ........................................................... 13-34 Flag Inputs ..................................................................... 13-34 Flag Outputs .................................................................. 13-34 Programmable I/O Flags ..................................................... 13-35 Example #1: Configuring FLGx as Output Flags ............. 13-37 Example #2: Configuring FLGx as Input Flags ................ 13-38 System Design Considerations for Flags ............................... 13-38 Example #3: Programming 2:1 Clock Ratio ..................... 13-40 Example #4: Programming 3:1 Clock Ratio ..................... 13-40 Example #5: Programming 4:1 Clock Ratio ..................... 13-40 JTAG Interface Pins ............................................................ 13-41 Dual-Voltage Power-up Sequencing ........................................... 13-41 PLL Start-Up (Revisions 1.0/1.1) ........................................ 13-44 Power On Reset (POR) Circuit ....................................... 13-44 PLL CLKIN Enable Circuit ............................................ 13-46 PLL Start-Up (Revision 1.2) ................................................ 13-48 Designing For JTAG Emulation ................................................ 13-49 Target Board Connector ...................................................... 13-50 Layout Requirements ................................................................ 13-54 Power Sequence for Emulation .................................................. 13-56 Additional JTAG Emulator References ...................................... 13-56 Pod Specifications ..................................................................... 13-56 JTAG Pod Connector .......................................................... 13-57

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3.3 V Pod Logic .................................................................. 13-58 2.5 V Pod Logic .................................................................. 13-59 Conditioning Input Signals ....................................................... 13-60 Link Port Input Filter Circuits ............................................. 13-60 RESET Input Hysteresis ...................................................... 13-61 Designing For High Frequency Operation ................................. 13-62 Clock Specifications and Jitter ............................................. 13-63 Clock Distribution .............................................................. 13-63 Point-to-Point Connections ................................................. 13-65 Signal Integrity .................................................................... 13-67 Other Recommendations and Suggestions ............................ 13-68 Decoupling Capacitors and Ground Planes .......................... 13-69 Oscilloscope Probes ............................................................. 13-70 Recommended Reading ....................................................... 13-71 Booting Single and Multiple Processors ..................................... 13-71 Multiprocessor Host Booting ............................................... 13-73 Multiprocessor EPROM Booting ......................................... 13-73 Booting From a Single EPROM ...................................... 13-73 Sequential Booting .......................................................... 13-74 Multiprocessor Link Port Booting ........................................ 13-75 Multiprocessor Booting From External Memory ................... 13-75 Data Delays, Latencies, and Throughput ................................... 13-76 Execution Stalls ................................................................... 13-77 DAG Stalls .......................................................................... 13-77

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Memory Stalls ..................................................................... 13-77 IOP Register Stalls .............................................................. 13-78 DMA Stalls ......................................................................... 13-78 Link Port and Serial Port Stalls ............................................ 13-78

REGISTERS
Control and Status System Registers .............................................. A-2 Mode Control 1 Register (MODE1) ........................................ A-3 Mode Mask Register (MMASK) .............................................. A-8 Mode Control 2 Register (MODE2) ...................................... A-10 Arithmetic Status Registers (ASTATx and ASTATy) ............... A-13 Sticky Status Registers (STKYx and STKYy) .......................... A-18 User-Defined Status Registers (USTATx) ............................... A-22 Processing Element Registers ....................................................... A-23 Data File Data Registers (Rx, Fx, Sx) ..................................... A-23 Multiplier Results Registers (MRFx, MRBx) .......................... A-24 Program Memory Bus Exchange Register (PX) ....................... A-25 Program Sequencer Registers ....................................................... A-25 Interrupt Latch Register (IRPTL) .......................................... A-27 Interrupt Mask Register (IMASK) ......................................... A-31 Interrupt Mask Pointer Register (IMASKP) ........................... A-32 Link Port Interrupt Register (LIRPTL) .................................. A-34 Flag Value Register (FLAGS) ................................................. A-37 IOFLAG Value Register ........................................................ A-38 Program Counter Register (PC) ............................................. A-41

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Program Counter Stack Register (PCSTK) ............................ A-44 Program Counter Stack Pointer Register (PCSTKP) .............. A-44 Fetch Address Register (FADDR) .......................................... A-44 Decode Address Register (DADDR) ...................................... A-44 Loop Address Stack Register (LADDR) ................................. A-45 Current Loop Counter Register (CURLCNTR) .................... A-45 Loop Counter Register (LCNTR) ......................................... A-45 Timer Period Register (TPERIOD) ....................................... A-46 Timer Count Register (TCOUNT) ....................................... A-46 Data Address Generator Registers ............................................... A-46 Index Registers (Ix) ............................................................... A-47 Modify Registers (Mx) .......................................................... A-47 Length and Base Registers (Lx,Bx) ........................................ A-47 I/O Processor Registers ............................................................... A-47 System Configuration Register (SYSCON) ............................ A-60 Vector Interrupt Address Register (VIRPT) ........................... A-63 External Memory Waitstate and Access Mode Register (WAIT) ............................................................................. A-65 System Status Register (SYSTAT) .......................................... A-69 SDRDIV Register (SDRDIV) ............................................... A-72 SDRAM Control Register (SDCTL) ..................................... A-73 External Port DMA Buffer Registers (EPBx) .......................... A-76 Message Registers (MSGRx) ................................................. A-77 PC Shadow Register (PC_SHDW) ........................................ A-77 MODE2 Shadow Register (MODE2_SHDW) ...................... A-78 ADSP-21161 SHARC Processor Hardware Reference xxvii

CONTENTS

Bus Time-Out Maximum Register (BMAX) ........................... A-79 Bus (Time-Out) Counter Register (BCNT) ........................... A-79 External Port DMA Control Registers (DMACx) ................... A-80 Internal Memory DMA Index Registers (IIx) ......................... A-87 Internal Memory DMA Modifier Registers (IMx) .................. A-87 Internal Memory DMA Count Registers (Cx) ........................ A-87 Chain Pointer For Next DMA TCB Registers (CPx) .............. A-88 General Purpose DMA Registers (GPx) ................................. A-89 External Memory DMA Index Registers (EIEPx) ................... A-89 External Memory DMA Modifier Registers (EMEPx) ............ A-89 External Memory DMA Count Registers (ECEPx) ................. A-90 DMA Channel Status Register (DMASTAT) .......................... A-90 Link Port Buffer Registers (LBUFx) ....................................... A-92 Link Port Buffer Control Register (LCTL) ............................. A-92 Link Port Service Request & Mask Register (LSRQ) ............... A-98 Serial Port Registers ............................................................. A-100 SPORT Serial Control Registers (SPCTLx) ..................... A-100 SPORT Multichannel Control Registers (SPxyMCTL) .... A-109 SPORT Transmit Buffer Registers (TXx) ......................... A-111 SPORT Receive Buffer Registers (RXx) ........................... A-111 SPORT Divisor Registers (DIVx) .................................... A-112 SPORT Count Registers (CNTx) .................................... A-113 SPORT Transmit Select Registers (MT2CSx and MT3CSx) .................................................................... A-113

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SPORT Transmit Compand Registers (MT2CCSx and MT3CCSx) ................................................................. A-113 SPORT Receive Select Registers ..................................... A-114 SPORT Receive Compand Registers ............................... A-114 Serial Peripheral Interface Registers ........................................... A-114 SPI Port Status Register ...................................................... A-115 SPI Control Register (SPICTL) ........................................... A-117 SPI Receive Buffer Register (SPIRX) ................................... A-120 SPI Transmit Buffer Register (SPITX) ................................. A-121 Register and Bit #Defines (def21161.h) .................................... A-121

INTERRUPT VECTOR ADDRESSES NUMERIC FORMATS

IEEE Single-Precision Floating-Point Data ................................... C-1 Extended-Precision Floating-Point ................................................ C-3 Short Word Floating-Point Format ............................................... C-4 Packing for Floating-Point Data ................................................... C-4 Fixed-Point Formats ..................................................................... C-6

GLOSSARY INDEX

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1 INTRODUCTION

Thank you for purchasing the Analog Devices SHARC digital signal processor (DSP).

Design Advantages
The ADSP-21161 processor is a high-performance 32-bit processor used for medical imaging, communications, military, audio, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. This processor builds on the ADSP-21000 Family processor core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM, integrated I/O peripherals, and an additional processing element for Single-Instruction-Multiple-Data (SIMD) support. The SHARC architecture balances a high performance processor core with high performance buses (PM, DM, IO). In the core, every instruction can execute in a single cycle. The buses and instruction cache provide rapid, unimpeded data flow to the core to maintain the execution rate. Figure 1-1 shows a detailed block diagram of the processor, which illustrates the following architectural features. Two processing elements (PEx and PEy), each containing 32-Bit IEEE floating-point computation unitmultiplier, ALU, Shifter, and data register file Program sequencer with related instruction cache, interval timer, and Data Address Generators (DAG1 and DAG2)

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Design Advantages

Dual-ported SRAM External port for interfacing to off-chip memory such as SDRAM, peripherals, hosts, and multiprocessor systems Input/Output (IO) processor with integrated DMA controller, SPI-compatible port, serial ports, and link ports for point-to-point multiprocessor communications JTAG Test Access Port for emulation
CO RE PR OCESSOR
T IME R INST RUCT ION CACHE
32 x 48- B IT A DD R AD D R

DU AL-PORTE D SRA M
B LO C K 0 B LO C K 1

TWO I NDEPENDENT DUA L-PO RTED BL OCKS PR OCE SSO R POR T

D A TA DA T A

JT AG
T EST & E MUL ATIO N

I/ O P OR T
D A TA D AT A ADDR

AD D R

DAG 1
8 x4 x32

DAG2
8x4x 32

P ROGRAM S EQUENCER 32 32 IOD 64 IO A 32

P M ADDRESS BU S DM ADDRES S BUS

EXTERN A L PORT
AD DR BUS MUX MULTIPROCESSOR INTERFACE 64 32

PM DATA BUS
BUS CONNECT (PX)

48/64 32/40/64

DM DAT A BUS

DATA BUS MUX HOS T PO RT

MULT

DAT A REGISTER FILE (P Ex) 16 x 40- BIT

BAR RE L SHIFTER

B ARRE L SHIFT ER

DATA R EGISTER F ILE (P Ey) 16 x 40- BIT

MUL T

IOP REGISTERS (MEMORY MAPPED) CONT ROL, S TAT US, & DATA B UFFERS

DMA CONTROLLER
SE RIAL PO RTS (2) L INK PORT S (6)

4 6 6 60

ALU

A LU

I/O PR OCESSOR

Figure 1-1. ADSP-21161 SHARC Block Diagram Figure 1-1 also shows the three on-chip buses of the ADSP-21161 processor: the Program Memory (PM) bus, Data Memory (DM) bus, and Input/Output (IO) bus. The PM bus provides access to either instructions

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INTRODUCTION

or data. During a single cycle, these buses let the processor access two data operands from memory, access an instruction (from the cache), and perform a DMA transfer. The buses connect to the ADSP-21161 processor external port, which provides the processor interface to external memory, memory-mapped I/O, a host processor, and additional multiprocessing ADSP-21161 processors. The external port performs bus arbitration and supplies control signals to shared, global memory and I/O devices. Figure 1-2 illustrates a typical single-processor system. The ADSP-21161 processor includes extensive support for multiprocessor systems as well. For more information, see Multiprocessor (MP) Interface on page 7-87. Further, the ADSP-21161 processor addresses the five central requirements for DSPs: Fast, flexible arithmetic computation units Unconstrained data flow to and from the computation units Extended precision and dynamic range in the computation units Dual address generators with circular buffering support Efficient program sequencing Fast, Flexible Arithmetic. The ADSP-21000 Family processors execute all instructions in a single cycle. They provide fast cycle times and a complete set of arithmetic operations. The processor is IEEE floating-point compatible and allows either interrupt on arithmetic exception or latched status exception handling. Unconstrained Data Flow. The ADSP-21161 processor has a Super Harvard Architecture combined with a 10-port data register file. In every cycle, the processor can write or read two operands to or from the register

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Design Advantages

CONTROL

CLOCK 2

CLKIN XTAL CLK_CFG1-0 CLKDBL EBOOT LBOOT IRQ2-0 BMS

DATA

ADSP-21161

ADDRESS

CS ADDR BOOT EPROM (OPTIONAL)

3 12

BRST

DATA

LINK DEVICES (2 MAX) (OPTIONAL) SERIAL DEVICE (OPTIONAL)

FLAG11-0 ADDR23-0 TIMEXP DATA47-16 RPBA ID2-0 RD LXCLK WR LXACK ACK LXDAT7-0 MS3-0 SCLK0 FS0 D0A D0B SCLK1 FS1 D1A D1B SCLK2 FS2 D2A D2B SCLK3 FS3 D3A D3B SPICLK SPDS MOSI MISO RAS CAS DQM SDWE SDCLK1-0 SDCKE SDA10

ADDR DATA MEMORY AND OE PERIPHERALS WE (OPTIONAL) ACK CS RAS CAS DQM WE CLK CKE A10 CS ADDR DATA SDRAM (OPTIONAL)

SERIAL DEVICE (OPTIONAL)

SERIAL DEVICE (OPTIONAL)

CLKOUT DMAR1-2 DMAG1-2

DMA DEVICE (OPTIONAL) DATA

SERIAL DEVICE (OPTIONAL)

CS HBR HBG REDY BR1-6 PA SBTS

SPI COMPATIBLE DEVICE (HOST OR SLAVE) (OPTIONAL)

HOST PROCESSOR INTERFACE (OPTIONAL) ADDR DATA

RESET RSTOUT JTAG 7

Figure 1-2. Typical Single Processor System file, supply two operands to the ALU, supply two operands to the multiplier, and receive three results from the ALU and multiplier. The processors 48-bit orthogonal instruction word supports parallel data transfers and arithmetic operations in the same instruction. 1-4 ADSP-21161 SHARC Processor Hardware Reference

INTRODUCTION

40-Bit Extended Precision. The processor handles 32-bit IEEE floating-point format, 32-bit integer and fractional formats (twos-complement and unsigned), and extended-precision 40-bit floating-point format. The processors carry extended precision throughout their computation units, limiting intermediate data truncation errors. Dual Address Generators. The processor has two Data Address Generators (DAGs) that provide immediate or indirect (pre- and post-modify) addressing. Modulus, bit-reverse, and broadcast operations are supported with no constraints on data buffer placement. Efficient Program Sequencing. In addition to zero-overhead loops, the processor supports single-cycle setup and exit for loops. Loops are both nestable (six levels in hardware) and interruptable. The processors support both delayed and non-delayed branches.

Architecture Overview
The ADSP-21161 processor forms a complete system-on-a-chip, integrating a large, high-speed SRAM and I/O peripherals supported by a dedicated I/O bus. The following sections summarize the features of each functional block in the ADSP-21161 processor SHARC architecture, which appears in Figure 1-1 on page 1-2. With each summary, a cross reference points to the sections where the features are described in greater detail.

Processor Core
The processor core of the ADSP-21161 processor consists of two processing elements (each with three computation units and data register file), a program sequencer, two data address generators, a timer, and an instruction cache. All digital signal processing occurs in the processor core.

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Architecture Overview

Processing Elements The processor core contains two processing elements (PEx and PEy). Each element contains a data register file and three independent computation units: an ALU, a multiplier with a fixed-point accumulator, and a shifter. For meeting a wide variety of processing needs, the computation units process data in three formats: 32-bit fixed-point, 32-bit floating-point and 40-bit floating-point. The floating-point operations are single-precision IEEE-compatible. The 32-bit floating-point format is the standard IEEE format, whereas the 40-bit extended-precision format has eight additional Least Significant Bits (LSBs) of mantissa for greater accuracy. The ALU performs a set of arithmetic and logic operations on both fixed-point and floating-point formats. The multiplier performs floating-point or fixed-point multiplication and fixed-point multiply/add or multiply/subtract operations. The shifter performs logical and arithmetic shifts, bit manipulation, field deposit and extraction, and exponent derivation operations on 32-bit operands. These computation units perform single-cycle operations; there is no computation pipeline. All units are connected in parallel, rather than serially. The output of any unit may serve as the input of any unit on the next cycle. In a multifunction computation, the ALU and multiplier perform independent, simultaneous operations. Each processing element has a general-purpose data register file that transfers data between the computation units and the data buses and stores intermediate results. A register file has two sets (primary and secondary) of sixteen registers each, for fast context switching. All of the registers are 40 bits wide. The register file, combined with the core processors Super Harvard architecture, allows unconstrained data flow between computation units and internal memory.

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INTRODUCTION

Primary Processing Element (PEx). PEx processes all computational instructions whether the processor is in Single-Instruction, Single-Data (SISD) or Single-Instruction, Multiple-Data (SIMD) mode. This element corresponds to the computational units and register file in previous ADSP-21000 family DSPs. Secondary Processing Element (PEy). PEy processes each computational instruction in lock-step with PEx, but only processes these instructions when the processor is in SIMD mode. Because many operations are influenced by this mode, more information on SIMD is available in multiple locations: For information on PEy operations, see Processing Elements on page 2-1 For information on data addressing in SIMD mode, see Addressing in SISD and SIMD Modes on page 4-18 For information on data accesses in SIMD mode, see SISD, SIMD, and Broadcast Load Modes on page 5-51 For information on multiprocessing in SIMD mode, see Multiprocessor (MP) Interface on page 7-87 For information on SIMD programming, see the ADSP-21160 SHARC DSP Instruction Set Reference Program Sequence Control Internal controls for ADSP-21161 processor program execution come from four functional blocks: program sequencer, data address generators, timer, and instruction cache. Two dedicated address generators and a program sequencer supply addresses for memory accesses. Together the sequencer and data address generators allow computational operations to execute with maximum efficiency since the computation units can be devoted exclusively to processing data. With its instruction cache, the

ADSP-21161 SHARC Processor Hardware Reference

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Architecture Overview

ADSP-21161 processor can simultaneously fetch an instruction from the cache and access two data operands from memory. The data address generators implement circular data buffers in hardware. Program Sequencer. The program sequencer supplies instruction addresses to program memory. It controls loop iterations and evaluates conditional instructions. With an internal loop counter and loop stack, the ADSP-21161 processor executes looped code with zero overhead. No explicit jump instructions are required to loop or to decrement and test the counter. The ADSP-21161 processor achieves its fast execution rate by means of pipelined fetch, decode, and execute cycles. If external memories are used, they are allowed more time to complete an access than if there were no decode cycle. Data Address Generators. The Data Address Generators (DAGs) provide memory addresses when data is transferred between memory and registers. Dual data address generators enable the processor to output simultaneous addresses for two operand reads or writes. DAG1 supplies 32-bit addresses to data memory. DAG2 supplies 32-bit addresses to program memory for program memory data accesses. Each DAG keeps track of up to eight address pointers, eight modifiers and eight length values. A pointer used for indirect addressing can be modified by a value in a specified register, either before (pre-modify) or after (post-modify) the access. A length value may be associated with each pointer to perform automatic modulo addressing for circular data buffers; the circular buffers can be located at arbitrary boundaries in memory. Each DAG register has a secondary register that can be activated for fast context switching.

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INTRODUCTION

Circular buffers allow efficient implementation of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance, and simplifying implementation. Interrupts. The ADSP-21161 processor has four external hardware interrupts: three general-purpose interrupts, IRQ2-0, and a special interrupt for reset. The processor also has internally generated interrupts for the timer, DMA controller operations, circular buffer overflow, stack overflows, arithmetic exceptions, multiprocessor vector interrupts, and user-defined software interrupts. For the general-purpose external interrupts and the internal timer interrupt, the ADSP-21161 processor automatically stacks the arithmetic status and mode (MODE1) registers in parallel with the interrupt servicing, allowing fifteen nesting levels of very fast service for these interrupts. Context Switch. Many of the processors registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result register all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. Timer. The programmable interval timer provides periodic interrupt generation. When enabled, the timer decrements a 32-bit count register every cycle. When this count register reaches zero, the ADSP-21161 processor generates an interrupt and asserts its timer expired output. The count register is automatically reloaded from a 32-bit period register and the count resumes immediately. Instruction Cache. The program sequencer includes a 32-word instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective; only instructions whose fetches

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Architecture Overview

conflict with program memory data accesses are cached. This caching allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and FFT butterfly processing. Processor Internal Buses The processor core has six buses: PM address, PM data, DM address, DM data, IO address, and IO data. Due to processors Super Harvard Architecture, data memory stores data operands, while program memory can store both instructions and data. This architecture allows dual data fetches, when the instruction is supplied by the cache. Bus Capacities. The PM address bus and DM address bus transfer the addresses for instructions and data. The PM data bus and DM data bus transfer the data or instructions from each type of memory. the PM address bus is 32 bits wide, allowing access of up to 62 Mwords for non-SDRAM and 254 Mwords for SDRAM banks of mixed instructions and data. The PM data bus is 64 bits wide from (8-, 16-, and 32-bits) to accommodate the 48-bit instructions and 32-bit data. The DM address bus is 32 bits wide allowing direct access of up to 4G words of data. The DM data bus is 64 bits wide. The DM data bus provides a path for the contents of any register in the processor to be transferred to any other register or to any data memory location in a single cycle. The data memory address comes from one of two sources: an absolute value specified in the instruction code (direct addressing) or the output of a data address generator (indirect addressing). The IO address and IO data buses let the IO processor access internal memory for DMA without delaying the processor core. The IO address bus is 18 bits wide, and the IO data bus is 64 bits wide. Data Transfers. Nearly every register in the processor core is classified as a Universal Register (UREG). Instructions allow transferring data between any two universal registers or between a universal register and memory. This support includes transfers between control registers, status registers,

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and data registers in the register file. The PM bus connect (PX) registers permit data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM data bus. These registers contain hardware to handle the data width difference. For more information, see For more information, see Processing Element Registers on page A-23.

Processor Peripherals
The term processor peripherals refers to everything outside the processor core. The ADSP-21161 processor peripherals include internal memory, external port, I/O processor, JTAG port, and any external devices that connect to the processor. Dual-Ported Internal Memory (SRAM) The ADSP-21161 processor contains 1 megabit of on-chip SRAM, organized as two blocks of 0.5 Mbits. Each block can be configured for different combinations of code and data storage. Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor or DMA controller. The dual-ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle. All of the memory can be accessed as 16-, 32-, 48-, or 64-bit words. On the ADSP-21161 processor, the memory can be configured as a maximum of 32K words of 32-bit data, 64K words of 16-bit data, 21.25K words of 48-bit instructions (and 40-bit data), or combinations of different word sizes up to 1.0 Mbit. The processor supports a 16-bit floating-point storage format, which effectively doubles the amount of data that may be stored on chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats completes in a single instruction.

ADSP-21161 SHARC Processor Hardware Reference

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Architecture Overview

While each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the DM bus for transfers, and the other block stores instructions and data, using the PM bus for transfers. Using the DM bus and PM bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The processor uses its external port to maintain single-cycle execution when one of the data operands is transferred to or from off-chip. External Port The ADSP-21161 processor external port provides the processor interface to off-chip memory and peripherals. The 254 Mword off-chip address space is included in the unified address space of the ADSP-21161 processor. The separate on-chip busesfor PM address, PM data, DM address, DM data, IO address, and IO datamultiplex at the external port to create an external system bus with a single 24-bit address bus and a single 32-bit data bus. The ADSP-21161 processor on-chip DMA controller automatically packs external data into the appropriate word width during transfers. The ADSP-21161 processor supports instruction packing modes to execute from 48-, 32-, 16-, and 8-bit wide memories. With the link ports disabled, the additional link port pins can be used to execute 48-bit wide instructions. The ADSP-21161 processor also includes 32- to 48-bit, 16to 48-bit, 8- to 48-bit execution packing for executing instruction directly from 32-bit, 16-bit, or 8-bit wide external memories. External SDRAM, SRAM, or SBSRAM can be 8-, 16-, or 32-bits wide for DMA transfers to or from external memory. On-chip decoding of high-order address lines generates memory bank select signals for addressing external memory devices. The ADSP-21161 processor provides programmable memory waitstates and external memory acknowledge controls for interfacing to peripherals with variable access, hold, and disable time requirements.

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SDRAM Interface. The ADSP-21161 processor integrated on-chip SDRAM controller transfers data to and from synchronous DRAM (SDRAM) at the core clock frequency or one-half the core clock frequency. The synchronous approach, coupled with the core clock frequency, supports data transfer at a high throughputup to 400 Mbytes/second for 32-bit transfers and 600 Mbytes/second for 48-bit transfers. The SDRAM interface provides a glueless interface with standard SDRAMs16 Mbits, 64 Mbits, 128 Mbits, and 256 Mbitsand includes options to support additional buffers between the ADSP-21161 processor and SDRAM. The SDRAM interface is extremely flexible and provides capability for connecting SDRAMs to any one of the ADSP-21161 processor four external memory banks, with up to all four banks mapped to SDRAM. Systems with several SDRAM devices connected in parallel may require buffering to meet overall system timing requirements. The ADSP-21161 processor supports pipelining of the address and control signals to enable such buffering between itself and multiple SDRAM devices. Host Processor Interface. The ADSP-21161 processor host interface allows easy connection to standard microprocessor buses, 8-bit, 16-bit and 32-bit, with little additional hardware required. The interface supports asynchronous and synchronous transfers at speeds up to the half the internal core clock rate of the ADSP-21161 processor. The host interface operates through the ADSP-21161 processor external port and maps into the unified address space. Four channels of DMA are available for the host interface; code and data transfers occur with low software overhead. The host can directly read and write the IOP register space of the ADSP-21161 processor and can access the DMA channel setup and mailbox registers. The host can also perform DMA transfers to and from the internal memory of the processor. Vector interrupt support provides for efficient execution of host commands.

ADSP-21161 SHARC Processor Hardware Reference

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Architecture Overview

Multiprocessor System Interface. The ADSP-21161 processor offers powerful features tailored to multiprocessing systems. The unified address space allows direct interprocessor accesses of each ADSP-21161 processor internal IOP registers. Distributed bus arbitration logic on the processor allows simple, glueless connection of systems containing up to six ADSP-21161 processor and a host processor. Master processor changeover incurs only one cycle of overhead. Bus arbitration handles either fixed or rotating priority. Processor bus lock allows indivisible read-modify-write sequences for semaphores. A vector interrupt capability is provided for interprocessor commands. I/O Processor The ADSP-21161 processor Input/Output Processor (IOP) includes four serial ports, two link ports, a SPI-compatible port, and a DMA controller. One of the processes that the IO processor automates is booting. The processor can boot from the external port (with data from an 8-bit EPROM or a host processor) or a link port. Alternatively, a no-boot mode lets the processor start by executing instructions from external memory without booting. Serial Ports. The ADSP-21161 processor features four synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at up to half the processor core clock rate. Programmable data direction provides greater flexibility for serial communications. Serial port data can automatically transfer to and from on-chip memory using DMA. Each of the serial ports offers a TDM multichannel mode (up to 128 channels) and supports m-law or A-law companding. I2S support is also provided with the ADSP-21161 processor. The serial ports can operate with little-endian or big-endian transmission formats, with word lengths from 3 to 32 bits. The serial ports offer selectable synchronization and transmit modes. Serial port clocks and frame syncs can be internally or externally generated.

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INTRODUCTION

Link Ports. The ADSP-21161 processor features two 8-bit link ports that provide additional I/O capabilities. Link port I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. The link ports can operate independently and simultaneously. The data packs into 32-bit or 48-bit words, which the processor core can directly read or the IO processor can DMA-transfer to on-chip memory. Clock and acknowledge handshaking signals control link port transfers. Transfers are programmable as either transmit or receive. Serial Peripheral (Compatible) Interface. The ADSP-21161 processor Serial Peripheral Interface (SPI) is an industry standard synchronous serial link that enables the ADSP-21161 processor SPI-compatible port to communicate with other SPI-compatible devices. SPI is a 4-wire interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. It can operate in a multi-master environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21161 processor SPI-compatible peripheral implementation also supports programmable baud rate and clock phase/polarities, and the use of open drain drivers to support the multi-master scenario to avoid data contention. DMA Controller. The ADSP-21161 processor on-chip DMA controller allows zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program. Both code and data can be downloaded to the ADSP-21161 processor using DMA transfers. DMA transfers can occur between the ADSP-21161 processor internal memory and external memory, external peripherals, or a host processor. DMA transfers between external memory and external peripheral devices are another option. External bus packing to 8-, 16-, 32-, 48-, or 64-bit words is automatically performed during DMA transfers.

ADSP-21161 SHARC Processor Hardware Reference

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Differences From Previous SHARC Processors

Fourteen channels of DMA are available on the ADSP-21161 processor two over the link ports (shared with SPI), eight over the serial ports, and four over the processors external port. The external port DMA channels serve for host processor, other ADSP-21161 processor DSPs, memory, or I/O transfers.

JTAG Port
The JTAG port on the ADSP-21161 processor supports the IEEE standard 1149.1 Joint Test Action Group (JTAG) standard for system test. This standard defines a method for serially scanning the I/O status of each component in a system. Emulators use the JTAG port to monitor and control the processor during emulation. Emulators using this port provide full-speed emulation with access to inspect and modify memory, registers, and processor stacks. JTAG-based emulation is non-intrusive and does not effect target system loading or timing.

Differences From Previous SHARC Processors

This section identifies differences between the ADSP-21161 processor and previous SHARC processors: ADSP-21160, ADSP-21060, ADSP-21061, ADSP-21062, and ADSP-21065. The ADSP-21161 processor preserves much of the ADSP-2106x architecture and is comparable to the ADSP-21160 with extended performance and functionality. For background information on SHARC and the ADSP-2106x Family processors, see the ADSP-2106x SHARC Users Manual or the ADSP-21065L SHARC Technical Reference.

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ADSP-21161 SHARC Processor Hardware Reference

INTRODUCTION

Processor Core Enhancements

Computational bandwidth on the ADSP-21161 processor is significantly greater than that on the ADSP-2106x DSPs. The increase comes from raising the operational frequency and adding another processing element: ALU, shifter, multiplier, and register file. The new processing element lets the processor to process multiple data streams in parallel (SIMD mode). Like the ADSP-21160, the program sequencer on the ADSP-21161 processor differs from the ADSP-2106x family, having several enhancements: new interrupt vector table definitions, SIMD mode stack and conditional execution model, and instruction decodes associated with new instructions. Interrupt vectors have been added that detect illegal memory accesses. Link port interrupt control has moved to a new register to support the additional DMA channels. Also, mode stack and mode mask support has been added to improve context switch time. As with the ADSP-21160, the data address generators on the ADSP-21161 processor differ from the ADSP-2106x in that DAG2 (for the PM bus) has the same addressing capability as DAG1 (for the DM bus). The DAG registers move 64-bits per cycle. Additionally, the DAGs support the new memory map and Long Word transfer capability. Circular buffering on the ADSP-21161 processor can be quickly disabled on interrupts and restored on the return. Data broadcast, from one memory location to both data register files, is determined by appropriate index register usage.

Processor Internal Bus Enhancements

The PM, DM, and IO data buses on the ADSP-21161 processor have increased on the ADSP-2106x processors to 64 bits. Additional multiplexing and control logic on the ADSP-21161 processor enable 16-, 32-, or 64-bit wide moves between both register files and memory. The ADSP-21161 processor is capable of broadcasting a single memory loca-

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Differences From Previous SHARC Processors

tion to each of the register files in parallel. Also, the ADSP-21161 processor permits register contents to be exchanged between the two processing elements register files in a single cycle.

Memory Organization Enhancements

The ADSP-21161 processor memory map differs from the ADSP-2106xs and is similar in organization to the ADSP-21160. The system memory map on the ADSP-21161 processor supports double-word transfers each cycle, reflects extended internal memory capacity for derivative designs, and works with updated control register for SIMD support.

External Port Enhancements

The ADSP-21161 processor external port differs from the ADSP-2106x DSPs. The data bus on the ADSP-21160 is 32-bits wide. A new packing mode permits DMA for instructions and data to and from 8-bit external memory. The ADSP-21161 processor has a new synchronous interface that improves local bus switching frequency. Also, burst support on the ADSP-21161 processor improves bus usage. Host Interface Enhancements The ADSP-21161 processor host interface differs from the ADSP-2106x DSPs. It is 32-bit wide and supports 8-bit, 16- and 32-bit hosts. Although the ADSP-21161 processor supports the ADSP-2106x asynchronous host interface protocols, the ADSP-21161 processor also provides new synchronous interface protocols for maximum throughput. The host/local bus deadlock resolution function on the ADSP-21161 processor is extended to the DMA controller. With this function the host (or bridge) logic forces the local bus to wait until the host completes its operation.

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INTRODUCTION

Multiprocessor Interface Enhancements The ADSP-21161 processor multiprocessor system interface supports greater throughput than the ADSP-2106x DSPs. The throughput between ADSP-21161 processors in a multiprocessing application increases due to new shared bus transfer protocols, shared bus cycle time improvements due to synchronous interface, and improvements in link port throughput. The external port supports glueless multiprocessing, with distributed arbitration for up to six ADSP-21161 processors.

IO Architecture Enhancements
The IO processor on the ADSP-21161 processor provides much greater throughput than the ADSP-2106x DSPs. This section describes how the link ports and DMA controller differ on the ADSP-21161 processor. DMA Controller Enhancements The ADSP-21161 processor DMA controller supports 14 channels compared to 10 on the ADSP-2106x DSPs. New packing modes support the 64-bit internal busing. To resolve potential deadlock scenarios, the ADSP-21161 processor DMA controller relinquishes the local bus in a similar fashion to the processor core when host logic asserts both HBR and SBTS. Link Port Enhancements The ADSP-21161 processor two link ports provide greater throughput than the ADSP-2106x DSPs. The link port data bus width on the ADSP-21161 processor is 8 bits wide (versus 4 bits on the ADSP-2106x DSPs). Link port clock control on the ADSP-21161 processor supports a wider frequency range.

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Differences From Previous SHARC Processors

Instruction Set Enhancements

ADSP-21161 processor provides source code compatibility with the previous SHARC family members, to the application assembly source code level. All instructions, control registers, and system resources available in the ADSP-2106x core programming model are available in ADSP-21161 processor. Instructions, control registers, or other facilities, required to support the new feature set of ADSP-2116x core include the following. Code compatible to the ADSP-21160 SIMD core Supersets of the ADSP-2106x programming model Reserved facilities in the ADSP-2106x programming model Symbol name changes from the ADSP-2106x and ADSP-21161 processor programming models These name changes can be managed through re-assembly using the ADSP-21161 processor development tools to apply the ADSP-21161 processor symbol definitions header file and linker description file. While these changes have no direct impact on existing core applications, system and I/O processor initialization code and control code do require modifications. Although the porting of source code written for the ADSP-2106x family to ADSP-21161 processor has been simplified, code changes are required to take full advantage of the new ADSP-21161 processor features. For more information, see the ADSP-21160 SHARC DSP Instruction Set Reference.

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INTRODUCTION

For More Information About Analog Products

Analog Devices is online on the internet at http://www.analog.com. Our web pages provide information on the company and products, including access to technical information and documentation, product overviews, and product announcements. Additional information may be obtained about Analog Devices and its products in any of the following ways: Visit our World Wide Web site at www.analog.com FAX questions or requests for information to 1(781)461-3010. Access the Computer Products Division File Transfer Protocol (FTP) site at ftp ftp.analog.com or ftp 137.71.23.21 or ftp://ftp.analog.com

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For Technical or Customer Support

For Technical or Customer Support

Our Customer Support group can be reached in the following ways: E-mail questions to [email protected] (hardware support), [email protected] (software support) or [email protected] (European customer support). Contact your local ADI sales office or an authorized ADI distributor Send questions by mail to:
Analog Devices, Inc. DSP Division One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA

Whats New in This Manual

The fourth edition of the ADSP-21161 SHARC Processor Hardware Reference is revised based on the published document errata.

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INTRODUCTION

Related Documents
For more information about Analog Devices DSPs and development products, see the following documents: ADSP-21161 SHARC DSP Microcomputer Data Sheet ADSP-21160 SHARC DSP Instruction Set Reference Getting Started Guide for VisualDSP++ & ADSP-21xxx Family DSPs VisualDSP++ User's Guide for ADSP-21xxx Family DSPs C/C++ Compiler & Library Manual for ADSP-21xxx Family DSPs Assembler Manual for ADSP-21xxx Family DSPs Linker & Utilities Manual for ADSP-21xxx Family DSPs All the manuals are included in the software distribution CD-ROM. To access these manuals, use the Help Topics command in the VisualDSP++ environments Help menu and select the Online Manuals book. From this Help topic, you can open any of the manuals, which are in Adobe Acrobat PDF format.

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Conventions

Conventions
The following are conventions that apply to all chapters. Note that additional conventions, which apply only to specific chapters, appear throughout this document. Table 1-1. Notation Conventions
Example Close command (File menu)
{this | that}

Description Titles in reference sections indicate the location of an item within the VisualDSP++ environments menu system (for example, the Close command appears on the File menu). Alternative items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required. Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that. Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this. Commands, directives, keywords, and feature names are in text with letter gothic font. Non-keyword placeholders appear in text with italic style format. Note: For correct operation, ... A Note: provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol. Warning: Injury to device users may result if ... A Warning: identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for devices users. In the online version of this book, the word Warning appears instead of this symbol.

[this | that]

[this,]

.SECTION
filename

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ADSP-21161 SHARC Processor Hardware Reference

2 PROCESSING ELEMENTS

The processors Processing Elements (PEx and PEy) perform numeric processing for digital signal processing algorithms. Each processing element contains a data register file and three computation units: an arithmetic/logic unit (ALU), a multiplier, and a shifter. Computational instructions for these elements include both fixed-point and floating-point operations, and each computational instruction can execute in a single cycle. The computational units in a processing element handle different types of operations. The ALU performs arithmetic and logic operations on fixed-point and floating-point data. The multiplier does floating-point and fixed-point multiplication and executes fixed-point multiply/add and multiply/subtract operations. The shifter completes logical shifts, arithmetic shifts, bit manipulation, field deposit, and field extraction operations on 32-bit operands. Also, the Shifter can derive exponents. Data flow paths through the computational units are arranged in parallel, as shown in Figure 2-1. The output of any computation unit may serve as the input of any computation unit on the next instruction cycle. Data moving in and out of the computational units goes through a 10-port register file, consisting of sixteen primary registers and sixteen alternate registers. Two ports on the register file connect to the PM and DM data buses, allowing data transfer between the computational units and memory (and anything else) connected to these buses.

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The processors assembly language provides access to the data register files in both processing elements. The syntax lets programs move data to and from these registers and specify a computations data format at the same time with naming conventions for the registers. For information on the data register names, see Data Register File on page 2-30. Figure 2-1 provides a graphical guide to the other topics in this chapter. First, a description of the MODE1 register shows how to set rounding, data format, and other modes for the processing elements. Next, an examination of each computational unit provides details on operation and a summary of computational instructions. Outside the computational units, details on register files and data buses identify how to flow data for computations. Finally, details on the processors advanced parallelism reveal how to take advantage of multifunction instructions and SIMD mode.

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Processing Elements

MODE1

PM DATA BUS DM DATA BUS REGISTER FILE (16 40-BIT) R0 R8 R9 R1 R10 R2 R11 R3 R4 R5 R6 R7 R12 R13 R14 R15

MULTIPLIER

SHIFTER

ALU

MRF2 MRF1 MRF0 ASTATx STKYx

TO PROGRAM SEQUENCER

Figure 2-1. Computation Units

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Setting Computational Modes

Setting Computational Modes

The MODE1 register controls the operating mode of the processing elements. Table A-2 on page A-3 lists all the bits in MODE1. The following bits in MODE1 control computational modes. Floating-point data format. Bit 16 (RND32) directs the computational units to round floating-point data to 32 bits (if 1) or round to 40 bits (if 0). Rounding mode. Bit 15 (TRUNC) directs the computational units to round results with round-to-zero (if 1) or round-to-nearest (if 0). ALU saturation. Bit 13 (ALUSAT) directs the computational units to saturate results on positive or negative fixed-point overflows (if 1) or return unsaturated results (if 0). Short word sign extension. Bit 14 (SSE) directs the computational units to sign extend short-word, 16-bit data (if 1) or zero-fill the upper 16 bits (if 0). Secondary processor element (PEy). Bit 21 (PEYEN) enables computations in PEySIMD mode(if 1) or disables PEySISD mode(if 0).

32-Bit (Normal Word) Floating-Point Format

In the default mode of the processor (RND32 bit=1), the multiplier and ALU support a single-precision floating-point format, which is specified in the IEEE 754/854 standard. For more information on this standard, see

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Processing Elements

For more information, see Numeric Formats on page C-1. This format is IEEE 754/854 compatible for single-precision floating-point operations in all respects except that: The processor does not provide inexact flags. NAN (Not-A-Number) inputs generate an invalid exception and return a quiet NAN (all 1s). Denormal operands flush to zero when input to a computation unit and do not generate an underflow exception. Any denormal or underflow result from an arithmetic operation flushes to zero and generates an underflow exception. The processor supports round to nearest and round toward zero modes, but does not support round to +Infinity and round to -Infinity. IEEE Single-precision floating-point data uses a 23-bit mantissa with an 8-bit exponent plus sign bit. In this case, the computation unit sets the eight LSBs of floating-point inputs to zeros before performing the operation. The mantissa of a result rounds to 23 bits (not including the hidden bit), and the 8 LSBs of the 40-bit result clear to zeros to form a 32-bit number, which is equivalent to the IEEE standard result. In fixed-point to floating-point conversion, the rounding boundary is always 40 bits even if the RND32 bit is set.

40-Bit Floating-Point Format

When in extended precision mode (RND32 bit=0), the processor supports a 40-bit extended precision floating-point mode, which has eight additional LSBs of the mantissa and is compliant with the 754/854 standards; however, results in this format are more precise than the IEEE single-precision standard specifies. Extended-precision floating-point data uses a 31-bit mantissa with a 8-bit exponent plus sign bit.

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Setting Computational Modes

16-Bit (Short Word) Floating-Point Format

The processor supports a 16-bit floating-point storage format and provides instructions that convert the data for 40-bit computations. The 16-bit floating-point format uses an 11-bit mantissa with a 4-bit exponent plus sign bit. The 16-bit data goes into bits 23 through 8 of a data register. Two shifter instructions, Fpack and Funpack, perform the packing and unpacking conversions between 32-bit floating-point words and 16-bit floating-point words. The Fpack instruction converts a 32-bit IEEE floating-point number in a data register into a 16-bit floating-point number. Funpack converts a 16-bit floating-point number in a data register into a 32-bit IEEE floating-point number. Each instruction executes in a single cycle. When 16-bit data is written to bits 23 through 8 of a data register, the processor automatically extends the data into a 32-bit integer (bits 39 through 8). If the SSE bit in MODE1 is set (1), the processor sign extends the upper 16 bits. If the SSE bit is cleared (0), the processor zeros the upper 16 bits. The 16-bit floating-point format supports gradual underflow. This method sacrifices precision for dynamic range. When packing a number that would have underflowed, the exponent clears to zero and the mantissa (including hidden 1) right-shifts the appropriate amount. The packed result is a denormal, which can be unpacked into a normal IEEE floating-point number.

32-Bit Fixed-Point Format

The processor always represents fixed-point numbers in 32 bits, occupying the 32 MSBs in 40-bit data registers. Fixed-point data may be fractional or integer numbers and unsigned or twos-complement. Each computational unit has its own limitations on how these formats may be mixed for

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Processing Elements

a given operation. All computational units read the upper 32 bits of data (inputs, operands) from the 40-bit registers (ignoring the 8 LSBs) and write results to the upper 32 bits (zeroing the 8 LSBs).

Rounding Mode
The TRUNC bit in the MODE1 register determines the rounding mode for all ALU operations, all floating-point multiplies, and fixed-point multiplies of fractional data. The processor supports two modes of rounding: round-toward-zero and round-toward-nearest. The rounding modes comply with the IEEE 754 standard and have the following definitions. Round-Toward-Zero (TRUNC bit=1). If the result before rounding is not exactly representable in the destination format, the rounded result is the number that is nearer to zero. This definition is equivalent to truncation. Round-Toward-Nearest (TRUNC bit=0). If the result before rounding is not exactly representable in the destination format, the rounded result is the number that is nearer to the result before rounding. If the result before rounding is exactly halfway between two numbers in the destination format (differing by an LSB), the rounded result is the number that has an LSB equal to zero. Statistically, rounding up occurs as often as rounding down, so there is no large sample bias. Because the maximum floating-point value is one LSB less than the value that represents Infinity, a result that is halfway between the maximum floating-point value and Infinity rounds to Infinity in this mode. Though these rounding modes comply with standards set for floating-point data, they also apply for fixed-point multiplier operations on fractional data. The same two rounding modes are supported, but only the round-to-nearest operation is actually performed by the multiplier. Using

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Using Computational Status

its local result register for fixed-point operations, the multiplier rounds-to-zero by reading only the upper bits of the result and discarding the lower bits.

Using Computational Status

The multiplier and ALU each provide exception information when executing floating-point operations. Each unit updates overflow, underflow, and invalid operation flags in the processing elements arithmetic status (ASTATx and ASTATy) register and sticky status (STKYx and STKYy) register. An underflow, overflow, or invalid operation from any unit also generates a maskable interrupt. There are three ways to use floating-point exceptions from computations in program sequencing: Interrupts. Enable interrupts and use an interrupt service routine to handle the exception condition immediately. This method is appropriate if it is important to correct all exceptions as they occur. and ASTATy registers. Use conditional instructions to test the exception flags in the ASTATx or ASTATy register after the instruction executes. This method permits monitoring each instructions outcome.
ASTATx

and STKYy registers. Use the Bit Tst instruction to examine exception flags in the STKY register after a series of operations. If any flags are set, some of the results are incorrect. This method is useful when exception handling is not critical.
STKYx

More information on ASTAT and STKY status appears in the sections that describe the computational units. For summaries relating instructions and status bits, see Table 2-1, Table 2-2, Table 2-4, Table 2-6, and Table 2-7.

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Processing Elements

Arithmetic Logic Unit (ALU)

The ALU performs arithmetic operations on fixed-point or floating-point data and logical operations on fixed-point data. ALU fixed-point instructions operate on 32-bit fixed-point operands and output 32-bit fixed-point results. ALU floating-point instructions operate on 32-bit or 40-bit floating-point operands and output 32-bit or 40-bit floating-point results. ALU instructions include: Floating-point addition, subtraction, add/subtract, average Fixed-point addition, subtraction, add/subtract, average Floating-point manipulation: binary log, scale, mantissa Fixed-point add with carry, subtract with borrow, increment, decrement Logical And, Or, Xor, Not Functions: Abs, pass, min, max, clip, compare Format conversion Reciprocal and reciprocal square root primitives

ALU Operation
ALU instructions take one or two inputs: X input and Y input. These inputs (also known as operands) can be any data registers in the register file. Most ALU operations return one result; in add/subtract operations, the ALU operation returns two results, and in compare operations, the ALU operation returns no result (only flags are updated). ALU results can be returned to any location in the register file.

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Arithmetic Logic Unit (ALU)

The processor transfers input operands from the register file during the first half of the cycle and transfers results to the register file during the second half of the cycle. With this arrangement, the ALU can read and write the same register file location in a single cycle. If the ALU operation is fixed-point, the inputs are treated as 32-bit fixed-point operands. The ALU transfers the upper 32 bits from the source location in the register file. For fixed-point operations, the result(s) are always 32-bit fixed-point values. Some floating-point operations (Logb, Mant and Fix) can also yield fixed-point results. The processor transfers fixed-point results to the upper 32 bits of the data register and clears the lower eight bits of the register. The format of fixed-point operands and results depends on the operation. In most arithmetic operations, there is no need to distinguish between integer and fractional formats. Fixed-point inputs to operations such as scaling a floating-point value are treated as integers. For purposes of determining status such as overflow, fixed-point arithmetic operands and results are treated as twos-complement numbers.

ALU Saturation
When the ALUSAT bit is set (1) in the MODE1 register, the ALU is in saturation mode. In this mode, all positive fixed-point overflows return the maximum positive fixed-point number (0x7FFF FFFF), and all negative overflows return the maximum negative number (0x8000 0000). When the ALUSAT bit is cleared (0) in the MODE1 register, fixed-point results that overflow are not saturated; the upper 32 bits of the result are returned unaltered. The ALU overflow flag reflects the ALU result before saturation.

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Processing Elements

ALU Status Flags

ALU operations update seven status flags in the processing elements Arithmetic Status (ASTATx and ASTATy) register. Table A-4 on page A-18 lists all the bits in these registers. The following bits in ASTATx or ASTATy flag ALU status (a 1 indicates the condition) for the most recent ALU operation: ALU result zero or floating-point underflow. Bit 0 (AZ) ALU overflow. Bit 1 (AV) ALU result negative. Bit 2 (AN) ALU fixed-point carry. Bit 3 (AC) ALU X input sign for Abs, Mant operations. Bit 4 (AS) ALU floating-point invalid operation. Bit 5 (AI) Last ALU operation was a floating-point operation. Bit 10 (AF) Compare Accumulation register results of last 8 compare operations. Bits 31-24 (CACC) ALU operations also update four sticky status flags in the processing elements Sticky status (STKYx and STKYy) register. Sticky Status Registers (STKYx and STKYy) on page A-18 lists all the bits in these registers. The following bits in STKYx or STKYy flag ALU status (a 1 indicates the condition). Once set, a sticky flag remains high until explicitly cleared: ALU floating-point underflow. Bit 0 (AUS) ALU floating-point overflow. Bit 1 (AVS) ALU fixed-point overflow. Bit 2 (AOS) ALU floating-point invalid operation. Bit 5 (AIS)

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Arithmetic Logic Unit (ALU)

Flag update occurs at the end of the cycle in which the status is generated and is available on the next cycle. If a program writes the arithmetic status register or sticky status register explicitly in the same cycle that the ALU is performing an operation, the explicit write to the status register supersedes any flag update from the ALU operation.

ALU Instruction Summary

Table 2-1 and Table 2-2 list the ALU instructions and how they relate to ASTATx,y and STKYx,y flags. For more information on assembly language syntax, see the ADSP-21160 SHARC DSP Instruction Set Reference. In these tables, note the meaning of the following symbols. Rn, Rx, Ry indicate any register file location; treated as fixed-point Fn, Fx, Fy indicate any register file location; treated as floating-point * indicates the flag may be set or cleared, depending on results of instruction ** indicates the flag may be set (but not cleared), depending on results of instruction indicates no effect

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Processing Elements

Table 2-1. Fixed-Point ALU Instruction Summary

Instruction Fixed-Point: ASTATx,y Status Flags A Z AV A N A C AS AI AF STKYx,y Status Flags C A C C * * A AV A US S O S - - ** ** ** ** -** ** ** ** ** ** AI S

Rn = Rx + Ry Rn = Rx Ry Rn = Rx + Ry + CI Rn = Rx Ry + CI 1 Rn = (Rx + Ry)/2 COMP(Rx, Ry) COMPU(Rx,Ry) Rn = Rx + CI Rn = Rx + CI 1 Rn = Rx + 1 Rn = Rx 1 Rn = Rx Rn = ABS Rx Rn = PASS Rx Rn = Rx AND Ry Rn = Rx OR Ry Rn = Rx XOR Ry Rn = NOT Rx Rn = MIN(Rx, Ry) Rn = MAX(Rx, Ry) Rn = CLIP Rx BY Ry

* * * * * * * * * * * * * * * * * * * * *

* * * * 0 0 0 * * * * * * 0 0 0 0 0 0 0 0

* * * * * * * * * * * * 0 * * * * * * * *

* * * * * 0 0 * * * * * 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 * 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Arithmetic Logic Unit (ALU)

Table 2-2. Floating-Point ALU Instruction Summary

Instruction FloatingPoint: Fn = Fx + Fy Fn = Fx Fy Fn = ABS (Fx + Fy) Fn = ABS (Fx Fy) Fn = (Fx + Fy)/2 COMP(Fx, Fy) Fn = Fx Fn = ABS Fx Fn = PASS Fx Fn = RND Fx Fn = SCALB Fx BY Ry Rn = MANT Fx Rn = LOGB Fx Rn = FIX Fx BY Ry Rn = FIX Fx Fn = FLOAT Rx BY Ry Fn = FLOAT Rx Fn = RECIPS Fx Fn = RSQRTS Fx Fn = Fx COPYSIGN Fy Fn = MIN(Fx, Fy) Fn = MAX(Fx, Fy) Fn = CLIP Fx BY Fy ASTATx,y Status Flags AZ * * * * * * * * * * * * * * * * * * * * * * * AV * * * * 0 0 * * 0 * * * * * * * 0 * * 0 0 0 0 AN * * 0 0 * * * 0 * * * 0 * * * * * * * * * * * AC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AS 0 0 0 0 0 0 0 * 0 0 0 * 0 0 0 0 0 0 0 0 0 0 0 AI * * * * * * * * * * * * * * * 0 0 * * * * * * AF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 STKYx,y Status Flags CA CC * AU S ** ** ** ** ** ** ** ** ** ** AV S ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** AO S AIS ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **

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Processing Elements

MultiplyAccumulator (Multiplier)
The multiplier performs fixed-point or floating-point multiplication and fixed-point multiply/accumulate operations. Fixed-point multiply/accumulates are available with either cumulative addition or cumulative subtraction. Multiplier floating-point instructions operate on 32-bit or 40-bit floating-point operands and output 32-bit or 40-bit floating-point results. Multiplier fixed-point instructions operate on 32-bit fixed-point data and produce 80-bit results. Inputs are treated as fractional or integer, unsigned or twos-complement. Multiplier instructions include: Floating-point multiplication Fixed-point multiplication Fixed-point multiply/accumulate with addition, rounding optional Fixed-point multiply/accumulate with subtraction, rounding optional Rounding result register Saturating result register Clearing result register

Multiplier Operation
The multiplier takes two inputs: X input and Y input. These inputs (also known as operands) can be any data registers in the register file. The multiplier can accumulate fixed-point results in the local Multiplier Result (MRF) registers or write results back to the register file. The results in MRF can also be rounded or saturated in separate operations. Floating-point multiplies yield floating-point results, which the multiplier always writes directly to the register file.

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MultiplyAccumulator (Multiplier)

The multiplier transfers input operands during the first half of the cycle and transfers results during the second half of the cycle. With this arrangement, the multiplier can read and write the same register file location in a single cycle. For fixed-point multiplies, the multiplier reads the inputs from the upper 32 bits of the data registers. Fixed-point operands may be either both in integer format or both in fractional format. The format of the result matches the format of the inputs. Each fixed-point operand may be either an unsigned or a twos-complement number. If both inputs are fractional and signed, the multiplier automatically shifts the result left one bit to remove the redundant sign bit. The register name(s) within the multiplier instruction specify input data type(s)Fx for floating-point and Rx for fixed-point.

Multiplier (Fixed-Point) Result Register

Fixed-point operations place 80-bit results in the multipliers foreground MRF register or background MRB register, depending on which is active. For more information on selecting the result register, see Alternate (Secondary) Data Registers on page 2-32. The location of a result in the MRF registers 80-bit field depends on whether the result is in fractional or integer format, as shown in Figure 2-2. If the result is sent directly to a data register, the 32-bit result with the same format as the input data is transferred, using bits 63-32 for a fractional result or bits 31-0 for an integer result. The eight LSBs of the 40-bit register file location are zero-filled.

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Processing Elements

79

63

31

MRF2

MRF1

MRF0

OVERFLOW

FRACTIONAL RESULT

UNDERFLOW

OVERFLOW

OVERFLOW

INTEGER RESULT

Figure 2-2. Multiplier Fixed-Point Result Placement Fractional results can be rounded-to-nearest before being sent to the register file. If rounding is not specified, discarding bits 31-0 effectively truncates a fractional result (rounds to zero). For more information on rounding, see Rounding Mode on page 2-7. The MRF register is divided into MRF2, MRF1, and MRF0 registers, which can be individually read from or written to the register file. Each of these registers has the same format. When data is read from MRF2, it is sign-extended to 32 bits as shown in Figure 2-3. The processor zero fills the eight LSBs of the 40-bit register file location when data is read from MRF2, MRF1, or MRF0 to the register file. When the processor writes data into MRF2, MRF1, or MRF0 from the 32 MSBs of a register file location, the eight LSBs are ignored. Data written to MRF1 is sign-extended to MRF2, repeating the MSB of MRF1 in the 16 bits of MRF2. Data written to MRF0 is not sign-extended.

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MultiplyAccumulator (Multiplier)

16 BITS SI GN EXTE ND

16 BITS

16 BITS ZEROS

MRF2

32 BI TS

8 BITS ZEROS

MRF1

32-BITS

8-BITS ZEROS

MRF0

Figure 2-3. MR Transfer Formats In addition to multiplication, fixed-point operations include accumulation, rounding and saturation of fixed-point data. There are three MRF register operations: Clear, Round, and Saturate. The clear operationMRF=0resets the specified MRF register to zero. Often, it is best to perform this operation at the start of a multiply/accumulate operation to remove results left over from the previous operation. The rounding operationMRF=Rnd MRFapplies only to fractional results, so integer results are not effected. This operation rounds the 80-bit MRF value to nearest at bit 32; for example, the MRF1-MRF0 boundary. Rounding of a fixed-point result occurs either as part of a multiply or multiply/accumulate operation or as an explicit operation on the MRF register. The rounded result in MRF1 can be sent either to the register file or back to the same MRF register. To round a fractional result to zero (truncation) instead of to nearest, a program would transfer the unrounded result from MRF1, discarding the lower 32 bits in MRF0. The saturate operationMRF=Sat MRFsets MRF to a maximum value if the MRF value has overflowed. Overflow occurs when the MRF value is greater than the maximum value for the data formatunsigned or twos-complement and integer or fractionalas specified in the saturate instruction.

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The six possible maximum values appear in Table 2-3. The result from MRF saturation can be sent either to the register file or back to the same MRF register. Table 2-3. Fixed-Point Format Maximum Values (For Saturation)
Maximum Number (Hexadecimal) MRF2 2s complement fractional (positive) 2s complement fractional (negative) 2s complement integer (positive) 2s complement integer (negative) Unsigned fractional number Unsigned integer number 0000 FFFF 0000 FFFF 0000 0000 MRF1 7FFF FFFF 8000 0000 0000 0000 FFFF FFFF FFFF FFFF 0000 0000 MRF0 FFFF FFFF 0000 0000 7FFF FFFF 8000 0000 FFFF FFFF FFFF FFFF

Multiplier Status Flags

Multiplier operations update four status flags in the processing elements arithmetic status register (ASTATx and ASTATy). Table A-5 on page A-19 lists all the bits in these registers. The following bits in ASTATx or ASTATy flag multiplier status (a 1 indicates the condition) for the most recent multiplier operation. Multiplier result negative. Bit 6 (MN) Multiplier overflow. Bit 7 (MV) Multiplier underflow. Bit 8 (MU) Multiplier floating-point invalid operation. Bit 9 (MI)

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MultiplyAccumulator (Multiplier)

Multiplier operations also update four sticky status flags in the processing elements Sticky status ( STKYx and STKYy) register. Table A-5 on page A-19 lists all the bits in these registers. The following bits in STKYx or STKYy flag multiplier status (a 1 indicates the condition). Once set, a sticky flag remains high until explicitly cleared: Multiplier fixed-point overflow. Bit 6 (MOS) Multiplier floating-point overflow. Bit 7 (MVS) Multiplier underflow. Bit 8 (MUS) Multiplier floating-point invalid operation. Bit 9 (MIS) Flag update occurs at the end of the cycle in which the status is generated and is available on the next cycle. If a program writes the arithmetic status register or sticky register explicitly in the same cycle that the multiplier is performing an operation, the explicit write to ASTAT or STKY supersedes any flag update from the multiplier operation.

Multiplier Instruction Summary

Table 2-4 and Table 2-6 list the Multiplier instructions and how they relate to ASTATx,y and STKYx,y flags. For more information on assembly language syntax, see the ADSP-21160 SHARC DSP Instruction Set Reference. In these tables, note the meaning of the following symbols. Rn, Rx, Ry indicate any register file location; treated as fixed-point Fn, Fx, Fy indicate any register file location; treated as floating-point * indicates the flag may be set or cleared, depending on results of instruction ** indicates the flag may be set (but not cleared), depending on results of instruction

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indicates no effect The Input Mods column indicates the types of optional modifiers that you can apply to the instructions inputs. For a list of modifiers, see Table 2-5. Table 2-4. Fixed-Point Multiplier Instruction Summary
Instruction Fixed-Point: For Input Mods, see Table 2-5 Rn = Rx * Ry MRF = Rx * Ry MRB = Rx * Ry Rn = MRF + Rx * Ry Rn = MRB + Rx * Ry MRF = MRF + Rx * Ry MRB = MRB + Rx * Ry Rn = MRF Rx * Ry Rn = MRB Rx * Ry MRF = MRF Rx * Ry MRB = MRB Rx * Ry Rn = SAT MRF Rn = SAT MRB MRF = SAT MRF MRB = SAT MRB Rn = RND MRF Rn = RND MRB MRF = RND MRF MRB = RND MRB MRF = 0 Input Mods ASTATx,y Flags MU MN MV MI STKYx,y Flags MUS MOS MVS MIS

1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 3 3 3 3

* * * * * * * * * * * * * * * * * * *

* * * * * * * * * * * * * * * * * * *

* * * * * * * * * * * * * * * * * * *

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **

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MultiplyAccumulator (Multiplier)

Table 2-4. Fixed-Point Multiplier Instruction Summary (Contd)

Instruction Fixed-Point: For Input Mods, see Table 2-5 MRB = 0 MRxF = Rn MRxB = Rn Rn = MRxF Rn = MRxB Input Mods ASTATx,y Flags MU MN MV MI STKYx,y Flags MUS MOS MVS MIS

Table 2-5. Input Modifiers For Fixed-Point Multiplier Instruction

Input Mods from Table 2-4 Input ModsOptions For Fixed-point Multiplier Instructions Note the meaning of the following symbols in this table: SSigned input UUnsigned input IInteger input(s) FFractional input(s) FRFractional inputs, Rounded output Note that (SF) is the default format for 1-input operations, and (SSF) is the default format for 2-input operations 1 2 3 (SSF), (SSI), (SSFR), (SUF), (SUI), (SUFR), (USF), (USI), (USFR), (UUF), (UUI), or (UUFR) (SF), (SI), (UF), or (UI) (SF) or (UF)

Table 2-6. Floating-Point Multiplier Instruction Summary

Instruction Floating-Point: Fn = Fx * Fy ASTATx,y Flags MU * MN * MV * MI * STKYx,y Flags MUS MOS MVS ** ** MIS **

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Barrel-Shifter (Shifter)
The shifter performs bit-wise operations on 32-bit fixed-point operands. Shifter operations include: Shifts and rotates from off-scale left to off-scale right Bit manipulation operations, including bit set, clear, toggle, and test Bit field manipulation operations, including extract and deposit Fixed-point/floating-point conversion operations, including exponent extract, number of leading 1s or 0s

Shifter Operation
The shifter takes from one to three inputs: X-input, Y-input, and Z-input. The inputs (also known as operands) can be any register in the register file. Within a shifter instruction, the inputs serve as follows. The X-input provides data that is operated on The Y-input specifies shift magnitudes, bit field lengths or bit positions The Z-input provides data that is operated on and updated In the following example, Rx is the X-input, Ry is the Y-input, and Rn is the Z-input. The shifter returns one output (Rn) to the register file.
Rn = Rn OR LSHIFT Rx BY Ry;

As shown in Figure 2-4, the shifter fetches input operands from the upper 32 bits of a register file location (bits 39-8) or from an immediate value in the instruction. The shifter transfers operands during the first half of the cycle and transfers the result to the upper 32 bits of a register (with the

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Barrel-Shifter (Shifter)

eight LSBs zero-filled) during the second half of the cycle. With this arrangement, the shifter can read and write the same register file location in a single cycle. The X-input and Z-input are always 32-bit fixed-point values. The Y-input is a 32-bit fixed-point value or an 8-bit field (shf8), positioned in the register file. These inputs appear in Figure 2-4. Some shifter operations produce 8-bit or 6-bit results. As shown in Figure 2-5, the shifter places these results in either the shf8 field or the bit6 field and sign-extends the results to 32 bits. The shifter always returns a 32-bit result.
39 7 0

32-BIT Y-INPUT OR RESULT

39

15 SHF8 8-BIT Y-INPUT OR RESULT

Figure 2-4. Register File Fields for Shifter Instructions The shifter supports bit field deposit and bit field extract instructions for manipulating groups of bits within an input. The Y-input for bit field instructions specifies two 6-bit values: bit6 and len6, which are positioned in the Ry register as shown in Figure 2-5. The shifter interprets bit6 and

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Processing Elements

len6 as positive integers. Bit6 is the starting bit position for the deposit or extract, and len6 is the bit field length, which specifies how many bits are deposited or extracted.
39 R2 32 24 16 8 0

00000000

00000000

000000 10
len6

00010000
bit6

00000000
len6 = 8 bit6 = 16

0x0000 0210 00

39 R1

32

24

16

00000000

00000000
16

00000000
8

11111111
0

0 0 0 0 0 0 0 0 0x0000 00FF 00

39 R0

32

24

16

00000000

11111111
16

00000000
8

00000000
0
Reference point

00000000

0x00FF 0000 00

Starting bit position for deposit

Figure 2-5. Register File Fields for FDEP, FEXT Instructions Field deposit (Fdep) instructions take a group of bits from the input register (starting at the LSB of the 32-bit integer field) and deposit the bits as directed anywhere within the result register. The bit6 value specifies the starting bit position for the deposit. Figure 2-7 shows how the inputs, bit6 and len6, work in an field deposit instruction (Rn=Fdep Rx By Ry). Figure 2-8 shows bit placement for the field deposit instruction R0 = FDEP R1 BY R2;. Field extract (Fext) instructions extract a group of bits as directed from anywhere within the input register and place them in the result register (aligned with the LSB of the 32-bit integer field). The bit6 value specifies the starting bit position for the extract. Figure 2-8 shows bit placement for the following field extract instruction R3 = FEXT R4 BY R5;

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Barrel-Shifter (Shifter)

39 R2

32

24

16

00000000

00000000

000000 10
len6

00010000
bit6

00000000
len6 = 8 bit6 = 16

0x0000 0210 00

39 R1

32

24

16

00000000

00000000
16

00000000
8

11111111
0

00000000

0x0000 00FF 00

39 R0

32

24

16

00000000

11111111
16

00000000
8

00000000
0
Reference point

00000000

0x00FF 0000 00

Starting bit position for deposit

Figure 2-6. Bit Field Deposit Example

39 19 LEN6 13 BIT6 7 0

RY

RY DETERMINES LENGTH OF BIT FIELD TO TAKE FROM RX AND STARTING POSITION FOR DEPOSIT IN RN

39

RX
LEN6 = NUMBER OF BITS TO TAKE FROM RX, STARTING FROM LSB OF 32-BIT FIELD

39

7 DEPOSIT FIELD

RN

BIT6 BIT6 = STARTING BIT POSITION FOR DEPOSIT, REFERENCED FROM LSB OF 32-BIT FIELD

REFERENCE POINT

Figure 2-7. Bit Field Deposit Instruction

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Processing Elements

39 R5

32

24

16

0 0x0000 0217 00

00000000

00000000

00000010
len6

000 1 0 1 1 1 00000000 010111

bit6 len6 = 8 bit6 = 23 8 0

39 R4

32

24

16

10000111

1 0000000
16

00000000
8

00000000
0

0 0 0 0 0 0 0 0 0x8710 0000 00

Starting bit position for deposit 39 R3 32 24 16

Reference point

00000000

00000000
16

00000000
8

00001111
0

00000000

0x0000 000F 00

Figure 2-8. Bit Field Extract Example

Shifter Status Flags

Shifter operations update three status flags in the processing elements arithmetic status register (ASTATx and ASTATy). Table A-4 on page A-13 lists all the bits in these registers. The following bits in ASTATx or ASTATy indicate shifter status (a 1 indicates the condition) for the most recent ALU operation: Shifter overflow of bits to left of MSB. Bit 11 (SV) Shifter result zero. Bit 12 (SZ) Shifter input sign for exponent extract only. Bit 13 (SS) Flag update occurs at the end of the cycle in which the status is generated and is available on the next cycle. If a program writes the arithmetic status register explicitly in the same cycle that the shifter is performing an operation, the explicit write to ASTAT supersedes any flag update caused by the shift operation.

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Barrel-Shifter (Shifter)

Shifter Instruction Summary

Table 2-7 lists the Shifter instructions and how they relate to ASTATx,y flags. For more information on assembly language syntax, see the ADSP-21160 SHARC DSP Instruction Set Reference. In these tables, note the meaning of the following symbols: Rn, Rx, Ry indicate any register file location; bit fields used depend on instruction Fn, Fx indicate any register file location; floating-point word * indicates the flag may set or cleared, depending on data Table 2-7. Shifter Instruction Summary
Instruction ASTATx,y Flags SZ Rn = LSHIFT Rx BY Ry Rn = LSHIFT Rx BY <data8> Rn = Rn OR LSHIFT Rx BY Ry Rn = Rn OR LSHIFT Rx BY <data8> Rn = ASHIFT Rx BY Ry Rn = ASHIFT Rx BY<data8> Rn = Rn OR ASHIFT Rx BY Ry Rn = Rn OR ASHIFT Rx BY <data8> Rn = ROT Rx BY Ry Rn = ROT Rx BY <data8> Rn = BCLR Rx BY Ry Rn = BCLR Rx BY <data8> Rn = BSET Rx BY Ry Rn = BSET Rx BY <data8> Rn = BTGL Rx BY Ry * * * * * * * * * * * * * * * SV * * * * * * * * 0 0 * * * * * SS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 2-7. Shifter Instruction Summary (Contd)

Instruction ASTATx,y Flags SZ Rn = BTGL Rx BY <data8> BTST Rx BY Ry BTST Rx BY <data8> Rn = FDEP Rx BY Ry Rn = FDEP Rx BY <bit6>:<len6> Rn = Rn OR FDEP Rx BY Ry Rn = Rn OR FDEP Rx BY <bit6>:<len6> Rn = FDEP Rx BY Ry (SE) Rn = FDEP Rx BY <bit6>:<len6> (SE) Rn = Rn OR FDEP Rx BY Ry (SE) Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE) Rn = FEXT Rx BY Ry Rn = FEXT Rx BY <bit6>:<len6> Rn = FEXT Rx BY Ry (SE) Rn = FEXT Rx BY <bit6>:<len6> (SE) Rn = EXP Rx (EX) Rn = EXP Rx Rn = LEFTZ Rx Rn = LEFTO Rx Rn = FPACK Fx Fn = FUNPACK Rx * * * * * * * * * * * * * * * * * * * 0 0 SV * * * * * * * * * * * * * * * 0 0 * * * 0 SS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * 0 0 0 0

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Data Register File

Data Register File

Each of the processors processing elements has a data register file: a set of data registers that transfer data between the data buses and the computation units. These registers also provide local storage for operands and results. The two register files each consist of 16 primary registers and 16 alternate (secondary) registers. All of the data registers are 40 bits wide. Within these registers, 32-bit data is always left-justified. If an operation specifies a 32-bit data transfer to these 40-bit registers, the eight LSBs are ignored on register reads, and the eight LSBs are cleared to zeros on writes. Program memory data accesses and data memory accesses to/from the register file(s) occur on the PM data bus and DM data bus, respectively. One PM data bus access for each processing element and/or one DM data bus access for each processing element can occur in one cycle. Transfers between the register files and the DM or PM data buses can move up to 64-bits of valid data on each bus. If an operation specifies the same register file location as both an input and output, the read occurs in the first half of the cycle and the write in the second half. With this arrangement, the processor uses the old data as the operand, before updating the location with the new result data. If writes to the same location take place in the same cycle, only the write with higher precedence actually occurs. The processor determines precedence for the write operation from the source of the data; from highest to lowest, the precedence is: 1. Data memory or universal register 2. Program memory 3. PEx ALU 4. PEy ALU

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Processing Elements

5. PEx Multiplier 6. PEy Multiplier 7. PEx Shifter 8. PEy Shifter The data register file in Figure 2-1 on page 2-3 lists register names of R0 through R15 within PExs register file. When a program refers to these registers as R0 through R15, the computational units treat the registers contents as fixed-point data. To perform floating point computations, refer to these registers as F0 through F15. For example, the following instructions refer to the same registers, but direct the computational units to perform different operations:
F0=F1 * F2; /*floating-point multiply*/ R0=R1 * R2; /*fixed-point multiply*/

The F and R prefixes on register names do not effect the 32-bit or 40-bit data transfer; the naming convention only determines how the ALU, multiplier, and shifter treat the data. To maintain compatibility with code written for previous SHARC DSPs, the assembly syntax accommodates references to PEx data registers and PEy data registers. Code may only refer to the PEy data registers (S0 through S15) for data move instructions. The rules for using register names are as follows. through R15 and F0 through F15 always refer to PEx registers for data move and computational instructions, whether the processor is in SISD or SIMD mode
R0

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Alternate (Secondary) Data Registers

through R15 and F0 through F15 refer to both PEx and PEy register for computational instructions in SIMD mode
R0 S0

through S15 always refer to PEy registers for data move instructions, whether the processor is in SISD or SIMD mode

For more information on SISD and SIMD computational operations, see Alternate (Secondary) Data Registers on page 2-32. For more information on ADSP-21161 processor assembly language, see the ADSP-21160 SHARC DSP Instruction Set Reference.

Alternate (Secondary) Data Registers

Each register file has an alternate register set. To facilitate fast context switching, the processor includes alternate register sets for data, results, and data address generator registers. Bits in the MODE1 register control when alternate registers become accessible. While inaccessible, the contents of alternate registers are not effected by processor operations. Note that there is a one cycle latency between writing to MODE1 and being able to access an alternate register set. The alternate register sets for data and results are described in this section. For more information on alternate data address generator registers, see the DAG Alternate (Secondary) Data Registers on page 2-32. Bits in the MODE1 register can activate independent-alternate-data-register sets: the lower half (R0-R7 and S0-S7) and the upper half (R8-R15 and S8-S15). To share data between contexts, a program places the data to be shared in one half of either the current processing elements register file or the opposite processing elements register file and activates the alternate register set of the other half. For information on how to activate alternate data registers, see the description on page 2-33. Each multiplier has a primary or foreground (MRF) register and alternate or background (MRB) results register. A bit in the MODE1 register selects which result register receives the result from the multiplier operation, swapping

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which register is the current MRF or MRB. This swapping facilitates context switching. Unlike other registers that have alternates, both MRF and MRB are accessible at the same time. All fixed-point multiplies can accumulate results in either MRF or MRB, without regard to the state of the MODE1 register. With this arrangement, code can use the result registers as primary and alternate accumulators, or code can use these registers as two parallel accumulators. This feature facilitates complex math. The MODE1 register controls the access to alternate registers. Table A-2 on page A-3 lists all the bits in MODE1. The following bits in MODE1 control alternate registers (a 1 enables the alternate set). Secondary registers for computation unit results. Bit 2 (SRCU) Secondary registers for hi register file, R8-R15 and S8-15. Bit 7 (SRRFH) Secondary registers for lo register file, R0-R7 and S0-S7. Bit 10 (SRRFL) The following example demonstrates how code should handle the one cycle of latency from the instruction setting the bit in MODE1 to when the alternate registers may be accessed. Note that it is possible to use any instruction that does not access the switching register file instead of an NOP instruction.
BIT SET MODE1 SRRFL; NOP; R0=7; /* activate alternate reg. file */ /* wait for access to alternates */

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Multifunction Computations

Multifunction Computations
Using the many parallel data paths within its computational units, the processor supports multiple-parallel (multifunction) computations. These instructions complete in a single cycle, and they combine parallel operation of the multiplier and the ALU or dual ALU functions. The multiple operations perform the same as if they were in corresponding single-function computations. Multifunction computations also handle flags in the same way as the single-function computations, except that in the dual add/subtract computation the ALU flags from the two operations are Ored together. To work with the available data paths, the computation units constrain which data registers may hold the four input operands for multifunction computations. These constraints limit which registers may hold the X-input and Y-input for the ALU and multiplier. Figure 2-9 shows a computational unit and indicates which registers may serve as X-inputs and Y-inputs for the ALU and multiplier. For example, the X-input to the ALU can only be R8, R9, R10 or R11. Note that the shifter is gray in Figure 2-7 to indicate that there are no shifter multifunction operations.

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Processing Elements

MODE1

PM DATA BUS DM DATA BUS

NOTE THAT SHIFTER IS FADED HERE, INDICATING THAT IT IS NOT AVAILABLE FOR MULTIFUNCTION INSTRUCTIONS.

REGISTER FILE (16 40-BIT) R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15

MULTIPLIER

SHIFTER

ALU

MRF2 MRF1 MRF0 ASTATx STKYx

TO PROGRAM SEQUENCER

Figure 2-9. Input Registers for Multifunction Computations (ALU and Multiplier) Table 2-8, through Table 2-11 list the multifunction computations. For more information on assembly language syntax, see the ADSP-21160 SHARC DSP Instruction Set Reference. In these tables, note the meaning of the following symbols. Rm, Ra, Rs, Rx, Ry indicate any register file location; fixed-point Fm, Fa, Fs, Fx, Fy indicate any register file location; floating-point R3-0 indicates data file registers R3, R2, R1, or R0, and F3-0 indicates data file registers F3, F2, F1, or F0

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Multifunction Computations

R7-4 indicates data file registers R7, R6, R5, or R4, and F7-4 indicates data file registers F7, F6, F5, or F4 R11-8 indicates data file registers R11, R10, R9, or R8, and F11-8 indicates data file registers F11, F10, F9, or F8 R15-12 indicates data file registers R15, R14, R13, or R12, and F15-12 indicates data file registers F15, F14, F13, or F12 SSFR indicates the X-input is signed, Y-input is signed, use Fractional inputs, and Rounded-to-nearest output SSF indicates the X-input is signed, Y-input is signed, use Fractional input Table 2-8. Dual Add And Subtract
Ra = Rx + Ry, Rs = Rx Ry Fa = Fx + Fy, Fs = Fx Fy

Table 2-9. Fixed-Point Multiply and Add, Subtract, Or Average

(Any combination of left and right column) Rm=R3-0 * R7-4 (SSFR), MRF=MRF + R3-0 * R7-4 (SSF), Rm=MRF + R3-0 * R7-4 (SSFR), MRF=MRF R3-0 * R7-4 (SSF), Rm=MRF R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Ra=R11-8 R15-12 Ra=(R11-8 + R15-12)/2

Table 2-10. Floating-Point Multiply And ALU Operation

Fm=F3-0 * F7-4, Fa=F11-8 + F15-12 Fm=F3-0 * F7-4, Fa=F11-8 F15-12 Fm=F3-0 * F7-4, Fa=FLOAT R11-8 by R15-12 Fm=F3-0 * F7-4, Ra=FIX F11-8 by R15-12

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Table 2-10. Floating-Point Multiply And ALU Operation (Contd)

Fm=F3-0 * F7-4, Fa=(F11-8 + F15-12)/2 Fm=F3-0 * F7-4, Fa=ABS F11-8 Fm=F3-0 * F7-4, Fa=MAX (F11-8, F15-12) Fm=F3-0 * F7-4, Fa=MIN (F11-8, F15-12)

Table 2-11. Multiply With Dual Add and Subtract

Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12, Rs = R11-8 R15-12 Fm = F3-0 * F7-4, Fa = F11-8 + F15-12, Fs = F11-8 F15-12

Another type of multifunction operation is also available on the processor, combining transfers between the results and data registers and transfers between memory and data registers. Like other multifunction instructions, these parallel operations complete in a single cycle. For example, the processor can perform the following multiply and parallel read of data memory:
MRF=MRF-R5*R0, R6=DM(I1,M2);

Or, the processor can perform the following result register transfer and parallel read:
R5=MR1F, R6=DM(I1,M2);

Secondary Processing Element (PEy)

The ADSP-21161 processor contains two sets of computation units and associated register files. As shown in Figure 2-10, these two Processing Elements (PEx and PEy) support Single Instruction, Multiple Data (SIMD) operation.

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Secondary Processing Element (PEy)

DIF FERENT DATA GO ES T O EA CH ELEMENT

PM DAT A BUS
BUS CONNE CT (PX )

16/32/40/64 16/32/40/64

D M DATA BU S

MUL T

D ATA REGIST ER FIL E ( PEx) 16 x 40-BIT

BARREL SHIFT ER

BARREL SHIF TER

DAT A REGISTER FIL E (PEy) 16 x 40-BIT

MULT

AL U

ALU

SA ME I NST RUCT ION GO ES T O BOT H ELEMENTS

PRO GRAM SEQUENCER

Figure 2-10. Block Diagram Showing Secondary Execution Complex The MODE1 register controls the operating mode of the processing elements. Table A-2 on page A-3 lists all the bits in MODE1. The PEYEN bit (bit 21) in the MODE1 register enables or disables the PEy processing element. When PEYEN is cleared (0), the ADSP-21161 processor operates in Single-Instruction-Single-Data (SISD) mode, using only PEx; this is the mode in which ADSP-2106x family DSPs operate. When the PEYEN bit is set (1), the ADSP-21161 processor operates in SIMD mode, using the PEx and PEy processing elements. There is a one cycle delay after PEYEN is set or cleared, before the change to or from SIMD mode takes effect.

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Processing Elements

To support SIMD, the processor performs the following parallel operations. Dispatches a single instruction to both processing elements computation units Loads two sets of data from memory, one for each processing element Executes the same instruction simultaneously in both processing elements Stores data results from the dual executions to memory Using the information here and in the ADSP-21160 SHARC DSP Instruction Set Reference, it is possible through SIMD modes parallelism to double performance over similar algorithms running in SISD (ADSP-2106x processor compatible) mode. The two processing elements are symmetrical, and each contains the following functional blocks. ALU Multiplier primary and alternate result registers Shifter Data register file and alternate register file

Dual Compute Units Sets

The computation units (ALU, Multiplier, and Shifter) in PEx and PEy are identical. The data bus connections for the dual computation units permit asymmetric data moves to, from, and between the two processing elements. Identical instructions execute on the PEx and PEy computational units; the difference is the data. The data registers for PEy operations are identified (implicitly) from the PEx registers in the instruction. This

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Secondary Processing Element (PEy)

implicit relation between PEx and PEy data registers corresponds to complementary register pairs in Table 2-12. Any universal registers that dont appear in Table 2-12 have the same identities in both PEx and PEy. When a computation in SIMD mode refers to a register in the PEx column, the corresponding computation in PEy refers to the complimentary register in the PEy column. Table 2-12. SIMD Mode Complementary Register Pairs
PEx R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 ASTATx STKYx PEy S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 ASTATy STKYy

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Processing Elements

Table 2-13 lists the multiplier result SIMD mode complementary register pairs. These multiplier result registers are not universal (UREGs) registers and cannot be accessed directly. These registers can be read with the following multiplier operations:
MRxF/B = Rn; Rn = MRxF/B;

Table 2-13. Multiplier Result SIMD Mode Complementary Register Pairs

PEx MRF0 MRF1 MRF2 MRB0 MRB1 MRB2 PEy MSF0 MSF1 MSF2 MSB0 MSB1 MSB2

Table 2-14. Other Complementary Register Pairs

USTAT1 USTAT3 PX1 USTAT2 USTAT4 PX2

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Secondary Processing Element (PEy)

Dual Register Files

The two 16 entry data register files (one in each PE) and their operand and result busing and porting are identical. The same is true for each 16 entry alternate register files. The transfer direction, source and destination registers, and data bus usage depend on the following conditions: Computational mode: Is PEy enabledPEYEN bit=1 in MODE1 register Is the data register file in PEx (R0-R15, F0-F15) or PEy (S0-S15) Is the instruction a data register swap between the processing elements Data addressing mode: What is the state of the Internal Memory Data Width (IMDW) bits in the System Configuration (SYSCON) register Is Broadcast write enabledBDCST1,9 bits in MODE1 register What is the type of addresslong, normal, or short word Is Long Word override (LW) specified in the instruction What are the states of instruction fields for DAG1 or DAG2 Program sequencing (conditional logic): What is the outcome of the instructions condition comparison on each processing element For information on SIMD issues that relate to computational modes, see SIMD (Computational) Operations on page 2-43. For information on SIMD issues relating to data addressing, see SIMD Mode and Sequencing on page 3-57. For information on SIMD issues relating to program sequencing, see Addressing in SISD and SIMD Modes on page 4-18.

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Dual Alternate Registers

Both register files consist of a primary set of 16 by 40-bit registers and an alternate set of 16 by 40-bit registers. Context switching between the two sets of registers occur in parallel between the two processing elements. Alternate (Secondary) Data Registers on page 2-32.

SIMD (Computational) Operations

In SIMD mode, the dual processing elements execute the same instruction, but operate on different data. To support SIMD operation, the elements support a variety of dual data move features. The processor supports unidirectional and bidirectional register-to-register transfers with the conditional compute and move instruction. All four combinations of inter-register file and intra-register file transfers (PEx PEx, PEx PEy, PEy PEx, and PEy PEy) are possible in both SISD (unidirectional) and SIMD (bidirectional) modes. In SISD mode (PEYEN bit=0), the register-to-register transfers are unidirectional, meaning that an operation performed on one processing element is not duplicated on the other processing element. The SISD transfer uses a source register and a destination register, and either register can be in either elements data register file. For a summary of unidirectional transfers, see the upper half of Table 2-15. Note that in SISD mode a condition for an instruction only tests in the PEx element and applies to the entire instruction. In SIMD mode (PEYEN bit=1), the register-to-register transfers are bidirectional, meaning that an operation performed on one element is duplicated in parallel on the other element. The instruction uses two source registers (one from each elements register file) and two destination registers (one from each elements register file). For a summary of bidirectional transfers, see the lower half of Table 2-15. Note that in SIMD mode a

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Secondary Processing Element (PEy)

conditional for an instruction test in both the PEx and PEy elements, dividing control of the explicit and implicit transfers as detailed in Table 2-15. Bidirectional register-to-register transfers in SIMD mode are allowed between a data register and DAG, control, or status registers. When the DAG, control, or status register is a source of the transfer, the destination can be a data register. This SIMD transfer duplicates the contents of the source register in a data register in both processing elements. Careful programming is required when a DAG, control, or status register is a destination of a transfer from a data register. If the destination register has a complement (for example ASTATx and ASTATy), the SIMD transfer moves the contents of the explicit data register into the explicit destination and moves the contents of the implicit data register into the implicit destination (the complement). If the destination register has no complement (for example, I0), only the explicit transfer occurs. Even if the code uses a conditional operation to select whether the transfer occurs, only the explicit transfer can take place if the destination register has no complement. In the case where a DAG, control, or status register is both source and destination, the data move operation executes the same as if SIMD mode were disabled. In both SISD and SIMD modes, the processor supports bidirectional register-to-register swaps. The swap always occurs between one register in each processing elements data register file. Registers swaps use the special swap operator, <->. A register-to-register swap occurs when registers in different processing elements exchange values; for example R0 <-> S1. Only single, 40-bit register to register swaps are supportedno double register operations.

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When they are unconditional, register-to-register swaps operate the same in SISD mode and SIMD mode. If a condition is added to the instruction in SISD mode, the condition tests only in the PEx element and controls the entire operation. If a condition is added in SIMD mode, the condition tests in both the PEx and PEy elements and controls the halves of the operation as detailed in Table 2-15. Table 2-15. Register-To-Register Move Summary (SISD Versus SIMD)
Mode SISD1 Instruction IF condition compute, Rx = Ry; IF condition compute, Rx = Sy; IF condition compute, Sx = Ry; IF condition compute, Sx = Sy; IF condition compute, Rx <-> Sy; SIMD2 IF condition compute, Rx = Ry; IF condition compute, Rx = Sy; IF condition compute, Sx = Ry; IF condition compute, Sx = Sy; IF condition compute, Rx <-> Sy;3 1 Explicit Transfer Rx loaded from Ry Rx loaded from Sy Sx loaded from Ry Sx loaded from Sy Rx swaps to Sy Sy swaps to Rx Rx loaded from Ry Rx loaded from Sy Sx loaded from Ry Sx loaded from Sy Rx swaps to Sy Sy swaps to Rx Implicit Transfer None None None None None Sx loaded from Sy Sx loaded from Ry Rx loaded from Sy Rx loaded from Ry None

In SISD mode, the conditional applies only to the entire operation and is only tested against PExs flags. When the condition tests true, the entire operation occurs. 2 In SIMD mode, the conditional applies separately to the explicit and implicit transfers. Where the condition tests true (PEx for the explicit and PEy for the implicit), the operation occurs in that processing element. 3 Register to register transfers (R0=S0) and register swaps (R0<->S0) do not cause a PMD bus conflict. These operations use only the DMD bus and a hidden 16-bit bus to do the two register moves.

SIMD conditional instructions with the same destination registers do not produce predictable transfers. For example, the instruction IF EQ R4 = R14 R15, S4 = R6; may not work as expected. This kind of usage is prohibited, as it is not logical to use it this way.

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Secondary Processing Element (PEy)

SIMD And Status Flags

When the processor is in SIMD mode (PEYEN bit=1), computations on both processing elements generate status flags, producing a logical Oring of the exception status test on each processing element. If one of the four fixed-point or floating-point exceptions is enabled, an exception condition on either or both processing elements generates an exception interrupt. Interrupt service routines must determine which of the processing elements encountered the exception. Note that returning from a floating point interrupt does not automatically clear the STKY state. Code must clear the STKY bits in both processing elements sticky status (STKYx and STKYy) registers as part of the exception service routine. For more information, see Interrupts and Sequencing on page 3-34.

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3 PROGRAM SEQUENCER

The processors program sequencer implements program flow which constantly provides the address of the next instruction to be executed by other parts of the processor. Program flow in the processor is mostly linear, with the processor executing program instructions sequentially. This linear flow varies occasionally when the program uses non-sequential program structures, such as those illustrated in Figure 3-1. Non-sequential structures direct the processor to execute an instruction that is not at the next sequential address following the current instruction. These structures include: Loops. One sequence of instructions executes several times with zero overhead. Subroutines. The processor temporarily interrupts sequential flow to execute instructions from another part of program memory. Jumps. Program flow transfers permanently to another part of program memory. Interrupts. Subroutines in which a runtime event (not an instruction) triggers the execution of the routine. Idle. An instruction that causes the processor to cease operations and hold its current state until an interrupt occurs. Then, the processor services the interrupt and continues normal execution.

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The sequencer manages execution of these program structures by selecting the address of the next instruction to execute. As part of its process, the sequencer handles the following tasks: Increments the fetch address Maintains stacks Evaluates conditions Decrements the loop counter Calculates new addresses Maintains an instruction cache Handles interrupts To accomplish these tasks, the sequencer uses the blocks shown in Figure 3-2. The sequencers address multiplexer selects the value of the next fetch address from several possible sources. The fetched address enters the instruction pipeline, made up of the fetch address register, decode address register, and program counter (PC). These contain the 24-bit addresses of the instructions currently being fetched, decoded, and executed. The PC couples with the PC stack, which stores return addresses and top-of-loop addresses. All addresses generated by the sequencer are 24-bit program memory instruction addresses. To manage events, the sequencers interrupt controller handles interrupt processing, determines whether an interrupt is masked, and generates the appropriate interrupt vector address. With selective caching, the instruction cache lets the processor access data in program memory and fetch an instruction (from the cache) in the same cycle. The DAG2 data address generator outputs program memory data addresses.

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Program Sequencer

LINEAR FLOW
ADDRESS: N N+1 N+2 N+3 N+4 N+5 INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION

LOOP
DO UNTIL INSTRUCTION INSTRUCTION INSTRUCTION N TIMES INSTRUCTION INSTRUCTION

JUMP
JUMP INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION

SUBROUTINE
IRQ CALL INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION RTS

INTERRUPT
INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION RTI VECTOR

IDLE
IDLE INSTRUCTION WAITING FOR IRQ INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION

Figure 3-1. Program Flow Variations The sequencer evaluates conditional instructions and loop termination conditions by using information from the status registers. The loop address stack and loop counter stack support nested loops. The status stack stores status registers for implementing nested interrupt routines. Table 3-1 and Table 3-2 list the registers within and related to the program sequencer. All registers in the program sequencer are universal registers, so they are accessible to other universal registers and to data memory. All the sequencers registers and the tops of stacks are readable,

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MODE1

MODE2

STKYX

ASTATX

A STATY

STKYY

U STAT1

U STAT2

USTAT3

US TAT4

TPERIOD

INPUT FLAGS LOOP ADDRESS STACK (LADDR)

INSTRUCTION CACHE

MULTIPLEXER

INS TRUCTI ON LATCH

TCOUNT

CONDITION LOGIC

LOOP COUNT STACK (CURLCNTR, LC NTR)

DEC REMENT

LOOP CONTROL BRANCH CONTROL ADDRESS FROM DAG2

TCOUNT=0 NO OTHER INTERRUPTS INTERRUPT CONTROLLER INTERRUPT LATC H (IRPTL) INTERRUPT MASK (IMASK) INTERRUPT MASK POINTER (IMA SKP) INTERRUPT VE CTOR

YES

TIME XP INS TRUCTI ON PIPE LINE PROGRAM COUNTER STACK FETCH ADDRESS (FADDR) DEC ODE PROGRAM ADDRESS COUNTER (DADDR) (PC) PC-RELATIVE ADDRESS +1 NEXT ADDRES S (LINE AR FLOW ) +

TOP OF PC STACK (PCS TK) PC STACK POINTE R (PCS TKP) REPE ATED ADDRESS (IDLE)

RE TURN ADDRESS OR TOP OF LOOP

DIRECT BRANCH

INDI RE CT BRANCH

32

32

N EXT ADDRE SS MU LTIPLEXER 24

32

DM DATA BUS

PM ADDRESS BUS

PM DATA BUS

Figure 3-2. Sequencer Block Diagram

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Program Sequencer

and all these registers are writable, except for the fetch address, decode address, and PC. Pushing or popping the PC stack is done with a write to the PC stack pointer, which is readable and writable. Pushing or popping the loop address stack requires explicit instructions. A set of system control registers configures or provides input to the sequencer. These registers appear across the top and within the interrupt controller shown in Figure 3-2. A bit manipulation instruction permits setting, clearing, toggling, or testing specific bits in the system registers. For information on this instruction (Bit), see the ADSP-21160 SHARC DSP Instruction Set Reference. Writes to some of these registers do not take effect on the next cycle. For example, after a write to the MODE1 register to enable ALU saturation mode, the change does not take effect until two cycles after the write. Also, some of these registers do not update on the cycle immediately following a write. An extra cycle is required before a read of the register returns the new value. With the lists of sequencer and system registers, Table 3-1 and Table 3-2 summarize the number of extra cycles (latency) for a write to take effect (effect latency) and for a new value to appear in the register (read latency). A 0 indicates that the write takes effect or appears in the register on the next cycle after the write instruction is executed, and a 1 indicates one extra cycle. Table 3-1. Program Sequencer Registers Read and Effect Latencies
Register FADDR DADDR PC PCSTK PCSTKP LADDER Contents fetch address decode address execute address top of PC stack PC stack pointer top of loop address stack Bits 24 24 24 24 5 32 Read Latency 0 1 0 Effect Latency 0 1 0

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Table 3-1. Program Sequencer Registers Read and Effect Latencies (Contd)
Register CURLCNTR LCNTR Contents top of loop count stack (current loop count) Bits 32 Read Latency 0 0 Effect Latency 0 0

loop count for next DO UNTIL loop 32

Table 3-2. System Registers Read and Effect Latencies

Register Contents Bits Read Latency Maximum Effect Latency 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0

MODE1 MODE2 IRPTL IMASK IMASKP MMASK FLAGS LIRPTL ASTATX ASTATY STKYX STKYY USTAT1 USTAT2 USTAT3 USTAT4

mode control bits mode control bits interrupt latch interrupt mask

32 32 32 32

interrupt mask pointer (for nest- 32 ing) mode mask flag inputs link port interrupt latch/mask arithmetic status flags arithmetic status flags sticky status flags sticky status flags user-defined status flags user-defined status user-defined status user-defined status 32 32 32 32 32 32 32 32 32 32 32

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The following sections in this chapter explain how to use each of the functional blocks in Figure 3-2: Instruction Pipeline on page 3-7 Instruction Cache on page 3-8 Branches and Sequencing on page 3-13 Loops and Sequencing on page 3-22 Interrupts and Sequencing on page 3-34 Timer and Sequencing on page 3-50 Stacks and Sequencing on page 3-52 Conditional Sequencing on page 3-53 SIMD Mode and Sequencing on page 3-57

Instruction Pipeline
The program sequencer determines the next instruction address by examining both the current instruction being executed and the current state of the processor. If no conditions require otherwise, the processor executes instructions from program memory in sequential order by incrementing the fetch address. Using its instruction pipeline, the processor processes instructions in three clock cycles: Fetch cycle. The processor reads the instruction from either the on-chip instruction cache or from program memory. Decode cycle. The processor decodes the instruction, generating conditions that control instruction execution. Execute cycle. The processor executes the instruction; the operations specified by the instruction complete in a single cycle.

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Instruction Cache

These cycles overlap in the pipeline, as shown in Table 3-3. In sequential program flow, when one instruction is being fetched, the instruction fetched in the previous cycle is being decoded, and the instruction fetched two cycles before is being executed. Sequential program flow always has a throughput of one instruction per cycle. Table 3-3. Pipelined Execution Cycles
Cycles 1 2 3 4 5 Fetch 0x08 0x09 0x0A 0x0B 0x0C 0x08 0x09 0x0A 0x0B 0x08 0x09 0x0A Decode Execute

Any non-sequential program flow can potentially decrease the processors instruction throughput. Non-sequential program operations include: Program memory data accesses that conflict with instruction fetches Jumps Subroutine calls and returns Interrupts and return Loops

Instruction Cache
Usually, the sequencer fetches an instruction from memory on each cycle. Occasionally, bus constraints prevent some of the data and instructions from being fetched in a single cycle. To alleviate these data flow con-

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straints, the processor has an instruction cache, which appears in Figure 3-2. When the processor executes an instruction that requires data access over the PM data bus, a bus conflict occurs because the sequencer uses the PM data bus for fetching instructions. To avoid these conflicts, the processor caches these instructions, reducing delays. Except for enabling or disabling the cache, its operation requires no user intervention. For more information, see Using the Cache on page 3-11. When the processor first encounters a fetch conflict, the processor must wait to fetch the instruction on the following cycle, causing a delay. The processor automatically writes the fetched instruction to the cache to prevent the same delay from happening again. The sequencer checks the instruction cache on every program memory data access. If the instruction needed is in the cache, the instruction fetch from the cache happens in parallel with the program memory data access, without incurring a delay. Because of the three-stage instruction pipeline, as the processor executes an instruction (at address n) that requires a program memory data access, this execution creates a conflict with the instruction fetch (at address n+2), assuming sequential execution. The cache stores the fetched instruction (n+2), not the instruction requiring the program memory data access. If the instruction needed to avoid a conflict is in the cache, the cache provides the instruction while the program memory data access is performed. If the needed instruction is not in the cache, the instruction fetch from memory takes place in the cycle following the program memory data access, incurring one cycle of overhead. The fetched instruction is loaded into the cache, if the cache is enabled and not frozen, so that it is available the next time the same conflict occurs. Figure 3-3 shows a block diagram of the instruction cache. The cache holds 32 instuction-address pairs. These pairs (or cache entries) are arranged into 16 (15-0) cache sets according to their address 4 least significant bits (3-0). The two entries in each set (entry 0 and entry 1) have a

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Instruction Cache

valid bit, indicating whether the entry contains a valid instruction. The least recently used (LRU) bit for each set indicates which entry was not used last (0=entry 0 and 1=entry 1).
LRU VALID BIT BIT SET 0 ENTRY 0 ENTRY 1 SET 1 ENTRY 0 ENTRY 1 SET 2 ENTRY 0 ENTRY 1 0010 0001 INSTRUCTIONS ADDRESSES BITS (23-4) ADDRESSES BITS (3-0) 0000

SET 13 ENTRY 0 ENTRY 1 SET 14 ENTRY 0 ENTRY 1 SET 15 ENTRY 0 ENTRY 1

1101

1110

1111

Figure 3-3. Instruction Cache Architecture The cache places instructions in entries according to the 4 LSBs of the instructions address. When the sequencer checks for an instruction to fetch from the cache, it uses the 4 address LSBs as an index to a cache set. Within that set, the sequencer checks the addresses of the two entries, looking for the needed instruction. If the cache contains the instruction, the sequencer uses the entry and updates the LRU bit (if necessary) to indicate the entry did not contain the needed instruction. When the cache does not contain a needed instruction, the cache loads a new instruction and its address, placing these in the least recently used entry of the appropriate cache set and toggling the LRU bit (if necessary).

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Using the Cache

After a processor reset, the cache starts cleared (containing no instructions), unfrozen, and enabled. From then on, the MODE2 register controls the operating mode of the instruction cache. Table A-3 on page A-10 lists all the bits in MODE2. The following bits in MODE2 control cache modes: Cache Disable. Bit 4 (CADIS) directs the sequencer to disable the cache (if 1) or enable the cache (if 0). Disabling the cache does not mark the current content of the cache as invalid. If the cache is enabled again, the existing content is used again. To clear the cache, use the FLUSH CACHE instruction. Cache Freeze. Bit 19 (CAFRZ) directs the sequencer to freeze the contents of the cache (if 1) or let new entries displace the entries in the cache (if 0). If self-modifying code (for example, software loader kernel) or software overlays are used, execute a FLUSH CACHE instruction followed by a NOP before executing the new code. Otherwise, old content from the cache could still be used, although the code has changed. When changing the caches mode, note that an instruction containing a program memory data access must not be placed directly after a cache enable or cache disable instruction, because the processor must wait at least one cycle before executing the PM data access. A program should have an NOP inserted after the cache enable instruction.

Optimizing Cache Usage

Cache operation is usually efficient and requires no intervention. However, certain ordering of instructions can work against the caches architecture and degrade cache efficiency. When the order of PM data accesses and instruction fetches continuously displaces cache entries and loads new entries, the cache is not operating efficiently. Rearranging the order of these instructions remedies this inefficiency.

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Instruction Cache

An example of inefficient cache code appears in Table 3-4. The program memory data access at address 0x101 in the loop, Outer, causes the cache to load the instruction at 0x103 (into set 3). Each time the program calls the subroutine, Inner, the program memory data accesses at 0x201 and 0x211 displace the instruction at 0x103 by loading the instructions at 0x203 and 0x213 (also into set 3). If the program only calls the Inner subroutine rarely during the Outer loop execution, the repeated cache loads do not greatly influence performance. If the program frequently calls the subroutine while in the loop, the cache inefficiency has a noticeable effect on performance. To improve cache efficiency on this code (if for instance, execution of the Outer loop is time-critical), rearrange the order of some instructions. Moving the subroutine call up one location (starting at 0x201) would work here, because with that order the two cached instructions end up in cache set 4 instead of set 3. Table 3-4. Cache-Inefficient Code
Address 0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 ... 0x0200 0x0201 ... 0x0211 pm(i9,m9)=r12; Inner: r1=R13; r14=pm(i9,m9); Instruction lcntr=1024, do Outer until LCE; r0=dm(i0,m0), pm(i8,m8)=f3; r1=r0-r15; if eq call (Inner); f2=float r1; f3=f2*f2; Outer: f3=f3+f4; pm(i8,m8)=f3;

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Table 3-4. Cache-Inefficient Code (Contd)

Address ... 0x021F rts; Instruction

Branches and Sequencing

One of type of non-sequential program flow that the sequencer supports is branching. A branch occurs when a JUMP or CALL/return instruction begins execution at a new location, other than the next sequential address. For descriptions on how to use JUMP and CALL/return instructions, see the ADSP-21160 SHARC DSP Instruction Set Reference. Briefly, these instructions operate as follows: A JUMP or a CALL instruction transfers program flow to another memory location. The difference between a JUMP and a CALL is that a CALL automatically pushes the return address (the next sequential address after the CALL instruction) onto the PC stack. This push makes the address available for the CALL instructions matching return instruction, allowing easy return from the subroutine. A return instruction causes the sequencer to fetch the instruction at the return address, which is stored at the top of the PC stack. The two types of return instructions are return from subroutine (RTS) and return from interrupt (RTI). While the return from subroutine (RTS) only pops the return address off the PC stack, the return from interrupt (RTI) pops the return address and: 1. Pops the status stack if the ASTATx,y and MODE1 status registers have been pushed for any of the following interrupts: IRQ2-0, timer, or VIRPT. 2. Clears the interrupts bit in the interrupt latch register (IRPTL) and the interrupt mask pointer (IMASKP). ADSP-21161 SHARC Processor Hardware Reference 3-13

Branches and Sequencing

There are a number of parameters that can be specified for branches: and CALL/return instructions can be conditional. The program sequencer can evaluate status conditions to decide whether to execute a branch. If no condition is specified, the branch is always taken. For more information on these conditions, see Conditional Sequencing on page 3-53.
JUMP JUMP

and CALL/return instructions can be immediate or delayed. Because of the instructions pipeline, an immediate branch incurs two lost (overhead) cycles. A delayed branch has no overhead. For more information, see Delayed Branches on page 3-15.

instructions that appear within a loop or within an interrupt service routine have additional options. For information on the loop abort (LA) option, see Loops and Sequencing on page 3-22. For information on the loop re-entry (LR) option, see Restrictions on Ending Loops on page 3-25.For information on the clear interrupt (CI) option, see Interrupts and Sequencing on page 3-34.
JUMP

The sequencer block diagram in Figure 3-2 on page 3-4 shows that branches can be direct or indirect. The difference is that the sequencer generates the address for a direct branch, and the PM data address generator (DAG2) produces the address for an indirect branch. Direct branches are JUMP or CALL/return instructions that use an absolutenot changing at runtimeaddress (such as a program label) or use a PC-relative address. Some instruction examples that cause a direct branch are:
JUMP fft1024; /*Where fft1024 is an address label*/ CALL (pc,10); /*Where (pc,10) a PC-relative address*/

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Program Sequencer

Indirect branches are JUMP or CALL/return instructions that use a dynamic address that comes from the PM data address generator. For more information on the data address generator, see Chapter 4, Data Address Generator. Some instruction examples that cause an indirect branch are:
JUMP (m8,i12); /*where (m8,i12) are DAG2 registers*/ CALL (m9,i13); /*where (m9,i13) are DAG2 registers*/

Conditional Branches
The sequencer supports conditional branches. These are JUMP or CALL/return instructions whose execution is based on testing an IF condition. For more information on condition types in IF condition instructions, see Conditional Sequencing on page 3-53. Note that the processors Single-Instruction, Multiple-Data mode influences the execution of conditional branches. For more information, see SIMD Mode and Sequencing on page 3-57.

Delayed Branches
The instruction pipeline influences how the sequencer handles branches. For immediate branches in which JUMPs and CALL/return instructions are not specified as delayed branches (DB), two instruction cycles are lost (NOPs) as the pipeline empties and refills with instructions from the new branch. As shown in Table 3-5 and Table 3-6, the processor does not execute the two instructions after the branch, which are in the fetch and decode stages. For a CALL, the decode address (the address of the instruction after the CALL) is the return address. During the two lost (no-operation) cycles, the pipeline fetches and decodes the first instruction at the branch address.

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Branches and Sequencing

Table 3-5. Pipelined Execution Cycles for Immediate Branch (JUMP/Call)

Cycles 1 2 3 4 Fetch n+2 j
2

Decode n+1nop1 n+2nop j j+1

3

Execute n NOP NOP j

j+1 j+2

Note that n is the branching instruction, and j is the instruction branch address 1. n+1 suppressed 2. For call, n+1 pushed on PC stack 3. n+2 suppressed

Table 3-6. Pipelined Execution Cycles for Immediate Branch (Return)

Cycles 1 2 3 4 Fetch n+2 r r+1 r+2 Decode n+1nop1 n+2nop3 r r+1 Execute n2 NOP NOP r

Note that n is the branching instruction, and r is the instruction branch address 1. n+1 suppressed 2. r (n+1 in Table 3-5) popped from PC stack 3. n+2 suppressed

For delayed branches, JUMPs and CALL/return instructions with the delayed branches (DB) modifier, no instruction cycles are lost in the pipeline, because the processor executes the two instructions after the branch while the pipeline fills with instructions from the new branch. As shown in Table 3-7 and Table 3-8, the processor executes the two instructions after the branch, while the instruction at the branch address is fetched and decoded. In the case of a CALL, the return address is the third address after the branch instruction. While delayed branches use the 3-16 ADSP-21161 SHARC Processor Hardware Reference

Program Sequencer

instruction pipeline more efficiently than immediate branches, note that delayed branch code can be harder to understand because of the instructions between the branch instruction and the actual branch. Table 3-7. Pipelined Execution Cycles for Delayed Branch (JUMP or CALL)
Cycles 1 2 3 4 Fetch n+2 j1 j+1 j+2 Decode n+1 n+2 j j+1 Execute n n+1 n+2 j

Note that n is the branching instruction, and j is the instruction branch address 1. For call, n+3 pushed on PC stack

Table 3-8. Pipelined Execution Cycles For Delayed Branch (return)

Cycles 1 2 3 4 Fetch n+2 r r+1 r+2 Decode n+1 n+2 r r+1 Execute n1 n+1 n+2 r

n is the branching instruction, and r is the instruction branch address 1. r (n+3 in Table 3-7) popped from PC stack

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Branches and Sequencing

Besides being more challenging to code, delayed branches impose some limitations that stem from the instruction pipeline architecture. Because the delayed branch instruction and the two instructions that follow it must execute sequentially, the instructions in the two locations that follow a delayed branch instruction cannot be any of the following: Other branches (no JUMP, CALL, or return instructions) Any stack manipulations (no PUSH or POP instructions or writes to the PC stack or PC stack pointer) Any loops or other breaks in sequential operation (no DO/UNTIL or IDLE instructions) Development software for the processor should always flag these types of instructions as code errors in the two locations after a delayed branch instruction. It is possible to follow a delayed branch instruction with a JUMP, CALL, or return instruction in one special case. If the sequential branch instructions use mutually exclusive conditions, one branch may following another. The following example is valid.
if gt jump (PC, 7) (db); // if greater than... if le jump (PC,11) (db); // if less than or equal...

Interrupt processing is also influenced by delayed branches and the instruction pipeline. Because the delayed branch instruction and the two instructions that follow it must execute sequentially, the processor does not immediately process an interrupt that occurs in between a delayed branch instruction and either of the two instructions that follow. Any interrupt that occurs during these instructions is latched, but is not processed until the branch is complete.

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During a delayed branch, a program can read the PC stack or PC stack pointer immediately after a delayed call or return. This read shows that the return address on the PC stack has already been pushed or popped, even though the branch has not occurred yet. Restrictions and Limitations When Using Delayed Branches Besides being more challenging to code, delayed branches impose some limitations that stem from the instruction pipeline architecture. Because the delayed branch instruction and the two instructions that follow it must execute sequentially, the instructions in the two locations that follow a delayed branch instruction cannot be any of those described in the following five sections. Development software for the ADSP-21161 processor should always flag the operations described in the next five sections as code errors in the two locations after a delayed branch instruction. Normally it is not valid to use two conditional instructions using the (DB) option following each other. But the execution is allowed when these instructions are mutually exclusive as shown below.
If gt jump (PC, 7) (db); If le jump (pc, 11) (db);

Other Jumps, or Calls with RTI, RTS These instructions cannot be used when they follow a delayed branch instruction. This is shown in the following code that uses the JUMP instruction.
jump foo(db); jump my(db); r0=r0+r1; r1=r1+r2;

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In this case, the delayed branch instruction r1=r1+r2, is not executed. Further, the control jumps to my instead of foo, where the delayed branch instruction is the execution of foo. The exception is for the JUMP instruction, which applies for the mutually exclusive conditions EQ (equal), and NE (not equal). If the first EQ condition evaluates true, then the NE conditional jump has no meaning and is the same as a NOP instruction. Code samples for these conditions are shown below.
if eq jump label1 (db); if ne jump label1 (db); nop; nop;

Pushes or Pops of the PC Stack In this case a push of the PC stack in a delayed branch is followed by a pop. If a value is pushed in the delayed branch of a call, it is first popped in the called subroutine. This is followed by an RTS instruction.
call foo (db); push PCSTK; nop; foo; /* second push due to PCSTK */ /* first push because of call */

This example shows that when a program pushes the PCSTK during a delayed slot, the PC stack pointer is pushed onto the PCSTK. The following instructions are executed prior to executing the RTS.
pop PCSTK; RTS (db); nop; nop;

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If pushing the PC stack, a stack pop must be performed first. This is followed by an RTS instruction. If a value is popped inside a delayed branch, whatever subroutine return address is pushed is popped back, which is not allowed. Writes to the PC Stack or PC Stack Pointer The following two situations may arise when programs attempt to write to the PC stack inside a delayed branch. 1. If programs write into the PC stack inside a jump, one of the following situations can occur. a. The PC stack cannot hold a value that has already been pushed onto the PC stack. When the PC stack contains a value and a program writes that same value onto the stack, the original value is overwritten by the new value and the original value becomes corrupted. b. The PC stack is empty. Programs cannot write to the PC stack when they are inside a jump. In this case the PC stack remains empty. 2. Write to the PC stack inside a call. If a program writes to the PC stack inside of a call, the value that is pushed onto the PC stack because that call is overwritten by the value written onto the PC stack. Therefore, when a program performs an RTS, the program returns to the address pushed onto the PC stack and not to the address pushed while branching to the subroutine. For example:

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call foo3 (db); PCSTK=0x9011C; nop;

The value 90114 is pushed onto the PC stack, while the value 9011C is written to the PC stack. Accordingly, the value 90114 is overwritten by the value 9011C in the PC stack because values that are pushed onto the stack have precedence over values written to the stack. Therefore, when the program comes back by executing an RTS, the return is to address 9011C and not to 90114. IDLE Instruction An interrupt is needed to come out of the IDLE instruction. If a program places an IDLE instruction inside the delayed branch the processor remains in the idled state because interrupts are latched but not serviced until the program exits a delayed branch.

Loops and Sequencing

Another type of non-sequential program flow that the sequencer supports is looping. A loop occurs when a DO/UNTIL instruction causes the processor to repeat a sequence of instructions until a condition tests true. A special condition for terminating a loop is Loop Counter Expired (LCE). This condition tests whether the loop has completed the number of iterations in the LCNTR register. Loops that terminate with conditions other than LCE have some additional restrictions. For more information, see Restrictions on Ending Loops on page 3-25 and Restrictions on Short Loops on page 3-26. For more information on condition types in DO/UNTIL instructions, see Conditional Sequencing on page 3-53. The processors Single-Instruction, Multiple-Data mode influences the execution of loops. For more information, see SIMD Mode and Sequencing on page 3-57.

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The DO/UNTIL instruction uses the sequencers loop and condition features, which appear in Figure 3-2 on page 3-4. These features provide efficient software loops without the overhead of additional instructions to branch, test a condition, or decrement a counter. The following code example shows a DO/UNTIL loop that contains three instructions and iterates 30 times.
LCNTR=30, DO the_end UNTIL LCE; /*Loop iterates 30 times*/ R0=DM(I0,M0), F2=PM(I8,M8); R1=R0-R15; the_end: F4=F2+F3; /*Last instruction in loop*/

When executing a DO/UNTIL instruction, the program sequencer pushes the address of the loops last instruction and loops termination condition onto the loop address stack. The sequencer also pushes the top-of-loop addressaddress of the instruction following the DO/UNTIL instruction onto the PC stack. The sequencers instruction pipeline architecture influences loop termination. Because instructions are pipelined, the sequencer must test the termination condition (and, if the loop is counter-based, decrement the counter) before the end of the loop. Based on the tests outcome, the next fetch either exits the loop or returns to the top-of-loop. The condition test occurs when the processor is executing the instruction two locations before the last instruction in the loop (at location e 2, where e is the end-of-loop address). If the condition tests false, the sequencer repeats the loop, fetching the instruction from the top-of-loop address, which is stored on the top of the PC stack. If the condition tests true, the sequencer terminates the loop, fetching the next instruction after the end of the loop and popping the loop and PC stacks.

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A special case of loop termination is the loop abort instruction, JUMP (LA). This instruction causes an automatic loop abort when it occurs inside a loop. When the loop aborts, the sequencer pops the PC and loop address stacks once. If the aborted loop was nested, the single pop of the stacks leaves the correct values in place for the outer loop. Table 3-9 and Table 3-10 show the pipeline states for loop iteration and termination. Table 3-9. Pipelined Execution Cycles for Loop Back (Iteration)
Cycles 1 2 3 4 Fetch e b2 b+1 b+2 Decode e 1 e b b+1 Execute e 21 e 1 e b

Note that e is the loop end instruction, and b is the loop start instruction. 1. Termination condition tests false 2. Loop start address is top of PC stack

Table 3-10. Pipelined Execution Cycles for Loop Termination

Cycles 1 2 3 4 Fetch e e+12 e+2 e+3 Decode e 1 e e+1 e+2 Execute e 21 e 1 e e+1

Note that e is the loop end instruction. 1. Termination condition tests true 2. Loop aborts and loop stacks pop

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Restrictions on Ending Loops

The sequencers loop features (which optimize performance in many ways) limit the types of instructions that may appear at or near the end of the loop. These restrictions include: Nested loops cannot use the same end-of-loop instruction address. Nested loops with a non-counter-based loop as the outer loop must place the end address of the outer loop at least two addresses after the end address of the inner loop. Nested loops with a non-counter-based loop as the outer loop that use the loop abort instruction, JUMP (LA), to abort the inner loop may not JUMP (LA) to the last instruction of the outer loop. An instruction that writes to the loop counter from memory cannot be used as the third-to-last instruction of a counter-based loop (at e2, where e is the end-of-loop address). An IF NOT LCE instruction cannot be used as the instruction that follows a write to CURLCNTR from memory. Branch (JUMP or CALL/return) instructions may not be used as any of the last three instructions of a loop. This no end-of-loop branches rule also applies to single-instruction and two-instruction loops with only one iteration. There is one exception to the no end-of-loop branches rule. The last three instructions of a loop may contain an immediate CALL a CALL without a DB modifierthat is paired with a loop re-entry returna return (RTS) with loop re-entry modifier (LR). The immediate CALL may be one of the last three instructions of a loop, but not in a one-instruction loop or a two-instruction, single-iteration loop.

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Restrictions on Short Loops

The sequencers pipeline features (which optimize performance in many ways) restrict how short loops iterate and terminate. Short loops (1- or 2-instruction loops) terminate in a special way because they are shorter than the instruction pipeline. Counter-based loops (DO/UNTIL LCE) of one or two instructions are not long enough for the sequencer to check the termination condition two instructions from the end of the loop. In these short loops, the sequencer has already looped back when the termination condition is tested. The sequencer provides special handling to prevent overhead (NOP) cycles if the loop is iterated a minimum number of times. Table 3-11 and Table 3-12 show the pipeline execution for counter-based single-instruction loops. Table 3-13 and Table 3-14 show the pipeline execution for counter-based two-instruction loops. For no overhead, a loop of length one must be executed at least three times and a loop of length two must be executed at least twice. Loops of length one that iterate only once or twice and loops of length two that iterate only once incur two cycles of overhead, because two aborted instructions after the last iteration clear the instruction pipeline. Table 3-11. Pipelined Execution Cycles for Single Instruction Counter-Based Loop With Three Iterations
Cycles 1 2 3 4 5 Fetch n+2 n+12 n+23 n+3 n+4 Decode n+1 n+1 n+1 n+2 n+3 Execute n1 n+1 (pass 1) n+1 (pass 2) n+1 (pass 3) n+2

Note: n is the loop start instruction, and n+2 is the instruction after the loop. 1. Loop count (LCNTR) equals 3 2. No opcode latch or fetch address update; count expired tests true 3. Loop iteration aborts; PC and loop stacks pop

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Table 3-12. Pipelined Execution Cycles for Single Instruction Counter-Based Loop With Two Iterations (Two Overhead Cycles)
Cycles 1 2 3 4 5 6 Fetch n+2 n+12 n+13 n+2 n+3 n+4 Decode n+1 n+1 n+1nop4 n+1nop n+2 n+3
5

Execute n1 n+1 (pass 1) n+1 (pass 2) NOP NOP n+2

Note: n is the loop start instruction, and n+2 is the instruction after the loop. 1. Loop count (LCNTR) equals 2 2. No opcode latch or fetch address update 3. Count expired tests true 4. Loop iteration aborts; PC and loop stacks pop; n+1 suppressed 5. n+1 suppressed

Table 3-13. Pipelined Execution Cycles for Two Instruction Counter-Based Loop With Two Iterations
Cycles 1 2 3 4 5 6 Fetch n+2 n+12 n+23 n+34 n+4 n+5 Decode n+1 n+2 n+1 n+2 n+3 n+4 Execute n1 n+1 (pass 1) n+2 (pass 1) n+1 (pass 2) n+2 (pass 2) n+3

Note: n is the loop start instruction, and n+3 is the instruction after the loop. 1. Loop count (LCNTR) equals 2 2. PC stack supplies loop start address 3. Count expired tests true 4. Loop iteration aborts; PC and loop stacks pop

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Table 3-14. Pipelined Execution Cycles for Two Instruction Counter-Based Loop With One Iteration (Two Overhead Cycles)
Cycles 1 2 3 4 5 6 Fetch n+2 n+12 n+23 n+3 n+4 n+5 Decode n+1 n+2 n+1nop4 n+2nop n+3 n+4
5

Execute n1 n+1 (pass 1) n+2 (pass 1) NOP NOP n+3

Note: n is the loop start instruction, and n+3 is the instruction after the loop. 1. Loop count (LCNTR) equals 1 2. PC stack supplies loop start address 3. Count expired tests true 4. Loop iteration aborts; PC and loop stacks pop; n+1 suppressed 5. n+2 suppressed

Processing of an interrupt that occurs during the last iteration of a one-instruction loop is delayed by one cycle in the following cases: the loop executes once or twice a two-instruction loop executes once a cycle follows one of these loops (which is an NOP) Similarly, in a one-instruction loop that iterates at least three times, processing is delayed by one cycle if the interrupt occurs during the third-to-last iteration. For more information on pipeline execution during interrupts, see Interrupts and Sequencing on page 3-34.

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Short non-counter-based loops terminate differently from short counter-based loops. These differences stem from the architecture of the pipeline and conditional logic: In a three-instruction non-counter-based loop, the sequencer tests the termination condition when the processor executes the top of loop instruction. When the condition tests true, the sequencer completes the iteration of the loop and terminates. In a two-instruction non-counter-based loop, the sequencer tests the termination condition when the processor executes the last (second) instruction. If the condition becomes true when the first instruction is executed, the condition tests true during the second instruction, and the sequencer completes one more iteration of the loop before exiting. If the condition becomes true during the second instruction, the sequencer completes two more iterations of the loop before exiting. In a one-instruction non-counter-based loop, the sequencer tests the termination condition every cycle. After the cycle when the condition becomes true, the sequencer completes three more iterations of the loop before exiting.

Loop Address Stack

The sequencers loop support, which appears in Figure 3-2 on page 3-4, includes a loop address stack. The loop address stack is six levels deep by 32 bits wide. The LADDR register contains the top entry on the loop address stack. This register is readable and writable over the DM Data bus. Reading and writing LADDR does not move the loop address stack pointer; only a stack push or pop performed with explicit instructions moves the stack pointer. LADDR contains the value 0xFFFF FFFF when the loop address stack is empty. Table A-14 on page A-45 lists all the bits in LADDR.

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The sequencer pushes an entry onto the loop address stack when executing a DO/UNTIL or PUSH loop instruction. The stack entry pops off the stack two instructions before the end of its loops last iteration or on a POP loop instruction. A stack overflow occurs if a seventh entry (one more than full) is pushed onto the loop stack. The stack is empty when no entries are occupied. The loop stacks overflow or empty status is available. Because the sequencer keeps the loop stack and loop counter stack synchronized, the same overflow and empty flags apply to both stacks. These flags are in the sticky status register (STKYx). For more information on STKYx, see Table A-5 on page A-19. For more information on how these flags work with the loop stacks, see Loop Counter Stack on page 3-30. Note that a loop stack overflow causes a maskable interrupt. Because the sequencer tests the termination condition two instructions before the end of the loop, the loop stack pops before the end of the loops final iteration. If a program reads LADDR at either of these instructions, the value is already the termination address for the next loop stack entry.

Loop Counter Stack

The sequencers loop support, which appears in Figure 3-2 on page 3-4, includes a loop counter stack. The sequencer keeps the loop counter stack synchronized with the loop address stack. Both stacks always have the same number of locations occupied. Because these stacks are synchronized, the same empty and overflow status flags from the STKYx register apply to both stacks. The loop counter stack is six locations deep. The stack is full when all entries are occupied, is empty when no entries are occupied, and is overflowed if a push occurs when the stack is already full. Bits in the STKYx

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register indicate the loop counter stack full and empty states. Table A-5 on page A-19 lists the bits in the STYKx register. The STKYx bits that indicate loop counter stack status are: Loop stacks overflowed. Bit 25 (LSOV) indicates that the loop counter stack and loop stack are overflowed (if 1) or not overflowed (if 0)A sticky bit. Loop stacks empty. Bit 26 (LSEM) indicates that the loop counter stack and loop stack are empty (if 1) or not empty (if 0)Not sticky, cleared by a PUSH. Within the sequencer, the current loop counter (CURLCNTR) and loop counter (LCNTR) registers allow access to the loop counter stack. CURLCNTR tracks iterations for a loop being executed, and LCNTR holds the count value before the loop is executed. The two counters let the processor maintain the count for an outer loop, while a program is setting up the count for an inner loop. The top entry in the loop counter stack (CURLCNTR) always contains the current loop count. This register is readable and writable over the DM Data bus. Reading CURLCNTR when the loop counter stack is empty returns the value 0xFFFF FFFF. The sequencer decrements the value of CURLCNTR for each loop iteration. Because the sequencer tests the termination condition two instruction cycles before the end of the loop, the loop counter also decrements before the end of the loop. If a program reads CURLCNTR at either of the last two loop instructions, the value is already the count for the next iteration. The loop counter stack pops two instructions before the end of the last loop iteration. When the loop counter stack pops, the new top entry of the stack becomes the CURLCNTR valuethe count in effect for the executing loop. If there is no executing loop, the value of CURLCNTR is 0xFFFF FFFF after the pop.

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Writing CURLCNTR does not cause a stack push. If a program writes a new value to CURLCNTR, the program changes the count value of the loop currently executing. When no DO/UNTIL LCE loop is executing, writing to CURLCNTR has no effect. Because the processor must use CURLCNTR to perform counter-based loops, some restrictions apply to how a program can write CURLCNTR. For more information, see Restrictions on Ending Loops on page 3-25. The next-to-top entry in the loop counter stack (LCNTR) is the location on the stack that takes effect on the next loop stack push. To set up a count value for a nested loop without changing the count for the currently executing loop, a program writes the count value to LCNTR. A value of zero in LCNTR causes a loop to execute 232 times. A DO/UNTIL LCE instruction pushes the value of LCNTR onto the loop count stack, making that value the new CURLCNTR value. Figure 3-4 demonstrates this process for a set of nested loops. The previous CURLCNTR value is preserved one location down in the stack. If a program reads LCNTR when the loop counter stack is full, the stack returns invalid data. When the loop counter stack is full, the stack discards any data written to LCNTR. If a program reads LCNTR during the last two instructions of a terminating loop, the value of LCNTR is the last CURLCNTR value for the loop.

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LCNTR

AAAA AAAA

CURLCNTR

0XFFFF FFFF

1 LCNTR AAAA AAAA CURLCNTR LCNTR

2 AAAA AAAA BBBB BBBB CURLCNTR LCNTR

3 AAAA AAAA BBBB BBBB CCCC CCCC

4 AAAA AAAA BBBB BBBB CURLCNTR LCNTR CCCC CCCC DDDD DDDD CURLCNTR LCNTR

5 AAAA AAAA BBBB BBBB CCCC CCCC DDDD DDDD EEEE EEEE CURLCNTR LCNTR

6 AAAA AAAA BBBB BBBB CCCC CCCC DDDD DDDD EEEE EEEE F F F F F F FF

7 AAAA AAAA BBBB BBBB CCCC CCCC DDDD DDDD EEEE EEEE CURLCNTR F F FF FF F F

Figure 3-4. Pushing the Loop Counter Stack for Nested Loops

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Interrupts and Sequencing

Another type of non-sequential program flow that the sequencer supports is interrupt processing. Interrupts may stem from a variety of conditions, both internal and external to the processor. In response to an interrupt, the sequencer processes a subroutine call to a predefined address, the interrupt vector. The processor assigns a unique vector to each type of interrupt. The processor supports three prioritized, individually-maskable external interrupts, each of which can be either level- or edge-sensitive. External interrupts occur when another device asserts one of the processors interrupt inputs (IRQ2-0). The processor also supports internal interrupts. An internal interrupt can stem from arithmetic exceptions, stack overflows, or circular data buffer overflows. Several factors control the processors response to an interrupt request. The processor responds to an interrupt request if: The processor is executing instructions or is in an idle state The interrupt is not masked Interrupts are globally enabled A higher priority request is not pending When the processor responds to an interrupt, the sequencer branches program execution with a call to the corresponding interrupt vector address. Within the processors program memory, the interrupt vectors are grouped in an area called the interrupt vector table. The interrupt vectors in this table are spaced at 4-instruction intervals. For a list of interrupt vector addresses and their associated latch and mask bits, see Table B-1 on page B-1. Each interrupt vector has associated latch and mask bits. Table A-9 on page A-27 lists the latch and mask bits.

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To process an interrupt, the processors program sequencer does the following: 1. Outputs the appropriate interrupt vector address 2. Pushes the current PC value (the return address) onto the PC stack 3. Pushes the current value of the ASTATx,y and MODE1 registers onto the status stack (if the interrupt is IRQ2-0, timer, or VIRPT) 4. Sets the appropriate bit in the interrupt latch register (IRPTL) 5. Alters the interrupt mask pointer (IMASKP) to reflect the current interrupt nesting state, depending on the nesting mode At the end of the interrupt service routine, the sequencer processes the return from interrupt (RTI) instruction and does following: 1. Returns to the address stored at the top of the PC stack 2. Pops this value off of the PC stack 3. Pops the status stack (if the ASTATx,y and MODE1 status registers were pushed for the IRQ2-0, timer, or VIRPT interrupt) 4. Clears the appropriate bit in the interrupt latch register (IRPTL) and interrupt mask pointer (IMASKP) Except for reset, all interrupt service routines should end with a return-from-interrupt (RTI) instruction. After reset, the PC stack is empty, so there is no return address. The last instruction of the reset service routine should be a jump to the start of your program. If software writes to a bit in IRPTL forcing an interrupt, the processor recognizes the interrupt in the following cycle, and two cycles of branching to the interrupt vector follow the recognition cycle.

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The processor responds to interrupts in three stages: synchronization and latching (1 cycle), recognition (1 cycle), and branching to the interrupt vector (2 cycles). Table 3-15, Table 3-16, and Table 3-17 show the pipelined execution cycles for interrupt processing. Table 3-15. Pipelined Execution Cycles for Interrupt During Single-Cycle Instruction
Cycles 1 2 3 4 5 Fetch n+1 n+22 v4 v+1 v+2 Decode n n+1nop3 n+2nop5 v v+1 Execute n11 n nop nop v

Note that n is the single-cycle instruction, and v is the interrupt vector instruction 1. Interrupt occurs 2. Interrupt recognized 3. n+1 pushed on PC stack; n+1 suppressed 4. Interrupt vector output 5. n+2 suppressed

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Table 3-16. Pipelined Execution Cycles for Interrupt During Instruction With Conflicting PM Data Access (Instruction Not Cached)
Cycles 1 2 3 4 5 6 Fetch n+1 2 n+24 v
6

Decode n n+1nop3 n+1nop5 n+2nop v v+1

7

Execute n11 n nop nop nop v

v+1 v+2

Note that n is the conflicting instruction, and v is the interrupt vector instruction 1. Interrupt occurs 2. Interrupt recognized, but not processed; PM data access 3. n+1 suppressed 4. Interrupt processed 5. n+1 suppressed 6. Interrupt vector output 7. n+1 pushed on PC stack; n+2 suppressed

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Table 3-17. Pipelined Execution Cycles for Interrupt During Delayed Branch Instruction
Cycles 1 2 3 4 5 6 7 Fetch n+1 n+22 j j+1 v5 v+1 v+2
3

Decode n n+1 n+2 jnop

4

Execute n11 n n+1 n+2 nop nop v

j+1nop6 v v+1

Note that n is the delayed branch instruction, j is the instruction at the branch address, and v is the interrupt vector instruction 1. Interrupt occurs 2. Interrupt recognized, but not processed 3. Interrupt processed 4. For a Call, n+3 (return address) is pushed onto the PC stack; j suppressed 5. Interrupt vector output 6. j pushed on PC stack; j+1 suppressed

For most interrupts, internal and external, only one instruction is executed after the interrupt occurs (and before the two instructions aborted) while the processor fetches and decodes the first instruction of the service routine. Because of the one-cycle delay between an arithmetic exception and the STKYx,y register update, interrupt processing starts two cycles after an arithmetic exception occurs. Table 3-18 lists the latency associated with the IRQ2-0 interrupts and the multiprocessor vector interrupt. Table 3-18. Minimum Latency of the IRQ2-0 and VIRPT Interrupts
Interrupt IRQ2-0 VIRPT Minimum Latency 3 cycles 6 cycles

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If nesting is enabled and a higher priority interrupt occurs immediately after a lower priority interrupt, the service routine of the higher priority interrupt is delayed by one additional cycle. This delay allows the first instruction of the lower priority interrupt routine to be executed before it is interrupted. For more information, see Nesting Interrupts on page 3-45. Certain processor operations that span more than one cycle hold off interrupt processing. If an interrupt occurs during one of these operations, the processor latches the interrupt, but delays its processing. The operations that have delayed interrupt processing are as follows: A branch (JUMP or CALL/return) instruction and the following cycle, whether it is an instruction (in a delayed branch) or an NOP (in a non-delayed branch) The first of the two cycles used to perform a program memory data access and an instruction fetch when the instruction is not cached The third-to-last iteration of a one-instruction loop The last iteration of either a one-instruction loop executed once or twice or a two-instruction loop executed once, and the following cycle (which is an NOP) The first of the two cycles used to fetch and decode the first instruction of an interrupt service routine Any waitstates for external memory accesses Any external memory access required when the processor does not have control of the external bus, during a host bus grant or when the processor is a bus slave in a multiprocessing system

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Sensing Interrupts
The processor supports two types of interrupt sensitivitythe signal shape that triggers the interrupt. On interrupt pins (IRQ2-0), either the input signals edge or level can trigger an external interrupt. The processor detects a level-sensitive interrupt if the signal input is low (active) when sampled on the rising edge of CLKIN. A level-sensitive interrupt must go high (inactive) before the processor returns from the interrupt service routine. If a level-sensitive interrupt is still active when the processor samples it after returning from its service routine, the processor treats the signal as a new request. The processor repeats the same interrupt routine without returning to the main program, assuming no higher priority interrupts are active. The processor detects an edge-sensitive interrupt if the input signal is high (inactive) on one cycle and low (active) on the next cycle when sampled on the rising edge of CLKIN. An edge-sensitive interrupt signal can stay active indefinitely without triggering additional interrupts. To request another interrupt, the signal must go high, then low again. Edge-sensitive interrupts require less external hardware compared to level-sensitive requests, because negating the request is unnecessary. An advantage of level-sensitive interrupts is that multiple interrupting devices may share a single level-sensitive request line on a wired-OR basis, allowing easy system expansion. The MODE2 register controls external interrupt sensitivity. Table A-3 on page A-10 lists all bits in the MODE2 register. The following bits in MODE2 control interrupt sensitivity: Interrupt 0 Sensitivity. Bit 0 (IRQ0E), directs the processor to detect IRQ0 as edge-sensitive (if 1) or level-sensitive (if 0).

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Interrupt 1 Sensitivity. Bit 1 (IRQ1E), directs the processor to detect IRQ1 as edge-sensitive (if 1) or level-sensitive (if 0). Interrupt 2 Sensitivity. Bit 2 (IRQ2E), directs the processor to detect IRQ2 as edge-sensitive (if 1) or level-sensitive (if 0). The processor accepts external interrupts that are asynchronous to the processors clock (CLKIN), allowing external interrupt signals to change at any time. An external interrupt must be held low at least one CLKIN cycle to guarantee that the processor samples the signal. External interrupts must meet the setup and hold time requirements relative to the rising edge of CLKIN. For information on interrupt signal timing requirements, see the processors Data Sheet.

Masking Interrupts
The sequencer supports interrupt maskinglatching an interrupt, but not responding to it. Except for the RESET and EMU interrupts, all interrupts are maskable. If a masked interrupt is latched, the processor responds to the latched interrupt if it is later unmasked. Interrupts can be masked globally or selectively. Bits in the MODE1, IMASK, and LIRPTL registers control interrupt masking. Table A-2 on page A-3 lists the bits in MODE1, Table A-9 on page A-27 lists the bits in IMASK, and Table A-10 on page A-34 lists the bits in LIRPTL. These bits control interrupt masking as follows: Global interrupt enable. MODE1, Bit 12 (IRPTEN) directs the processor to enable (if 1) or disable (if 0) all interrupts. Selective interrupt enable. IMASK, Bits 30-10 and 8-0, direct the processor to enable (if 1) or disable/mask (if 0) the corresponding interrupt.

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Selective link port interrupt enable. LIRPTL, Bits 17-16 (LPxMSK) direct the processor to enable (if 1) or disable/mask (if 0) the corresponding link port interrupt. SPI port interrupt enable. LIRPTL, Bit 18 (SPIRMSK) and Bit 19 (SPITMSK) direct the processor to enable (if 1) or disable/mask (if 0) the SPI port receive interrupt or transmit interrupt, respectively. Except for the non-maskable interrupts and boot interrupts, all interrupts are masked at reset. For booting, the processor automatically unmasks and uses the external port (EPOI), link port (LP0I) or SPI port (SPIRI) interrupt after reset. Usage depends on whether the ADSP-21161 processor is booting from EPROM, host, SPI or link ports.

Latching Interrupts
When the processor recognizes an interrupt, the processors interrupt latch (IRPTL and LIRPTL) registers latch the interruptsset a bit to record that the interrupt occurred. The bits in these registers indicate all interrupts that are currently being serviced or are pending. Because these registers are readable and writable, any interrupt except reset can be set or cleared in software. Note that writing to the reset bit (bit 1) in IRPTL puts the processor into an illegal state. When an interrupt occurs, the sequencer sets the corresponding bit in IRPTL or LIRPTL. During execution of the interrupts service routine, the processor clears this bit during every cycle to prevent the same interrupt from being latched while its service routine is executing. After the return from interrupt (RTI), the sequencer stops clearing the latch bit. If necessary, it is possible to re-use an interrupt while it is being serviced. For more information, see Reusing Interrupts on page 3-47. The interrupt latch bits in IRPTL correspond to interrupt mask bits in the IMASK register. In both registers, the interrupt bits are arranged in order of priority. The interrupt priority is from 0 (highest) to 31 (lowest). Inter-

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rupt priority determines which interrupt is serviced first when more than one occurs in the same cycle. Priority also determines which interrupts are nested when the processor has interrupt nesting enabled. For more information, see Nesting Interrupts on page 3-45. While IRPTL latches interrupts for a variety of events, the LIRPTL register contains latch and mask bits only for Link port and SPI DMA interrupts. A logical Oring of link port interrupts (masked-latch state) appears in the LPSUM bit in the IRPTL register. Because the LPSUM bit has a corresponding mask bit in the IMASK register, programs can use LPSUM for a second level of link port interrupt masking. Multiple events can cause arithmetic interruptsfixed-point overflow (FIXI) and floating-point overflow (FLTOI), underflow (FLTUI), and invalid operation (FLTII). To determine which event caused the interrupt, a program can read the arithmetic status flags in the STYKx or STKYy status registers. Table A-5 on page A-19 lists the bits in these registers. Service routines for arithmetic interrupts must clear the appropriate STKYx or STKYy bits to clear the interrupt. If the bits are not cleared, the interrupt is still active after the return from interrupt (RTI). Status bits in STKYy apply only in SIMD mode. For more information, see Secondary Processing Element (PEy) on page 2-37. One event can cause multiple interrupts. The timer decrementing to zero causes two timer expired interrupts, TMZHI (high priority) and TMZLI (low priority). This feature allows selection of the priority for the timer interrupt. Programs should unmask the timer interrupt with the desired priority and leave the other one masked. If both interrupts are unmasked, IRPTL latches both interrupts when the timer reaches zero, and the processor services the higher priority interrupt first, and then the lower priority interrupt.

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The IRPTL also supports software interrupts. When a program sets the latch bit for one of these interrupts (SFT0I, SFT1I, SFT2I, or SFT3I), the sequencer services the interrupt, and the processor branches to the corresponding interrupt routine. Software interrupts have the same behavior as all other maskable interrupts.

Stacking Status During Interrupts

To run in an interrupt driven system, programs depend on the processor being restored to its pre-interrupt state after an interrupt is serviced. The sequencers status stack eases the return from interrupt process by eliminating some interrupt service overheadregister saves and restores. The status stack is fifteen locations deep. The stack is full when all entries are occupied, is empty when no entries are occupied, and is overflowed if a push occurs when the stack is already full. Bits in the STKYx register indicate the status stack full and empty states. Table A-5 on page A-19 lists the bits in the STYKx register. The STKYx bits that indicate status stack status are: Status stack overflow. Bit 23 (SSOV) indicates that the status stack is overflowed (if 1) or not overflowed (if 0)A sticky bit. Status stack empty. Bit 24, (SSEM) indicates that the status stack is empty (if 1) or not empty (if 0)Not sticky, cleared by a PUSH. For some interrupts (IRQ2-0, timer expired, and VIRPT), the sequencer automatically pushes the ASTATx, ASTATy, and MODE1 registers onto the status stack. When the sequencer pushes an entry onto the status stack, the processor uses the MMASK register to clear the corresponding bits in the MODE1 register. All other bit settings remain the same. For more information and an example of how the MMASK and MODE1 registers work together, see the section Mode Mask Register (MMASK) on page A-8.

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The sequencer automatically pops the ASTATx, ASTATY, and MODE1 registers from the status stack during the return from interrupt instruction (RTI). In one other case, JUMP (CI), the sequencer pops the stack. For more information, see Reusing Interrupts on page 3-47. Only the IRQ2-0, timer expired, and VIRPT interrupts cause the sequencer to push an entry onto the status stack. All other interrupts require either explicit saves and restores of effected registers or an explicit push or pop of the stack (PUSH/POP STS). Pushing ASTATx, ASTATy, and MODE1 preserves the status and control bit settings. This feature allows a service routine to alter these bits with the knowledge that the original settings are automatically restored upon the return from the interrupt. The top of the status stack contains the current values of ASTATx, ASTATy, and MODE1. Reading and writing these registers does not move the stack pointer. Explicit PUSH or POP instructions do move the status stack pointer.

Nesting Interrupts
The sequencer supports interrupt nestingresponding to another interrupt while a previous interrupt is being serviced. Bits in the MODE1, IMASKP, and LIRPTL registers control interrupt nesting. Table A-2 on page A-3 lists the bits in MODE1, Table A-9 on page A-27 lists the bits in IMASKP, and Table A-10 on page A-34 lists the bits in LIRPTL. These bits control interrupt nesting as follows: Interrupt nesting enable. MODE1 Bit 11 (NESTM). This bit directs the processor to enable (if 1) or disable (if 0) interrupt nesting. Interrupt Mask Pointer. IMASKP Bits 30- 15, 13-10 and 8-0. These bits list the interrupts in priority order and provide a temporary interrupt mask for each nesting level.

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Link Port DMA Interrupt Mask Pointer. LIRPTL Bits 25-24, (LPxMSKP). These bits are the link port DMA interrupts in priority order. They provide a temporary interrupt mask for each nesting level. SPI Port DMA Interrupt Mask Pointer. LIRPTL Bits 27-26, (SPITMSKP and SPIRMSKP). These bits are the SPI port transmit and receive DMA interrupts respectively. They provide a temporary interrupt mask. When interrupt nesting is disabled, a higher priority interrupt can not interrupt a lower priority interrupts service routine. Other interrupts are latched as they occur, but the processor processes them after the active routine finishes. When interrupt nesting is enabled, a higher priority interrupt can interrupt a lower priority interrupts service routine. Lower interrupts are latched as they occur, but the processor process them after the nested routines finish. Programs should change the interrupt nesting enable (NESTM) bit only while outside of an interrupt service routine or during the reset service routine. If nesting is enabled and a higher priority interrupt occurs immediately after a lower priority interrupt, the service routine of the higher priority interrupt is delayed by one cycle. This delay allows the first instruction of the lower priority interrupt routine to be executed, before it is interrupted. When servicing nested interrupts, the processor uses the interrupt mask pointer (IMASKP) to create a temporary interrupt mask for each level of interrupt nesting; the IMASK value is not effected. The processor changes IMASKP each time a higher priority interrupt interrupts a lower priority service routine.

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The bits in IMASKP correspond to the interrupts in order of priority. When an interrupt occurs, the processor sets its bit in IMASKP. If nesting is enabled, the processor uses IMASKP to generate a new temporary interrupt mask, masking all interrupts of equal or lower priority to the highest priority bit set in IMASKP and keeping higher priority interrupts the same as in IMASK. When a return from an interrupt service routine (RTI) is executed, the processor clears the highest priority bit set in IMASKP and generates a new temporary interrupt mask. The processor masks all interrupts of equal or lower priority to the highest priority bit set in IMASKP. The bit set in IMASKP that has the highest priority always corresponds to the priority of the interrupt being serviced. If an interrupt recurs while its service routine is running and nesting is enabled, the processor updates IRPTL, but does not service the interrupt. The processor waits until the return from interrupt (RTI) completes before vectoring to the service routine again. If nesting is not enabled, the processor masks out all interrupts and IMASKP is not used, but the processor still updates IMASKP to create a temporary interrupt mask. The interrupt controller uses the IMASKP register and the LPxMSKP, SPITMSKP, and SPIRMSKP bits of the LIRPTL register. These bits should not be modified.

Reusing Interrupts
When an interrupt occurs the sequencer sets the corresponding bit in IRPTL. During execution of the service routine, the sequencer keeps this bit clearedthe processor clears the bit during every cycle, preventing the same interrupt from being latched while its service routine is already executing.

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If necessary, it is possible to re-use an interrupt while it is being serviced. Using a JUMP clear interrupt, JUMP (CI), instruction in the interrupt service routine clears the interrupt, allowing its reuse while the service routing is executing. The JUMP (CI) instruction reduces an interrupt service routine to a normal subroutine, clearing the appropriate bit in the interrupt latch and interrupt mask pointer and popping the status stack. After the JUMP (CI) instruction, the processor stops automatically clearing the interrupts latch bit, allowing the interrupt to latch again. When returning from a subroutine entered with a JUMP (CI) instruction, a program must use a return loop reentry, RTS(LR), instruction. For more information, see Restrictions on Ending Loops on page 3-25. The following example shows an interrupt service routine that is reduced to a subroutine with the (CI) modifier:
instr1; /*Interrupt entry from main program*/ JUMP(PC,3) (DB,CI); /*Clear interrupt status*/ instr3; instr4; instr5; RTS (LR); /*Use LR modifier with return from subroutine*/

The JUMP (PC,3)(DB,CI) instruction actually only continues linear execution flow by jumping to the location PC + 3 (instr5). The two intervening instructions (instr3, instr4) are executed because of the delayed branch (DB). This JUMP instruction is only an examplea JUMP (CI) can be to any location.

Interrupting IDLE
The sequencer supports placing the processor in IDLEa special instruction that halts the processor core in a low-power state. The halt occurs until an external interrupt (IRQ2-0), timer interrupt, DMA interrupt, or

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vector interrupt occurs. When executing an IDLE instruction, the sequencer fetches one more instruction at the current fetch address and then suspends operation. The processors I/O processor is not effected by the IDLE instructionDMA transfers to or from internal memory continues uninterrupted.
VIRPT

The processors internal clock and timer (if enabled) continue to run during IDLE. When an external interrupt (IRQ2-0), timer interrupt, DMA interrupt, or VIRPT vector interrupt occurs, the processor responds normally. After two cycles used to fetch and decode the first instruction of the interrupt service routine, the processor continues executing instructions normally.

Multiprocessing Interrupts
The sequencer supports a multiprocessor vector interrupt. The vector interrupt (VIRPT) permits passing interprocessor commands in multiple-processor systems. This interrupt occurs when an external processor (a host or another processor) writes an address to the VIRPT register, inserting a new vector address for VIRPT. The VIRPT register has space for the vector address and data for the service routine. Table A-19 on page A-64 lists the bits in the VIRPT registers. When servicing a VIRPT interrupt, the processor automatically pushes the status stack and executes the service routine located at the address specified in VIRPT. During the return from interrupt (RTI), the processor automatically pops the status stack.

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To flag that a VIRPT interrupt is pending, the processor sets the VIPD bit in the SYSTAT register when the external processor writes to the VIRPT register. Programs passing interprocessor commands must monitor VIPD to check if the processor can receive a new VIRPT address, because: If an external processor writes VIRPT while a previous vector is pending, the new VIRPT address replaces the previous pending one. If an external processor writes VIRPT while a previous vector is executing, the new VIRPT address does not execute (no new interrupt is triggered). When returning from a VIRPT interrupt, the processor clears the VIPD bit. Note that if a processor writes to its own VIRPT register, the write is ignored.

Timer and Sequencing

The sequencer includes a programmable interval timer, which appears in Figure 3-2 on page 3-4. Bits in the MODE2, TCOUNT, and TPERIOD registers control timer operations. Table A-3 on page A-10 lists the bits in the MODE2 register. The bits that control the timer are given as follows: Timer enable. MODE2 Bit 5 (TIMEN). This bit directs the processor to enable (if 1) or disable (if 0) the timer. Timer count. (TCOUNT) This register contains the decrementing timer count value, counting down the cycles between timer interrupts. Timer period. (TPERIOD) This register contains the timer period, indicating the number of cycles between timer interrupts. The TCOUNT register contains the timer counter. The timer decrements the TCOUNT register during each clock cycle. When the TCOUNT value reaches zero, the timer generates an interrupt and asserts the TIMEXP output high

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for 4 cycles (when the timer is enabled), as shown in Figure 3-5. On the clock cycle after TCOUNT reaches zero, the timer automatically reloads TCOUNT from the TPERIOD register. The TPERIOD value specifies the frequency of timer interrupts. The number of cycles between interrupts is TPERIOD + 1. The maximum value of 32 TPERIOD is 2 1. To start and stop the timer, programs use the MODE2 registers TIMEN bit. With the timer disabled (TIMEN=0), the program loads TCOUNT with an initial count value and loads TPERIOD with the number of cycles for the desired interval. Then, the program enables the timer (TIMEN=1) to begin the count. When a program enables the timer, the timer starts decrementing the TCOUNT register at the end of the next clock cycle. If the timer is subsequently disabled, the timer stops decrementing TCOUNT after the next clock cycle as shown in Figure 3-5. The timer expired event (TCOUNT decrements to zero) generates two interrupts, TMZHI and TMZLI. For information on latching and masking these interrupts to select timer expired priority, see Latching Interrupts on page 3-42. As with other interrupts, the sequencer needs two cycles to fetch and decode the first instruction of the timer expired service routine before executing the routine. The pipeline execution for the timer interrupt appears in Table 3-15 on page 3-36. Programs can read and write the TPERIOD and TCOUNT registers by using universal register transfers. Reading the registers does not effect the timer. Note that an explicit write to TCOUNT takes priority over the sequencers loading TCOUNT from TPERIOD and the timers decrementing of TCOUNT. Also note that TCOUNT and TPERIOD are not initialized at reset. Programs should initialize these registers before enabling the timer.

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TIMER ENABLE Set TIMEN in MODE2 Timer Active

CLKIN TCOUNT=N TIMER DISABLE Clear TIMEN in MODE2 Timer Inactive TCOUNT=N TCOUNT=N-1

CLKIN TCOUNT=M-1 TCOUNT=M-2 TCOUNT=M-2

Figure 3-5. Timer Enable and Disable

Stacks and Sequencing

The sequencer includes a Program Counter (PC) stack, which appears in Figure 3-2 on page 3-4. At the start of a subroutine or loop, the sequencer pushes return addresses for subroutines (CALL/return instructions) and top-of-loop addresses for loops (DO/UNTIL) instructions onto the PC stack. The sequencer pops the PC stack during a return from interrupt (RTI), returns from subroutine (RTS), and loop termination. The PC stack is 30 locations deep. The stack is full when all entries are occupied, is empty when no entries are occupied, and is overflowed if a push occurs when the stack is already full. Bits in the STKYx register indicate the PC stack full and empty states. Table A-5 on page A-19 lists the bits in the STYKx register. The STKYx bits that indicate PC stack status are:

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PC stack full. Bit 21 (PCFL) indicates that the PC stack is full (if 1) or not full (if 0)Not a sticky bit, cleared by a POP. PC stack empty. Bit 22 (PCEM) indicates that the PC stack is empty (if 1) or not empty (if 0)Not sticky, cleared by a PUSH. The PC stack full condition causes a maskable interrupt (SOVFI). This interrupt occurs when the PC stack has 29 locations filled (the almost full state). The PC stack full interrupt occurs when one location is left, because the PC stack full service routine needs that last location for its return address. The address of the top of the PC stack is available in the PC stack pointer (PCSTKP) register. The value of PCSTKP is zero when the PC stack is empty, is 1...30 when the stack contains data, and is 31 when the stack overflows. This register is a readable and writable register. A write to PCSTKP takes effect after a one-cycle delay. If the PC stack is overflowed, a write to PCSTKP has no effect. The overflow and full flags provide diagnostic aid only. Programs should not use these flags for runtime recovery from overflow. Note that the status stack, loop stack overflow, and PC stack full conditions trigger a maskable interrupt. The empty flags can ease stack saves to memory. Programs can monitor the empty flag when saving a stack to memory to determine when the processor has transferred all values.

Conditional Sequencing
The sequencer supports conditional execution with conditional logic that appears in Figure 3-2 on page 3-4. This logic evaluates conditions for conditional (IF) instructions and loop (DO/UNTIL) terminations. The conditions are based on information from the arithmetic status registers (ASTATx and ASTATy), the mode control 1 register (MODE1), the flag inputs,

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and the loop counter. For more information on arithmetic status, see Using Computational Status on page 2-8. When in SIMD mode, conditional execution is effected by the arithmetic status of both processing elements. For information on conditional sequencing in SIMD mode, see SIMD Mode and Sequencing on page 3-57. Each condition that the processor evaluates has an assembler mnemonic. The condition mnemonics for conditional instructions appear in Table 3-19. For most conditions, the sequencer can test both true and false states. For example, the sequencer can evaluate ALU equal-to-zero (EQ) and ALU not-equal-to-zero (NZ). To test conditions that do not appear in Table 3-19, a program can use the Test Flag (TF) condition generated from a Bit Test Flag (BTF) instruction. The TF flag is set or cleared as a result of a BIT TEST or BIT XOR instruction, which can test the contents of any of the processors system registers, including STKYx and STKYy. Table 3-19. IF Condition and DO/UNTIL Termination Mnemonics
Condition From ALU Description ALU = 0 ALU 0 ALU > 0 ALU < zero ALU 0 ALU 0 ALU carry ALU not carry ALU overflow ALU not overflow True if AZ = 1 AZ = 0 footnote1 footnote2 footnote3 footnote4 AC = 1 AC = 0 AV = 1 AV = 0 Mnemonic EQ NE GT LT GE LE AC NOT AC AV NOT AV

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Table 3-19. IF Condition and DO/UNTIL Termination Mnemonics (Contd)

Condition From Multiplier Description Multiplier overflow Multiplier not overflow Multiplier sign Multiplier not sign Shifter Shifter overflow Shifter not overflow Shifter zero Shifter not zero Bit Test Bit test flag true Bit test flag false Flag Input Flag0 asserted Flag0 not asserted Flag1 asserted Flag1 not asserted Flag2 asserted Flag2 not asserted Flag3 asserted Flag3 not asserted Mode Bus master true Bus master false True if MV = 1 MV= 0 MN = 1 MN = 0 SV = 1 SV = 0 SZ = 1 SZ = 0 BTF = 1 BTF = 0 FI0 = 1 FI0 = 0 FI1 = 1 FI1 = 0 FI2 = 1 FI2 = 0 FI3 = 1 FI3 = 0 Mnemonic MV NOT MV MS NOT MS SV NOT SV SZ NOT SZ TF NOT TF FLAG0_IN NOT FLAG0_IN FLAG1_IN NOT FLAG1_IN FLAG2_IN NOT FLAG2_IN FLAG3_IN NOT FLAG3_IN BM NOT BM

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Table 3-19. IF Condition and DO/UNTIL Termination Mnemonics (Contd)

Condition From Sequencer Description Loop counter expired (Do) Loop counter not expired (IF) Always false (Do) Always true (IF) True if CURLCNTR = 1 CURLCNTR 1 Always Always Mnemonic LCE NOT ICE FOREVER TRUE

1 ALU greater than (GT) is true if: [AF and (AN xor (AV and ALUSAT)) or (AF and AN)] or AZ = 0 2 ALU less than (LT) is true if: [AF and (AN xor (AV and ALUSAT)) or (AF and AN and AZ)] = 1 3 ALU greater equal (GE) is true if: [AF and (AN xor (AV and ALUSAT)) or (AF and AN and AZ)] = 0 4 ALU lesser or equal (LT) is true if: [AF and (AN xor (AV and ALUSAT)) or (AF and AN)] or AZ = 1

The two conditions that do not have complements are LCE/NOT LCE (loop counter expired/not expired) and TRUE/FOREVER. The context of these condition codes determines their interpretation. Programs should use TRUE and NOT LCE in conditional (IF) instructions. Programs should use FOREVER and LCE to specify loop (DO/UNTIL) termination. A DO FOREVER instruction executes a loop indefinitely, until an interrupt or reset intervenes. There are some restrictions on how programs may use conditions in DO/UNTIL loops. For more information, see Restrictions on Ending Loops on page 3-25 and Restrictions on Short Loops on page 3-26. The bus master (BM) condition indicates whether the processor is the current bus master in a multiprocessor system. To enable testing this condition, a program must clear the MODE1 registers Condition Code Select (CSEL) bits. Otherwise, the bus master condition is always false.

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SIMD Mode and Sequencing

The processor supports a Single-Instruction, Multiple-Data (SIMD) mode. In this mode, both of the processors processing elements (PEx and PEy) execute instructions and generate status conditions. For more information on SIMD computations, see Secondary Processing Element (PEy) on page 2-37. Because the two processing elements can generate different outcomes, the sequencers must evaluate conditions from both elements (in SIMD mode) for conditional (IF) instructions and loop (DO/UNTIL) terminations. The processor records status for the PEx element in the ASTATx and STKYx registers. The processor records status for the PEy element in the ASTATy and STKYy registers. Table A-4 on page A-13 lists the bits in ASTATx and ASTATy, and Table A-5 on page A-19 lists the bits in STKYx and STKYy. Even though the processor has dual processing elements, the sequencer does not have dual sets of stacks. The sequencer has one PC stack, one loop address stack, and one loop counter stack. The status bits for stacks are in STKYx and are not duplicated in STKYy. In SIMD mode, the status stack stores both ASTATx and ASTATy. A status stack PUSH or POP instruction in SIMD mode affects both registers in parallel. While in SIMD mode, the sequencer evaluates conditions from both PEs for conditional (IF) and loop (DO/UNTIL) instructions. Table 3-20 summarizes how the sequencer resolves each conditional test when SIMD mode is enabled.

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Table 3-20. Conditional Execution Summary

Conditional Operation Compute Operations Branches and Loops Data Moves (from complementary pair1 to complementary pair) Conditional Outcome Depends On Executes in each processing element independently depending on condition test in each processing element Executes in sequencer depending on ANDing condition test in each processing element Executes move in each processing element (and/or memory) independently depending on condition test in each processing element. The same uncomplimented universal register is the source for each move, including X<->Y swap. Executes move in each processing element (and/or memory) independently depending on condition test in each processing element. The same uncomplimented universal register is the source for each move, including X<->Y swap. Executes explicit move to uncomplemented universal register depending on condition test in PEx only; no implicit move occurs. The same uncomplimented universal register is the source for each move, including X<->Y swap. Executes modify3 in DAG depending on ORing condition test in each processing element

Data Moves (from uncomplemented Ureg register to complementary pair)

Data Moves (from complementary pair to uncomplemented register2)

DAG Operations 1 2 3

Complementary pairs are registers with SIMD complements, include PEx/y data registers and USTAT1/2, USTAT3/4, ASTATx/y, STKYx/y, and PX1/2 universal registers. Uncomplemented registers are universal registers that do not have SIMD complements. Post-modify operations follow this rule, but pre-modify operations always occur despite outcome.

Conditional Compute Operations

While in SIMD mode, a conditional compute operation can execute on both PEs, either PE, or neither PE, depending on the outcome of the status flag test. Flag testing is independently performed on each PE.

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Conditional Branches and Loops

The processor executes a conditional branch (JUMP or CALL/return) or loop (DO/UNTIL) based on the result of ANDing the condition tests on both PEx and PEy. A conditional branch or loop in SIMD mode occurs only when the condition is true in PEx and PEy. Using complementary conditions (for example EQ and NE), programs can produce an ORing of the condition tests for branches and loops in SIMD mode. A conditional branch or loop that uses this technique should consist of a series of conditional compute operations. These conditional computes generate NOPs on the processing element where a branch or loop does not execute. For more information on programming in SIMD mode, see the ADSP-21160 SHARC DSP Instruction Set Reference.

Conditional Data Moves

The execution of a conditional (IF) data move (register-to-register and register-to/from-memory) instruction depends on three factors: The explicit data move depends on the evaluation of the conditional test in the PEx processing element The implicit data move depends on the evaluation of the conditional test in the PEy processing element Both moves depend on the types of registers used in the move There are four cases for SIMD conditional data moves:

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Case 1: Complementary Register Pair Data Move In this case data moves from a complementary register pair to a complementary register pair. The processor executes the explicit move depending on the evaluation of the conditional test in the PEx processing element and the implicit move depending on the evaluation of the conditional test in the PEy processing element. Example: RegistertoMemory Move PEx Explicit Register
IF EQ DM(I0,M0) = R2;

For this instruction the processor is operating in SIMD mode, a register in the PEx data register file is the explicit register and I0 is pointing to an even address in internal memory. Indirect addressing is shown in the instructions shown in this example. However, the same results occur using direct addressing. The data movement resulting from the evaluation of the conditional test in the PEx and PEy processing elements is shown in Table 3-21. Table 3-21. RegistertoMemory Moves Complementary Pairs
Condition in PEx AZx 0 0 1 1 Condition in PEy AZy 0 1 0 1 Result Explicit NO data move occurs NO data move occurs from r2 to location I0 r2 transfers to location I0 r2 transfers to location I0 Implicit NO data move occurs s2 transfers to location (I0+1) NO data move occurs from s2 to location (I0+1) s2 transfers to location (I0+1)

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Example: RegistertoMemory Move PEy Explicit Register

IF EQ DM(I0,M0) = S2;

For this instruction the processor is operating in SIMD mode, a register in the PEy data register file is the explicit register and I0 is pointing to an even address in internal memory. The data movement resulting from the evaluation of the conditional test in the PEx and PEy processing elements is shown in Table 3-22. Table 3-22. RegistertoRegister Moves Complementary Pairs
Condition in PEx AZx 0 0 1 1 Condition in PEy AZy 0 1 0 1 Result Explicit NO data move occurs NO data move occurs from s2 to location I0 s2 transfers to location I0 s2 transfers to location I0 Implicit NO data move occurs r2 transfers to location I0+1 NO data move occurs from r2 to location I0+1 r2 transfers to location I0+1

Examples: RegistertoRegister Move Instructions

IF EQ R8 = R2; IF EQ PX1 = R2; IF EQ USTAT1 = R2;

For these instruction the processor is operating in SIMD mode and registers in the PEx data register file are used as the explicit registers. The data movement resulting from the evaluation of the conditional test in the PEx and PEy processing elements is shown in Table 3-23.

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Table 3-23. RegistertoRegister Moves Complementary Pairs

Condition in PEx AZx 0 0 1 1 Condition in PEy AZy 0 1 0 1 Result Explicit NO data move occurs NO data move to registers r9,px1,ustat1 occurs r2 transfers to registers r9,px1 and ustat1 r2 transfers to registers r9,px1, and ustat1 Implicit NO data move occurs s2 transfers to registers s9,px2 and ustat2 NO data move to s9, px2, or ustat2 occurs s2 transfers to registers s9,px2,and ustat2

Examples: RegistertoRegister Move Instructions

IF EQ R8 = S2; IF EQ PX1 = S2; IF EQ USTAT1 = S2;

For these instructions the processor is operating in SIMD mode and registers in the PEy data register file are used as explicit registers. The data movement resulting from the evaluation of the conditional test in the PEx and PEy processing elements is shown in Table 3-24. Table 3-24. RegistertoRegister Moves Complementary Register Pairs
Condition in PEx AZx 0 0 Condition in PEy AZy 0 1 Result Explicit NO data move occurs NO data move to registers s9,px and ustat1 occurs Implicit NO data move occurs r2 transfers to registers s9,px2, and ustat2

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Table 3-24. RegistertoRegister Moves Complementary Register Pairs (Contd)

Condition in PEx AZx 1 1 Condition in PEy AZy 0 1 Result Explicit s2 transfers to registers r9,px1 and ustat1 s2 transfers to registers r9,px1, and ustat1 Implicit NO data move to registers s9,px2, and ustat2 occurs r2 transfers to registers s9,px2, and ustat2

Case 2: UncomplementedtoComplementary Register Move In this case data moves from an uncomplemented register (Ureg without a SIMD complement) to a complementary register pair. The processor executes the explicit move depending on the evaluation of the conditional test in the PEx processing element. The processor executes the implicit move depending on the evaluation of the conditional test in the PEy processing element. In each processing element where the move occurs, the content of the source register is duplicated in destination. Example: RegistertoRegister Move
IF EQ R1 = PX;

While PX1 and PX2 are complementary registers, the combined PX register has no complementary register. For more information, see Internal Data Bus Exchange on page 5-10. For this instruction the processor is operating in SIMD mode. The data movement resulting from the evaluation of the conditional test in the PEx and PEy processing elements is shown in Table 3-24.

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SIMD Mode and Sequencing

Table 3-25. ComplementarytoUncomplemented Register Move

Condition in PEx AZx 0 0 1 1 Condition in PEy AZy 0 1 0 1 Result Explicit r1 remains unchanged r1 remains unchanged r1 gets px value r1 gets px value Implicit s1 remains unchanged s1 gets px value s1 remains unchanged s1 gets px value

Case 3: Complementary Register => Uncomplimentary Register In this case data moves from a complementary register pair to an uncomplemented register. The processor executes the explicit move to the uncomplemented universal register, depending on the condition test in the PEx processing element only. The processor does not perform an implicit move. Example: RegistertoRegister Move
IF EQ PX = R1;

For this instruction the processor is operating in SIMD mode. The data movement resulting from the evaluation of the conditional test in the PEx and PEy processing elements is shown in Table 3-26. Table 3-26. ComplementarytoUncomplemented Move
Condition in PEx AZx 0 0 Condition in PEy AZy 0 1 Result Explicit px remains unchanged px remains unchanged Implicit no implicit move no implicit move

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Table 3-26. ComplementarytoUncomplemented Move (Contd)

Condition in PEx AZx 1 1 Condition in PEy AZy 0 1 Result Explicit r1 40-bit explicit move to px r1 40-bit explicit move to px Implicit no implicit move no implicit move

For more details on PX register transfers, refer to Internal Data Bus Exchange on page 5-10. Case 4: Data Move Involves External Memory or IOP Memory Space Conditional data moves from a complementary register pair to an uncomplemented register with an access to external memory space or IOP memory space. This results in unexpected behavior and should not be used.
IF EQ DM(I0,M0) = R2; IF EQ DM(I0,M0) = S2;

For these instruction the processor is operating in SIMD mode and the explicit register is either a PEx register or PEy register. I0 points to either external memory space or IOP memory space. Indirect addressing is shown in the instructions shown in this example. However, the same results occur using direct addressing.

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SIMD Mode and Sequencing

Conditional DAG Operations

Conditional post-modify DAG operations update the DAG register based on ORing of the condition tests on both processing elements. Actual data movement involved in a conditional DAG operation is based on independent evaluation of condition tests in PEx and PEy. Only the post modify update is based on the ORing of the these conditional tests. Conditional pre-modify DAG operations behave differently. The DAGs always pre-modify an index, independent of the outcome of the condition tests on each processing element.

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4 DATA ADDRESS GENERATOR

The processors Data Address Generators (DAGs) generate addresses for data moves to and from Data Memory (DM) and Program Memory (PM). By generating addresses, the DAGs let programs refer to addresses indirectly, using a DAG register instead of an absolute address. The DAGs architecture, which appears in Figure 4-1, supports several functions that minimize overhead in data access routines. These functions include: Supply address and post-modifyprovides an address during a data move and auto-increments the stored address for the next move. Supply pre-modified addressprovides a modified address during a data move without incrementing the stored address. Modify addressincrements the stored address without performing a data move. Bit-reverse addressprovides a bit-reversed address during a data move without reversing the stored address. Broadcast data movesperforms dual data moves to complementary registers in each processing element to support SIMD mode.

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Setting DAG Modes

As shown in Figure 4-1, each DAG has four types of registers. These registers hold the values that the DAG uses for generating addresses. The four types of registers are: Index registers (I0-I7 for DAG1 and I8-I15 for DAG2). An index register holds an address and acts as a pointer to memory. For example, the DAG interprets DM(I0,0) and PM(I8,0) syntax in an instruction as addresses. Modify registers (M0-M7 for DAG1 and M8-M15 for DAG2). A modify register provides the increment or step size by which an index register is pre- or post-modified during a register move. For example, the DM(I0, M1) instruction directs the DAG to output the address in register I0 then modify the contents of I0 using the M1 register. Length and Base registers (L0-L7 and B0-B7 for DAG1 and L8-L15 and B8-B15 for DAG2). Length and base registers setup the range of addresses and the starting address for a circular buffer. For more information on circular buffers, see Addressing Circular Buffers on page 4-12.

Setting DAG Modes

The MODE1 register controls the operating mode of the DAGs. Table A-2 on page A-3 lists all the bits in MODE1. The following bits in MODE1 control Data Address Generator modes: Circular buffering enable. Bit 24 (CBUFEN) enables circular buffering (if 1) or disables circular buffering (if 0). Broadcast register loading enable, DAG1-I1. Bit 23 (BDCST1) enables register broadcast loads to complementary registers from I1 indexed moves (if 1) or disables broadcast loads (if 0).

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Data Address Generator

DM OR PM DATA BUS 32 IMMEDIATE VALUE FROM INSTRUCTION 32 32 32

I REGISTERS 8 X 32 32

M REGISTERS 8 X 32

L REGISTERS 8 X 32

B REGISTERS 8 X 32

MUX

POST-MODIFY ADDRESSING

MODULUS LOGIC

32

ADD BIT-REVERSE (OPTIONAL) MUX 32 PRE-MODIFY ADDRESSING 32

UPDATE

ADDRESS ADJUSTMENT PER WORD SIZE (SHORT, NORMAL, OR LONG) OPTIONAL BIT-REVERSE FOR I0-DAG1 & I8-DAG2 OPTIONAL BROADCAST FOR I1-DAG1 & I9-DAG2 32 32 MODE1

PM ADDRESS BUS (DAG2 - I,M,L,B8-15)

MODE2

DM ADDRESS BUS (DAG1 - I,M,L,B0-7)

STKYX

Figure 4-1. Data Address Generator (DAG) Block Diagram Broadcast register loading enable, DAG2-I9. Bit 22 (BDCST9) enables register broadcast loads to complementary registers from I9 indexed moves (if 1) or disables broadcast loads (if 0). SIMD mode enable. Bit 21 (PEYEN) enables computations in PEySIMD mode(if 1) or disables PEySISD mode(if 0). For more information on SIMD mode, see Secondary Processing Element (PEy) on page 2-37.

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Setting DAG Modes

Secondary registers for DAG2 lo, I,M,L,B8-11. Bit 6 (SRD2L) Secondary registers for DAG2 hi, I,M,L,B12-15. Bit 5 (SRD2H) Secondary registers for DAG1 lo, I,M,L,B0-3. Bit 4 (SRD1L) Secondary registers for DAG1 hi, I,M,L,B4-7. Bit 3 (SRD1H) These bits select the corresponding secondary register set (if 1) or select the corresponding primary register setthe set that is available at reset(if 0). Bit-reverse addressing enable, DAG1-I0. Bit 1 (BR0) enables bit-reversed addressing on I0 indexed moves (if 1) or disables bit-reversed addressing (if 0). Bit-reverse addressing enable, DAG2-I8. Bit 0 (BR8) enables bit-reversed addressing on I8 indexed moves (if 1) or disables bit-reversed addressing (if 0).

Circular Buffering Mode

The CBUFEN bit in the MODE1 register enables circular bufferinga mode in which the DAG supplies addresses ranging within a constrained buffer length (set with an L register), starting at a base address (set with a B register), and incrementing the addresses on each access by a modify value (set with an M register). For revision 1.0 and greater of ADSP-21161 processor, the Circular Buffer Enable bit (CBUFEN) in SYSCON is set (=1) upon reset. For earlier silicon revisions 0.x, this bit is cleared (=0) upon reset. This change was made to ensure code compatibility with the ADSP-2106x SHARC family (ADSP-21060/1/2 and ADSP-21065L) where circular buffering is active upon reset. However, circular buffering is disabled upon reset for the ADSP-21160. Make note of this when porting code from ADSP-21160 to ADSP-21161 processor.

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Data Address Generator

For more information on setting up and using circular buffers, see Addressing Circular Buffers on page 4-12. When using circular buffers, the DAGs can generate an interrupt on buffer overflow (wrap around). For more information, see Using DAG Status on page 4-8.

Broadcast Loading Mode

The BDCST1 and BDCST9 bits in the MODE1 register enable broadcast loading modemultiple register loads from a single load command. When the BDCST1 bit is set (1), the DAG performs a dual data register load on instructions that use the I1 register for the address. The DAG loads both the named register (explicit register) in one processing element and loads that registers complementary register (implicit register) in the other processing element. The BDCST9 bit in the MODE1 register enables this feature for the I9 register. Enabling either DAG1 or DAG2 register load broadcasting has no effect on register stores or loads to universal registers other than the register file data registers. Table 4-1 demonstrates the effects of a register load operation on both processing elements with register load broadcasting enabled. In Table 4-1, note that Rx and Sx are complementary data registers. Table 4-1. Dual Processing Element Register Load Broadcasts
Instruction syntax Rx = DM(I1,Ma); {Syntax #1} Rx = PM(I9,Mb); {Syntax #2} Rx = DM(I1,Ma), Rx = PM(I9,Mb); {Syntax #3} Rx = DM(I1,Ma); {Explicit #1} Rx = PM(I9,Mb); {Explicit #2} Rx = DM(I1,Ma), Rx = PM(I9,Mb); {Explicit #3} Sx = DM(I1,Ma); {Implicit #1} Sx = PM(I9,Mb); {Implicit #2} Sx = DM(I1,Ma), Sx = PM(I9,Mb); {Implicit #3}

PEx explicit operations

PEy implicit operations

1. Note that the letters a and b (as in Ma or Mb) indicate numbers for modify registers in DAG1 and DAG2. The letter a indicates a DAG1 register and can be replaced with 0 through 7. The letter b indicates a DAG2 register and can be replaced with 8 through 15.

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Setting DAG Modes

The PEYEN bit (SISD/SIMD mode select) does not influence broadcast operations. Broadcast loading is particularly useful in SIMD applications where the algorithm needs identical data loaded into each processing element. For more information on SIMD mode (in particular, a list of complementary data registers), see Secondary Processing Element (PEy) on page 2-37.

Alternate (Secondary) DAG Registers

Each DAG has an alternate register set. To facilitate fast context switching, the processor includes alternate register sets for data, results, and data address generator registers. Bits in the MODE1 register control when alternate registers become accessible. While inaccessible, the contents of alternate registers are not effected by processor operations. Note that there is a one cycle latency between writing to MODE1 and being able to access an alternate register set. The alternate register sets for the DAGs are described in this section. For more information on alternate data and results registers, see Alternate (Secondary) Data Registers on page 2-32. Bits in the MODE1 register can activate alternate register sets within the DAGs: the lower half of DAG1 (I,M,L,B0-3), the upper half of DAG1 (I,M,L,B4-7), the lower half of DAG2 (I,M,L,B8-11), and the upper half of DAG2 (I,M,L,B12-15). Figure 4-1 shows the DAGs primary and alternate register sets. To share data between contexts, a program places the data to be shared in one half of either the current DAGs registers or the other DAGs registers and activates the alternate register set of the other half. The following example demonstrates how code should handle the one cycle of latency

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Data Address Generator

MODE1 SELECT BIT

DAG1 REGISTERS (DATA MEMORY)

I0 I1 M0 M1 M2 M3 L0 L1 L2 L3 B0 B1 B2 B3

SRD1L

I2 I3

I4 I5 SRD1H I6 I7

M4 M5 M6 M7

L4 L5 L6 L7

B4 B5 B6 B7

DAG2 REGISTERS (PROGRAM MEMORY)

I8 I9 SRD2L I10 I11 I12 I13 SRD2H I14 I15 M8 M9 M10 M11 L8 L9 L10 L11 L12 L13 L14 L15 B8 B9 B10 B11

M12 M13 M14 M15

B12 B13 B14 B15

Figure 4-2. Data Address Generator Primary and Alternate Registers from the instruction setting the bit in MODE1 to when the alternate registers may be accessed. Note that it is possible to use any instruction that does not access the switching register file instead of an NOP instruction.
BIT SET MODE1 SRD1L; NOP; R0=DM(i0,m1); /* Activate alternate dag1 lo regs */ /* Wait for access to alternates */

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Using DAG Status

Bit-reverse Addressing Mode

The BR0 and BR8 bits in the MODE1 register enable bit-reverse addressing modeoutputting addresses in reverse bit order. When BR0 is set (1), DAG1 bit-reverses 32-bit addresses output from I0. When BR8 is set (1), DAG2 bit-reverses 32-bit addresses output from I8. The DAGs only bit-reverse the address output from I0 or I8; the contents of these registers are not reversed. Bit-reverse addressing mode effects both pre-modify and post-modify operations. The following example demonstrates how bit-reverse mode effects address output:
BIT SET Mode1 BR0; I0=0x8a000; M0=0x4000000; R1=DM(I0,M0); /* Enables bit-rev. addressing for DAG1 */ /* Loads I0 with the bit reverse of the /* Loads M0 with value for post-modify */ /* Loads r1 with contents of DM address

buffers base address, DM(0x51000) */

DM(0x51000), which is the bit-reverse of 0x8a000, then post modifies I0 for the next access with (0x8a000 + 0x4000000)=0x408a000, which is the bit-reverse of DM(0x51020) */

In addition to bit-reverse addressing mode, the processor supports a bit-reverse instruction (BITREV). This instruction bit-reverses the contents of the selected register. For more information on the BITREV instruction, see Modifying DAG Registers on page 4-17 or the ADSP-21160 SHARC DSP Instruction Set Reference.

Using DAG Status

As described in Addressing Circular Buffers on page 4-12, the DAGs can provide addressing for a constrained range of addresses, repeatedly cycling through this data (or buffer). A buffer overflow (or wrap around) occurs each time the DAG circles past the buffers base address.

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Data Address Generator

The DAGs can provide buffer overflow information when executing circular buffer addressing for I7 or I15. When a buffer overflow occurs (a circular buffering operation increments the I register past the end of the buffer), the appropriate DAG updates a buffer overflow flag in a sticky status (STKYx) register. A buffer overflow can also generate a maskable interrupt. Two ways to use buffer overflows from circular buffering are: Interrupts. Enable interrupts and use an interrupt service routine to handle the overflow condition immediately. This method is appropriate if it is important to handle all overflows as they occur; for example in a ping-pong or swap I/O buffer pointers routine. STKYx registers. Use the BIT TST instruction to examine overflow flags in the STKY register after a series of operations. If an overflow flag is set, the buffer has overflowedwrapped aroundat least once. This method is useful when overflow handling is not critical.

DAG Operations
The processors DAGs perform several types of operations to generate data addresses. As shown in Figure 4-1 on page 4-3, the DAG registers and the MODE1, MODE2, and STKYx registers all contribute to DAG operations. The following sections provide details on DAG operations: Addressing With DAGs on page 4-10 Addressing Circular Buffers on page 4-12 Modifying DAG Registers on page 4-17 An important item to note from Figure 4-1 on page 4-3 is that the DAG automatically adjusts the output address per the word size of the address location (short word, normal word, or long word). This address adjustment lets internal memory use the address directly.

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DAG Operations

SISD/SIMD mode, access word size, and data location (internal/external) all influence data access operations.

Addressing With DAGs

The DAGs support two types of modified addressinggenerating an address that is incremented by a value or a register. In pre-modify addressing, the DAG adds an offset (modifier), either an M register or an immediate value, to an I register and outputs the resulting address. Pre-modify addressing does not change (or update) the I register. The other type of modified addressing is post-modify addressing. In post-modify addressing, the DAG outputs the I register value unchanged then adds an M register or immediate value, updating the I register value. Figure 4-3 compares pre- and post-modify addressing.
PRE-MODIFY NO I REGISTER UPDATE
SYNTAX: PM(MX, IX) DM(MX, IX)

POST-MODIFY I REGISTER UPDATE

SYNTAX: PM(IX, MX) DM(IX, MX) 2. UPDATE I

1. OUTPUT

+
M

+
M

OUTPUT

I+M

I+M

Figure 4-3. Pre-Modify and Post-Modify Operations The difference between pre-modify and post-modify instructions in the processors assembly syntax is the position of the index and modifier in the instruction. If the I register comes before the modifier, the instruction is a post-modify operation. If the modifier comes before the I register, the

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Data Address Generator

instruction is a pre-modify without update operation. The following instruction accesses the program memory location indicated by the value in I15 and writes the value I15 + M12 to the I15 register:
R6 = PM(I15,M12); /* Post-modify addressing with update */

By comparison, the following instruction accesses the program memory location indicated by the value I15 + M12 and does not change the value in I15:
R6 = PM(M12,I15); /* Pre-modify addressing without update */

Modify (M) registers can work with any index (I) register in the same DAG (DAG1 or DAG2). For a list of I and M registers and their DAGs, see Figure 4-2 on page 4-7. Instructions can use a number (immediate value), instead of an M register, as the modifier. The size of an immediate value that can modify an I register depends on the instruction type. For all single data access operations, modify immediate values can be up to 32 bits wide. Instructions that combine DAG addressing with computations limit the size of the modify immediate value. In these instructions (multifunction computations), the modify immediate values can be up to 6 bits wide. The following example instruction accepts up to 32-bit modifiers:
R1=DM(0x40000000,I1); /* DM address = I1+0x4000 0000 */

The following example instruction accepts up to 6-bit modifiers:

F6=F1+F2,PM(I8,0x0B)=ASTAT; /* PM address = I8, I8=I8+0x0B */

Note that pre-modify addressing operations must not change the memory space of the address. For example, pre-modifying an address in the processors internal memory space should not generate an address in external memory space.

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DAG Operations

Addressing Circular Buffers

The DAGs support addressing circular buffersa range of addresses containing data that the DAG steps through repeatedly, wrapping around to repeat stepping through the range of addresses in a circular pattern. To address a circular buffer, the DAG steps the index pointer (I register) through the buffer, post-modifying and updating the index on each access with a positive or negative modify value (M register or immediate value). If the index pointer falls outside the buffer, the DAG subtracts or adds the length of the buffer from or to the value, wrapping the index pointer back to the start of the buffer. The DAGs support for circular buffer addressing appears in Figure 4-1 on page 4-3, and an example of circular buffer addressing appears in Figure 4-4. The starting address that the DAG wraps around is called the buffers base address (B register). There are no restrictions on the value of the base address for a circular buffer. Circular buffering may only use post-modify addressing. The DAGs architecture, as shown in Figure 4-1 on page 4-3, cannot support pre-modify addressing for circular buffering, because circular buffering requires that the index be updated on each access. It is important to note that the DAGs do not detect memory map overflow or underflow. If the address post-modify produces I+M > 0xFFFF FFFF or IM < 0, circular buffering may not function correctly. Also, the length of a circular buffer should not let the buffer straddle the top of the memory map. For more information on the processors memory map, see Internal Address and Data Buses on page 5-7.

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THE FOLLOWING SYNTAX SETS UP AND ACCESSES A CIRCULAR BUFFER WITH: LENGTH = 11 BASE ADDRESS = 0X55000 MODIFIER = 4 BIT SET MODE1 CBUFEN; /* ENABLES CIRCULAR BUFFER ADDRESSING; JUST ONCE IN PROGRAM */ B0 = 0X55000; /* LOADS B0 AND L0 REGISTERS WITH BASE ADDRESS */ L0 = 0XB; /* LOADS L0 REGISTER WITH LENGTH OF BUFFER */ M1 = 0X4; /* LOADS M1 WITH MODIFIER OR STEP SIZE */ LCNTR = 11, DO MY_CIR_BUFFER UNTIL LCE; /* SETS UP A LOOP CONTAINING BUFFER ACCESSES */ R0 = DM(I0,M1); /* AN ACCESS WITHIN THE BUFFER USES POST MODIFY ADDRESSING */ ... /* OTHER INSTRUCTIONS IN THE MY_CIR_BUFFER LOOP */ MY_CIR_BUFFER: NOP; /* END OF MY_CIR_BUFFER LOOP */ 0 1 2 3 4 5 6 7 8 9 10 3 2 1 0 1 2 3 4 5 6 7 8 9 10 6 5 4 0 1 2 3 4 5 6 7 8 9 10 9 8 7 0 1 2 3 4 5 6 7 8 9 10 11 10

THE COLUMNS ABOVE SHOW THE SEQUENCE IN ORDER OF LOCATIONS ACCESSED IN ONE PASS. NOTE THAT "0" ABOVE IS ADDRESS DM(0X55000). THE SEQUENCE REPEATS ON SUBSEQUENT PASSES.

Figure 4-4. Circular Data Buffers As shown in Figure 4-4, programs use the following steps to set up a circular buffer: 1. Enable circular buffering (BIT SET is only needed once in a program.
Mode1 CBUFEN;).

This operation

2. Load the buffers base address into the B register. This operation automatically loads the corresponding I register.

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DAG Operations

3. Load the buffers length into the corresponding L register. For example, L0 corresponds to B0. 4. Load the modify value (step size) into an M register in the corresponding DAG. For example, M0 through M7 correspond to B0. Alternatively, the program can use an immediate value for the modifier. After this set up, the DAGs use the modulus logic in Figure 4-1 on page 4-3 to process circular buffer addressing. On the ADSP-21161 processor, programs enable circular buffering by setting the CBUFEN bit in the MODE1 register. This bit has a corresponding mask bit in the MMASK register. Setting the corresponding MMASK bit causes the CBUFEN bit to be cleared following a push status instruction (PUSH STS), the execution of an external interrupt, timer interrupt, or vectored interrupt. This feature lets programs disable circular buffering while in an interrupt service routine that does not use circular buffering. By disabling circular buffering, the routine does not need to save and restore the DAGs B and L registers. Clearing the CBUFEN bit disables circular buffering for all data load and store operations. The DAGs perform normal post-modify load and store accesses instead, ignoring the B and L register values. Note that a write to a B register modifies the corresponding I register, independent of the state of the CBUFEN bit. The MODIFY instruction executes independent of the state of the CBUFEN bit. The MODIFY instruction always performs circular buffer modify of the index registers if the corresponding B and L registers are set up, independent of the state of the CBUFEN bit. For revision 1.0 and greater of ADSP-21161 processor, the Circular Buffer Enable bit (CBUFEN) in SYSCON is set (=1) upon reset. For earlier silicon revisions 0.x, this bit is cleared (=0) upon reset. This change was made to ensure code compatibility with the ADSP-2106x SHARC family (ADSP-21060/1/2 and ADSP-21065L) where circular buffering is active upon reset.

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Data Address Generator

However, circular buffering is disabled upon reset for the ADSP-21160. Make note of this when porting code from ADSP-21160 to ADSP-21161 processor. On the first post-modify access to the buffer, the DAG outputs the I register value on the address bus then modifies the address by adding the modify value. If the updated index value is within the buffer length, the DAG writes the value to the I register. If the updated value is outside the buffer length, the DAG subtracts (positive) or adds (negative) the L register value before writing the updated index value to the I register. In equation form, these post-modify and wrap around operations work as follows: If M is positive: Inew = Iold + M if Iold + M < Buffer base + length (end of buffer) Inew = Iold + M L if Iold + M Buffer base + length (end of buffer) If M is negative: Inew = Iold + M if Iold + M Buffer base (start of buffer) Inew = Iold + M + L if Iold + M < Buffer base (start of buffer) The DAGs use all four types of DAG registers for addressing circular buffers. These registers operate as follows for circular buffering: The index (I) register contains the value that the DAG outputs on the address bus. The modify (M) register contains the post-modify amount (positive or negative) that the DAG adds to the I register at the end of each memory access. The M register can be any M register in the same DAG as the I register and does not have to have the same number. The modify value also can be an immediate value instead

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DAG Operations

of an M register. The size of the modify value, whether from an M register or immediate, must be less than the length (L register) of the circular buffer. The length (L) register sets the size of the circular buffer and the address range that the DAG circulates the I register through. L must be positive and cannot have a value greater than 231 1. If an L registers value is zero, its circular buffer operation is disabled. The base (B) register, or the B register plus the L register, is the value that the DAG compares the modified I value with after each access. When the B register is loaded, the corresponding I register is simultaneously loaded with the same value. When I is loaded, B is not changed. Programs can read the B and I registers independently. There is one set of registers (I7 and I15) in each DAG that can generate an interrupt on circular buffer overflow (address wraparound). For more information, see Using DAG Status on page 4-8. When a program needs to use I7 or I15 without circular buffering and the processor has the circular buffer overflow interrupts unmasked, the program should disable the generation of these interrupts by setting the B7/B15 and L7/L15 registers to values that prevent the interrupts from occurring. If I7 were accessing the address range 0x10000x2000, the program could set B7=0x0000 and L7=0xFFFF. Because the processor generates the circular buffer interrupt based on the wrap around equations on page 4-15, setting the L register to zero does not necessarily achieve the desired results. If the program is using either of the circular buffer overflow interrupts, it should avoid using the corresponding I register(s) (I7 or I15) where interrupt branching is not needed.

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Data Address Generator

In the case of circular buffer overflow interrupts, if CBUFEN = 1 and register L7 = 0 (or L15 = 0), then the CB7I (or CB15I) interrupt occurs at every change of I7 (or I15), after the index register (I7 or I15) crosses the base register (B7 or B15) value. This behavior is independent of the context of the DAG registers, both primary and alternate. When a Long word access, SIMD access, or Normal word access (with LW option) crosses the end of the circular buffer, the processor completes the access before responding to the end of buffer condition.

Modifying DAG Registers

The DAGs support two operations that modify an address value in an index register without outputting an address. These two operations, address bit-reversal and address modify, are useful for bit-reverse addressing and maintaining pointers. The MODIFY instruction modifies addresses in any DAG index register (I0-I15) without accessing memory. If the I registers corresponding B and L registers are set up for circular buffering, a MODIFY instruction performs the specified buffer wrap around (if needed). The syntax for MODIFY is similar to post-modify addressing (index, then modifier). MODIFY accepts either a 32-bit immediate values or an M register as the modifier. The following example adds 4 to I1 and updates I1 with the new value:
MODIFY(I1,4);

The BITREV instruction modifies and bit-reverses addresses in any DAG index register (I0-I15) without accessing memory. This instruction is independent of the bit-reverse mode. The BITREV instruction adds a 32-bit immediate value to a DAG index register, bit-reverses the result, and writes the result back to the same index register. The following example adds 4 to I1, bit-reverses the result, and updates I1 with the new value:
BITREV(I1,4);

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DAGs, Registers, and Memory

Addressing in SISD and SIMD Modes

Single-Instruction, Multiple-Data (SIMD) mode (PEYEN bit=1) does not change the addressing operations in the DAGs, but it does change the amount of data that moves during each access. The DAGs put the same addresses on the address buses in SIMD and SISD modes. In SIMD mode, the processors memory and processing elements get data from the locations named (explicit) in the instruction syntax and complementary (implicit) locations. For more information on data moves between registers, see Secondary Processing Element (PEy) on page 2-37.

DAGs, Registers, and Memory

DAG registers are part of the processors universal register set. Programs may load the DAG registers from memory, from another universal register, or with an immediate value. Programs may store DAG registers contents to memory or to another universal register. The DAGs registers support the bidirectional register-to-register transfers that are described in SIMD (Computational) Operations on page 2-43. When the DAG register is a source of the transfer, the destination can be a register file data register. This transfer results in the contents of the single source register being duplicated in complementary data registers in each processing element. Programs should use care in the case where the DAG register is a destination of a transfer from a register file data register source. Programs should use a conditional operation to select either one processing element or neither as the source. Having both processing elements contribute a source value results in the PEx elements write having precedence over the PEy elements write. In the case where a DAG register is both source and destination, the data move operation executes the same as it would if SIMD mode were disabled (PEYEN cleared). 4-18 ADSP-21161 SHARC Processor Hardware Reference

Data Address Generator

DAG Register-to-Bus Alignment

There are three word alignment cases for DAG registers and PM or DM data buses: Normal word, Extended-precision Normal word, and Long word. The DAGs align normal word (32-bit) addressed transfers to the low order bits of the buses. These transfers between memory and 32-bit DAG1 or DAG2 registers use the 64-bit DM and PM data buses. Figure 4-5 illustrates these transfers.
DM OR PM DATA BUS
63 0X0000 0000 31 0

31

DAG1 OR DAG2 REGISTERS

Figure 4-5. Normal Word (32-bit) DAG Register Memory Transfers The DAGs align extended-precision normal word (40-bit) addressed transfers or register-to-register transfers to bits 39-8 of the buses. These transfers between a 40-bit data register and 32-bit DAG1 or DAG2 registers use the 64-bit DM and PM data buses. Figure 4-6 illustrates these transfers.

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DAGs, Registers, and Memory

DM OR PM DATA BUS
63 0X0000 00 39 8 0X00 0

31

DAG1 OR DAG2 REGISTERS

Figure 4-6. DAG Register to Data Register Transfers Long word (64-bit) addressed transfers between memory and 32-bit DAG1 or DAG2 registers target double DAG registers and use the 64-bit DM and PM data buses. Figure 4-7 illustrates how the bus works in these transfers. If the Long word transfer specifies an even-numbered DAG register (e.g., I0 or I2), then the even numbered register value transfers on the lower half of the 64-bit bus, and the even numbered register + 1 value transfers on the upper half (bits 63-32) of the bus.
DM OR PM DATA BUS
63 31 0

31

31

IMPLICIT (NAMED+1) DAG1 OR DAG2 REGISTERS

EXPLICIT (NAMED) DAG1 OR DAG2 REGISTERS

Figure 4-7. Long Word DAG Register to Data Register Transfers If the Long word transfer specifies an odd numbered DAG register (e.g., I1, or B3), the odd numbered register value transfers on the lower half of the 64-bit bus, and the odd numbered register - 1 value (I0 or B2 in this example) transfers on the upper half (bits 63-32) of the bus.

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Data Address Generator

In both the even- and odd-numbered cases, the explicitly specified DAG register sources or sinks bits 31-0 of the Long word addressed memory.

DAG Register Transfer Restrictions

The two types of transfer restrictions are hold-off conditions and illegal conditions that the processor does not detect. For certain instruction sequences involving transfers to and from DAG registers, an extra ( NOP) cycle is automatically inserted by the processor. When an instruction that loads a DAG register is followed by an instruction that uses any register in the same DAG register pair1 for data addressing, modify instructions, or indirect jumps, the processor inserts an extra (NOP) cycle between the two instructions. This hold-off happens because the same bus is needed by both operations in the same cycle. So, the second operation must be delayed. The following case causes a delay because it exhibits a write/read dependency in which I0 is written in one cycle. The results of that register write are not available to a register read for one cycle. Note that if either instruction had specified I1, the stall would still occur, because the processors DAG register transfers can occur in pairs. The DAG detects write/read dependencies with a register pair granularity:
I0=8; DM(I0,M1)=R1;

DAG register are accessible in pair granularity for single-cycle access. The pairings are odd-even. For example I0 and I1 are a pair, and I2 and I3 are a pair.

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DAGs, Registers, and Memory

Certain other sequences of instructions cause incorrect results on the processor and are flagged as errors by processor assembler software. These types of instructions can execute on the processor, but cause incorrect results: An instruction that stores a DAG register in memory using indirect addressing from the same DAG, with or without update of the index register. The instruction writes the wrong data to memory or updates the wrong index register. Do not try these: DM(M2,I1)=I0; or DM(I1,M2)=I0; These example instructions do not work because I0 and I1 are both DAG1 registers. An instruction that loads a DAG register from memory using indirect addressing from the same DAG, with update of the index register. The instruction either loads the DAG register or updates the index register, but not both. Do not try this: L2=DM(I1,M0); This example instruction does not work because L2 and I1 are both DAG1 registers.

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Data Address Generator

DAG Instruction Summary

Table 4-3 through, Table 4-9 list the DAG instructions. For more information on assembly language syntax, see the ADSP-21160 SHARC DSP Instruction Set Reference. In these tables, note the meaning of the following symbols: I15-8 indicates a DAG2 index register: I15, I14, I13, I12, I11, I10, I9, or I8, and I7-0 indicates a DAG1 index register I7, I6, I5, I4, I3, I2, I1, or I0. M15-8 indicates a DAG2 modify register: M15, M14, M13, M12, M11, M10, M9, or M8, and M7-0 indicates a DAG1 modify register M7, M6, M5, M4, M3, M2, M1, or M0. Ureg indicates any universal register; For a list of the processors universal registers, see Table A-1 on page A-2. Dreg indicates any data register; For a list of the processors data registers, see the Data Register File registers that are listed in Table A-1 on page A-2. Data32 indicates any 32-bit value, and Data6 indicates any 6-bit value Table 4-2. Post-Modify Addressing, Modified By M Register and Updating I Register
DM(I7-0,M7-0)=Ureg (LW); {DAG1} PM(I15-8,M15-8)=Ureg (LW); {DAG2} Ureg=DM(I7-0,M7-0) (LW); {DAG1} Ureg=PM(I15-8,M15-8) (LW); {DAG2} DM(I7-0,M7-0)=Data32; {DAG1} PM(I15-8,M15-8)=Data32; {DAG2}

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DAG Instruction Summary

Table 4-3. Post-Modify Addressing, Modified By 6-Bit Data and Updating I Register
DM(I7-0,Data6)=Dreg; {DAG1} PM(I15-8,Data6)=Dreg; {DAG2} Dreg=DM(I7-0,Data6); {DAG1} Dreg=PM(I15-8,Data6); {DAG2}

Table 4-4. Pre-Modify Addressing, Modified By M Register (No I Register Update)

DM(M7-0,I7-0)=Ureg (LW); {DAG1} PM(M15-8,I15-8)=Ureg (LW); {DAG2} Ureg=DM(M7-0,I7-0) (LW); {DAG1} Ureg=PM(M15-8,I15-8) (LW); {DAG2}

Table 4-5. Pre-Modify Addressing, Modified By 6-Bit Data (No I Register Update)
DM(Data6,I7-0)=Dreg; {DAG1} PM(Data6,I15-8)=Dreg; {DAG2} Dreg=DM(Data6,I7-0); {DAG1} Dreg=PM(Data6,I15-8); {DAG2}

Table 4-6. Pre-Modify Addressing, Modified By 32-Bit Data (No I Register Update)
Ureg=DM(Data32,I7-0) (LW); {DAG1} Ureg=PM(Data32,I15-8) (LW); {DAG2} DM(Data32,I7-0)=Ureg (LW); {DAG1} PM(Data32,I15-8)=Ureg (LW); {DAG2}

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Data Address Generator

Table 4-7. Update (Modify) I Register, Modified By M Register

Modify(I7-0,M7-0); {DAG1} Modify(I15-8,M15-8); {DAG2}

Table 4-8. Update (Modify) I Register, Modified By 32-Bit Data

Modify(I7-0,Data32); {DAG1} Modify(I15-8,Data32); {DAG2}

Table 4-9. Bit-Reverse and Update I Register, Modified By 32-Bit Data

Bitrev(I7-0,Data32); {DAG1} Bitrev(I15-8,Data32); {DAG2}

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DAG Instruction Summary

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5 MEMORY

The ADSP-21161 processor contains a large, dual-ported internal memory for single-cycle, simultaneous, independent accesses by the core processor and I/O processor. The dual-ported memory in combination with three separate on-chip buses allow two data transfers from the core and one transfer from the I/O processor in a single cycle. Using the IO bus, the I/O processor provides data transfers between internal memory and the processors communication ports (link ports, serial ports, and external port) without hindering the processor cores access to memory. This chapter describes the processors memory and how to use it. The processor provides access to external memory through the processors external port. For information on connecting and timing accesses to external memory, see External Memory Interface on page 7-3. The processor contains one megabit of on-chip SRAM, organized as two blocks of 0.5 Mbits. Each block can be configured for different combinations of code and data storage. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. The memory can be configured in each block as a maximum of 16K words of 32-bit data, 8K words of 64-bit data, 32K words of 16-bit data, 10.67K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 0.5 Mbit. This gives a total for the complete internal memory: a maximum of 32K words of 32-bit data, 16K words of 64-bit data, 64K words of 16-bit data, and 21K words of 48-bit instructions (or 40-bit data). The processor features a 16-bit floating-point storage format that effectively doubles the amount of data that may be stored on-chip. A single instruction converts the format from 32-bit floating-point to 16-bit floating-point.

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Internal Memory

While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus, (typically block 1) for transfers, and the other block (typically block 0) stores instructions and data using the PM bus. Using the DM bus and PM bus with one dedicated to each memory block assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.

Internal Memory
The ADSP-21161 has 2 MBits of internal memory space; 1 MBit is addressable. The 1 MBit of memory is divided into two 0.5 MBit blocks: Block 0 and Block 1. The additional 1MBit of the memory space is reserved on the ADSP-21161. Table 5-1 shows the maximum number of data or instruction words that can fit in each 0.5 MBit internal memory block. Table 5-1. Words Per 0.5 MBit Internal Memory Block
Word Type Instruction Long Word Data Extended Precision Normal Word Data Normal Word Data Short Word Data Bits Per Word 48-bits 64-bits 40-bits 32-bits 16-bits Maximum Number of Words Per 0.5 MBit block 10.67K Words 8K Words 10.67K Words 16K Words 32K Words

External Memory
While the processors internal memory is divided into blocks, the processors external memory spaces are divided into banks. The internal memory blocks and the external memory spaces may be addressed by either data 5-2 ADSP-21161 SHARC Processor Hardware Reference

Memory

address generator. External memory banks are fixed sizes that can be configured for various waitstate and access configurations. For more information, see External Memory on page 5-22. There are 254 Mwords of external memory space that the processor can address. External memory connects to the processors external port, which extends the processors 24-bit address and 32-bit data buses off the processor. The processor can make 8, 16, 32, or 48-bit accesses to external memory for instructions and 8,16, or 32-bit accesses for data. Table 5-2 shows the access types and words for processor external memory accesses. The processors DMA controller automatically packs external data into the appropriate word width during data transfer. The external data bus can be expanded to 48-bits if the link ports are disabled and the corresponding full width instruction packing mode (IPACK) is enabled in the SYSCON register. Ensure that link ports are disabled when executing code from external 48-bit memory. For more information, see Executing Instructions From External Memory on page 5-101. Table 5-2. Internal-to-External Memory Word Transfers1
Word Type Packed Instruction Normal Word Data Short Word Data 1 Transfer Type 32, 16, or 8- to 48-bit packing 32-bit word in 32-bit transfer Not supported

For external port word alignment, see Figure 7-1 on page 7-2.

The total addressable space for the fixed external memory bank sizes depends on whether SDRAM or Non-SDRAM (for example, SRAM, SBSRAM) is used. Each external memory bank for SDRAM can address 64M words. For Non-SDRAM memory, each bank can address up to

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Processor Architecture

16M words. The remaining 48M words are reserved. These reserved addresses for non-SDRAM accesses are aliased to the first 16M spaces within the bank. The total external memory available is given as follows: 3*(16M) + 14M = 62M (Non- SDRAM banks) 3*(64M) + 62M = 254M (SDRAM banks) Banks 1, 2 and 3 have the same amount of external memory (16M for Non-SDRAM and 64M for SDRAM), while bank 0 is smaller (14M for Non-SDRAM and 62M for SDRAM). The external memory address bus is 24-bits wide with four additional bank select MSx lines. For more information on the external memory, see the section External Memory on page 5-22.

Processor Architecture
Most microprocessors use a single address and single data bus for memory access. This type of memory architecture is called Von Neumann architecture. But, DSPs require greater data throughput than Von Neumann architecture provides, so many DSPs use memory architectures that have separate data and address buses for program and data storage. These two sets of buses let the processor retrieve a data word and an instruction simultaneously. This type of memory architecture is called Harvard architecture. SHARC DSPs go a step further by using a Super Harvard architecture. This four bus architecture has two address buses and two data buses, but provides a single, unified address space for program and data storage. While the Data Memory (DM) bus only carries data, the Program Memory (PM) bus handles instructions and data, allowing dual-data accesses.

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Memory

Processor core and I/O processor accesses to internal memory are completely independent and transparent to one another. Each block of memory can be accessed by the processor core and I/O processor in every cycleno extra cycles are incurred if the processor core and the I/O processor access the same block. A memory access conflict can occur when the processor core attempts two accesses to the same internal memory block in the same cycle. When this conflict, known as block conflict occurs, an extra cycle is incurred. The DM bus access completes first and the PM bus access completes in the following (extra) cycle. During a single-cycle, dual-data access, the processor core uses the independent PM and DM buses to simultaneously access data from both memory blocks. Though dual-data accesses provide greater data throughput, it is important to note some limitations on how programs may use them. The limitations on single-cycle, dual-data accesses are: The two pieces of data must come from different memory blocks. If the core accesses two words from the same memory block over the same bus in a single instruction, an extra cycle is needed. The data access execution may not conflict with an instruction fetch operation. The PM data bus tries to fetch an instruction in every cycle. If a data fetch is also attempted over the PM bus, an extra cycle may be required depending on the cache. If the cache contains the conflicting instruction, the data access completes in a single-cycle and the sequencer uses the cached instruction. If the conflicting instruction is not in the cache, an extra cycle is needed to complete the data access and cache the conflicting instruction. For more information, see Instruction Cache on page 3-8. For more information on how the buses access memory blocks, see Internal Memory on page 5-16.

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Off-Chip Memory and Peripherals Interface

Off-Chip Memory and Peripherals Interface

The ADSP-21161 processors external port provides the processors interface to off-chip memory and peripherals. Figure 5-9 on page 5-23 shows the external memory of ADSP-21161. The 62 Mword off-chip address space (254 Mword if all SDRAM) is included in the ADSP-21161s unified address space. The separate on-chip buses-for PM addresses, PM data, DM addresses, DM data, I/O addresses, and I/O data-are multiplexed at the external port to create an external system bus with a single 24-bit address bus and a single 32-bit data bus. Every access to external memory is based on an address that fetches a 32-bit word. When fetching instructions from external 32-bit memory, the program sequencer accesses two 32-bit data locations, four 16-bit locations or eight 8-bit locations. Unused link port lines can also be used as additional data lines DATA15-0, allowing single cycle execution of 48-bit instructions from external memory at up to 100 MHz. The external port supports asynchronous, synchronous, and synchronous burst accesses. ZBT synchronous burst SRAM can be interfaced gluelessly. However, the zero bus turnaround feature is not supported by this processor; only the bursting protocol is supported. The ADSP-21161 processor also can interface gluelessly to SDRAM. Addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. The ADSP-21161 processor provides programmable memory wait states and external memory acknowledge controls to allow interfacing to memory and peripherals with variable access, hold, and disable time requirements. Efficient memory usage relies on how the program and data are arranged in memory and varies how the program accesses the data. For more information, see Arranging Data in Memory on page 5-100.

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Memory

Buses
As shown in Figure 5-1 on page 5-9, the processor has three sets of internal buses connected to its dual-ported memory, the Program Memory (PM) bus, Data Memory (DM) bus, and I/O Processor (IO) bus. The PM bus and DM bus share one memory port and the IO bus connects to the other port. Memory accesses from the processors core (computational units, data address generators, or program sequencer) use the PM or DM buses, while the I/O processor uses the IO bus for memory accesses. The processor cores PM bus and DM bus and I/O processors External Port (EP) bus can try to access multiprocessor memory space or external memory space in the same cycle. The processor has a two level arbitration system to handle this conflicting access. Arbitration stems from a priority convention and the state of the SYSCON registers EBPRx bits. When arbitrating between the processor core buses, the DM bus always has priority over the PM bus. Arbitration between the winning core bus and I/O processor EP bus depends on the priority set with the EBPRx bits. For more information on setting this priority, see External Bus Priority on page 5-39.

Internal Address and Data Buses

Figure 5-1 shows that the PM buses, DM buses, and I/O processor have access to the external bus (pins DATA47-16, ADDR23-0) through the processors external port. The external port provides access to system (off-processor) memory and peripherals. This port also lets the processor access the IOP register space of other DSPs when connected in a multiprocessing system.

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Buses

Almost without exception, the processors three buses can access all memory spaces, supporting all data sizes. There are three restrictions on the access of buses to memory. The limitations on the PM, DM, and IO buses are as follows: The PM, DM, and IO buses make Normal Word addressing accesses to multiprocessor or external memory. These buses can make 40/48 bit data transfers by configuring the link data pins as additional data pins for external accesses. For more information, see Multiprocessor Memory on page 5-19. The IO bus may not access the I/O processors memory mapped registers. For more information, see I/O Processor on page 6-1. The IO bus may not use short word addressing for DMA operation. Addresses for the PM and DM buses come from the processors program sequencer and Data Address Generators (DAGs). The program sequencer generates 24-bit program memory addresses while DAGs supply 32-bit addresses for locations throughout the processors memory spaces. The DAGs supply addresses for data reads and writes on both the PM and DM address buses, while the program sequencer uses only the PM address bus for sequencing execution. Each DAG is associated with a particular data bus. DAG1 supplies addresses over the DM bus and DAG2 supplies addresses over the PM bus. For more information on address generation, see Program Sequencer on page 3-1 or Data Address Generator on page 4-1. Because the processors internal memory is arranged in four 16-bit wide by 8K high columns, memory is addressable in widths that are multiples of columns up to 64 bits: 1 column = 16-bit words, 2 columns = 32-bit words, 3 columns = 48- or 40-bit words, and 4 columns = 64-bit words. For more information on the how the processor works with memory words, see Memory Organization and Word Size on page 5-25.

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Memory

INTERNAL (DSP) MEMORY

DATA DATA BLOCK 0 (NORMAL WORD 0X40000 - 0X43FFF) ADDRESS

EXTERNAL (SYSTEM) MEMORY

ADDRESS

BLOCK 1 (NORMAL WORD 0X50000 - 0X53FFF) ADDRESS DATA ADDRESS DATA

BANK 0 (STARTING AT NORMAL WORD 0X200000) ADDRESS 24 ANY TWO PATHS SIMULTANEOUSLY ADDRESSES AND DATA FOLLOW PARALLEL PATHS EXTERNAL PORT DATA 32

PM ADDRESS BUS PM DATA BUS 18 64 32 64 64 PX BUS EXCHANGE REGISTER 64 DM ADDRESS BUS 32 64 32 64

DM DATA BUS

IO ADDRESS BUS

IO ADDRESS IO DATA

I/O PROCESSOR

EP EP ADDRESS DATA

IO DATA BUS

Figure 5-1. ADSP-21161 Memory and Internal Buses Block Diagram

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Buses

The PM and DM data buses are 64 bits wide. Both data buses can handle long word (64-bit), normal word (32-bit), extended-precision normal word (40-bit), and short word (16-bit) data, but only the PM data bus carries Instruction words (48-bit).

Internal Data Bus Exchange

The data buses let programs transfer the contents of any register in the processor to any other register or to any internal memory location in a single cycle. As shown in Figure 5-1 on page 5-2, the PM Bus Exchange (PX) register permits data to flow between the PM and DM data buses. The PX register can work as one 64-bit register or as two 32-bit registers (PX1 and PX2). The alignment of PX1 and PX2 within PX appears in Figure 5-2.
Instruction Examples PX = DM(0x80000)(LW); PX = DM(0x40000);

Combined PX Register 63 32 31 0

PX2 31 0 31

PX1 0

Figure 5-2. PM Bus Exchange (PX, PX1, and PX2) Registers The PX1, PX2, and the combined PX register are Universal registers (UREG) that are accessible for register-to-register or memory-to-register transfers.

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Instruction Examples R3 = PX; Register File Transfer 40 bits 39 0 39 R3 = PX1; or R3 = PX2; Register File Transfer 32 bits 0x0 8 7 0

40 bits 63 PX2 Combined PX

0x0 0 24 23 PX1 31

32 bits

0
PX1 or PX2

Figure 5-3. PX, PX1, and PX2 Register-to-Register Transfers register-to-register transfers with data registers are either 40-bit transfers for the combined PX or 32-bit transfers for PX1 or PX2. Figure 5-3 shows the bit alignment and gives an example of instructions for register-to-register transfers.
PX

Figure 5-3 shows that during a transfer between PX1 or PX2 and a data register (DREG), the bus transfers the upper 32 bits of the register file and zero fills the eight LSBs. During a transfer between the combined PX register and a register file, the bus transfers the upper 40 bits of PX and zero fills the lower 24 bits.

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Buses

register-to- internal memory transfers over the DM or PM data bus are either 48-bit for the combined PX or 32-bit transfers (on bits 31-0 of the bus) for PX1 or PX2. Figure 5-4 shows these transfers.
PX Instruction Examples PX = DM (0xC0000) (LW); DM and PM Data Bus Transfer (not LW) 48 bits 63 31 0x0 8 7 0 63 PM(I7,M7) = PX1; DM or PM Data Bus Transfer 0x0 31 32 bits 0

48 bits 63 PX2 Combined PX 31 PX1

0x0 8 7 0 31

32 bits 0 PX1 or PX2

Figure 5-4. PX, PX1, PX2 Register-to-Memory Transfers on DM (LW) or PM (LW) Data Bus Figure 5-4 shows that during a transfer between PX1 or PX2 and internal memory, the bus transfers the lower 32 bits of the register. During a transfer between the combined PX register and internal memory, the bus transfers the upper 48 bits of PX and zero fills the lower 8 bits. The status of the memory blocks Internal Memory Data Width (IMDWx) setting does not effect this default transfer size for PX to internal memory. Figure 5-5 shows a PX register-to-external memory transfer. The PX register transfers the upper 32 bits of the PM data bus into PX1 and the lower 16 bits to PX2, zero filling the remaining 16 bits.

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Memory

Instruction Example PX = PM (0xB8000)(LW); DM (LW) or PM (LW) Data Bus Transfer 64 bits 63 31 0

64 bits 63 31 Combined PX 0

Figure 5-5. PX Register-to-External Memory Transfers Since there are 32 DATA pins on the ADSP-21161 processor, 40/48 bit data transfers using register to register transfers are not directly supported. To accomplish 40/48 bit data transfers with the PX register, you must configure the link data pins as additional data pins for external accesses. Full width instruction mode (IPACK) must be enabled in the SYSCON register. The 16 link data pins are configured as DATA pins and the processor fetches the upper 32 bits of instruction on 32 DATA pins and lower 16 bits of instruction on the link data pins. To transfer both 48-bit instructions and 40-bit double precision data to a register, you must swap the PX1 and PX2 registers. See the following code examples:

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Buses

Example 1: To transfer 48-bits from external memory to internal memory, use the following code:
PX = DM(EXT_MEMORY_LOC); R0 = PX1; PX1 = PX2; PX2 = R0; DM(INT_MEMORY_LOC) = PX;

Example 2: To transfer a 40-bit data from external memory to a register, use the following code:
PX = DM(EXT_MEMORY_LOC); R0 = PX1; PX1 = PX2; PX2 = R0; R1 = PX;

All transfers between the PX register and the I/O processor LBUFx registers are 48-bit transfers (most significant 48-bits of PX). All transfers between the PX register (or any other internal register/memory) and any I/O processor register (other than the EPBx or LBUFx) are 32-bit transfers (least significant 32-bits of PX). All transfers between the PX register and data registers (R0-R15 or S0-S15) are 40-bit transfers. The most significant 40-bits are transferred as shown in Figure 5-3 on page 5-11. Figure 5-6 shows the transfer size between PX and internal memory over the PM or DM data bus when using the long word (LW) option.

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Memory

Instruction Example PX = PM (0x40200)LW;

DM (LW) or PM (LW) Data Bus Transfer 64-bits 63 31 0

64-bits 63 31 Combined PX 0

Figure 5-6. PX Register-to-Memory Transfers on PM Data Bus The LW notation in Figure 5-6 draws attention to an important feature of PX register-to-internal memory transfers over the PM or DM data bus for the combined PX register. PX transfers to memory are 48-bit (3-column) transfers on bits 0-31 of the PM or DM data bus, unless forced to be 64-bit (4-column) transfers with the LW (Long Word) mnemonic. There is no implicit move when the combined PX register is used in SIMD mode. For example, in SIMD mode, the following moves could occur:
PX1 = R0; PX = R0; /* R0 32-bit explicit move to PX1, and R1 32-bit implicit move to PX2 */ /* R0 40-bit explicit move to PX, but no implicit move for R1 */

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ADSP-21161 Memory Map

The ADSP-21161s memory map appears in Figure 5-7 and has three memory spaces: internal memory space, multiprocessor memory space, and external memory space. These spaces have the following definitions: Internal memory space. This space ranges from address 0x0000 0000 through 0x0005 3FFF (Normal word). Internal memory space refers to the processors on-chip SRAM and memory mapped registers. Multiprocessor memory space. This space ranges from address 0x0010 0000 through 0x001F FFFF (Normal word). Multiprocessor memory space refers to the internal memory space of other DSPs that are connected in a multiprocessor system. External memory space. This space ranges from address 0x0200 0000 to 0x0CFF FFFF for Non-SDRAM and 0x0020 0000 through 0x0FFF FFFF (Normal word) for SDRAM. External memory space refers to the off-chip memory or memory mapped peripherals that are attached to the processors external address (ADDR23-0) and data (DATA47-16) buses.

Internal Memory
The ADSP-21161s internal memory space appears in Figure 5-7. This memory space has four address regions. I/O processor memory mapped registers. This region ranges from address 0x0000 0000 through 0x0000 01FF (Normal Word). Reserved memory. This region ranges from address 0x0000 0200 through 0x0001 FFFF. These addresses are not accessible.

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LONG WORD (64-BIT) 0X0000 0000 0X0000 01FF

I/O PROCESSOR REGISTERS

NORMAL WORD (32-BIT)

EXT. PREC. NORMAL WORD (40-BIT) OR INSTRUCTION WORD (48-BIT)

SHORT WORD (16-BIT)

RESERVED (I/O)

EACH OF THESE ADDRESSING TYPES ADDRESS THE SAME PHYSICAL MEMORY BUT USE DIFFERENT WORD WIDTHS.

0X0002 0000

0X0004 0000

0X0004 0000

0X0008 0000

BLOCK 0

0X0002 1FFF 0X0002 8000

0X0004 3FFF 0X0005 0000

0X0004 2AA9 0X0005 0000

0X0008 7FFF 0X000A 0000

BLOCK 1

0X0002 9FFF

0X0005 3FFF

0X0005 2AA9

0X000A 7FFF

Figure 5-7. ADSP-21161 Internal Memory Space

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Block 0 memory. This region, typically PM, ranges from address 0x0004 0000 through 0x0004 3FFF (Normal Word). DAG2 generates PM data addresses. Block 1 memory. This region, typically DM, ranges from address 0x0005 0000 through 0x0005 3FFF (Normal Word). DAG1 generates DM data addresses. The I/O processors memory-mapped registers control the system configuration of the processor and I/O operations. For more information, see I/O Processor on page 6-1. These registers occupy consecutive 32-bit locations in this region. If a program uses long word addressing (forced with the LW mnemonic) to accesses this region, the access is only to the addressed 32-bit register, rather than accessing two adjacent I/O processor registers. The register contents are transferred on bits 31-0 of the data bus. There are a couple of exceptions to this one-at-a-time I/O processor register access rule: Long word accesses to external port buffer (EPBx) or link port buffer (LBUFx) locations using the PX register access two adjacent 32-bit I/O registers. Long word accesses to the external port data buffer locations (EPBx) in SIMD mode access two adjacent 32-bit I/O registers. As shown in Figure 5-7 on page 5-17, the processor can address memory in the Block 0 and Block 1 using long word, normal word, or short word addressing. The processor interprets the addressing mode from the address range for the access. Though there are multiple addressing modes for each memory region, these different modes are addressing the same physical memory. For example, the long word address 0x0002 0000 corresponds to the same locations as normal word addresses 0x0004 0000 and 0x0004 0001. This also corresponds to the same locations as short word addresses 0x0008 0000, 0x0008 0001, 0x0008 0002, and 0x0008 0003.

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Figure 5-7 on page 5-17 also shows that there are gaps in the processors memory map when using normal word addressing for 48-bit (instruction word) or 40-bit (extended-precision normal word) accesses. These gaps of missing addresses stem from the arrangement of this 3-column data in memory. For more information, see Memory Organization and Word Size on page 5-25.

Multiprocessor Memory
The ADSP-21161s multiprocessor memory space appears in Figure 5-8. This memory space has seven address regions that correspond to the IOP register space of the DSPs in a multiprocessing system. Each of the processors in such a system has a processor ID, which is set with the processors ID2-0 pins. The address regions by processor ID are: Internal memory with ID=001. This region ranges from address 0x0010 0000 through 0x0011 FFFF. Internal memory with ID=010. This region ranges from address 0x0012 0000 through 0x0013 FFFF. Internal memory with ID=011. This region ranges from address 0x0014 0000 through 0x0015 FFFF. Internal memory with ID=100. This region ranges from address 0x0016 0000 through 0x0017 FFFF. Internal memory with ID=101. This region ranges from address 0x0018 0000 through 0x0019 FFFF. Internal memory with ID=110. This region ranges from address 0x001A 0000 through 0x001B FFFF.

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0x0000 0000 INTERNAL MEMORY SPACE IOP Registers Long Word Addressing 0x0004 0000 Normal Word Addressing 0x0008 0000 Short Word Addressing 0x0010 0000 IOP Space of ADSP-21161 with ID=001 BANK 1 0x0012 0000 IOP Space of ADSP-21161 with ID=010 0x0014 0000 IOP Space of ADSP-21161 with ID=011 MULTIPROCESSOR MEMORY SPACE 0x0016 0000 IOP Space of ADSP-21161 with ID=100 0x0018 0000 IOP Space of ADSP-21161 with ID=101 0x001A 0000 IOP Space of ADSP-21161 with ID=110 0x001C 0000 Reserved 0x001F FFFF Normal Word Addressing : 32-bit Data Words Short Word Addressing : 16-bit Data Words BANK 2 EXTERNAL MEMORY SPACE BANK 0 0x0002 0000

0x0020 0000

MS 0

0x0400 0000

MS 1

0x0800 0000

MS 2

0x0C00 0000

BANK 3

MS

0x0FFF FFFF

Figure 5-8. Multiprocessor Memory Map

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It is important to note that programs may only use normal word addressing in multiprocessor memory space. Long or short word writes may corrupt valid data, and long or short word reads return invalid data. The address range of the access determines which processors internal memory is the multiprocessor memory access source or destination. Instead of using its own IOP register address range, a processor can access its IOP space through the corresponding address range in multiprocessor memory space. In this case, the processor reads or writes to its own IOP registers and does not make an access on the external system bus. Note that such self-accesses through multiprocessor memory space may only be accomplished with processor-core-generated addresses, not I/O processor-generated addresses. For more information on memory accesses in multiprocessor systems, see External Port on page 7-1. Table 5-3 shows how the processor decodes and routes memory addresses over the DM and PM buses. Table 5-3. Address Decoding For Memory Accesses
Address Bits1 ADDR31-28 ADDR27-24 Field NA V Description Reserved Virtual address. Drives MS3-0 as follows: 00 = Depends on E, S and M bits; address corresponds to local processors internal or external memory bank 0 01 = External memory bank 1, local processor 10 = External memory bank 2, local processor 11 = External memory bank 3, local processor Memory address. 00000[00] = Address in local or remote processors internal memory space. xxxxx[xx] = Based on V bits; address in one of local processors four external memory banks.

ADDR23-21

E2

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Table 5-3. Address Decoding For Memory Accesses (Contd)

Address Bits1 ADDR20 Field M
2

Description Multiprocessor memory. If this bit is 1, the address is in multiprocessor memory space. If this bit is 0, the address is in IOP register space. IOP MMS accesses. Depends on M bit. When bit 20 is set to 1, bits 19:17 indicate the following: 000 = Address is in IOP space of processor with ID1 001 = Address is in IOP space of processor with ID2 010 = Address is in IOP space of processor with ID3 100 = Address is in IOP space of processor with ID4 011 = Address is in IOP space of processor with ID5 101 = Address is in IOP space of processor with ID6 Internal memory and IOP register space.

ADDR19-17

S2

ADDR16-0 1 2

NA

Setup and hold times for these address lines are specified in the processor Data Sheet. For a description of these address fields, see Multiprocessor Memory on page 5-19.

External Memory
The ADSP-21161s external memory space appears in Figure 5-9. The processor accesses external memory space through the external port, which multiplexes the processor cores PM and DM buses and the I/O processors EP bus. To address this space, the processors DAG1, DAG2, and I/O processor generate 32-bit addresses over the DM, PM, and EP address buses, allowing the processor to access to the complete 254 Mword memory map. The program sequencer only generates 24-bit addresses over the PM bus, limiting sequencing to the low 62 Mwords (for SDRAM) or low 14 Mwords (for SRAM) of the memory map. The external memory space has four banks (bank 0-3). The processor controls access to the banked regions with memory select lines (MS3-0) in addition to the memory address. Each region of external memory may be configured for access modes and waitstates. For more information on con-

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figuring external memory banks, see Setting Data Access Modes on page 5-32. For more information on accessing external memory, see External Port on page 7-1. The external memory space can also accommodate an optional boot memory EPROM or FLASH. For more information, see Using Boot Memory on page 5-35.
ALWAYS ADDRESSED AS NORMAL WORD
0X0020 0000

BANK 0
0X00FF FFFF ( NON-SDRAM ) 0X03FF FFFF ( SDRAM ) 0X0400 0000

MS0

BANK 1
0X04FF FFFF ( NON-SDRAM ) 0X07FF FFFF ( SDRAM ) 0X0800 0000

MS1

BMS

EPROM (BOOT) MEMORY BANK 2

MS2

0X08FF FFFF ( NON-SDRAM ) 0X0BFF FFFF ( SDRAM ) 0X0C00 0000

BANK 4

MS3

0X0CFF FFFF ( NON-SDRAM ) 0X0FFF FFFF ( SDRAM )

EXTERNAL MEMORY

Figure 5-9. ADSP-21161 External Memory Space

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Shadow Write FIFO

Because the processors internal memory operates at high speeds, writes to the memory do not go directly into the memory array, but rather to a two-deep FIFO called the shadow write FIFO. This FIFO uses a non-read cycle (either a write cycle, or a cycle in which there is no access of internal memory) to load data from the FIFO into internal memory. When an internal memory write cycle occurs, the FIFO loads any data from a previous write into memory and accepts new data. FIFO operation is normally transparent, but there is one case in which programs need to intervene in the operation of the shadow write FIFO: mixing 48-bit and 32-bit word accesses to the same locations in memory. The shadow FIFO cannot differentiate between the mapping of 48-bit words and the mapping of 32-bit words. Examples of these mappings appear in Figure 5-10 through Figure 5-13. If a program writes a 48-bit word to memory and then tries to read the data with a 16-, 32- or 64-bit word access or writes a 16-, 32- or 64-bit word to memory and tries to read the data with a 48-bit access, the shadow FIFO does not intercept the read. It returns incorrect data. If a program must mix 48-bit or 40-bit accesses and 16-, 32-, or 64-bit accesses to the same locations, the program must ensure that the FIFO is flushed before attempting to read the data. The program flushes the FIFO by performing two dummy writes or executing two instructions that do not access the internal memory. These operations force the FIFO to automatically use the non-access cycles to push the write data.

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Memory Organization and Word Size

The processors internal memory is organized as four 16-bit wide by 8K high columns. These columns of memory are addressable as a variety of word sizes: 64-bit long word data (4-columns) 48-bit instruction words or 40-bit extended-precision normal word data (3-columns) 32-bit normal word data (2-columns) 16-bit short word data (1-column) Extended precision normal word data is only accessible if the IMDWx bit is set in the SYSCON register. It is left-justified within a three column location, using bits 47-8 of the location. Placing 32-Bit Words and 48-Bit Words When the processor core or I/O processor addresses memory, the word width of the access determines which columns within the memory are accessed. For instruction words (48-bit) or extended-precision normal word data (40-bit), the word width is 48 bits, and the processor accesses from the memorys 16-bit columns in groups of three. Because these sets of three column accesses are packed into a four column matrix, there are four rotations of the columns for storing 40/48-bit data. The 3-column word rotations within the 4-column matrix appear in Figure 5-10. For long word (64-bit), normal word (32-bit), and short word (16-bit) memory accesses, The processor selects from fixed columns in memory. No rotations of words within columns occur for these data types.

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Figure 5-7 on page 5-17 shows the memory ranges for each data size in the processors internal memory.

Rotation 3 Rotation 2 Addresses Rotation 1 0

Rotation 2 Rotation 1 Rotation 0

15 0 15 0 15 0 15 Column 0 Column 3 Column 2 Column 1

Figure 5-10. 48-bit Word Rotations Mixing 32-Bit and 48-Bit Words The processors memory organization lets programs freely place memory words of all sizes (see Memory Organization and Word Size on page 5-25) with few restrictions (see Restrictions on Mixing 32-Bit and 48-Bit Words on page 5-28). This memory organization also lets programs mix (place in adjacent addresses) words of all sizes. This section discusses how to mix odd (3-column) and even (4-column) data words in the processors memory. Transition boundaries between 48-bit (3-column) data and any other data size, can only occur at any 64-bit address boundary within either internal memory block. Depending on the ending address of the 48-bit words, there are zero, one, or two empty locations at the transition between the 48-bit (3-column) words and the 64-bit (4-column) words. These empty locations result from the column rotation for storing 48-bit words. The three possible transition arrangements appear in Figure 5-11, Figure 5-12, and Figure 5-13.

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Transitioning from 48-bit to 32-bit data with zero empty locations: (48-bit word top address) 32-bit word 3 32-bit word 1 48-bit word top 48-bit word top-1 Addresses 48-bit word top-2 0 32-bit word 2 32-bit word 0 48-bit word top-1 48-bit word top-2 48-bit word top-3

15 0 15 0 15 0 15 Column 0 Column 3 Column 2 Column 1

Figure 5-11. Mixed Instructions and Data With No Unused Locations

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Transitioning from 48-bit to 32-bit data with one empty locations: (48-bit word top address) 32-bit word 3 32-bit word 1 Empty 32-bit word 2 32-bit word 0 48-bit word top 48-bit word top-1 Addresses 48-bit word top-2 0 48-bit word top-2 48-bit word top-3

15 0 15 0 15 0 15 Column 0 Column 3 Column 2 Column 1

Figure 5-12. Mixed Instructions and Data With One Unused Location Restrictions on Mixing 32-Bit and 48-Bit Words There are some restrictions that stem from the memory column rotations for 3-column data (48- or 40-bit words) and relate to the way that 3-column data can mix with 4-column data (32-bit words) in memory. These restrictions apply to mixing 48- and 32-bit words, because the processor uses a normal word address to access both of these types of data even though 48-bit data maps onto 3-columns of memory and 32-bit data maps onto 2-columns of memory.

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Transitioning from 48-bit to 32-bit data with two empty locations: (48-bit word top address) 32-bit word 3 32-bit word 1 Empty 48-bit word top Addresses Empty 32-bit word 2 32-bit word 0 48-bit word top 48-bit word top-1 48-bit word top-2 0 48-bit word top-3

15 0 15 0 15 0 15 Column 0 Column 3 Column 2 Column 1

Figure 5-13. Mixed Instructions and Data With One Unused Location When a system has a range of 3-column (48-bit) words followed by a range of 2-column (32-bit) words, there is often a gap of empty 16-bit locations between the two address ranges. The size of the address gap varies with the ending address of the range of 48-bit words. Because the addresses within the gap alias to both 48- and 32-bit words, a 48-bit write into the gap corrupts 32-bit locations, and a 32-bit write into the gap corrupts 48-bit locations. The locations within the gap are only accessible with short word (16-bit) accesses.

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Calculating the starting address for 4-column data that minimizes the gap after 3-column data is a useful calculation for programs that are mixing 3and 4-column data. Given the last address of the 3-column (48-bit) data, the starting address of the 32-bit range that most efficiently uses memory can be determined by the equation shown in Listing 5-1: Listing 5-1. Starting Address m = B + 2 [(n MOD 10,922) TRUNC((n MOD 10,922) / 4)] where: n is the number of contiguous 48-bit words allocated in the internal memory block (n < 21845) B is the base normal word address of the internal memory block; if {0 < n < 10,922} then B = 0x40000 (Block 0) else B = 0x50000 (Block 1) m is the first 32-bit normal word address to use after the end of 48-bit words Example 1: Calculating a starting address for a 32-bit addresses The last valid address is 0x42694. The number of 48-bit words (n) is given as follows: n = 0x42694 - 0x40000+1= 0x2695 When you convert 0x2695 to decimal representation, the result is 9877. The base (B) Normal word address of the internal memory block is 0x40000 since the condition: 0 < 10922 is TRUE.

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The first 32-bit Normal word address to use after the end of the 48-bit words is given by: m = 0x40000 + 2 [(9877 MOD 10922)- TRUNC (9877 MOD 10922)/4] m = 0x40000 + 14816decimal Convert to a hexadecimal address: 14816decimal = 0x39E0 m = 0x40000 + 0x39E0 = 0x439E0 The first valid starting 32-bit address is 0x439E0. The starting address must begin on an even address. 48-Bit Word Allocation Another useful calculation for programs that are mixing 3- and 4-column data is to calculate the amount of 3-column data that minimizes the gap before starting 4-column data. Given the starting address of the 4-column (32-bit) data, the number of 48-bit words to allocate that most efficiently uses memory can be determined as shown in Listing 5-2: Listing 5-2. 48-bit Word Allocation m = TRUNC{(4/3)[(1/2)(m-b)]} + W where m is the first 32-bit normal word address after the end of 48-bit words (0x3FFFF < m < 0x44000 for block 1, 0x4FFFF < m < 0x54000 for block 2) B is the base normal word address of the internal memory block; if {0x3FFFF < m < 0x50000} then B = 0x40000 else B = 0x50000 (Block 1)

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W is the number of offset words; if {B = 0x50000} then W = 43,690 else W = 0 n is the number of contiguous 48-bit words the system should allocate in the internal memory block

Setting Data Access Modes

The SYSCON, MODE1, MODE2, and WAIT registers control the operating mode of the processors memory. Table A-18 on page A-60 lists all the bits in SYSCON, Table A-2 on page A-3 lists all the bits in MODE1, Table A-2 on page A-3 lists all the bits in MODE2, and Table A-20 on page A-66 lists all the bits in WAIT.

SYSCON Register Control Bits

Figure 5-14 shows the control bits for the SYSCON register. The following bits in the SYSCON register control memory access modes: Boot Select Override. SYSCON Bit 1 (BSO). This bit overrides normal usage of MSx chip select lines in favor of the BMS select line for access to boot memory instead of external memory (if 1) or allows normal access to external memory with the MSx chip select lines (if 0). Internal Interrupt Vector Table. SYSCON Bit 2 (IIVT). This bit forces placement of the interrupt vector table at address 0x0004 0000 regardless of booting mode (if 1) or allows placement of the interrupt vector table as selected by the booting mode (if 0). Internal Memory Block Data Width. SYSCON Bit 9 (IMDW0) and Bit 10 (IMDW1). These bits select the normal word data access size for internal memory Block 0 and Block1. A blocks normal word access size is fixed as 32-bit (2-column, IMDWx=0) or 40-bit (3-column, IMDWx=1).

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Instruction Packing Mode. SYSCON Bits 30 and 31 (IPACK1 and IPACK0). These bits select the external packing instruction execution as 8- to 48-bit, 16- to 48-bit, 32- to 48-bit or no pack mode. External Bus Priority. SYSCON Bits 18-17 (EBPRx). This bit field selects the priority for the I/O processors EP bus when both the core and the IOP attempt to access external memory.
SYSCON (0x0000)
IPACK
External Packed Instruction Execution Mode 00 = 32-to-48 packed instruction execution 01 = Full 48-bit instruction execution / No-Packing Mode 10 = 16 -to-48 packed instruction execution 11 = 8- to -48 packed instruction execution 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

External Bus Priority 00=even priority between core processor and IOP bus 01=core processor priority, 10= I/O processor priority

EBPR

BSO IMDW1
Internal Memory Block 1 Data Width 0=32 -bit data, 1=40 -bit data Internal Memory Block 0 Data Width 0=32 -bit data, 1=40 -bit data

Boot Select Override

IIVT

IMDW0

Internal Interrupt Vector Table (no boot mode)

Figure 5-14. Syscon Register Control Bits Only

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Mode 1 Register Control Bits

The following bits in the MODE1 register control memory access modes: Secondary Processor Element (PEy). MODE1 Bit 21 (PEYEN) enables computations in PEySIMD mode(if 1) or disables PEySISD mode(if 0). Broadcast Register Loads. Mode1 Bit 22 (BDCST9) and Bit 23 (BDCST1) enable broadcast register loads for memory transfers indexed with I1 (if BDCST1 = 1) or indexed with I9 (if BDCST9 =1).

Mode 2 Register Control Bits

The following bits in the MODE2 register control memory access modes: Illegal IOP Register Access Enable. MODE2 Bit 20 (IIRAE) enables detection of I/O processor register access (if 1) or disables detection (if 0). Unaligned 64-bit Memory Access Enable. MODE2 Bit 21 (U64MAE) enables detection of uneven address memory access (if 1) or disables detection (if 0).

Wait Register Control Bits

The following bits in the WAIT register control memory access modes: External Bank X Access Mode. WAIT Bits 1-0 (EB0AM), Bits 6-5 (EB1AM), Bits 11-10 (EB2AM), Bits 16-15 (EB3AM), and Bits 21-20 (RBAM). These bit fields select the access modes (synchronous, asynchronous, SDRAM, SBSRAM) for the external memory banks.

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External Bank X Waitstates. WAIT Bits 4-2 (EB0WS), Bits 9-7 (EB1WS), Bits 14-12 (EB2WS), Bits 19-17 (EB3WS) and Bits 24-22 (RBWS). These bit fields independently select the number of waitstates for each of the external memory banks. After reset, the default number of waitstates is seven.

Using Boot Memory

As shown in Figure 5-9 on page 5-23, the processor supports an external boot EPROM mapped to external memory and selected with the BMS pin. The boot EPROM provides one of the methods for automatically loading a program in to the internal memory of the processor after power-up or after a software reset. This process is called booting. For information on boot options and the booting process, see the following sections: Bootloading Through The External Port on page 6-70 Bootloading Through The Link Port on page 6-88 Bootloading Through the SPI Port on page 6-113 For information on systems with a boot EPROM, see Booting Single and Multiple Processors on page 13-71. Reading From Boot Memory When the processor boots from an EPROM, the processors I/O processor is hard-wired to load 256 instructions automatically from EPROM (via DMA). Once the initial 256-word DMA is complete, the processor typically needs to maintain access to boot memory. The processor does this by setting the Boot Select Override (BSO) bit in the SYSCON register. Setting (=1) the BSO bit overrides the external memory selects and asserts the processors BMS pin for an external memory DMA transfer. For accessing boot memory, the program first sets the BSO bit in SYSCON then sets up an external port DMA channel to read the EPROMs contents. The pro-

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gram must unmask the DMA channels interrupt in the IMASK register; if using external port DMA buffer zero (EP0I), the program could enable this interrupt by setting the EPOI bit to 1 in the IMASK register. For more information on external port DMA, see External Port DMA on page 6-29. While a program may use any external port DMA channel for accessing boot memory, it is important to note that only DMA channel 10 has a fixed 8- to 48-bit packing mode for boot memory reads. By using DMA channel 10 to complete initial program loading, a program can take advantage of this special packing mode. When a program sets BSO, the processor ignores the DMA channels packing mode (PMODE) bits for DMA channel 10 and forces 8- to 48-bit packing for reads. This 8-bit packing mode is used on DMA channel 10 during EPROM booting or on DMA reads when BSO is set. While one of the external port DMA channels is making a DMA access to boot memory with the BSO bit set, none of the other three channels may make a DMA access to external (not boot) memory. Only external port DMA transfers assert BMS when BSO is set; processor core accesses to external memory always use the MSx pins. Because the processor core only accesses external (not boot) memory, programs can access external memory in between DMA accesses to boot memory. Writing to Boot Memory In systems using write-able EEPROM or FLASH memory for boot memory, programs can write new data to the processors boot memory using the boot select override (BSO) pin. As described in Reading From Boot Memory on page 5-35, setting (=1) the BSO bit overrides the external memory selects and asserts the processors BMS pin for an external memory DMA transfer.

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To write to boot memory using the BMS signal, programs must use DMA channels 11, 12 or 13, but not DMA channel 10. With the BSO bit set, programs should only use DMA channel 10 for reads. When BSO is set, programs can use DMA channels 11-13 with any settings in channels the DMACx register, any packing mode, and any data or instruction.

Internal Interrupt Vector Table

The default location of the ADSP-21161s interrupt vector table depends on the processors booting mode. When the processor boots from an external source (EPROM, host port, SPI port or link port booting), the vector table starts at address 0x0004 0000 (normal word). When the processor is in no boot mode (runs from external memory location 0x0020 0000 without loading), the interrupt vector table starts at address 0x0020 0000. The Internal Interrupt Vector Table (IIVT) bit in the SYSCON register overrides the default placement of the vector table. If IIVT is set (=1), the interrupt table starts at address 0x0004 0000 (internal memory) regardless of the booting mode.

Internal Memory Data Width

The processors internal memory blocks use normal word addressing to access either single-precision 32-bit data or extended-precision 40-bit data. Programs select the data width independently for each internal memory block using the Internal Memory Data Width (IMDW0 and IMDW1) bits in the SYSCON register. If a blocks IMDWx bit is cleared (=0), normal word addressed accesses to the block access 32-bit data. If a blocks IMDWx bit is set (=1), normal word addressed accesses to the block access 40-bit extended-precision data. Reading or writing 40-bit data using a normal word access to a memory block whose IMDWx bit is cleared (=0) has the following results.

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If a program tries to write 40-bit data (for example, a data register-to-memory transfer), the transfer truncates the lower 8-bits from the register; only writing 32 most significant bits. If a program tries to read 40-bit data (for example, a memory-to-data register transfer), the transfer zero-fills the lower 8 bits of the register; only reading the 32 most significant bits. The Program Memory Bus Exchange (PX) register is the only exception to these transfer rulesall loads/stores of the PX register are performed as 48-bit accesses unless forced to 64-bit access with the LW mnemonic. If any 40-bit data must be stored in a memory block configured for 32-bit words, the program should use the PX register to access the 40-bit data in 48-bit words. Programs should take care not to corrupt any 32-bit data with this type of access. For more information, see Restrictions on Mixing 32-Bit and 48-Bit Words on page 5-28. The Long word (LW) mnemonic only effects normal word address accesses and overrides all other factors (SIMD, IMDWx).

Memory Bank Size

The processors external memory space has four banks of equal, fixed size. Mapping peripherals into different banks lets systems accommodate I/O devices with different timing requirements, because the banked regions have associated waitstate and access mode settings. This processor permits a glueless interface to multiple devices because each bank has a independent memory select signal associated with it. For more information, see External Bank X Access Mode on page 5-42 and External Bank X Waitstates on page 5-45. As shown in Figure 5-9 on page 5-23, bank 0 starts at address 0x0020 0000 in external memory, and the banks 1, 2, and 3 regions follow. Whenever the processor generates an address that is located within

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one of the four banks, the processor asserts the corresponding memory select line (MS3-0).The size of the memory banks is 3.67 Mwords (SRAM) or 15.67 Mwords (SDRAM).

External Bus Priority

The processors internal bus architecture lets the PM bus, DM bus, and IOP bus try to access multiprocessor memory space or external memory space in the same cycle. This contending access produces a conflict that the processor resolves with a two level arbitration policy. The processor cores DM bus always has priority over the PM bus. External Bus Priority (EBPRx) bits in the SYSCON register control the further arbitration between the winning core bus and the I/O processor. The EBPRx field assigns priority as follows: If EBPR is 00, priority rotates between core and I/O processor buses. Priority is evaluated and switched in each cycle in which the conflict exists. For example, if the IOP was transferring data to the external port and the core tried to read from the external memory four times consecutively, the core and IOP would take turns accessing external memory for eight cycles. If EBPR is 01, the winning core bus has priority over the I/O processor bus. If EBPR is 10, the I/O processor bus has priority over the winning core bus.

Secondary Processor Element (PEy)

When the PEYEN bit in the MODE1 register is set (=1), the processor is in Single-Instruction, Multiple-Data (SIMD) mode. In SIMD mode, many data access operations differ from the processors default Single-Instruction, Single-Data (SISD) mode. These differences relate to doubling the amount of data transferred for each data access.

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Accesses in SIMD mode transfer both an explicit (named) location and an implicit (un-named, complementary) location. The explicit transfers is a data transfers between the explicit register and the explicit address, and the implicit transfer is between the implicit register and the implicit address. For information on complementary (implicit) registers in SIMD mode accesses, see Secondary Processing Element (PEy) on page 2-37. For more information on complementary (implicit) memory locations in SIMD mode accesses, see Accessing Memory on page 5-46.

Broadcast Register Loads

The processors BDCST1 and BDCST9 bits in the MODE1 register control broadcast register loading. When broadcast loading is enabled, the processor writes to complementary registers or complementary register pairs in each processing element on writes that are indexed with DAG1 register I1 (if BDCST1 =1) or DAG2 register I9 (if BDCST9 =1). Broadcast load accesses are similar to SIMD mode accesses in that the processor transfers both an explicit (named) location and an implicit (un-named, complementary) location, but broadcast loading only influences writes to registers and write identical data to these registers. Broadcast mode is independent of SIMD mode. Table 5-4 shows examples of explicit and implicit effects of broadcast register loads to both processing elements. Note that broadcast loading only effects loads of data registers (register file); broadcast loading does not effect register stores or loads to other system registers. And, broadcast loads only work on register loads; broadcast loading cannot be used for memory writes. For more information on broadcast loading, see Accessing Memory on page 5-46.

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Table 5-4. Register Load Dual PE Broadcast Operation

Instruction (Explicit, PEx Operation)1 Rx = dm(i1,ma); Rx = pm(i9,mb); Rx = dm(i1,ma), Ry = pm(i9,mb); 1 (Implicit, PEy operation) Sx = dm(i1,ma); Sx = pm(i9,mb); Sx = dm(i1,ma), Sy = pm(i9,mb);

The post increment in the explicit operation is performed before the implicit instructions are executed.

Illegal I/O Processor Register Access

The processor monitors I/O processor register access when the Illegal I/O processor Register Access (IIRAE) bit in the MODE2 register is set (=1). If access to the IOP registers is detected, an Illegal Input Condition Detected (IICDI) interrupt occurs. The interrupt is enabled in the IMASK register in the following cases: A core access to an IOP register occurs. A host external port access to an IOP register occurs. The I/O processors DMA controller cannot generate the IICDI interrupt. For more information, see Mode Control 2 Register (MODE2) on page A-10.

Unaligned 64-Bit Memory Access

The processor monitors for unaligned 64-bit memory accesses if the Unaligned 64-bit Memory Accesses (U64MAE) bit in the MODE2 register (bit 21) is set (=1). An unaligned access is an odd numbered address normal word access that is forced to 64-bit with the LW mnemonic. When detected, this condition is an input that can cause an Illegal Input Condi-

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tion Detected (IICDI) interrupt if the interrupt is enabled in the IMASK register. For more information, see Mode Control 2 Register (MODE2) on page A-10. The following code example shows the access for even and odd addresses. When accessing an odd address, the sticky bit is set to indicate the unaligned access.
bit set mode2 U64MAE; bit access r0=0x11111111; r1=0x22222222; pm(0x4e800)=r0(lw); //even address in 32 bit, access is aligned pm(0x4e803)=r0(lw); //odd address in 32 bit, sticky bit is set //set testbit for align or unaligned 64

External Bank X Access Mode

The processor has four modes for accessing external memory space. The External Bank Access Mode (EBxAM) fields in the WAIT register select how the processor uses waitstates and the acknowledge (ACK) pin to access each external memory bank region. ACK has a 20 k internal pull-up resistor

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that is enabled during reset or on DSPs with ID2-0=00x. The external bank access modes appear in Table 5-5. The WAIT register bit descriptions appear in Figure 5-15. Table 5-5. External Bank Access Mode
EBxAM Field 00 External Bank Access Mode Asynchronous RD and WR strobes change before CLKOUTs edge. Accesses use the waitstate count setting from EBxWS AND require external acknowledge (ACK), allowing a de-asserted ACK to extend the access time. 01 Synchronous RD and WR strobes change on CLKOUTs edge. Accesses use the waitstate count setting from EBxWS (minimum EBxWS=001) AND require external acknowledge (ACK), allowing a de-asserted ACK to extend the read access time. Writes are 0-wait state. 10 Synchronous RD and WR strobes change on CLKOUTs edge. Accesses use the waitstate count setting from EBxWS (minimum EBxWS=001) AND require external acknowledge (ACK), allowing a de-asserted ACK to extend the read access time. Writes are 1-wait state. 11 Reserved

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WAIT (0x0002)

1 1

HIDMA
Handshake and Idle for DMA enable 0 =no idle cycle 1=adds an idle cycle after every handshake DMA DMAG asserted longer reduces bus contention for slower devices

EB3AM
External Bank 3 Access Mode

EB3WS
External Bank 3 waitstates

RBAM
ROM Boot Access Mode

RBWS
ROM Boot Waitstates

15 14 13 12 11 10 9 0 1 1 1 0 0 1

8 1

7 1

6 0

5 0

4 1

3 1

2 1

1 0

0 0

EB2WS
External Bank 2 waitstates

EB0AM
External Bank 0 Access Mode 00=Async, uses both internal waitstate& ext ACK 01=Sync (RD~ and WR~ change on CLKOUTsedge) min 2 cycle reads, 1 cycle writes (EP0WS=001) 10=Sync (RD~ and WR~ change on CLKOUTsedge) min 2 cycle reads, 2 cycles writes (EP0WS=001) 11= reserved External Bank 0 Waitstates 000= 0 waitstates , no hold time cycle 001=1 waitstate, no hold time cycle, minimum for sync 010=2 waitstates, hold time cycle 011=3 waitstates, hold time cycle 100=4 waitstates, hold time cycle 101=5 waitstates, hold time cycle 110=6 waitstates, hold time cycle 111=7 waitstates, hold time cycle (hold time cycles for Async Mode only)

EB2AM
External Bank 2 Access Mode

EB1WS
External Bank 1 waitstates

EB1AM
External Bank 1 Access Mode

EB0WS

Figure 5-15. WAIT Register

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External Bank X Waitstates

The processor applies waitstates to each external memory access depending on the banks external memory access mode (EBxAM). The External Bank Waitstate (EBxWS) field in the WAIT register sets the number of waitstates for each bank as shown in Table 5-6. Table 5-6 lists the hold time settings that EBxWS associates with external memory accesses. A hold time cycle is an inactive bus cycle that the processor inserts automatically at the end of a read or write, allowing a longer hold time for address and data. The address and data remain unchanged and are driven for one cycle after the processor deasserts the read or write strobes. Table 5-6. External Bank Waitstates
EBxWS 000 001 010 011 100 101 110 111 1 # of Waitstates 0 1 2 3 4 5 6 7 Hold Time Cycle?1 no no yes yes yes yes yes yes

Hold cycle applies to asynchronous mode only.

The processor applies hold time cycles regardless of the external bank access mode (EBxAM). For example, the asynchronous (ACK plus waitstate) mode could also have an associated hold time cycle.

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Using Memory Access Status

As described in Illegal I/O Processor Register Access on page 5-41 and Unaligned 64-Bit Memory Access on page 5-41, the processor can provide illegal access information for long word or I/O register accesses. When these conditions occur, the processor updates an illegal condition flag in a sticky status (STKYx) register. Either of these two conditions can also generate a maskable interrupt. Two ways to use illegal access information are: Interrupts. Enable interrupts and use an interrupt service routine to handle the illegal access condition immediately. This method is appropriate if it is important to handle all illegal accesses as they occur. STKYx registers. Sticky registers hold a value that can be checked for a specific condition at a later time. Use the Bit Tst instruction to examine illegal condition flags in the STKY register after an interrupt to determine which illegal access condition occurred.

Accessing Memory
The word width of the processor core accesses to internal memory include the following: 48-bit access for instruction words, extended-precision normal word (40-bit) data, and PX register 64-bit access for long word data, and normal word (32-bit) or PX register data with the LW mnemonic 32-bit access for normal word (32-bit) data 16-bit access for short word data

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The processor determines whether a normal word access is 32- or 40-bit from the internal memory blocks IMDWx setting. For more information, see Internal Memory Data Width on page 5-37. While mixed accesses of 48-bit words and 16-, 32-, or 64-bit words at the same address are not allowed, mixed read/writes of 16-, 32-, and 64-bit words to the same address are allowed. For more information, see Restrictions on Mixing 32-Bit and 48-Bit Words on page 5-28. The processors DM and PM buses support 24 combinations of register-to-memory data access options. The following factors influence the data access type: Size of words: short word, normal word, extended-precision normal word, or long word Number of words: single- or dual-data move Mode of processor: SISD, SIMD, or broadcast load

Access Word Size

The processors internal memory accommodates the following word sizes: 64-bit word data 48-bit instruction words 40-bit extended-precision normal word data 32-bit normal word data 16-bit short word data

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The processors external memory accommodates the following word sizes: 48-bit instruction words 40-bit extended-precision normal word data (accessed as 48-bit via PX) 32-bit normal word data Long Word (64-Bit) Accesses A program makes a long word (64-bit) access to internal memory, using an access to a long word address. Programs can also make a 64-bit access through normal word addressing with the LW mnemonic or through a PX register move with the LW mnemonic. Programs may not use long word addressing to access multiprocessor memory space or external memory. The address ranges for internal memory accesses appear in Figure 5-7 on page 5-17. Since the ADSP-21161 processor external port is 32 bits wide, the SIMD and long word accesses are not supported. When data is accessed using long word addressing, the data is always long word aligned on 64-bit boundaries in internal memory space. When data is accessed using normal word addressing and the LW mnemonic, the program should maintain this alignment by using an even normal word address (least significant bit of address =0). This register selection aligns the normal word address with a 64-bit boundary (long word address). All long word accesses load or store two consecutive 32-bit data values. The register file source or destination of a long word access is a set of two neighboring data registers in a processing element. In a forced long word access (uses the LW mnemonic), the even (normal word address) location moves to or from the explicit register in the neighbor-pair, and the odd

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(normal word address) location moves to or from the implicit register in the neighbor-pair. For example, the following long word moves could occur:
DM(0x40000) = R0 (LW); /* The data in R0 moves to location DM(0x40000), and the data in R1 moves to location DM(0x40001) */ R0 (LW) = DM(0x40003)(LW); /* The data at location DM(0x40002) moves to R0, and the data at location DM(0x40003) moves to R1 */

The example shows that R0 and R1 are a neighbor registers in the same processing element. Table 5-7 lists the other neighbor register assignments that apply to long word accesses. In un-forced long word accesses (accesses to LW memory space), the processor places the lower 32-bits of the long word in the named (explicit) register and places the upper 32-bits of the long word in the neighbor (implicit) register. Table 5-7. Neighbor Registers for Long Word Accesses
PEx neighbor registers r0 neighbors r1 r2 neighbors r3 r4 neighbors r5 r6 neighbors r7 r8 neighbors r9 r10 neighbors r11 r12 neighbors r13 r14 neighbors r15 PEy neighbor registers s0 neighbors s1 s2 neighbors s3 s4 neighbors s5 s6 neighbors s7 s8 neighbors s9 s10 neighbors s11 s12 neighbors s13 s14 neighbors s15

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Programs can monitor for unaligned 64-bit accesses by enabling the U64MAE bit. For more information, see Unaligned 64-Bit Memory Access on page 5-41. The Long word (LW) mnemonic only effects normal word address accesses and overrides all other factors (PEYEN, IMDWx). Instruction Word (48-Bit) and Extended-Precision Normal Word (40-Bit) Accesses The sequencer uses 48-bit memory accesses for instruction fetches. Program can make 48-bit accesses with PX register moves, which default to 48-bit. A program makes an extended-precision normal word (40-bit) access to internal memory using an access to a normal word address when that internal memory blocks IMDWx bit is set (=1) for 40-bit words. Programs may not use extended-precision normal word addressing to access multiprocessor memory space or external memory. The address ranges for internal memory accesses appear in Figure 5-7 on page 5-17. For more information on configuring memory for extended-precision normal word accesses, see Internal Memory Data Width on page 5-37. The processor transfers the 40-bit data to internal memory as a 48-bit value, zero-filling the least significant 8 bits on stores and truncating these 8 bits on loads. The register file source or destination of such an access is a single 40-bit data register. Normal Word (32-Bit) Accesses A program makes a normal word (32-bit) access to internal memory using an access to a normal word address when that internal memory blocks IMDWx bit is cleared (=0) for 32-bit words. Programs use normal word addressing to access all processor memory spaces: internal, multiprocessor, and external memory space. The address ranges for memory accesses appear in Figure 5-7 on page 5-17, and Figure 5-9 on page 5-23.

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The register file source or destination of a normal word access is a single 40-bit data register. The processor zero-fills the least significant 8 bits on loads and truncates these bits on stores. External memory space accesses using normal word addressing and the LW mnemonic perform a 32-bit accesses, not a 64-bit access. Short Word (16-Bit) Accesses A program makes a short word (16-bit) access to internal memory, using an access to a short word address. Programs may not use short word addressing to access multiprocessor memory space or external memory. The address ranges for internal memory accesses appear in Figure 5-7 on page 5-17. The register file source or destination of such an access is a single 40-bit data register. The processor zero-fills the least significant 8 bits on loads and truncates these bits on stores. Depending on the value of the SSE bit in the MODE1 system register, the processor loads the registers upper 16 bits by either: Zero-filling these bits if SSE=0 Sign-extending these bits if SSE=1

SISD, SIMD, and Broadcast Load Modes

These three processing element modes influence memory accesses. For a comparison of their effects, see the examples in Data Access Options on page 5-52. For more information on SISD and SIMD modes, see Secondary Processing Element (PEy) on page 2-37. Broadcast load mode is a hybrid between SISD and SIMD modes, transferring dual-data under special conditions. For examples of broadcast transfers, see Data Access Options on page 5-52. For more information on broadcast load mode, see Broadcast Register Loads on page 5-40.

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Single and Dual Data Accesses

The number of transfers that occur in a cycle influences the data access operation. As described on page 5-5, the processor supports single-cycle, dual-data accesses to and from internal memory for register-to-memory and memory-to-register transfers. Dual-data accesses occur over the PM and DM bus and act independent of SIMD/SISD. Though only available for transfers between memory and data registers, dual-data transfers are extremely useful because they double the data throughput over single-data transfers. Instruction Examples
R8 = DM (I4,M3), PM (I12,M13) = R0; R0 = DM (I5,M5); /* Dual access */ / * Single access */

For examples of data flow paths for single- and dual-data transfers, see Data Access Options on page 5-52.

Data Access Options

Table 5-8 on page 5-53 lists the processors possible memory transfer modes and provides a cross reference to examples of each memory access option that stems from the processors data access options. Table 5-8 shows the transfer modes that stem from the following data access options: The mode of the processor: SISD, SIMD, or Broadcast Load The size of access words: long, extended-precision normal word, normal word, or short word The number of transferred words: single- or dual-data Note that long and short word addressing may not target multiprocessor memory space or external memory space.

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Table 5-8. Memory Transfer Modes Cross Reference

Access Type Mode Address Space Long Word SISD mode SIMD mode B-cast Load Dual Data Access SISD mode SIMD mode B-cast Load LW page 5-76 LW page 5-76 LW Figure 5-38 LW page 5-78 LW page 5-80 LW Figure 5-35 Extended Precision EW page 5-70 EW page 5-70 EW Figure 5-36 EW page 5-72 EW page 5-74 EW Figure 5-37 Normal Word NW page 5-62 LW page 5-64 NW Figure 5-34 NW page 5-66 LW page 5-68 NW Figure 5-35 Short Word SW page 5-54 SWx2 page 5-56 SW Figure 5-32 SW page 5-58 SWx2 page 5-60 SW Figure 5-33

Single Data Access

Symbols:LW = 64-bit data value (two 32-bit values), EW = 40-bit data value (48-bit value), NW = 32-bit data value, SW = 16-bit data value, and SWx2 = two 16-bit data values.

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Short Word Addressing of Single Data in SISD Mode Figure 5-16 displays one possible SISD mode, single data, short word addressed access. For short word addressing, the processor treats the data buses as four 16-bit short word lanes. The 16-bit value for the short word access transfers using the least significant short word lane of the PM or DM data bus. The processor drives the other short word lanes of the data buses with zeros. In SISD mode, the instruction accesses PEx registers to transfer data from memory. This instruction accesses WORD X0 whose short word address has 00 for its least significant two bits of address. Other locations within this row have addresses with least significant two bits of 01, 10, or 11 and select WORD X1, WORD X2, or WORD X3 from memory respectively. The syntax targets register, RX, in PEx. The example would target a PEy register if using the syntax SX. The cross () in the PEx registers in Figure 5-16 indicates that the processor zero-fills or sign-extends the most significant 16 bits of the data register while loading the short word value into a 40-bit data register. This depends on the state of the SSE bit in the MODE1 system register. For SW transfers, the least significant 8 bits of the data register are always zero.

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BLOCK 0 (PM)

MEMORY

BLOCK 1 (DM)

ADDRESS

WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD Y3 WORD Y2 WORD Y1 WORD Y0
ADDRESS

WORD X11 WORD X10 WORD X9 WORD X8 WORD X7 WORD X6 WORD X5 WORD X4 WORD X3 WORD X2 WORD X1 WORD X0

NO ACCESS

SHORT WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48 0X0000

47-32 0X0000

31-16 0X0000

15-0 WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8

RX 7-0

0X0000 WORD X0 0X00 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0 39-24 23-8 SY 7-0 39-24 23-8 SX 7-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(SHORT WORD X0 ADDRESS); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SISD, SHORT WORD, SINGLE-DATA TRANSFERS ARE: UREG = PM(SHORT WORD ADDRESS); UREG = DM(SHORT WORD ADDRESS); PM(SHORT WORD ADDRESS) = UREG; DM(SHORT WORD ADDRESS) = UREG;

NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL DATA ACCESSES. DUAL DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-16. Short Word Addressing of Single Data in SISD Mode

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Short Word Addressing of Single Data in SIMD Mode Figure 5-17 displays one possible SIMD mode, single data, short word addressed access. For short word addressing, the processor treats the data buses as four 16-bit short word lanes. The explicitly addressed (named in the instruction) 16-bit value transfers using the least significant short word lane of the PM or DM data bus. The implicitly addressed (not named in the instruction, but inferred from the address in SIMD mode) short word value transfers using the 47-32 bit short word lane of the PM or DM data bus. The processor drives the other short word lanes of the PM or DM data buses with zeros. The instruction explicitly accesses the register, RX, and implicitly accesses that registers complementary register, SX. This instruction uses a PEx register with an RX mnemonic. If the syntax named a PEy register SX as the explicit target the processor would use that registers complement RX as the implicit target. For more information on complementary registers, see Secondary Processing Element (PEy) on page 2-37. The cross () in the PEx and PEy registers in Figure 5-17 indicates that the processor zero-fills or sign-extends the most significant 16 bits of the data register while loading the short word value into a 40-bit data register. This depends on the state of the SSE bit in the MODE1 system register. For short word accesses, the least significant 8 bits of the data register are always zero. Figure 5-17 shows the data path for one transfer. The processor accesses short words sequentially in memory. Table 5-9 shows the pattern of SIMD mode short word accesses. For more information on arranging data in memory to take advantage of this access pattern, see Arranging Data in Memory on page 5-100.

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BLOCK 0 (PM)

MEMORY

BLOCK 1 (DM)

ADDRESS

WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD Y3 WORD Y2 WORD Y1 WORD Y0
ADDRESS

WORD X11 WORD X10 WORD X9 WORD X8 WORD X7 WORD X6 WORD X5 WORD X4 WORD X3 WORD X2 WORD X1 WORD X0

NO ACCESS

SHORT WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48 0X0000

47-32 WORD X2

31-16 0X0000

15-0 WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8

RX 7-0

0X0000 WORD X0 0X00 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0 39-24 23-8 SY 7-0 39-24 23-8 SX 7-0

0X0000 WORD X2 0X00

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(SHORT WORD X0 ADDRESS); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SIMD, SHORT WORD, SINGLE-DATA TRANSFERS ARE: UREG = PM(SHORT WORD ADDRESS); UREG = DM(SHORT WORD ADDRESS); PM(SHORT WORD ADDRESS) = UREG; DM(SHORT WORD ADDRESS) = UREG; NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL DATA ACCESSES. DUAL DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-17. Short Word Addressing of Single Data in SIMD Mode

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Table 5-9. Short Word Addressing in SIMD Mode

Explicit Short Word Accessed Word X0 (Address two LSBs = 00) Word X1 (Address two LSBs = 01) Word X2 (Address two LSBs = 10) Word X3 (Address two LSBs = 11) Implicit Short Word Accessed Word X2 (Address two LSBs = 10) Word X3 (Address two LSBs = 11) Word X4 (Address two LSBs = 00) Word X5 (Address two LSBs = 01)

Short Word Addressing of Dual-Data in SISD Mode Figure 5-18 displays one possible SISD mode, dual-data, short word addressed access. For short word addressing, the processor treats the data buses as four 16-bit short word lanes. The 16-bit values for short word accesses transfer using the least significant short word lanes of the PM and DM data buses. The processor drives the other short word lanes of the data buses with zeros. Note that the accesses on both buses do not have to be the same word width. SISD mode dual-data accesses can handle any combination of short word, normal word, extended-precision normal word, or long word accesses. For more information, see Mixed Word Width Addressing of Dual Data in SISD Mode on page 5-82. In SISD mode, the instruction explicitly accesses PEx registers. This instruction accesses WORD X0 in block 1 and WORD Y0 in block 0. Each of these words has a short word address with 00 for its least significant two bits of address. Other accesses within these 4-column location have the addresses with least significant two bits of 01, 10, or 11 and select WORD X1/Y1, WORD X2/Y2, or WORD X3/Y3 from memory respectively. The syntax explicitly accesses registers, RX and RY, in PEx. The example would target PEy registers if using the syntax SX or SY.

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BLOCK 0 (PM)

MEMORY

BLOCK 1 (DM)

ADDRESS

WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD Y3 WORD Y2 WORD Y1 WORD Y0

ADDRESS

WORD Y11 WORD Y10 WORD Y9 WORD Y8

WORD X11 WORD X10 WORD X9 WORD X8 WORD X7 WORD X6 WORD X5 WORD X4 WORD X3 WORD X2 WORD X1 WORD X0

SHORT WORD ACCESS

SHORT WORD ACCESS

63-48 PM DATA BUS 0X0000

47-32 0

31-16 0X0000

15-0 WORD Y0 DM DATA BUS

63-48 0X0000

47-32 0

31-16 0X0000

15-0 WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 0X0000 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8

RX 7-0

WORD Y0 0X00 SA SY 39-24 23-8 7-0

0X0000 WORD X0 0X00 SX 39-24 23-8 7-0

PEY REGISTERS 39-24 23-8

SB 7-0 39-24 23-8

7-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(SHORT WORD X0 ADDRESS), RA = PM(SHORT WORD Y0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SIMD, SHORT WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(SHORT WORD ADDRESS), DREG = DM(SHORT WORD ADDRESS); PM(SHORT WORD ADDRESS) = DREG, DM(SHORT WORD ADDRESS) = DREG;

NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-18. Short Word Addressing of Dual-Data in SISD Mode

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Accessing Memory

The cross () in the PEx registers in Figure 5-18 indicates that the processor zero-fills or sign-extends the most significant 16 bits of the data register while loading a short word value into a 40-bit data register. This depends on the state of the SSE bit in the MODE1 system register. For short word accesses, the least significant 8 bits of the data register are always zero. Short Word Addressing of Dual-Data in SIMD Mode Figure 5-19 displays one possible SIMD mode, dual-data, short word addressed access. For short word addressing, the processor treats the data buses as four 16-bit short word lanes. The explicitly addressed (named in the instruction) 16-bit values transfer using the least significant short word lanes of the PM and DM data bus. The implicitly addressed (not named in the instruction, but inferred from the address in SIMD mode) short word values transfer using the 47-32 bit short word lanes of the PM and DM data buses. The processor drives the other short word lanes of the PM and DM data buses with zeros. The accesses on both buses do not have to be the same word width. SIMD mode dual-data accesses can handle combinations of short word and normal word or extended-precision normal word and long word accesses. For more information, see Mixed Word Width Addressing of Dual Data in SIMD Mode on page 5-84. The instruction explicitly accesses registers RX and RA, and implicitly accesses the complementary registers, SX and SA. This instruction uses a PEx registers with the RX and RA mnemonics. If the syntax named PEy registers SX and SA as the explicit targets, the processor would use those registers complements, RX and RA, as the implicit targets. For more information on complementary registers, see Secondary Processing Element (PEy) on page 2-37.

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Memory

BLOCK 0 (PM)

MEMORY

BLOCK 1 (DM)

ADDRESS

WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD Y3 WORD Y2 WORD Y1 WORD Y0

ADDRESS

WORD Y11 WORD Y10 WORD Y9 WORD Y8

WORD X11 WORD X10 WORD X9 WORD X8 WORD X7 WORD X6 WORD X5 WORD X4 WORD X3 WORD X2 WORD X1 WORD X0

SHORT WORD ACCESS

SHORT WORD ACCESS

63-48 PM DATA BUS 0X0000

47-32 WORD Y2

31-16 0X0000

15-0 WORD Y0 DM DATA BUS

63-48 0X0000

47-32 WORD X2

31-16 0X0000

15-0 WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8

RX 7-0

0X0000 WORD Y0 0X00 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0 39-24 23-8 SY 7-0

0X0000 WORD X0 0X00 SX 39-24 23-8 7-0

0X0000 WORD Y2 0X00

0X0000 WORD X2 0X00

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM (SHORT WORD X0 ADDRESS), RA = PM (SHORT WORD Y0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SIMD, SHORT WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(SHORT WORD ADDRESS), DREG = DM(SHORT WORD ADDRESS); PM(SHORT WORD ADDRESS) = DREG, DM(SHORT WORD ADDRESS) = DREG; NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-19. Short Word Addressing of Dual-Data in SIMD Mode

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Accessing Memory

The cross () in the PEx and PEy registers in Figure 5-19 indicates that the processor zero-fills or sign-extends the most significant 16 bits of the data registers while loading the short word values into the 40-bit data registers. For short word accesses, this depends on the state of the SSE bit in the MODE1 system register. For the short word accesses, the least significant 8 bits of the data register are always zero. Figure 5-19 shows the data path for one transfer. For short word accesses, the processor accesses short words sequentially in memory. Table 5-9 on page 5-58 shows the pattern of SIMD mode short word accesses. For more information on arranging data in memory to take advantage of this access pattern, see Arranging Data in Memory on page 5-100. 32-Bit Normal Word Addressing of Single Data in SISD Mode Figure 5-20 displays one possible SISD mode, single data, 32-bit normal word addressed access. For normal word addressing, the processor treats the data buses as two 32-bit normal word lanes. The 32-bit value for the normal word access transfers using the least significant normal word lane of the PM or DM data bus. The processor drives the other normal word lanes of the data buses with zeros. In SISD mode, the instruction accesses a PEx register. This mode accesses whose normal word address has 0 for its least significant address bit. The other access within this 4-column location has an addresses with a least significant bit of 1 and selects WORD X1 from memory. The syntax targets register RX in PEx. The example would target a PEy register if using the syntax SX.
WORD X0

For normal word accesses, the processor zero-fills least significant 8 bits of the data register on loads and truncates these bits on stores to memory.

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Memory

BLOCK 0 (PM)
WORD Y5
ADDRESS

MEMORY

BLOCK 1 (DM)
WORD X5 WORD X4 WORD X2 WORD X0

WORD Y4 WORD Y2 WORD Y0

ADDRESS

WORD Y3 WORD Y1

WORD X3 WORD X1

NO ACCESS

NORMAL WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48 0X0000

47-32 0X0000

31-16

15-0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8

RX 7-0 0X00 SX 39-24 23-8 7-0

WORD X0 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0 39-24 23-8 SY 7-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(NORMAL WORD X0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SISD, NORMAL WORD, SINGLE-DATA TRANSFERS ARE: UREG = PM(NORMAL WORD ADDRESS); UREG = DM(NORMAL WORD ADDRESS); PM(NORMAL WORD ADDRESS) = UREG; DM(NORMAL WORD ADDRESS) = UREG;

Figure 5-20. 32-Bit Normal Word Addressing of Single Data in SISD Mode

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32-Bit Normal Word Addressing of Single Data in SIMD Mode Figure 5-21 displays one possible SIMD mode, single data, normal word addressed access. For normal word addressing, the processor treats the data buses as two 32-bit normal word lanes. The explicitly addressed (named in the instruction) 32-bit value transfers using the least significant normal word lane of the PM or DM data bus. The implicitly addressed (not named in the instruction, but inferred from the address in SIMD mode) Normal word value transfers using the most significant normal word lane of the PM or DM data bus. In Figure 5-21, the explicit access targets the named register RX, and the implicit access targets that registers complementary register SX. This case uses a PEx register with an RX mnemonic. If the syntax named a PEy register SX as the explicit target, the processor would use that registers complement, RX, as the implicit target. For more information on complementary registers, see Secondary Processing Element (PEy) on page 2-37. For normal word accesses, the processor zero-fills least significant 8 bits of the data register on loads and truncates these bits on stores to memory. Figure 5-21 shows the data path for one transfer. For normal word accesses, the processor accesses normal words sequentially in memory. Table 5-9 shows the pattern of SIMD mode normal word accesses. For more information on arranging data in memory to take advantage of this access pattern, see Arranging Data in Memory on page 5-100.

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ADSP-21161 SHARC Processor Hardware Reference

Memory

BLOCK 0 (PM)

MEMORY

BLOCK 1 (DM)

ADDRESS

WORD Y3 WORD Y1

WORD Y2 WORD Y0

ADDRESS

WORD Y5

WORD Y4

WORD X5 WORD X3 WORD X1

WORD X4 WORD X2 WORD X0

NO ACCESS

NORMAL WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48

47-32

31-16

15-0

WORD X1

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8

RX 7-0 0X00 SX 39-24 23-8 7-0 0X00

WORD X0 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0 39-24 23-8 SY 7-0

WORD X1

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(NORMAL WORD X0 ADDRESS);

PEY REGISTER S

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SIMD, NORMAL WORD, SINGLE-DATA TRANSFERS ARE: UREG = PM(NORMAL WORD ADDRESS); UREG = DM(NORMAL WORD ADDRESS); PM(NORMAL WORD ADDRESS) = UREG; DM(NORMAL WORD ADDRESS) = UREG;

Figure 5-21. 32-Bit Normal Word Addressing of Single Data in SIMD Mode

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Table 5-10. Normal Word Addressing in SIMD Mode

Explicit Normal Word Accessed Word X0 (Address LSB = 0) Word X1 (Address LSB = 1) Implicit Normal Word Accessed Word X1 (Address LSB = 1) Word X2 (Address LSB = 0)

32-Bit Normal Word Addressing of Dual Data in SISD Mode Figure 5-22 displays one possible SISD mode, dual data, 32-bit normal word addressed access. For normal word addressing, the processor treats the data buses as two 32-bit normal word lanes. The 32-bit values for normal word accesses transfer using the least significant normal word lanes of the PM and DM data buses. The processor drives the other normal word lanes of the data buses with zeros. Note that the accesses on both buses do not have to be the same word width. SISD mode dual-data accesses can handle any combination of short word, normal word, extended-precision normal word, or long word accesses. For more information, see Mixed Word Width Addressing of Dual Data in SISD Mode on page 5-82. In Figure 5-22, the access targets PEx registers in a SISD mode operation. This case accesses WORD X0 in block 1 and WORD Y0 in block 0. Each of these words has a normal word address with 0 for its least significant address bit. Other accesses within these 4-column locations have the addresses with the least significant bit of 1 and select WORD X1/Y1 from memory. The syntax targets registers RX and RY in PEx. The example would target PEy registers if using the syntax SX or SY. For normal word accesses, the processor zero-fills least significant 8 bits of the data register on loads and truncates these bits on stores to memory.

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Memory

BLOCK 0 (PM)

MEMORY

BLOCK 1 (DM)

WORD Y5
ADDRESS

WORD Y4 WORD Y2 WORD Y0

ADDRESS

WORD X5 WORD X3 WORD X1

WORD X4 WORD X2 WORD X0

WORD Y3 WORD Y1

NORMAL WORD ACCESS

NORMAL WORD ACCESS

63-48 PM DATA BUS 0X0000

47-32 0X0000

31-16

15-0 DM DATA BUS

63-48 0X0000

47-32 0X0000

31-16

15-0

WORD Y0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 0X00 39-24 23-8

RX 7-0 0X00

WORD Y0

WORD X0

PEY REGISTERS 39-24 23-8

SB 7-0 39-24 23-8

SA 7-0 39-24 23-8

SY 7-0 39-24 23-8

SX 7-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(NORMAL WORD X0 ADDRESS), RY = PM(NORMAL WORD Y0 ADDRESS); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SISD, NORMAL WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(NORMAL WORD ADDRESS), DREG = DM(NORMAL WORD ADDRESS); PM(NORMAL WORD ADDRESS) = DREG, DM(NORMAL WORD ADDRESS) = DREG; NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-22. 32-Bit Normal Word Addressing of Dual Data in SISD Mode

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32-Bit Normal Word Addressing of Dual Data in SIMD Mode Figure 5-23 displays one possible SIMD mode, dual data, 32-bit normal word addressed access. For normal word addressing, the processor treats the data buses as two 32-bit normal word lanes. The explicitly addressed (named in the instruction) 32-bit values transfer using the least significant normal word lane of the PM or DM data bus. The implicitly addressed (not named in the instruction, but inferred from the address in SIMD mode) normal word values transfer using the most significant normal word lanes of the PM and DM data bus. Note that the accesses on both buses do not have to be the same word width. SIMD mode dual-data accesses can handle combinations of short word and normal word or extended-precision normal word and long word accesses. For more information, see Mixed Word Width Addressing of Dual Data in SIMD Mode on page 5-84. In Figure 5-23, the explicit access targets the named registers RX and RA, and the implicit access targets those registers complementary registers SX and SA. This case uses a PEx registers with the RX and RA mnemonics. If the syntax named PEy registers SX and SA as the explicit targets, the processor would use those registers complements RX and RA as the implicit targets. For more information on complementary registers, see Secondary Processing Element (PEy) on page 2-37. For normal word accesses, the processor zero-fills least significant 8 bits of the data register on loads and truncates these bits on stores to memory. Figure 5-23 shows the data path for one transfer. For normal word accesses, the processor accesses normal words sequentially in memory. Table 5-9 on page 5-58 shows the pattern of SIMD mode normal word accesses. For more information on arranging data in memory to take advantage of this access pattern, see Arranging Data in Memory on page 5-100.

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Memory

BLOCK 0 (PM)
WORD Y4 WORD Y2 WORD Y0

MEMORY

BLOCK 1 (DM)
WORD X4 WORD X2 WORD X0

WORD Y5
ADDRESS

WORD X5
ADDRESS

WORD Y3 WORD Y1

WORD X3 WORD X1

NORMAL WORD ACCESS

NORMAL WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48

47-32

31-16

15-0

WORD Y1

WORD Y0

WORD X1

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 0X00 SA 39-24 23-8 7-0 0X00 39-24 23-8 39-24 23-8

RY 7-0 39-24 23-8

RX 7-0 0X00 SX 39-24 23-8 7-0 0X00

WORD Y0 PEY REGISTERS 39-24 23-8 SB 7-0

WORD X0 SY 7-0

WORD Y1

WORD X1

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(NORMAL WORD X0 ADDRESS), RY = PM(NORMAL WORD Y0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SIMD, NORMAL WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(NORMAL WORD ADDRESS), DREG = DM(NORMAL WORD ADDRESS); PM(NORMAL WORD ADDRESS) = DREG, DM(NORMAL WORD ADDRESS) = DREG;

NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-23. 32-Bit Normal Word Addressing of Dual Data in SIMD Mode ADSP-21161 SHARC Processor Hardware Reference 5-69

Accessing Memory

Extended Precision Normal Word Addressing of Single Data Figure 5-24 displays one possible single data, 40-bit extended-precision normal word addressed access. For extended-precision normal word addressing, the processor treats each data bus as a 40-bit extended-precision normal word lane. The 40-bit value for the extended-precision normal word access transfers using the most significant 40 bits of the PM or DM data bus. The processor drives the lower 24 bits of the data buses with zeros. In Figure 5-24, the access targets a PEx register in a SISD or SIMD mode operation; extended-precision normal word single-data access operate the same in SISD or SIMD mode. This case accesses WORD X0 with syntax that targets register RX in PEx. The example would target a PEy register if using the syntax SX.

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Memory

BLOCK 0 (PM)
WORD Y3
ADDRESS

MEMORY

BLOCK 1 (DM)
WORD X3 WORD X2 WORD X1 WORD X0

WORD Y2 WORD Y1
ADDRESS

WORD Y2 WORD Y1

WORD X2 WORD X1

WORD Y0

NO ACCESS

EXTENDED PRECISION NORMAL WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48

47-32 WORD X0

31-16 0X00

15-0 0X0000

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8 WORD X0

RX 7-0

PEY REGISTERS 39-24 23-8

SB 7-0 39-24 23-8

SA 7-0 39-24 23-8

SY 7-0 39-24 23-8 WORD X0

SX 7-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(EXTENDED-PRECISION NORMAL WORD X0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR BROADCAST, EXTENDED-PRECISION NORMAL WORD, SINGLE-DATA TRANSFERS ARE: UREG = PM(EP NORMAL WORD ADDRESS); UREG = DM(EP NORMAL WORD ADDRESS); PM(EP NORMAL WORD ADDRESS) = UREG; DM(EP NORMAL WORD ADDRESS) = UREG;

Figure 5-24. Extended Precision Normal Word Addressing of Single Data

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Extended Precision Normal Word Addressing of Dual Data in SISD Mode Figure 5-25 displays one possible SISD mode, dual data, 40-bit extended-precision normal word addressed access. For extended-precision normal word addressing, the processor treats each data bus as a 40-bit extended-precision normal word lane. The 40-bit values for the extended-precision normal word accesses transfer using the most significant 40 bits of the PM and DM data bus. The processor drives the lower 24 bits of the data buses with zeros. Note that the accesses on both buses do not have to be the same word width. SISD mode dual-data accesses can handle any combination of short word, normal word, extended-precision normal word, or long word accesses. For more information, see Mixed Word Width Addressing of Dual Data in SISD Mode on page 5-82. In Figure 5-25, the access targets PEx registers in a SISD mode operation. This case accesses WORD X0 in block 1 and WORD Y0 in block 0 with syntax that targets registers RX and RY in PEx. The example would target a PEy registers if using the syntax SX or SY.

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Memory

BLOCK 0 (PM)
WORD Y3
ADDRESS

MEMORY
WORD Y2

BLOCK 1 (DM)
WORD X3 WORD X2 WORD X1 WORD X0

WORD Y2 WORD Y1

WORD Y1 WORD Y0

ADDRESS

WORD X2 WORD X1

EXTENDED PRECISION NORMAL WORD ACCESS

EXTENDED PRECISION NORMAL WORD ACCESS

63-48 PM DATA BUS

47-32

31-16 0X00

15-0 0X0000 DM DATA BUS

63-48

47-32 WORD X0

31-16

15-0

WORD Y0

0X00 0X0000

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8 WORD Y0

RY 7-0 39-24 23-8 WORD X0 SY 39-24 23-8 7-0 39-24 23-8

RX 7-0

PEY REGISTERS 39-24 23-8

SB 7-0 39-24 23-8

SA 7-0

SX 7-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(EP NORMAL WORD X0 ADDR.), RY = PM(EP NORMAL WORD Y0 ADDR.); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SISD, EXTENDED PRECISION NORMAL WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(EXT. PREC. NORMAL WORD ADDRESS), DREG = DM(EXT. PREC. NORMAL WORD ADDRESS); PM(EXT. PREC. NORMAL WORD ADDRESS) = DREG, DM(EXT. PREC. NORMAL WORD ADDRESS) = DREG; NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-25. Extended-Precision Normal Word Addressing of Dual Data in SISD Mode

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Extended-Precision Normal Word Addressing of Dual Data in SIMD Mode Figure 5-26 displays one possible SIMD mode, dual data, 40-bit extended-precision normal word addressed access. For extended-precision normal word addressing, the processor treats each data bus as a 40-bit extended-precision normal word lane. Because this word size approaches the limit of the data buses capacity, this SIMD mode transfer only moves the explicitly addressed locations and restricts data bus usage. The explicitly addressed (named in the instruction) 40-bit values transferred over the DM bus must source or sink a PEx data register, and the explicitly addressed (named in the instruction) 40-bit values transferred over the PM bus must source or sink a PEy data register; there are no implicit transfers in this mode. The 40-bit values for the extended-precision normal word accesses transfer using the most significant 40 bits of the PM and DM data bus. The processor drives the lower 24 bits of the data buses with zeros. The accesses on both buses do not have to be the same word width. This special case of SIMD mode dual-data accesses can handle any combination of extended-precision normal word or long word accesses. For more information, see Mixed Word Width Addressing of Dual Data in SIMD Mode on page 5-84. In Figure 5-26, the access targets PEx and PEy registers in a SIMD mode operation. This case accesses WORD X0 in block 1 with syntax that targets register RX in PEx and accesses WORD Y0 in block 0 with syntax that targets register SX in PEy.

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Memory

BLOCK 0 (PM)
WORD Y3
ADDRESS

MEMORY

BLOCK 1 (DM)
WORD X3 WORD X2 WORD X1 WORD X0

ADDRESS

WORD Y2 WORD Y1 WORD Y0

WORD Y2 WORD Y1

WORD X2 WORD X1

EXTENDED PRECISION NORMAL WORD ACCESS

EXTENDED PRECISION NORMAL WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48

47-32 WORD X0

31-16

15-0

WORD Y0

0X00 0X0000

0X00 0X0000

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8 WORD X0

RX 7-0

PEY REGISTERS 39-24 23-8

SB 7-0 39-24 23-8

SA 7-0 39-24 23-8

SY 7-0 39-24 23-8 WORD Y0

SX 7-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(EP NORMAL WORD X0 ADDR.), SX = PM(EP NORMAL WORD Y0 ADDR.); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SIMD, EXTENDED-PRECISION NORMAL WORD, DUAL-DATA TRANSFERS ARE: PEY DREG = PM(EP NORMAL WORD ADDRESS), PEX DREG = DM(EP NORMAL WORD ADDRESS); PM(EP NORMAL WORD ADDRESS) = PEY DREG, DM(EP NORMAL WORD ADDRESS) = PEX DREG; NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-26. Extended-Precision Normal Word Addressing of Dual Data in SIMD Mode

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Long Word Addressing of Single Data Figure 5-27 displays one possible single data, long word addressed access. For long word addressing, the processor treats each data bus as a 64-bit long word lane. The 64-bit value for the long word access transfers using the full width of the PM or DM data bus. In Figure 5-27, the access targets a PEx register in a SISD or SIMD mode operation; long word single-data access operate the same in SISD or SIMD mode. This case accesses WORD X0 with syntax that explicitly targets register RX and implicitly targets its neighbor register RY in PEx. The example would target PEy registers if using the syntax SX. For more information on how neighbor registers (listed in Table 5-7 on page 5-49) work, see Long Word (64-Bit) Accesses on page 5-48.

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Memory

BLOCK 0 (PM)
WORD Y2
ADDRESS

MEMORY

BLOCK 1 (DM)

WORD X2
ADDRESS

WORD Y1 WORD Y0

WORD X1 WORD X0

NO ACCESS

LONG WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48

47-32

31-16

15-0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 0X00 39-24 23-8

RX 7-0 0X00

WORD X0, 63-32

WORD X0, 31-0

PEY REGISTERS 39-24 23-8

SB 7-0 39-24 23-8

SA 7-0 39-24 23-8

SY 7-0 39-24 23-8

SX 7-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(LONG WORD X0 ADDRESS); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SISD OR SIMD, LONG WORD, SINGLE-DATA TRANSFERS ARE: UREG = PM(LONG WORD ADDRESS); UREG = DM(LONG WORD ADDRESS); PM(LONG WORD ADDRESS) = UREG; DM(LONG WORD ADDRESS) = UREG;

NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-27. Long Word Addressing of Single Data

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Accessing Memory

Long Word Addressing of Dual Data in SISD Mode Figure 5-28 displays one possible SISD mode, dual data, long word addressed access. For long word addressing, the processor treats each data bus as a 64-bit long word lane. The 64-bit values for the long word accesses transfer using the full width of the PM or DM data bus. In Figure 5-28, the access targets PEx registers in a SISD mode operation. This case accesses WORD X0 and WORD Y0 with syntax that explicitly targets registers RX registers RA and implicitly targets their neighbor registers RY and RB in PEx. The example would target PEy registers if using the syntax SX and SA. For more information on how neighbor registers (listed in Table 5-7 on page 5-49) work, see Long Word (64-Bit) Accesses on page 5-48. Programs must be careful not to explicitly target neighbor registers in this case. While the syntax lets programs target these registers, one of the explicit accesses targets the other accesss implicit target. The processor resolves this conflict by performing only the access with higher priority. For more information on the priority order of data register file accesses, see Data Register File on page 2-30.

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Memory

BLOCK 0 (PM)
WORD Y2 WORD Y1 WORD Y0

MEMORY

BLOCK 1 (DM)

ADDRESS

ADDRESS

WORD X2 WORD X1 WORD X0

LONG WORD ACCESS

LONG WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48

47-32

31-16

15-0

WORD Y0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 0X00 SB 23-8 7-0 39-24 23-8 39-24 23-8

RA 7-0 0X00 SA 7-0 39-24 23-8 39-24 23-8

RY 7-0 0X0 0 SY 7-0 39-24 23-8 39-24 23-8

RX 7-0 0X00 SX 7-0

WORD Y0, 63-32 PEY REGISTERS 39-24

WORD Y0, 31-0

WORD X0, 63-32

WORD X0, 31-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(LONG WORD X0 ADDRESS), RA = PM(LONG WORD Y0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SISD, LONG WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(LONG WORD ADDRESS), DREG = DM(LONG WORD ADDRESS); PM(LONG WORD ADDRESS) = DREG, DM(LONG WORD ADDRESS) = DREG;

NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-28. Long Word Addressing of Dual Data in SISD Mode

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Long Word Addressing of Dual Data in SIMD Mode Figure 5-29 displays one possible SIMD mode, dual data, long word addressed access targeting internal memory space. For long word addressing, the processor treats each data bus as a 64-bit long word lane. The 64-bit values for the long word accesses transfer using the full width of the PM or DM data bus. Because this word size approaches the limit of the data buses capacity, this SIMD mode transfer only moves the explicitly addressed locations and restricts data bus usage. The explicitly addressed (named in the instruction) 64-bit values transferred over the DM bus must source or sink a PEx data register, and the explicitly addressed (named in the instruction) 64-bit values transferred over the PM bus must source or sink a PEy data register; there are no implicit transfers in this mode. In Figure 5-29, the access targets PEx and PEy registers in a SIMD mode operation. This case accesses WORD X0 in block 1 with syntax that targets register RX and its neighbor register RY in PEx and accesses WORD Y0 in block 0 with syntax that targets register SX and its neighbor register SY in PEy. For more information on how neighbor registers (listed in Table 5-7 on page 5-49) work, see Long Word (64-Bit) Accesses on page 5-48. The accesses on both buses do not have to be the same word width. This special case of SIMD mode dual-data accesses can handle any combination of extended-precision normal word or long word accesses. For more information, see Mixed Word Width Addressing of Dual Data in SIMD Mode on page 5-84.

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BLOCK 0 (PM)
WORD Y2
ADDRESS

MEMORY

BLOCK 1 (DM)

WORD X2
ADDRESS

WORD Y1 WORD Y0

WORD X1 WORD X0

LONG WORD ACCESS

LONG WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48

47-32

31-16

15-0

WORD Y0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 0X00 SY 39-24 23-8 7-0 0X00 39-24 23-8 39-24 23-8

RX 7-0 0X00 SX 7-0 0X00

WORD X0, 63-32 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0

WORD X0, 31-0

WORD Y0, 63-32

WORD Y0, 31-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(LONG WORD X0 ADDRESS), SX = PM(LONG WORD Y0 ADDRESS); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SIMD, LONG WORD, DUAL-DATA TRANSFERS ARE: PEY DREG = PM(LONG WORD ADDRESS), PEX DREG = DM(LONG WORD ADDRESS); PM(LONG WORD ADDRESS) = PEY DREG, DM(LONG WORD ADDRESS) = PEX DREG;

NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-29. Long Word Addressing of Dual Data in SIMD Mode

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Mixed Word Width Addressing of Dual Data in SISD Mode Figure 5-30 displays an example of a mixed word width, dual data, SISD mode access. This example shows how the processor transfers a long word access on the DM bus and transfers a short word access on the PM bus. The memory architecture permits mixing all other combinations of dual-data SISD mode short word, normal word, extended-precision normal word, and long word accesses. In case of conflicting dual access to the data register file, the processor only performs the access with higher priority. For more information on how the processor prioritizes accesses, see Data Register File on page 2-30.

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BLOCK 0 (PM)

MEMORY

BLOCK 1 (DM)

WORD Y11 WORD Y10 WORD Y9 WORD Y8

ADDRESS

WORD X2
ADDRESS

WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD Y3 WORD Y2 WORD Y1 WORD Y0

WORD X1 WORD X0

LONG WORD ACCESS

LONG WORD ACCESS

63-48 PM DATA BUS 0X0000

47-32 0X0000

31-16 0X0000

15-0 WORD Y0 DM DATA BUS

63-48

47-32

31-16

15-0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 0X00 SY 39-24 23-8 7-0 39-24 23-8 39-24 23-8

RX 7-0 0X00 SX 7-0

0X0000 WORD Y0 0X00 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0

WORD X0, 63-32

WORD X0, 31-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(LONG WORD X0 ADDRESS), RA = PM(SHORT WORD Y0 ADDRESS); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SISD, MIXED-WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(SHORT, NORMAL, EP NORMAL, LONG ADD), DREG = DM(SHORT, NORMAL, EP NORMAL, LONG ADD); PM(SHORT, NORMAL, EP NORMAL, LONG ADD) = DREG, DM(SHORT, NORMAL, EP NORMAL, LONG ADD) = DREG; NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-30. Mixed Word Width Addressing of Dual Data in SISD Mode

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Mixed Word Width Addressing of Dual Data in SIMD Mode Figure 5-31 displays an example of a mixed word width, dual data, SIMD mode access. This example shows how the processor transfers a long word access on the DM bus and transfers an extended-precision normal word access on the PM bus. The memory architecture permits mixing SIMD mode dual data short word and normal word accesses or extended-precision normal word and long word accesses. No other combinations of mixed word dual-data SIMD mode accesses are permissible.

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BLOCK 0 (PM)
WORD Y3 WORD Y2 WORD Y1

MEMORY

BLOCK 1 (DM)

ADDRESS

WORD Y1 WORD Y0

ADDRESS

WORD Y2

WORD X2 WORD X1 WORD X0

EXTENDED PRECISION NORMAL WORD ACCESS

LONG WORD ACCESS

63-48 PM DATA BUS

47-32

31-16 0X00

15-0 0X0000 DM DATA BUS

63-48

47-32

31-16

15-0

WORD Y0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 0X00 SY 39-24 23-8 7-0 39-24 23-8 WORD Y0 39-24 23-8

RX 7-0 0X00 SX 7-0

WORD X0, 63-32 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0

WORD X0, 31-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(LONG WORD X0 ADDRESS), SX = PM(EP NORMAL WORD Y0 ADDRESS); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR SIMD, MIXED-WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(ADDRESS), DREG = DM(ADDRESS); PM(ADDRESS) = DREG, DM(ADDRESS) = DREG; NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-31. Mixed Word Width Addressing of Dual Data in SIMD Mode

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Broadcast Load Access Figure 5-32 through Figure 5-39 provide examples of broadcast load accesses for single- and dual-data transfers. These examples show that the broadcast loads memory and register access is a hybrid of the corresponding non-broadcast SISD and SIMD mode accesses. The exceptions to this relation are broadcast load dual-data, extended-precision normal word and long word accesses. These broadcast accesses differ from their corresponding non-broadcast mode accesses.

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BLOCK 0 (PM)

MEMORY

BLOCK 1 (DM)

WORD Y11 WORD Y10 WORD Y9 WORD Y8

ADDRESS

WORD X11 WORD X10 WORD X9 WORD X8

ADDRESS

WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD Y3 WORD Y2 WORD Y1 WORD Y0

WORD X7 WORD X6 WORD X5 WORD X4 WORD X3 WORD X2 WORD X1 WORD X0

NO ACCESS

SHORT WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48 0X0000

47-32 0X0000

31-16 0X0000

15-0 WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8

RX 7-0

0X0000 WORD X0 0X00 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0 39-24 23-8 SY 7-0 39-24 23-8 SX 7-0

0X0000 WORD X0 0X00

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(SHORT WORD X0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR BROADCAST, SHORT WORD, SINGLE-DATA TRANSFERS ARE: UREG = PM(SHORT WORD ADDRESS); UREG = DM(SHORT WORD ADDRESS); PM(SHORT WORD ADDRESS) = UREG; DM(SHORT WORD ADDRESS) = UREG;

Figure 5-32. Short Word Addressing of Single Data in Broadcast Load

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BLOCK 0 (PM)

ADDRESS

MEMORY

ADDRESS

BLOCK 1 (DM)

WORD Y11 WORD Y10 WORD Y9 WORD Y8 WORD Y7 WORD Y6 WORD Y5 WORD Y4 WORD Y3 WORD Y2 WORD Y1 WORD Y0

WORD X11 WORD X10 WORD X9 WORD X8 WORD X7 WORD X6 WORD X5 WORD X4 WORD X3 WORD X2 WORD X1 WORD X0

SHORT WORD ACCESS

SHORT WORD ACCESS

63-48 PM DATA BUS 0X0000

47-32 0X0000

31-16 0X0000

15-0 WORD Y0 DM DATA BUS

63-48 0X0000

47-32 0X0000

31-16 0X0000

15-0 WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8

RX 7-0

0X0000 WORD Y0 0X00 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0 39-24 23-8 SY 7-0

0X0000 WORD X0 0X00 SX 39-24 23-8 7-0

0X0000 WORD Y0 0X00

0X0000 WORD X0 0X00

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(SHORT WORD X0 ADDRESS), RY = PM(SHORT WORD Y0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR BROADCAST, SHORT WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(SHORT WORD ADDRESS), DREG = DM(SHORT WORD ADDRESS); PM(SHORT WORD ADDRESS) = DREG, DM(SHORT WORD ADDRESS) = DREG;

NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-33. Short Word Addressing of Dual Data in Broadcast Load

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BLOCK 0 (PM)
WORD Y5
ADDRESS

MEMORY

BLOCK 1 (DM)
WORD X5

WORD Y4 WORD Y2 WORD Y0

ADDRESS

WORD X4 WORD X2 WORD X0

WORD Y3 WORD Y1

WORD X3 WORD X1

NO ACCESS

NORMAL WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48 0X0000

47-32 0X0000

31-16

15-0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8

RX 7-0 0X00 SX 39-24 23-8 7-0 0X00

WORD X0 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0 39-24 23-8 SY 7-0

WORD X0

THE ABOVE EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(NORMAL WORD X0 ADDRESS); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR BROADCAST, NORMAL WORD, SINGLE-DATA TRANSFERS ARE: UREG = PM(NORMAL WORD ADDRESS); UREG = DM(NORMAL WORD ADDRESS); PM(NORMAL WORD ADDRESS) = UREG; DM(NORMAL WORD ADDRESS) = UREG;

Figure 5-34. Normal Word Addressing of Single Data in Broadcast Load

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BLOCK 0 (PM)

MEMORY

BLOCK 1 (DM)

WORD Y5
ADDRESS

WORD Y4 WORD Y2 WORD Y0

ADDRESS

WORD X5 WORD X3 WORD X1

WORD X4 WORD X2 WORD X0

WORD Y3 WORD Y1

NORMAL WORD ACCESS

NORMAL WORD ACCESS

63-48 PM DATA BUS 0X0000

47-32 0X0000

31-16

15-0 DM DATA BUS

63-48 0X0000

47-32 0X0000

31-16

15-0

WORD Y0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 0X00 SY 39-24 23-8 7-0 0X00 39-24 23-8 39-24 23-8

RX 7-0 0X00 SX 7-0 0X00

WORD Y0 PEY REGISTERS 39-24 23-8 SB 7-0 39-24 23-8 SA 7-0

WORD X0

WORD Y0

WORD X0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(NORMAL WORD X0 ADDRESS), RY = PM(NORMAL WORD Y0 ADDRESS); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR BROADCAST, NORMAL WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(NORMAL WORD ADDRESS), DREG = DM(NORMAL WORD ADDRESS); PM(NORMAL WORD ADDRESS) = DREG, DM(NORMAL WORD ADDRESS) = DREG;

NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-35. Normal Word Addressing of Dual Data in Broadcast Load

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BLOCK 0 (PM)
WORD Y3
ADDRESS

MEMORY

BLOCK 1 (DM)
WORD X3 WORD X2 WORD X1 WORD X0

WORD Y2 WORD Y1
ADDRESS

WORD Y2 WORD Y1

WORD X2 WORD X1

WORD Y0

NO ACCESS

EXTENDED PRECISION NORMAL WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48

47-32 WORD X0

31-16 0X00

15-0 0X0000

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 39-24 23-8 WORD X0

RX 7-0

PEY REGISTERS 39-24 23-8

SB 7-0 39-24 23-8

SA 7-0 39-24 23-8

SY 7-0 39-24 23-8 WORD X0

SX 7-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(EXTENDED-PRECISION NORMAL WORD X0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR BROADCAST, EXTENDED-PRECISION NORMAL WORD, SINGLE-DATA TRANSFERS ARE: UREG = PM(EP NORMAL WORD ADDRESS); UREG = DM(EP NORMAL WORD ADDRESS); PM(EP NORMAL WORD ADDRESS) = UREG; DM(EP NORMAL WORD ADDRESS) = UREG;

Figure 5-36. Extended Precision Normal Word Addressing of Single Data in Broadcast Load

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BLOCK 0 (PM)
WORD Y3
ADDRESS

MEMORY

BLOCK 1 (DM)
WORD X3 WORD X2 WORD X1 WORD X0

WORD Y2
ADDRESS

WORD Y2 WORD Y1

WORD Y1 WORD Y0 WORD

WORD X2 WORD X1

EXTENDED PRECISION NORMAL WORD ACCESS

EXTENDED PRECISION NORMAL WORD ACCESS

63-48 PM DATA BUS

47-32

31-16 0X00

15-0 0X0000 DM DATA BUS

63-48

47-32

31-16

15-0

WORD Y0

WORD X0

0X00 0X0000

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8 WORD Y0

RY 7-0 39-24 23-8 WORD X0 SY 39-24 23-8 WORD Y0 7-0 39-24 23-8 WORD X0

RX 7-0

PEY REGISTERS 39-24 23-8

SB 7-0 39-24 23-8

SA 7-0

SX 7-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(EP NORMAL WORD X0 ADDR.), RY = PM(EP NORMAL WORD Y0 ADDR.); OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR BROADCAST, EXTENDED-PRECISION NORMAL WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(EP NORMAL WORD ADDRESS), DREG = DM(EP NORMAL WORD ADDRESS); PM(EP NORMAL WORD ADDRESS) = DREG, DM(EP NORMAL WORD ADDRESS) = DREG;

NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-37. Extended Precision Normal Word Addressing of Dual Data in Broadcast Load

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BLOCK 0 (PM)
WORD Y2
ADDRESS

MEMORY

BLOCK 1 (DM)

WORD X2
ADDRESS

WORD Y1 WORD Y0

WORD X1 WORD X0

NO ACCESS

LONG WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48

47-32

31-16

15-0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 39-24 23-8

RA 7-0 39-24 23-8

RY 7-0 0X00 39-24 23-8

RX 7-0 0X00

WORD X0, 63-32

WORD X0, 31-0

PEY REGISTERS 39-24 23-8

SB 7-0 39-24 23-8

SA 7-0 39-24 23-8

SY 7-0 0X00 39-24 23-8

SX 7-0 0X00

WORD X0, 63-32

WORD X0, 31-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(LONG WORD X0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR BROADCAST, LONG WORD, SINGLE-DATA TRANSFERS ARE: UREG = PM(LONG WORD ADDRESS); UREG = DM(LONG WORD ADDRESS); PM(LONG WORD ADDRESS) = UREG; DM(LONG WORD ADDRESS) = UREG;

Figure 5-38. Long Word Addressing of Single Data in Broadcast Load

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BLOCK 0 (PM)
WORD Y2
ADDRESS

MEMORY

BLOCK 1 (DM)

WORD X2
ADDRESS

WORD Y1 WORD Y0

WORD X1 WORD X0

LONG WORD ACCESS

LONG WORD ACCESS

63-48 PM DATA BUS

47-32

31-16

15-0 DM DATA BUS

63-48

47-32

31-16

15-0

WORD Y0

WORD X0

PEX REGISTERS 39-24 23-8

RB 7-0 0X00 SB 23-8 7-0 0X00 39-24 23-8 39-24 23-8

RA 7-0 0X00 39-24 23-8

RY 7-0 0X00 SY 39-24 23-8 7-0 0X00 39-24 23-8 39-24 23-8

RX 7-0 0X00 SX 7-0 0X00

WORD Y0, 63-32 PEY REGISTERS 39-24

WORD Y0, 31-0

WORD X0, 63-32

WORD X0, 31-0

SA 7-0 0X00

WORD Y0, 63-32

WORD Y0, 31-0

WORD X0, 63-32

WORD X0, 31-0

THIS EXAMPLE SHOWS THE DATA FLOW FOR INSTRUCTION: RX = DM(LONG WORD X0 ADDRESS), RA = PM(LONG WORD Y0 ADDRESS);

OTHER INSTRUCTIONS WITH SIMILAR DATA FLOWS FOR BROADCAST, LONG WORD, DUAL-DATA TRANSFERS ARE: DREG = PM(LONG WORD ADDRESS), PM(LONG WORD ADDRESS) = DREG, DREG = DM(LONG WORD ADDRESS); DM(LONG WORD ADDRESS) = DREG;

NOTE: DIRECT ADDRESSING IS NOT SUPPORTED FOR DUAL-DATA ACCESSES. DUAL-DATA ACCESSES CAN BE ACCOMPLISHED BY INDIRECT ADDRESSING USING THE DAG REGISTERS.

Figure 5-39. Long Word Addressing of Dual Data in Broadcast Load

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Shadow Write FIFO Considerations in SIMD Mode

The shadow write FIFOs is located between the internal memory array of the ADSP-21161 and core and the IOP busses that access the memory. When performing SIMD reads that cross long word address boundaries and the data read resides in the shadow write FIFO, the read in SIMD mode causes unpredictable results for explicit accesses of odd normal word addresses in internal memory. The implicit part of this SIMD mode transfer incorrectly accesses the previous sequential even address when the data is in the shadow write FIFO. When the read data resides in internal memory, a SIMD mode explicit access to normal word address 0x40001 results in an implicit access to the next sequential even address value. As shown in Table 5-11, a SIMD mode explicit access to normal word address 0x40001 result in an implicit access to normal word address 0x40002. Table 5-11. Data Resides In Internal Memory
Explicit R0 R0=dm(I0,M0); Explicit Address (I0) 0x40001 R0 32-bit word at 0x40001 S0 32-bit word at 0x40002 Explicit S0 S0=dm(I0,M0); R0 32-bit word at 0x40002 S0 32-bit word at 0x40001

Table 5-12 illustrates operation when the previously written data still resides in the shadow write FIFO. For example, from a previous memory write instruction. A SIMD mode explicit access to normal word address 0x40001 results in an implicit access to normal word address 0x40000 if

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the reading of the data from 0x40001 occurs while the data is still in the shadow write FIFO. This access type results in an implicit access to the next sequential even address value. Table 5-12. Data Resides In Shadow Write FIFO
Explicit R0 R0=dm(I0,M0); Explicit Address (I0) 0x40001 R0 32-bit word at 0x40001 S0 32-bit word at 0x40000 Explicit S0 S0=dm(I0,M0); R0 32-bit word at 0x40000 S0 32-bit word at 0x40001

To better demonstrate what results if the read data is in the shadow write FIFO versus internal memory, Table 5-13 shows the failing cases for a SIMD shadow aligned and non-aligned access when a SIMD read immediately follows a SIMD write. Table 5-13. SIMD Write - SIMD Read Illegal Cases
Address of Write Data in Shadow Write FIFO 0x500011 Immediate Read after Write Result Resultant Register Address Contents

r0=dm(0x50000) r0=dm(0x50001) r0=dm(0x50002)

Incorrect Correct Incorrect Incorrect Correct Incorrect Incorrect Correct Correct

r0=(0x50002), s0=(0x50001) r0=(0x50001), s0=(0x50002) r0=(0x50002)2, s0=(0x50003) r0=(0x50001), s0=(0x50002)2 r0=(0x50002), s0=(0x50003) r0=(0x50003), s0=(0x50002) r0=(0xA0004), s0=(0xA0002) r0=(0xA0001), s0=(0xA0003) r0=(0xA0002), s0=(0xA0004)

0x500021

r0=dm(0x50001) r0=dm(0x50002) r0=dm(0x50003)

0xA0002 3

r0=dm(0xA0000) r0=dm(0xA0001) r0=dm(0xA0002)

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Table 5-13. SIMD Write - SIMD Read Illegal Cases (Contd)

Address of Write Data in Shadow Write FIFO Immediate Read after Write Result Resultant Register Address Contents

r0=dm(0xA0003) r0=dm(0xA0004) 0xA00033 r0=dm(0xA0001) r0=dm(0xA0002) r0=dm(0xA0003) r0=dm(0xA0004) r0=dm(0xA0005) 0xA00043 r0=dm(0xA0002) r0=dm(0xA0003) r0=dm(0xA0004) r0=dm(0xA0005) r0=dm(0xA0006) 0xA00053 r0=dm(0xA0003) r0=dm(0xA0004) r0=dm(0xA0005) r0=dm(0xA0006) r0=dm(0xA0007) 0x28001 r0=dm(0x50000) r0=dm(0x50001) r0=dm(0x50002) r0=dm(0x50003) r0=dm(0x50004) 0x28001 r0=dm(0xA0001)

Correct Incorrect Incorrect Correct Correct Correct Incorrect Incorrect Correct Correct Correct Incorrect Incorrect Correct Correct Correct Incorrect Correct Incorrect Correct Incorrect Correct Correct

r0=(0xA0003), s0=(0xA0005) r0=(0xA0004)2, s0=(0xA0006) r0=(0xA0005), s0=(0xA0003) r0=(0xA0002), s0=(0xA0004) r0=(0xA0003), s0=(0xA0005)2 r0=(0xA0004), s0=(0xA0006) r0=(0xA0005)2, s0=(0xA0007) r0=(0xA0002), s0=(0xA0004)2 r0=(0xA0003), s0=(0xA0005) r0=(0xA0004), s0=(0xA0006) r0=(0xA0005), s0=(0xA0007) r0=(0xA0006)2, s0=(0xA0004) r0=(0xA0003), s0=(0xA0005)2 r0=(0xA0004), s0=(0xA0006) r0=(0xA0005), s0=(0xA0007) r0=(0xA0006), s0=(0xA0008) r0=(0xA0007), s0=(0xA0005) r0=(0x50000), s0=(0x50001) r0=(0x50001), s0=(0x50002)2 r0=(0x50002), s0=(0x50003) r0=(0x50003), s0=(0x50002) r0=(0x50004), s0=(0x50005) r0=(0xA0001), s0=(0xA0003)

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Table 5-13. SIMD Write - SIMD Read Illegal Cases (Contd)

Address of Write Data in Shadow Write FIFO Immediate Read after Write Result Resultant Register Address Contents

r0=dm(0xA0002) r0=dm(0xA0003) r0=dm(0xA0004) r0=dm(0xA0005) r0=dm(0xA0006) r0=dm(0xA0007) r0=dm(0xA0008) 0x50002 r0=dm(0x28000) r0=dm(0x28001) r0=dm(0x28002) 0x50003 r0=dm(0x28000) r0=dm(0x28001) r0=dm(0x28002) r0=dm(0x28003) 0x50002 r0=dm(0xA0001) r0=dm(0xA0002) r0=dm(0xA0003) r0=dm(0xA0004) r0=dm(0xA0005) r0=dm(0xA0006) r0=dm(0xA0007) r0=dm(0xA0008) 0xA0004 r0=dm(0x28000)

Incorrect Incorrect Correct Correct Incorrect Incorrect Correct Correct Correct Correct Correct Incorrect Incorrect Correct Correct Incorrect Incorrect Correct Correct Incorrect Incorrect Correct Correct

r0=(0xA0002), s0=(0xA0004)2 r0=(0xA0003), s0=(0xA0005)2 r0=(0xA0004), s0=(0xA0006) r0=(0xA0005), s0=(0xA0007) r0=(0xA0006), s0=(0xA0004) r0=(0xA0007), s0=(0xA0005) r0=(0xA0008), s0=(0xA000A) r0=(0x50000), r1=(0x50001) r0=(0x50002), r1=(0x50003) r0=(0x50004), r1=(0x50005) r0=(0x50000), r1=(0x50001) r0=(0x50004), r1=(0x50003) r0=(0x50004)2, r1=(0x50005) r0=(0x50006), r1=(0x50007) r0=(0xA0001), s0=(0xA0003) r0=(0xA0002), s0=(0xA0004)2 r0=(0xA0003), s0=(0xA0005)2 r0=(0xA0004), s0=(0xA0006) r0=(0xA0005), s0=(0xA0007) r0=(0xA0006), s0=(0xA0004) r0=(0xA0007), s0=(0xA0005) r0=(0xA0008), s0=(0xA000A) r0=(0x50000), r1=(0x50001)

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Table 5-13. SIMD Write - SIMD Read Illegal Cases (Contd)

Address of Write Data in Shadow Write FIFO Immediate Read after Write Result Resultant Register Address Contents

r0=dm(0x28001) r0=dm(0x28002) 0xA0006 r0=dm(0x28000) r0=dm(0x28001) r0=dm(0x28002) r0=dm(0x28003) 0xA0004 r0=dm(0x50000) r0=dm(0x50001) r0=dm(0x50002) r0=dm(0x50003) r0=dm(0x50004) 1 2 3 4

Correct Correct Correct Incorrect Incorrect Correct Correct Incorrect Correct Incorrect Correct

r0=(0x50002), r1=(0x50003) r0=(0x50004), r1=(0x50005) r0=(0x50000), r1=(0x50001) r0=(0x50002)4, r1=(0x50003) r0=(0x50004)2, r1=(0x50005) r0=(0x50006), r1=(0x50007) r0=(0x50000), s0=(0x50001) r0=(0x50001), s0=(0x50002)2 r0=(0x50002), s0=(0x50003) r0=(0x50003), s0=(0x50002)4 r0=(0x50004), s0=(0x50005)

Normal word accesses Old data from memory is accessed instead of new data in Shadow Write FIFO Short word accesses PEx and PEy data is partly from shadow and partly from memory

If the new written data resides in shadow write FIFO, then for normal and short word SIMD accesses, a write access to an even address followed by a read access to the adjacent (higher or lower) odd address results in incorrect SIMD access operation. Similarly, a write access to an odd address followed by a read access to the adjacent (higher or lower) even address results in incorrect SIMD access operation.

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To prevent unexpected SIMD read results when a write is followed by a read from the same long word boundary addresses, two options are recommended. These two suggestions are independent of one another and can be used to work around the SIMD shadow write FIFO. Align all variables and arrays in memory to long word address boundaries using the .ALIGN assembler directive. Do not explicitly access odd normal word addresses or non-long word boundary aligned short word addresses in SIMD mode. Note that for program generated addresses which are odd, you cannot use the .ALIGN workaround. For example, this workaround cannot be used for indirect addressing using the index or pointer DAG registers. OR Include two NOPs or non-memory access instructions to clear the shadow write FIFO.

Arranging Data in Memory

Each processors access to internal memory gets data from 4-columns (long, word) or 3-columns (instruction or extended-precision normal word), 2-column (normal word), or 1-column (short word) memory location. For more information on how the processor accesses 4- or 3-column data, see Memory Organization and Word Size on page 5-25. To take advantage of the processors data accesses to 4- and 3-column locations, programs must adjust the interleaving of data into memory locations to accommodate the memory access mode.

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The following guidelines provide an overview of how programs should interleave data in memory locations. For more information and examples, see the ADSP-21160 SHARC DSP Instruction Set Reference: Programs can use odd or even modify values (1, 2, 3, ) to step through a buffer in single-or dual-data, SISD or Broadcast load mode regardless of the data word size (long word, extended-precision normal word, normal word, or short word). Programs should use multiple of 4 modify values (4, 8, 12, ) to step through a buffer of short word data in single-or dual-data, SIMD mode. Programs must step through a buffer twice, once for addressing even short word addresses and once for addressing odd short word addresses. Programs should use multiple of 2 modify values (2, 4, 6, ) to step through a buffer of normal word data in single- or dual-data SIMD mode. Programs can use odd or even modify values (1, 2, 3, ) to step through a buffer of long word or extended-precision normal word data in single- or dual-data, SIMD mode.

Executing Instructions From External Memory

The ADSP-21161 supports the execution of 48-bit wide program instructions from external memory devices of various widths. The processor can transparently pack and execute 8-bit, 16-bit or 32-bit external memory or execute 48-bit non-packed instructions. This requires that instructions be packed into external memory in a way that differs from the normal packing modes that exist for DMA accesses or host accesses.

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This automatic instruction packing is performed only when the Program Sequencer initiates an external access to fetch an instruction with one of four instruction packing modes enabled in the SYSCON register: 8- to 48-bit, 16- to 48-bit, 32- to 48-bit or 48- to 48-bit packing. Note that the processor only supports program execution from external memory bank 0. The default packing mode the ADSP-21161 processor is 32- to 48-bit packing. Packed instruction execution for 8-, 16-, 32-, or 48-bit wide external memory is also supported and controlled by the IPACK[1:0] bits of the SYSCON register. Table 5-14 summarizes the packing mode configurations controlled by IPACK[1:0] bits. There is a no packing 48-bit bus width mode available on the processor which assumes the EPD bus is 48 bits wide. This full instruction width execution from external memory is made possible by multiplexing 16 link port pins with DATA[15:0] enabling the program execution to run at full-rate. These additional 16 data lines should only be enabled when the link ports are not used. Data lines DATA[15:8] multiplex with L1DAT[7:0] and data lines DATA[7:0] multiplex with L0DAT[7:0]. Set the IPACK bits [1:0] of the SYSCON register to 01 in order to enable DATA[15:0] pins for a 48-bit wide external bus. There are four boot and one no boot modes available on the processor. In the no-boot mode, the processor fetches instructions using a 32- to 48-bit packing. In a boot mode, the packing mode can be changed by writing the new execution packing mode to the IPACK bits before a fetch from external memory occurs. A host can write the new values into the processor or the software loader kernel can change the values during booting.

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Table 5-14. External Instruction Execution Packing Modes

IPACK1 0 0 IPACK0 0 1 Packing Mode Description 32- to 48-bit packed instruction execution Full 48-bit instruction execution / No-Pack mode (DATA[15:0] enabled) with unused L1DAT[7:0] and L0DAT[7:0]. 16- to 48-bit packed instruction execution 8- to 48-bit packed instruction execution

1 1

0 1

L1DATA[7:0] L0DATA[7:0] DATA 15-8 DATA 7-0

DATA 47-16
47 40 39 32 31 24 23 16 15

DATA 15-0
8 7 0

PROM BOOT 8-bit Packed DMA Data 8-bit Packed Instruction Execution 16-bit Packed DMA Data 16-bit Packed Instruction Execution Float or Fixed, D31-D0 DMA 32-bit Packed Instruction 48-bit Instruction Fetch (No Packing)

Extra Data Lines DATA[15-0] Are Only Accessible If Link Ports Are Disabled. Enabled by setting IPACK [1:0] to the no instruction pack mode in the SYSCON register

Figure 5-40. ADSP-21161 External Data Alignment Options

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When writing to bits 30 and 31(IPACK[1:0]) in the SYSCON register to enable the packed instruction mode, delay the instruction fetch from external memory by two instructions. This can be done by inserting two NOPs after a write to SYSCON register or by following the execution sequence shown in the code segment.
ext_isr_tabl_seg_dma10: jump int_codeaddr (db); ustatx = 0x80000000 ; /* change packing from 32-48 to 16-48 */ dm(syscon) = ustatx; int_codeaddr: jump ext_codeaddr (db); ustatx = new_wait_value; dm(WAIT) = ustatx;

The following tables show the addresses for instructions packed in two, three or six consecutive locations in external memory: 48- to 48-Bit External Instruction Packing on page 5-104 32- to 48-Bit External Instruction Packing on page 5-105 16- to 48-Bit External Instruction Packing on page 5-106 8- to 48-Bit External Instruction Packing on page 5-107 For more information on instruction packing in external memory, see the VisualDSP++ Users Guide for ADSP-21xxx Family DSPs. Table 5-15. 48- to 48-Bit External Instruction Packing
ADDRESS 0x200000 0x200001 0x200002 DATA[47:0] Instr0[47:0] Instr1[47:0] Instr2[47:0]

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Table 5-15. 48- to 48-Bit External Instruction Packing (Contd)

ADDRESS 0x200003 0x200004 DATA[47:0] Instr3[47:0] .........

For 48- to 48-bit full instruction width packing, the processor stores one instruction in every 48-bit word memory location. In this packing mode, no address translation is performed by the program sequencer. Instructions are executed from SDRAM at the core clock rate. By enabling IPACK[1:0], the link port data pins L1DAT[7:0] and L0DAT[7:0] are activated as DATA[15:0]. Table 5-16. 32- to 48-Bit External Instruction Packing
ADDRESS 0x200000 0x200001 0x200002 0x200003 0x200004 ......... Instr1[47:16] Instr1[15:0] DATA[47: 2] Instr0[47:16] Instr0[15:0] DATA[31:16]

For 32- to 48-bit instruction packing, the processor stores an instruction in two consecutive memory locations. In this packing mode, the first 32 bits of the 48-bit instruction are stored in an even location and the lower 16 bits of the 48-bit opcode are stored in the adjacent odd location in memory. The program sequencer automatically generates the correct external addresses based on the IPACK bits in the SYSCON register. The program sequencer generates addresses in groups of two physical locations.

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To generate a corresponding address in external memory for the second part of the 48-bit instruction, the processor increments the internal logical address of the previous access by 1. Table 5-17. 16- to 48-Bit External Instruction Packing
ADDRESS 0x200000 0x200001 0x200002 0x200003 0x200004 0x200005 0x200006 0x200007 DATA[31:16] Instr0[47:32] Instr0[31:16] Instr0[15:0] Unused Memory Space Instr1[47:32] Instr1[31:16] Instr1[15:0] Unused Memory Space

Similarly, for 16- to 48-bit instruction packing, the first 16 bits are stored at an even address and the remaining 16 bit segments are stored in consecutive locations. The program sequencer generates addresses in groups of four physical locations. For the remaining accesses, the previous internal logical address is incremented by 1. However, this leaves an unused 16-bit location after every three 16-bit valid instruction segments in the external memory. For example, the three 16 bit segments may be placed at 0x0200000, 0x0200001 and 0x0200002 respectively. The next instruction sixteen bit segments should be placed from address 0x200004 to 0x200007 and so on.

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Table 5-18. 8- to 48-Bit External Instruction Packing

Address 0x200000 0x200001 0x200002 0x200003 0x200004 0x200005 0x200006 0x200007 0x200008 0x200009 0x20000A 0x20000B 0x20000C 0x20000D 0x20000E 0x20000F DATA[23:16] Instr0[47:40] Instr0[39:32] Instr0[31:24] Instr0[23:16] Instr0[15:8] Instr0[7:0] Unused Memory Space Unused Memory Space Instr1[47:40] Instr1[39:32] Instr1[31:24] Instr1[23:16] Instr1[15:8] Instr1[7:0] Unused Memory Space Unused Memory Space

For 8- to 48-bit instruction packing, the first 8 bits are stored at an even address and the remaining 8-bit segments are stored in consecutive locations. The program sequencer generate addresses in groups of eight physical locations. For the remaining accesses, the previous internal logical

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address is incremented by 1. However, this leaves two unused 8-bit locations after every six 8-bit internal logical segments in the external memory. For example, the six 8-bit segments may be placed at 0x0200000, 0x0200001, 0x0200002, 0x0200003, 0x0200004 and 0x0200005 respectively. The next instruction eight bit segments should be placed from address 0x200008 to 0x20000D and so on. In 32- to 48-bit packing mode, each access of external memory to fetch an instruction translates into two accesses to successive locations. In 16- to 48-bit packing mode, each access of external memory to fetch an instruction translates into three accesses to successive locations. In 8- to 48-bit packing mode, each access of external memory to fetch an instruction translates into six accesses to successive locations. The processor core speed for instruction execution is affected by the type of external memory (SDRAM or non-SDRAM) and external memory width. For packed execution modes of 32- to 48-bit, 16- to 48-bit and 8to 48-bit, with the SDCKR bit in the SDCTL register set (=1) and the program executing from SDRAM, the core instruction rate is 2, 3 or 6 times slower than executing from internal memory. When SDCKR=0, the core instruction rate is 4, 6 or 12 times slower. If the program is executing from SRAM or FLASH with a CLKIN-core clock ratio of 2:1, the core speed is reduced by the number of waitstates and a factor of 4, 6 or 12. The effect of external memory accesses on core speed is shown in Table 5-19.

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Table 5-19. External Memory Width Versus Core Speeds

External Memory Width 8-bit 16-bit 32-bit 48-bit SDRAM SDCKR = 1 Core Speed 6 Core Speed 3 Core Speed 2 Core Speed SDCKR = 0 Core Speed 12 Core Speed 6 Core Speed 4 Core Speed 2 Non SDRAM (FLASH, SRAM, SBSRAM) for CLKIN-core clock ratio of 2:1 Core Speed 12 x number of waitstates Core Speed 6 x number of waitstates Core Speed 4 x number of waitstates Core Speed 2 x number of waitstates

In summary, instruction access to external memory translate to one (full 48-bit data bus mode), two, three, or six accesses to successive locations depending on the instruction packing mode selected in bits 30 and 31 in the SYSCON register. For 16- to 48-bit packing, one external address space (two bytes) is unused for every single instruction. Similarly, for 8- to 48-bit packing two external address spaces (two bytes) are unused for every single instruction. For 32- to 48-bit packing, every external address contains valid data. The next sections examine the addressing schemes and unused addresses for all three packing mode cases.

32- to 48-Bit Packing Address Generation Scheme

To generate a corresponding address in external memory for the first part of the instruction, the processor left-shifts the lower bits [19:0] to generate [20:1] bits (ADDR20-0)in external memory, while the processor leaves bits [23:21] unaltered. is 0 for the first access and 1 for the second in the case of operating in 32- to 48-bit packing mode. In this way, internal address 0x200000 on the PM address bus aligns with the beginning of external memory at address 0x200000.
ADDR[0]

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Table 5-20. Address Generation Scheme for 32- to 48-bit Packing1

Segment Seg 1 PM ADDR Bus 0x0200000 0x0200001 0x0200002 ....... 0x02FFFFF 0x0400000 0x0400001 0x0400002 ....... 0x04FFFFF 0x0600000 0x0600001 0x0600002 ...... 0x06FFFFF External Address - ADDR23-0 0x0200000/1 0x0200002/3 0x0200004/5 ....... 0x03FFFFE/F 0x0400000/1 0x0400002/3 0x0400004/5 ....... 0x05FFFFE/F 0x0600000/1 0x0600002/3 0x0600004/5 ...... 0x07FFFFE/F

Seg 2

Seg 3

1 Note that segmented internal address ranges allows continuous addresses in external memory for 48- to 32-bit packing.

Total Program Size (32- to 48-Bit Packing) Total external memory available is 14 Mwords (non-SDRAM) and 62 Mwords (SDRAM). Given that one instruction takes two external memory locations, the external program memory is 7 Mwords non-SDRAM space and 31 Mwords SDRAM space. This scheme limits the size of the contiguous program segment (internal) to 1 Mword. There are seven of these segments in bank 0 non-SDRAM space and 30 segments in bank 0 SDRAM space. See Table 5-22 on page 5-112 for a comparison of total program sizes based on different packing modes.

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16- to 48-Bit Packing Address Generation Scheme

For a 16- to 48-bit packing the lower [18:0] bits of the address are left shifted by two positions to generate [20:2] bits of ADDR (address in external memory) while bits [23:21] are unaltered. ADDR1-0 is 00 for the first access and 01 for the next access and 10 for the third access. Table 5-21. Address Generation Scheme for 16- to 48-Bit Packing
Segment Seg 1 PM ADDR Bus 0x0200000 0x0200001 0x0200002 ...... 0x027FFFF 0x0400000 0x0400001 0x0400002 ...... 0x047FFFF 0x0600000 0x0600001 0x0600002 ...... 0x067FFFF ...... External Address - ADDR23-0 0x0200000/1/2 0x0200004/5/6 0x0200008/9/A ....... 0x03FFFFC/D/E 0x0400000/1/2 0x0400004/5/6 0x0400008/9/A ...... 0x05FFFFC/D/E 0x0600000/1/2 0x0600004/5/6 0x0600008/9/A ...... 0x07FFFFC/D/E ......

Seg 2

Seg 3

Total Program Size (16- to 48-Bit Packing) Total external memory available is 14 Mwords (non-SDRAM) and 62 Mwords (SDRAM). Given that one instruction takes four external memory locations, the external program memory is 3.5 Mwords non-SDRAM space and 15.5 Mwords SDRAM space. This scheme limits the size of the contiguous program segment (internal) to 0.5M. There are seven of these

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segments in bank 0 non-SDRAM space and 30 segments in bank 0 SDRAM space. See Table 5-23 on page 5-113 for a comparison of total program sizes based on different packing modes.

8- to 48-Bit Packing Address Generation Scheme

Similarly, for a 8- to 48-bit packing the lower [17:0] bits of the address are left shifted by three positions to generate [20:3] bits of ADDR while bits [23:21] are unaltered. This way internal address 0x200000 aligns with the beginning of external memory at 0x200000. However, this sort of execution packing gives variable maximum program lengths in external memory for different packing. Table 5-22. Address Generation Scheme for 8- to 48-Bit Packing
Segment Seg 1 PM ADDR Bus 0x0200000 0x0200001 0x0200002 ..... 0x023FFFF 0x0400000 0x0400001 0x0400002 ...... 0x043FFFF 0x0600000 0x0600001 0x0600002 ..... 0x063FFFF ...... External Address - ADDR23-0 0x0200000/1/2/3/4/5 0x0200008/9/A/B/C/D 0x0200010/1/2/3/4/5 ..... 0x03FFFF8/9/A/B/C/D 0x0400000/1/2/3/4/5 0x0400008/9/A/B/C/D 0x0400010/1/2/3/4/5 ....... 0x05FFFF8/9/A/B/C/D 0x0600000/1/2/3/4/5 0x0600008/9/A/B/C/D 0x0600010/1/2/3/4/5 ....... 0x07FFFF8/9/A/B/C/D ......

Seg 2

Seg 3

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Total Program Size (8- to 48-Bit Packing) Total external memory available is 14 Mwords (non-SDRAM) and 62 Mwords (SDRAM). Given that one instruction takes eight external memory locations, the external program memory is 1.75 Mwords non-SDRAM space and 7.75 Mwords SDRAM space. This scheme limits the size of the contiguous program segment (internal) to 0.25 Mwords. There are seven of these segments in bank 0 non-SDRAM space and 30 segments in bank 0 SDRAM space.

No Packing (48- to 48-Bit) Address Generation Scheme

In no-packing 48- to 48-bit mode, execution at full-rate is supported and the size of the external program memory can be 14 Mwords non-SDRAM space or 62 Mwords SDRAM space. No packing is performed for data accesses to external memory. Table 5-23. Total Program Size Comparison
48- to 48-bit (Mwords) SRAM SDRAM 14 62 32- to 48-bit (Mwords) 7 31.34 16- to 48-bit (Mwords) 3.5 15.67 8- to 48-bit (Mwords) 1.75 7.83

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6 I/O PROCESSOR

The processors I/O processor manages Direct Memory Accessing (DMA) of processor memory through the external, SPI, link, and serial ports. Each DMA operation transfers an entire block of data. By managing DMA, the I/O processor lets programs move data as a background task while using the processor core for other processor operations. The I/O processors architecture supports a number of DMA operations. These operations include the following transfer types: Internal memory external memory or external peripherals Internal memory internal memory of other processors Internal memory host processor Internal memory serial port I/O Internal memory link port I/O Internal memory SPI I/O External memory external peripherals This chapter describes the I/O processor and how it controls external port, link port, SPI port, and serial port operations. DMA transfers between internal memory and external memory, multiprocessor memory, or a host use the processors external port. For these types of transfers, a program provides the DMA controller with the internal memory buffer size and address, the address modifier, and the direction of

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transfer. After setup, the DMA transfers begin when the program enables the channel and continues until the I/O processor transfers the entire buffer to or from processor memory. Similarly, DMA transfers between internal memory and link, serial, or SPI port have DMA parameters. When the I/O processor performs DMA between internal memory and one of these ports, the program sets up the parameters, and the I/O uses the port instead of the external bus. The direction (receive or transmit) of the I/O port determines the direction of data transfer. When the port receives data, the I/O processor automatically transfers the data to internal memory. When the port needs to transmit a word, the I/O processor automatically fetches the data from internal memory. The I/O processor also lets the processor system perform DMA transfers between an external device and external memory. This external to external transfer only uses the external port and I/O processor. External devices can control external port DMA transfers in two ways. If the external device can handle bus mastership, the external device master reads or writes to DMA buffers on the processor. External devices also can assert a DMA Request input (DMARx) to request service. To further minimize loading on the processor core, the I/O processor supports chained DMA operations. When using chained DMA, a program initiates a DMA transfer to automatically set up and start the next DMA transfer after the current one completes. External bus packing and unpacking of 16-, 32-, 48-, or 64- bit words in internal memory is performed during DMA transfers from either 8-, 16-, or 32- bit wide external memory. Fourteen channels of DMA are available on the ADSP-21161; two channels are shared between the SPI interface and the link ports, eight channels are available via the serial ports, and four channels are available via the processor's external port for host processor, other ADSP-21161s, memory, or I/O transfers. Asynchronous off-chip peripherals can control two DMA channels using DMA

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Request/Grant lines (DMAR1-2, DMAG1-2). Other DMA features include interrupt generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers. For information on connecting external devices to the external port, link ports, SPI port, or serial ports, see External Port on page 7-1, Link Ports on page 9-1, Serial Peripheral Interface (SPI) on page 11-1 or Serial Ports on page 10-1. Figure 6-1 shows the processors I/O processor, related ports, and buses. Figure 6-5 on page 6-23 shows more detail on DMA channel data paths.

Internal Memory Core Processor

PM Addr DM Addr PM Data DM Data Ext. Port Data Bus (EPD)
48 32 Ext. Port Addr Bus (EPA)

Addr

Data

Addr

Data

External Port

Addr (24-bit)

Data (32-bit)

I/O Address Bus (IOA)

18

64

I/O Data Bus (IOD)

Slave Write FIFO (Async writes 4-deep) (Sync writes 2- deep)

Serial Port Buffer FIFOs (2 deep x 32-bits) Link Port Buffer FIFOs (2 deep x 48-bits) SPI Port Buffer FIFOs (2 deep x 32-bits)

Serial Ports (4) Link Ports (2) SPI Port (1)

DMA Controller Internal Address Generator

External Port Buffer FIFOs (8 deep x 64- bits)

DMA Controller External Address Generator

Figure 6-1. I/O Processor Block Diagram

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The Data Buffer Registers column in Figure 6-2 shows the data buffer registers for each port. These registers include: External Port Buffer (EBPx). These 64-bit buffers for the external port have eight-position FIFOs for transmitting or receiving data when interfacing with a host or external devices such as memory and memory mapped devices. Link Port Buffer (LBUFx). These buffers for the link ports have two-position FIFOs for transmitting or receiving DMA data when connected to another link port. Serial Port Receive Buffer (RXx). These receive buffers for the serial ports have two-position FIFOs for receiving data when connected to another serial device. Serial Port Transmit Buffer (TXx). These transmit buffers for the serial ports have two position FIFOs for transmitting data when connected to another serial device. SPI Receive Buffer (SPIRX). This receive buffer for the SPI port has two-position FIFOs for receiving data when connected to another serial device. SPI Transmit Buffer (SPITX). This transmit buffer for the SPI port has two position FIFOs for transmitting data when connected to another serial device.

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I/O Processor

INTERNAL MEMORY ADDRESS IOA BUS

INTERNAL MEMORY DATA IOD BUS

IRPTL, LIRPTL

SERIAL PORTS 3-0 II3A-0A, II3B- 0B, IM3A-0A, IM3B-0B C3A-0A,C3B-0B, CP3A-0A, CP3B-0B, GP3A-0A, GP3B-0B TX3A-0A, TX3B-0B, RX3A-0A, RX3B-0B SPI PORT IISRX, IISTX, IMSTX, IMSRX, CSRX, CSTX, GPSTX, GPSRX IILB1-0, IMLB1-0, CLB1-0, CPLB1-0, GPLB1-0

SPCTL3-0

SPICTL

SPIRX, SPITX LINK PORTS 1-0

LCTL

LBUF1-0

IIEP3-0, IMEP3-0, CEP3-0, CPEP3-0, GPEP3-0, EIEP3-0, EMEP3-0, ECEP3-0

EXTERNAL PORT DATA SYSCON, WAIT, DMAC13-10, EPB3-0

DMARx DMAGx

DMA PARAMETER REGISTERS

PORT, BUFFER, & DMA CONTROL REGISTERS

DATA BUFFER REGISTERS

EXTERNAL PORT ADDRESS

Figure 6-2. I/O Processor Registers

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The Port, Buffer, and DMA Control Registers column in Figure 6-2 shows the control registers for the ports and DMA channels. These registers include: System Configuration register (SYSCON). This register configures packing, priority, and word order for the external port. Waitstate and Access Mode register (WAIT). This register configures handshake, idle cycle insertion, and waitstate insertion for external memory DMA accesses. External Port DMA Control registers (DMACx). These control registers for each external port DMA channel select the direction, format, handshake, and enable chaining, transfer mode, and DMA start. Link Port Control register (LCTL). This control register selects the direction, word width, transfer rate, and enable chaining and DMA start. This register assigns link buffers to link ports for link port operations. This register indicates link buffer packing and error status for link port operations. Serial Port Control registers (SPCTLx). These control registers for each port select the receive or transmit format, monitor FIFO status, enable chaining, and start DMA. SPI Port Control register (SPICTL). This control register configures and enables the SPI interface, selects the device as master or slave, and determines the data transfer and word size.

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I/O Processor

The DMA Parameter Registers column in Figure 6-2 shows the parameter registers for each DMA channel. These registers function similarly to data address generator registers and include: Internal Index registers (IIx). Index registers provide an internal memory address, acting as a pointer to the next internal memory DMA read or write location. These registers are 18 bits wide and are offset 0x40000 for internal addressing in normal word space. Internal Modify registers (IMx). Modify registers provide the signed increment by which the DMA controller post-modifies the corresponding internal memory index register after the DMA read or write. These registers are 16 bits wide. Count registers (Cx). Count registers indicate the number of words remaining to be transferred to or from internal memory on the corresponding DMA channel. These registers are 16 bits wide. Chain Pointer registers (CPx). Chain pointer registers hold the starting address of the Transfer Control Block (parameter register values) for the next DMA operation on the corresponding channel. These registers also control whether the I/O processor generates an interrupt when the current DMA process ends. These registers are 19 bits wide and are offset 0x40000 for internal addressing in normal word space. General Purpose registers (GPx). General purpose DMA registers hold an address or other value. These registers are 17 bits wide. External Index registers (EIEPx). Index registers provide an external memory address, acting as a pointer to the next external memory DMA read or write location. These registers only apply to external port EPBx DMA. These External Port DMA registers are 32 bits wide.

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 External Modify registers (EMEPx). Modify registers provide the increment by which the DMA controller post-modifies the corresponding external memory index register after the DMA read or write. These registers only apply to external port EPBx DMA. These External Port DMA registers are 32 bits wide. External Count registers (ECEPx). External count registers indicate the number of words remaining to be transferred to or from external memory on the corresponding DMA channel. These registers only apply to external port EPBx DMA. These External Port DMA registers are 32 bits wide. Figure 6-3 shows a block diagram of the I/O processors address generator (DMA controller). Table 6-1 lists the parameter registers for each DMA channel. The parameter registers are uninitialized following a processor reset.

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I/O Processor

DMA ADDRESS GENERATOR (INTERNAL ADDRESSES)

LOCA L BUS

INTERNAL MEMORY ADDRESS

I IX INDEX (ADDRESS)

IMX MODIFI ER

+
POST-MO DIFY

MUX

DMA WORD COUNTER

LO CAL BUS

1 +

CX CO UNT

CPX CHAIN POINTER

GPX GENERAL PURPOSE

WORKING REGISTER

MUX

DMA ADDRESS GENERATOR (EXTERNAL ADDRESSES)

LOCAL BU S

EXTERNAL MEMORY ADDRESS

EIEPX EXT . INDEX (ADDR ESS)

EMEPX EXT. MODIFIER

ECEPX EXT. COUNT

+
POST-MODIFY

Figure 6-3. DMA Address Generator The I/O processor generates addresses for DMA channels much the same way that the Data Address Generators (DAGs) generate addresses for data memory accesses. Each channel has a set of parameter registers (shown in Figure 6-4) including an index register (IIx) and modify register (IMx)

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that the I/O processor uses to address a data buffer in internal memory. The index register must be initialized with a starting address for the data buffer. As part of the DMA operation, the I/O processor outputs the address in the index register onto the processors I/O address bus and applies the address to internal memory during each DMA cyclea clock cycle in which a DMA transfer is taking place.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IIx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IMx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Cx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CPx
Program -Controlled Interrupt Bit If this bit is set, the I/O processor will generate a DMA interrupt on completion of a chained DMA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCI Bit

GPx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EIEPx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EMEPx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ECEPx
(Reserved bits must always be set to zero when programming DMA parameter registers)

Figure 6-4. IOP Parameter Registers

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All addresses in the index (IIx) registers are offset by a value matching the processors first internal Normal word addressed RAM location, before the I/O processor uses the addresses. For the ADSP-21161, this offset value is 0x0004 0000. While DMA addresses must always be Normal word (32-bit) memory, the internal memory data transfer sizes may be 64-, 48-, or 32-bits. External memory data transfer sizes may be 32-, 16 or 8-bits. The I/O processor can transfer Short word data (16-bit) using the packing capability of the external port, serial port and SPI port DMA channels. After transferring each data word to or from internal memory, the I/O processor adds the modify value to the index register to generate the address for the next DMA transfer and writes the modified index value to the index register. The modify value in the IMx register is a signed integer, which allows both increment and decrement modifies. The modify value IMx (which was fixed to 1 on the ADSP-21065L) can now have any positive or negative integer value because of SIMD mode. If the I/O processor modifies the index register past the maximum 18-bit value to indicate an address out of internal memory, the index wraps around to zero. With the offset for the ADSP-21161, the wrap around address is 0x0004 0000. Each DMA channel has a count register (Cx) that loads the programs with a word count to be transferred. The I/O processor decrements the count register after each DMA transfer on that channel. When the count reaches zero, the I/O processor generates the interrupt for that DMA channel. For more information on DMA interrupts, see Using I/O Processor Status on page 6-121. If a program loads the count (Cx) register with zero, the I/O processor does not disable DMA transfers on that channel. The I/O processor interprets the zero as a request for 216 transfers. This count occurs because the I/O processor starts the first transfer before the testing the count value. The only way to disable a DMA

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channel is to clear its DMA enable bit. For more information, see External Port Channel Transfer Modes on page 6-46, Link Port Channel Transfer Modes on page 6-85, or Serial Port Channel Transfer Modes on page 6-99. Each DMA channel also has a chain pointer register (CPx) and a general-purpose register (GPx). Chained DMA sequences are a set of multiple DMA sequences, each autoinitializing the next in line. The location of the parameters for the next sequence comes from the CPx register. These parameters are called a Transfer Control Block (TCB), and they set up DMA parameter values for autoinitializing the next DMA sequence in the chain. Programs can use the GP register for any purpose, but usually programs store the address of the previous TCB in this register during chained DMA. For more information, see Chaining DMA Processes on page 6-25. The external port DMA channels each contain three additional parameter registers, the external index register (EIEPx), external modify register (EMEPx), and external count register (ECEPx). These three registers are not available for the serial port, SPI port and link port DMA channels. The I/O processor generates 32-bit external memory addresses using the EIEPx, EMEPx, and ECEPx registers, during DMA transfers between internal memory and external memory or devices. Programs must load the ECEPx register with the count of external bus transfers in the DMA. If the external port is using word packing, the ECEPx count differs from the number of words transferred in the DMA. Memory mapped devices can communicate with the I/O processor using an internal DMA request/grant handshake on an external port DMA channel. Each channel has a single request and a single grant. When a particular I/O port needs to perform transfers to or from internal memory, the channel asserts a request. The I/O processor prioritizes this request with all other valid DMA requests. The default channel priority is DMA

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I/O Processor

channel 0 as highest and DMA channel 13 as lowest. Table 6-1 lists the DMA channels in priority order. For more information, see Managing DMA Channel Priority on page 6-22. When a channel becomes the highest priority requester, the I/O processor services the channels request. In the next clock cycle, the I/O processor starts the DMA transfer. If a DMA channel is disabled, the I/O processor does not service requests for that channel, whether or not the channel has data to transfer. The processors 14 DMA channels are numbered as shown in Table 6-1. This table also shows the control, parameter, and data buffer registers that correspond to each channel. Table 6-1. DMA Channel Registers: Controls, Parameters, and Buffers
DMA Chan# 0 1 2 3 4 5 SPCTL2 SPCTL1 Control Registers SPCTL0 Parameter Registers Buffer Register Description

II0A, IM0A, C0A, CP0A, GP0A RX0A, TX0A Serial Port 0 A Data II0B, IM0B, C0B, CP0B, GP0B RX0B, TX0B Serial Port 0 B Data

II1A, IM1A, C1A, CP1A, GP1A RX1A, TX1A Serial Port 1 A Data II1B, IM1B, C1B, CP1B, GP1B RX1B, TX1B Serial Port 1 B Data

II2A, IM2A, C2A, CP2A, GP2A RX2A, TX2A Serial Port 2 A Data II2B, IM2B, C2B, CP2B, GP2B RX2B, TX2B Serial Port 2 B Data

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Table 6-1. DMA Channel Registers: Controls, Parameters, and Buffers (Contd)
DMA Chan# 6 7 8 LCTL, SPICTL1 Control Registers SPCTL3 Parameter Registers Buffer Register Description

II3A, IM3A, C3A, CP3A, GP3A RX3A, TX3A Serial Port 3 A Data II3B, IM3B, C3B, CP3B, GP3B IILB0, IMLB0, CLB0, CPLB0, GPLB0 IISRX, IMSRX, CSRX, GPSRX IILB1, IMLB1, CLB1, CPLB1, GPLB1 IISTX, IMSTX, CSTX, GPSTX RX3B, TX3B LBUF0, SPIRX LBUF1 SPITX EPB0 Serial Port 3 B Data Link Buffer 0 SPI Receive Link Buffer 1 SPI Transmit External Port FIFO Buffer 0 External Port FIFO Buffer 1 External Port FIFO Buffer 2 External Port FIFO Buffer 3

10

DMAC10

IIEP0, IMEP0, CEP0, CPEP0, GPEP0, EIEP0, EMEP0, ECEP0 IIEP1, IMEP1, CEP1, CPEP1, GPEP1, EIEP1, EMEP1, ECEP1 IIEP2, IMEP2, CEP2, CPEP2, GPEP2, EIEP2, EMEP2, ECEP2 IIEP3, IMEP3, CEP3, CPEP3, GPEP3, EIEP3, EMEP3, ECEP3

112

DMAC11

EPB1

123

DMAC12

EPB2

13

DMAC13

EPB3

Link port and SPI DMA parameter register names correspond to the same IOP addresses since these peripherals share DMA channels 8 and 9. Since chaining is not supported for SPI DMA, a chain pointer register cannot be use for DMA operation. 2 The DMAR1 and DMAG1 pins are handshake controls for DMA channel 11. 3 The DMAR2 and DMAG2 pins are handshake controls for DMA channel 12.

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I/O Processor

All of the I/O processors registers are memory-mapped in the processors internal memory, ranging from address 0x0000 0000 to 0x0000 01FF. For more information on these registers, see I/O Processor Registers on page A-47. Because the I/O processor registers are memory-mapped, the processor and external processors (host or multiprocessors) have access to program DMA operations. A processor sets up a DMA channel by writing the transfers parameters to the DMA parameter registers. After the IIx, IMx, and Cx registers (among others) are loaded with a starting source or destination address, an address modifier, and a word count, the processor is ready to start the DMA. The external ports, link ports, SPI port, and serial ports each have a DMA enable bit (DEN, LxDEN, SPIEN, or SDEN) in their channel control register. Setting this bit for a DMA channel with configured DMA parameters starts the DMA on that channel. If the parameters configure the channel to receive, the I/O processor transfers data words received at the buffer to the destination in internal memory. If the parameters configure the channel to transmit, the I/O processor transfers a word automatically from the source memory to the channels buffer register. These transfers continue until the I/O processor transfers the selected number of words as determined by the count parameter. To start a new (non-chained) DMA sequence after the current one is finished, programs must disable the channel (clear its DEN bit); write new parameters to the IIx, IMx, and CEPx registers; then enable the channel (set its DEN bit). For chained DMA operations, this disable-enable process is not necessary. For more information, see Chaining DMA Processes on page 6-25.

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DMA Channel Allocation and Priorities

DMA Channel Allocation and Priorities

ADSP-21161 has 14 DMA channels including eight channels accessible via the serial ports, four via the external port and two via the link ports. SPI shares the link port channels for receive and transmit. It is assumed that if DMA is enabled in SPI, then link ports cannot use any of the DMA channels.Table 6-2 shows the DMA channel allocation for the ADSP-21161. Table 6-2. DMA Channel Allocation and Parameter Register Assignments
DMA Channel # 0 1 2 3 4 5 6 7 Data Buffer Parameter Registers IOP Address of DMA Parameter Register 0x60 to 0x64 0x80 to 0x84 0x68 to 0x6C 0x88 to 0x8C 0x70 to 0x74 0x90 to 0x94 0x78 to 0x7C 0x98 to 0x9C Description

RX0A or TX0A RX0B or TX0B RX1A or TX1A RX1B or TX1B RX2A or TX2A RX2B or TX2B RX3A or TX3A RX3B or TX3B

II0A, IM0A, C0A, CP0A, GP0A II0B, IM0B, C0B, CP0B, GP0B II1A, IM1A, C1A, CP1A, GP1A II1B, IM1B, C1B, CP1B, GP1B II2A, IM2A, C2A, CP2A, GP2A II2B, IM2B, C2B, CP2B, GP2B II3A, IM3A, C3A, CP3A, GP3A II3B, IM3B,C3B, CP3B, GP3B

Serial Port 0 A data Serial Port 0 B data Serial Port 1 A data Serial Port 1 B data Serial Port 2 A data Serial Port 2 B data Serial Port 3 A data Serial Port 3 B dara

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I/O Processor

Table 6-2. DMA Channel Allocation and Parameter Register Assignments (Contd)
DMA Channel # 8 Data Buffer Parameter Registers IOP Address of DMA Parameter Register 0x30 to 0x34 Description

LBUF0/SPIRX

IILB0,IMLB0,CLB0, CPLB0,GPLB0 IISRX, IMSRX, CSRX, GPSRX (no CPx) IILB1, IMLB1, CLB1, CPLB1, GPLB1 IISTX, IMSTX, CSTX, GPSTX (no CPx) IIEP0, IMEP0, CEP0, CPEP0, GPEP0, EIEP0, EMEP0, ECEP0 IIEP1, IMEP1, CEP1, CPEP1, GPEP1, EIEP1, EMEP1, ECEP1 IIEP2, IMEP2, CEP2, CPEP2, GPEP2, EIEP2, EMEP2, ECEP2 IIEP3, IMEP3, CEP3, CPEP3, GPEP3, EIEP3, EMEP3, ECEP3

Link Buffer 0 / SPI Receive

LBUF1/SPITX

0x38 to 0x3C

Link Buffer 1 / SPI Transmit

10

EPB0

0x40 to 0x47

External Port FIFO Buffer 0

111

EPB1

0x48 to 0x4F

External Port FIFO Buffer 1

122

EPB2

0x50 to 0x57

External Port FIFO Buffer 2

13

EPB3

0x58 to 0x5F

External Port FIFO Buffer 3

1 2

DMAR1 and DMAG1 are handshake controls for DMA channel 11 DMAR2 and DMAG2 are handshake controls for DMA channel 12.

DMA channel 0 has the highest priority and DMA channel 13 has the lowest priority.

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DMA Interrupt Vector Locations

The DMA channel arbitration feature allows the link port or SPI channel group to rotate priority with the external port channels. This feature may be enabled by setting the PRROT bit in the SYSCON IOP register. The DMA controller can be programmed to use a rotating priority scheme for the four external port channels by setting the DCPR bit in the SYSCON register. The DMA controller can be programmed to use a rotating priority scheme for the two link port DMA channels (channels 8 and 9) by setting the LDCPR bit in the SYSCON register. Each channel has a set of parameter registers (II, IM, C, CP, GP etc.) which are used to setup DMA transfers. DMA parameter register assignments for the various channels are shown in Table 6-2. For ADSP-21160 programs to run on ADSP-21161 processor with no modifications, note that previously used mnemonics and the new mnemonics map to the same addresses whenever appropriate.

DMA Interrupt Vector Locations

Interrupts on the ADSP-21161 are generated at the end of a DMA transfer. This happens when the count register Cx for that channel decrements to zero. The interrupt vector locations for the each channel is listed in Table 6-3. The Link Port Interrupt vector locations and channels are listed in Table 6-4. The interrupt register diagram and bit descriptions are given in Interrupt Mask Pointer Register (IMASKP) on page A-32 Table 6-3. Interrupt Vector Locations
IRPTL/IMASK Bit # 10 11 12 13 Vector Address 0x28 0x2C 0x30 0x34 DMA Channel 0 2 4 6 Data Buffer RX0A or TX0A RX1A or TX1A RX2A or TX2A RX3A or TX3A

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Table 6-3. Interrupt Vector Locations (Contd)

IRPTL/IMASK Bit # 10 11 12 13 15 16 17 18 Vector Address 0x28 0x2C 0x30 0x34 0x50 0x54 0x58 0x5C DMA Channel 1 3 5 7 10 11 12 13 Data Buffer RX0B or TX0B RX1B or TX1B RX2B or TX2B RX3B or TX3B EPB0 EPB1 EPB2 EPB3

Table 6-4. Link Port Interrupt Vector Locations

LIRPTL Bits Ptr/Mask/Latch 24/16/0 26/18/2 25/17/1 27/19/3 Vector Address 0x38 0x40 0x3C 0x44 9 DMA Channel 8 Data Buffer LBUF0 SPIRX LBUF1 SPITX

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Booting Modes

Booting Modes
The booting modes that are supported by the ADSP-21161 processor are given in Table 6-5. Table 6-5. Booting Modes for ADSP-21161
EBOOT 1 0 0 0 0 1 2 3 LBOOT 0 0 1 1 0 BMS output 1 (input) 1 (input) 0 (input) 0 (input) Booting Mode EPROM Boot (connect BMS to EPROM chip select)1 Host Boot1 Link Boot2 Serial Boot (SPI)3 No Booting (processor executes from the external memory)

For the Host and EPROM boots, the DMA channel 10 (EPB0) is used. For the link boot, the DMA channel 8 (LBUF0) is used. Serial boot (SPI) uses DMA channel 8 (its mutually exclusive with the link ports).

DMA Controller Operation

DMA sequences start in different ways depending on whether DMA chaining is enabled. When chaining is not enabled, only the DMA enable bit (DEN) allows DMA transfers to occur. A DMA sequence starts when one of the following occurs: Chaining is disabled and the DMA enable bit (DEN) transitions from low to high. Chaining is enabled, DMA is enabled (DEN=1), and the CPx register address field is written with a non-zero value. In this case, TCB chain loading of the channel parameter registers occurs first.

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I/O Processor

Chaining is enabled, the CPx register address field is non-zero, and the current DMA sequence finishes. Again, TCB chain loading occurs. A DMA sequence ends when one of the following occurs: The count register Cx decrements to zero (both CEPx and ECEPx for external port channels). Chaining is disabled and the channels DEN bit transitions from high to low. If the DEN bit goes low (=0) and chaining is enabled, the channel enters chain insertion mode and the DMA sequence continues. For more information, see Inserting a TCB in an Active Chain on page 6-28. When a program sets the DEN bit (=1) after a single DMA finishes, the DMA sequence continues from where it left off (for non-chained operations only). To start a new DMA sequence after the current one is finished, a program must first clear the DEN enable bit, write new parameters to the IIx, IMx, and Cx registers, then set the DEN bit to re-enable DMA. For chained DMA operations, these steps are not necessary. For more information, see Chaining DMA Processes on page 6-25. If a DMA operation completes and the count register is rewritten before the DMA enable bit is cleared, the DMA transfer restarts at the new count. Once a program starts a DMA process, the process is influenced by two external controls: DMA channel priority and DMA chaining. For more information, see Managing DMA Channel Priority on page 6-22 or Chaining DMA Processes on page 6-25.

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DMA Controller Operation

Managing DMA Channel Priority

The DMA channels for each of the processors I/O ports negotiate channel priority with the I/O processor using an internal DMA request/grant handshake. Each I/O port (link ports, serial port, SPI port, and external port) has one or more DMA channels, with each channel having a single request and a single grant. When a particular channel needs to read or write data to internal memory, the channel asserts an internal DMA request. The I/O processor prioritizes the request with all other valid DMA requests. When a channel becomes the highest priority requester, the I/O processor asserts the channels internal DMA grant. In the next clock cycle, the DMA transfer starts. Figure 6-5 shows the paths for internal DMA requests within the I/O processor. If a DMA channel is disabled (DEN, LxDEN, SPIEN, or SDEN bit =0), the I/O processor does not issue internal DMA grants to that channel, whether or not the channel has data to transfer. Because more than one DMA channel can make a DMA request in a particular cycle, the I/O processor prioritizes DMA channel service. DMA channel prioritization determines which channel can use the IOD (I/O Data) bus to access memory. Default DMA channel priority is fixed prioritization by DMA channel type (serial ports, SPI port, link ports, or external port). Within the DMA channel types, the serial port DMA channels are always fixed priority, the external port DMA channels may be either fixed or rotated priority, and the link port DMA channels may be either fixed or rotated priority. Table 6-1 on page 6-13 lists the DMA channels in descending order of priority. For information on programming external port priority modes, see External Port Channel Priority Modes on page 6-43. For information on programming link port priority modes, see Link Port Channel Priority Modes on page 6-83.

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I/O Processor

DSP CORE PM ADDRESS DM ADDRESS ADDR ADDR

INTERNAL MEMORY

ON ASYNCHRONOUS WRITES, THE SLAVE WRITE FIFO IS 2 DEEP. ON SYNCHRONOUS WRITES, THE SLAVE WRITE FIFO IS 4 DEEP.

ADDR

DATA

DATA

DATA IOD PMA DMA PMD DMD EPD

IOA PM DATA DM DATA

PMD

DMD

EXTERNAL PORT

ADDR 24 SLAVE WRITE FIFO (2/4 DEEP) BUFFER 32 DATA

I/O ADDRESS BUS (IOA) 18 64

I/O DATA BUS (IOD) 64 EXT. PORT DATA BUS (EPD)

EPA 32

EXT. PORT ADDR BUS (EPA)

I/O PROCESSOR INTERNAL DMA ADDRESS GENERATORS GRNTS REQ.S EXTERNAL PORT FIFOS EPB (8 DEEP) LINK PORT FIFOS LBUF (2 DEEP) EXTERNAL DMA ADDRESS GENERATORS GRNTS REQ.S DMAR REQUESTS GRANTS DMAG EXTERNAL DMA PRIORITZER SPI PORT BUFFER FIF OS (2 DEEP) DMA CONTROLLER LINK PORTS OTHER IOP REGISTERS SERIAL PORTS SPI PORT

14 REQUESTS GRANTS INTERNAL DMA PRIORITZER DMA CONTROLLER 14

SERIAL PORT FIFOS RX,TX (2 DEEP)

Figure 6-5. I/O Processor Request and Grant Paths

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DMA Controller Operation

For information on programming serial port priority modes, see Serial Port Channel Priority Modes on page 6-99. For information on programming SPI port priority modes, see SPI DMA Channel Priority on page 6-112. The SPI port does not support DMA chaining. The I/O processor determines which DMA channel has the highest priority internal DMA request during every cycle between each data transfer. Internal DMA channel arbitration differs from external bus arbitration. For more information on external bus arbitration, see Multiprocessor Bus Arbitration on page 7-93. Processor core accesses of I/O processor registers and TCB chain loading are subject to the same prioritization scheme as the DMA channels. Applying this scheme uniformly prevents I/O bus contention, because these accesses are also performed over the internal I/O bus. TCB chain loading has a higher priority than external port accesses and link port/SPI port DMA accesses. This TCB priority permits chained serial port DMA, even when the external port is attempting an access in every cycle. For more information, see Chaining DMA Processes on page 6-25. If a processor has the link ports enabled and active at the same time, the default priority scheme could hold off external port DMA channels for extended periods of time. Because this hold off could have a significant negative impact on external bus performance, the I/O processor permits rotating DMA channel priority between the link port channel group and external port channel group. For more information on using the PRROT bit to rotate priority between link ports and the external port, see Link Port Channel Priority Modes on page 6-83.

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I/O Processor

Chaining DMA Processes

DMA chaining lets the I/O processor automatically load DMA parameters and start the next DMA when the current DMA finishes. This feature permits unlimited multiple DMA transfers without processor core intervention. Using chaining, programs can set up multiple DMA operations with each operation can have different attributes. To chain together multiple DMA operations, the I/O processor must load the next Transfer Control Block (DMA parameters) into the DMA parameter registers when the current DMA finishes (DMA count =0). The chain pointer register (CPx) points to the next set of DMA parameters, which are stored in internal memory. This process of loading the TCB into the parameter registers is called TCB chain loading. Two controls enable chained DMA. Each DMA channel has a chaining enable bit (CHEN) in the channels control register. When set, the CHEN bit directs the I/O processor to use the CPx register for chained DMA. Programs start the chained DMA by writing a non-zero address to the CPx register, directing the I/O processor to start the DMA with TCB chain loading. Programs can disable chained DMA by writing all zeros to the address field of the CPx register. Chained DMA operations may only occur within the same channel. The processor does not support cross-channel chaining and the SPI port does not support DMA chaining The CPx register is 19 bits wide, of which the lower 18 bits are the memory address field. Like other I/O processor address registers, the CPx registers value is offset to match the starting address of internal memory before being used by the I/O processor. On the ADSP-21161, this offset value is 0x0004 0000.

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DMA Controller Operation

Bit 18 of the CPx register (shown in Figure 6-6) is the Program Controlled Interrupts (PCI) bit. If set, the PCI bit enables a DMA channel interrupt to occurs at the completion of the current DMA sequence. The PCI bit only effects DMA channels that have chaining enabled (CHEN =1). Also, interrupt requests enabled by the PCI bit are maskable with the IMASK register. Because the PCI bit is not part of the memory address in the CPx register, programs must be careful when writing and reading addresses to and from the register. To prevent errors, programs should mask out the PCI bit (bit 18) when copying the address in CPx to another address register.
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CPx
Program -Controlled Interrupt Bit If this bit is set, the I/O processor will generate a DMA interrupt on completion of a chained DMA

PCI Bit

Figure 6-6. CPX Register During chained DMA, the channels General Purpose (GP) register is a useful place to point to the last completed DMA sequence. This practice lets programs determine where the last full (or empty) data buffer is located. Transfer Control Block (TCB) Chain Loading During TCB chain loading, the I/O processor loads the DMA channel parameter registers with values retrieved from internal memory. The address in the CPx register points to the highest address of the TCB (containing the IIx or IIEPx parameter). The TCB values reside in consecutive memory locations.

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Table 6-6 shows the TCB-to-register loading sequence for the external port, link port, and serial port DMA channels. The I/O processor reads each word of the TCB and loads it into the corresponding register. Programs must set up the TCB in memory in the order shown in Table 6-6, placing the IIx parameter at the address pointed to by the CPx register of the previous DMA operation of the chain. Table 6-6. TCB Chain Loading Sequence
Address1 CPx + 0x0004 0000 CPx 1 + 0x0004 0000 CPx 2 + 0x0004 0000 CPx 3 + 0x0004 0000 CPx 4 + 0x0004 0000 CPx 5 + 0x0004 0000 CPx 6 + 0x0004 0000 CPx 7 + 0x0004 0000 CPx 8 + 0x0004 0000 1 External Port IIEPx IMEPx CEPx CPEPx GPEPx EIEPx EMEPx ECEPx Link and Serial Ports IIx IMx Cx CPx GPx

An x denotes the DMA channel used. Link, SPI, and serial ports use the first five locations only.

A TCB chain load request is prioritized like all other DMA operations. The I/O processor latches a TCB loading request and holds it until the load request has the highest priority. If multiple chaining requests are present, the I/O processor services the TCB registers for the highest priority DMA channel first. A channel which is in the process of chain loading cannot be interrupted by a higher priority channel. For a list of DMA channels in priority order, see Table 6-1 on page 6-13. For more information on DMA priority, see Managing DMA Channel Priority on page 6-22.

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DMA Controller Operation

Setting Up and Starting the Chain To setup and initiate a chain of DMA operations, use the following steps: 1. Set up all TCBs in internal memory. 2. Write to the appropriate DMA control register, setting the DEN DMA enable bit to 1 and the CHEN chaining enable bit to 1. 3. Write the address containing the IIx register value of the first TCB to the CPx register, starting the chain. The I/O processor responds by autoinitializing the channels parameter registers with the first TCB and starting the first transfer. When the transfer finishes, the I/O processor begins the next TCB chain load if the current chain pointer address is non-zero. The CPx address points to the next TCB. The address field of the CPx registers is only 18 bits wide. If a program writes a symbolic address to bit 18 of CPx, there may be a conflict with the PCI bit. Programs should clear the upper bits of the address, then AND the PCI bit separately, if needed. Inserting a TCB in an Active Chain It is possible to insert a single DMA operation or another DMA chain within an active DMA chain. Programs may need to perform insertion when a high priority DMA requires service and cannot wait for the current chain to finish.

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When DMA on a channel is disabled (DEN=0) and chaining on the channel is enabled (CHEN=1), the DMA channel is in chain insertion mode. This mode lets a program insert a new DMA or DMA chain within the current chain without effecting the current DMA transfer. Use the following sequence to insert a DMA subchain while another chain is active: 1. Enter chain insertion mode by setting CHEN=1 and DEN=0 in the channels DMA control register. The DMA interrupt indicates when the current DMA sequence has completed. 2. Write the CPx register value into the CP position of the last TCB in the new chain. 3. Enter chained DMA mode by setting DEN=1 and CHEN=1. 4. Write the start address of the first TCB of the new chain into the CPx register. Chain insertion mode operates the same as chained DMA mode (DEN=1, CHEN=1), except that when the current DMA transfer ends, automatic chaining is disabled and an interrupt request occurs. This interrupt request is independent of the PCI bit state. Chain insertion should not be set up as an initial mode of operation. This mode should only be used to insert a DMA within an active DMA chaining operation.

External Port DMA

There are four external port DMA channels available on the ADSP-21161: channels 10, 11, 12 and 13. These DMA channels enable efficient data transfers between the processor's internal memory and external memory, peripherals, host processor, or other SHARCs. DMA transfers between the processor and any external devices that do not have

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External Port DMA

bus master capability use these channels. Channels 10, 11, 12, and 13 are assigned to EPB0, EBP1, EPB2 and EPB3 buffers respectively, and are controlled by DMAC10, DMAC11, DMAC12 and DMAC13 DMA control registers. The ADSP-21161 processor supports a number of DMA modes for external port DMA. The following sections describes typical external port DMA processes: Setting Up External Port DMA on page 6-68 Bootloading Through The External Port on page 6-70 Boot Memory DMA Mode on page 6-42 External Port Buffer Modes on page 6-42 External Port Channel Priority Modes on page 6-43 External Port Channel Transfer Modes on page 6-46 External Port Channel Handshake Modes on page 6-47

External Port Registers

The SYSCON, WAIT, and DMACx registers control the external port operating mode for the I/O processor. The following tables and figures describe the external port registers: Table A-10 on page A-34 lists all the bits in SYSCON Table A-11 on page A-37 lists all the bits in WAIT Table A-13 on page A-43 and Figure 6-8 on page 6-41 lists all the bits in DMACx

The following bits control external port I/O processor modes. Except for the FLSH bit, the control bits in the DMACx registers have a one cycle effect latency. The FLSH bit has a two cycle effect latency. Programs should not modify an active DMA channels DMACx register other than to disable the 6-30 ADSP-21161 SHARC Processor Hardware Reference

I/O Processor

channel by clearing the DEN bit. For information on verifying a channels status with the DMASTAT register, see Using I/O Processor Status on page 6-121. Some other bits in SYSCON, WAIT, and DMACx setup non-DMA external port features. For information on these features, see Setting External Port Modes on page 7-3. Boot Select Override. SYSCON Bit 1 (BSO). This bit enables (if set, =1) or disables (if cleared, =0) access to Boot Memory Space. When BSO is set, the processor uses the BMS select line (instead of MS3-0) to perform DMA channel 10 accesses to external memory. Host Bus Width. SYSCON Bits 5-4 (HBW). These bits select the host bus width as follows: 00=32-bit width, 01=16-bit width, 10=8-bit width (reset value). Host Most Significant Word First Packing Select. SYSCON Bit 7 (HMSWF). This bit selects the word packing order for host accesses as most-significant-word first (if set, =1) or least-significant-word first (if cleared, =0). Buffer Hang Disable. SYSCON Bit 16 (BHD). This bit controls whether the processor core proceeds (hang disabled if set, =1) or is held-off (hang enabled if cleared, =0) when the core tries to read from an empty EPBx, RXx, LBUFx or SPIRX buffer or tries to write to a full EPBx, TXx, LBUFx or SPITX buffer. External Port DMA Channel Priority Rotation Enable. SYSCON Bit 19 (DCPR). This bit enables (rotates if set, =1) or disables (fixed if cleared, =0) priority rotation among external port DMA channels (channel 10-13). Handshake and Idle for DMA Enable. WAIT Bit 30 (HIDMA). This bit enables (if set, =1) or disables (if cleared, =0) adding an idle cycle after every memory access for DMAs with handshaking (DMARx-DMAGx).

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External Port DMA Enable. DMACx Bit 0 (DEN). This bit enables (if set, =1) or disables (if cleared, =0) DMA for the corresponding external port FIFO buffer (EPBx). External Port DMA Chaining Enable. DMACx Bit 1 (CHEN). This bit enables (if set, =1) or disables (if cleared, =0) DMA chaining for the corresponding external port FIFO buffer (EPBx). External Port Transmit/Receive Select. DMACx Bit 2 (TRAN). This bit selects the transfer direction for the corresponding external port FIFO buffer (EPBx). If set (=1), the port transmits data from internal memory. If cleared (=0), the port receives data from external memory. External Port Data Type Select. DMACx Bit 5 (DTYPE). This bit selects the transfer data type (40/48=bit, 3-column if set, =1) (32/64-bit, 4-column if cleared, =0) for the corresponding external port FIFO buffer (EPBx). External Port Packing Mode. DMACx Bits 8-6 (PMODE). These bits select the packing mode for the corresponding external port FIFO buffer (EPBx) as follows: 000=reserved, 001=16 external to 32/64 internal packing, 010=16 external to 48 internal packing, 011=32 external to 48 internal packing, 100= no packing, 101=8 external to 48 internal packing, 110= 8 external to 32/64 internal packing, 111=reserved. During reset, the default is PMODE = 101. Most Significant Word First. DMACx Bit 9 (MSWF). When the buffers PMODE is 001 or 010, this bit selects the packing order of 8-bit or 16-bit words (most significant first if set, =1) (least significant first if cleared, =0) for the corresponding external port FIFO buffer (EPBx). Master Mode Enable. DMACx Bit 10 (MASTER). This bit enables (if set, =1) or disables (if cleared, =0) master mode for the corresponding external port FIFO buffer (EPBx).

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Handshake Mode Enable. DMACx Bit 11 (HSHAKE) This bit enables (if set, =1) or disables (if cleared, =0) handshake mode for the corresponding external port FIFO buffer (EPBx). External Handshake Mode Enable. DMACx Bit 13 (EXTERN). This bit enables (if set, =1) or disables (if cleared, =0) external handshake mode for the corresponding external port FIFO buffer (EPBx). External Port Bus Priority. DMACx Bit 15 (PRIO). This bit selects the external bus access priority level (high if set, =1) (low if cleared, =0) for the corresponding external port FIFO buffer (EPBx).

External Port FIFO Buffers

DMA channels 10, 11, 12 and 13 are associated with the external port FIFO data buffers EPB0, EPB1, EPB2, and EPB3. Each buffer acts as an eight-location FIFO that has two ports: a read port and a write port. Each port can connect to either the EPD (External Port Data) or one of the following buses: the IOD (I/O Data) bus, the PM Data bus, or the DM Data bus. The FIFO structure enables DMA transfers at full processor clock frequency with SDRAM or at the CLKIN system clock rate for host and other memories. This is possible because reads and writes for the same data can occur simultaneously through the FIFO's separate read and write ports. You can also use the external port FIFO buffers for non-DMA, single word data transfers too. Do not attempt to make core reads or writes to or from an EPBx buffer when a DMA operation using that buffer is in progress. This corrupts the DMA data.

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To flush (clear) an external port buffer, write 1 to the FLSH bit in the appropriate DMACx control register. The DMA for the channel must be disabled during the write operation. The FLSH bit is not latched internally and always reads as 0. Status can change in the following cycle. Do not enable and flush an external port buffer in the same cycle. For DMA transfers between the processors internal memory and external memory, the DMA controller must generate addresses in both memories. The external port DMA channels contain both EIEPx (External Index) and EMEPx (External Modify) registers to generate external addresses. The EIEPx register provides the external port address for the current DMA cycle. It is updated with the modifier value in EMEPx for the next external memory access.

External Port DMA Data Packing

Each external port buffer contains data packing logic to pack 8-, 16-, or 32-bit external bus words into 32/64 or 48-bit internal words. The packing logic works in reverse to unpack 32/64-bit data or 48-bit internal data into 8-, 16-, or 32-bit external data. The external port data alignment is shown in Figure 6-7. To support the wide range of data packing options provided for external DMA transfers, the EIEPx and EMEPx registers can generate addresses at a different rate than the internal address generating registers IIEPx and IMEPx. For this reason, the internal and external address generators operate independently, and the ECEPx (External Count) register serves as the external DMA word counter. For example, when a 16-bit DMA device reads data from the processors internal memory, two external 16-bit transfers occur for each 32-bit internal memory word. The ECEPx (external) word count is twice the value of the CEPx (internal) word count.

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L1DATA[7:0] L0DATA[7:0] DATA15-8 DATA7-0

DATA47-16
47 40 39 32 31 24 23 16 15

DATA15-0
87 0

PROM BOOT 8-bit Packed DMAData 8-bit Packed Instruction Execution

16-bit Packed DMAData 16-bit Packed Instruction Execution Float or Fixed, D31-D0, 32-bit Packed DMA 32-bit Packed Instruction Execution 48-bit Instruction Fetch (No Packing)

Figure 6-7. External Port Data Alignment The PMODE bits in the DMACx control registers determine the packing mode for internal bus words while the HBW bits in the SYSCON register determine the packing mode for external bus words. Table 6-7 shows the packing modes of operation for the PMODE[2:0] that correspond to bits 8, 7, and 6 in the DMACx register. During reset, the default value PMODE in DMAC10 is 101 (8- to 48-bit packing for PROM or Host booting)

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Table 6-7. Packing Mode Combinations

PMODE HBW 8/16/32 Host Packing Mode (External:Internal) IOP Buffers Internal Packing Fixed to 32-bit Reserved 16 : 32 16 : 32 32 : 32 32 : 32 8 : 32 8 : 32 Reserved 16 : 48 16 : 48 32 : 48 32 : 48 8 : 48 8 : 48 16 : 32/64 16 : 48 32 : 48 32 : 32/64 8 : 48 8 : 32/64 Link Ports Buffers Internal Packing Fixed to 48-bit External Port Buffers Uses PMODE, INT32 and DTYPE (1=48/40, 0=32/64)

000 001 010 011 100 101 110 111

01 (16-bit) 01 (16-bit) 00 (32-bit) 00 (32-bit) 10 (8-bit) 10 (8-bit) -

Each external port DMA control register contains a three bit PS field that indicates the number of short words currently packed in the EPBx buffer. The PS status field behaves the same way during packing and unpacking operations. All packing functions are available for all types of DMA transfers. Table 6-8 shows the values of PS[2:0] that correspond to bits 23, 22, and 21 of the DMACx register. Packing mode bit settings depend on whether the host access is processor-to-processor or processor-to-memory. To access another ADSP-21161 or memory, you must set the PMODE bits only (HBW bits have no effect) to pack and unpack individual data words for the following modes: master mode, paced master mode and handshake mode DMA.

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For host accesses, to pack and unpack individual data words, you must set both the PMODE bits in the appropriate DMACx control register and the HBW bits in the SYSCON register. Table 6-7 shows the packing mode bit settings for access to IOP, link port and external port buffers. Table 6-8. External Port FIFO Buffer Packing Status (Read Only)
PS[2:0] 000 001 010 011 100 EPBx Packing Status Packing complete 1st stage 2nd stage 3rd stage fifth stage of 8/48

For transfers to or from the EPBx data buffers, the packing mode is determined by the setting of the HBW bits of the SYSCON register AND the PMODE bits in the DMACx control register of each external port buffer. The external port buffer can pack data in most significant word first (MSWF) order or in least significant word first (LSWF) order. Setting the bit MSWF to 1 in the DMACx control register selects MSW mode for both packing and unpacking operations. The MSWF bit has no effect when PMODE=111 or PMODE=000. 32-Bit Bus Downloading The packing sequence for downloading processor instruction from a 32-bit bus (PMODE=011, HBW=00) takes three cycles for every two words, as shown in Table 6-9.

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Table 6-9. Download Packing Sequence From a 32-Bit Bus

Transfer First Second Third Data Bus Pins 47-32 Word 1; bits 47-32 Word 2; bits 15-0 Word 2; bits 47-32 Data Bus Pins 31-16 Word 1; bits 31-16 Word 1; bits 15-0 Word 2; bits 31-16

For host transfers to or from the EPBx buffers, you must set the HBW bits in the SYSCON register to correspond to the external bus width. Note that the processor transfers 32-bit data on data bus lines DATA[47-16]. To transfer an odd number of instruction words, you must write a dummy access to flush the packing buffer and remove the unused word. For 32- to 48-bit host packing, the processor ignores the HMSWF bit in the SYSCON register and the MSWF bit in the DMACx control register. For non-host accesses (for example, DMA master mode accesses to external memory) the processor uses the MSWF bit for packing and ignores the value of HMSWF in SYSCON. 16-Bit Bus Downloading Table 6-10 and Table 6-11 show the packing sequence for downloading processor instructions from a 16-bit bus (PMODE=010, HBW=01). When interfacing to a host processor, the HMSWF bit determines whether the I/O processor packs to most significant 16-bit word first (=1) or least significant 16-bit word first (=0). Table 6-10. Download Packing sequence for 16-bit bus (MSW first)
Transfer First Second Third Data Bus Pins 31-16 Word 1; bits 47-32 Word 1; bits 31-16 Word 1; bits 15-0

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Table 6-11. Download Packing Sequence For 16-Bit Bus (LSW first)
Transfer First Second Third Data Bus Pins Word 1; bits 15-0 Word 1; bits 31-16 Word 1; bits 47-32

8-Bit Bus Downloading The packing sequence for downloading processor instructions from an 8-bit host (PMODE=101, HBW=10) takes six cycles for each word, as shown in Table 6-12 and Table 6-13. The HMSWF bit in SYSCON determines whether the I/O processor packs the most significant (=1) or least significant 8-bit word first (=0). Table 6-12. Download Packing Sequence From 8-Bit Bus (MSW first)
Transfer First Second Third Fourth Fifth Sixth Data Bus Pins 23-16 Word 1; bits 47-40 Word 1; bits 39-32 Word 1; bits 31-24 Word 1; bits 23-16 Word 1; bits 15-8 Word 1; bits 7-0

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Table 6-13. Download Packing Sequence From 8-bit Bus (LSW first)
Transfer First Second Third Fourth Fifth Sixth Data Bus Pins 23-16 Word 1; bits 7-0 Word 1; bits 15-8 Word 1; bits 23-16 Word 1; bits 31-24 Word 1; bits 39-32 Word 1; bits 47-40

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DMAC10 DMAC11 DMAC12 DMAC13

0x1c 0x1d 0x1e 0x1f

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PS
Ext Port EPBx FIFO Buffer Packing Status (read-only) 000=packing complete 001=1st stage pack/unpack 010=2 nd stage pack/unpack 011=3rd stage 100=5 th stage of 8 to 48 -bit packing 101=110=111=reserved

FS
Ext. Port FIFO Buffer Status (read-only) 00=buffer empty 01=buffer-not- full 10=buffer-not - empty 11=buffer full

INT32
Internal Memory 32 -bit Transfers Select 1=32-bit transfers/EPBx access width 0=64-bit transfers/EPBx access width

MAXBL
Maximum Burst Length Select 00=burst disabled 01=burst limit of 4 10=11=reserved 15 14 13 12 11 10 9 0 0 0 0 0 0 0

8 0

7 0

6 0

5 0

4 0

1 0

0 0

0 0

External Port Bus Priority Access 1=DSP asserts PA~ for external bus access 0=PA~ not asserted Flush EPBx FIFO Buffers & Status 1=flush EPBx External Handshake Mode Enable 1=enable, external devices to external memory 0=disable

PRIO

DEN
Ext. Port DMA Enable 1=enable, 0=disable

FLSH

CHEN
Ext. Port DMA Chaining Enable 1=enable, 0=disable

EXTERN

TRAN
Ext. Port EPBx Transmit/Rcv. Select 1=transmit data from intern memory 0=receive data from ext memory

INTIO
Single Word Interrupts for EPBx FIFO Buffers 1=enable single - wd non -DMA interrupt-driven xfers 0=disabled, FIFO fully enabled

DTYPE
EPBx FIFO Buffer Data Type Select 1=40/48 - bit, 3-column data 0=32/64 - bit, 4- column data

HSHAKE
EPBx DMA Handshake Mode Enable 1=enable, 0=disable

PMODE
Ext Port EPBx FIFO Packing Mode 000, 111= reserved 001=16 ext- to- 32/64 int 010=16 ext-to-48 int 011=32 ext- to -48 int 100=no pack (32 ext -to - 32/64 int) 101=8 ext-to -48 int 110=8 ext - to- 32/64int

MASTER
EPBx DMA Master Mode Enable 1=enable, 0=disable

MSWF
Most Significant Word First During Packing 1=enable, MSW first 0=disable, LSW first

Figure 6-8. DMAC Register

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Boot Memory DMA Mode

The BSO bit in the SYSCON register enables Boot Memory Select Override, a mode in which the I/O processor supports DMA access to boot memory space. When BSO is set, the processor uses the BMS select line (instead of MS3-0) to perform DMA channel 10 accesses to external memory. When reading from 8-bit boot memory space, the processor uses 8- to 48-bit packing. Programs most often use this feature to finish loading programs and data after the processor completes its automatic 256-instruction bootload.

External Port Buffer Modes

The HBW, HMSWF, PMODE, MSWF, and BHD bits in the SYSCON and DMACx registers select a buffers packing mode and disable buffer not-ready processor core stalls. The packing mode bits PMODE for processor and HBW for host select the external bus width and word size for transfers. Packed data or instructions are arranged in external memory according to the memory address that stems from their word size. For more information, see Memory Organization and Word Size on page 5-25. When data or instructions in external memory are not packed, the words are arranged in memory according to the external bus data alignment. This data alignment appears in Figure 7-1 on page 7-2. During reset, the default value for the PMODE bits in the DMAC10 register is 101 (8- to 48-bit packing for PROM/Host boot). When the packing mode (PMODE or HBW) is set for a 16-bit bus, programs should set up the 16-bit word order. The 16-bit word order bits ( MSWF for processor and HMSWF for host) control the order of 16-bit words being packed or unpacked in the 32-, 48-, or 64-bit word being transferred. If the MSWF or HMSWF bit is set (=1), the packing and unpacking is most significant 16-bit word first.

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In addition to selecting the packing mode for external port processor transfers, programs must indicate the type of data in the transfer, using the Data Type (DTYPE) bit. For more information, see External Port Channel Transfer Modes on page 6-46. The Buffer Hang Disable (BHD) bit lets the processor core proceed if the core tries to read from an empty EPBx, TXx, LBUFx or SPIRX buffer or tries to write to a full EPBx, RXx, LBUFx or SPITX buffer. The processor core still performs buffer accesses when buffer hang is disabled (FBHD=1). If the processor core attempts to read from an empty receive buffer, the core gets a repeat of the last value that was in the buffer. If the processor core attempts to write to a full buffer, the core overwrites the last value that was written to the buffer. Because these buffers are not initialized at reset, a read from a buffer that hasn't been filled since the reset returns an undefined value. If an external port buffers INTIO bit is set and DMA for that channel is not enabled, the external port channel is in single-word, interrupt-driven transfer mode. For more information, see Using I/O Processor Status on page 6-121.

External Port Channel Priority Modes

The DCPR and PRIO bits in the SYSCON and DMACx registers influence priority levels for an external port buffer and the external port in relation to external port DMA channels and external bus arbitration. For more information on prioritization operations, see Managing DMA Channel Priority on page 6-22. Priority for DMA requests from external port channels can be fixed or rotated. When the DMA Channel Priority Rotate (DCPR) bit is cleared, the lowest number external port channel has the highest priority, ranging from highest-priority channel 10 to lowest-priority channel 13.

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When the DCPR bit is set, the priority levels rotate. High priority shifts to a new channel after each packed single-word transfer. The I/O processor services a single-word transfer then rotates priority to the next higher numbered channel. Rotation continues until the I/O processor services all four external port channels. Figure 6-9 illustrates this process as described in the following steps: 1. At reset, external port channels have priority orderfrom high to low10, 11, 12, and 13. 2. The external port performs a single transfer on channel 11. 3. The I/O processor rotates channel priority, changing it to 12, 13, 10, and 11 (because rotating priority is enabled for this example, DCPR=1).
HIGHEST PRIORITY 10 HIGHEST PRIORITY 12

LOWEST PRIORITY

13

STEP 2

11

LOWEST PRIORITY

11

STEP 3

13

12

10

ONE TRANSFER OCCURS ON CHANNEL 11 (STEP 2), ROTATING CHANNEL 11'S PRIORITY TO THE LOWEST PRIORITY SLOT (STEP 3).

Figure 6-9. Rotating External Port DMA Channel Priority

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Even though the external port channel DMA priority can rotate, the interrupt priorities of all DMA channels are fixed. When external port DMA channel priority is fixed (DCPR=0), channel 10 has the highest priority, and channel 13 has the lowest priority. But, programs can redefine this priority order by assigning one of the other channels the highest priority. To change the fixed priority sequence of the external port DMA channels, a program could use the following procedure: 1. Disable all external port DMA channels except the one which is to have lowest priority. 2. Select rotating priority. 3. Cause at least one transfer to occur on the enabled channel. 4. Disable rotating priority and re-enable all of the external port DMA channels. After completing this procedure, the channel immediately after the selected channel has the highest fixed priority. In systems where multiple processors are using the external bus, the PRIO bit raises the priority level for external port DMA transfers. When a channels PRIO bit is set, the I/O processor asserts the Priority Access (PA) pin when that channel uses the external bus. The channel gets higher priority in bus arbitration, allowing the DMA to complete more quickly. Programs can also rotate priority between external port and link port DMA channels. For more information, see Link Port Channel Priority Modes on page 6-83.

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External Port Channel Transfer Modes

The DEN, CHEN, TRAN, and DTYPE bits in the DMACx register enable DMA and chained DMA and select the transfer direction and data type. The DMA enable (DEN) and Chained DMA enable (CHEN) bits work together to select an external port DMA channels transfer mode. Table 6-14 lists the possible modes. Table 6-14. External Port DMA Enable Modes
CHEN 0 0 1 DEN 0 1 0 DMA Enable Mode Description Channel disabled (chaining disabled, DMA disabled) Single DMA mode (chaining disabled, DMA enabled) Chain insertion mode (chaining enabled, DMA enabled, auto-chaining disabled); For more information, see Chaining DMA Processes on page 6-25. Chained DMA mode (chaining enabled, DMA enabled, auto-chaining enabled)

Because the external port is bidirectional, the I/O processor uses the Transmit select (TRAN) bit to determine the transfer direction (transmit or receive). Data flows from internal to external memory when in transmit mode. In transmit mode, the I/O processor fills the channels EPBx buffer with data from internal memory when the channels DEN bit is set. The Data Type (DTYPE) bit determines how the DMA channel accesses columns of internal memory. If DTYPE is set, the data is 40- or 48-bit words, and the I/O processor makes 3-column internal memory accesses. If DTYPE is cleared, the data is 32- or 64-bit words, and the I/O processor makes 4-column internal memory accesses. For more information, see Memory Organization and Word Size on page 5-25. The DTYPE for the transfer overrides the Internal Memory Data Width (IMDWx) setting for the internal memory block.

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External Port Channel Handshake Modes

The MASTER, HSHAKE, EXTERN, and HIDMA bits in the DMACx and WAIT registers select the channels DMA handshake and enable the hold cycles for host DMA. Table 6-15 summarizes the external port DMA modes. Table 6-16 shows how the MASTER, HSHAKE, and EXTERN bits work to select the channels DMA handshake mode. Table 6-15. External Port DMA Modes
Mode Slave Master Paced Master Handshake External Handshake Operation Internal Memory <--> EPBx Internal Memory <--> EPBx <-->External Memory Uses strobes and address, No DMAR and DMAG. Internal Memory <--> EPBx <-->External Memory Uses strobes and address, Uses DMAR , No DMAG. Internal Memory <--> EPBx <-->External Memory No strobes and address, Uses DMAR and DMAG. External Memory <--> External Device Uses strobes and address, Uses DMAR and DMAG.

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Table 6-16. External Port DMA Handshake Modes: DMACx MASTER (M), HSHAKE (H), and EXTERN (E) Bits
EHM 000 DMA Mode of Operation Slave Mode. The processor responds to the buffers internal memory transfer activity based on the buffer status in the FS field, generating a DMA request whenever the buffer is not empty (on receive) or is not full (on transmit). During transmit (TRAN=1), the processor fills the EPBx buffer with data from internal memory when the program enables the buffer (DEN=1). For more information, see Slave Mode on page 6-55. 001 Master Mode. The processor attempts the internal memory DMA transfers indicated by the DMA counter (CEPx) based on the buffer status in the FS field, making transfers whenever the buffer is not empty (on receive) or is not full (on transmit). Systems using Master Mode should de-assert corresponding DMA request inputs, de-asserting DMAR1 if channel 11 is in master mode and de-asserting DMAR2 if channel 12 is in master mode. For more information, see Master Mode on page 6-50. 010 Handshake Mode. When in this mode, the processor generates a DMA request whenever the external device asserts the DMARx pin, then the processor asserts the DMAGx pin, transferring the data (and de-asserting DMAGx) when the external devices de-asserts the DMARx pin. Note that this mode only applies to external port buffers EPB1 and EPB2 and DMA channels 11 and 12. For more information, see Handshake Mode on page 6-57. 011 Paced Master Mode. The processor attempts the internal memory DMA transfers indicated by the DMA counter (CEPx), making transfers based on external DMA request inputs. The processor generates a DMA request whenever the external device asserts the DMARx pin. The processor controls the data transfer using the RD or WR and ACK pins and by applying the selected number of waitstates. Note that this mode only applies to external port buffers EPB1 and EPB2 and DMA channels 11 and 12. For more information, see Paced Master Mode on page 6-54.

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Table 6-16. External Port DMA Handshake Modes: DMACx MASTER (M), HSHAKE (H), and EXTERN (E) Bits (Contd)
EHM 100 101 110 DMA Mode of Operation Reserved Reserved External-Handshake Mode. The processor responds to external memory DMA requests based on external DMA request inputs. This mode is identical to Handshake Mode, but applies to transfers between external memory and external devices. The processor generates a DMA request whenever the external device asserts the DMARx pin. The processor asserts the DMAGx pin, transferring the data (and de-asserting DMAGx) when the external devices de-asserts the DMARx pin. Note that this mode only applies to external port buffers EPB1 and EPB2 and DMA channels 11 and 12. For more information, see External-Handshake Mode on page 6-66. 111 Reserved

For the handshake and external-handshake modes shown in Table 6-16, programs can insert an added idle cycle after every memory access. The handshake and Idle for DMA (HIDMA) bit in the WAIT register enables this added cycle, which reduces bus contention from devices with slow three-state timing or long recovery times. Because external port DMA transfers can go between processor internal memory and external memory, the I/O processor must generate addresses for both memory spaces. The external port DMA channels have additional parameter registers (EIEPx, EMEPx, ECEPx) for external memory access. To support data packing options for external memory DMA transfers, the EIEPx and EMEPx registers can generate addresses at a different rate than the internal address registers (IIEPx and IMEPx). Figure 6-5 on page 6-23 shows that the I/O processor has separate address generators for internal and external addresses. For this reason, when packing is used for external

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memory DMA, the external count (ECEPx) register indicates the number of external port transfers, not the number of internal memory words being transferred. The DMA mode and other factors determine the size of the DMA data transfer on the external port. These other factors include the EIEPx, EMEPx, and ECEPx parameters; the PMODE, DTYPE, and MAXBL values in DMACx; and the transfer capacity available in the EPBx data buffer employed in the transfer. The internal I/O processor bus transfer size varies with the IIEPx, IMEPx, and CEPx parameters, and the PMODE, DMA mode, DTYPE, and INT32 values in DMACx. The following sections describe these DMA modes and transfer sizes in more detail: Master Mode on page 6-50 Paced Master Mode on page 6-54 Slave Mode on page 6-55 Handshake Mode on page 6-57 External-Handshake Mode on page 6-66 Master Mode When the MASTER bit is set (=1) and the EXTERN and HSHAKE bits are cleared (=0) in the channels DMACx register, the DMA channel is in master mode. A channel in this mode can independently initiate internal or external memory transfers. Master mode applies to all external port DMA channels: 10, 11, 12, and 13. When interfacing to SDRAM memory, only master mode DMA can be used for external port DMA transfers between SDRAM and internal memory. DMARx and DMAGx pins cannot be used to pace or handshake DMA transfers using SDRAM interface pins.

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To initiate a master mode DMA transfer, the processor sets up the channels parameter registers and sets the channels DMA enable (DEN) bit. A master mode DMA channel performing internal memory to external memory data transfer automatically performs enough transfers from internal memory to keep the EPBx buffer full. When the data transfer direction is external to internal, a master mode DMA channel also performs enough transfers from external memory to keep the EPBx buffer full. The I/O processor uses the EIEPx, EMEPx, and ECEPx registers to access external processor memory in master mode DMA. External Transfer Controls In Master Mode. In master mode, the processor determines the size of the external transfer from the channels PMODE bits and EIEPx, EMEPx, and ECEPx registers. Table 6-8 on page 6-37 shows the packing mode selected by the PMODE bits, and Table 6-17 shows the external transfer size in master mode that results from the combination of the PMODE bits. Table 6-17. Master Mode External Transfer Size
Transfer Size PMODE EIEP EMEP ECEP DTYPE EPBx Depth 1 32-bit 011, 100 X1 X X X >=1 16-bit 001, 010 X X # of 16-bit xfers X >=1 8-bit 110, 101 X X # of 8-bit xfers X >=1

An X in Table 6-17 indicates any supported value.

32-bit External Transfers. The processor performs 32-bit transfers when PMODE= 011 (32- to 48-bit internal), or 100 (32-bit external-to-32-bit/64-bit internal). In PMODE=011or 100, all data transfers across the upper word of the data bus (DATA47-16) are as indicated in

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Figure 7-1 on page 7-2. This mode supports all values of EIEPx, EMEPx, and ECEPx. ECEPx contains the number of 32-bit words to transfer. There must be at least one 32-bit EPBx FIFO entry available to support the 32-bit external transfer. 16-bit External Transfers. The processor performs 16-bit transfers when PMODE=001 (16-bit external-to-32/64-bit internal) or 010 (16-bit external to 48-bit internal). This mode supports all values of EIEPx, EMEPx, and ECEPx. The value ECEPx is programmed to the number of 16-bit words to transfer. There must be at least one 32-bit EPBx FIFO entry available to support the 16-bit external transfer. In PMODE=001, or 010, all data transfers across DATA31-16 as indicated in Figure 7-1 on page 7-2. 8-bit External Transfers. The processor performs 8-bit transfers when (8-bit external to 32/64-bit internal) or 101 (8-bit external to 48-bit internal). This mode supports all values of EIEPx, EMEPx, and ECEPx. The value ECEPx is programmed to be the number of 8-bit words to transfer. There must be at least one 32-bit EPBx FIFO entry available to support the 8-bit external transfer. In PMODE=110 or 101, all data transfers across DATA23-16 as indicated in Figure 7-1 on page 7-2.
PMODE=110

Internal Address/Transfer Size Generation. In master mode, the processor determines the size of the internal transfer from the channels PMODE bits and IIEPx, IMEPx, and CEPx registers. Table 6-7 on page 6-36 shows the packing mode selected by the PMODE bits, and Table 6-18 shows the internal transfer size in master mode that results from the combination of the PMODE bits. Table 6-18. Master Mode Internal Transfer Size Determination
Transfer Size PMODE IIEPx IMEPx 64-bit1 001, 100, 110 depends on IM2 -1 or 1 48-bit 010, 011, 101 X3 X 32-bit 001, 100, 110 X X

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Table 6-18. Master Mode Internal Transfer Size Determination (Contd)

CEPx DTYPE EPBx Depth INT32 1 2 3 even # of 32-bit words 0 >1 0 # of 48-bit words 1 >1 0 X 0 >=1 0 or 1

Including packed instructions. If IMEPx is 1 for increment, IIEPx must be an even, 64-bit aligned Normal word address. If IMEPx is -1 for decrement, IIEPx must be an odd, Normal word address. X indicates any supported value.

64-bit Internal Transfers. To enable internal 64-bit transfers and increment the internal IIEPx pointer, programs must set IIEPx to match the IMEPx selection as shown in Table 6-18. CEPx contains the number of 32-bit words to transfer, and should be set to an even number of 32-bit words. The processor decrements CEPx by 2 for each 64-bit transfer. For 64-bit transfers, PMODE must be set to 001 (16-bit-to-32/64-bit internal), 100 (32-bit external-to-32/64-bit internal) or 110 (8-bit external-to-32/64-bit internal). DTYPE and INT32 must be cleared. There must be at least two 32-bit EPBx FIFO entries available to support the 64-bit external transfer. 48-bit Internal Transfers. The processor can perform 48-bit internal transfers for DMA of packed or unpacked 48-bit instructions. Many applications can use internal 64-bit transfer for 48-bit instructions. This technique can provide greater throughput than 48-bit internal transfers. In either of the 48-bit internal transfer modes in Table 6-18 (PMODE=101 and DTYPE=1 or PMODE=010 or 011 and DTYPE=0), the processor accesses the memory using instruction alignment (3-column read or write) for the EPBx buffer. In this case, IIEPx points to 48-bit words, and CEPx counts the number of 48-bit internal transfers.

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32-bit Internal Transfers. The processor performs according to the conditions in Table 6-18. Under these additional conditions, the processor performs 32-bit transfers instead of 64- or 48-bit transfers: PMODE= 001 (16-bit external to 32-bit internal), or 100 (32-bit external to 32-bit internal), and IIEPx is not aligned to a 64-bit boundary, or IMEPx is < -1, or > 1, or CEPx is < 2, or EPBx depth < 2, or INT32 = 1, and DTYPE=0. Paced Master Mode When the MASTER and HSHAKE bits are set (=1) and the EXTERN bit is cleared (=0) in the channels DMACx register, the DMA channel is in Paced Master mode. A channel in this mode can independently initiate internal or external memory transfers. Paced Master mode applies only to external port DMA channels 11 and 12. In Paced Master mode, the processor has the same control for address generation and transfer size as in master mode. For more information, see Master Mode on page 6-50. The difference between these modes is that in Paced Master mode external transfers are controlled and initiated (paced) by the DMARx signal as in handshake mode. For more information, see Handshake Mode on page 6-57. The processor responds to the DMARx request only with the RD, or WR strobes, depending on direction and data alignment. DMAGx is not asserted in Paced Master mode. This method lets the processor share the same buffer between the I/O processor and processor core without external gating. Paced Master mode accesses can be extended by the ACK input, by waitstates programmed in the WAIT register, and by holding the DMARx input low.

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Slave Mode When the MASTER, HSHAKE, and EXTERN bits in the channels DMACx register are cleared (=0), the DMA channel is in slave mode. A channel in this mode cannot independently initiate external memory transfers. To initiate a slave mode DMA transfer, an external device must read or write the channels EPBx buffer. A slave mode DMA channel performing internal to external data transfer automatically performs enough transfers from internal memory to keep the EPBx buffer full. When the data transfer direction is external to internal, a slave mode DMA channel does not initiate any internal DMA transfers until the external device writes data to the channels EPBx buffer. Note that the I/O processor does not use the EIEPx, EMEPx, and ECEPx registers in slave mode DMA The following sequence describes a typical external to internal slave mode DMA operation where an external device transfers a block of data into the processors internal memory: 1. The external device initializes the channel by writing the DMA channels parameter registers (IIEPx, IMEPx, and CEPx) and DMACx control register. 2. The external device begins writing data to the EPBx buffer. 3. The EPBx buffer detects that data is present and asserts an internal DMA request to the I/O processor. 4. The I/O processor grants the request and performs the internal DMA transfer, emptying the EPBx buffer FIFO. If the internal DMA transfer is held off, the external device can continue writing to the EPBx buffer because of its eight-deep FIFO. When the EPBx FIFO becomes full, the processor holds off the external device with the ACK signal (for synchronous accesses) or with the REDY signal (for asynchro-

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nous, host-driven accesses). This hold-off state continues until the I/O processor finishes the internal DMA transfer, freeing space in the EPBx buffer. The following sequence describes a typical internal to external slave mode DMA operation where an external device transfers a block of data from the processors internal memory: 1. The external device writes the DMA channels parameter registers (IIEPx, IMEPx, and CEPx) and DMACx control register, initializing the channel and automatically asserting an internal DMA request to the I/O processor. 2. The I/O processor grants the request and performs the internal DMA transfer, filling the EPBx buffers FIFO. 3. The external device begins reading data from the EPBx buffer. 4. The EPBx buffer detects that there is room in the buffer (it is now partially empty) and asserts another internal DMA request to the I/O processor, continuing the process. If the internal DMA transfers cannot fill the EPBx FIFO buffer at the same rate as the external device empties it, the processor holds off the external device with the ACK signal (for synchronous accesses) or with the REDY signal (for asynchronous, host-driven accesses) until valid data can be transferred to the EPBx buffer. The processor only deasserts the ACK (or REDY) signal when the EPBx FIFO buffer (or pad data buffer) is full during a write. The ACK (or REDY) signal remains asserted at the end of a completed block transfer if the EPBx buffer is not full. For reads, the processor deasserts the ACK (or REDY) signal for each read to handle the latency of the read versus posting the write to a buffer.

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In slave mode, the processor determines the size of the transfer based on the setting of channels PMODE bits. Table 6-19 shows the transfer size in slave mode that results from the PMODE bits and Table 6-7 on page 6-36 shows the packing mode selected by the PMODE bits. Table 6-19. Slave Mode Transfer Size Determination
Transfer Size (externalinternal) PMODE DTYPE 1 2 32-bit 32/64-bit 100 0 32-bit 48-bit 011 1 16-bit 32/64-bit1 001 0 16-bit 48-bit1 010 1 8-bit 32/64-bit2 110 0 8-bit 48-bit2 101 1

External device must be connected to DATA[31:16] External device must be connected to DATA[23:16]

Handshake Mode When the MASTER and EXTERN bits are cleared (=0) and the HSHAKE bit is set (=1) in the channels DMACx register, the DMA channel is in handshake mode. A channel in this mode cannot independently initiate external memory transfers. Note that handshake mode only applies to DMA channels 11 and 12. To initiate a handshake mode DMA transfer, an external device must assert an external DMA request, asserting DMAR1 for access to EPB1 or DMAR2 for access to EPB2. The buffers pass these request to the I/O processor, which prioritizes these requests with other internal DMA requests. When the external DMA request has the highest priority, the I/O processor asserts an external DMA grant, asserting DMAG1 for EPB1 or DMAG2 for EPB2. The grant signals the external device to read or write the EPBx buffer. A handshake mode DMA channel performing internal to external data transfer automatically performs enough transfers from internal memory to keep the EPBx buffer full. When the data transfer direction is external to

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internal, a handshake mode DMA channel does not initiate any internal DMA transfers until the external devices writes data to the channels EPBx buffer. The I/O processor does not use the EIEPx or EMEPx registers in handshake mode DMA. It uses the ECEPx registers. Other than the DMARx/DMAGx handshake, handshake mode DMA operations follow almost the same process as slave mode DMA operations. The exception is that in handshake mode DMAs from internal to external memory the external device must load the channels ECEPx register with the number of external bus transfers. In handshake mode, the processor determines the size of the transfer from the channels parameter registers and PMODE bits. Table 6-7 on page 6-36 shows the packing mode selected by the PMODE bits, and Table 6-20 shows the transfer size in handshake mode that results from the combination of the read and write signals and PMODE bits. Table 6-20. Handshake Mode Transfer Size Determination
Transfer Size (externalinternal) PMODE IIEPx IMEPx CEPx ECEPx DTYPE 1 2 3 4 32-bit 32/64-bit1 100 X4 X # of 32-bit words # of 32-bit words 0 32-bit 48-bit2 011 X X # of 32-bit words 6/4 * CEPx 1 16-bit 32/64-bit2 001 X X # of 16-bit words 2 * CEPx 0 16-bit 48-bit2 010 X X # of 16-bit words 3 * CEPx 1 8-bit 32/64-bit3 110 X X # of 8-bit words 4 * CEPx 0 8-bit 48-bit2 101 X X # of 8-bit words 6 * CEPx 1

External device must be connected to the upper half of the data bus (Data[47:16]) External device must be connected to Data[16:31]) External device must be connected to Data[16:23]) X indicates any legal value

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DMA transfers are supported at the full system CLKIN/CLKOUT rates of 50MHz. However, full bandwidth at 2:1 core clock (CCLK) to CLKIN/CLKOUT ratio is not possible. Non synchronous timing specifications limit throughput for three DMA handshake modes: paced master mode, handshake mode and external handshake mode. The sampling rate of the DMARx signal by the internal circuitry of the ADSP-21161 processor prohibits maximum throughput at a CCLK to CLKIN/CLKOUT ratio of 2:1. For handshake mode DMA, the processor does not assert the MS3-0 memory select lines (the address strobes). For information on DMARx/DMAGx handshake timing, see Figure 6-10. to CLKIN ratios of 3:1 and 4:1 with CLKDBL =1 and CCLK to CLKIN ratios of 4:1, 6:1 and 8:1 with CLKDBL =0 support full speed throughput at the CLKIN frequency. If the maximum DMARx/DMAGx throughput at 50MHz is needed, synchronize the assertions and deassertions of DMARx with respect to CLKOUT. Refer to the ADSP-21161N DSP Microcomputer Data Sheet for specific timing information.
CCLK
DMAR rising edge allows 1st DMAG to complete DMAG has a wait state because DMAR remained asserted in the cycle prior to the DMAG assertion

CLKIN

1st DMA Request

2nd DMA request

DMARx

DMAGx

DATA47-16 Bus Transition Cycle (If not bus master)

data valid

data valid

data valid

data valid

DMA device must place data in buffer prior to DMAG falling edge if no wait state

DMA device need not provide data until this cycle if wait state

Figure 6-10. Handshake DMA Timing (Asynchronous Requests)

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The I/O processor uses the rising and falling edges of DMARx in the DMARx/ DMAGx handshake as prompts for DMA operations. On the falling edge of DMARx, the edge signals the I/O processor to begin a DMA access. On the rising edge of DMARx, the edge signals the I/O processor to complete the DMA access. The following sequence describes the process for requesting access to an EPBx buffer in handshake mode: 1. The external device asserts the buffers DMARx signal, placing an external DMA request for access to the EPBx buffer. 2. The EPBx buffer detects the falling edge of the DMARx signal and passes the external DMA request to the I/O processor, synchronizing the DMA operation with the processors system clock. To be recognized in a particular cycle, the DMARx low transition must meet the signal setup time from the processor data sheet. If the transition is slower than the setup time, the signal may not take effect until the following cycle. 3. The I/O processor prioritizes the external DMA request with other internal DMA requests. If the processor is not already bus master, the processor arbitrates for the external bus when the external DMA request has the highest priority, unless the EPBx buffer is blocked. If the EPBx buffer is full during a write or empty during a read, the buffer is blocked. The processor does not begin external bus arbitration until the I/O processor services the EPBx buffer, returning it to the unblocked state empty for writing or full for reading. 4. The processor becomes bus master and asserts DMAGx. The processor keeps DMAGx asserted until the cycle after the external device deasserts DMARx. By holding DMARx asserted, the external device holds the processor until the external device is ready to pro-

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ceed. If the external device does not need to extend the DMA grant cycle, the external device can deassert DMARx immediately (not waiting for DMAGx), providing the DMARx assertion time meets the timing requirements from the processor data sheet. The responding DMAGx in this case is a short pulse, and the processor only uses the external bus for one cycle. The I/O processor has a three-cycle DMA pipeline and a seven-deep external request counter. The I/O processors DMA pipeline is similar to the program sequencers fetchdecodeexecute instruction pipeline. The I/O processor processes the DMA pipeline in the following stages: It recognizes the DMA request and arbitrates internal DMA priority during the DMA fetch cycle. It generates the DMA address and arbitrates external bus access during the DMA decode cycle. It transfers DMA data during the DMA execute cycle. Because the I/O processor has a three-cycle DMA pipeline, there is a minimum delay of three cycles before the processor asserts DMAGx. This delay is in addition to any delay from internal DMA arbitration, so the external device must not assume that the DMA grant can arrive within two cycles even if higher priority DMA operations are disabled and the external bus is available for the transfer. The I/O processors external request counter increments each time the external device asserts DMARx and decrements each time the processor replies by asserting DMAGx. The external request counter records up to seven requests, so the external device can make up to seven requests before the first one has been serviced.

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If the processor cannot immediately service the DMA requests in the external request counter, the processor services the requests on a prioritized basis. The external DMA device is responsible for keeping track of requests, monitoring grants, and pipelining the data when operating at full speed. If the external device makes more than seven DMARx without receiving a grant, the delayed grant causes unpredictable results. The processor only asserts DMAGx for the number of DMARx requests indicated by the external request counter. If the external devices make more requests than the count indicates, the processor DMAGx assertions cannot match the number of external device requests. To clear this mismatch, programs can clear the buffer and the external request counter using the flush bit (FLSH) in the channels DMACx register. To prevent holding off the processor, the external device must service the processors data requirements when it asserts the DMAGx grant signal. The external device should immediately supply data for writes to the processor or immediately accept data on reads from the processor. External interfaces can handle this I/O by placing the data in an external FIFO. When performing DMA operations at the full CLKIN speed of the processor, the system may need a three-deep external FIFO to handle the latency between request and grant. Programs on the external device can optimize operation of this FIFO by issuing three requests rapidly and making the next requests conditional on when the processor issues a grant. The external devices must follow the conditions in Figure 6-11 when enabling or disabling handshake mode for an external port DMA channel: The processor ignores a disabled (transitioning from disabled to enabled) DMA channels DMARx and DMAGx pins and ignores internal DMARx assertions for up to two processor core clock cycles after the instruction that enables the channel in handshake mode.

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The external devices must maintain DMARx deasserted (kept high, not low or changing) during the instruction that enables DMA in handshake mode. Before using the channel for the first time, programs flush the DMA channel, asserting the FLSH bit in the DMACx control register. This action is not required during chain insertion. The processor deasserts DMAGx if a program disables the channel while DMARx and DMAGx are asserted (=0). This action clears the channels active status bit, avoiding a potential deadlock condition.

CCLK
(core clock)

DMARx

DMAR must be kept HI during this instruction

DMARx ignored

Executing Instruction

Instruction enabling DMA by setting DEN=1 and HSHAKE=1 in DMAC11 or DMAC12

Instruction

Instruction

Figure 6-11. DMARx Delay After Enabling Handshake DMA ADSP-21161 processors in a multiprocessing cluster may share a DMAGx signal, because only the bus master drives DMAGx. On the bus slaves, DMAGx is three-stated. This state eliminates the need for external gating if more than one processor or the host needs to drive the DMA buffer. Systems may need a pullup resistor on this line if the host is not connected to the pin or does not drive it when it acquires the bus. DMAGx has the same timing and transitions as the RD and WR strobes in asynchronous access mode. For more information, see Bus Arbitration Protocol on page 7-95. DMAGx responds to the SBTS and HBR signals in the same way as the read and write strobes.

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DMA Handshake Idle Cycle

Idle cycles can be inserted during DMA handshaking to interface with slower devices. Normally a bus idle cycle occurs when an asynchronous read is followed by an immediate write to an external memory bank or when crossing bank boundary. During this idle cycle, the address and data lines continue to drive the previous value. RD, WR and DMAGx lines deassert. If the asynchronous read is immediately followed by a write, the processor recognizes that a write request is pending during the idle cycle. Therefore, the MSx lines do not deassert during the idle cycle. Instead, the lines are driven with their previous value (asserted). Idle cycles can be inserted after every memory access by setting the HIDMA bit in the WAIT register for DMAs with handshaking. For a handshake mode DMA transfer, the MSx lines are never asserted. When an external handshake mode DMA is enabled with a bus idle cycle inserted in between the transfers, the MSx lines do not deassert during the bus idle cycle if the I/O processor recognizes a pending DMARx request. If there are no pending DMARx requests, MSx lines do deassert. Figure 6-12 shows an external handshake mode DMA transfer on channel 11 with three DMAR1 pulses asserted. The HIDMA bit is set in the WAIT register in order to insert bus idle cycles between two handshake transfers. The first data transfer is to location 0x255000 in bank 0 and the second transfer is to location 0x255001. An idle cycle is inserted between the two transfers. Note that the first two DMAR1 pulses are sequential. Therefore, during this idle cycle, the I/O processor recognizes that there is a DMAR1 request pending. As a result of the pending request, the MS0 line is not deasserted. The third data transfer is to location 0x255002. Again, an idle cycle is inserted between the second and third transfers. However, the third DMA transfer request happens after some time has transpired and following the 2nd DMAR1 pulse. In this case, the I/O processor recognizes that there are

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CLKIN

DMAR1

DMAG1

MS0

RD

WR

ADDR[23:0]

0x255000

0x255001

0x255002

DATA[47:16]

DATA VALID

DATA VALID

DATA VALID

Figure 6-12. DMA Handshake Idle Cycle no more DMAR1 requests pending. Therefore, during the idle cycle between the second and third transfers, the MS0 line goes high. MS0 goes low again when the 3rd data transfer occurs. Systems must be evaluated to determine if the idle cycle during a external handshake DMA with an activated MSx line has an adverse impact on the chip selected memory devices or peripherals. The RD, WR, and DMAG strobes are inactive during the idle cycle, and therefore the MSx lines being activated should not affect interconnection to other devices as long as RD and WR remain inactive. Otherwise, an idle cycle insertion between DMA handshake transfers cannot be used.

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External-Handshake Mode External-handshake mode is identical to handshake mode, except that external-handshake mode transfers data between external memory and an external device. This section describes the differences between handshake mode and external-handshake mode. For more information, see Handshake Mode on page 6-57. When the MASTER bit is cleared (=0) and the HSHAKE and EXTERN bits are set (=1) in the channels DMACx register, the DMA channel is in external-handshake mode. A channel in this mode cannot independently initiate external memory transfers. Like handshake mode, external-handshake mode only applies to DMA channels 11 and 12. Do not use external handshake mode DMA on an external memory bank that has SDRAM mapped and connected to its MSx line. To initiate an external-handshake mode DMA transfer, an external device must assert an external DMA request, asserting DMAR1 for access to DMA channel 11or DMAR2 for access to DMA channel 12. The channels pass these request to the I/O processor, which prioritizes these requests with other internal DMA requests. When the external DMA request has the highest priority, the I/O processor asserts an external DMA grant, asserting DMAG1 for channel 11 or DMAG2 for channel 12. The grant signals the external device to read or write the external bus. An external-handshake mode DMA channel performing external to external data transfer automatically generates external memory addresses and strobes for transfers between external memory and the external device. Unlike handshake mode, the I/O processor must use the EIEPx, EMEPx, and ECEPx registers in external-handshake mode DMA. Also unlike handshake mode, the data for DMA channels 11 and 12 does not pass through the EPB1 or EPB2 buffers.

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During external-handshake mode transfers, the I/O processor generates external memory access cycles. DMARx and DMAGx operate the same as in handshake mode, but the processor also outputs addresses, MS3-0 memory selects, and RD and WR strobes, and responds to ACK. On external memory writes, the processor asserts DMAGx until the external device releases the ACK line or any of the processor waitstates expire. The external memory access by the external devices responds as if the processor core were making the access. For more information, see External Port on page 7-1. Because the I/O processor accesses external memory in external-handshake mode, programs must load the DMA channels EIEPx, EMEPx, and ECEPx parameter registers and the DMAC10 or DMAC11 PMODE bits. These settings let the I/O processor generate the external memory addresses and word count. External-handshake mode does not support chained DMA interrupts. Because no internal DMA transfers occur in external-handshake mode, the PCI bit in the channels CPEPx register cannot disable the DMA interrupt. Programs must use the IMASK register to mask this interrupt. In external-handshake mode, the processor does not perform packing. The processor does determine the size of the transfer from the channels parameter registers, PMODE bits. Table 6-21 shows the transfer size in external handshake mode that results from the combination of the read and write signals and PMODE bits. For 32-bit memory transfers to an external device, PMODE must be set to the no packing mode (=100) in the DMACx register.

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Setting Up External Port DMA

The method for setting up and starting an external port DMA sequence varies slightly with the selection of transfer and DMA handshake for the channel. For more information on transfer modes, see External Port Channel Transfer Modes on page 6-46. For more information on DMA handshake modes, seeExternal Port Channel Handshake Modes on page 6-47. Table 6-21. External Handshake Mode Transfer Size
Transfer Size (memorydevice) PMODE EIx EMx ECx DTYPE 32-bit memory32-bit device1 100 X2 X X 0

1 External device must be connected to the upper half of the data bus (Data[47:16]) 2 X indicates any legal value

The following sequence describes a typical external to internal DMA operation where an external device transfers a block of data into the processors internal memory: 1. The processor or host (depending on the mode) writes to the DMA channels parameter registers (IIEPx, IMEPx, and CEPx) and the DMACx register, initializing the channel for receive ( TRAN=0). 2. The processor or host (depending on the mode) sets the channels DEN bit to 1 enabling the DMA process.

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3. The external device begins writing data to the EPBx buffer through the external port. 4. The EPBx buffer detects data is present and asserts an internal DMA request to the I/O processor. 5. The I/O processor grants the request and performs the internal DMA transfer, emptying the EPBx buffer FIFO. The following sequence describes a typical internal to external DMA operation where an external device transfers a block of data from the processors internal memory: 1. The processor or host (depending on the mode) writes the DMA channels parameter registers (IIEPx, IMEPx, and CEPx) and the DMACx register, initializing the channel for transmit (TRAN=1). 2. The processor or host (depending on the mode) sets the channels DEN bit to 1 enabling the DMA process. Because this is a transmit, setting DEN automatically asserts an internal DMA request to the I/O processor. 3. The I/O processor grants the request and performs the internal DMA transfer, filling the EPBx buffers FIFO. The processor may signal the start of this transfer depending on the mode. 4. The external device begins reading data from the EPBx buffer through the external port. The processor may signal the start of this transfer depending on the mode. 5. The EPBx buffer detects that there is room in the buffer because it is now partially empty and asserts another internal DMA request to the I/O processor, continuing the process.

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Bootloading Through The External Port

The processor can boot from an EPROM or host processor through the external port. The DMAC10 control register is initialized for booting in each case. Each booting mode packs boot data into 48-bit instructions. EPROM and host boot use channel 10 of the I/O processors DMA controller to transfer the instructions to internal memory. For EPROM booting, the processor reads data from an 8-bit external EPROM. For host booting, the processor accepts data from a 8-, 16- or 32-bit host microprocessor (or other external device). It is important to note that DMA channel differences between the ADSP-21161 and previous SHARC processors (ADSP-2106x) introduce some booting differences. Even with these differences, the ADSP-21161 supports the same boot capability and configuration as the ADSP-2106x processors. The DMACx register default values differ because the ADSP-21161 has additional parameters and different DMA channel assignments. The EPROM and Host boot modes use EPB0, DMA channel 10. Like the ADSP-2106x, the ADSP-21161 boots from DATA23-16. For EPROM or host booting the ADSP-21161, the Program sequencer automatically unmasks the DMA channel 10 channel interrupt, initializing the IMASK register to 0x00008003. The processor determines the booting mode at reset from the EBOOT, LBOOT, and BMS pin inputs. When EBOOT=1 and LBOOT=0, the processor boots from an EPROM through the external port and uses BMS as the memory select output. When EBOOT=0, LBOOT=0, and BMS =1, the processor

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boots from a host through the external port. For a list showing how to select different boot modes, see the Boot Memory Select pin description in the table Table 13-11 on page 13-72. When using any of the power-up booting modes, address 0x0004 0004 should not contain a valid instruction since it is not executed during the booting sequence. A NOP or IDLE instruction should be placed at this location. In EPROM booting through the external port, an 8-bit wide boot EPROM must be connected to data bus pins 23-16 (DATA23-16). The lowest address pins of the processor should be connected to the EPROMs address lines. The EPROMs chip select should be connected to BMS and its output enable should be connected to RD. In a multiprocessor system, the BMS output is only driven by the ADSP-21161 bus master. This allows wire-ORing of multiple BMS signals for a single common boot EPROM. Systems can boot any number of ADSP-21161s from a single EPROM using the same code for each processor or differing code for each. During reset, the processors ACK line is internally pulled high with a 20k equivalent resistor and is held high with an internal keeper latch. It is not necessary to use an external pullup resistor on the ACK line during booting or at any other time. After the boot process loads 256 words into memory locations 0x4 0000 through 0x4 00FF, the processor begins executing instructions. Because most processor programs require more than 256 words of instructions and initialization data, the 256 words typically serve as a loading routine for the application. Analog Devices supplies loading routines (loader kernels) that can load entire programs. These routines come with the development tools. For more information on loader kernels, see the development tools documentation.

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Host Processor Booting When host booting mode is configured, the ADSP-21161 enters slave mode after reset and waits for the host to download the boot program. After reset the ADSP-21161 processor goes into an idle state, identical to that caused by the IDLE instruction, with the program counter (PC) set to address 0x0004 0004. The parameter registers for the external port DMA channel 10 are initialized as shown in Table 6-22. Table 6-22. DMA Channel 10 Parameter Register Initialization for Host Booting
Parameter Register IIEP0 IMEP0 CEP0 CPEP0 GPEP0 EIEP0 EMEP0 ECEP0 Initialization Value 0x0004 0000 uninitialized (increment by 1 is automatic) 0x0100 (256 instruction words) uninitialized uninitialized uninitialized uninitialized uninitialized

Table 6-22 shows how the DMA channel 10 parameter registers are initialized at reset for host booting.The count register (CEP0) is initialized to 0x0100 for transferring 256 words to internal memory. The DMAC10 control register is initialized to 0x00000161. The default value sets up external port transfers as follows:
DEN

= 1, external port enabled = 0, LSW first

MSWF

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PMODE DTYPE

= 101, 8- to 48-bit packing = 1, three-column data

The external port DMA Channel 10 (DMAC10) becomes active following reset; it is initialized to 0x0000 0161. This enables the external port DMA and selects DTYPE for instruction words. The packing mode bits (PMODE) in the DMACx register are set to 8- to 48-bit packing. The host bus width (HBW) and word order (HMSWF) bits must be programmed in the SYSCON register. For each 48-bit word of boot image, an 8-bit host performs the following sequence of operations: 1. Assert HBR and CS. 2. Wait for HBG. After the host receives the host bus grant signal back from the ADSP-21161 processor, it can start downloading instructions or it can change the reset initialization conditions of the ADSP-21161 processor by writing to any of the IOP control registers. 3. Write the six subwords to the external port buffer, EPB0. This buffer corresponds to DMA channel 10. The host must use data pins DATA23-16. 4. Deassert CS and HBR. The processor samples the inactive HBR and allows a host transition cycle. The processor can access the bus for external memory initialization. For 16 and 32-bit host bus widths, the HBW bits in the SYSCON register must be modified. The host must use the data lines as follows: 16-bit host bus width = 3 subwords using data pins DATA31-16 32-bit host bus width = 2 subwords using data pins DATA47-16

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PROM Booting When the EPROM boot mode is configured, the external port DMA Channel 10 (DMAC10) becomes active following reset; it is initialized to 0000 0561. This enables the external port DMA and selects DTYPE for instruction words. 8- to 48-bit packing is forced with least-significant-word first. The RBWS and RBAM fields of the WAIT register are initialized to perform asynchronous access and to generate seven wait states (eight cycles total) for the EPROM access in external memory space. Note that wait states defined for boot memory are applied to BMS-asserted accesses. Table 6-23 shows how the DMA channel 10 parameter registers are initialized at reset for EPROM. The count register (CEP0) is initialized to 0x0100 for transferring 256 words to internal memory. The external count register (ECEP0), which is used when external addresses are generated by the DMA controller, is initialized to 0x0600 (for example, 0x0100 words with six bytes per word). The DMAC10 control register is initialized to 0000 0561. The default value sets up external port transfers as follows:
DEN

= 1, external port enabled = 0, LSW first = 101, 8- to 48-bit packing = 1, three-column data

MSWF

PMODE DTYPE

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Table 6-23. DMA Channel 10 Parameter Register Initialization for EPROM Booting
Parameter Register IIEP0 IMEP0 CEP0 CPEP0 GPEP0 EIEP0 EMEP0 ECEP0 Initialization Value 0x0004 0000 uninitialized (increment by 1 is automatic) 0x0100 (256 instruction words) uninitialized uninitialized 0x0080 0000 uninitialized (increment by 1 is automatic) 0x0600 (256 words x 6 bytes/word)

At system start-up, when the processors RESET input goes inactive, the following sequence occurs: 1. The processor goes into an idle state, identical to that caused by the IDLE instruction. The program counter (PC) is set to address 0x0004 0004. 2. The DMA parameter registers for channel 10 are initialized as shown in Table 6-23. 3.
BMS

becomes the boot EPROM chip select.

4. 8-bit Master Mode DMA transfers from EPROM to internal memory begin, on the external port data bus lines 23-16. 5. The external address lines (ADDR23-0) start at 0x0080 0000 and increment after each access. 6. The RD strobe asserts as in a normal memory access with seven wait states (eight cycles).

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The processors DMA controller reads the 8-bit EPROM words, packs them into 48-bit instruction words, and transfers them to internal memory until 256 words have been loaded. The EPROM is automatically selected by the BMS pin; other memory select pins are disabled. The DMA external count register (ECEP0) decrements after each EPROM transfer. When ECEP0 reaches zero, the following wake-up sequence occurs: 1. The DMA transfers stop. 2. The External Port DMA Channel 10 interrupt (EP0I) is activated. 3. is deactivated and normal external memory selects are activated.
BMS

4. The processor vectors to the EP0I interrupt vector at 0x0004 0050. At this point the processor has completed its booting mode and is executing instructions normally. The first instruction at the EP0I interrupt vector location, address 0x0004 0050, should be an RTI (Return from Interrupt). This process returns execution to the reset routine at location 0x0004 0005 where normal program execution can resume. After reaching this point, a program can write a different service routine at the EP0I vector location 0x0004 0050.

External Port DMA Programming Examples

This section provides two programming examples written for the ADSP-21161 processor. The example shown in Listing 6-1 demonstrates how the I/O processor uses DMA to read from the external port receive buffer and write to the external port transmit buffer after an interrupt. The example shown in Listing 6-2 demonstrates how the I/O processor uses DMA chaining to read from the external port receive buffer and write to the external port transmit buffer.

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Listing 6-1. External Port DMA Example

/*_____________________________________________________________ ADSP-21161 Internal-to-External Memory (External Port) DMA Example This example shows an internal to external memory no packing 32-bit DMA transfer. ______________________________________________________________*/ #include "def21161.h" #define N 8

.GLOBALinit_int_to_ext_memory_DMA; .SECTION/DM dm_data;

.VAR source[N]= 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888; .SECTION/DM .VAR dest[8]; /*___________start of DMA initialization routine___________________*/ .SECTION/PMpm_code; init_int_to_ext_memory_DMA: segsdram;

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r0=0;dm(DMAC10)=r0; r0=source;dm(IIEP0) = r0; r0=1;dm(IMEP0)=r0; r0=@source;dm(CEP0)=r0;

/* Clear DMA Control Register */ /* Write source address to IIEP0 */ /* Write internal address modify to IMEP0 */ /* Load internal DMA 10 Count Register */

r0=dest; dm(EIEP0)=r0; r0=1; dm(EMEP0)=r0; r0=@dest;dm(ECEP0)=r0;

/* Write destination address to EIEP0 register */ /* Write external address modify to EMEP0 */ /* Load external DMA 10 Count Register */

/* master mode, no packing mode [PMODE=100] */ /* transmit data from int>ext, enable EP DMA */ /* DMAC10=b#00000000000000000000010100000101; */ ustat1 = 0x00000000; bit set ustat1 MASTER | PMODE4 | TRAN | DEN; dm(DMAC10)=ustat1; bit set imask EP0I; /* Unmask external port buffer 0 DMA interrupt */ rts;

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Listing 6-2. External Port Chained DMA Example

/*__________________________________________________________ ADSP-21161 Internal-to-External Memory (External Port) Chained DMA Example This example shows an internal to external memory, no packing 32-bit chained DMA transfer. _____________________________________________________________*/ #include "def21161.h" #define N 8

.GLOBALint_to_ext_memory_chainDMA; .SECTION/DM 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888; .VAR tcb[8] = N, /* ECx */ 1, /* EMx */ 0, /* EIx */ 0, /* GPx */ 0, /* CPx */ N, /* Cx */ 1, /* IMx */ 0; /* IIx */ dm_data;

.VAR source[N]= 0x11111111,

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.SECTION/DM .VAR dest[8];

segsdram;

/*________start of DMA initialization routine__________*/ .SECTION/PMpm_code; int_to_ext_memory_chainDMA: r0=source; dm(tcb + 7) = r0; r0=dest; dm(tcb + 2) = r0; r0=tcb + 7; r1= b#10000000000000000000; r0=r0 or r1; /* set PCI Bit */ dm(tcb + 4) = r0; /* Write tcb address to CP slot in tcb */ r0=0; dm(DMAC10)=r0; dm(DMAC10)=r0; */ r0=tcb + 7; dm(CPEP0) =r0; bit set imask EP0I; rts; /* Load CP register*/ /* Clear DMA Control Register */ /* dma enable, Chain enable,int>ext, master mode r0=b#00000000000000000000010100000111; /* Write Dest1 address to EI slot in tcb_a */ /* Write Source1 address to II tcb_a */

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Link Port DMA

There are two link ports DMA channels available on the ADSP-21161: channels 8 and 9. These two channels are shared with the SPI port. Channel 8 is assigned to link port 0 while channel 9 is assigned to link port 1. These bidirectional ports transfer data to other processors or link port peripherals. The processor support a number of DMA modes for link port DMA. The following sections describe typical link port DMA processes: Setting Up Link Port DMA on page 6-86 Bootloading Through The Link Port on page 6-88 Link Port Buffer Modes on page 6-83 Link Port Channel Priority Modes on page 6-83 Link Port Channel Transfer Modes on page 6-85

Link Port Registers

The SYSCON and LCTL registers control the link ports operating modes for the I/O processor. Table A-18 on page A-60 lists all the bits in SYSCON. Table A-25 on page A-93 lists all the bits in LCTL.

The following bits control link port I/O processor modes. The control bits in the LCTL registers have a one cycle effect latency. Programs should not modify an active DMA channels bits in the LCTL register other than to disable the channel by clearing the LxDEN bit. For information on verifying a channels status with the DMASTAT register, see Using I/O Processor Status on page 6-121.

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Some other bits in LCTL setup non-DMA link port features. For information on these features, see Setting Link Port Modes on page 9-5. Link Port DMA Channel Priority Rotation Enable. SYSCON Bit 20 (LDCPR). This bit enables (rotates if set, =1) or disables (fixed if cleared, =0) priority rotation between link port DMA channels 8 and 9. LinkExternal Port DMA Channel Priority Rotation Enable. SYSCON Bit 21 (PRROT). This bit enables (rotates if set, =1) or disables (fixed if cleared, =0) priority rotation between link port DMA channels 8 and 9 and external port DMA channels 10 to 13. Link Port assignment for LBUFx. LCTL Bits 9-0 and 23-22 correspond to link buffer 0. LCTL Bits 19-10 and 25-24 correspond to link buffer 1. Link Buffer Enable. LCTL Bits 0 and 10 (LxEN). This bit enables (if set, =1) or disables (if cleared, =0) the corresponding link buffer (LBUFx). Link Buffer DMA Enable. LCTL Bits 1 and 11 (LxDEN). This bit enables (if set, =1) or disables (if cleared, =0) DMA transfers for the corresponding link buffer (LBUFx). Link Buffer DMA Chaining Enable. LCTL Bits 2 and 12 (LxCHEN). This bit enables (if set, =1) or disables (if cleared, =0) DMA chaining for the corresponding link buffer (LBUFx). Link Buffer Transfer Direction. LCTL Bits 3 and 13 (LxTRAN). This bit selects the transfer direction (transmit if set, =1) (receive if cleared, =0) for the corresponding link buffer (LBUFx).

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Link Buffer Extended Word Size. LCTL Bits 4 and 14 (LxEXT). This bit selects the transfer extended word size (48-bit if set, =1) (32-bit if cleared, =0) for the corresponding link buffer (LBUFx). Programs must not change a buffers LxEXT setting while the buffer is enabled.

Link Port Buffer Modes

The LABx bits in the LCTL register assign link ports to link buffers and enable link buffers. Bit 19 LAB0 enables link buffer 0 while Bit 20 LAB1 enables link buffer 1. To enable a link buffer, a program sets the buffers LxEN bit in LCTL. To disable a link buffer, a program clears the buffers LxEN bit in LCTL. The LCTL bit descriptions appear in Link Port Buffer Control Registers (LCTL) Bit Definitions on page A-93. When the processor disables the buffer (LxEN transitions from high to low), the processor clears the corresponding LxSTATx and LRERRx bits.

Link Port Channel Priority Modes

The LDCPR and PRROT bits in the SYSCON register select priority levels for the link port buffers in relation to the priority of other link port buffer and the other I/O ports. The Link Port DMA Channel Priority Rotation Enable (LDCPR) bit enables (rotates if set, =1) or disables (fixed if cleared, =0) priority rotation between link port DMA channels 8 and 9. Rotating priority distributes link port DMA channels access to the I/O bus. When channel priority is rotating, the processor arbitrates I/O bus access between contending link port DMA channels, forcing the channels to take turns. When channel priorities fixed, the lower numbered link port DMA channel always has priority over the higher numbered channel when contending for I/O bus access.

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When LDCPR is set (rotating priority), high priority shifts to a new channel after each single-word transfer. The following steps illustrate this process: 1. At reset, link port channels have priority orderfrom high to low. 2. The link port performs a single transfer on channel 8. 3. The I/O processor rotates channel priority, changing it from 8 to 9. Even though the link port channel DMA priority can rotate, the interrupt priorities of all DMA channels are fixed. When a program uses fixed priority for the link port DMA channels, the I/O processor assigns the higher priority to channel 8 and the lower priority to channel 9. For a list of all channel assignments, see Table 6-1 on page 6-13. Programs can change the fixed priority order, assigning a different channel to the highest priority. The following example shows how to change the fixed priority sequence of the link port DMA channels: 1. Disable all link port DMA channels except the one immediately above the channel that is to have highest priority. 2. Select rotating priority by setting the LDCPR bit. 3. Cause at least one transfer to occur on the enabled channel. 4. Disable rotating priority and re-enable all of the link port DMA channels. The channel immediately after the selected channel now has the highest fixed priority.

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Programs can also rotate priority between the link port and external port DMA channels. The DMA Channel Priority Rotation Enable (PRROT) bit enables (rotates if set, =1) or disables (fixed if cleared, =0) priority rotation between link port DMA channels 8 and 9 and external port DMA channels 10 to 13. Rotating priority distributes link port and external port DMA channels access to the I/O bus. When channel priority is rotating, the processor arbitrates I/O bus access between contending link port and external port DMA channels, forcing the channel types to take turns. When channel priority is fixed, any link port DMA channel always has priority over any external port DMA channel when contending for I/O bus access.

Link Port Channel Transfer Modes

The LxDEN, LxCHEN, LxTRAN, and LxEXT bits in the LCTL register enable link port DMA, and chained DMA and select the transfer direction and format. The link DMA enable (LxDEN) and link Chained DMA enable (LxCHEN) bits work together to select a link port DMA channels transfer mode. Table 6-24 lists the modes. Table 6-24. Link Port DMA Enable Modes
LxCHEN 0 0 1 LxDEN 0 1 0 DMA Enable Mode Description Channel disabled (chaining disabled, DMA disabled) Single DMA mode (chaining disabled, DMA enabled) Chain insertion mode (chaining enabled, DMA enabled, auto-chaining disabled); For more information, see Chaining DMA Processes on page 6-25. Chained DMA mode (chaining enabled, DMA enabled, auto-chaining enabled)

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Because link ports are bidirectional, the I/O processor uses the link Transmit select (LxTRAN) bit to determine the transfer direction (transmit or receive). Data flows from internal to external memory when in transmit mode. In transmit mode, the I/O processor fills the channels LBUFx buffer when the channels LxDEN bit is set. The Link Extended Word Size (LxEXT) bit determines how the DMA channel accesses columns of internal memory. If LxEXT is set, the data is 40- or 48-bit words, and the I/O processor makes 3-column internal memory accesses. If LxEXT is cleared, the data is 32-bit words, and the I/O processor makes 2-column internal memory accesses. For more information, see Memory Organization and Word Size on page 5-25. The LxEXT for the transfer overrides the Internal Memory Data Width (IMDWx) setting for the internal memory block.

Setting Up Link Port DMA

The method for setting up and starting an link port DMA sequence varies slightly with the transfer mode for the channel. For more information on DMA transfer modes, see Link Port Channel Transfer Modes on page 6-85. The following sequence describes a typical external to internal DMA operation where an external device transfers a block of data into the processors internal memory using a link port. 1. The processor or host (depending on the mode) assigns the DMA channels link buffer to a link port using the channels LABx bits in the LCTL register. 2. The processor or host (depending on the mode) enables the DMA channels link buffer, setting the buffers LxEN bit in the channels LCTL register. The processor or host selects a words size (32- or 40/48-bits) using the LxEXT in the channels LCTL register.

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3. The processor or host (depending on the mode) writes the DMA channels parameter registers (IILBx, IMLBx, and CLBx) and LCTL control register, initializing the channel for receive (LxTRAN=0). 4. The processor or host (depending on the mode) sets (=1) the channels LxDEN bit enabling the DMA process. 5. The external device begins writing data to the LBUFx buffer through the link port. 6. The LBUFx buffer detects data is present and asserts an internal DMA request to the I/O processor. 7. The I/O processor grants the request and performs the internal DMA transfer, emptying the LBUFx buffer FIFO. In general, the following sequence describes a typical internal to external DMA operation where an external device transfers a block of data from the processors internal memory using a link port: 1. The processor or host (depending on the mode) assigns the DMA channels link buffer to a link port using the channels LABx bits in the LCTL register. 2. The processor or host (depending on the mode) enables the DMA channels link buffer, setting the buffers LxEN bit in the channels LCTL register. The processor or host selects a words size (32- or 40/48-bits) using the LxEXT in the channels LCTL register. 3. The processor or host (depending on the mode) writes the DMA channels parameter registers (IILBx, IMLBx, and CLBx) and LCTL control register, initializing the channel for transmit (LxTRAN=1). 4. The processor or host (depending on the mode) sets (=1) the channels LxDEN bit enabling the DMA process. Because this is a transmit, setting LxDEN automatically asserts an internal DMA request to the I/O processor.

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5. The I/O processor grants the request and performs the internal DMA transfer, filling the LBUFx buffers FIFO. 6. The external device begins reading data from the LBUFx buffer (through the link port). 7. The LBUFx buffer detects that there is room in the buffer (it is now partially empty) and asserts another internal DMA request to the I/O processor, continuing the process.

Bootloading Through The Link Port

One of the processors booting modes is booting the processor through the link port. Link port booting uses DMA channel 8 of the I/O processor to transfer the instructions to internal memory. In this boot mode, the processor receives 4-bit wide data in link buffer 0. After the boot process loads 256 words into memory locations 0x40000 through 0x400FF, the processor begins executing instructions. Because most processor programs require more than 256 words of instructions and initialization data, the 256 words typically serve as a loading routine for the application. Analog Devices supplies loading routines (loader kernels) that load an entire program through the selected port. These routines come with the development tools. For more information on loader kernels, see the development tools documentation. It is important to note that DMA channel differences between the ADSP-21161 and previous SHARC processors (ADSP-2106x) introduce some booting differences. Even with these differences, the ADSP-21161 supports the same boot capability and configuration as the ADSP-2106x processors. For link booting the ADSP-21161, the program sequencer automatically unmasks the DMA channel 8 interrupt, initializing the LIRPTL register to 0x00010000 and IMASK register to 0x00004003.

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The processor determines the booting mode at reset from the EBOOT, LBOOT, and BMS pin inputs. When EBOOT=0, LBOOT=1, and BMS=1, the processor boots through the link port. For a list showing how to select different boot modes, see the Boot Memory Select pin description in the table Booting Modes on page 13-72. When using any of the power-up booting modes, address 0x0004 0004 should not contain a valid instruction since it is not executed during the booting sequence. A NOP or IDLE instruction should be placed at this location. In link port booting, the processor gets boot data from another processors link port or 4-bit wide external device after system powerup. The external device must provide a clock signal to the link port assigned to link buffer 0. The clock can be any frequency, up to a maximum of the processor clock frequency. The clocks falling edges strobe the data into the link port. The most significant 4-bit nibble of the 48-bit instruction must be downloaded first. Table 6-25 shows how the DMA channel 8 parameter registers are initialized at reset for EPROM booting. The count register (CLB0) is initialized to 0x0100 for transferring 256 words to internal memory. The LCTL register is overridden during link port booting to allow link buffer 0 to receive 48-bit data. Table 6-25. DMA Channel 8 Parameter Register Initialization For Link Port Booting
Parameter Register IILB0 IMLB0 CLB0 Initialization Value 0x0004 0000 uninitialized (increment by 1 is automatic) 0x0100 (256 instruction words)

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Link Port DMA

Table 6-25. DMA Channel 8 Parameter Register Initialization For Link Port Booting (Contd)
Parameter Register CPLB0 GPLB0 Initialization Value uninitialized uninitialized

In systems where multiple processors are not connected by the parallel external bus, booting can be accomplished from a single source through the link ports. To simultaneously boot all of the processors, a parallel common connection should be made to link buffer 0 on each of the processors. If only a daisy chain connection exists between the processors link ports, then each processor can boot the next one in turn. Link buffer 0 must always be used for booting.

Link Port DMA Programming Examples

This section provides two programming examples written for the ADSP-21161 processor. The example shown in Listing 6-3 demonstrates how the I/O processor uses DMA chaining to read from the link port receive buffer and write to the link port transmit buffer. The example shown in Listing 6-4 demonstrates how the I/O processor uses DMA to read from the link port receive buffer and write to the link port transmit buffer after an interrupt.

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Listing 6-3. DMA-Chained Link Loopback Example

/*____________ ADSP-21161 DMA-Chained LINK Loopback Example This example shows an internally looped-back link port 32-bit transfer. DMA is used to transfer the data to and from the buffers. Loopback is achieved by assigning the transmit and receive link buffers to the same port (Port 0). #include "def21161.h" #define N 8 .section/pm seg_rth; /*Reset vector from ldf file*/ nop; jump start; .section/dm seg_dmda;/*Data section from ldf file*/ .var source[N]= 0X11111111, 0X22222222, 0X33333333, 0X44444444, 0X55555555, 0X66666666, 0X77777777, 0X88888888; .var dest[N]; .var txtcb_source[8]=0,0,0,0,0,N,1,source; /*DMA TCB settings*/ .var rxtcb_dest[8]=0,0,0,0,0,N,1,dest; /*DMA TCB settings*/ /*_____________________Main Routine________________________*/ .section/pm seg_pmco;/*Main code section described in .ldf file*/ start: ustat1 = dm(SYSCON); bit clr ustat1 BHD; dm(SYSCON) = ustat1; imask = 0; irptl = 0; bit set imask LPISUMI; bit set lirptl LP1MSK; bit set mode1 IRPTEN; /*Enable Link port interrupts*/ /*Enable Link port 1 interrupt*/ /*Enable global interrupts*/ /*Clear IMASK and IRPTL registers*/ /*Disable Buffer Hang*/

____________________*/

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Link Port DMA

r0 = 0; dm(LCTL) = r0; ustat1=dm(LCTL); /*LCTL REGISTER-->LBUF0=TX, LBUF1=RX, 2x CLK RATE, LBUF 0 & 1 ENABLED, LBUF 0 & 1 -> PORT 0 DMA Enabled, DMA Chain Enabled*/ bit clr ustat1 L0TRAN | LAB0 | LAB1 | L0CLKD0 | L1CLKD0; bit set ustat1 L1TRAN | L1EN | L0EN | L0CLKD1 | L1CLKD1 | L0DEN | L1DEN | L0CHEN | L1CHEN; dm(LCTL)=ustat1; r1 = 0x0003FFFF; r0 = txtcb_source + 7; r0 = r1 AND r0; r0 = BSET r0 BY 18; dm(txtcb_source + 4) = r0; dm(CPLB1) = r0; /* CPX register mask */ /* Get DMA chaining int. mem. ptr with tx buf address */ /* Mask the pointer */ /* Set the pci bit */ /* Write DMA transmit block chain pointer to TCB buffer */ /* Transmit blk chain ptr, init.LP1 DMA transfers */ r0 = rxtcb_dest + 7; r0 = r1 AND r0; /* Mask the pointer */ r0 = BSET r0 BY 18; /* Set the pci bit */ dm(rxtcb_dest + 4) = r0; dm(CPLB0) = r0; /* Write DMA receive block chain pointer to TCB buffer*/ /* Receive block chain pointer, Initiate LP0 DMA transfers */ wait: idle; jump wait;

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Listing 6-4. Interrupt DMA-Driven Link Loopback Example

/*__________________________________________________________ ADSP-21161 Interrupt DMA-Driven LINK Loopback Example This example shows an internally looped-back link port 32-bit transfer. DMA is used to write to and read from the buffers. Loopback is achieved by assigning the transmit and receive link buffers to the same port. (Port 0) ___________________________________________________________*/ #include "def21161.h" #define N 8 .section/pm seg_rth; /*Reset vector from ldf file*/ nop; jump start; .section/dm seg_dmda; /*Data segment section from ldf file*/

.var source[N]= 0X11111111, 0X22222222, 0X33333333, 0X44444444, 0X55555555, 0X66666666, 0X77777777, 0X88888888; .var dest[N]; .section/pm lp1i_svc; /*Link Port 1 Vector from ldf file*/

jump lpISR1;rti;rti;rti; .section/pm lp0i_svc; jump lpISR0;rti;rti;rti; /*Link Port 0 Vector from ldf file*/

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Link Port DMA

/*_____________________Main Routine________________________*/ .section/pm seg_pmco;/*Main code section from ldf file*/ start: r0 = 0; DM(LCTL) = r0; r0=source; dm(IILB0)=r0; r0=dest; dm(IILB1)=r0; buffer*/ r0=@source; dm(CLB0)=r0; dm(CLB1)=r0; r0=1; dm(IMLB0)=r0; dm(IMLB1)=r0; ustat1 = dm(SYSCON); bit clr ustat1 BHD; dm(SYSCON) = ustat1; imask = 0; lirptl = 0; /*Enable Global,Link Port and Link Port Buffer 1 interrupt */ bit set imask LPISUMI; bit set lirptl LP1MSK | LP0MSK; bit set mode1 IRPTEN | CBUFEN; ustat1=dm(LCTL); /*LCTL Register-->LBUF1=TX, LBUF0=RX, 1/4x CCLK RATE, LBUF 0 & 1 ENABLED, LBUF 0 & 1 -> PORT 0 Link buffer 0 & 1 DMA Enabled*/ /*Disable Buffer Hang*/ /*Set DMA modify (stride) to 1*/ /*Set DMA count to length of data buffers*/ /*Set DMA rx index to start of destination /*Set DMA tx index to start of source buffer*/

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bit clr ustat1 L1TRAN | L0CLKD0 | L1CLKD0 | LAB0 | LAB1; bit set ustat1 L0TRAN | L1EN | L0EN | L0CLKD1 | L1CLKD1 | L0DEN | L1DEN; dm(LCTL)=ustat1; wait: idle; jump wait; lpISR0: rti; lpISR1: rti;

Serial Port DMA

Serial Port DMA provides a mechanism for receiving or transmitting an entire block of serial data before an interrupt is generated. The processor's on-chip DMA controller handles DMA transfers, allowing the processor core to continue running until the entire block of data is transmitted or received. There are eight serial port channels available on the ADSP-21161 for DMA transfers: channels 0 through 7. Each of the serial port channels can be configured to transmit or receive data. The A path for each sport allows expansion or compression of data. The processor supports a number of DMA modes for serial port DMA. The following sections describe typical serial port DMA processes: Setting Up Serial Port DMA on page 6-100 Serial Port Buffer Modes on page 6-97 Serial Port Channel Priority Modes on page 6-99 Serial Port Channel Transfer Modes on page 6-99

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Serial Port DMA

Serial Port Registers

The SPCTLx registers control the serial port operating mode for the I/O processor. Figure 6-13 lists all the bits in SPCTLx. The following bits control serial port I/O processor modes. The control bits in the SPCTLx registers have a one cycle effect latency. Programs should not modify an active DMA channels bits in the SPCTLx registers; other than to disable the channel by clearing the SDEN bit. To change an inactive serial ports operating mode, programs should clear a serial ports control register before writing new settings to the control register. For information on verifying a channels status with the DMASTAT register, see Using I/O Processor Status on page 6-121. Some other bits in SPCTLx setup non-DMA serial port features. For information on these features, see Serial Port DMA on page 6-95. Serial Port Enable. SPCTLx Bit 0 (SPEN_A) and Bit 24 (SPEN_B). These bits enables (if set, =1) or disables (if cleared, =0) the corresponding serial port. SPEN_A corresponds to the A channel (companding). SPEN_B corresponds to the B channel (no companding). You can enable one or both of these bits. Data Type Select. SPCTLx Bits 2-1 (DTYPE). These bits select the data type formatting for normal and multi-channel reception as follows: (normal/multichannel= format) 00/x0=Right-justify and zero-fill unused MSBs, 01/x1=Right-justify and sign-extend unused MSBs, 10/0x=Compand using -law, 11/1x=Compand using A-law. Serial Word Endian Select. SPCTLx Bit 3 (SENDN). This bit selects little endian words (LSB first, if set, =1) or big endian words (MSB first, if cleared, =0). Serial Word Length Select. SPCTLx Bits 8-4 (SLEN). These bits select the word length 1 in bits. Word sizes can be from 3-bit (SLEN=2) to 32-bit (SLEN=31). 6-96 ADSP-21161 SHARC Processor Hardware Reference

I/O Processor

16-bit to 32-bit Word Packing Enable. SPCTLx Bit 9 (PACK). This bit enables (if set, =1) or disables (if cleared, =0) 16- to 32-bit word packing. Serial Port DMA Enable. SPCTLx Bit 18 (SDEN_A) and Bit 20 (SDEN_B).These bits enable (if set, =1) or disable (if cleared, =0) the serial ports A or B channel DMA. Serial Port DMA Chaining Enable. SPCTLx Bit 19 (SCHEN_A) and Bit 21 (SCHEN_B). These bits enable (if set, =1) or disables (if cleared, =0) the serial ports A or B channel DMA chaining.

Serial Port Buffer Modes

The SPEN, SENDN, SLEN, and PACK bits in the SPCTLx registers enable the serial port and select the transfer format. To enable a serial port transmit or receive buffer, a program sets the buffers SPEN bit in the SPCTLx register. To disable a serial port transmit or receive buffer, a program clears the buffers SPEN_A or SPEN_B bit in the SPCTLx register. If a serial port buffer is enabled and DMA for that channel is not enabled, the serial port is in single-word, interrupt-driven transfer mode. For more information, see Using I/O Processor Status on page 6-121. Each serial port buffer allows independent settings for the three transfer format features: bit order, word length, and word packing. For transferring little endian words (LSB first, if set, =1) to or from little endian devices, the serial port buffers have a Serial Word Endian Select (SENDN) bit. This bit selects little endian words (LSB first, if set, =1) or big endian words (MSB first, if cleared, =0). The Serial Word Length Select (SLEN) bit field selects the transfer word length (-1) in bits. Word sizes can be from 3-bit (SLEN=2) to 32-bit (SLEN=31).

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S P C T L0 (0 x0 1 c0 ) S P C T L1 (0 x0 1 e 0 ) S P C T L2 (0 x0 1 d 0 ) S P C T L3 (0 x0 1 f0 )
DXS_A
D X A D a ta B u ffe r S ta tu s 1 1 = fu ll, 1 0 = p a rtia lly fu ll, 0 0 = e m p ty

D S P S e ria l M o d e
31 30 29 28 27 26 25 24 23 22 21 20 0 0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 0 0 0 0

LFS

A ctiv e L o w F S 0 =a c tive h ig h , 1 =a c tive lo w

LAFS
L a te F S 0 = e a rly F S , 1 =la te F S

D ER R _A
D X A E rro r S ta tu s (s tic k y) D D IR = 1 ,tra n sm it u n d e rflo w s ta tu s D D IR = 0 , re ce ive o v e rflo w sta tu s

SDEN_A
S P O R T D M A e n a b le A c h a n n e l 1 =e n a b le , 0 =d isa b le

D X S_B *
D X B D a ta B u ffe r S ta tu s 1 1 = fu ll, 1 0 = p a rtia lly fu ll ,0 0 =e m p ty

SCHEN_A
D M A c h a in in g e n a b le A c h a n n e l 1 =e n a b le , 0 =d isa b le

DE R R_B *
D X B E rro r S ta tu s (s tic k y)

SDEN_B
S P O R T D M A e n a b le B c h a n n e l 1 =e n a b le , 0 =d isa b le

D D IR **
D a ta D ire c tio n C o n tro l 1 = A c tiv e T ra n s m it B u ffe rs T X n B /T X n A 0 = E n a b le R e ce ive B u ffe rs R X n B /R X n A

SCHEN_B
D M A c h a in in g e n a b le B c h a n n e l 1 =e n a b le , 0 =d isa b le

S PE N _B
S P O R T E n a b le B 1 =e n a b le , 0 =d isa b le * S ta tu s is R e a d -o n ly ** D o n o t re a d /w rite fro m /to in a c tive R X n /T X n b u ffe rs 15 14 0 0 13 12 0 0 11 10 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

FS_B O TH
1 = is su e W S o n ly if d a ta is p re s e n t in b o th T x 0 = is su e W S if d a ta is p re s e n t in e ith e r T x

D IT F S
D a ta In d e p e n d e n t tx F S (if D D IR = 1 ) 1 =d a ta in d e p e n d e n t, 0 = d a ta d e p e n d e n t

SP E N_A
S P O R T E n a b le A (1 = e n a b le , 0 = d is a b le )

IF S
In te rn a lly ge n e ra te d FS 1 = in te rn a l F S , 0 =e x te rn a l F S

DTYPE
D a ta typ e 0 0 = righ t-ju stify; fill M S B w ith 0 s 0 1 = righ t-ju stify; s ig n e x te n d M S B 1 0 = c o m p a n d m u -la w 1 1 = c o m p a n d A -la w

FS R
F S re qu ire m e n t 1 = F S re qu ire d , 0 = FS n o t re q u ire d

SENDN
E n d ia n w o rd fo rm a t 0 = M S B firs t, 1 = L S B firs t

CKRE
C lo ck e d ge fo r d a ta F ra m e S yn c s a m p lin g o r d rivin g (1 =ris in g e d g e , 0 = fa llin g e d g e )

SLEN
S e ria l W o rd L e n g th -1

OPMODE
S P O R T O p e ra tio n M o d e 0 =D S P s e ria l m o d e /m u ltich a n n e l m o d e 1 =I 2 S m o d e

PACK
1 6 /3 2 p a c k in g 1 = p a c kin g, 0 = n o p a c k in g

IC L K

In te rn a lly ge n e ra te d S C L K 1 = in te rn a l c lo c k, 0 = e x te rn a l c lo c k

Figure 6-13. SPCTLx Register DSP Serial Mode If the serial word length is 16-bits or smaller, the serial port can pack two of these words into the serial port buffer. The 16-bit to 32-bit word Packing Enable (PACK) bit can enable this packing because the I/O processor performs 32-bit transfers between the serial port buffers and processor memory.

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In addition to selecting the endian, length, and packing modes for serial port processor transfers, programs must indicate the type of data in the transfer, using the Data Type (DTYPE) bit. For more information, see Serial Port Channel Transfer Modes on page 6-99.

Serial Port Channel Priority Modes

Serial port DMA transfers always take priority over external port, SPI port, or link port DMA transfers. For more information on prioritization operations, see Managing DMA Channel Priority on page 6-22.

Serial Port Channel Transfer Modes

The SDEN_A, SDEN_B, SCHEN_A, SCHEN_B, and DTYPE bits in the SPCTLx register enable serial port DMA, chained DMA, and select the format. The DMA enable (SDEN) and Chained DMA enable (SCHEN) bits work together to select a serial port DMA channels transfer mode. Table 6-26 lists the modes. Table 6-26. Serial Port DMA Enable Modes
SCHEN A or B 0 0 1 SDEN A or B 0 1 0 DMA Enable Mode Description Channel disabled (chaining disabled, DMA disabled) Single DMA mode (chaining disabled, DMA enabled) Chain insertion mode (chaining enabled, DMA enabled, auto-chaining disabled); For more information, see Chaining DMA Processes on page 6-25. Chained DMA mode (chaining enabled, DMA enabled, auto-chaining enabled)

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Serial Port DMA

Because serial port buffers are bidirectional, the I/O processor does not need an indicator to determine the transfer direction (transmit or receive). Data flows from internal to external devices using a transmit (TXx) buffer. When transmitting serial data as DMA, the I/O processor fills the channels TXx buffer when the channels SDEN bit is set.

Setting Up Serial Port DMA

The method for setting up and starting an serial port DMA sequence varies slightly with the transfer mode for the channel. For more information on DMA transfer modes, see Serial Port Channel Transfer Modes on page 6-99. In general, the following sequence describes a typical external to internal DMA operation where an external device transfers a block of data into the processors internal memory using a serial port: 1. The processor or host (depending on the mode) enables the DMA channels serial port, setting the ports SPEN_A or SPEN_B bit in the ports SPCTLx register. The processor or host selects a words size using the DTYPE in the ports SPCTLx register. When you clear DDIR(= 0), the program configures SPORT A and B data pins as receivers and activates the RXA and RXB registers. 2. The processor or host (depending on the mode) writes to the DMA channels parameter registers (IIx, IMx, and Cx) and SPCTLx control register, initializing the channel for receive. 3. The processor or host (depending on the mode) sets (=1) the channels SDEN_A or SDEN_B bit enabling the DMA process. 4. The external device begins writing data to the RXx buffer through the serial port.

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5. The RXx buffer detects data is present and asserts an internal DMA request to the I/O processor. 6. The I/O processor grants the request and performs the internal DMA transfer, emptying the RXx buffer. In general, the following sequence describes a typical internal to external DMA operation where an external device transfers a block of data from the processors internal memory using a serial port: 1. The processor or host (depending on the mode) enables the DMA channels serial port, setting the ports SPEN bit in the ports SPCTLx register. The processor or host selects a words size using the DTYPE in the ports SPCTLx register. The DDIR bit is set (=1) to enable the serial interface as a transmitter. The program activates the TX buffers allowing data to transmit out of the SPORT A and B data pins. 2. The processor or host (depending on the mode) writes to the DMA channels parameter registers (IIx, IMx, and Cx) and SPCTLx control register, initializing the channel for transmit. 3. The processor or host (depending on the mode) sets (=1) the channels SDEN bit enabling the DMA process. Because this is a transmit, setting SDEN_A or SDEN_B automatically asserts an internal DMA request to the I/O processor. 4. The I/O processor grants the request and performs the internal DMA transfer, filling the TXx buffer. 5. The external device begins reading data from the TXx buffer through the serial port. 6. The TXx buffer detects that there is room in the buffer because it is now partially empty and asserts another internal DMA request to the I/O processor, continuing the process.

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Serial Port DMA

When programming the serial port channel (A or B) as a transmitter only the corresponding TXA and TXB become active, while the receive buffers RXA and RXB remain inactive. Similarly, when the SPORT channel A and B is programmed as receive only the corresponding RX0A and RX0B is activated. When performing core driven transfers, programs must write to the proper buffer depending on the direction setting in the SPCTL register (DDIR). For DMA-driven transfers the serial port logic performs the data transfer from internal memory to/from the appropriate buffer depending on the DDIR bit setting. If the inactive SPORT data buffers are read or written to by core while the port is already being enabled, the SPORT does not operate correctly. If, for example, the SPORT is programmed to be a transmitter, while at the same time, the core reads from the receive buffer of the same SPORT, the core hangs, just as it would if it was reading an empty buffer which was currently active. This locks up the core permanently until the SPORT is reset. The program must set the direction bit along with serial port enable and DMA enable bits before initiating any operations on the SPORT data buffers. If the processor operates on the inactive transmit or receive buffers while the SPORT is enabled it can cause unpredictable results.

SPORT DMA Programming Examples

This section provides two programming examples written for the ADSP-21161 processor. The example shown in Listing 6-5 demonstrates how the I/O processor uses DMA chaining to read from the SPORT receive buffer and write to the SPORT transmit buffer. The example shown in Listing 6-6 demonstrates how the I/O processor uses DMA to read from the SPORT receive buffer and write to the SPORT transmit buffer.

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Listing 6-5. DMA-Chained Sport Loopback Example

/*___________________________________________________________ ADSP-21161 DMA-Chained SPORT Loopback Example This example shows an internally looped-back SPORT 32-bit transfer. The transfer buffer (TX2A) and receive buffer (RX0A) are both handled via DMA chaining. ___________________________________________________________*/ #include "def21161.h" #define N 8 .section/pm seg_rth; nop; jump start; .section/dm seg_dmda; .var source[N]= 0X11111111, 0X22222222, 0X33333333, 0X44444444, 0X55555555, 0X66666666, 0X77777777, 0X88888888; .var dest[N]; .var txtcb[8] = 0,0,0,0,0,N,1,source; .var rxtcb[8] = 0,0,0,0,0,N,1,dest; .section/pm sp0i_svc; jump IRQ; rti;rti;rti; .section/pm sp2i_svc; jump IRQ; rti;rti;rti; /*-----------------Main Routine----------------------------*/ .section/pm seg_pmco; start: /*DMA tcb settings*/ /*Reset vector from ldf file*/

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Serial Port DMA

ustat3=dm(SYSCON); bit clr ustat3 BHD; dm(SYSCON)=ustat3; bit set imask SP0I |SP2I; bit set mode1 CBUFEN | IRPTEN; /*Unmask SPORT 0 & 2 Interrupts*/ /*Enable Circ Buffers & Interupts*/ r0 = 0x00001000; /*Set the SPL bit in the SPxxMCTL register to enable loopback*/ dm(SP02MCTL)=r0; r0 = 0x0; dm(DIV0) = r0; r0 = 0x000c21f1; /*Set bits SPEN_A, SLEN0-4, FSR--enable the A channel, set the word length to 32 bits, require frame synch, and enable DMA and DMA Chaining.*/ dm(SPCTL0)=r0; r0=0x00270004; /*TCLKDIV=[FCCLK(96Mhz)/2xFSCLK((19.2Mhz)]-1=0x0004*/ /*TFSDIV=[FSCLK(9.6Mhz)/TFS(.24Mhz)]-1=0x0027*/ dm(DIV2)=r0; r0=0x20c65f1; /*Set bits SPEN_A, SLEN0-4, ICLK, IFS, FSR, DDIR--enable the A channel, set the word length to 32 bits, generate internal framesynch and clock, require frame synch, set for transmit, and enable DMA and DMA Chaining.*/ dm(SPCTL2)=r0; r1=0x0003FFFF; /*CPx register mask*/ /*Externally generated clock and framesync*/ /*Disable Buffer Hang*/

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r0=txtcb+7; r0=r1 AND r0; r0= BSET r0 by 18; dm(txtcb+4)=r0; dm(CP2A)=r0;

/*Get DMA chaining memory pntr containing tx buff address*/ /*Mask the pointer*/ /*Set the PCI bit*/ /*Write DMA transmit block chain pntr to TCB buffer*/ /*Transmit block chain pointer, init SP2 DMA transfers*/

r0=rxtcb+7; r0=r1 AND r0; r0=BSET r0 by 18; dm(rxtcb+4)=r0; dm(CP0A)=r0; wait: idle; jump wait; IRQ: rti; /*Initiate SP0 DMA transfers*/

Listing 6-6. DMA-Driven Sport Loopback Example

/*___________________________________________________________ ADSP-21161 DMA-Driven SPORT Loopback Example This example shows an internally looped-back SPORT 32-bit transfer. The transfer buffer (TX2A) and receive buffer (RX0A) are both handled via DMA. ___________________________________________________________*/ #include "def21161.h" #define N 8 .section/pm seg_rth; /*Reset vector from ldf file*/ nop; jump start;

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Serial Port DMA

.section/dm seg_dmda; .var source[N]= 0X11111111, 0X22222222, 0X33333333, 0X44444444, 0X55555555, 0X66666666, 0X77777777, 0X88888888; .var dest[N]; .section/pm sp0i_svc; jump IRQ; rti;rti;rti; .section/pm sp2i_svc; jump IRQ; rti;rti;rti; /*-----------------Main Routine----------------------------*/ .section/pm seg_pmco; start: r0=source; dm(II2A)=r0; r0=dest; dm(II0A)=r0; r0=@source; dm(C0A)=r0; dm(C2A)=r0; r0=1; dm(IM0A)=r0; dm(IM2A)=r0; ustat3=dm(SYSCON); bit clr ustat3 BHD; dm(SYSCON)=ustat3; bit set imask SP0I |SP2I; /*Unmask Sport 0&2 interrupts*/ /*Disable Core Buffer Hang*/ /*Set DMA modify (stride) to 1.*/ /*Set DMA count to length of data buffers*/ /*Set DMA rx index to start of dest buffer*/ /*Set DMA tx index to start of source buffer*/

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bit set mode1 CBUFEN | IRPTEN;

/*Enable Circ. Buffer & Global Inters*/

r0 = 0x00001000; /*Set the SPL bit in the SPxxMCTL register to enable loopback*/ dm(SP02MCTL)=r0; r0 = 0x0; /*Externally generated clock and framesync*/

dm(DIV0) = r0; r0 = 0x000421f1; /*Set bits SPEN_A, SLEN=32, FSR--enable the A channel, set the word length to 32 bits, and require frame synch.*/ dm(SPCTL0)=r0; r0=0x00270004; /*TCLKDIV=[FCCLK(96Mhz)/2xFSCLK((19.2Mhz)]-1=0x0004*/ /*TFSDIV=[FSCLK(9.6Mhz)/TFS(.24Mhz)]-1=0x0027*/ dm(DIV2)=r0; r0=0x20465f1; /*Set bits SPEN_A, SLEN=32, ICLK, IFS, FSR, DDIR--enable the A channel, set the word length to 32 bits, generate internal framesynch and clock, require frame synch, and set for transmit.*/ dm(SPCTL2)=r0; wait: idle; jump wait; IRQ: rti;

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SPI Port DMA

SPI Port DMA

There are two DMA channels available on the ADSP-21161 for SPI port transfers: channels 8 and 9. These two channels are shared with the link port. Channel 8 which is assigned to SPI receive buffer SPIRX handles receive data while channel 9 which is assigned to SPI transmit buffer SPITX handles transmit data. The following sections describe typical SPI port DMA processes: Setting up SPl Port DMA on page 6-112 Bootloading Through the SPI Port on page 6-113 SPI Port Buffer on page 6-109 SPI DMA Channel Priority on page 6-112

SPI Port Registers

The SPICTL register controls the SPI port operating mode for the I/O processor. Figure 6-14 lists all the bits in SPICTL. The following bits control SPI port I/O processor modes. The control bits in the SPICTL registers have a one cycle effect latency. Programs should not modify an active DMA channels SPICTL register; other than to disable the channel by clearing the SPIEN bit. For information on verifying a channels status with the DMASTAT register, see DMA Channel Status Register (DMASTAT) on page A-90. For information on SPI port status, see SPI Port Status Register on page A-115.

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The following bits in SPICTL setup DMA SPI port features: SPI Port Enable. SPICTL Bit 0 (SPIEN). This bit enables (if set, =1) or disables (if cleared, =0) the SPI port. Data Format. SPICTL Bits 6 (DF). This bit selects the data format. When set (=1), the MSB is sent/received first. When cleared (=0), the LSB is sent/received first. SPI Word Length Select. SPICTL Bits 8-7 (WL). These bits select the word length. Word sizes can be 8-bit (WL = 00), 16-bit (WL = 01) or 32-bit (WL = 11). Word Packing Enable. SPICTL Bit 28 (PACKEN). This bit enables (if set, =1) 8- to 32-bit packing or (if cleared, =0) disables the packing. If this bit is enabled, the receiver packs the received byte whereas the transmitter unpacks the data before sending it. For more information on packing formats, see SPI Word Packing on page 11-24. This bit should be 1 only in 8-bit data word length (WL=00). SPI Port Receive DMA Enable. SPICTL Bit 27 (RDMAEN). This bit enables (if set, =1) or disables (if cleared, =0) DMA transfers from the receive data buffer. At SPI boot this bit is set to 1 to enable the booting process through the SPI port. SPI Port Transmit DMA Enable. SPICTL Bit 13 (TDMAEN). This bit enables (if set, =1) or disables (if cleared, =0) DMA transfers to the transmit data buffer. At SPI boot this bit is 0.

SPI Port Buffer

The SPIEN bit in the SPICTL register enables the SPI port. The SPI port shares channel 8 with link buffer 0 for the receive function. It shares channel 9 with link buffer 1 for the transmit function. Data is loaded into SPITX from internal memory by the DMA controller. Once the SPI is

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SPICTL
0xB4
GM
Fetch/Discard Incoming RXB data when RXB full 0=Discard incoming data 1=Overwrite with new data

31 30 29 28 27 26 25 24 23 22 21 20 0 0 0 0 0 0 0 0 0 0 0 0

19 18 17 16 0 0 0 0

FLS1
FLAG1 Slave Device Select 1=Enable, 0=Disable

SENDLW
Send Zero/Repeat Byte When TXB Empty 0=Send zero, 1=Repeat last data

FLS2
FLAG2 Slave Device Select 1=Enable, 0=Disable

SGN
Sign Extend Data 0=no sign extend, 1=sign extend

FLS3
FLAG3 Slave Device Select 1=Enable, 0=Disable

PACKEN
8-bit Packing Enable 0=no packing, 1=8 to 32-bit packing

NSMLS
Non-Seamless operation 0=no delay, 1=delay before next word starts

RDMAEN
Receive DMA Enable 1=Enable, 0=Disable

OPD
Open Drain Output Enable for Data Pins 0=Normal, 1=Open Drain

DCPH0
Deselect SPIDS in CPHASE =0 (master mode only, NSMLS bit=1) 0=No SPI device select 1=Deselects slaves between successive transfers

DMISO
Disable MISO Pin (Broadcast) 0=MISO Enabled, 1=MISO Disabled

15 14 13 12 11 10 1 0 0 0 0 1

9 1

8 1

7 0

6 1

5 0

4 0

3 0

2 0

1 0

0 0 SPIEN
SPI System Enable 1=enable, 0=disable

FLS0
FLAG0 Slave Device Select 1=Enable, 0=Disable

PSSE
Programmable Slave Select Enable 0=Disable, 1=Enable

SPRINT
SPI RX Buffer Interrupt Enable 1=enable SPI IRQ on RXB empty, 0=disable

TDMAEN
Transmit DMA Enable 1=Enable, 0=Disable

SPTINT
SPI TX Buffer Interrupt Enable 1=enable SPI IRQ on TXB not full, 0=disable

BAUDR
Baud Rate CCLK / (2**(2 + BR))

MS
Master/Slave Mode Bit 0=SPI slave device, 1=SPI Master Device

WL
Word Length 00=8 bits, 01=16 bits, 11=32 bits, 10=RESERVED

CP
Clock polarity 0=SPICLK active high, low in idle state 1=SPICLK active low, high in idle state

DF
Data Format 0=LSB sent / received first 1=MSB sent / received first

CPHASE
Clock phase 0=SPICLK toggles at middle of 1st data bit 1=SPICLK toggles at beginning of 1st data bit

Figure 6-14. SPICTL Register enabled, data in SPITX is automatically loaded into the transmit shift register. After a word is received completely in the receive shift register, it is automatically transferred to the SPIRX. The data in SPIRX is moved into internal memory by the DMA controller All DMA transfers are 32-bit words. To disable the SPI port, clear the SPIEN bit in the SPICTL register,

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which also clears the status of the buffers in the SPISTAT register. The bits in the SPI control register (SPICTL) are shown in Figure A-38 on page A-120. If the SPI port is enabled without enabling DMA, the SPI port is either in single-word, interrupt-driven data transfer mode (if the corresponding interrupt enable bits in the SPICTL is set) or is in core-driven data transfer mode. The software must do the data transfers to the SPI data buffers. For more information on the different SPI transfer modes, see Master Mode Operation on page 11-25. For more information on transfer status, see Using I/O Processor Status on page 6-121. The SPI allows independent settings for the three transfer format features: bit order, word length, and word packing. The SPI port buffer has a SPI data format (DF) bit, which when cleared (=0) can transmit data as little endian words (LSB first) to or from little endian devices. This bit selects big endian words (MSB first, if set, =1) or little endian words (LSB first, if cleared, =0). The SPI Word Length (WL) bit field selects the transfer word length. Word sizes can be 8-bit (WL = 00), 16-bit (WL = 01) or 32-bit (WL = 11). If the SPI word length is 8-bits or smaller, the SPI port can pack two of these words into the SPI port data buffer. The 8-bit to 32-bit Word Packing Enable (PACKEN) bit can enable this packing because the I/O processor performs 32-bit transfers between the SPI port buffer and processor memory. If this bit is enabled, the transmitter unpacks the data before sending it, while the receiver packs the received byte. For more information on packing formats, see SPI Word Packing on page 11-24. This bit should be 1 only in 8-bit data word length (WL= 00).

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SPI DMA Channel Priority

SPI shares DMA channels with the link port. The receive DMA is shared with link port 0 DMA while the transmit DMA is shared with link port 1. SPI port DMA transfers have the same priority as link port DMA transfers. If SPI DMAs are enabled, you should disable the link port DMAs. For more information on prioritization operations, see Managing DMA Channel Priority on page 6-22.

Setting up SPl Port DMA

In general, the following sequence describes a typical external to internal DMA operation where an external device transfers a block of data into the processors internal memory using a SPI port: 1. The processor or host (depending on the mode) enables the DMA channels serial port, setting the ports SPIEN bit in the ports SPICTL register. The processor or host selects a words size using the WL bits in the ports SPICTL register. 2. The processor or host (depending on the mode) writes the DMA channels parameter registers (IISRx, IMSRx, and CSRx) and SPICTL control register, initializing the channel for receive. 3. Depending on the mode, the processor or host sets the channels RDMAEN bit to 1 enabling the DMA process. 4. The external device begins writing data to the SPIRX buffer through the SPI port. 5. The SPIRX buffer detects data is present and asserts an internal DMA request to the I/O processor. 6. The I/O processor grants the request and performs the internal DMA transfer, emptying the SPIRX buffer.

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In general, the following sequence describes a typical internal to external DMA operation where an external device transfers a block of data from the processors internal memory using a serial port: 1. The processor or host (depending on the mode) enables the DMA channels serial port, setting the ports SPIEN bit in the ports SPICTL register. The processor or host selects a words size using the WL bits in the ports SPICTL register. 2. The processor or host (depending on the mode) writes the DMA channels parameter registers (IISTx, IMSTx, and CSTx) and SPICTL control register, initializing the channel for transmit. 3. The processor or host (depending on the mode) sets the channels TDMAEN bit to 1 enabling the DMA process. Because this is a transmit, setting TDMAEN automatically asserts an internal DMA request to the I/O processor. 4. The I/O processor grants the request and performs the internal DMA transfer, filling the SPITX buffer. 5. The external device begins reading data from the SPITX buffer through the SPI port. 6. The SPITX buffer detects that there is room in the buffer because it is now partially empty and asserts another internal DMA request to the I/O processor, continuing the process.

Bootloading Through the SPI Port

One of the processors booting modes is booting the processor through the SPI port. SPI port booting uses DMA channel 8 of the I/O processor to transfer the instructions to internal memory. In this boot mode, the processor receives 32-bit wide data in the SPIRX buffer.

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During the boot process the program loads 256 words into memory locations 0x40000 through 0x400FF. The processor subsequently begins executing instructions. Because most programs require more than 256 words of instructions and initialization data, the 256 words typically serve as a loading routine for the application. Analog Devices supplies loading routines (loader kernels) that load an entire program through the selected port. These routines come with the development tools. For more information on loader kernels, see the development tools documentation. For SPI booting the ADSP-21161, the Program sequencer automatically unmasks the DMA channel 8 interrupt, initializing the SPICTL register to 0x0A001F81 and IMASK register to 0x00004003. The processor determines the booting mode at reset from the EBOOT, LBOOT, and BMS pin inputs. When EBOOT=0, LBOOT=1, and BMS=0, the processor boots through the SPI Port. For a list showing how to select different boot modes, see the Boot Memory Select pin description in the table Booting Modes on page 13-72. When using any of the power-up booting modes, address 0x0004 0004 should not contain a valid instruction since it is not executed during the booting sequence. A NOP or IDLE instruction should be placed at this location. In SPI Port Booting, the processor gets boot data from another processors SPI port or another SPI compatible device after system powerup. Table 6-27 on page 6-115 shows how the DMA channel 8 parameter registers are initialized at reset for EPROM booting. The count register (CSRX) is initialized to 0x0180 for transferring 256 words to internal memory. The SPI Control Register (SPICTL) is configured to 0x0A001F81 upon reset during on SPI boot. The default value sets up SPI transfers as follows:
SPIEN MS

= 1, SPI enabled

= 0, slave device

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DF WL

= 0, LSB first = 11, 32-bit SPI receive shift register word length = 1111 (at 100 MHz, SPICLK = 763 Hz) = 1, MISO disabled

BAUDR DMISO RDMA

= 1, SPIRX DMA enabled on channel 8

This configuration sets up the SPIRX register for 32-bit serial transfers. The SPIRX DMA channel 8 parameter registers are configured to DMA in 0x180 number of 32-bit words into internal memory normal word address space starting at 0x40000. Once the 32-bit DMA transfer completes, the data is then accessed as 3-column 48-bit instructions. The processor executes a 256 (0x100) word loader kernel upon completion of the 32-bit, 0x180 word DMA. Note that for 16-bit SPI hosts, shift two words into the 32-bit receive shift register before a DMA transfer to internal memory occurs. For 8-bit SPI hosts, shift four words into the 32-bit receive shift register before a DMA transfer to internal memory occurs. Table 6-27. DMA Channel 8 Parameter Register Initialization for SPI Port Booting
Parameter Register IISRX IMSRX CSRX GPSRX Initialization Value 0x0004 0000 uninitialized (increment by 1 is automatic) 0x0180 (256 instruction words) uninitialized

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SPI Port DMA Programming Examples

This section provides two programming examples written for the ADSP-21161 processor. The example shown in Listing 6-7 demonstrates how the I/O processor uses DMA to read from the SPI port receive buffer and write to the SPI port transmit buffer. The example shown in Listing 6-8 demonstrates how the I/O processor uses DMA to read from the SPI port receive buffer and write to the SPI port transmit buffer after an interrupt. Listing 6-7. DMA-Driven SPI Loopback
/*______________________________________________________________ ADSP-21161 DMA-Driven SPI Loopback Example This example shows looped-back SPI 32-bit transfer. On this peripheral loop-back is performed by externally connecting the hardware MOSI and MISO pins on the processor. The transfer buffer and receive buffer are both handled via DMA. Hardware loop-back does not require the use of flags as device selects so the FLS bits do not need to be used as they would in an SPI transfer between two different SPI devices (non-loop-back.) ______________________________________________________________*/ #include <def21161.h> #define size 10 /* vector code for reset vector from ldf file .section/pm Chip_Reset: seg_rth; idle; jump start; nop; nop;

*/

/* vector code for receive interrupt vector from ldf file .section/pm spiri_svc; nop; nop; jump finish; nop;

*/

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.section/dm seg_dmda; /* transmit buffer

*/

.var spi_tx_buf[size] =0x11111111,0x22222222, 0x33333333, 0x44444444, 0x55555555,0x66666666, 0x77777777, 0x88888888, 0x99999999,0xaaaaaaaa; /* receive buffer

*/

.var spi_rx_buf[size]; .section/pm seg_pmco; start: r0=spi_tx_buf; dm(IISTX)=r0; r0=@spi_tx_buf; dm(CSTX)=r0; r0=1; /* configure modify register for SPI transmit /* configure count register for SPI transmit /* configure index register for SPI transmit

*/

*/

*/

dm(IMSTX)=r0; r0=spi_rx_buf; dm(IISRX)=r0; r0=@spi_rx_buf; dm(CSRX)=r0; r0=1; dm(IMSRX)=r0; /* configure modify register for SPI receive /* configure count register for SPI receive /* configure index register for SPI receive

*/

*/

*/

ustat1 = dm(SYSCON); bit clr ustat1 BHD; dm(SYSCON) = ustat1; bit set LIRPTL SPIRMSK ; /* enable SPI RX interrupts */ /* Clear Buffer Hang Disable in SYSCON

*/

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bit set MODE1 IRPTEN | CBUFEN; bit set IMASK LPISUMI; r0=0x00000000; dm(SPICTL)=r0; ustat1=dm(SPICTL); /*

/* allow global interrupts and circular buffer enable

*/

/* unmask spi interrupts

*/ */

/* initially clear SPI control register

set up options for the SPI port

*/

bit set ustat1

SPIEN | SPRINT | SPTINT | MS | CPHASE | DF | WL32

| BAUDR5 | SGN | GM | RDMAEN | TDMAEN; /* enable spi port, spitx and spirx interrupts, master device spiclk toggles at beginning of first data transfer bit, MSB first format, 32 bit word length, baud rate sign extend, get more new data even if receive buffer is full enable transmit and receive dma */ dm(SPICTL) = ustat1; wait: idle; jump wait; finish:rti; /* start transfer by configuring SPICTL */

Listing 6-8. Interrupt DMA-Driven SPI Loopback Example

/*_________________________________________________________ ADSP-21161 Interrupt DMA-Driven SPI Loopback Example This example shows an externally looped-back SPI 32-bit transfer. DMA is used to write to and read from the buffers. to the processor. Loopback is achieved by physically connecting the MOSI and MISO pins external

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___________________________________________________________*/ #include "def21161.h" #define size 10 /* PM interrupt vector code

*/

.SECTION/pm seg_rth; Reserved_1: rti; nop; nop; nop; Chip_Reset: idle; jump start; nop; nop; .SECTION/DMseg_dmda; .var spi_tx_buf[size] =0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xaaaaaaaa; .var spi_rx_buf[size]; .SECTION/PMseg_pmco; .GLOBAL SPI_register_init; .GLOBALSPI_lpbk_irq_test; start: ustat1 = dm(SYSCON); bit clr ustat1 BHD; dm(SYSCON) = ustat1; bit set mode1 CBUFEN; SPIDMA_tx: r0=spi_tx_buf;dm(IILB1)=r0; /* set circular buffer enable /* Clear Buffer Hang Disable in SYSCON

*/

*/

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r0=@spi_tx_buf;dm(CLB1)=r0; r0=1;dm(IMLB1)=r0; SPIDMA_rx: r0=spi_rx_buf;dm(IILB0)=r0; r0=@spi_rx_buf;dm(CLB0)=r0; r0=1;dm(IMLB0)=r0; r0=0x00000000;dm(SPICTL)=r0; /* Initially clear SPI control reg.*/ ustat1=dm(SPICTL); bit set ustat1 SPIEN|SPRINT|SPTINT|MS|CPHASE|DF|WL32|BAUDR5|PSSE|DCPH0|SGN|GM|R DMAEN|TDMAEN; bit clr ustat1 CP|FLS0|FLS1|FLS2|FLS3|SMLS|DMISO|OPD|PACKEN|SENDLW; dm(SPICTL) = ustat1; bit set LIRPTL SPIRMSK | SPITMSK; interrupts bit set MODE1 IRPTEN; wait: jump start; /* Allow global interrupts /* enable SPI TX & SPI RX */

*/

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Using I/O Processor Status

The I/O processor monitors the status of data transfers on DMA channels and indicates status in the DMASTAT, IRPTL, and LIRPTL registers. Table A-9 on page A-27 lists all the bits in IRPTL. Table A-10 on page A-34 lists all the bits in LIRPTL. A discussion of DMASTAT appears in DMA Channel Status Register (DMASTAT) on page A-90.

The DMA controller of ADSP-21161 processor maintains the status information of the channels in a read only register, DMASTAT. Bits 0-13 indicate which DMA channel is active; bits 16-29 indicate the chaining status of the channels. Bit definitions for the DMASTAT register are defined in Table 6-28 and in Figure 6-15. Bit definitions for the SPISTAT register are defined in Table A-29 on page A-115.

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DMASTAT
0x37

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0

DMA13CHST
Channel 13(EPB3) Chaining Status

DMA0CHST
Channel 0 (RX0A/TX0A) Chaining Status

DMA12CHST
Channel 12 (EPB2) Chaining Status Channel 11 (EPB1) Chaining Status Channel 10 (EPB0) Chaining Status

DMA2CHST
Channel 2 (RX1A/TX1A) Chaining Status

DMA11CHST DMA10CHST DMA7CHST

DMA4CHST DMA6CHST

Channel 4 (RX2A/TX2A) Chaining Status Channel 6 (RX3A/TX3A) Chaining Status

Channel 7 (RX3B/TX3B) Chaining Status

DMA8CHST
Channel 8 (LBUF0) Chaining Status

DMA5CHST
Channel 5 (RX2B/TX2B) Chaining Status

DMA9CHST DMA1CHST

Channel 9 (LBUF1) Chaining Status Channel 1 (RX0B/TX0B) Chaining Status

DMA3CHST
Channel 3 (RX1B/TX1B) Chaining Status 15 14 13 12 11 10 0 0 9 8 7 6 5 4 3 2 1 0

DMA13ST
Channel 13 (EPB3) Status

DMA0ST
Channel 0 (RX0A/TX0A) Status Channel 2 (RX1A/TX1A) Status

DMA12ST
Channel 12 (EPB2) Status

DMA2ST DMA4ST

DMA11ST
Channel 11 (EPB1) Status

Channel 4 (RX2A/TX2A) Status

DMA10ST
Channel 10 (EPB0) Status

DMA6ST
Channel 6 (RX3A/TX3A) Status

DMA7ST
Channel 7 (RX3B/TX3B) Status

DMA8ST
Channel 8 (LBUF0/SPIRX) Status

DMA5ST
Channel 5 (RX2B/TX2B) Status

DMA9ST
Channel 9 (LBUF1/SPITX) Status

DMA3ST
Channel 3 (RX1B/TX1B) Status

DMA1ST
Channel 1 (RX0B/TX0B) Status

* Channel Active Status: 1=Active [ transferring data or waiting to transfer current block, and not transferring TCB ] 0= Inactive [DMA transter complete, or in TCB chain loading] ** Channel Chaining Status: 1=Chaining is Enabled and currently transferring TCB, or is Pending to transfer TCB, 0 = Chaining Disabled Status does not change on the master ADSP-21161 processor during external port DMA until the external portion is completed (for example, the EPBx buffers are emptied). If in chain insertion mode (DEN=0, CHEN=1), then channel chaining status will never go to a 1. Therefore, test channel status to see if it is ready so that your program can rewrite the chain pointer (CPx) register.

Figure 6-15. DMA STAT Register

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Table 6-28. DMASTAT Register Definitions

Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 - 15 16 17 18 19 20 21 22 23 24 0 2 4 6 8 9 1 3 5 DMA Channel # 0 2 4 6 8 9 1 3 5 7 10 11 12 13 Definitions Status1 (RX0A or TX0A) Status1 (RX1A or TX1A) Status1 (RX2A or TX2A) Status1 (RX3A or TX3A) Status1 (LBUF0/SPIRX) Status1 (LBUF1/SPITX) Status1 (RX0B or TX0B) Status1 (RX1B or TX1B) Status1 (RX2B or TX2B) Status1 (RX3B or TX3B) Status1 (EPB0) Status1 (EPB1) Status1 (EPB2) Status1 (EPB3) Reserved Chaining Status2 (RX0A or TX0A) Chaining Status2 (RX1A or TX1A) Chaining Status2 (RX2A or TX2A) Chaining Status2 (RX3A or TX3A) Chaining Status2 (LBUF0) Chaining Status2 (LBUF1) Chaining Status2 (RX0B or TX0B) Chaining Status2 (RX1B or TX1B) Chaining Status2 (RX2B or TX2B)

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Table 6-28. DMASTAT Register Definitions (Contd)

Bit # 25 26 27 28 29 30-31 1 2 DMA Channel # 7 10 11 12 13 Definitions Chaining Status2 (RX3B or TX3B) Chaining Status2 (EPB0) Chaining Status2 (EPB1) Chaining Status2 (EPB2) Chaining Status2 (EPB3) Reserved

Channel Active status: 1-active, 0 = inactive Channel Chaining status: 1 = chaining enabled/pending, 0 = chaining disabled

The I/O processor reports on DMA in progress, DMA complete, or DMA channel not ready status as follows: All DMA channels can be active or inactive. If a channel is active, a DMA is in progress on that channel. The I/O processor indicates the active status by setting the channels bit in the DMASTAT register. When an unchained (single-block) DMA process reaches completion on any DMA channel, the I/O processor generates that DMA channel's interrupt. It does this by setting the DMA channel's interrupt latch bit in the IRPTL or LIRPTL register. The DMA process is complete when the count in CEPx=0 (for Slave mode and Handshake modes) or when the count in ECEPx=0 (for External Handshake mode) or when the count in CEPx=0 and ECEPx=0 (for Master mode and Paced Master mode). When a DMA process in a chained DMA sequence reaches completion (the count in Cx=0 or CEPx=0) on any DMA channel, the I/O processor generates an interrupt if the PCI bit in the channels CPx register is set. The only exception is external-handshake mode.

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The I/O processor also generates that DMA channels interrupt when the last block in a chained DMA reaches completion regardless of the PCI setting. When a DMA channels buffer not being used for a DMA process, the I/O processor can generate an interrupt on single word writes or reads of the buffer. This interrupt service differs slightly for each port. For more information on single-word interrupt-driven transfers, see External Port Status on page 6-127, Link Port Status on page 6-131, and Serial Port Status on page 6-135. Using the DMA Channel Status Register (DMASTAT), programs can check which DMA channels are performing a DMA or chained DMA. For each channel, the I/O processor sets the channels active status bit if DMA for that channel is enabled and a DMA sequence is in progress on that channel. The I/O processor sets the channels chaining status bit if a chained DMA sequence is in progress or pending on that channel. There is a one cycle latency between a change in DMA channel status and the status update in the DMASTAT register. As an alternative to interrupt-driven DMA, programs can poll the DMASTAT register to determine when a single DMA sequence is done. To poll channel status, programs read DMASTAT. If both status bits for the channel are cleared, the DMA sequence has completed. If chaining is enabled on a DMA channel, programs should not use polling to determine channel status. Polling could provide inaccurate information in this case because the next DMA sequence might be under way by the time the polled status is returned. During interrupt-driven DMA, programs use the interrupt mask bits in the IMASK and LIRPTL registers to selectively mask DMA channel interrupts that the I/O processor latches into the IRPTL and LIRPTL registers.

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The I/O processor only generates a DMA complete interrupt when the channels count register decrements to zero as a result of actual DMA transfers. Writing zero to a count register does not generate the interrupt. A channel interrupt mask in IMASK and IRPTL masks out DMA complete interrupts for a channel, but other types of interrupt masking are also available. These other types of interrupt masking include: By clearing a channels PCI bit during chained DMA, programs mask the DMA complete interrupt for a DMA processes within a chained DMA sequence. By masking the LPISUM interrupt, programs mask out the logical Oring of link port interrupt status. By masking the LSRQ interrupt, programs mask out link port service requests to link ports that do not have an assigned link buffer. These lower levels of interrupt masking let programs limit some of the conditions that can cause DMA channel interrupts. Each DMA channel has its own interrupt. Although the external port and link port channel access priority can rotate, the interrupt priorities of all DMA channels are fixed. In processor systems using I/O processor interrupts, an external device may need to change the processors interrupt mask. This task presents a challenge because the IMASK register is not memory-mapped and is not directly accessible to external devices through the external port. To read or write IMASK through the external port, programs can set up an interrupt vector routine to handle this task. The VIRPT vector interrupt register may be used for this task. The I/O processor can also generate non-DMA single-word interrupts for I/O port operations that do not use DMA. In this case, the I/O processor generates a DMA interrupt when data becomes available at the receive

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buffer or when the transmit buffer does not have new data to transmit. Generating DMA interrupts in this fashion lets programs implement interrupt-driven I/O under control of the processor core. Care is needed because multiple interrupts can occur if several I/O ports transmit or receive data in the same cycle.

External Port Status

The I/O processor monitors the status of data transfers on the external port. DMA channel status for the external port is described in Using I/O Processor Status on page 6-121. This section describes external port specific status features, such as buffer status, buffer control, and single-word interrupt-driven transfers. Bits in the SYSTAT, SYSCON and DMACx registers indicate and control the status of external port buffers. Table A-21 on page A-69 lists all the bits in SYSTAT. Table A-18 on page A-60 lists all the bits in SYSCON.

Table A-24 on page A-80 and Figure 6-16 lists all the bits in the DMACx register . For a description of the IOP registers, see the Registers appendix of this manual. The following bits influence external port buffer status: Host Packing Status. SYSTAT bits 24-22 (HPS). These bits indicate the hosts packing status. External Port Packing Status. DMACx Bits 23-21(PS). These bits indicate the corresponding FIFO buffers packing status. Table 6-29 shows the available bit setting.

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Single-Word Interrupt Enable. DMACx Bit 12 (INTIO). This bit enables (if set, =1) or disables (if cleared, =0) single-word, non-DMA, interrupt-driven transfers for the corresponding external port FIFO buffer (EPBx). To avoid spurious interrupts, programs must not change a buffers INTIO setting while the buffer is enabled. Flush DMA Buffers and Status. DMACx Bit 14 (FLSH). This bit flushes (when set, =1) settings for the corresponding external port FIFO buffer (EPBx). External Port FIFO Buffer Status. DMACx bit 17-16 (FS). These bits indicate the corresponding external port FIFO buffers status. Table 6-30 shows the available setting.
DMAC10 DMAC11 DMAC12 DMAC13
0x1c 0x1d 0x1e 0x1f

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PS
Ext Port EPBx FIFO Buffer Packing Status (read-only) 000=packing complete 001=1st stage pack/unpack 010=2 nd stage pack/unpack 011=3rd stage 100 = 5 th stage of 8 to 48 -bit packing 101=110=111= reserved 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 4 0 3 2 1 0

FS
Ext. Port FIFO Buffer Status (read-only) 00=buffer empty 01=buffer-not-full 10=buffer-not - empty 11=buffer full

0 0

0 0

Flush EPBx FIFO Buffers & Status 1=flush EPBx

FLSH

INTIO
Single Word Interrupts for EPBx FIFO Buffers 1=enable single - wd non -DMA interrupt-driven xfers 0=disabled, FIFO fully enabled

Figure 6-16. DMAC RegisterStatus Bits Only

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The HPS bits in the SYSTAT and PS bits in the DMACx registers indicate an external buffers packing status. These bits are read-only, and the processor clears these bits when DEN is cleared (changes from 1 to 0). Table 6-29. Processor (PS) and Host (HPS) Packing Status
PS or HPS 000 001 010 011 100 Packing Status packing complete (6th stage of 8- to 48-bit packing, 4th stage of 8- to 32-bit packing, etc.) 1st stage 2nd stage 3rd stage fifth stage of 8/48

The FS bits in the DMACx registers indicate an external buffers FIFO status. These bits are read-only. The processor clears these bits when DEN is cleared (changes from 1 to 0). Table 6-30. External Port Buffer FIFO Status
FS 00 01 10 11 FIFO Buffer Status buffer empty buffer-not-full buffer-not-empty buffer full

For transmit (TRAN=1), buffer-not-full means that the buffer has space for one normal word, and buffer-not-empty means that the buffer has space for two-or-more normal words. For receive (TRAN=0), buffer-not-full means that the buffer contains one normal word, and buffer-not-empty

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means that the buffer contains two or more normal words. Any type of full status (01, 10, or 11) in receive mode indicates that new (unread) data is in the buffer. When a program sets (=1) the FLSH bit, the processor flushes the settings for the corresponding external port FIFO buffer (EPBx). Flushing these settings does the following: clears (=0) the FS and PS status bits, clears (=0) the FIFO buffer and DMA request counter, clears any partially packed words. There is a two-cycle effect latency in completing the flush operation. Programs must not set a buffers FLSH during the same write that enables the buffer. Also, programs must not set a buffers FLSH bit while the DMA channel is active. Programs should determine the channels active status by reading the corresponding bit in the DMASTAT register. Status does not change on the master processor during external port DMA until the external portion is completed (for example, the EPBx buffers are emptied). If in chain insertion mode (DEN=0, CHEN=1), then channel chaining status never goes to 1. Programs should test channel status to see if it is ready before re-writing the chain pointer (CPx). The INTIO bit in the DMACx registers support single-word interrupt-driven transfers for each corresponding external port buffer. These non-DMA transfers are available under the following conditions: The external port DMA channels DEN bit is cleared (DMA disabled). The external port DMA channels INTIO bit is set enabling interrupt-driven I/O. The external port DMA channels buffer is not empty on an external read or not full on an external write. Under these conditions, the I/O processor generates that DMA channels interrupt on the single word transfer to or from that channels external port buffer.

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Link Port Status

The I/O processor monitors the status of data transfers on the link ports. DMA channel status for the link ports is described in Using I/O Processor Status on page 6-121. This section describes link ports specific status features, such as buffer status, buffer control, and single-word interrupt-driven transfers. The LRSQ (Link Service Request) register allows a disabled link port to respond to a link port transmit or receive request from another processor. Bits in the LSRQ registers indicate and control status of link port buffers.The following bits influence link port buffer status: Link Port x Transmit Mask. LSRQ Bit 4 and 6 (LxTM). These bits mask (if set, =1) or unmask (if cleared, =0) the L0TRQ through L1TRQ status bits. Link Port x Receive Mask. LSRQ Bit 5 and 7 (LxRM). These bits mask (if set, =1) or unmask (if cleared, =0) the L0RRQ and L1RRQ status bits. Link Port x Transmit Request Status (read-only). LSRQ Bit 20 and 22 (LxTRQ). If set (=1), these bits indicate that the corresponding link port (0 or 1) is disabled, but has a request to transmit data. Link Port x Receive Request Status (read-only). LSRQ Bit 21and 23 (LxRRQ). If set (=1), these bits indicate that the corresponding link port (0 or 1) is disabled, but has a request to receive data. The Link Port Status Register (LSRQ) is shown in Figure 6-16. The status bits in the Link Port Control Register (LCTL) are shown in Figure 6-17 on page 6-132.

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LSRQ 0xD0
L1RRQ

31 30 29 28 27 0 0 0 0 0

26 25 24 23 22 21 20 19 18 17 0 0 0 0 0 0 0 0 0 0

16 0

L0TRQ
Link Port 0 Transmit Request

Link Port 1 Receive Request

L1TRQ
Link Port 1 Transmit Request

L0RRQ
Link Port 0 Receive Request

15 14 13 12 0 L1RM
Link Port 1 Receive Mask

11 10 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0 L0TM
Link Port 0 Transmit Mask

L1TM
Link Port 1 Transmit Mask

L0RM
Link Port 0 Receive Mask

Figure 6-17. LSRQ Register

LCTL 0xCC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

LRERR1
Rcv. Pack Error Status for Link Buffer 1 1=incomplete, 0=complete

L1STAT[1:0]
Link Buffer 1 Status (Read - Only) 11=Full, 00 = Empty, 10=one word

LRERR0
Rcv. Pack Error Status for Link Buffer 0 1=incomplete, 0=complete

L0STAT[1:0]
Link Buffer 0 Status (Read - Only) 11=Full, 00= Empty, 10=one word

Figure 6-18. LCTL Register Status Bits The LRERRx bits in the LCTL register indicate a link port buffers receive packing status. When the buffer is ready to receive and pack a new word, the processor clears (=0) LRERRx. If this bit remains set (=1) after the buffer receives a word, a link transfer error (for example, a clock glitch) has

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occurred. These bits are read-only, and the processor clears these bits when LxEN is cleared (changes from 1 to 0). Table 6-31 shows the available settings. Table 6-31. Link Port Buffer Receive Packing Status
LRERRx 0 1 Receive Packing Status pack complete (reset value) pack not complete

The LxSTATx bits in the LCTL register indicate a link buffers FIFO status. When transmitting, these bits indicate when the buffer has space for more data. When receiving, these status bits indicate when the buffer contains new (unread) data. These bits are read-only. The processor clears these bits when LxEN is cleared (changes from 1 to 0) and empties the buffer. Table 6-32 shows the available settings. Table 6-32. Link Port Buffer FIFO Status
LxSTATx 00 01 10 11 FIFO Buffer Status buffer empty reserved one word buffer full

The LCTL register lets programs assign link buffers to link ports. Bits LABO and LAB1 in the LCTL register assign link buffers to link ports. Because this mapping allows link ports to be unassigned (no buffer), the I/O processor has an interrupt (LSRQI) to notify programs that an external device has made a read or write request on a disabled link port.

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When an LSRQI interrupt is latched into the IRPTL register, programs use the transmit (LxTRQ) and receive (LxRRQ) request bits in LSRQ register to determine which port has a request. The LSRQ registers bits indicate the following: For a transmit request (LxTRQ=1), the LSRQI interrupt indicates that the link port (0 or 1) is disabled, but another processor has requested more data by setting the link ports acknowledge (LxACK=1). For a receive request (LxRRQ=1), the LSRQI interrupt indicates that the link port is disabled, but another processor has requested to send data by setting the link ports clock (LxCLK=1). To control sources of link port service requests, the I/O processor lets programs mask these service requests. The LSRQ register provides mask bits for transmit (LxTM) and receive (LxRM) link service requests. The LxEN bits in the LCTL register support single-word interrupt-driven transfers for each corresponding link port buffer. These non-DMA transfers are available under the following conditions: The link port DMA channels LxDEN bit is cleared (DMA disabled). The link port DMA channels LxEN bit is set enabling the link buffer. The link port DMA channels buffer is not empty on receive or not full on transmit. Under these conditions, the I/O processor generates that DMA channels interrupt on the single word transfer to or from that channels link port buffer.

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Serial Port Status

The I/O processor monitors the status of data transfers on the serial ports. DMA channel status for the serial ports is described in Using I/O Processor Status on page 6-121. This section describes serial ports specific status features, such as buffer status, transmit buffer underflow, receive buffer overflow, and single-word interrupt-driven transfers. Bits in the SPCTLx registers indicate and control status of serial port buffers. For more information, see SPORT Serial Control Registers (SPCTLx) on page A-100. The following bits influence serial port buffer status: DXA Error Status (sticky, read-only). SPCTLx Bit 29 (DERR_A). This bit indicates (if set, =1 and DDIR =1) whether the serial transmit operation has underflowed or (if cleared, =0 and DDIR =0)the serial receive has overflowed on the A path. DXS_A Data Buffer Status (read-only). SPCTLx Bits 31-30 (DXS_A). These bits indicate the status of the serial ports DXA data buffer. See Table 6-33 for available bit settings. DXB Error Status (sticky, read-only). SPCTLx Bit 26 (DERR_B). This bit indicates (if set, =1 and DDIR =1) whether the serial transmit operation has underflowed or (if cleared, =0 and DDIR =0)the serial receive has overflowed on the B path. DXS_B Data Buffer Status (read-only). SPCTLx Bits 28-27 (DXS_B). These bits indicate the status of the serial ports DXB data buffer. See Table 6-33 for available bit settings. The DXS_A and DXS_B bits in the SPCTLx registers indicate a serial port transmit or receive buffers FIFO status. Status bits are read-only. Disabling the serial port (setting SPEN=0), clears the status bits and empties

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the buffer. The bits may change state if the data is read or written by the processor core while the serial port is disabled. Table 6-33 shows the available settings. Table 6-33. Serial Port Transmit and Receive Buffer FIFO Status
DXS_A or DXS_B 00 01 10 11 FIFO Buffer Status buffer empty reserved partially full buffer full

The DERR_A and DERR_B bits in the SPCTLx registers indicate a serial port transmit underflow or receive overflow to the buffers FIFO. Status bits are read-only. Disabling the serial port (setting SPEN=0), clears the status bits and empties the buffer. These overflow and underflow bits are sticky; once set, they remain set regardless of buffer status until the serial port is disabled. The SPEN bit in the SPCTLx register support single-word interrupt-driven transfers for each corresponding serial port transmit or receive buffer. These non-DMA transfers are available under the following conditions: The serial port DMA channels SDEN bit is cleared (DMA disabled). The serial port DMA channels SPEN bit is set (enabling the serial port transmit or receive buffer). The serial port DMA channels buffer is not empty on receive or not full on transmit. Under these conditions, the I/O processor generates that DMA channels interrupt on the single word transfer to or from that channels serial port buffer.

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SPI Port Status

The I/O processor monitors the status of data transfers on the SPI port. DMA channel status for the SPI port is described in Using I/O Processor Status on page 6-121. This section describes SPI port specific status features, such as buffer status, transmit or receive buffer errors, and transfer completion test. Bits in the SPISTAT register indicate and control status of SPI port buffers, SPIRX and SPITX. Table A-29 on page A-115 and Figure 6-19 lists all the bits in SPISTAT. The following bits influence SPI port buffer status: SPI Transmit Transfer Completion. SPISTAT Bit 0 (SPIF). This bit is set (=1) when the SPI transfer is complete. For example, the following condition is met: the transmit data buffer is empty and the last data has been transmitted out of the transmit shift register. The bit is cleared (=0) when the transfer is active. Transmit Error (sticky, read-only). SPISTAT Bit 2 (TXE). This bit indicates an error in the transmission. This bit is set (=1) when the transmit data buffer is empty and the last data has been transmitted out of the transmit shift register. If you are not servicing the interrupt quickly enough and not updating the contents of SPITX so that it is available to be transferred to the transmit shift register when required, this bit is set. Transmit Data Buffer Status (read-only). SPISTAT Bit 3-4 (TXS). These bits indicate the status of the SPI port transmit buffer (SPITX). If TXS =00, the buffer is empty. See Table 6-34 for available TXS bit settings. Receive Error (sticky, read-only). SPISTAT Bit 5 (RBSY). This bit indicates an error in the receive operation. This bit is set (=1) when the SPITX data buffer is full and the last data has been received into

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the receive shift register. If you are not servicing the interrupt quickly enough and not transferring the contents of SPIRX, this bit is set. Receive Data Buffer Status (read-only). SPISTAT Bits 6-7 (RXS). These bits indicate the status of the SPI port receive buffer (SPIRX). If RXS =00, the buffer is empty. See Table 6-34 for available RXS bit settings.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPISTAT 0xB5

15 14 13 12 11 10 9 0 0 0 0 0 0 0

8 0

7 0

6 0

5 0

4 0

1 0

0 0

0 0

RXS
SPIRX Data Buffer Status (Read-only) 00=SPIRX empty 01=SPIRX partially full 11=SPIRX full 10=Reserved

SPIF
SPI Transmit Transfer Complete 1=transfer complete, 0=active transfer

MME
Multimaster Error 0=no error, 1=SPIDS~ asserted by slave

RBSY
Reception Error (Overflow) 1=new data received with full RXB FIFO SPI enters idle mode if master device

TXE
Transmission Error (Underflow) 1=no new data in TX FIFO, SPI enters idle mode if master device

TXS
SPITX Data Buffer Status (read only) 00=SPITX empty 01=TXB partially full 11=SPITX full 10=Reserved

Figure 6-19. SPISTAT Register The TXS and RXS bits in the SPISTAT registers indicate a SPI port transmit (SPITX) or receive (SPIRX) buffers FIFO status. Disabling the SPI port (setting SPIEN=0), clears the status bits and empties the buffer. TXS and RXS may change state if the data is read or written by the processor core while the SPI port is disabled. Table 6-34 shows the available settings.

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Table 6-34. SPI Port Transmit and Receive Buffer FIFO Status
TXS or RXS 00 01 10 11 FIFO Buffer Status buffer empty partially full reserved buffer full

The TXE and RBSY bits in the SPISTAT registers indicate a SPI port transmit underflow or receive overflow to the buffers FIFO. Status bits are read-only. Disabling the SPI port (setting SPIEN=0), clears the status bits and empties the buffer. These overflow and underflow bits are sticky; once set, they remain set regardless of buffer status until the SPI port is disabled. Under these conditions, the I/O processor generates that DMA channels transfer request over the IOD bus on the single word transfer to the SPITX data buffer or from the SPIRX data buffers.

Optimizing DMA Throughput

This section discusses overall DMA throughput when several DMA channels are trying to access internal or external memory at the same time. Table 6-35 summarizes the advantages of different system configurations.

Internal Memory DMA

The DMA channels arbitrate for access to the processors internal memory. The DMA controller determines, on a cycle-by-cycle basis, which channel is allowed access to the internal I/O bus and consequently which channel can read or write to internal memory. The priority order of the DMA channels appears in Table 6-1 on page 6-3.

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Each DMA transfer takes one clock cycle even when different DMA channels are being allowed access on sequential cycles; for example, there is no overall throughput loss in switching between channels. Thus, two link port DMA channels, each transferring one byte per cycle, would have one half the I/O transfer rate as one external port DMA channel transferring data to internal memory on every cycle. Any combination of link ports, serial ports, and external port transfers has the same maximum transfer rate.

External Memory DMA

When the DMA transfer is between processor internal memory and external memory, the external memory may have one or more wait states. External memory wait states, however, do not reduce the overall internal DMA transfer rate if other channels have data available to transfer. In other words, the processors internal I/O data bus cannot be held up by an incomplete external transfer.

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Table 6-35. Configurations for Processor Processor DMA

Processor Config. (Data Source) Bus Master DMA Master Mode (MASTER= 1) TRAN=1, EIEPx = address of EPBx buffer in destination, EMEPx= 0 Bus Slave DMA Slave Mode (MASTER= 0), TRAN= 1 Processor Config. (Data Destination) Bus Slave DMA Slave Mode (MASTER= 0), TRAN= 0 C/T1 1 Advantages, Disadvantages Advantage: Destination automatically generates interrupt upon completion. Disadvantage: DMA must be programmed on both source and destination. Bus Master DMA Master Mode (MASTER= 1), TRAN=0, EIEPx = address of EPBx buffer in source, EMEPx=0 32 Advantage: Source automatically generates interrupt upon completion. Disadvantages: Slower throughput. DMA must be programmed on both source and destination.

1 2

C/T is throughput in cycles/transfer. Maximum burst read throughput: 3-2-2-2

Figure 6-20 shows an example DMA hardware interface. The following should be noted in this figure. Because DMARx and DMAGx are tied together, only one of the processors may have DMA enabled at a time.
DMAGx

is only driven by the processor bus master.

The DMA Write Grant signal can be the combination of WR and MS3-0 instead of DMAG2 if paced master mode is used. The DMA Read Grant signal can be the combination of RD and MS3-0 instead of DMAG1 if paced master mode is used. DMA transfers may be to either processor or to external memory (in external handshake mode).

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ADSP-2116X

8,16, OR 32

LATCH D Q

BR2
5

ADDR23-0 DATA47-16

DMA DATA BUS DMA READ REQ.

BR1

OE DMAR1 DMAG1 DMAR2 DMAG2

3 010

ID2-0

DMA READ GRANT

HBR

RD WR ACK MS3-0

COMMON GRANT LINE

COMMON REQ. LINE

HBG

ADSP-2116X ADDR23-0 DATA47-16

8, 16, OR 32

LATCH Q D

DMA DATA BUS

BR1
5

BR2
ID2-0

OE

3 001

DMAR1 DMAG1 DMAR2 DMAG2 HBG HBR RD WR

ACK DMA WRITE REQ.

OE WE ACK CS
ADDR DATA EXTERNAL MEMORY

DMA WRITE GRANT

MS3-0

Figure 6-20. Example DMA Hardware Interface

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I/O Processor

CLKIN FETCH/DECODE CYCLES2 CYCLES MIN. DMARx tHDGC

tSDRLC

tSDRHC DMAGx tWDGL

tVDATDGH

VALID DATA47-16

Figure 6-21. DMAR and DMAG Timing Figure 6-21 shows DMAR and DMAG timing. The following should be noted in this figure. setup times relate to the use of the signal in that cycle by the processor. DMA requests may be asserted asynchronously to CLKIN.
DMARx

drives DATA47-16 if the processor is receiving. DMAGx latches DATA47-16 if the processor is transmitting.
DMAGx

When data is to be transferred from internal to external memory, the internal memory data is first placed in the external ports EPBx buffer by the DMA controller; the external memory access begins independently once the data is detected in the EPBx buffer. Likewise, for external-to-internal DMA, the internal DMA request is not be made until the external memory data is in the EPBx buffer. In both cases, the external DMA address generatorthe EIEPx and EMEPx parameter registersmain-

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tains the external address until the data transfer is completed. The internal and external address generators of a DMA channel are decoupled and operate independently. When EXTERN mode DMA transfers occur between an external device and external memory, no internal resources of the processor are utilized and internal DMA throughput is not affected.

System-Level Considerations
Slave mode DMA is useful in systems with a host processor because it allows the host to access any processor internal memory location indirectly through DMA while limiting the address space the host must recognize only the address space of the processors I/O processor registers. Slave mode DMA is also useful for processor-to-processor DMA transfers. Slave mode DMA has one drawback when interfacing to a slow hostthe fact that the external bus is held up during the transfer (whether initiated by the processor or the host) and no other transactions can proceed. To overcome this, the handshake DMA mode may be used. In handshake mode, the host does not have to master the bus in order to make a DMA request, nor does the processor (in master mode) have to wait on the bus for the transfer to complete. Instead, the host asserts the DMARx pin. When the processor is ready to make the transfer, it can complete it in one bus cycle. For more information, see Handshake Mode on page 6-57.

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7 EXTERNAL PORT

The ADSP-21161 processors external port extends its address and data buses off-chip. Using these buses and external control lines, systems can interface the processor with external memory, 8-, 16- or 32-bit host processors, and other DSPs. Because many of the external port operations relate to external memory accessing or I/O processing, this chapter refers to the memory and I/O processor chapters (Memory on page 5-1 and I/O Processor on page 6-1) frequently. This chapter describes connection and timing issues for the external port. The main sections of this chapter describe the interfaces that are available through the external port. These interfaces include: External Memory Interface on page 7-3 Host Processor Interface on page 7-42 Multiprocessor (MP) Interface on page 7-87 Data alignment through the external port is identical for these interfaces. Figure 7-1 shows the external ports data alignment.

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7-1

L1DATA[7:0] L0DATA[7:0] DATA 15-8 DATA 7-0

DATA 47-16
47 40 39 32 31 24 23 16 15

DATA 15-0
8 7 0

PROM BOOT 8-bit Packed DMA Data 8-bit Packed Instruction Execution 16-bit Packed DMA Data 16-bit Packed Instruction Execution Float or Fixed, D31-D0, 32-bit Packed DMA 32-bit Packed Instruction Execution 48-bit Instruction Fetch (No Packing)

Extra data lines DATA[15-0] are only accessible if Link Ports are disabled. Enabled when IPACK = 1 in the SYSCON register

Figure 7-1. ADSP-21161 External Data Alignment Options

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External Port

Setting External Port Modes

This section describes the various ways to use the external port for data transfer. The SYSCON, WAIT, and DMACx registers control the external port operating mode. Table A-18 on page A-60 lists all the bits in SYSCON, Table A-17 on page A-68 lists all the bits in WAIT, and Table A-24 on page A-80 lists all the bits in DMACx. For information about setting up memory access modes (synchronous versus asynchronous interface), see Setting Data Access Modes on page 5-32. For information on setting DMA through the external port, see External Port DMA on page 6-29. For information on using external port interrupts, see Using I/O Processor Status on page 6-121. There is a 3:1 bus conflict resolution ratio at the external port interface (three internal buses to one external bus) in addition to the 2:1 or greater clock ratio between the processors internal clock and the external system clock. Systems that fetch instructions or data through the external port must tolerate at least one cycleand possibly many additional cyclesof latency for non-SDRAM accesses. SDRAM accesses operate at the core clock rate.

External Memory Interface

In addition to its on-chip SRAM, the processor provides addressing of up to 64 megawords SRAM or SBSRAM or 254 megawords of off-chip SDRAM memory through its external port. This external address space includes multiprocessor memory spacethe IOP register space of all other ADSP-21161s connected in a multiprocessor systemas well as external memory spacethe region for standard addressing of off-chip memory.

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External Memory Interface

Figure 7-2 shows how the buses and control signals extend off-chip, connecting to external memory. Table 7-1 defines the processor pins used for interfacing to external memory. The processors memory control signals permit direct connection to fast static RAM devices. Memory mapped peripherals and slower memories can also connect to the processor using a user-defined combination of programmable waitstates and hardware acknowledge signals. External memory can hold instructions and data. Packed instructions can be executed directly from 32-bit, 16-bit, or 8-bit wide external memories using 32- to 48-bit, 16- to 48-bit or 8- to 48-bit execution packing modes supported by the external port and program sequencer. The external port can also be configured to have a 48-bit wide external data bus for 48-bit non-packed execution of instructions when link ports are not used. The link port data lines are multiplexed with the data lines D0 to D15 and are enabled through control bits in the memory mapped control register SYSCON. Data packing of 32- to 48-bit, 16- to 48-bit, 8- to 48-bit, 32- to 32/64-bit, 16- to 32/64-bit or 8- to 32/64-bit is supported for DMA transfers directly from 32-bit, 16-bit, or 8-bit wide external memories to and from 32-, 48-, or 64-bit internal memory. Figure 7-1 shows how the processor transfers different data word sizes over the external port.

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External Port

CONTROL

CLOCK 2

CLKIN XTAL CLK_CFG1-0 CLKDBL EBOOT LBOOT IRQ2-0

BMS

DATA

ADSP-21161

ADDRESS

CS ADDR

3 12

BRST

DATA ADDR DATA OE WE ACK CS

BOOT EPROM (OPTIONAL)

LINK DEVICES (2 MAX) (OPTIONAL) SERIAL DEVICE (OPTIONAL)

FLAG11-0 ADDR23-0 TIMEXP RPBA DATA47-16 ID2-0 RD LXCLK WR LXACK ACK LXDAT7-0 MS3-0 SCLK0 FS0 D0A D0B SCLK1 FS1 D1A D1B SCLK2 FS2 D2A D2B SCLK3 FS3 D3A D3B SPICLK SPIDS MOSI MISO RAS CAS DQ M SDWE SDCLK[1-0] SDCKE SDA10

MEMORY AND PERIPHERALS (OPTIONAL)

RAS CAS DQM WE CLK CKE A10 CS ADDR DATA SDRAM (OPTIONAL)

SERI AL DEVI CE (OPTIONAL)

SERIAL DEVICE (OPTIONAL)

CLKOUT DMAR1-2 DMAG1-2 DMA DEVICE (OPTIONAL) DATA CS HBR HBG REDY BR1-6 PA SBTS ADDR DATA HOST PROCESSOR INTERFACE (O PTIONAL)

SERIAL DEVICE (OPTIONAL)

SPICOMPATIBLE DEVICE (HOST OR SLAVE) (OPTIONAL )

RESET RSTOUT JTAG 7

Figure 7-2. ADSP-21161 Processor System

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External Memory Interface

Table 7-1. External Memory Interface Signals

Pin ACK Type I/O/S Function Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-21161 processor deasserts ACK as an output to add wait states to a synchronous access of its IOP registers. ACK has a 20 k internal pull-up resistor that is enabled during reset or on processors with ID2-0=00x. External Bus Address. The ADSP-21161 processor outputs addresses for external memory and peripherals on these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the IOP registers of other ADSP-21161 processors while all other internal memory resources can be accessed indirectly via DMA control (that is, accessing IOP DMA parameter registers). The ADSP-21161 processor inputs addresses when a host processor or multiprocessing bus master is reading or writing its IOP registers. A keeper latch on the processors ADDR23-0 pins maintains the input at the level it was last driven. This latch is only enabled on the processors with ID2-0=00x. Sequential Burst Access. BRST is asserted by ADSP-21161 processor to indicate that data associated with consecutive addresses is being read or written. A slave device samples the initial address and increments an internal address counter after each transfer. The incremented address is not pipelined on the bus. A master ADSP-21161 processor in a multiprocessor environment can read slave external port buffers (EPBx) using the burst protocol. BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that, except for the last data request cycle (denoted by RD or WR asserted and BRST negated). A keeper latch on the processors BRST pin maintains the input at the level it was last driven. This latch is only enabled on processors with ID2-0=00x.

ADDR23-0

I/O/T

BRST

I/O/T

I (Input), S (Synchronous), o/d (Open Drain), O (Output), A (Asynchronous), a/d (Active Drive), T (Three-state, when SBTS or HBR is asserted, or when the processor is a bus slave)

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External Port

Table 7-1. External Memory Interface Signals (Contd)

Pin CLKIN Type I Function Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21161 processor clock input. It configures the ADSP-21161 processor to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21161 processor to use the external clock source such as an external clock oscillator.The ADSP-21161 processor external port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the CLKIN frequency; it is programmable at power-up via the CLK_CFG1-0 pins. CLKIN may not be halted, changed, or operated below the specified frequency. Local Clock Out. CLKOUT is 1x or 2x and is driven at either 1x or 2x the frequency of CLKIN frequency by the current bus master. The frequency is determined by the CLKDBL pin. This output is three-stated when the ADSP-21161 processor is not the bus master. A keeper latch on the processors CLKOUT pin maintains the output at the level it was last driven. This latch is only enabled on processors with ID2-0=00x. If CLKDBL enabled, CLKOUT = 2xCLKIN If CLKDBL disabled, CLKOUT = 1xCLKIN Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1xCLKIN or 2xCLKIN. Do not use CLKOUT in multiprocessing systems. Use CLKIN instead.

CLKOUT

O/T

I (Input), S (Synchronous), o/d (Open Drain), O (Output), A (Asynchronous), a/d (Active Drive), T (Three-state, when SBTS or HBR is asserted, or when the processor is a bus slave)

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Table 7-1. External Memory Interface Signals (Contd)

Pin DATA47-16 Type I/O/T Function External Bus Data. The ADSP-21161 processor inputs and outputs data and instructions on these pins. Pull-up resistors on unused data pins are not necessary. A keeper latch on the processors DATA47-16 pins maintains the input at the level it was last driven. This latch is only enabled on the processors with ID2-0=00x. Note: DATA[15:8] pins (multiplexed with L1DATA[7:0]) can also be used to extend the data bus if the link ports are disabled and not used. In addition, DATA[7:0] pins (multiplexed with L0DATA[7:0]) can also be used to extend the data bus if the link ports are not used. This allows execution of 48-bit instructions from external SBSRAM (system clock speed-external port), SRAM (system clock speed-external port) and SDRAM (core clock or one-half the core clock speed). The IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1-0 = 0x1) to enable this full instruction Width/No-packing Mode of operation. Link Port Data (Link Ports 0-1). Each LxDAT pin has a 50 k internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register. Note: L1DATA[7:0] are multiplexed with the DATA[15:8] pins L0DATA[7:0] are multiplexed with the DATA[7:0] pins. If link ports are disabled and are not be used, then these pins can be used as additional data lines for executing instructions at up to the full clock rate from external memory. Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of external memory. Memory bank sizes are fixed to 16 Mwords for non-SDRAM and 64 Mwords for SDRAM. The MS3-0 outputs are decoded memory address lines. In asynchronous access mode, the MS3-0 outputs transition with the other address outputs. In synchronous access modes, the MS3-0 outputs assert with the other address lines; however, they de-assert after the first CLKIN cycle in which ACK is sampled asserted. In a multiprocessor systems, the MSx signals are tracked by slave SHARCs.

LxDAT7-0 [DAT15-0]

I/O [I/O/T]

MS3-0

I/O/T

I (Input), S (Synchronous), o/d (Open Drain), O (Output), A (Asynchronous), a/d (Active Drive), T (Three-state, when SBTS or HBR is asserted, or when the processor is a bus slave)

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Table 7-1. External Memory Interface Signals (Contd)

Pin RD Type I/O/T Function Memory Read Strobe. RD is asserted whenever ADSP-21161 processor reads a word from external memory or from the IOP registers of other ADSP-21161 processors. External devices, including other ADSP-21161 processors, must assert RD for reading from a word of the ADSP-21161 processor IOP register memory. In a multiprocessing system, RD is driven by the bus master. RD has a 20 k internal pull-up resistor that is enabled for processors with ID2-0=00x. Memory Write Low Strobe. WR is asserted when ADSP-21161 processor writes a word to external memory or IOP registers of other ADSP-21161 processors. External devices must assert WR for writing to ADSP-21161 processor's IOP registers. In a multiprocessing system, WR is driven by the bus master. WR has a 20 k internal pull-up resistor that is enabled for processors with ID2-0=00x.

WR

I/O/T

I (Input), S (Synchronous), o/d (Open Drain), O (Output), A (Asynchronous), a/d (Active Drive), T (Three-state, when SBTS or HBR is asserted, or when the processor is a bus slave)

Banked External Memory

The processor divides external memory into four equal-size, fixed banks. Bank sizes are 16 Mword for non-SDRAM and 64 Mword for SDRAM. By mapping peripherals into different banks, systems can accommodate I/O devices with different timing requirements. For information on configuring these memory banks for waitstates and synchronous or asynchronous access modes, see Setting Data Access Modes on page 5-32. On the ADSP-21161 processor, Bank 0 starts at address 0x20 0000 in external memory and is followed in order by Banks 1, 2, and 3. When the processor generates an address located within one of the four banks, the processor asserts the corresponding memory select line, MS3-0.

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The MS3-0 outputs serve as chip selects for memories or other external devices, eliminating the need for external decoding logic. For more information, see Timing External Memory Accesses on page 7-13. The MS3-0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring, the MS3-0 lines are inactive. Unlike previous SHARCs, strobe assertion for conditional instructions occurs only when the instruction condition code evaluates as true.

Boot Memory
Most often, the processor only asserts the BMS memory select line when the processor is reading from a boot EPROM. This line allows access to a separate external memory space for booting. Both ROM boot memory waitstates and the mode of the WAIT register are applied to BMS-selected accesses. The BMS output is only driven by the processor bus master. For more information on booting, see Bootloading Through The External Port on page 6-70 or Bootloading Through The Link Port on page 6-88. It is also possible to write to boot memory using BMS. For more information, see Using Boot Memory on page 5-35. Idle Cycle A bus idle cycle is an inactive bus cycle that the processor automatically generates to avoid data bus driver conflicts. Such a conflict can occur when a device with a long output disable time continues to drive after RD is deasserted while another device begins driving on the following cycle. Idle cycles are also required to provide time for a slave in one bank to three-state its ACK driver, before the slave in the next bank enables its ACK

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driver in the synchronous access modes. Figure 7-3 shows idle cycle insertion between a synchronous read and a zero-wait, synchronous write in cycle 3.
READ OP 1 CLKIN ADDRESS 23:0 MS3-0 RD WR BRST DATA 47:16 ACK 2 IDLE CYCLE 3 WRITE OP 4 5

Figure 7-3. Idle Cycle Example All timing diagrams show the default data bus width DATA [47:16]. When the full bus is enabled for 48-bit non-packed execution of instructions or transfers of data with the PX register, the data bus width is 48 bits, DATA47:0.

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To avoid this data bus driver conflict, the processor generates an idle cycle in the following cases: On a transition from a read operation to a write operation in the same bank. On a transition from one bank or multiprocessor memory ID space to any other bank or multiprocessor slave ID space, independent of access mode. Unlike previous SHARCs, the ADSP-21161 processor does not support idle cycle insertion on a page boundary crossing. Data Hold Cycle The data hold cycle is another configurable memory access feature for adding cycles much like waitstates, as discussed in Setting Data Access Modes on page 5-32. A hold time cycle is an inactive bus cycle that the processor automatically generates at the end of a read or write to allow a longer hold time for address and data. The address, data (if a write), and bank select (if in banked external memory) remain unchanged and are driven for one cycle after the read or write strobes are deasserted. The processor inserts the data hold cycle only in asynchronous mode and only if the number of programmed waitstates code (EBxWS) is 010-111. Figure 7-4 demonstrates a hold time cycle appended to an asynchronous write access (EBxWS=011). The ADSP-21161 processor does not append an Idle cycle after a Hold cycle. Multiprocessor Memory Space Waitstates and Acknowledge Multiprocessor memory space uses only the synchronous transfer protocols, using the zero-waitstate access for writes and a minimum one-waitstate access for reads. Slave processors deassert ACK if more access

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WRITE OPERATION 1 CLKIN ADDRESS 23:0 MS3-0 WR DATA 47:16 2 3 4

HOLD TIME CYCLE 5

Figure 7-4. Hold Time Cycle Example time is required. DMA burst transfers are only defined for direct read access of a processor slaves external port buffers (EPBx). For more information, see Multiprocessor (MP) Interface on page 7-87. The ADSP-21161 processor does not support the MMSWS bit from previous SHARCs.

Timing External Memory Accesses

Memory access timing for external memory space and multiprocessor space is the same. For exact timing specifications, refer to the ADSP-21161N DSP Microcomputer Data Sheet. The processor can interface to external memories and memory-mapped peripherals that operate asynchronously with respect to CLKIN. The processor also supports synchronous external memories and memory-mapped peripherals. Synchronous devices derive all of their bus timing from CLKIN of the processor.

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with CLKDBL tied low can be used as a clock source to peripherals only in single processor systems.
CLKOUT

The synchronous interface mode supports DMA burst transfers, which can significantly improve bus throughput for large, contiguous block transfers. The synchronous interface protocols are compatible with Synchronous Burst SRAMS (SBSRAMs) from a variety of vendors. In a multiprocessing system, the ADSP-21161 processor must be the bus master in order to access external memory. When interfacing to synchronous external memories, CLKIN must be used to provide the clock source to the synchronous device. Asynchronous Mode Interface Timing Figure 7-5 shows typical timing for an asynchronous read or write of external memory. Here, the CLKIN clock signal indicates that the access occurs within a single CLKIN cycle. All timing for the master processor is derived synchronously from CLKIN. The asynchronous slave mode modifies the basic synchronous access to better support slaves whose timing is not derived from CLKIN. Figure 7-6 shows timing relationships used by the asynchronous external access mode. In this mode, The strobes assert and deassert based on timing derived from an internal clock whose frequency is twice that of the core clock. (This differs from synchronous mode where the strobes assert from the same edge.) The trailing edge timing is derived from the rising edge of the internal version of CLKIN. The MSx memory select lines are held stable for the entire access. (This differs from synchronous read or synchronous writeminimum 2-cyclemodes where the memory select lines are deasserted after the first cycle of the transfer that uses ACK.)

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CLKIN ADDRESS[23:0] MS3-0 RD or WR (WRITE) DATA 47:16 (READ) DATA 47:16 ACK WRITE DATA READ/WRITE ADDRESS

Figure 7-5. External Memory Asynchronous Access Cycle For read operations, DATA47:16 are sampled by the processor on the rising edge of the RD. This differs from synchronous mode where DATA47:16 are sampled by the internal version of CLKIN. Asynchronous memories or memory mapped devices that require added waitstates through the deassertion of ACK must be configured for a minimum of one internal waitstate due to a potential lack of sufficient decode time for ACK delay from address/selects Refer to ADSP-21161N DSP Microcomputer Data Sheet for timing specifications. Asynchronous Mode ReadBus Master Processor bus master reads of external memory, in asynchronous mode, occur with the following sequence of events as shown in Figure 7-5. 1. The processor samples ACK synchronously. If ACK is asserted, the processor drives the read address and asserts a memory select signal (MS3-0) to indicate the selected bank. A memory select signal is not

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1 CLKIN ADDRESS 23:0 MS3-0 BRST RD WR ACK DATA 47:16 D0 A0

Figure 7-6. Asynchronous Access Timing Derivation deasserted between successive accesses of the same memory bank. If ACK is sampled deasserted, the processor waits one CLKIN cycle to sample ACK again. 2. The processor asserts the read strobe. 3. The processor checks whether waitstates are needed. If so, the memory select and read strobe remain active for additional cycles. Waitstates are determined by a combination of the state of the external acknowledge signal (ACK) AND the internally programmed waitstate count.

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4. The processor deasserts the read strobe in the cycle where no further waitstates are indicated. The data bus (DATA47:16) is sampled on the rising edge of the read strobe. 5. If a hold cycle is programmed for the accessed bank (via the EBxWS parameter of the WAIT register), the address bus and memory selects are held stable for an additional cycle. If initiating another read memory access to the same bank, the processor drives the address and memory select for that access in the next cycle. Asynchronous Mode WriteBus Master Processor bus master writes to external memory, in asynchronous mode, occur with the following sequence of events as shown in Figure 7-5. 1. The processor samples ACK synchronously. If ACK is asserted, the processor drives the write address and asserts a memory select signal (MS3-0) to indicate the selected bank. A memory select signal is not deasserted between successive accesses of the same memory bank. The processor also drives the write data (DATA47:16). If ACK is sampled deasserted, the processor waits one CLKIN cycle to sample ACK again. 2. The processor asserts the write strobes. 3. The processor checks whether waitstates are needed. If so, the memory select and write strobe remain active for additional cycles. Waitstates are determined by a combination of the state of the external acknowledge signal (ACK) AND the internally programmed waitstate count. 4. The processor deasserts the write strobes near the end of the cycle where no further waitstates are indicated. 5. The processor three-states its data outputs, unless the next access is also a write to the same bank, or if a hold cycle is programmed for the accessed bank using the EBxWS parameter of the WAIT register. If

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a Hold cycle is inserted, the address bus, data bus, and memory selects are held stable for an additional cycle. If initiating another memory access to the same bank, the processor drives the address and memory select for the next access in the following cycle. Synchronous Mode Interface Timing Any slave addressed by a processor in a bank configured for synchronous transfer mode must use a clock with frequency and phase characteristics similar to CLKIN on the processor. The slave samples all inputs, and drives all outputs on the rising edge of this clock. Except for zero-waitstate writes, the slave must assert ACK at least twice for each access; once to acknowledge the address/command (strobe assertion) and once (if not a burst) or more to acknowledge the data transfer. Due to insufficient decode time, the first ACK can be due to the keeper latch (internal pullup enabled for ID=00x) holding the assertion of ACK from the previous slave. The following notes apply to all synchronous access modes: A slave recognizes the start of a valid bus operation by synchronously sampling one or more of the strobes and ACK asserted. ACK assertion is by the previous bus slave, allowing a new bus access to launch. For each of the non-burst, synchronous read/write accesses (except zero-waitstate writes), the master recognizes the end of the access as the cycle in which: 1. The slave samples or drives data in response to a valid operation driven by the master (read or write), 2. The slave asserts ACK to the master (except for zero-waitstate write operations), and

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3. The number of waitstates for read or write access to that bank has occurredasserting ACK does not terminate the wait count early. The program must select a number of waitstates that is consistent with the access time for the slave addressed by that external memory bank. For the zero-waitstate writes, the access can only be extended beyond one clock cycle by deasserting ACK in the cycle of the transfer. This extension can occur on back-to-back writes in which ACK is deasserted due to full write buffer capacity from the previous write. Otherwise, slaves can asynchronously deassert ACK in the first cycle. Deasserting ACK during the initial command phase does inhibit waitstate count and change of bus signals. After the first ACK assertion, deasserting ACK for the data phase does not inhibit waitstate counting. Only one slave (or driver for ACK) should be allocated per external memory bank. More than one slave may introduce ACK drive contention. The read/write strobes for an access do not assert until ACK is sampled asserted. This conditional strobe assertion delays the start of an access until ACK is asserted by the previous slave. This sampling is because the slave target of a single-cycle write operation may have deasserted ACK in the cycle (due to a previous write access), to stall further writes to that slave. To provide a cycle for the previous slave to three-state its ACK driver before the next slave drives ACK, the next operation to a new bank must not launch on the bus.

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Write/read access stalls (no state change, other than internal waitstate counting) on the bus if ACK is deasserted in cycle(s) of data transfer. The last read/write operation must be acknowledged via ACK before a transition to a new bus master (BTC), bank, or multiprocessor space slave occurs. The master always inserts an Idle cycle on this transition. No pipelining can occur across these boundaries. Synchronous Mode ReadBus Master An example synchronous read cycle appears in Figure 7-7. Propagation delays are not shown in this timing diagram. Because a synchronous access requires a rising clock edge for the slave to sample the asserted signals of the master (and for the master to sample the signals of the slave), the minimum read access in the synchronous mode is two CLKIN cycles. In synchronous access mode, the waitstate selection in the WAIT register (EBxWS) must be 001 or greater. EBxWS=000 is not supported in synchronous access mode. This example demonstrates a minimum latency, one-waitstate, 32-bit (normal word) read, from external memory. Bus master synchronous reads from external memory occur with the following sequence of events as shown in Figure 7-7: 1. (cycle 1) If ACK is sampled as asserted at the beginning of cycle 1, the processor drives the read address and asserts a memory select signal (MS3-0) to indicate the selected bank. The processor asserts the RD strobe. The read strobe is not deasserted between successive read accesses of the same memory bank. 2. (cycle 2) If ACK was sampled as deasserted at the beginning of the cycle (not shown), the MSx strobes would remain asserted. If ACK was sampled asserted, the MSx strobes would deassert. The slave must be capable of detecting that MSx was asserted in cycle 1 and

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must retain this information internally. If ACK was deasserted by the previous slave (for a single-cycle write), deassertion of the MSx is delayed.

1 CLKIN ADDRESS 23:0 MS3-0 RD WR BRST DATA 47:16 ACK

Figure 7-7. Typical Synchronous Read Timing 3. (cycle 2) The processor checks whether more than one waitstate is needed. If so, the read strobe remains active for additional cycle(s). Waitstates are determined by a combination of the state of the external acknowledge signal (ACK) AND the programmed waitstate count. 4. (end of cycle 2) The data bus (DATA47:16) is sampled on the rising edge of CLKIN.

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5. (cycle 3) If initiating another read memory access to the same bank, the processor drives the address, memory select, and strobe for the next access. Figure 7-8 shows back-to-back reads to the same bank with the second access stalled for one cycle by the slave deasserting ACK. This example assumes that the EBxWS=001 for this bank, indicating one internal waitstate. Synchronous Write, Zero-Waitstate Mode Figure 7-9 on page 7-24 shows typical synchronous write cycle timing. Propagation delays are not shown in this timing diagram. Synchronous access requires a rising clock edge for the slave to sample the asserted signals of the master (and for the master to sample the signals of the slave). In the case of writes, the latency can be reduced to a single cycle if the slave always latches the bus signals on each clock cycle (it does not sample ACK). For example, the slave can not sample the bus, decode that it is being addressed as a slave, and sample the write data of the bus in the following cycle. The slave samples the bus each cycle and decodes the sampled value to determine if that slave was addressed by the write operation. If the slaves write queue goes full with that write, the slave deasserts ACK in the cycle after the write operation transferred on the bus. Any subsequent bus operation (read or write) stalls until ACK is sampled asserted, as shown in cycle 2 of Figure 7-9. The example demonstrates a minimum latency, zero-waitstate, 32-bit write in cycle 1 followed by a write to the same bank. This write stalls because ACK is deasserted in cycle 2 in response to the write in cycle 1. The second access is a 32-bit write to external memory. The zero-waitstate write mode provides the highest performance if the slave has sufficient write buffer storage. Systems should use this mode where the slave can always accept one write transfer (unless ACK is deasserted) and can generally accept more than one write. If the slave has only one store buffer, such that it always deasserts ACK after the first write, the

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1 CLKIN ADDRESS 23:0 MS3-0] RD WR BRST DATA 47:16 ACK

Figure 7-8. Two Synchronous Reads From Same Bank one-waitstate write mode may be the better choice. The zero-waitstate write mode is targeted towards ASIC/FPGA designs, which implement multiple write buffers (including processor as a slave), and fully pipelined synchronous devices such as SBSRAMs. Slaves that do not support bursting protocols do not need to connect to the BRST signal.

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1 CLKIN ADDRESS 23:0 MS3-0 RD WR BRST DATA 47:16 ACK WRITE #1 WRITE #1

WRITE #2

WRITE #2 STALL 2ND WRITE

Figure 7-9. Typical Synchronous Write Example Bus master synchronous writes to external memory occur with the following sequence of events as shown in Figure 7-9: 1. (cycle 1 in Figure 7-9) If ACK is sampled asserted at the start of cycle 1, the processor bus master drives the write address and asserts a memory select signal (MS3-0) to indicate the selected bank. The processor asserts the WR strobe. The write strobe is not deasserted between successive write accesses of the same memory bank. 2. (cycle 1) The previous slave three-states ACK. Note that the previous slave could have driven ACK deasserted through cycle 1 if a write in the previous cycle caused its write queue to fill. Only one slave is supported per bank, and any bank transition has an IDLE cycle inserted to provide time for the slave to three-state ACK.

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3. (cycle 2) The processor is initiating another write memory access to the same bank. It drives the address, memory select, and strobe for the next access. 4. (cycle 2) The slave, having decoded that it received a valid write operation in the previous cycle, detects that it cannot accept further bus operations until an element in the write queue becomes available, so it deasserts ACK. 5. (cycle 3) The processor samples ACK deasserted by the slave. It inserts waitstates until ACK is sampled asserted. The write ends in the cycle where ACK is asserted by the slave (end of cycle 3). Figure 7-10 shows a zero waitstate write, followed by a synchronous read from the same bank. The slave addressed by both accesses determines in cycle 2 that it has no more write capacity. It deasserts ACK in this cycle, in response to the write in cycle 1. In cycle 3, the slave determines that it is now addressed by the master to perform a read and asserts ACK to acknowledge the transfer. The slave asserts ACK in cycle 4 when read data is available to complete the data transfer. The memory select for the read access is held asserted by the master until cycle 4, because ACK was deasserted in cycle 2. Synchronous Write, One Waitstate Mode Because some synchronous slaves cannot support a free-running latch function to capture zero-wait bus writes, the processor also supports a minimum two-cycle (minimum one-waitstate) write access. This mode is set using the bank Access Mode bits (EBxAM). For more information on access modes, see Table A-20 on page A-66. The one-waitstate, synchronous write access is shown in the second write of Figure 7-11. In this example, the first access is to a bank configured for asynchronous writes (cycle 1). In Figure 7-11, this condition is shown by the deassertion of the write strobe before the rising edge of CLKIN for cycle 2. In cycle 2, a bank transition occurs, and an idle cycle is inserted to

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1
CLKIN write address ADDRESS 23:0 MS3-0 RD WR BRST write data DATA 47:16 ACK

read address

read data

Figure 7-10. Synchronous Write Followed by Synchronous Read Example allow the slaves to transition ownership of ACK. In cycle 3, the second write begins, to a new bank configured for one-waitstate write access. The address and data are held for a minimum of two cycles. Similar to the synchronous read, MSx deassert in the second cycle of the write (cycle 4), and the waitstate counter decrements if ACK is sampled asserted. The access can be held off the bus by deasserting ACK in cycle 2, or extended by deasserting ACK in cycle 3 (unlikely for a synchronous slave) or cycle 4. Synchronous Burst Mode Interface Timing Synchronous burst mode provides improved performance on synchronous operations. The processor supports a DMA-mastered burst mode. If the addressed slave supports this burst transfer, after the one or more waitstates associated with access to the first 32-bit read data transfer,

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contiguous data can transfer on each subsequent clock cycle, up to a maximum of four 32-bit transfers. Burst accesses support only 32-bit data transfers. Partial data bus width transfers are not supported. For burst transfers, the master drives the address of the first access on the bus during the entire burst transfer. The master does not increment the address for the slave. Because the maximum length of the burst transfer is four, slaves only need a 2-bit address incrementer to generate the offset address from the address driven by the master on the bus. Table 7-2 shows burst length determination as a function of initial address. If the DMA channel has sufficient data to transfer, it initiates a new burst transfer starting at ADDR1-0 = 00, 01, or 10 when it wins bus arbitration. Bursts always terminate when ADDR1-0=11.
WRITE #1 1 CLKIN ADDRESS 23:0 MS3-0 RD WR BRST DATA 47:16 ACK IDLE 2 WRITE #2, DIFFERENT BANK 3 4

Figure 7-11. Asynchronous Write Followed By Synchronous Write One-Waitstate Mode ADSP-21161 SHARC Processor Hardware Reference 7-27

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Table 7-2. Linear Burst Address Order

First Address[1:0] (external) 00 01 10 11 1 2 Second Address (internal) 01 10 11 Burst Terminated2 Master always terminates burst when internal address[1:0] = 11 Master transfers this case as a single synchronous access Third Address (internal) 10 11 Burst Terminated1 Fourth Address (internal) 11 Burst Terminated1

An example of a synchronous burst read of length three appears in Figure 7-12. Here, the bank used in the transfer has two waitstates.

1 CLKIN ADDRESS 23:0 MS3-0 RD WR BRST DATA 47:16 ACK

ADDRESS[1:0] = 01

Figure 7-12. External Memory Synchronous Burst Read Example

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Burst Length Determination The DMA arbitration logic reduces the initial access latency by bursting up to the maximum burst length of four when possible, assuming the channel is burst enabled. When a DMA channel wins internal I/O processor arbitration, the channel drives the internal buses as with a non-burst transfer. At the same time, the I/O processor detects whether it can perform a burst transfer, according to the following criteria: 1. The DMAC burst enable (MAXBL1-0) control bit field is set for that DMA channel. 2. The EM register is set to 0 or 1. A value of 0 does not increment EI. This is useful when bursting to or from a registered data port, buffer, or register, such as the EPBx FIFOs of another processor. 3. The EC register is greater than or equal to two (32-bit) words. 4. The EPBx FIFO for that channel has at least two 32-bit words to transfer for an external burst write or has at least two empty 32-bit elements to receive data for an external burst read. 5. The two least significant bits of the DMA channel external address are not set (ADDR1-0 does not equal 11). Burst Stall Criteria If the I/O processor determines that it can perform a burst transfer (according to the burst length criteria), the arbitration between the processor core and the I/O processor locks the effective arbitration grant to that DMA channel until: 1. The DMA channel external ADDR1-0 = 11. By disconnecting the burst on this boundary, a modulo4 (ADDR23-0) is effectively implemented, which is required by SBSRAMs, and other slaves with

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limited address incrementing capability. For processor-based systems, slaves only need a 2-bit counter to support the address incrementing function of the burst. 2. Space in the EPB FIFO drops to less than two 32-bit elements (if an external bus read), or less than four valid 32-bit elements for external bus writes. This almost full or empty detection is required by the master logic to deassert BRST on the cycle before the end of the burst. 3. 4.
EC

goes to < 2; the burst pin must negate at EC=1.

and SBTS are asserted on the external bus, indicating the deadlock resolution case in which the processor must three-state its outputs and switch into slave mode. For more information, see Deadlock Resolution on page 7-82. Assertion of either signal alone does not terminate the burst early. HBR assertion does not receive an HBG until the burst finishes. SBTS assertion causes the master to three-state outputs and insert waitstates.
HBR

If any of these conditions occur, normal arbitration between the processor core and I/O processor for the external bus occurs. If the same bursting channel wins arbitration again, a new burst is initiated, introducing at least one lost or dead cycle in the burst throughput for reads. When arbitration occurs, the DMA channel loses arbitration if any of the following conditions are detected: 1. Higher priority external request for the bus: a. b. c.
HBR BRx BRx

asserted asserted and BMAX time out has occurred asserted and PA asserted, but not by this master

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2. Higher priority internal I/O processor requester: a. Processor core request (DAGs or program sequencer) b. A higher priority request from another DMA channel or direct read/write access causes this channel to lose arbitration. For more information, see I/O Processor on page 6-1. Synchronous Burst Reads External memory synchronous burst reads occur with the following sequence of events as shown in Figure 7-12: 1. (cycle 1 in Figure 7-12) If ACK is sampled asserted at the beginning of cycle 1, the processor drives the read address and asserts a memory select signal (MS3-0) to indicate the selected bank. 2. (cycle 1) The processor asserts RD strobe to indicate a read request of the slave. 3. (cycle 2) As with the non-burst synchronous read, the processor deasserts the MSx output signal, asserts the BRST output signal, and enables waitstate counting if ACK is sampled asserted at the end of cycle 1. 4. (cycle 2) The processor checks whether more than one waitstates (2 waitstates for this example) is needed. If so, BRST and the read strobe remain active for additional cycle(s). 5. (cycle 3) The slave samples BRST asserted, informing it that the master requests at least one more transfer after the current transfer is acknowledged via ACK by the slave. 6. (cycle 3) The programmed number of waitstates has been counted, and the slave is driving 32-bits of valid data and asserting the ACK signal. This ends the first access.

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7. (cycle 4) The slave drives the next 32-bits of contiguous data and asserts ACK. If the slave needs more time to service any one transfer within the burst, it can deassert ACK to stall the bus transfer. 8. (cycle 4) The slave samples BRST asserted, informing it that the master requests at least one more 32-bit transfer. 9. (cycle 5) The master deasserts BRST to inform the slave that this is the last transfer of the burst. In this example, the master deasserts BRST due to the address modulo4 function. The two LSBs of the initial address = 01. The slave increments the address as 01->10->11. This is the maximum offset needed to support from the initial address. 10.(cycle 5) The slave drives valid data for the last transfer, and asserts ACK. 11.(cycle 6) If initiating another burst read memory access to the same bank, the processor asserts the address, memory select, and strobes for the next access. This introduces at least two dead cycles in the back-to-back burst throughput, because the initial waitstate count applies to the first access of the second burst. 12.(cycle 6) With BRST sampled deasserted, the slave concludes its service of the burst request by three-stating the DATA47:16 and ACK drivers. As a master, the processor supports burst reads on each of the four external port DMA channels. Each channel has an independent burst enable control field (MAXBL1-0). As a slave, the processor supports read bursts from the EPBx buffers (with the EPBx read). For more information, see Multiprocessor (MP) Interface on page 7-87 and Host Processor Interface on page 7-42.

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Because reads of the EPBx FIFO are destructive, the processor slave must deassert ACK on each transfer of the burst to guarantee that it samples the deasserted BRST input before performing the EPBx FIFO read. If your system design uses a similar destructive read data buffer, use precaution when burst reads of the buffer are supported. Synchronous Burst Writes The processor can master burst read and write operations in the one-waitstate write access mode (EBxAM=10) if one or more DMA channels are configured appropriately. The processor can master non-burst, zero-waitstate, writes in every cycle. Burst write transfers are not supported in this access mode. Synchronous external devices require at least one cycle of write access latency (for example, bus bridges, SDRAM controllers, and others). These devices may be able to optimize throughput for burst write operations, based on the contiguous, incrementing block transfer information conveyed by the burst protocol. Burst accesses support only 32-bit data transfers; partial data bus width transfers are not supported. An example of a synchronous burst write appears in Figure 7-13. Here, the bank used in the transfer has the one-waitstate mode, for the first write of the burst. External memory synchronous burst writes occur with the following sequence of events as shown in Figure 7-13: 1. (cycle 1 in Figure 7-13) If ACK is sampled asserted at the start of cycle 1, the processor drives the write address and asserts a memory select signal (MS3-0) to indicate the selected bank. The processor also drives valid data in this cycle. The processor asserts the WR strobe to indicate a write command to the slave. 2. (cycle 2) The slave samples the write command and address. At this point, the slave does not see that a burst write is in progressthe access looks identical to a non-burst synchronous write. If the slave

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1 CLKIN ADDRESS 23:0 MS3-0 RD WR BRST DATA 47:16 ACK

ADDRESS[1:0]=00

Figure 7-13. External Memory Synchronous Burst Write Example cannot accept the write command, it deasserts ACK in this cycle to stall the bus until it can. In this example, it has buffer capacity to accept all of the data of the burst, so ACK stays asserted. 3. (cycle 2) If ACK was sampled asserted at the start of the cycle, the processor asserts the BRST output signal and deasserts the MSx output signal. 4. (cycle 3) The processor samples ACK asserted by the slave at the start of the cycle. It increments the data bus to the second of four data transfers within the burst.

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5. (cycle 3) The slave samples BRST asserted at the start of the cycle, informing it that the master is writing at least one more 32-bit transfer. The slave samples the second of four data transfers within the burst and asserts ACK. 6. (cycle 4) The processor samples ACK asserted by the slave at the start of the cycle. It increments the data bus to the third of four data transfers within the burst. 7. (cycle 4) The slave samples BRST asserted at the start of the cycle, informing it that the master is writing at least one more 32-bit transfer. The slave also samples the third of four data transfers within the burst, and asserts ACK. If the slave needs more time to service any one transfer within the burst, it can deassert ACK to stall the bus transfer. 8. (cycle 5) The processor samples ACK asserted by the slave at the start of the cycle. It increments the data bus to the last of four data transfers within the burst. The master deasserts BRST to inform the slave that this is the last transfer of the burst. 9. (cycle 5) The slave samples BRST asserted at the start of the cycle, informing it that the master is writing at least one more 32-bit transfer. The slave samples the fourth of four data transfers within the burst and asserts ACK. 10.(cycle 6) If initiating another write burst memory access to the same bank, the processor asserts the address, memory select, and strobes for the next access. This introduces at least one dead cycle in the back-to-back burst throughput, because the initial waitstate count applies to the first access of the second burst. 11.(cycle 6) With BRST sampled deasserted, the slave concludes its service of the burst request by three-stating the ACK driver.

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As a master, the processor supports burst writes on each of the four external port DMA channels. Each channel has an independent burst enable control field (MAXBL1-0). As a slave, ADSP-21161 processor does not support burst writes. Bursting is enabled by setting MAXBL1-0 to 01 in the DMACx register. Enabling bursting can corrupt data transmitted during DMA master writes because the MAXBL bit setting is not ignored when the BRST signal is asserted. The ADSP-21161 only supports processor-to-processor single cycle writes. Therefore, no improvement in throughput performance is achieved by enabling bursting. To enable ADSP-21161 to ADSP-21161 DMA driven write transfers, set MAXBL1-0 to 00.

Using External SBSRAM

The processor can connect to a variety of synchronous burst static RAMs (SBSRAMs) with a glueless interfaceno external logic required. These synchronous memories can provide high throughput, especially when using the burst read transfer modes. The processor has features to support SBSRAMs from several memory vendors. The processor can support both flow-through and fully-pipelined SBSRAMs. Using flow-through devices delivers lower latency and higher system performance when a system is designed properly.
CLKIN

must be used as the clock source for SBSRAM. You cannot use an external crystal when interfacing with SBSRAM.

Do not use CLKOUT as the clock source for the SBSRAM device. Using an external crystal in conjunction with CLKDBL to generate a CLKOUT frequency is not supported. Negative hold times can result from the potential skew between CLKIN and CLKOUT.

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The processor can support SBSRAMs on any of the four external memory banks. The processor supports SBSRAM single transfer reads and writes and SBSRAM burst read transfer operations. Burst write transfers are not supported, because the single-write feature of SBSRAMs achieves the same throughput level, with less complexity. SBSRAM support is enabled by configuring the bank access mode (EBxAM) bits for synchronous, one-cycle writes and waitstate (EBxWS) bits for one waitstate (flow-through SBSRAMs) or two waitstates (fully pipelined SBRAMs). For more information on programming access modes and waitstates, see the WAIT register bits in Table A-20 on page A-66. If burst read transfer functionality is needed, one or more of the external port DMA channels must be configured appropriately. Because burst transfers are controlled at the DMA channel, the DMA sequence must make sure that the DMA burst transfer addresses a memory bank or slave that supports the read burst transfer. Figure 7-14 and Table 7-3 show how the processor I/O should be connected to the SBSRAM I/O. Table 7-3 assumes a 512 Kbyte SBSRAM array consisting of one bank with a 3.3V, 32K x 32 device. The names of the SBSRAM signals may vary from between vendors. Figure 7-14 is for illustrative purposesactual system designs may differ and must be carefully analyzed to determine the actual system topology. The SBSRAM devices are fully synchronous devices, except for the output enable. The processor issues commands and updates the SBSRAM address latches, as a controller, using the ADSC input of the SBSRAMs, rather than the ADSP processor input. Using the ADSC SBSRAM input enables single cycle writes and simplifies SBSRAM deselect operations.

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ADSP-21161
ADDR[23:0] MS0 BRST RD WR CLKIN DATA[47:16] DATA[47:16]

SBSRAM 32KX32
ADDR[15:0] CE1 ADSC OE GW DATA[31:0] CLK ADSP CE BWE BW[4:1] LBO ADV CE2 ZZ

Figure 7-14. SBSRAM System Interface Example Table 7-3. ADSP-21161 to SBSRAM Signal Mapping
ADSP-21161 CLKIN ADDR15-0 MSx BRST RD WR DATA47:16 No connect No connect No connect No connect No connect No connect SBSRAM CLK ADDR15-0 CE ADSC OE GW DATA31-0 CE CE2 ADSP ADV BWE BW4-1 Comment Clock input of SBSRAM should be driven by CLKIN of the processor. Address connection Chip Enable, active low Address Status Controller, active low Asynchronous Output Enable of SBSRAM, active low Global Write Enable of SBSRAM, active low I/O of SBSRAM (High word of bus, odd address) Chip Enable, active high, always asserted (Vdd) Second Chip Enable, always asserted (GND) Always Deasserted (Vdd) Always Asserted (GND) Byte Write Enable, always deasserted (Vdd) Byte Write Selects, always deasserted (Vdd)

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Table 7-3. ADSP-21161 to SBSRAM Signal Mapping (Contd)

ADSP-21161 No connect No connect SBSRAM LBO ZZ Comment Linear Burst Order, active low, always asserted (GND) Sleep Mode Enable, active high, always deasserted (GND)

By asserting the ADV (advance address) input to the SBSRAM, the device is continuously attempting to burst. This input is ignored when ADSC is asserted. Because the BRST/ADSC signal is always low for a single access or the first access of a burst, the SBSRAM always updates its address latches correctly. For the subsequent transfers (up to three, after the initial access) of a read burst, the SBSRAM samples BRST/ADSC high. The asserted ADV correctly advances the internal address count of the SBSRAM. The processor issues four types of bus operations to the SBSRAMs, as shown in Table 7-4. Table 7-4. SBSRAM Partial Truth Table
SBSRAM Operation Read cycle, begin burst Write cycle, begin burst Read cycle, continue burst Deselect Cycle CE1 MSx L2 L X H ADSC BRST L L H L ADV1 X X L X GW WR H L H X OE RD L H L X I/O Data Hi-Z Data Hi-Z

All other signal inputs held static per Figure 7-14 1 2 ADV statically held asserted, low L=low, H=High, X=dont care, Hi-Z=three-stated, high impedance output

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Single read or write transfers, and the first transfer of a burst read, use the read or write cycle and begin burst bus operation. Burst write transfers are not supported. The subsequent transfers (up to three) of a read burst use the read cycle and continue burst bus operation. The last cycle of any read access performs a deselect bus operation ensure that the SBSRAM data buffers remain three-stated for accesses to other banks. The write operations are achieved by configuring the appropriate bank of the processor to synchronous minimum one-cycle write mode. The synchronous read waitstate count should be programmed to one for flow-through SBSRAMs, or two for fully pipelined SBSRAMs. SBSRAMs are not stalled, or suspended, by assertion of ACK in this configuration. Systems should not deassert ACK during any SBSRAM access. The processor has a weak pullup device on ACK; ACK does not need to be driven during an access to a slave which does not or cannot control ACK. Figure 7-15 demonstrates a burst read of the flow-through SBSRAM, followed by a single write to the SBSRAM, and a single read of the SBSRAM. For burst operations, the deasserting BRST is not required in the last cycle of the burst transfer. The processors burst protocols also support ASIC/FPGA systems. The pipelined end-of-burst indicator may be useful in these systems. The SBSRAM array size can be increased from the example by using higher density devices or implementing multiple banks of SBSRAM. Multiple banks are possible using the depth expansion feature of the SBSRAMs and the multiple memory select outputs of the processor.

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1 CLKIN ADDRESS 23:0 MS0 (CE) BRST (ADSC) RD (OE) WR (GW) ACK DATA 47:16

10

A0 DESELECT CYCLE

B1

C1 DESELECT CYCLE

IDLE CYCLE

A0

A1

A2

A3

B1

C1

Figure 7-15. SBSRAM Burst Read, Single Write, Single Read

SBSRAM Restrictions
SBSRAM (or other synchronous peripherals such as bridge chips) is restricted using the same external clock generator source provided to the CLKIN pin of the processor. Do not use CLKOUT as the clock source to the SBSRAM. The clock source connected to both the CLKIN and the clock input of the SBSRAM must be a clock source provided by an external oscillator or other clock source. External crystals in conjunction with the internal clock generator (and CLKDBL) should not be used to generate a CLKOUT source for the SBSRAM.

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Host Processor Interface

The ADSP-21161 processors host interface supports connecting the processor to 8-, 16- or 32-bit microprocessor buses. By providing an address, a data bus, and memory control signalssuch as read, write and chip selecta host may access any device on the processor bus as if it were a memory. The processor accommodates asynchronous data transfers, allowing the host to use a different clock frequency. For maximum host throughput and low and high pulse widths for WR and RD, refer to the ADSP-21161N processor Microcomputer Data Sheet. The ADSP-21161 processor host processor interface does not support synchronous data transfers. Figure 7-16 shows an example of how to connect a host processor to the ADSP-21161 processor and Table 7-5 defines the processor pins used in host processor interfacing. The host accesses the ADSP-21161 processor through its external port. Figure 6-5 on page 6-23 shows a block diagram of the external port, I/O processor, and FIFO data buffers, illustrating the on-chip data paths for host-driven transfers. The four external port DMA channels are available for use by the hostDMA transfers of code and data can be performed with low software overhead. The host processor requests and controls the processors external bus with the host bus request (HBR) and host bus grant (HBG) signals. Host logic does not need to duplicate the distributed multiprocessor arbitration protocol of the DSPs. After the host gets control of the bus, the host transfers data asynchronously. The host bus may be 8-, 16-, or 32-bits wide for asynchronous transfers. The host also uses the chip select (CS) and ready (REDY) signals. After getting control of the bus, the host can read and write to any of the processors I/O processor registers, including the EPBx FIFO buffers. The host uses I/O processor registers such as SYSCON and SYSTAT to control and

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HBG REDY HBR ADSP-21161 BR1-BR6 3 ADDR23-0 SYSTEM BUS INTERFACE SYSTEM DATA BUS

DATA47:16 ID2-0 HBR HBG REDY CS WR RD ACK MS3-0 RD EXTERNAL MEMORY ADDR DATA WE OE ACK CS HBR CS ADDRESS COMPARATOR "ADDRESS VALID" REDY DSP BUS ACK SYSTEM BUS SYSTEM ADDRESS BUS WR HBG OE T/R

000

Figure 7-16. Example Processor to Host System Interface monitor the processor and to set up DMA transfers. DMA transfers are controlled by the processors I/O processor after they are set up by the host. In a multiprocessor system, the host can access the I/O processor registers of every ADSP-21161. Data written to and read from the processor can be packed or unpacked into different word widths. The host bus width control bits (HBW) in the SYSCON register configure data packing and unpacking.

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Table 7-5. Host Interface Signals

Signal HBR Type I/A Definition Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21161 processor's external bus. When HBR is asserted in a multiprocessing system, the ADSP-21161 processor that is bus master relinquishes the bus and asserts HBG. To relinquish the bus, the ADSP-21161 processor places the address, data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-21161 processor bus requests (BR6-1) in a multiprocessing system. Host Bus Grant. HBG acknowledges an HBR bus request, indicating that the host processor may take control of the external bus. HBG is asserted (held low) by the processor until HBR is released. In a multiprocessing system, HBG is output by the processor bus master and is monitored by all others. Chip Select. Asserted by host processor to select the ADSP-21161 processor.

HBG

I/O

CS

I/A

I=Input, S=Synchronous, (o/d)=Open Drain, O=Output, A=Asynchronous, (a/d)=Active Drive

Acquiring the Bus

For a host processor to gain access to the processor, the host must first assert HBR, the host bus request signal. HBR has priority over all BRx multiprocessor bus requests. When asserted, HBR causes the current master to

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give up the bus to the host after the it finishes the current bus operation. If the current operation is a burst transfer, the change in bus mastership interrupts the transfer on a modulo4 boundary. The current bus master signals that it is transferring ownership of the bus by asserting HBG (low) when the current bus operation ends. The cycle in which control of the bus is transferred to the host is called a Host Transition Cycle (HTC). Bus slaves respond to HBG assertion with or without the assertion of HBR. Therefore erroneous assertions of HBG (glitching, etc.) can cause slave DSPs to believe that the host is the current bus master. Figure 7-17 shows the timing for the host acquiring the bus. HBG is asserted while the bus master releases control of the bus and remains asserted until HBR is sampled deasserted by the ADSP-21161 processor. The cycle in which control of the bus is released by the bus master is called the processors Bus Transition Cycle (BTC). HBG freezes the multiprocessor bus arbitration during the time that the host has control of the bus. HBG may be used to enable the hosts signal buffers, as shown in Figure 7-16 on page 7-43, Figure 7-24 on page 7-80, and Figure 7-25 on page 7-81. Arbitration is frozen due to the current bus master continuously asserting its BRx. While HBG is asserted in a multiprocessor system, the DSPs continue to assert their BRx outputs, as in normal operation, but no BTC occurs. The current bus master keeps its BRx output asserted throughout the entire time the host controls the bus. After HBR is asserted, and before HBG is given, HBG floats for 1 tCK (1 CLKIN cycle). To avoid erroneous grants, HBG should be pulled up with a 20k to 50k external resistor. After the host gets control of the bus, the host can perform transfers with the processor or other system components. To initiate transfers, the host asserts (low) the CS and HBR inputs of the processor that it intends to access and performs the read or write. The processor does not respond to CS until HBG is asserted.

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The host may also communicate directly with system peripherals, such as SBSRAMs. These transfers occur using the protocol of the peripheral or using the external handshake mode of DMA channels 10 and 11 to control the memory or peripheral. With DMA handshaking, the host only needs to source or sink the data with the correct timing. Either of these solutions may require additional hardware support for the host. The host is responsible for driving the following signals during the HTC in which it gains control of the bus: ADDR23-0, RD, WR, and DMAGx (if used in the system). These signals must be driven by the host while the host is bus master. Also, the host must drive or weakly pull up or down the MS3-0, BRST, CLKIN, DMAG1, and DMAG2 signals as required. The bus master three-states these lines, letting the host use them. The processor with device ID=000 or 001 enables internal pullup devices on the MS3-0, RD, WR, DMAR1, DMAR2, DMAG1, and DMAG2 signals. The pullup provides a weak current source to hold these signals in the deasserted state when driven to that state. Excessive system noise can cause these weakly driven signals (MS3-0, RD, WR, DMAR1, DMAR2, DMAG1, and DMAG2) to be sampled asserted. The processor with device ID=000 or 001 enables its keeper latches on ADDR23-0 and DATA47-16, BRST, and CLKOUT, so these signals are weakly pulled to the last value driven on them if any of these signals remain undriven for multiple cycles. During read-modify-write operations, the host should keep HBR asserted to avoid temporary loss of bus mastership. HBR must remain asserted until after the host completes the last data transfer.

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1 CLKIN HBR CS REDY HBG BRx ADDR 23:0 MSx A0

Host Address

A1

WR RD DATA 47:16 ACK D0 Host Data D1

Figure 7-17. Example Timing for Host Acquisition of Bus

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The following restrictions apply to bus acquisition by the host: If HBR is asserted while the processor is in reset, it does not respond with HBG until after reset and multiprocessor synchronization is completed. The host should keep HBR asserted until after the host completes its last data transfer and is ready to give up bus ownership. If SBTS is asserted after HBR, the processor enters slave mode and suspends any unfinished access to the external bus. In uniprocessor systems (with ID2-0=000), the host must assert CS in the same cycle as HBR to initiate an asynchronous access. After the host finishes its task, it can relinquish control of the bus by deasserting HBR. The bus master responds by deasserting HBG in the cycle after sampling HBR deasserted. In the cycle following deassertion of HBG, the bus master assumes control of the bus and normal multiprocessor arbitration resumes.

Asynchronous Transfers
To initiate asynchronous transfers after acquiring control of the processors external bus, the host must assert the CS input of the processor to be accessed. The host then drives the address of the I/O processor register to access. To simplify the hardware requirements for external interface logic, only the address bits shown in Table 7-6 need to be driven.

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Table 7-6. Address Fields For Asynchronous Host Accesses

Address Bits1 ADDR8-0 ADDR16-9 ADDR19-17 ADDR20 or ADDR23-21 ADDR25-24 ADDR27-26 1 2 E field2, One of these bits must be 1. V field2, virtual. V field2, virtual, MSx. Comments Must be driven in all cases. Floating S field2, floating M field2, must be 0

Setup and hold times for these address lines are specified in the Data Sheet. For a complete description of these address fields, see Multiprocessor Memory on page 5-19.

Table 7-6 applies to all asynchronous host access cases, including multiprocessor systems. Fewer address bits may need to be driven depending on the system. For example, in a uniprocessor system, the host does not need to drive the ADDR20 address pins. Use the following guidelines when designing a system that uses asynchronous host accesses. A host can only access IOP register space on the ADSP-21161 processor. The ADSP-21161 processor now uses 9 address lines to access the IOP registers. The ADSP-21161 processor does not support the Instruction Word Transfer (IWT) function from previous SHARC DSPs. 48-bit instructions can be transferred by configuring the host packing mode to one of the 48-bit internal transfer modes.

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Host accesses to non-existent IOP register addresses are not supported. These accesses result in a host bus grant (HBG) hang. Therefore, ensure that host accesses generate valid IOP register addresses. When using asynchronous transfers and direct access to IOP register space, only the lower 9 bits, ADDR8-0, need be supplied by the host. The upper address bits can be configured as Table 7-6. Asynchronous write operations are latched at the I/O pads in a four-deep FIFO buffer; this buffer is called the slave write FIFO and appears in Figure 6-5 on page 6-23. This buffering allows previously written words to be re-synchronized while a new word is being written. For maximum host throughput and low and high pulse widths for WR and RD, refer to the ADSP-21161N DSP Microcomputer Data Sheet. A host may write to several ADSP-21161s simultaneously (a broadcast write) by asserting each of their CS pins. Each processor accepts the write as if it were the only device being addressed. Because the REDY output is wire-ORed (if configured as an open-drain output), REDY only appears asserted when all selected DSPs are ready, unless REDY is actively pulled up. ACK is not active when CS is asserted. To eliminate the need for a host to drive the multiprocessor address lines (ADDR20-17) in systems with only one processor (ID2-0=000), the processor with ID2-0=000 does not recognize synchronous accesses to these addresses. The host must drive these address lines with 0000 or one of the ADDR23-21 address pins must be driven high to select an address in external memory if the processors ID2-0 is anything other than 000. To account for buffer delays when sampling the REDY signal, systems must make sure that REDY is properly re-synchronized by the host.

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Host Transfer Timing

When a processors CS chip select is asserted (low), the selected processor deasserts the REDY signal. Refer to the ADSP-21161N DSP Microcomputer Data Sheet for exact timing specifications. As shown in Figure 7-18, the processor deasserts REDY in response to CS. The host can assert CS before or after HBR is asserted. When HBG is not asserted, this timing is determined by the tTRDYHG switching characteristic specified in the Multiprocessor Bus Request and Host Bus Request timing data in the ADSP-21161N DSP Microcomputer Data Sheet. is asserted prior to RD or WR being asserted and becomes deasserted only if the processor is not ready for the read or write to completethe only exception is when CS is first asserted. The REDY pin is an open-drain output to facilitate interfacing to common buses. It can be changed to an active-drive output by setting the ADREDY bit in the SYSCON register.
REDY

Figure 7-18 shows the timing of a host write cycle, including details of data packing and unpacking. This timing applies to the example host interface hardware shown in Figure 7-25 on page 7-81 and has the following sequence: 1. The host asserts the address. HBR and CS are decoded from the host bus interface address comparator and do not need to be supplied directly by the host. The selected processor deasserts REDY immediately. 2. The host asserts WR and drives data according to the timing requirements specified in the ADSP-21161N DSP Microcomputer Data Sheet. 3. The selected processor asserts REDY when it is ready to accept the data. This transition occurs after the current bus master has completed its current transfer and has asserted HBG. HBG enables the host interface buffers to drive onto the processor bus.

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HBR

CS

DRIVEN BY HOST

HOST ADDRESS

VALID

ADDRESS VALID

HOST WRITE

ADDRESS SETUP

HOST READ HOST BUFFERS TURN ON HBG

RD WR MSx DRIVEN BY DSP BUS MASTER BRx

DRIVEN INACTIVE BEFORE THREE-SATE

ACK

DRIVEN BY EACH DSP

REDY DATA SETUP REDY DEASSERTED FOR A MIN OF 1 CYCLE

V ALID DATA FROM DS P

DATA BUS HOST TRANSITION TRANSITION CYCLE (BTC) CYCLE (HTC)

VALID

HOST TRISTATES BEFORE ASSERTING RD DATA IS LATCHED IN HOST ON RD RISING EDGE DATA FR OM HOST IS LATCHED INTO DSP ON WR RISING EDGE

Figure 7-18. Example Timing for Host Read and Write Cycles

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4. The host deasserts WR when REDY is high and stops driving data. 5. The selected processor latches data on the rising edge of WR. After the first word, the write sequence is: 1. The host asserts WR and drives data according to the timing requirements specified in the ADSP-21161N DSP Microcomputer Data Sheet. 2. The processor deasserts REDY if it is not ready to accept data. 3. The host deasserts WR when REDY is high and stops driving data. 4. The selected processor latches data on the rising edge of WR. More than one processor may have its CS pin asserted at any one time during a write, but not during a read because of bus conflicts. Figure 7-18 also shows the timing of a host read cycle. This timing applies to the bus interface hardware in Figure 7-25 on page 7-81 and has the following sequence: 1. The host asserts the address. HBR and the appropriate CS line are decoded by the host bus interface address comparator. The selected processor deasserts REDY immediately and asserts HBG. 2. The host asserts RD. 3. The selected processor drives data onto the bus and asserts REDY when the data is available. 4. The host latches the data and deasserts RD.

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After the first word, the read sequence is: 1. The host asserts RD. 2. The selected processor deasserts REDY then asserts REDY, driving data when it becomes available. 3. The host deasserts RD when REDY is high and latches the data.

Host Interface Deadlock Resolution With SBTS

In host systems, the host may need to recover the processor from a slave deadlock condition. When a host processor uses SBTS and HBR for deadlock resolution, SBTS operates differently than when the host uses only SBTS. By asserting both SBTS and HBR, the host places the ADSP-21161 in slave mode. ACK, HBG, REDY, and the data bus may all be active in slave mode. If the ADSP-21161 was performing an external access (which did not complete) in the same cycle that SBTS and HBR were asserted, the access is suspended until SBTS and HBR are both deasserted again. As with previous SHARCs, this functionalityusing SBTS and HBR togethercan be used for host/processor deadlock resolution. If SBTS and HBR are asserted while bus lock is set, the processor three-states its bus signals, but does not go into slave mode. For more information, see Deadlock Resolution on page 7-82. If SBTS and HBR are asserted while an external DMA access is occurring, HBG is not asserted until the access is completed. The processor also supports burst transfers, which can be truncated by assertion of HBR and SBTS. If the DMA transaction was a burst transfer, when the host relinquishes control of the local bus, the processor resumes the burst transfer, starting at the address of the last operation that did not complete.

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Slave Reads and Writes

The host can directly access the I/O processor registers of a processor by reading or writing the appropriate address. These accesses are invisible to the slave processors core. They do not degrade internal memory or internal bus performance. This capability is important, because it lets the processor core continue program execution uninterrupted. The host can directly read or write the I/O processor registers to control and configure the processor or to set up DMA transfers for indirect read/write access to internal memory. IOP Shadow Registers To ease host and multiprocessor system operations, the I/O processor registers include registers that shadow or mirror some processor core system registers, including the program counter (PC), and MODE2_SHDW registers. These registers facilitate system start up and debug, by letting the host (or another processor in an multiprocessor system) interrogate these processor core registers. These shadow registers are read only and lag the value of the registers they shadow by one internal core clock. For more information, see PC Shadow Register (PC_SHDW) on page A-77 and MODE2 Shadow Register (MODE2_SHDW) on page A-78. The silicon revision field of the MODE2 shadow register MODE2_SHDW is now used for differentiating between silicon revisions. These corresponding bits in the MODE2 (foreground) register are now reserved. The application program must read the MODE2_SHDW register bits [31:25] to identify the silicon revision. MODE2_SHDW is a memory-mapped IOP register whose address is 0x11.

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Instruction Transfers For 8-, 16- or 32-bit host interfaces, the ADSP-21161 can pack and unpack 48-bit instructions or 40-bit extended precision normal word data based on the host packing mode selected with the HBW bits in the SYSCON register. Slave Write Latency The processor handles asynchronous (from a host) and synchronous (from another processor) writes differently. This difference influences the latency for the writes. When a bus slave receives data from an asynchronous write, the processor latches the data and address in a four-level FIFO buffer. For synchronous writes, this buffer is two levels deep. This buffer is called the slave write FIFO and appears in Figure 6-5 on page 6-23. In the following cycle, the slave write FIFO attempts to complete the write internally. This buffering lets the host (or bus master) perform writes at the full clock rate. The slaves core cannot explicitly read the slave write FIFO. Also, the processor cannot determine the slave write FIFOs status. Writes to the I/O processor registers from the slave write FIFO usually occur in the following one or two cycles or when any current DMA transfer is completed. The write takes more than two cycles only if a direct write in the previous cycle was held off by a full buffer. If the slave write FIFO is full when a write is attempted, the processor deasserts ACK (or REDY) until the FIFO is not full. Unless higher priority on-chip DMA transfers are occurring, the slave write FIFO usually empties out within one cycle, creating a one-cycle write latency. Slave reads are held off when there is data in the slave write FIFOthis prevents false data reads and out-of-sequence operations.

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Slave Reads When a read of an ADSP-21161 occurs, the address is latched on-chip by the I/O processor and REDY is deasserted asynchronously. When the data is available, the I/O processor drives the data and asserts REDY. I/O processor register reads have a maximum throughput of one access per every three CLKIN cycles. As a slave, the processor supports burst read accesses, which improve throughput for I/O processor register reads of EPBx FIFOs only. Maximum throughput for synchronous burst direct read accesses is summarized in Table 7-7. For hosts, the processor does not support the synchronous burst protocol. Table 7-7. Direct Read Latencies for a 1:2 Clock Ratio
Access Type Single Read of I/O processor register Burst Read of I/O processor registers (EPBx only) Latency (CLKIN cycles) 3 3-2-2-2

Broadcast Writes
Broadcast writes allow simultaneous transmission of data to all of the ADSP-21161 processors in a multiprocessing system. The host processor can perform broadcast writes to the same I/O processor register on all of the slaves. Broadcast writes can be used to implement reflective semaphores in a multiprocessing system. The host processor must assert the CS input of all processors in the system and the address of the appropriate memory mapped I/O processor register for a broadcast write. Unlike previous SHARCs, the ADSP-21161 processor does not include a broadcast write memory space into its address space and therefore processor to processor broadcast writes are not supported.

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Data Transfers Through the EPBx Buffers

The host processor can transfer data to and from the ADSP-21161 through the external port FIFO buffers, EPB0, EPB1, EPB2, and EPB3. Each of these buffers, which are part of the I/O processor register set, is an eight-location FIFO, 64-bit wide (or sixteen-location, 32-bit wide). These buffers support single-word transfers, DMA transfers, and sequential burst accesses. DMA transfers are handled internally by the I/O processor, but single-word transfers must be handled by the processor core. The processor supports synchronous burst read transfers (32-bit only) from the EPBx FIFOs as a slave. Burst write transfers are not supported. To perform a burst read transfer from an EPBx buffer, the master issues a starting burst address pointing to one of the EPBx buffer addresses in I/O processor control register space. The slave does not increment an EPBx burst read address, and the master limits the burst transfer length to the modulo4 address boundary restriction. For information on external port transfers, see External Port Channel Transfer Modes on page 6-46. For information on external port handshaking, see External Port Channel Handshake Modes on page 6-47. To support debugging buffer transfers, the processor has a Buffer Hang Disable (BHD) bit. When set (=1), this bit prevents the processor core from detecting a buffer-related stall condition, permitting debugging of this type of stall condition. For more information, see the BHD discussion on page 6-43.

DMA Transfers
The host processor can also set up DMA transfers to and from the ADSP-21161. After the host gets control of the processor, the host can access the on-chip DMA control and parameter registers to set up an external port DMA operation. DMA is the most efficient way to transfer

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blocks of data. For DMA programming examples, see External Port DMA Example on page 6-77 and External Port Chained DMA Example on page 6-79. DMA Transfers to Internal Memory. The host can set up external port DMA channels to transfer data to and from internal memory. DMA Transfers to External Memory. The host can set up an external port DMA channel to transfer data directly to external memory using the DMA request and grant lines (DMARx, DMAGx). For more information, see Setting Up External Port DMA on page 6-68. The host may also use the DMARx/DMAGx handshake signals for a DMA transfer as a bus slave, but may not use DMA as a bus master while HBR retains control of the bus.

Host Data Packing

The host interface uses the same data packing features as the I/O processor uses. The 8- to 32-Bit Data Packing on page 7-66 and 48-Bit Instruction Packing on page 7-74 sections describe timing for these data packing operations. For transfers to or from the EPBx data buffers, the packing mode is determined by the setting of the HBW bits of the SYSCON register AND the PMODE bits in the DMACx control register for each external port buffer. For host accesses, to pack and unpack individual data words, you must set both the PMODE bits in the appropriate DMACx control register and the HBW bits in the SYSCON register. Table 7-8 shows the packing mode bit settings for access to IOP, link port and external port buffers.

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Table 7-8. Packing Mode Combinations

PMODE HBW 8/16/32 Host Packing Mode (External:Internal) IOP Buffers Internal Packing Fixed to 32-bit Reserved 16 : 32 16 : 32 32 : 32 32 : 32 8 : 32 8 : 32 Reserved 16 : 48 16 : 48 32 : 48 32 : 48 8 : 48 8 : 48 16 : 32/64 16 : 48-bit 32 : 48-bit 32 : 32/64 8 : 48 8 : 32/64 Link Ports Buffers Internal Packing Fixed to 48-bit External Port Buffers Uses PMODE, INT32 & DTYPE (1=48/40, 0=32/64)

000 001 010 011 100 101 110 111

01 (16-bit) 01 (16-bit) 00 (32-bit) 00 (32-bit) 10 (8-bit) 10 (8-bit)

The ADSP-21161 provides a glueless interface to 8-, 16-, and 32-bit hosts. Three differences between the ADSP-21161 and the ADSP-21160 are: Connection of 8-bit hosts (in addition to 16- or 32-bit hosts) is supported. There is limited direct access to IOP register space. A host processor and other ADSP-21161s in a multiprocessing configuration can only directly access the memory mapped IOP registers of an ADSP-21161. A host can only use asynchronous access to ADSP-21161 registers (by using CS of the processor). The lower nine bits of the 24-bit address bus are decoded to select an IOP register for any access into the ADSP-21161s internal memory.

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Synchronous broadcast write is not supported by the ADSP-21161 because there is no broadcast memory space. However, the host can simultaneously write to the same address on all the processors asynchronously by asserting CS for each processor simultaneously during a write without any multiprocessor memory offset. The host data bus is connected to the ADSP-21161 data bus in a LSB-alignment to the default 32-bit active data bus DATA47-16. For example, data pin 0 (D0) of host data bus connects to DATA16 of ADSP-21161 data bus, data pin 1 (D1) of the host data bus connects to DATA17 of the ADSP-21161 data bus, and so on. Depending on the register access, the processor packs/unpacks data as 32 bits, 48 bits, or up to 64 bits. A host can indirectly transfer data (via DMA) to and from internal memory by writing or reading to/from EPBx. To support this, several packing options are available. The newly defined Host Bus Width (HBW) bits 5 and 4 in the SYSCON register control the host data packing. They are described in Table 7-9 on page 7-65. Host Packing Status (HPS) bits 24-22 have also been redefined in SYSTAT. They are described in Table A-21 on page A-69.

Packing Mode Variations For Host Accesses

The host interface (using HBR, HBG, CS) uses data packing logic to allow the packing of 8-, 16-, and 32-bit external bus words into 32-, 48-, and 64-bit internal words. The packing logic is fully reversible; packing and unpacking of data is performed for both directions of data transfer to external data. For 32-bit, 16-bit, and 8-bit host processors accessing IOP register space, the processor can pack and unpack data to or from internal memory, independent of the setting of the PMODE bits in the DMACx register, to either 32-bit, 48-bit, or up to 64-bits internal packing depending on the type of host access. Although the packing mode for host access is configurable, it can sometimes revert to fixed packing modes depending on the IOP regis-

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ter accessed. In most cases, when a host accesses IOP control/status registers, the processor defaults to internal data packing and unpacking to a 32-bit access (independent of the setting of the PMODE bits in the DMACx register). LBUFx buffer access is limited to 48-bits internal packing, ignoring the PMODE bits in DMACx. EPBx buffer access always depends on the PMODE bits, DTYPE and INT32 bits in DMACx. The three host access cases are described in the following sections: IOP Register Host Accesses on page 7-62 LINK Port Buffer Access on page 7-63 EPBx Buffer Accesses on page 7-64 IOP Register Host Accesses For accesses to all IOP registers except EPBx and LBUFx, the host data is fixed to packed or unpacked to/from 32-bit internal data word. In most cases, when accessing an IOP control or status register, or serial port and SPI data buffers (TXn/RXn, SPIRX/SPITX), the PMODE bits in the DMACx register are ignored. A fixed packing mode of 8-, 16- or 32-bit external to 32-bit internal is selected. This is because all IOP registers except LBUFx and EPBx are 32 bits wide. Ensure that host accesses generate valid IOP register addresses. Host accesses to non-existent IOP register addresses are not supported, and can result in host bus grant (HBG) hang. Host access of IOP control/status registers and SPORT/SPI data buffers (except EPBx and LBUFx) will pack or unpack to 32 bits internally, ignoring the value of PMODE in DMACx. The HBW bits in the SYSCON register are used as a reference to set the external packing mode.

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For example, when interfacing the ADSP-21161 to an 8-bit microcontroller, the HBW bits are set in the SYSCON register to specify a host bus width of 8 bits. This results in an 8-bit external to 32-bit internal fixed data packing mode to an IOP register. Table 7-8 on page 7-60 shows the packing mode combinations. LINK Port Buffer Access The link buffers LBUF0 and LBUF1 can also be accessed by an external host processor, using direct reads and writes to IOP register space. However, there are differences in how data is accessed with the link buffers compared to other IOP control/status registers. When the host processor reads or writes to these buffers, the external packing data access width is also determined by the host bus width bits in the SYSCON register while the internal packing mode is restricted to 48 bits. Hosts accesses to the link port buffers pack or unpack to 48 bits internally, ignoring the value of PMODE in DMACx. The HBW bits in the SYSCON register are used to set the external packing mode. In the case where a host processor reads or writes to the LBUF0 and LBUF1 link buffers, the PMODE bits in the DMACx external port DMA control register are ignored and are fixed to a special 48-bit internal packing mode. This fixed 48-bit internal packing mode is required because the ADSP-21161 link port buffers transmit and receive 48-bit words. Depending on the HBW bits in SYSCON, the appropriate external to 48-bit internal memory packing mode are selected. The available bit settings are shown in Table 7-8 on page 7-60. It may be desirable in some applications for a host processor to transfer instruction opcodes to another SHARC indirectly via the directly connected SHARCs link port by reading or writing the opcode data to or from the LBUF0 and LBUF1 link buffers through the external port. For example, with a 16-bit host, the packing mode internally defaults to 48-bit packed transfers such that the packing mode is 16-bit external to 48-bit internal packed data transfers.

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EPBx Buffer Accesses The external port buffers, EPB0, EPB1, EPB2, and EPB3 can also be accessed by an external host processor, using direct reads and writes to IOP register space. There are differences in how data is accessed with the EPBx buffers as compared with other IOP control/status registers. When the host processor reads or writes to external port buffers, the packing mode indicated by the PMODE bits in the corresponding DMACx register are selected. Host accesses to the external port buffers pack or unpack according to the packing mode specified with the PMODE bits in DMACx. Depending on the HBW bits in SYSCON and PMODE in DMACx, the appropriate packing mode are selected as shown in Table 7-8 on page 7-60. There is no direct write pending bit in SYSTAT (as in the ADSP-21160) since the ADSP-21161 does not have a direct write FIFO. However, the ADSP-21161 processor has two newly defined bits in SYSTAT for checking the status of the slave write FIFO. The following bits in the SYSTAT register affect host access: Synchronous Slave Write FIFO Data Pending. SYSTAT Bit 20 (SSWPD).Since a host cannot be synchronous, this bit is set for synchronous access by another ADSP-21161. The bit is set (=1) when synchronous slave IOP register write is pending. The bit is cleared (=0) when the direct write is complete. Slave Write FIFO Data Pending. SYSTAT Bit 21 (SWPD).This status bit is set for any host or SHARC write access to an IOP register. If a host processor attempts to write data through the asynchronous protocol, this status bit is set. The bit is set (=1) when a slave (asyn-

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chronous or synchronous) write to an IOP register is pending. The bit is cleared (=0) when there is no slave write pending. The processor clears SWPD when the direct write is complete. Host Packing Order. SYSCON Bit 7 (HMSWF).This bit determines whether the I/O processor packs the most significant or least significant word first for 8-bit and 16-bit hosts. For 32- to 32/64 and 32- to 48-bit packing, the processor ignores the HMSWF bit in the SYSCON register and the MSWF bit in the DMACx register. Host packing examples are shown below for host direct read/write access to IOP control/status registers, TXn/RXn, SPIRX/SPITX and LBUFx data buffers. The default internal packing is 32-bit for host accesses to IOP control/status registers and 48-bit for host accesses to LBUFx, ignoring PMODE bits in DMACx. If the HMSWF bit is set (=1), the packing and unpacking is most significant word first. If the HMSWF bit is cleared (=0), the packing and unpacking is least significant word first. Table 7-9. Packing sequence for 32-bit IOP Register Data
Transfer First Second Third Fourth Data Bus Pins 23-16 (8-bit bus, LSW first) Word 1; bits 7-0 Word 1; bits 15-8 Word 1; bits 23-16 Word 1; bits 31-24 Data Bus Pins 31-16 (16-bit bus, MSW first) Word 1; bits 31-16 Word 1; bits 15-0

Table 7-10. Packing Sequence for Accessing 48-bit LBUFx Data

Transfer First Second Third Data Bus Pins 31-16 (16-bit bus, MSW first) LBUFx; bits 47-32 LBUFx; bits 31-16 LBUFx; bits 15-0 Data Bus Pins 23-16 (8-bit bus, MSW first) LBUFx; bits 47-40 LBUFx; bits 39-32 LBUFx; bits 31-24

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Table 7-10. Packing Sequence for Accessing 48-bit LBUFx Data (Contd)
Transfer Fourth Fifth Sixth Data Bus Pins 31-16 (16-bit bus, MSW first) Data Bus Pins 23-16 (8-bit bus, MSW first) LBUFx; bits 23-16 LBUFx; bits 15-8 LBUFx; bits 7-0

Table 7-11. Packing Sequence for Accessing 48-bit LBUFx Data From a 32-bit bus (MSW First)
Transfer First Second Third Data Bus Pins 47-32 LBUFx 1; bits 47-32 LBUFx 2; bits 15-0 LBUFx 2; bits 47-32 Data Bus Pins 31-16 LBUFx 1; bits 31-16 LBUFx 1; bits 15-0 LBUFx 2; bits 31-16

To write a single 48-bit word or an odd number of 48-bit words to LBUFx, write a dummy access to completely fill the packing buffer. 8- to 32-Bit Data Packing The processor latches incoming data on pins DATA23-16 for 8- to 32-bit packing on an 8-bit host bus. Similarly, the processor drives outgoing data on DATA23-16 with the other lines equal to zeroes. The sequence of events for 32-bit packing and unpacking for writes and reads are shown in Figure 7-19 on page 7-71. When a host reads a 32-bit word with 8-bit unpacking using the typical bus interface hardware shown in Figure 7-25 on page 7-81, the following sequence of events occurs: The host initiates a read cycle by driving an address, asserting CS, and asserting RD (low).

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The selected processor deasserts REDY, latches the address, and performs an internal read to get the data. When the processor has the data, it asserts REDY and drives the first 8-bit word. The host latches the data and deasserts RD (high). The host initiates another read access, driving the address of the data to be accessed then asserting RD. The processor transmits the second 8-bit word. The host initiates another read access, driving the address of the data to be accessed then asserting RD. The processor transmits the third 8-bit word. The host initiates another read access, driving the address of the data to be accessed then asserting RD. The processor transmits the final 8-bit word. 8- to 32-bit packing is complete. When a host writes a 32-bit word with 8-bit packing using the typical bus interface hardware shown in Figure 7-25 on page 7-81, the following sequence of events occurs: The host initiates a write cycle by driving the write address, asserting CS, and asserting WR (low). The processor asserts REDY when it is ready to accept data. The host drives the address and the first 8-bit word and deasserts WR (high). The processor latches the first 8-bit word.

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The host drives the address and initiates another write cycle for the second 8-bit word by asserting WR. The processor latches the second 8-bit word. The host drives the address and initiates another write cycle for the third 8-bit word by asserting WR. The processor latches the third 8-bit word. The host drives the address and initiates another write cycle for the fourth 8-bit word by asserting WR. When the processor has accepted the fourth word, it performs an internal write to its memory-mapped I/O processor register. If the processor's internal write has not completed by the time another host access occurs, the processor holds off that access with REDY. The packing sequence for downloading 32-bit data from a 8-bit host bus takes four cycles for every word, as illustrated in as shown in Table 7-12. The endian format of the transfers is controlled by the HMSWF bit in the SYSCON register. If HMSWF=0, the least significant 8-bit word is packed first. If HMSWF=1, the most significant 8-bit word is packed first. Table 7-12. 8- to 32-Bit Word Packing, HMSWF=1 (Host Bus <-> ADSP-21161)
Transfer First transfer Second transfer Third transfer Fourth transfer Data Bus Pins 23-16 Word1, bits 31-24 Word1, bits 23-16 Word1, bits 15-8 Word1, bits 7-0

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16- to 32-Bit Packing For a 16-bit host bus, the processor latches incoming data on pins DATA31-16. Similarly, the processor drives outgoing data on DATA31-16 with the other lines equal to zeroes. The sequence of events for 32-bit packing and unpacking is different for writes and reads. When a host reads a 32-bit word with 16-bit unpacking using the bus interface hardware shown in Figure 7-25 on page 7-81, the following sequence of events occurs as illustrated in Figure 7-23 on page 7-73: The host initiates a read cycle by driving an address, asserting CS, and asserting RD (low). The selected processor deasserts REDY, latches the address, and performs an internal read to get the data. When the processor has the data, it asserts REDY and drives the first 16-bit word. The host latches the data and deasserts RD (high). The host initiates another read access, driving the address of the data to be accessed then asserting RD. The processor transmits the second 16-bit word (16 to 32-bit packing is complete). When a host writes a 32-bit word with 16-bit packing using typical bus interface hardware shown in Figure 7-25 on page 7-81, the following sequence of events occurs as illustrated in Figure 7-23 on page 7-73: The host initiates a write cycle by driving the write address, asserting CS, and asserting WR (low). The processor asserts REDY when it is ready to accept data. The host drives the address and the first 16-bit word and deasserts WR (high).

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The processor latches the first 16-bit word. The host drives the address and initiates another write cycle for the second 16-bit word by asserting WR. When the processor has accepted the second word, it performs an internal write to its memory-mapped I/O processor register. If the processor's internal write has not completed by the time another host access occurs and the 4 deep asynchronous slave FIFO is full, the processor holds off that access with REDY. The packing sequence for downloading or uploading instructions over an 16-bit host bus takes two cycles for every 32-bit word, as shown in Table 7-13. The endian format of the transfers is controlled by the HMSWF bit in the SYSCON register. If HMSWF=0, the least significant 16-bit word is packed first. If HMSWF=1, the most significant 16-bit word is packed first. Table 7-13. 16- to 32-Bit Word Packing, HMSWF=1 (Host Bus <-> ADSP-21161)
Transfer First transfer Second transfer Data Bus Pins 31-16 Word1, bits 31-16 Word1, bits 15-0

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8/32 BIT PACKING

HOST ADDRESS[23:0]
WRITE ADDR (SAME) WRITE ADDRESS READ ADDR (SAME) READ ADDRESS

WR

RD

REDY

WRITE 1ST WRITE 2ND WRITE 3RD WRITE 4TH WORD WORD WORD WORD

READ 1ST READ 2ND WORD WORD

READ 3RD WORD

READ 4TH WORD

DATA[23:16]

HOST WRITE WITH 8/32 BIT PACKING

HOST READ WITH 8/32 BIT PACKING

Figure 7-19. Timing for 8- to 32-Bit Host Data Packing

8/48 BIT PACKING (WRITE)
HOST ADDRESS[23:0]
WRITE ADDR (SAME) WRITE ADDRESS READ ADDR

WR

RD

REDY

WRITE 1ST WRITE 2ND WRITE 3RD WRITE 4TH WRITE 5TH WORD WORD WORD WORD WORD

WRITE 6TH WORD

READ 1ST READ 2ND WORD WORD

DATA[23:16]

HOST WRITE WITH 8/48 BIT PACKING

NEXT PACKED READ TRANSFER

Figure 7-20. Timing for 8- to 48-Bit Host Data Packing (Write)

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8/48 BIT PACKING(READ)

HOST ADDRESS[23:0]
WRITE ADDR READ ADDR (SAME) READ ADDRESS

WR

RD

REDY
READ 1ST READ 2ND WORD WORD READ 3RD WORD READ 4TH WORD

READ 5TH WORD

READ 6TH WORD

DATA[23:16]

PREVIOUS PACKED WRITE TRANSFER

HOST READ WITH 8/48 BIT PACKING

Figure 7-21. Timing for 8- to 48-Bit Host Data Packing (Read)

16/48 BIT PACKING
HOST ADDRESS[23:0]
WRITE ADDR (SAME) WRITE ADDRESS READ ADDR (SAME) READ ADDRESS

WR

RD

REDY

WRITE 1ST WORD

WRITE 2ND WORD

WRITE 3RD WORD

READ 1ST READ 2ND WORD WORD

READ 3RD WORD

DATA[31:16]

HOST WRITE WITH 16/48 BIT PACKING

HOST READ WITH 16/48 BIT PACKING

Figure 7-22. Timing for 16- to 48-Bit Host Data Packing

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16/32 BIT PACKING

HOST ADDRESS(15:0) WRITE ADDRESS (SAME) WRITE ADDRESS READ ADDRESS (SAME) READ ADDRESS

WR

RD

REDY WRITE 1ST WORD INTO DSP READ 1ST WORD FROM DSP VALID VALID READ 2ND WORD FROM DSP VALID

DATA31-16

VALID

HOST WRITE WITH 16/32 BIT PACKING

HOST READ WITH 16/32 BIT PACKING

32/48 BIT PACKING

ADDR23-0
WORD1 WRITE ADDR WORD1 WRITE ADDR WORD2 WRITE ADDR WORD1 READ ADDR WORD2 READ ADDR WORD2 READ ADDR

WR

RD

REDY WRITE 1ST WORD INTO DSP READ 1ST WORD INTO DSP
2ND WORD 3RD WORD

READ 2ND WORD INTO DSP

DATA47-16

1ST WORD

WORD1

WORD2

WORD3

HOST WRITE WITH 32/48 BIT PACKING

HOST READ WITH 32/48 BIT PACKING

Figure 7-23. Timing for Host Data Packing

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If the processor is waiting for another 8- or 16-bit word from the host to complete the packed word, the HPS field in the SYSTAT register is non-zero. For more information, see Host Interface Status on page 7-76. Because there is only one packing buffer for the host interface, the host must complete each packed transfer before another is begun. For more information, see External Port Status on page 6-127. 48-Bit Instruction Packing The host can also download and upload 48-bit instructions over its 8-, 16-, or 32-bit bus. 32- to 48-Bit Packing The packing sequence for downloading instructions from a 32-bit host bus (HBW=00) takes 3 cycles for every 2 words, as illustrated in Table 7-14. Data (32-bit) is transferred on data bus lines 47-16 (DATA47-16). If an odd number of instruction words are transferred, the packing buffer must be flushed by a dummy access to remove the unused word. 40-bit extended precision data may be transferred using the 48-bit packing mode. For more information on memory allocation for different word widths, see Memory Organization and Word Size on page 5-25. Table 7-14. 32- to 48-Bit Word Packing (Host Bus <-> ADSP-21161)
Transfer First transfer Second transfer Third transfer Data Bus Lines 47-32 Word1, bits 47-32 Word2, bits 15-0 Word2, bits 47-32 Data Bus Lines 31-16 Word1, bits 31-16 Word1, bits 15-0 Word2, bits 31-16

The HMSWF bit of SYSCON is ignored for 32- to-48-bit packing.

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When a host writes a 48-bit word with 32-bit packing using typical bus interface hardware shown in Figure 7-25 on page 7-81, the sequence of events occurs as illustrated in Figure 7-23 on page 7-73. 16- to 48-Bit Packing The packing sequence for downloading or uploading instructions over a 16-bit host bus takes three cycles for every 48-bit word, as shown in Table 7-15. Table 7-15. 16- to 48-Bit Word Packing, HMSWF=1 (Host Bus <-> ADSP-21161)
Transfer First transfer Second transfer Third transfer Data Bus Pins 31-16 Word1, bits 47-32 Word1, bits 31-16 Word1, bits 15-0

When a host writes a 48-bit word with 16-bit packing using typical bus interface hardware shown in Figure 7-25 on page 7-81, the sequence of events occurs as illustrated in Figure 7-22 on page 7-72. 8- to 48-Bit Packing The packing sequence for downloading or uploading instructions over an 8-bit host bus takes six cycles for every 48-bit word, as shown in Table 7-16. The endian format of the transfers is controlled by the HMSWF bit in the SYSCON register. If HMSWF=0, the least significant word is packed first. If HMSWF=1, the most significant word is packed first. When a host writes a 48-bit word with 8-bit packing using typical bus interface hardware shown in Figure 7-25 on page 7-81, the sequence of events occurs as illustrated in Figure 7-23 on page 7-73.

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Table 7-16. 8- to 48-Bit Word Packing, HMSWF=1 (Host Bus <-> ADSP-21161)
Transfer First transfer Second transfer Third transfer Fourth transfer Fifth transfer Sixth transfer Data Bus Pins 23-16 Word1, bits 47-40 Word1, bits 39-32 Word1, bits 31-24 Word1, bits 23-16 Word1, bits 15-8 Word1, bits 7-0

Host Interface Status

The SYSTAT register provides status information for host and multiprocessor systems. For more information on the SYSTAT register, see Table A-21 on page A-69.

Interprocessor Messages and Vector Interrupts

After getting control of the ADSP-21161, the host processor communicates with it by writing messages to the memory-mapped I/O processor registers. In a multiprocessor system, the host can access the I/O processor registers of every ADSP-21161. The MSGRx registers are general-purpose registers that can be used for message passing between the host and the ADSP-21161. They are also useful for semaphores and resource sharing between multiple DSPs. The MSGRx and VIRPT registers can be used for message passing in the following ways: Message Passing. The host can use any of the eight message registers, MSGR0 through MSGR7, to communicate with the processor.

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Vector Interrupts. The host can issue a vector interrupt to the processor by writing the address of an interrupt service routine to the VIRPT register. When serviced, this high priority interrupt causes the processor to branch to the service routine at that address. The MSGRx and VIRPT registers also support shared-bus multiprocessing through the external port. Because these registers may be shared resources within a single processor, conflicts may occuryour system software must prevent this. For further discussion of I/O processor register access conflicts, see I/O Processor Registers on page A-47. Message Passing (MSGRx) There are three possible software protocols that the host can use for communicating with the processor through the MSGRx message registers: vector-interrupt-driven, register handshake, and register write-back. For the vector-interrupt-driven method, the host fills predetermined MSGRx registers with data, and triggers a vector interrupt by writing the address of the service routine to VIRPT. The service routine should read the data from the MSGRx registers and then write 0 into VIRPT. This signals the host that the routine is complete. The service routine also could use one of the processors FLAG11-0 pins to indicate completion. For the register handshake method, four of the MSGRx registers are designated as follows: a receive register (R), a receive handshake register (RH), a transmit register (T), and a transmit handshake register (TH). To pass data to the ADSP-21161processor, the host would write data into T and then write a 1 into TH. When the ADSP-21161 sees a 1 in TH, it reads the data from T and then writes back a 0 into TH. When the host sees a 0 in TH, it knows that the transfer is complete. A similar sequence of events occurs when the ADSP-21161 passes data to the host through R and RH.

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The register write-back method is similar to register handshaking, but uses only the T and R data registers. The host writes data to T. When the ADSP-21161 sees a non-zero value in T, it retrieves it and writes back a 0 to T. A similar sequence occurs when the host is receiving data. This simpler method works well when the data to be passed does not include 0. Host Vector Interrupts (VIRPT) Vector interrupts are used for interprocessor commands between the host and a ADSP-21161 or between two ADSP-21161s. When the external processor writes an address to the ADSP-21161s VIRPT register, the write triggers a vector interrupt. For more information, see Multiprocessing Interrupts on page 3-49. To use the ADSP-21161s vector interrupt feature, the host can perform the following sequence of actions: 1. Poll the processors VIRPT register until the host reads a certain token value (for example, zero). 2. Write the vector interrupt service routine address to VIRPT. 3. When the service routine is finished, the processor writes the token back into VIRPT to indicate that it is finished and that another vector interrupt can be initiated.

System Bus Interfacing

A processor subsystem, consisting of several DSPs with local memory, may be viewed as one of several processors connected together by a system bus. Examples of such systems are the EISA bus, PCI bus, or several processor subsystems. The processors in this kind of system arbitrate for the system bus using an arbitration unit. Each device on the bus that needs to become a bus master must be able to drive a bus request signal and respond to a bus grant signal. The arbitration unit determines which request to grant in any given cycle.

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Access to the Processor Bus Slave Processor Figure 7-24 shows an example of a interface to a system bus that isolates the local processor bus from the system bus. When the system is not accessing the DSPs, the local bus supports transfers between other local DSPs and local external memory or devices. When the system needs to access a processor, the system executes a read or write to the address range of the processor subsystem. The external address comparator detects a local access and asserts HBR and one of the appropriate CS lines. The processor holds off the system bus with REDY until the processor is ready to accept the data. The HBG signal enables the system bus buffers. The buffers direction for data is controlled by the read or write signals. To avoid glitching the HBR line when addresses are changing, the address comparator may be qualified by an enable signal from the system or qualified by the system read or write signals. These methods cause HBR to be deasserted each time system read or write is deasserted or the address is changed. Because these techniques deassert HBR with each access, the overhead of an HTC occurs as part of each access. Access to the System Bus Master Processor Figure 7-25 shows a bidirectional system interface in which the processor subsystem can access the system bus by becoming a bus master. Before beginning the access, the processor first requests permission to become the bus master by generating the System Bus Request signal (SBR). A bus arbitration unit determines when to respond with SBR. Here, each system bus master generates and responds to its own unique pair of signals. The method a processor uses to arbitrate for the system bus depends on whether the access is from the processor processor core or the I/O processor. For more information, see Processor Core Access to System Bus on page 7-82 and DMA Access to System Bus on page 7-84.

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HBG REDY HBR ADSP-21161 #2 BR2 5 3 010 ADDR23-0

SYSTEM BUS INTERFACE SYSTEM DATA BUS

BR1, DATA47-16 BR3-BR6 ID2-0 HBR HBG REDY CS WR RD WRITE ACK MS3-0 READ EXTERNAL MEMORY ADDR DATA WE OE ACK CS HBR CS2 CS1 ADDRESS COMPARATOR "ADDRESS VALID" REDY ACK SYSTEM BUS SYSTEM ADDRESS BUS OE HBG T/R

ADSP-21161 #1 BR1 5 BR2-BR6 DATA47-16 3 001 ID2-0 HBR HBG REDY CS WR RD ACK MS3-0 CLUSTER BUS ADDR23-0

Figure 7-24. Slave System Bus Interface

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HBG REDY HBR ADSP-21161 #2 ADDR23-0

SYSTEM BUS INTERFACE FLAG0 BR2 5 010 3 SYSTEM DATA BUS

BR1, DATA47-16 BR3-BR6 ID2-0 HBR HBG REDY SBTS CS WR RD ACK MS3-0 READ EXTERNAL MEMORY ADDR DATA WE OE ACK CS HBR CS2 CS1 ADDRESS COMPARATOR ACK REDY SYSTEM ADDRESS BUS WRITE HBG SYSTEM BUS GRANT

"ADDRESS VALID"

FLAG0 BR1 5 001 3

ADSP-21161 #1 ADDR23-0

BR2-BR6 DATA47-16 ID2-0 HBR HBG REDY SBTS CS SYSTEM BUS WR RD ACK MS3-0 CLUSTER BUS SYSTEM BUS REQUEST ACK MS3-0 FLAG0 (1,2) SYSTEM BUS GRANT

FLAG0 (1,2) SBTS (1,2) SBTS (1,2)

Figure 7-25. Bidirectional System Bus Interface

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Processor Core Access to System Bus The processor core may arbitrate for the system bus by setting a flag and waiting for SBG on another flag. This technique has the benefit of not stalling the local bus while waiting. If SBG is tied to an interrupt pin, the processor can continue processing while waiting. Another method for the processor access is to attempt the access assuming that the system bus is available. The processor then either waits or aborts the access if the bus is not available. The processor begins the access to the system bus by asserting one of the memory select lines, MS3-0. This assertion also asserts SBR. If the system bus is not available (for example, SBG is deasserted), the processor should be held off with ACK. This approach is simple, but stalls the processor and the local bus when the system bus is accessed while it is busy. To overcome this stall, programs can use the Type 10 instruction:
IF condition JUMP(addr), ELSE compute, DM(addr)=dreg;

This instruction aborts the bus access if the condition (SBG) is not true and causes the program to branch to a try-again-later routine. This method works well if SBG is asserted most of the time. If the Type 10 instruction is not used, a deadlock condition can result if an access is attempted before the bus is granted. The processor samples FLAG inputs at the CLKIN frequency except when CLKDBL is enabled. When CLKDBL is enabled, the processor samples FLAG inputs at the CLKOUT frequency. FLAG outputs must be held stable for at least one full CLKIN cycle. Deadlock Resolution When both the processor subsystem and the system try to access each others bus in the same cycle, a deadlock may occur in which neither access can complete; ACK stays deasserted.

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Normally, the master processor responds to an HBR request by asserting HBG after the completion of the current access. If the processor is accessing the system bus at the same time, HBG is not asserted, because this current access cannot completethis condition results in a deadlock in which neither access can complete. The deadlock may be broken by asserting the Suspend Bus Three-state (SBTS) input for one or more cycles after the deadlock is detectedwhen the system bus to local bus buffer is requested from both sides. The combination of SBTS and HBR puts the master processor into slave mode and suspends the processor cores external access. This suspension lets the system access to the local bus proceed, after the processor asserts HBG. The combination of HBR and SBTS should only be applied when there is a deadlock caused by a processor access to the system bus. SBTS should not be used when there is a local bus transfer, because the WR signal is asserted twiceonce before the SBTS is asserted and once after the access resumes. For processor-to-processor transfers on the local bus, this double assertion violates the slave timing requirements. The following sequence of actions allows the host processor to suspend an ongoing processor access and gain access to its internal resources, provided that: 1) the access originates from the processors core, not the DMA controller, 2) a DRAM page miss is not detected for that memory access, and 3) bus lock is not enabled. 1. After HBR is asserted, the host asserts SBTS for one or more cycles. If SBTS is asserted one or more cycles after HBR is recognized, HBG is guaranteed to be asserted in the next cycle. SBTS should be deasserted before HBR is deasserted. 2. The host drives the RD and WR strobe to their correct values after HBG is asserted. The host may then perform as many accesses as desired. 3. The host has full control of the bus and may access any of the processors or peripherals on the bus.

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4. The host deasserts HBR. HBG is deasserted when the internal read buffer is empty. 5. One cycle after the processor deasserts HBG, it restarts its suspended access. DMA Access to System Bus Using the SBTS and HBR inputs to resolve a system bus deadlock, as described in Deadlock Resolution on page 7-82, cannot be used for DMA transfers, because after a DMA word transfer has begun in the ADSP-21161, it must be completed (for example, it must receive the ACK signal). If SBTS and HBR are asserted during a DMA access, the HBG pin is not asserted until the access cycle has completed. If the single DMA access is not allowed to complete, a deadlock condition may result. To prevent system bus deadlock when using DMA, programs must make sure that SBG has been asserted before the DMA sequence begins. If a higher priority access is needed, the DMA sequence may be held off (by asserting HBR) at any time after a word has been transferred. Systems must ensure that SBG is asserted before HBR is deasserted to prevent the possibility of another deadlock occurring. When the DMA sequence is complete, the DMA interrupt service routine should clear the external SBR flag. Because the system bus is likely to be considerably slower than the local bus, performance on the local bus may be improved considerably by using handshake mode DMA. In this case, the SBG signal is tied to the DMA request line, DMARx. The local and system bus accesses are only initiated when the system bus is available. Using a FIFO in the system interface unit, to allow DMA data from the local bus to be posted, may also increase performance on the local bus when using a slow system bus.

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Multiprocessing With Local Memory Figure 7-26 shows how several subsystems may be connected together on a system bus for high throughput. The gate array implements bus arbitration when the system bus is accessed. The buffers isolate the local buses from the system bus. The example system in Figure 7-26 works in the following way: A processor requests the system bus with SBR when it asserts the MS2 line. The gate array arbitrates between the SBR lines and then enables the highest priority group by asserting SBG, which is tied to FLAG0. The master processor may connect to system memory or to other processor groups. When the bus buffer is enabled, the read or write strobe enables should be asserted with a delay to allow the address to stabilize. To access a processor slave in another group, the master processor addresses that groups multiprocessor memory space. The gate array detects group multiprocessor memory space from three high-order address bits and asserts the HBR line for the selected group. When HBG is asserted, the gate array enables the slaves bus buffer. The high-order group address bits are cleared by the buffer to allow the group to decode the address as local multiprocessor memory space. The access is asynchronous because the CS line is asserted. The single waitstate option for the bus should be enabled. If two groups access each other in the same cycle, a deadlock may occur. The SBTS pin may be used to clear the deadlock. ADSP-21161 to Microprocessor Interface A ADSP-21161 without external memory may connect to a host microprocessors bus. Depending on the microprocessors I/O capabilities, the interface may not require any buffers. This type of connection assumes

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3 ADSP-21161 #2

SYSTEM BUS ADDRESS

SYSTEM BUS

SBR SBG

MS2 FLAG0 ACK REDY CS HBR HBG LOCAL MEMORY SYSTEM MEMORY DATA ADDR LOCAL BUS BUFFER ENABLE

SYSTEM BUS ARBITRATION

SBTS

DATA ADDR

(GATE ARRAY)

ADSP-2116I #1

SBR SBG

MS2 FLAG0 ACK REDY CS HBR HBG SBTS LOCAL MEMORY DATA ADDR LOCAL BUS ENABLE BUFFER

Figure 7-26. Subsystems on a System Bus that the processor can execute its application from internal memory most of the time and only occasionally needs to request an external access. The host microprocessor should always keep the HBR request asserted unless it sees BR1 asserted (for the BRx line of the processor with ID=001). The host can then deassert HBR to allow the processor to perform an external access

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DATA47-16

SYSTEM BUS ADDRESS

ADDR23-0

External Port

when the host is ready to give up its bus. Usually, the host can read or write to the processor as needed. The host accesses the processor by asserting CS and handshaking with REDY. The HBG is not necessary in this system.

Multiprocessor (MP) Interface

The ADSP-21161 processor supports connecting to other ADSP-21161 processors to create multiprocessing processor systems. This support includes: Distributed, on-chip arbitration for the shared external bus A unified multiprocessor address space that makes the I/O processor registers of all processors directly accessible to each processor (and host interface) Dedicated hardware support for interprocessor communication (for example, reflective semaphores) Dedicated, point-to-point communication channels between processors using the link ports Figure 7-27 illustrates a basic multiprocessing system. In a multiprocessor system with several processors sharing the external bus, any of the processors can become the bus master. The bus master has control of the bus, which consists of the DATA47-16, ADDR23-0, and associated control lines.

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CONTROL

ADDRESS

ADSP-21161 #4

ADSP-21161 #3
CLKIN RESET 3 ID2-0 CONTROL ADDR23-0 DATA47-16

ADSP-21161 #2
CLKIN RESET 2 ID2-0 ADDR23-0 DATA47-16 CONTROL ADDR DATA CS BOOT EPROM (OPTIONAL)

ADSP-21161 #1
BMS

CLOCK

ADDR23-0 CLKIN RESET 1 RESET ID2-0 DATA47-16 RD WR ACK MS3-0 SBTS CS HBR HBG REDY

DATA

ADDR DATA OE WE ACK CS GLOBAL MEMORY AND PERIPHERALS (OPTIONAL)

CONTROL

ADDR
CONTROL ADDRESS

HOST PROCESSOR INTERFACE (OPTIONAL)

BR6-2 BR1

DATA
DATA

RAS CAS DQM SDWE SDCLK[1-0] SDCKE

RAS CAS DQM WE CLK CKE SDRAM (OPTIONAL)

SDA10

A10 CS

ADDR DATA

Figure 7-27. ADSP-21161 Multiprocessor System

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Table 7-17 shows the external port signals for multiprocessor processor arbitration and communication. Table 7-17. Signal for Cluster Multiprocessor Systems
Signal Types Synchronization Arbitration Bused Information Master Controls Slave Control Host 1 2 Interface2 Signals CLKIN, RESET BR6-1, PA1 ADDR23-0, DATA47-16 RD, WR, BRST ACK HBR, HBG, CS, REDY, SBTS

Optional, only needed if Priority Access function is used Optional, only needed if Host Interface is used.

The I/O processor registers of the systems processors make up the multiprocessor memory space. Multiprocessor memory space is mapped into the unified address space of each processor. For more information, see the multiprocessor memory map in Figure 5-8 on page 5-20. After a processor becomes the bus master, it can read and write to any of the slaves I/O processor registers, including their external port FIFO data buffers. For example, the master processor may write to a slaves I/O processor registers to set up DMA transfers or to send a vector interrupt. The ADSP-21161 processor only supports direct reads and writes to I/O processor registers. However, internal memory can be accessed indirectly through EPBx DMA transfers.

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Multiprocessing System Architectures

Multiprocessor systems typically use one of two schemes to communicate between processor nodes. One scheme uses dedicated point-to-point communication channels. In the other scheme, nodes communicate through a single shared global memory over a parallel bus. The ADSP-21161 supports point-to-point communicationdata flow multiprocessingthrough its two link ports. Also, the ADSP-21161 supports a shared parallel bus communicationcluster multiprocessing through its link ports and external port. The following sections provide more detail on on data flow multiprocessing and cluster multiprocessing. Data Flow Multiprocessing Data flow multiprocessing works for applications requiring high computational bandwidth, but requiring only limited flexibility. The program partitions its algorithm sequentially across multiple processors and passes data through a line of processors, as shown in Figure 7-28.
ADSP-21161 ADSP-21161 ADSP-21161

LINK PORT

LINK PORT

LINK PORT

LINK PORT

LINK PORT

LINK PORT

Figure 7-28. Data Flow Multiprocessing The ADSP-21161 provides complete support for data flow multiprocessing applications, because the processor eliminates the need for interprocessor data FIFOs and external memory. The internal memory of the processor is usually large enough to contain both code and data for most applications using data-flow system topology. Data flow systems

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only require a number of processors and point-to-point signals connecting them. This design yields savings in complexity, board space, and system cost. For more information on connecting multiple processors using link ports, see Host Processor Access To Link Buffers on page 9-14. Cluster Multiprocessing Cluster multiprocessing works for applications where flexibility is required. This flexibility is needed when a system must be able to support a variety of different tasks, some of which may be running concurrently. The cluster multiprocessing configuration is shown in Figure 7-29. Also, the processor has an on-chip host interface that lets a cluster be interfaced to a host processor or another cluster.
ADSP-21161 ADSP-21161 ADSP-21161

LINK PORT

LINK PORT

LINK PORT

LINK PORT

LINK PORT

LINK PORT

EXTERNAL PORT

EXTERNAL PORT

EXTERNAL PORT

BULK MEMORY

Figure 7-29. Cluster Multiprocessing Cluster multiprocessing systems include multiple ADSP-21161s connected to a parallel bus that supports interprocessor access of on-chip memory-mapped registers and access to shared global memory. In a typical cluster of processors, up to six processors and a host can arbitrate for

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the bus. The on-chip bus arbitration logic lets these processors share the common bus. The ADSP-21161s features (such as large internal memory, link ports, and external port FIFOs) help eliminate the need for any extra hardware in the cluster multiprocessor configuration. External memory, both local and global, can frequently be eliminated in this type of system. The ADSP-21161 supports fixed and rotating priority schemes. Other supported techniques include bus locking, timed release, DMA prioritization, and core processor access preemption of background DMA transfers. The on-chip arbitration logic lets transitions in bus mastership take up to only one cycle of overhead. Bus requests are generated implicitly when a processor accesses an external address. Because each processor monitors all bus requests and applies the same priority logic to the requests, each can independently determine who is the next bus master. After getting mastership of the bus, a processor can access external memory and the I/O processor registers of all other processors (slaves) in the system. A processor can directly transfer data to another processor or set up a DMA channel to transfer the data. The processors are mapped into a common memory mapto identify the address space of each processor within the unified memory map of the system cluster. Also, each processor has a unique ID. The processors I/O processor registers and external memory are all part of the unified address space. The cluster configuration allows the processors to have a very fast node-to-node data transfer rate. Clusters also allow a simple, efficient software communication model. For example, all of the required setup operations for a DMA transfer can be accomplished by a single processor on one side of the transfer. The other processor is not interrupted until the DMA transfer is complete. The ADSP-21161s internal memory facilitates I/O in multiprocessor systems. The on-chip, dual-ported RAM supports full-speed inter-processor DMA transfers concurrent with dual accesses by the

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processors processor core. Because no cycles are stolen from the processor core, the processors full performance is maintained during these accesses. Link Port Data Transfers In A Cluster. A bottleneck exists within the cluster because only two processors can communicate over the shared bus during each cycleother processors are held off until the bus is released. Because the processor can also perform point-to-point link port transfers within a cluster, systems can eliminate this bottleneck by setting up data communication through the link ports. Data links between processors can be dynamically set up and initiated over the common bus. Both link ports can operate simultaneously on each processor. A disadvantage of the link ports is that individual transfers occur at a much lower rate than that of the shared parallel bus. Because the link ports 8-bit data path is smaller than the processors native word size, the transfer of each word requires multiple clock cycles. Link ports may also require more software overhead and complexity because they must be set up on both sides of the transfers before they can occur. SIMD Multiprocessing. For certain classes of applications such as radar imaging, a Single-Instruction Multiple-Data (SIMD) array of processors may be the most efficient topology to coordinate a large number of processors in a single system. The SIMD array of Figure 7-29 on page 7-91 consists of multiple processors connected in a two- or three-dimensional mesh. The data link ports provide nearest neighbor communications and through-routing of data. A single master processor provides the instruction stream that the array executes. Data flow in and out the array can be managed through multiple serial port streams.

Multiprocessor Bus Arbitration

Multiple processors can share the external bus with no additional arbitration logic. Arbitration logic is included on-chip to allow the connection of up to six processors and a host processor.

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The processor accomplishes bus arbitration through the BR1-6, HBR, and HBG signals. BR1-6 arbitrate between multiple processors, and HBR/HBG pass control of the bus from the processor bus master to the host and back. The priority scheme for bus arbitration is determined by the setting of the RPBA pin. Table 7-18 defines the processor pins used in multiprocessing systems. Table 7-18. MultiprocessingPins
Signal BR6-1 Type I/O/S Definition Multiprocessing Bus Requests. Used by multiprocessing to arbitrate for bus mastership. A processor only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six processors, the unused BRx pins should be tied high; the processors own BRx line must not be tied high or low because it is an output. Multiprocessing ID. Determines which multiprocessing bus request (BR1 - BR6) is used by ADSP-21161 processor. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system configuration selection that should be hardwired or only changed at reset. Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every processor. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every processor. Priority Access. The processor slave may assert the PA signal to interrupt background DMA transfers and gain access to the external bus. This signal is asserted when a processor slaves processor core requests the bus or if an external DMA channel requests the bus with the DMACx PRIO control bit set. The PA signal is an active drive output, which may be asserted (low) by one or more slaves. It is deasserted (high) by the master. A protocol is used to avoid driver contention.

ID2-0

RPBA

PA

(a/d) I/O/S

I = Input, S = Synchronous, (o/d) = Open Drain; O = Output, A = Asynchronous, (a/d) = Active Drive

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The ID2-0pins provide a unique identity for each processor in a multiprocessing system. The first processor should be assigned ID=001, the second should be assigned ID=010, and so on. One of the processors must be assigned ID=001 in order for the bus synchronization scheme to function properly. The processor with ID=001 holds the external bus control lines stable during reset. When the ID2-0 inputs of a processor are equal to 001, 010, 011, 100, 101, or 110, the processor configures itself for a multiprocessor system and maps its I/O processor registers into the multiprocessor memory space. ID=000 configures the processor for a single-processor system. ID=111 is reserved and should not be used. A processor in a multiprocessor system can determine which processor is the current bus master, by reading the CRBM2-0 bits of the SYSTAT register. These bits give the value of the ID2-0 inputs of the current bus master. Conditional instructions can be written that depend upon whether the processor is the current bus master in a multiprocessor system. The assembly language mnemonic for this condition code is BM, and its complement is Not BM (not bus master). The BM condition indicates whether the processor is the current bus master. For more information, see Conditional Sequencing on page 3-53. To use the bus master condition, the condition code select (CSEL) field in the MODE1 register must be zero or the condition is always evaluated as false. Bus Arbitration Protocol The Bus Request (BR1-6) pins are connected between each processor in a multiprocessing system, with the number of BRx lines used equal to the number of processors in the system. Each processor drives the BRx pin that corresponds to its ID2-0 inputs and monitors all others. If less than six processors are used in the system, the unused BRx pins should be tied high.

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When one of the slave processors needs to become bus master, it automatically initiates the bus arbitration process by asserting its BRx line at the beginning of the cycle. Later in the same cycle, the processor samples the value of the other BRx lines. The cycle in which mastership of the bus is passed from one processor to another is called a Bus Transition Cycle (BTC). A bus transition cycle occurs when the current bus masters BRx pin is deasserted and one or more of the slaves BRx pins is asserted. The bus master can retain bus mastership by keeping its BRx pin asserted. Also, the bus master does not always lose bus mastership when it deasserts its BRx lineanother BRx line must be asserted by one or more of the slaves at the same time. In this case, when no other BRx is asserted, the master does not lose any bus cycles. By observing all of the BRx lines, each processor can detect when a bus transition cycle occurs and which processor has become the new bus master. A bus transition cycle is the only time that bus mastership is transferred. After conditions determine that a bus transition cycle is going to occur, every processor in the system evaluates the priority of the BRx lines asserted within that cycle. For a description of bus arbitration priority, see Bus Arbitration Priority (RPBA) on page 7-98. The processor with the highest priority request becomes the bus master on the following cycle, and all of the processors update their internal records to indicate which processor is the current bus master. This information can be read from the current bus master field, CRBM, of the SYSTAT register. Figure 7-29 on page 7-91 shows typical timing for bus arbitration. The actual transfer of bus mastership is accomplished by the current bus master three-stating the external busDATA47-16, ADDR23-0, CLKOUT1, RD, WR, BRST, MS3-0, HBG, DMAG2-1at the end of the bus transition cycle and the new bus master driving these signals at the beginning of the next cycle.
1

For a complete description of CLKOUT functionality, see Table 13-1 on page 13-4.

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The bus strobes (RD, WR) and MS3-0 are driven high (inactive) before three-stating occurs. ACK must be sampled high by the new master before it starts a new bus operation. For more information, see Figure 7-30. During bus transition cycle delays, execution of external accesses are delayed. When one of the slave processors needs to perform an external read or write, it automatically initiates the bus arbitration process by asserting its BRx line. This read or write is delayed until the processor receives bus mastership. If the read or write was generated by the processors processor core (not the I/O processor), program execution stops on that processor until the instruction is completed. The following steps occur as a slave acquires bus mastership and performs an external read or write over the bus as shown in Figure 7-31 on page 7-100. 1. The slave determines that it is executing an instruction which requires an off-chip access. It asserts its BRx line at the beginning of the cycle. Extra cycles are generated by the core processor (or I/O processor) until the slave acquires bus mastership. 2. To acquire bus mastership, the slave waits for a bus transition cycle in which the current bus master deasserts its BRx line. If the slave has the highest priority request in the bus transition cycle, it becomes the bus master in the next cycle. If not, it continues waiting. 3. At the end of the bus transition cycle the current bus master releases the bus, and the new bus master starts driving. During the CLKIN cycle in which the bus master deasserts its BRx output, it three-states its outputs in case another bus master wins arbitration and enables its drivers in the next CLKIN cycle. If the current bus master retains control of the bus in the next cycle, it enables its bus drivers, even if it has no bus operation to run.

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The processor with ID=00x enables internal keeper latches, or pullup devices, on key signals, including the address and data buses, strobes, and ACK. These devices provide a weak current source or sinkapproximate 20K impedanceto keep these signals from drifting near input receiver thresholds when all drivers are three-stated. When the bus master stops using the bus, its BRx line is deasserted, allowing other processors to arbitrate for mastership if they need it. If no other processors are asserting their BRx line when the master deasserts its BRx, the master retains control of the bus and continues to drive the memory control signals until: 1) it needs to use the bus again, or 2) another processor asserts its BRx line. While a slave waits to be a master for a DMA transfer, it asserts BRx. If that slaves core accesses the DMA address registers, the BRx is deasserted during that access. See I/O Processor Registers Memory Map on page A-51. Bus Arbitration Priority (RPBA) To resolve competing bus requests, there are two available priority schemes: fixed and rotating. The RPBA pin selects the scheme. When RPBA is high, rotating priority bus arbitration is selected, and when RPBA is low, fixed priority is selected. The RPBA pin must be set to the same value on each processor in a multiprocessing system. If the value of RPBA is changed during system operation, it must be changed synchronously to CLKIN and must meet a setup time that lets all processors recognize the change in the same cycle. The priority scheme changes in that (same) cycle.

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1 CLKIN BRX ADDR MSX RD WR BRST

OPTIONAL
HIGHEST PRIORITY REQUESTER BECOMES BUS MASTER

VALID VALID
MS, STROBES DRIVEN INACTIVE BEFORE TRISTATE

VALID VALID

PULLUP HOLDS ACK ASSERTED

ACK DATA BTC

VALID VALID SYNC WRITE SYNC READ BTC DOES NOT ACCESS ACCESS OCCUR IF NO OTHER BRx ASSERTED

MINIMUM 2-CYCLE SYNC READ - SLAVE DEASSERTS ACK IN 2ND CYCLE IF NEEDED

Figure 7-30. Bus Request and Read/Write Timing In the fixed priority scheme, the processor with the lowest ID number among the competing bus requests becomes the bus master. If, for example, the processor with ID=010 and the processor with ID=100 request the bus simultaneously, the processor with ID=010 becomes bus master in the following cycle. Each processor knows the ID of the other processors requesting the bus, because the ID corresponds to the BRx line being used for each processor.

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Multiprocessor (MP) Interface

ADSP-21161 #1 IS BUS BTC MASTER CLKIN BUS REQUESTS: BR1 BR2 ADSP-21161 WITH ID=1:
INTERNAL OPERATION INTERNAL OPERATION

ADSP-21161 #2 IS BUS MASTER

BTC

BRX SAMPLED AT THIS POINT

EXECUTE FLOW BUS ACTIVE

INTERNAL OPERATION

INTERNAL OPERATION

INTERNAL OPERATION

EXTERNAL ACCESS

HOLD SIGNAL STABLE

UNDRIVEN

PERFORM ACCESS

ADSP-21161 WITH ID=2: EXECUTE FLOW BUS ACTIVE

INTERNAL OPERATION EXTERNAL ACCESS EXTERNAL ACCESS INTERNAL OPERATION EXTERNAL ACCESS INTERNAL OPERATION INTERNAL OPERATION

UNDRIVEN

PERFORM ACCESS

PERFORM ACCESS

HOLD SIGNAL STABLE

PERFORM ACCESS

HOLD SIGNAL STABLE

UNDRIVEN

Figure 7-31. Bus Arbitration Timing The rotating priority scheme gives roughly equal priority to each processor. When rotating priority is selected, the priority of each processor is reassigned after every transfer of bus mastership. Highest priority is rotated from processor to processor as if they were arranged in a circle

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the processor located next to (one place down from) the current bus master is the one that receives highest priority. Table 7-19 shows an example of how rotating priority changes on a cycle-by-cycle basis. Table 7-19. Rotating Priority Arbitration Example
Cycle Number Hardwired Processor IDs & Priority1 ID1 12 2 3 4 53 M 4 4 5-BR 1-BR ID2 1 5-BR 5-BR M 2 ID3 2-BR M-BR M 1 3 ID4 3 1 1 2 4 ID5 4 2 2 3 5 ID6 5 3 3 4-BR M

1 The following symbols appear in these cells: 1-5 = assigned priority, M = bus mastership (in that cycle), BR = requesting bus mastership with BRx 2 Initial priority assignments 3 Final priority assignments

Bus Mastership Timeout In either the fixed or rotating priority scheme, systems may need to limit how long a bus master can retain the bus. Systems can limit bus mastership by forcing the bus master to deassert its BRx line after a specified number of CLKIN cycles and giving the other processors a chance to acquire bus mastership. To set up a bus master timeout, a program must load the BMAX register (Figure 7-32) with the maximum number of CLKIN cycles (minus 2) that allows the processor to retain bus mastership. This equation is shown below
BMAX

= (maximum # of bus mastership CLKIN cycles) 2 Internal processor clock cycles are a multiple of CLKIN cycles.

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Multiprocessor (MP) Interface

The minimum value for BMAX is 2, which lets the processor retain bus mastership for four CLKIN cycles. Setting BMAX=1 is not allowed. To disable the bus master timeout function, set BMAX=0. Each time a processor acquires bus mastership, its BCNT register is loaded with the value in BMAX. BCNT is then decremented in every CLKIN cycle that the master performs a read or write over the bus and any other (slave) processors are requesting the bus. Any time the bus master deasserts its BRx line, BCNT is reloaded from BMAX. When BCNT decrements to zero, the bus master first completes its off-chip read/write and then deasserts its own BRx (any new off-chip accesses are delayed)this allows transfer of bus mastership. If the ACK signal is holding off an access when BCNT reaches zero, bus mastership is not relinquished until the access can complete. If BCNT reaches zero while a burst transfer is in progress, the bus master completes the burst transfer before deasserting its BRx output. If BCNT reaches zero while bus lock is active, the bus master does not deassert its BRx line until bus lock is removed. If HBR is being serviced, BCNT stops decrementing and continues only after HBR is deasserted. Bus lock is enabled by the BUSLK bit in the MODE2 register. For more information, see Bus Lock and Semaphores on page 7-110.
31 30 29 28 27 26 25 24 23 22 21 0 7 0 0 6 0 0 5 0 20 0 4 0 19 0 3 0 18 0 2 0 17 16 0 1 0 0 0 0

BMAX (0x18)

0 9 0

0 8 0

15 14 0 0

13 12 0 0

11 10 0 0

BMAX = (maximum # of bus mastership cycles -2)

Figure 7-32. BMAX Register

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External Port

Priority Access The Priority Access signal (PA) lets external bus accesses by a slave processor take priority over ongoing DMA transfers. Normally when external port DMA transfers are in progress, the slave processors cannot use the external bus until the DMA transfer is finished. By asserting its PA pin, the slave processor can acquire the bus without waiting for the DMA operation to complete. The PA signal can also be asserted by a slave with a high-priority DMA access pending on the external bus. If the PA signal is not used in a multiprocessor system, the processor bus master does not give up the bus to another processor until: 1) a cycle in which it does not perform an external bus access or 2) a bus timeout. If a slave processor needs to send a high priority message or perform an important data transfer, it normally must wait until any DMA operation completes. Using the PA signal lets the slave perform its higher priority bus access with less delay. Each of the DMACx registers has a PRIO bit that raises that DMA channel to a higher priority than all other internal DMA channels that do not have the PRIO bit set. Unless configured differently with the EBPR bit in the SYSCON register, this channel still has lower priority (internally) than the core. Programs should be careful to minimize the number of DMA channels enabled to high priority status in the multiprocessor system, because both core and (external) high priority DMA requests from slaves are arbitrated at the same priority level. For example, a slave core cannot arbitrate bus ownership away from a high priority DMA transfer, unless the bus timeout (BMAX function) occurs. When PA is asserted, the current processor bus master deasserts its BRx output, and gives up the bus, provided: 1. Its core does not have an external access pending, and 2. None of its external bus DMA channels have pending high-priority bus requests.

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Multiprocessor (MP) Interface

All processor slaves also deassert their BRx outputs, if each slave meets the same provisions. The current bus master never asserts PA, because it already has control of the bus. If the current master detects a condition that would assert PA while it is bus master, it performs that high priority operation before giving up bus ownership. In the CLKIN cycle after PA has been asserted, only the processor slaves with a pending high priority access have their bus requests asserted. Bus arbitration proceeds as usual with the highest priority device becoming the master when the previous bus master releases its BRx output. The new master samples all BRx inputs after gaining bus mastershipduring the cycle that follows the BTC. If no other bus requests are asserted, the master is the only device driving PA, and the master deasserts and three-states PA in this cycle as shown in Figure 7-33.
1 BR1-5 BR6 2 3 4

All ADSP-21161s that do not have core access pending remove their BRx

PA

Figure 7-33. Example PA Deassertion

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{ {
BTC Slaves cannot assert PA in this cycle Bus Master samples all other BRx negated and negates PA

External Port

If the master samples other BRx inputs as asserted, multiple devices are driving PA, and the new bus master cannot deassert PA. The new bus master three-states its PA driver in this case. All processor slaves recognize the cycle following the BTC. They do not assert PA during this cycle, unless they were already driving their BR and PA outputs in the BTC. This behavior is demonstrated in Figure 7-34.
All ADSP-21161s that do not have core access pending remove their BRx 1 BR1-6 PA 2 3 4

{ {
BTC Bus Master samples other BRx asserted and three-states (only) PA Slaves continue to assert PA in this cycle

Figure 7-34. Example of PA Driven by Multiple Slaves

Bus Synchronization After Reset

When a multiprocessing system is reset (RESET asserted), the bus arbitration logic on each processor must synchronize, making sure that only one processor drives the external bus. One processor must become the bus master, and all other processors must recognize which one it is before actively arbitrating for the bus. The bus synchronization scheme also lets the system safely bring individual processors into and out of reset.

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Multiprocessor (MP) Interface

One of the processors in the system must be assigned ID=001 in order for the bus synchronization scheme to function properly. This processor also holds the external bus control lines stable during reset. Bus arbitration synchronization is disabled if the processor is in a single-processor system (ID=000). To synchronize their bus arbitration logic and define the bus master after a system reset, the multiple processors obey the following rules: All processors except the one with ID=001 deassert their BRx line during reset. They keep their BRx deasserted for at least two cycles after reset and until their bus arbitration logic is synchronized1. After reset, a processor considers itself synchronized when it detects a cycle in which only one BRx line is asserted. The processor identifies the bus master by recognizing which BRx is asserted and updates its internal record to indicate the current master. The processor with ID=001 asserts its BRx (BR1) during reset and for at least two cycles after reset. If no other BRx lines are asserted during these cycles, the processor with ID=001 drives the memory control signals to prevent them from glitching. Although it is asserting its BRx and driving the memory control signals during these cycles, this processor does not perform reads or writes over the bus. If the processor with ID=001 is synchronized by the end of the two cycles following reset, it becomes the bus master. If it is not synchronized at this time, it deasserts its BRx (BR1) and waits until it is synchronized. When a processor has synchronized itself, it sets the BSYN bit in the SYSTAT register.

For a complete description of the functionality of the internal reset signal, RSTOUT, see Table 13-1 on page 13-4.

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If one processor comes out of reset after the others have synchronized and started program execution, that processor may not be able to synchronize immediately (for example, if it detects more than one BRx line asserted). If the un-synchronized processor tries to execute an instruction with an off-chip read or write, it cannot assert its BRx line to request the bus and execution is delayed until it can synchronize and correctly arbitrate for the bus. Synchronization cannot occur while HBG is asserted, because bus arbitration is suspended while the bus is controlled by a host. If HBR is asserted immediately after reset and no bus arbitration has taken place, the processor with ID=001 is considered to be the last bus master. The processor with ID=001 maintains correct logic levels on the RD, WR, MS3-0, and HBG signals during reset. Because the 001 processor can be accidently reset by an erroneous write to the soft reset bit (SRST) of the SYSCON register, it behaves in the following manner during reset: While it is in reset, the processor with ID=001 attempts to gain control of the bus by asserting BR1. While it is in reset, the processor with ID=001 drives the RD, WR, MS3-0, DMAG1, DMAG2, and HBG signals only if it determines that it has control of the bus. For the processor to decide it has control of the bus, two conditions must be true: 1) BR1 was asserted and no other BRx lines were asserted in the previous cycle, and 2) HBG was deasserted in the previous cycle. The processor with ID=001 continues to drive the RD, WR, MS3-0, DMAG1, DMAG2, and HBG signals for two cycles after reset, as long as neither HBG nor any other BRx lines are asserted. At the end of the second cycle it assumes bus mastership (if it is synchronized), and normal bus arbitration begins in the following cycle. If it is not synchronized, it deasserts BR1, stops driving the memory control signals and does not arbitrate for the bus until it becomes synchronized.

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Multiprocessor (MP) Interface

Although the bus synchronization scheme allows individual processors to be reset, the processor with ID=001 may fail to drive the memory control signals if it is in reset while any other processors are asserting their BRx line.If the processor with ID=001 has asserted HBG while it is in reset, it is synchronized when RSTOUT is deasserted1. This lets the host start using the bus while the processors are still in reset. If a host processor attempts to reset the processor bus master (which is driving the HBG output), the host immediately loses control of the bus. During reset2, the ACK line is pulled high internally by the processor bus master with a 20 k equivalent resistor.

Booting Another processor

If the system uses one processor to boot another processor over the cluster bus, the master processor must (for maximum efficiency) do the following to communicate to the slave processor through the external port interface: 1. Program the PMODE field in DMAC10 of the booting processor for 32to 48-bit packing. This modification must be made to the boot loader kernel as well. 2. Write 48-bit words to EPB0 on the booting processor.

For a complete description of the functionality of the internal reset signal, RSTOUT, see Table 13-1 on page 13-4. 2 For a complete description of the functionality of the internal reset signal, RSTOUT, see Table 13-1 on page 13-4.

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Multiprocessor Writes and Reads

A processor bus master can read or write to the I/O processor registers of a slave processor. For more information, see Slave Reads and Writes on page 7-55. For synchronous write accesses, the slave write FIFO functions as a 2-deep FIFO. One or both of the stages may be used to store write accesses. If a synchronous write to this processor completes by the end of cycle N and if this is the first write to be stored in the slave write FIFO (for example, due to stalled write to the EPBx FIFO), then the ACK deasserts in cycle N+2. If a subsequent write to the same slave processor completes in cycle N+1, the access is correctly stored in the second stage of slave FIFO. Independent of this access in cycle N+1, an access in cycle N+2 is stalled on the bus due to a deasserted ACK. Only when the slave write FIFO is empty is ACK asserted again. Each processor bus slave monitors addresses driven on the external bus and responds to any that fall within its region of multiprocessor memory space. These accesses are invisible to the slave processors processor core. They do not degrade internal memory or internal bus performance as seen by the core. This feature lets the processor core continue program execution uninterrupted. The processor bus master can read and write the slaves I/O processor registers (for example, SYSCON, SYSTAT) to send a vector interrupt or to set up DMA transfers. For information on topics relevant to multiprocessing, see the following referenced sections: IOP Shadow Registers. For more information, see IOP Shadow Registers on page 7-55. Slave Write Latency. For more information, see Slave Write Latency on page 7-56. ADSP-21161 SHARC Processor Hardware Reference 7-109

Multiprocessor (MP) Interface

Slave Reads. For more information, see Slave Reads on page 7-57. Shadow Write FIFO. For more information, see Slave Reads on page 7-57. Data Transfers Through the EPBx Buffers. For more information, see Data Transfers Through the EPBx Buffers on page 7-58. Interprocessor Messages & Vector Interrupts. For more information, see Interprocessor Messages and Vector Interrupts on page 7-76. Instruction Transfers Multiprocessor instruction transfers to or from internal memory of processor should use 32-bit transfers for maximum performance. The 48-bit internal transfers use one of the slave EPBx FIFOs and the packing mode function (PMODE) of the DMA channel (32- to 48-bit). Maximum throughput is achieved by transferring packed instructions to or from internal memory, using DMA transfers with 32- to 48-bit packing.

Bus Lock and Semaphores

Semaphores can be used in multiprocessor systems to allow the processors to share resources such as memory or I/O. A semaphore is a flag that can be read and written by any of the processors sharing the resource. The value of the semaphore tells the processor when it can access the resource. Semaphores are also useful for synchronizing the tasks being performed by different processors in a multiprocessing system. With the use of its bus lock feature, the processor has the ability to read and modify a semaphore in a single indivisible operationa key requirement of multiprocessing systems.

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Because both external memory and each processors I/O processor registers are accessible by every other processor, semaphores can be located almost anywhere. Read-modify-write operations on semaphores can be performed if all of the processors obey two simple rules: 1. A processor must not write to a semaphore unless it is the bus master. This is especially important if the semaphore is located in the processors own internal memory or I/O processor registers. 2. When attempting a read-modify-write operation on a semaphore, the processor must have bus mastership for the duration of the operation. Both of these rules apply when a processor uses its bus lock feature, which retains its mastership of the bus and prevents the other processors from simultaneously accessing the semaphore. Bus lock is requested by setting the BUSLK bit in the MODE2 register. When this happens, the processor initiates the bus arbitration process by asserting its BRx line. When it becomes bus master, it locks the bus by keeping its BRx line asserted even when it is not performing an external read or write. Host Bus Request (HBR) is also ignored during a bus lock. When the BUSLK bit is cleared, the processor gives up the bus by deasserting its BRx line. While the BUSLK bit is set, the processor can determine if it has acquired bus mastership by executing a conditional instruction with the Bus Master (BM) or Not Bus Master (Not BM) condition codes, for example:
IF NOT BM JUMP(PC,0); /* Wait for bus mastership */

If it has become the bus master, the processor can proceed with the external read or write. If not, it can clear its BUSLK bit and try again later.

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Multiprocessor (MP) Interface

A read-modify-write operation is accomplished with the following steps: 1. Request bus lock by setting the BUSLK bit in MODE2. 2. Wait for bus mastership to be acquired. 3. Wait until Slave Write Pending bit (SWPD) is zero. 4. Read the semaphore, test it, then write to it. Locking the bus prevents other processors from writing to the semaphore while the read-modify-write is occurring. After bus mastership is acquired, check the SWPD bits status in SYSTAT to ensure that a semaphore write by another processor is not pending. If the semaphore is reflective, located in one of the processors I/O processor register, the processor must write to it only when it has bus lock. Multiprocessor Interface Status The SYSTAT register provides status information for host and multiprocessor systems. Figure 7-35 shows the status bits in this register.

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External Port

SYSTAT
0x03
HPS
Host Packing Status 000=packing complete [6th stage of 8-to -48, 4th stage of 8 -to-32, etc.] 001=1st stage pack/unpack 010=2nd stage pack/unpack 011=3rd stage pack/unpack 100=5th stage of 8- to -48 bit packing 101=110=111=reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0

CRAT
CCLK-to-CLKIN ratio Indicate state of CLKCFG[1:0] pins Undefined at RESET~

SSWPD
Synchronous Slave Write FIFO Data Pending 1=sync slave IOP register write pending 0=no sync slave IOP register write pending

SWPD
Slave Write FIFO Data Pending any data (sync or async) 1=slave write pending to IOP register 0=slave no write pending to IOP register

15 14 13 12 11 10 9 0 0 0 0 0

7 0

1 0

0 0

0 0

Vector Interrupt Pending 1=Vector interrupt pending ID Code Displays state of the ID[2:0] pins

VIPD

HSTM

Host Bus Master 1=host bus master controls ext bus 0=no host bus master

IDC

Bus Synchronized 1=bus arbitration logic synchronized 0=not synchronized

BSYN

CRBM
Current ADSP- 21161 Bus Master Status of ID of DSP who is Bus Master CRPM=001 when ID=000

Figure 7-35. SYSTAT Register

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8 SDRAM INTERFACE

The ADSP-21161 processors synchronous DRAM (SDRAM) interface enables it to transfer data at either the core clock frequency or one-half the core clock frequency. The synchronous approach, coupled with the ability to transfer data at the core clock frequency, supports data transfer at a high throughputup to 400 Mbytes/second for a 32-bit bus width, and 600 Mbytes/second for 48-bit bus width. All inputs are sampled and all outputs are valid on the rising edge of the clock SDCLK. The SDRAMs flexible interface allows you to connect SDRAMs to any one or more of the four external memory banks of the ADSP-21161 processor or to all four banks simultaneously. The ADSP-21161 processors SDRAM controller provides a glueless interface with standard SDRAMs. It supports: SDRAMs of 16 Mbits, 64 Mbits, 128 Mbits, and 256 Mbits with configurations 4-bit, 8-bit, 16-bit and 32-bit wide devices Additional buffers between ADSP-21161 processor and SDRAM Zero wait state, 100 Mwords/second with some access types Up to 254.68 Mwords [3x(64M) + 62.68M] of SDRAM in external memory SDRAM page sizes of 2048, 1024, 512, and 256 words A programmable refresh counter to coordinate between varying clock frequencies and the SDRAMs required refresh rate Buffering for multiple SDRAMs connected in parallel ADSP-21161 SHARC Processor Hardware Reference 8-1

 Shared SDRAM devices in a multiprocessing system A separate A10 pin that enables applications to precharge SDRAM before issuing a refresh command Connection to up to four external memory banks (0 to 3) of the ADSP-21161 processor Self-refresh, low-power mode Two power-up options The following are definitions used throughout this chapter: Bank Activate command. Activates the selected bank and latches in a new row address. It must be applied before a read or write command. Burst length. Determines the number of words that the SDRAM inputs or outputs after detecting a write or read command, respectively. The processor supports burst length ONE mode only. During a burst length of one cycle, the ADSP-21161 processor SDRAM controller applies the command every cycle and keeps accessing the data. See also, page size on page 8-3. Burst type. Determines the order in which the SDRAM delivers or stores burst data after detecting a read or write command, respectively. The processor supports sequential accesses only. CAS latency. The delay, in clock cycles, between when the SDRAM detects the read command and when it provides the data at its output pins. The speed grade of the device and the applications clock frequency determine the value of the CAS latency. The application must program the CAS latency value into the SDCTL register after power up.

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SDRAM INTERFACE

CBR Automatic Refresh (CAS before RAS) mode. In this mode, the SDRAM drives its own refresh cycle with no external control input. At cycle end, all SDRAM banks are precharged (idle). DQM Data I/O Mask function. This signal is asserted during a precharge command or when a burst stop command interrupts a burst write. When asserted during a write cycle, this signal interrupts and disables the write operation immediately. SDCTL Register. IOP register that contains programmable SDRAM control and configuration parameters that support different vendors timing and power-up sequence requirements. Mode Register. The SDRAMs configuration register that contains user-defined parameters corresponding to the processor's SDCTL register. After initial power-up and before executing a read or write command, the application must program the MODE register. Page Size. The size, in words, of the SDRAMs page. The processor supports 2048-, 1024-, 512-, and 256-word page sizes. Page size is a programmable option in the SDCTL register. Precharge Command. Precharges an active bank. SDRDIV Programmable Refresh Counter. An IOP register containing a refresh counter value. The clock supplied to the SDRAM can vary between 20 and 100 MHz. This counter enables applications to coordinate CLK rate with the SDRAMs required refresh rate. Self-Refresh. The SDRAMs internal timer initiates automatic refresh cycles periodically, without external control input. This command places the SDRAM device in a low-power mode. Self-refresh is a programmable option in the SDCTL register.

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8-3

 tRAS. Active Command time. Required delay between issuing an activate command and issuing a precharge command. A vendor-specific value. This option is programmable in the SDCTL register. tRC. Bank Cycle time. The required delay between successive Bank Activate commands to the same bank. This vendor-specific value is defined as: tRC = tRP + tRAS. The processor fixes the value of this parameter, so it is a non-programmable option. tRCD. RAS to CAS delay. The required delay between a ACT command and the start of the first read or write operation. This vendor-specific value is programmable in SDCTL. tRP. Precharge time. Required delay between issuing a precharge command and issuing an activate command. This vendor-specific value is programmable in SDCTL. Figure 8-1 shows the SDRAM controllers interface between the internal SHARC core and the external SDRAM device. (Note that in full instruction with no pack mode, the data bus extends to 48 bits, DATA47:00.) The ADSP-21161 processor normally generates an external memory address, which then asserts the corresponding MSx select, along with RD and WR strobes. These control signals are intercepted by the SDRAM controller. The memory access to SDRAM is based on the mapping of the addresses and memory selects. The configuration is programmed in the SDCTL register. The SDRAM controller can hold off the processor core or I/O processor with an internally connected acknowledge signal (ACK), as determined by refresh, nonsequential access, or page miss latency overhead.

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SDRAM INTERFACE

The SDRAM controller provides a glueless interconnection between the SDRAM control, address, and data pins and the processors internal Harvard Architecture busses. The internal 32-bit address bus is multiplexed by the SDRAM controller to generate the corresponding chip select, row address, column address, and bank select signals to the SDRAM.

ADSP-21161
CCLK OR 1/2 CCLK RD WR RESET ACK SDCLK SDCKE RAS CAS SDWE DQM SDA10 MSx CONTROLLER MSx CLK CKE RAS CAS WE DQM A10 CS (JEDEC) D47:16*

SDRAM

21161 CORE

BUFFER
A14/A13

DQ31:0

BA0/BA1 A12:0

A23:0

MUX

A23:0

A23:0

D47:16

Figure 8-1. SDRAM Controller Interface Figure 8-2 shows a block diagram of the ADSP-21161 processors SDRAM interface to four 8-bit SDRAMs. In this single processor example, the SDRAM interface connects to four 1M x 8 x2 (2M x 8) SDRAM devices to use 2M of 32-bit words. The same address and control bus communicates to all four SDRAM devices. The following connections are made:

ADSP-21161 SHARC Processor Hardware Reference

8-5

SDCKE

connects to the CKE of the SDRAM devices SDRAM clock connects to the CLK pins

SDCLK0 SDWE MSx

connects to all WE

pin connects to all chip selects (CS)

All CAS, RAS, and DQM signals are connected together between the processor and all of the SDRAM devices Notice that the data bus shows the processors default bus width, DATA[47:16]. For full non-packed instruction execution mode, the data bus can be extended to DATA[47:0] with the use of available disabled link port data pins. The A[10] pin of all SDRAM devices are connected to a separate SDA10 pin on the processor to allow the SDRAM controller to retain control of all SDRAMs for any non-SDRAM accesses during host bus requests.

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SDRAM INTERFACE

SDWE CAS RAS MSx A[14] SDA10 A[9:0] SDCKE SDCLK0 DQM

WE CAS RAS CS

SDRAM #1 2M x 8

WE CAS
DATA[23-16]

SDRAM #2 2M x 8

DQ [7:0]

RAS CS A11[BS] A[10] A[9:0] CKE CLK DQM

DQ [7:0]

DATA[31-24]

A11[BS] A[10] A[9:0] CKE CLK DQM

DATA[47-16]

DATA [47:16] WE CAS RAS CS A11[BS] A[10] A[9:0] CKE CLK DQM SDRAM #3 2M x 8 WE CAS RAS DQ [7:0]
DATA[39-32]

ADSP-21161

SDRAM #4 2M x 8

DATA[47-40]

CS A11[BS] A[10] A[9:0] CKE CLK DQM

DQ [7:0]

Figure 8-2. ADSP-21161 Processors Block Diagram

SDRAM Pin Connections

Table 8-1 describes the ADSP-21161 processor SDRAM controller pins and the connections for each pin. The pins are defined as Input (I), Output (O), Synchronous (S), or High Impedance (T). Table 8-1. SDRAM Pin Connections by Type
Pin CAS DQM Type I/0/T 0/T Description SDRAM Column Address Select pin. Connect to SDRAM's CAS buffer pin. SDRAM Data Mask pin. Connect to SDRAM's DQM buffer pin.

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Timing Specifications

Table 8-1. SDRAM Pin Connections by Type (Contd)

Pin MSx RAS SDA10 Type 0/T I/0/T 0/T Description Memory select pin of external memory bank configured for SDRAM. Connect to SDRAMs CS (Chip Select) pin. SDRAM Row Address Select pin. Connect to SDRAMs RAS pin. SDRAM A10 pin. SDRAM interface uses this pin to retain control of the SDRAM device during host bus requests. Connect to SDRAMs A10 pin. SDRAM Clock Enable pin. Connect to SDRAMs CKE (Clock Enable) pin. SDRAM SDCLKO output pin. Connect to the SDRAMs CLK pin. SDRAM SDCLK1 output pin. Connect to the SDRAMs CLK pin. SDRAM Write Enable pin. Connect to SDRAMs WE or W buffer pin.

SDCKE SDCLK0 SDCLK1 SDWE

I/0/T I/0/S/T 0/S/T I/0/T

SDRAM Timing Specifications

To support key timing requirements and power up sequences for different SDRAM vendors, the ADSP-21161 processor provides programmability for tRAS, tRP, tRCD, and a power up sequence mode. The CAS latency should be programmed in the SDCTL register based on the frequency of the operation. Refer to the SDRAM data sheet of the vendor for more details. For other parameters, the controller assumes: Bank Cycle Time, tRC =
tRAS

+ tRP

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SDRAM INTERFACE

SDRAM Control Register (SDCTL)

SDRAMs are available from several vendors, including IBM, Micron Electronics, Toshiba, Samsung Electronics, and NEC. Each vendor has different SDRAM product requirements for the power-up sequence and the timing parameters -tRAS (ACT to PRE command delay), tRCD and tRP (PRE to ACT command delay). Use only SDRAMS that comply with Joint Electronic Device Engineering Council (JEDEC) specifications. In order to support multiple vendors, the ADSP-21161 processor SDCTL register can be programmed to meet these requirements. The SDCTL register is an I/O processor register which does not support bitwise operations. Figure 8-3 provides bit descriptions for the SDRAM Register. Table A-22 on page A-73 provides bit descriptions.

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Configuration for Runtime

SDCTL
(0x00B8)
SDTRCD
SDRAM tRCD spec RAS to CAS delay [# of SDCLK cycles: 1 to 7 cycles] Pipelining option with external reg buffer [1=ext SDRAM ctl/addr buffer enable 0=no buffer option]

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDEM0
Ext mem Bank0 SDRAM enable

SDEM1
Ext mem Bank1 SDRAM enable

SDBUF

SDEM2
Ext mem Bank2 SDRAM enable

SDCKR
SDCLK-to-CCLK ratio 0=Half CCLK (core clock) freq. (1:2) 1=CCLK Core clock freq. (1:1)

SDEM3
Ext mem Bank 3 SDRAM enable 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

SDBN
SDRAM # of SDRAM device mem banks 0=2 banks, 1=4 banks 15 14 13 12 11 10 9 0 0 0 0 0 0 0

SDSRF
SDRAM self refresh command enable

SDCL
SDRAM CAS Latency spec 01=1 cycle, 10=2 cycles, 11=3 cycles Disable SDCLK0 &Control Signals 1=Disable SDCLK0, RAS~, CAS~ & SDCLKE 0=Activate SDCLK0, RAS~, CAS~ & SDCLKE SDCLK1 Disable 1=disable SDCLK1, 0=SDCLK active

SDPSS
SDRAM Power- up sequence

DSDCTL

SDPGS
SDRAM Page Size 00=256 words 01=512 words 10=1k words 11=2k words

DSDCK1

SDTRAS
SDRAMtRAS spec Active Command Delay [# of SDCLK cycles: 0 to 15 cycles]

SDPM
SDRAM Power- up mode 0=prechg , 8 CBR refs., mode reg. set 1=prechg, mode reg. set, 8 CBR refs.

SDTRP
SDRAMtRP spec PrechargeDelay [# of SDCLK cycles: 1 to 7 cycles]

Figure 8-3. SDCTL Register

SDRAM Configuration for Runtime

The ADSP-21161 processor supports 16 Mbits, 64 Mbits, 128 Mbits, and 256 Mbits SDRAM devices with 4-bit, 8-bit, 16-bit, and 32-bit configurations. Page sizes of 256, 512, 1024, and 2048 words are supported in the available the densities and configurations mentioned above. Each external memory bank has address space of 64 Mwords for SDRAMs.

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ADSP-21161 SHARC Processor Hardware Reference

SDRAM INTERFACE

The SDCTL register of the ADSP-21161 processor stores the configuration information of the SDRAM interface. Writing configuration parameters initiates commands to the SDRAM that take effect immediately. Before starting the SDRAM powerup sequence, complete the following steps: 1. Write to the WAIT register to set the waitstates to zero (EBxWS=000) for each bank that has SDRAM mapped to it. 2. Set the SDRDIV register at initial power-up. In the SDRDIV register, a memory-mapped IOP register, configure the value for the SDRAM refresh counter. 3. Write all of the SDRAM configuration parameter values to the SDCTL register. When the SDRAM controller is programmed with the register buffer option enabled, do not perform non-SDRAM write accesses to external memory until the power-up sequence is completed by the SDRAM controller. External memory non-SDRAM writes do not function correctly whenever the SDRAM controller is configured for SDBUF=1 (register buffering) option and the power up sequence has not yet been completed by the SDRAM controller. The MRS command that is applied by the SDRAM controller conflicts with the non-SDRAM write access started by either the core or DMA controller. In the SDCTL register, set the parameter bits as follows: Set the SDRAM clock enables (DSDCTL and DSDCK1). Select the number of banks that the SDRAM contains (SDBN). Select the external memory banks configured for and connected to an SDRAM (SDEMx). Set the SDRAM buffering option (SDBUF).

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SDRAM Configuration for Runtime

Select the CAS latency value (SDCL). Select the SDRAM page size (SDPGS). Select the SDRAM power-up mode (SDPM). Start the SDRAM power-up sequence (SDPSS). Start SDRAM self-refresh mode (SDSRF). Set the Active Command Delay (SDTRAS). Set the precharge delay (SDTRP). Set the RAS-to-CAS delay (SDTRCD). Set the SDCLK to Core Clock Ratio (SDCKR). In systems where several SDRAM devices are connected in parallel, buffering may be required to meet overall system timing requirements. The ADSP-21161 processor supports the pipelining of the address and control signals to enable buffering between ADSP-21161 processor and SDRAM. The pipeline bit (SDBUF) in the SDCTL register enables this mode. When this bit is set, the data for write accesses are delayed by one cycle, allowing the address and controls to be externally latched. In read accesses, data is sampled by ADSP-21161 processor one cycle later. To support the higher clock load requirements, two SDCLK pins are provided to eliminate the need for off-chip clock buffers. An option is provided in the SDCTL register (bits 2 and 3) to allow the SDRAM controller to three-state one or both the SDCLK pins. The SDCKR bit in the control register can be used to set the SDCLK to core clock ratio. The interface can run at full core clock frequency or at half the core clock frequency, depending upon the setting for this bit.

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SDRAM INTERFACE

Setting the Refresh Counter Value (SDRDIV)

Since the clock supplied to the SDRAM can vary between 20 MHz and 100 MHz, the processor provides a programmable refresh counter (SDRDIV) to coordinate the supplied clock rate with the SDRAM device's required refresh rate. Write to SDRDIV the delay, in a number of clock cycles, that must occur between consecutive refresh commands. Write the delay value to the SDRDIV register before writing the SDRAM parameter values to the SDCTL register. To calculate the value of the refresh counter for which to program the SDRDIV register, use the equation shown in Figure 8-4.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SDRDIV
0xB9
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDRDIV =

f CCLK
SDR AM refresh rate cycle

CL

tRP

Figure 8-4. SDRDIV Register and Calculation is 1x CCLK or 2x CCLK, as determined by the SDCKR bit and SDCTL register.
SDCLK

Where: f CCLK = CLKCFG f CLKOUT CL = CAS latency programmed into the SDCTL register tRP = tRP specification programmed in the SDCTL register

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Configuration for Runtime

CLK_CFG

= 2 for 2:1 CCLK-to-CLKOUT clock ratio = 3 for 3:1 CCLK-to-CLKOUT clock ratio = 4 for 4:1 CCLK-to-CLKOUT clock ratio

is defined as the internal core-clock frequency. CLKOUT is 1xCLKIN or 2xCLKIN, depending on whether CLKDBL is tied high or low during RESET. The signals SDCLK0 and SDCLK1 can operate at either 1xCCLK or 1/2 CCLK, as determined by the SDCKR in the SDCTL register.
CCLK

For example, for an IBM SDRAM with: Reference rate = 4096 cycles/64ms
CLKIN

= 25 MHz enabled

CLKDBL

Therefore, CLKOUT = 50 MHz

CLK_CFG CL

= 2, for 2:1 PLL ratio

=2 =2

tRP

The equation yields: 50x10 6 SDRDIV = 2x -------------------------------- 2 2 5 = 1554 ( decimal ) = 0x612 1 ------------------4096 64x10 3

Setting the SDRAM Clock Enables

Systems with several SDRAM devices connected in parallel require buffering between the processor and multiple SDRAM devices to reduce capacitive loading. Buffering, however, may also generate increased clock loads.

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SDRAM INTERFACE

To meet higher clock load requirements, the processor provides two SDRAM clock control pins, SDCLK0 and SDCLK1. These pins eliminate the need for off-chip clock buffers. The DSDCTL and DSDCK1 in the SDCTL register provide control for the SDRAM clock control pins. The DSDCTL bit, if set (=1), enables high impedance for all of the SDRAM control pins (DQM, CAS, RAS, SDWE, and SDCKE) and the SDCLK0 pin. The DSDCTL bit, if cleared (=0), disables all SDRAM control pins. The DSDCK1 bit, if set (=1), enables the SDCLK1 pin and places it into a high impedance state only. The DSDCK1 bit, if cleared (=0), disables SDCLK1. If your system does not use SDRAM, set both DSDCTL and DSDCK1 to 1. If your system uses SDRAM, but the clock load is minimal, set DSDCTL to 0 and DSDCK1 to 1 This setting enables the SDCLK0 pin and all related SDRAM control pins, but disables the second clock pin SDCLK1. If your system uses SDRAM and has a heavy clock load such as a system using registered buffers and eight 4-bit SDRAMs to get 32-bit data, set both DSDCTL and DSDCK1 to 0. This setting enables SDCLK0, SDCLK1, and all SDRAM control pins. In this configuration, SDCLK0 and SDCLK1 can each share half of the clock load.

Setting the Number of SDRAM Banks (SDBN)

The SDBN bit defines the number of banks in the SDRAM device. The SDRAM controller uses this value and the value assigned to the SDPGS (page size) bit to map the address bits on the processors internal 32-bit address (DMA/PMA/EPA) bus into SDRAM column address, row address, and bank select address. The SDBN bits in the SDCTL register select the number of banks the SDRAM as follows: 0 = 2 banks, 1 = 4 banks.

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Configuration for Runtime

Setting the External Memory Bank (SDEMx)

The SDCTL register can be programmed to select the external memory banks that have SDRAM devices by using the SDEMx bits. For example, if external memory banks 1 and 3 have SDRAMs, SDEM1 and SDEM3 bits are written with 1. However the controller tracks only the previously accessed page/bank. When using SDRAM, connect its CS line to any of the processors external memory banks MS3-0. In the SDCTL register, configure that bank for SDRAM operation. Program a zero (0) wait state for the external memory bank to which the SDRAM device maps by setting EBxWS to 000 in the WAIT register. Do not use external handshake mode DMA on the external memory bank mapped to an SDRAM device. The SDEMx bits in the SDCTL register configure the processors external memory banks for SDRAM operation as follows:
SDEM [0-3] = 0000 SDEM0 = 1 SDEM1 = 1 SDEM2 = 1 SDEM3 = 1

bits 16-19, No SDRAM enabled Bank 0 SDRAM Enable Bank 1 SDRAM Enable Bank 2 SDRAM Enable Bank 3 SDRAM Enable

Setting the SDRAM Buffering Option (SDBUF)

Systems that use several SDRAM devices connected in parallel may require buffering between the processor and multiple SDRAM devices in order to meet overall system timing requirements.

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ADSP-21161 SHARC Processor Hardware Reference

SDRAM INTERFACE

To meet such timing requirements and enable intermediary buffering, the processor supports pipelining of SDRAM address and control signals. The pipeline bit SDBUF (bit 23) in the SDCTL register enables this mode:
SDBUF = 0 SDBUF = 1

Disable pipelining Enable pipelining

When SDBUF is set (=1), the SDRAM controller delays the data in write accesses by one cycle, enabling the processor to latch the address and controls externally. In read accesses, the SDRAM controller samples data one cycle later. Figure 8-5 shows another single processor example in which the SDRAM interface connects to multiple banks of SDRAM to provide 512 M of SDRAM in a 4-bit I/O configuration. This configuration results in 16 M x 32-bit words. In this example, OxA and OxB output from the registered buffers are the same signal, but are buffered separately. In the registered buffers, a delay of one clock cycle occurs between the input (Ix) and its corresponding output (OxA or OxB).

Selecting the CAS Latency Value (SDCL)

The CAS latency value defines the delay, in number of clock cycles, between the time that the SDRAM detects the read command and the time that it provides the data at its output pins. This parameter facilitates matching the SDRAM operation with the processors ability to latch the data output. CAS latency does not apply to write cycles. The SDCL bits in the SDCTL register select the CAS latency value as follows: 01 = 1 clock cycle, 10 = 2 clock cycles and 11= 3 clock cycles. Generally, the frequency of the operation determines the value of the CAS latency. For more details, see the SDRAM device documentation.

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Configuration for Runtime

Addr [14] Ctrl [6]

D Q

20 SDRAM Bank 1 Addr & Ctrl

RAS CAS WE

SDRAM #1 4M x 4 x 4

CAS WE [3:0]

RAS SDRAM #5 4M x 4 x 4

D Q

20 SDRAM Bank 2 Addr & Ctrl

DQM DATA [3:0] CKE CLK CS A[13:0]

DQM DATA [3:0] CKE CLK CS A[13:0] RAS SDRAM #6 4M x 4 x 4

[19:16]

ADSP-21065L
C O N T R O L RAS CAS SDWE DQ M SDCKE MS3 A[13:11] A[9:0] SDA10

Registered Buffers
I0 I1 I2 I3 I4 I5 O0A O1A O2A O3A O4A O5A Aa[13:0]

CAS WE DQM CKE CLK

RAS SDRAM #2 4M x 4 x 4

DATA [3:0]

[7:4]

CAS WE DQM CKE CLK

DATA [3:0]

[23:20]

CS A[13:0]

CS A[13:0]

Ix[13:0] Oxa[13:0] O0B O1B O2B O3B O4B

RAS CAS WE DQM CKE CLK CS A[13:0]

SDRAM #3 4M x 4 x 4

RAS CAS WE DQM CKE CLK CS A[13:0]

SDRAM #7 4M x 4 x 4

O5B Oxb[13:0] Ab[13:0]

DATA [3:0]

[11:8]

DATA [3:0]

[27:24]

SDCLK0 SDCLK1

Ab[13:0]

DATA[31-0]

CAS WE DQM CKE CLK

RAS SDRAM #4 4M x 4 x 4

CAS WE [15:12]

RAS SDRAM #8 4M x 4 x 4

DQM DATA [3:0] CKE CLK CS A[13:0]

DATA [3:0]

[31:28]

CS A[13:0]

Figure 8-5. Uniprocessor System With Multiple SDRAM Devices

Selecting the SDRAM Page Size (SDPGS)

The processor's SDRAM controller SDPGS bit defines for the page size, in number of words, of the SDRAMs banks. The SDRAM controller uses this value and the value assigned to the SDBN (number of banks) bit to map the address bits on the processors internal 32-bit address (DMA/PMA/EPA) bus into SDRAM column address, row address, and bank select address.

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ADSP-21161 SHARC Processor Hardware Reference

SDRAM INTERFACE

Page length depends on the I/O organization and column addressing of the SDRAMs internal banks. For example, a 16 Mbits SDRAM organized as 2 M x 4 I/O x 2 banks has a page size of 1024 words. The SDPGS bits (bits 12 and 13) in the SDCTL register select the SDRAM page length: 00= 256 words, 01 = 512 words, 10= 1024 words and 11 = 2048 words.

Setting the SDRAM Power-Up Mode (SDPM)

To avoid unpredictable start-up modes, SDRAM devices must follow a specific initialization sequence during power up. The processor provides two commonly used power-up options. The SDPM bit (bit 11) in the SDCTL register selects the SDRAM power-up mode. When the SDPM bit is cleared (=0), the SDRAM controller sequentially issues: a PRE command, eight CBR refresh cycles, and an MRS (Mode Register Set) command. When the SDPM bit is set (=1), the SDRAM controller issues, in this order: a PRE command, an MRS (Mode Register Set) command, and eight CBR refresh cycles. For details, see the SDRAM device documentation.

Starting the SDRAM Power-Up Sequence (SDPSS)

Before starting the power-up sequence, write to the SDCTL register to configure the SDRAM parameters. Be sure to write to all the register bits, regardless of the number of parameter values that do not change. To start the SDRAM power-up sequence, write 1 to the SDPSS bit (bit 14) in the SDCTL register. The SDPSS bit always reads as zero (0). The initialization sequence executed during power-up depends on the value of the SDPM bit.

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Configuration for Runtime

Initialize the SDRDIV register before the ADSP-21161 processor starts the SDRAM power-up sequence. After power up, make sure that the processor waits one cycle before writing the SDCTL register to issue another SDRAM command. For more details, see the SDRAM device documentation.

Starting Self-Refresh Mode (SDSRF)

The processor supports SDRAM self-refresh mode. In self-refresh mode, the SDRAM performs refresh operations internally, without external control, which reduces the SDRAMs power consumption. The SDSRF bit (bit 15) in the SDCTL register enables and disables the self-refresh option:
SDSRF = 0 SDSRF = 1

Disable self-refresh mode Enable self-refresh mode

When SDSRF is set (=1), the processors SDRAM controller issues a SREF command to the SDRAM device or devices, putting them into self-refresh mode immediately. For details, see Self Refresh Command (SREF) on page 8-39.

Selecting the Active Command Delay (SDTRAS)

The tRAS value (Active Command Delay) defines the required delay, in number of clock cycles, between the time the SDRAM controller issues an ACT command and the time it issues a PRE command.

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ADSP-21161 SHARC Processor Hardware Reference

SDRAM INTERFACE

The SDTRAS bits (bits 4, 5, 6, and 7) in the SDCTL register select the tRAS value. For example:
SDTRAS=0001 SDTRAS=0010 SDTRAS=0111 SDTRAS=1111

1 clock cycle 2 clock cycles 7 clock cycles 15 clock cycles

For more details, see the SDRAM device documentation.

Selecting the Precharge Delay (SDTRP)

The tRP value (precharge delay) defines the required delay, in number of clock cycles, between the time the SDRAM controller issues a PRE command and the time it issues an ACT command. The SDTRP bits (bits 8, 9, and 10) in the SDCTL register select the tRP value. For example:
SDTRP = 001 SDTRP = 010 SDTRP = 111

1 clock cycle 2 clock cycles 7 clock cycles

Selecting the RAS-to-CAS Delay (SDTRCD)

The vendor-specific SDRAM value tRCD defines the required delay in number of clock cycles between an ACT command and the start of the first read or write operation. The SDTRCD[2:0] bits in the SDCTL register select the tRCD (RAS to CAS delay) value as follows: 001= 1 clock cycle, 010= 2 clock cycles, and 111= 7 clock cycles. For more details, see the SDRAM device documentation.
SDTRP, SDTRAS,

and SDTRCD settings represent the number of core clock (CCLK) cycles.

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Controller Standard Operation

SDRAM Controller Standard Operation

The ADSP-21161 processor SDRAM controller uses a burst length one for page read/write operations. Burst length determines the maximum number of column locations that can be accessed for a given read or write operation. The ADSP-21161 processor supports burst length one mode. This does not have an adverse impact on the throughput as compared to burst lengths of 2, 4, 8 and full page. Instead of applying the first address and continuing access to data on successive clocks (during which the controller drives the NOP command), the ADSP-21161 processor SDRAM controller applies the command at every cycle continuously accessing the data. Table 8-2 lists the data throughput rates for the processors core or DMA read/write accesses to SDRAM. The following assumptions are made for the information in this table: SDCLK is running at core clock speed (SDCKR =1) CAS latency = 2 cycles (SDCL=2) No SDRAM buffering (SDBUF=0) Precharge (tRP) = 2 cycles (SDTRP=2) Active command time (tRAS) = 3 cycles (SDTRAS=3)
tRCD

= 2 cycles (SDTRCD=2)

Understanding DAG and DMA Operation

For either core-driven accesses via the DAGs or DMA data transfers to and from SDRAM, one full page can be accessed at full throughput if the data address generator or external address increment is equal to one. If the

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ADSP-21161 SHARC Processor Hardware Reference

SDRAM INTERFACE

Table 8-2. Throughput for Core or DMA Read/Write Operations

Accesses Sequential, uninterrupted Sequential, uninterrupted Nonsequential, Uninterrupted Nonsequential, Uninterrupted Both Nonsequential Nonsequential Auto refresh before read Auto refresh before write Operations Read Write Read Write Alternating read/write Reads Writes Reads Writes Page Same Same Same Same Same Different Different Different Different Throughput per CCLK (32-bit words)1, 2 1 word/1 cycle 1 word/1 cycle 1 word/5 cycles (CL + 3) 1 word/1 cycle Average rate = 3 cycles per word (reads = 5 cycles, writes = 1 cycle) 1 word/10 cycles (tRP + CL + tRCD + 4) 1 word/7 cycles (tRP + tRCD + 3) 1 word/15 cycles (2tRP + tRAS + CL + tRCD + 4) 1 word/11 cycles (2tRP + tRAS + tRCD + 2)

1 When executing 48-bit packed instructions from 32-, 16-, or 8-bit SDRAM memories: - Add one clock cycle to the throughput value or to the average access rate for 32-bit wide SDRAM - Add three clock cycles to the throughput value or to the average access rate for 16-bit wide SDRAM - Add six clock cycles to the throughput value or to the average access rate for 8-bit wide SDRAM 2 With SDRAM buffering enabled (SBUF=1), replace any instance of (CL) with (CL + 1).

modify register or external address register is greater than a value of 1, then one full page can be written at full throughput, but reads increase the amount of processing time required.

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Controller Standard Operation

Whenever a page miss happens, the SDRAM controller executes a PRE command followed by a bank activate command before executing a read/write command. For SDRAM reads, a latency (equal to CAS latency) exists from the start of the read command until data is available from the SDRAM. For the first read in a sequence of reads, the latency always exists. Subsequent reads will not have latency if the address is sequential and uninterrupted. A fresh access to SDRAM always aligns to the CLKIN rising edge. So, interrupted access to SDRAM incur the overhead of additional cycles, depending on the CLK CFG setting. For example, WRT-NOP-WRT-NOP-WRT has a 6-cycle overhead for CLK-CFG-2:1 and SDCKR=1. Every write in the above sequence starts at the rising edge of CLKIN, and two core cycles transpire in every CLKIN. The last WRT completes in the first core cycle of the third CLKIN cycle (which is the ninth core cycle). If the three writes had been consecutive, the third write would be over by the third core cycle of the first CLKIN. As a result, the writes complete six core clock cycles later. Programmable refresh counter provides that can be used to set up a count, depending on the required refresh rate and the clock rate used. The refresh count is specified in the SDRDIV, a memory mapped IOP register. For more information on SDRDIV, see Setting the Refresh Counter Value (SDRDIV) on page 8-13.

Multiprocessing Operation
In a multiprocessing environment, the SDRAM is shared among two or more ADSP-21161 processors. SDRAM input signals (including clock) are always driven by the bus master. The slave processors track the commands that the master processor issues to the SDRAM. This feature or function helps to synchronize the SDRAM refresh counters and to prevent needless refreshing operations. A simplified multiprocessing is shown in Figure 8-6.

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ADSP-21161 SHARC Processor Hardware Reference

SDRAM INTERFACE

BR2-1 BRST ACK PA

ID=001

ADSP-21161N ID 1

1 0

SDRAM

ADSP-21161N ID 2

1 0

ID=001

BMSTR
SDRAM EP CONTROLLER SDRAM CONTROLLER EP

BMSTR

SDRAM CONTROL

ADDR 23:0

DATA47:16

Figure 8-6. Multiprocessing: Dual Processor System Example When a ADSP-21161 processor receives the bus mastership, it executes a PRE command prior to the first access to SDRAM. This occurs only if the previous master had accessed the SDRAM. In the user application code, the SDCTL and SDRDIV registers of both ADSP-21161 processors must be initialized to the same value. If there is no SDRAM used in the system (as indicated in SDCTL), then the bus transition process is the same as in the ADSP-21160.

Accessing SDRAM
To access SDRAM, the SDRAM controller multiplexes the internal 32-bit non-multiplexed address into a row address, a column address, and a bank select address for the SDRAM device, as shown in Figure 8-7. Lower bits are mapped into the column, next bit/bits are mapped into the bank select, and remaining bits are mapped into the row. This mapping is based on the page size and the number of banks in SDRAM (entered into the SDCTL register).

ADSP-21161 SHARC Processor Hardware Reference

8-25

SDRAM Controller Standard Operation

27

26

25
Row Addr. SDRAM Bank Select Column Addr.

Ext. Memory Bank Select 00 = MS0~ 01 = MS1~ 10 = MS2~ 11 = MS3~

Figure 8-7. Multiplexed 32-Bit SDRAM Address Based on the values programmed in the SDCTL register for page size and number of SDRAM banks, the SDRAM controller maps bits as follows: the lower ADDR bits into the column address the next bit or bits into the bank select address the remaining higher order bits into the row address The following tables show how the SDRAM controller maps the SDRAM address bits on the processors internal address bus to its external address pins that connect to the SDRAM. The internal and external address bus pins in the tables are defined as follows:
EA IA

= External address pins = Internal address bus For 16 M SDRAMs, A11 is the Bank Select pin. When using a 16 M SDRAM, connect the processor's A14 pin to the SDRAMs A11 pin.

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SDRAM INTERFACE

Address Mapping for SDRAM Table 8-3 through Table 8-7 provide information needed for interfacing to various SDRAMs. Table 8-3. SDRAM Size = 16 Mbit
16 Mbit SDRAM (Page Size x No. of Banks) 256 x 2 512 x 2 1024 x 2 Column Address (Page Access) IA[7:0]=>EA[7:0] IA[8:0]=>EA[8:0] IA[9:0] =>EA[9:0] Bank Select Row Address (Bank Activate) IA[19:9]=>EA[10:0] IA[20:10]=>EA[10:0] IA[21:11]=>EA[10:0]

IA[8]=>EA[14] IA[9]=>EA[14] IA[10]=>EA[14]

Table 8-4. SDRAM Size = 64 Mbit

64 Mbit SDRAM (Page Size x No. of Banks) 256 x 2 512 x 2 1024 x 2 256 x 4 512 x 4 1024 x 4 Column Address Bank Select Row Address

IA[7:0]=> EA[7:0] IA[8:0]=>EA[8:0] IA[9:0]=>EA[9:0] IA[7:0]=>EA[7:0] IA[8:0]=>EA[8:0] IA[9:0]=>EA[9:0]

IA[8] =>EA[14] IA[9]=>EA[14] IA[10]=>EA[14] IA[9:8]=>EA[14:13] IA[10:9]=>EA[14:13] IA[11:10]=>EA[14:13]

IA[21:9]=>EA[12:0] IA[22:10]=>EA[12:0] IA[23:11]=>EA[12:0] IA[21:10]=>EA[11:0] IA[22:11]=>EA[11:0] IA[23:12]=>EA[11:0]

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SDRAM Controller Standard Operation

Table 8-5. SDRAM Size = 128 Mbits

128 Mbit SDRAM (Page Size x No. of Banks) 256 x 4 512 x 4 1024 x 4 2048 x 4 Column Address Bank Select Row Address

IA[7:0]=>EA[7:0] IA[8:0]=>EA[8:0] IA[9:0]=>EA[9:0] IA[10:0]=>EA[11, 9:0]

IA[9:8]=>EA[14:13] IA[10:9]=>EA[14:13] IA[11:10]=>EA[14:13] IA[12:11]=>EA[14:13]

IA[21:10]=>EA[11], SDA10, EA [9:0] IA[22:11]=>EA[11:0] IA[23:12]=>EA[11:0] IA[24:13]=>EA[11:0]

Table 8-6. SDRAM Size = 256 Mbit

256 Mbit SDRAM (Page Size x No. of Banks) 512 x 4 1024 x 4 2048 x 4 Column Address Bank Select Row Address

IA[8:0]=>EA[8:0] IA[9:0]=>EA[9:0] IA[10:0]=>EA[11, 9:0]

IA[10:9]=>EA[14:13] IA[11:10]=>EA[14:13] IA[12:11]=>EA[14:13]

IA[23:11]=>EA[12:0] IA[24:12]=>EA[12:0] IA[25:13]=>EA[12:0]

Table 8-7. Address Ranges for Various SDRAM Device Densities and Page Size Combinations
SDRAM Device Size 16 Mbit1 1Mx16 2Mx8 4Mx4 2Mx32 4Mx16 8Mx8 16Mx4 Page Size 256 512 1024 512 256 512 1024 Address Range 0 - 0x000F FFFF (1 Mwords) 0 - 0x001F FFFF (2 Mwords) 0 - 0x003F FFFF (4 Mwords) 0 - 0x001F FFFF (2 Mwords) 0 - 0x003F FFFF (4 Mwords) 0 - 0x007F FFFF (8 Mwords) 0 - 0x00FF FFFF (16 Mwords)

64 Mbit

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SDRAM INTERFACE

Table 8-7. Address Ranges for Various SDRAM Device Densities and Page Size Combinations (Contd)
SDRAM Device Size 128 Mbit 2 4Mx32 8Mx16 16Mx8 32Mx4 16Mx16 32Mx8 64Mx4 Page Size 1024 512 1024 2048 512 1024 2048 Address Range 0 - 0x003F FFFF (4 Mwords) 0 - 0x007F FFFF (8 Mwords) 0 - 0x00FF FFFF (16 Mwords) 0 - 0x01FF FFFF (32 Mwords) 0 - 0x00FF FFFF (16 Mwords) 0 - 0x01FF FFFF (32 Mwords) 0 - 0x03FF FFFF (64 Mwords)

256 Mbit

1 2

16M and 64M devices do not have a page size of 2048. 128M and 256M devices do not have a page size of 256.

Understanding DQM Operation

The processors DQM (Data I/O Mask) pin is used only during the SDRAM powerup sequence and during a precharge command.

Executing a Parallel Refresh Command During Host Control

The ADSP-21161 processors SDRAM interface includes a separate A10 pin (SDA10) to enable the controller to execute a parallel refresh command with any non-SDRAM access. This separate pin allows the SDRAM controller to precharge the SDRAM before it issues a refresh command. Connecting this pin to the SDRAMs A10 line, instead of ADDR10 to precharge the SDRAM device, enables the processor to retain control of the SDRAM device while a host requests (using the HBR pin) and controls the external ADDR23-0 bus. Figure 8-8 shows an example ADSP-21161 system containing both a host and SDRAM. During host bus requests, the processor still retains mastership of the control pins of the SDRAM (RAS, CAS,

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Controller Standard Operation

and SDA10) when the host assumes control of the system busHBG is asserted. As a result, the single processor (or master processor in a multiprocessor system) can issue REF commands as required.
ADSP-21161
1X OR 1/2X CCLK RD WR RESET ACK SDCLK SDCKE RAS CAS CLK CKE RAS CAS WE DQM A10 CS

SDWE, SDCKE, SDCLK, MSx

CONTROLLER

SDWE DQM SDA10

SDRAM (JEDEC)

MSx

MSx

21161 CORE

D31:0

BUFFER
A14/A13

DQ31:0

BA0/BA1 A12:0

A23:0

MUX

A23:0

REDY

HBG

SBTS

CS

HBR

A23:0

D31:0

REQUEST CS CLEAR DEADLOCK OE ENABLE STROBES

HOST

Figure 8-8. SDRAM Interface Bus Slave

Powering Up After Reset

After reset, once the SDCTL register is written to in the user application code, the controller initiates the selected power-up sequence. The exact sequence is determined by SDPM bit of the SDCTL register. In a multiprocessing environment, the power-up sequence is initiated by any one of the ADSP-21161 processors. Note that a software reset does not reset the controller and does not re-initiate a power-up sequence.

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ADSP-21161 SHARC Processor Hardware Reference

SDRAM INTERFACE

Entering and Exiting Self-Refresh Mode

Writing 1 to the SDSRF bit in the SDCTL register causes the SDRAM controller to issue an SREF command to the SDRAM device. During entry into Self refresh, make sure that no SDRAM accesses are occurring and that the SDRAM has stopped bursting out data. Once the SDRAM device enters into self-refresh mode, the SDRAM controller resets the SDSRF bit in the SDCTL register. The SDSRF bit always reads as 0, regardless of a pending request. The SDRAM controller ignores other self-refresh requests (SDSRF=1) when the SDRAM device is already in self-refresh mode. The application cannot clear the SDSRF bit (SDSRF=0) to cancel self-refresh mode. The SDRAM device exits self-refresh mode only when it receives a core or DMA access request from the SDRAM controller.

SDRAM Controller Commands

This section describes each command that the SDRAM controller uses to manage the SDRAM interface. These commands are transparent to applications. A summary of the various commands used by the on chip controller for the SDRAM interface is as follows: ACT (bank activate). Activates a page in the required bank MRS (mode register set). Initializes the SDRAM operation parameters during the power-up sequence PRE (precharge). Precharges the active bank Read/Write

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SDRAM Controller Commands

REF (refresh). Causes the SDRAM to enter refresh mode and generate all addresses internally SREF (self-refresh). Places the SDRAM in self-refresh mode, in which it controls its refresh operations internally

Bank Activate (ACT) Command

A Bank Activate (ACT) command is required if the next data access is on a different page. The SDRAM controller executes a precharge (PRE) command followed by bank active (ACT) command to activate the page in the required bank. Only one bank is active at a time. The SDRAM pin state during the ACT command is shown in Table 8-9. Table 8-8. Pin State During ACT Command
Pin MSx CAS RAS SDWE SDCKE State Low High Low High High

Mode Register Set (MRS)

Mode Register Set (MRS) is a part of the power up sequence. MRS initializes SDRAM operation parameters by using address bits A0-A15 of the SDRAM as data input. An SDRAM power-up sequence is initiated by writing 1 to the SDPSS bit in SDCTL register. The exact power up sequence is determined by the SDPM bit of the SDCTL register.

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SDRAM INTERFACE

MRS

initializes the following SDRAM parameters: Burst length = 1, bits 2-0, hardwired to zero in ADSP-21161 processor Wrap type = sequential, bit 3, hardwired to zero in ADSP-21161 processor Ltmode = latency mode (CAS latency), bits 6-4, programmable in
SDCTL

Bits (14-7) always 0, hardwired in the ADSP-21161 processor While executing mode register set command, the SDRAM controller sets the unused address pins to zero. During the two clock cycles following MRS, ADSP-21161 processor does not issue any other commands. The SDRAM pin state during the MRS command is shown in Table 8-10. Table 8-9. Pin State During MRS Command
Pin MSx CAS RAS SDWE
SDCKE

State Low Low Low Low High

Precharge Command (PRE)

The PRE command is issued to precharge the active bank. The SDRAM controller executes this command if the data to be accessed is located in a different bank or in a different page in the same bank. After power up, a PRE command is issued to the SDRAM devices banks. The SDRAM pin state during the PRE command is shown in Table 8-10.

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SDRAM Controller Commands

Table 8-10. Table 10. Pin State During PRE Command

Pin MSx CAS RAS SDWE SDCKE SDA10 State Low High Low Low High High

Read/Write Command
The SDRAM controller executes a Read/Write command if the next read/write data falls in the present (currently active) page. In general, a Read interrupts a previous Read when the next access is a nonsequential address but a page miss does not occur. When a page miss does occur, the SDRAM controller precharges and activates (PRE and ACT commands) the SDRAM before issuing a Read or Write command. If the internal refresh counter (SDRDIV) asserts a refresh request, any new access is delayed until a refresh command is executed. Read Commands For the Read command, the CAS, MSx and SDA10 are asserted low to enable the SDRAM to latch the column address. The start address is set according to the column address. The delay between Active and Read commands is determined by the tRCD parameter (see SDRAM Timing Specifications on page 8-8). Data is available after the tRCD and CAS latency requirements are met. The SDRAM read timing is shown in Figure 8-9 and the pin state during the Read command is shown in Table 8-11.

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ADSP-21161 SHARC Processor Hardware Reference

SDRAM INTERFACE

T0 SDCLK

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

Command Pre NOP Act NOP Read Read Read Read NOP * CAS latency = 1 tCKE1, DQs CAS latency = 2 tCKE2, DQs CAS latency = 3 tCKE3, DQs tRP tRCD NOP NOP NOP

Data
A0

Data
A1

Data
A2

Data
A3

Data
A0

Data
A1

Data
A2

Data
A3

Data
A0

Data
A1

Data
A2

Data
A3

*burst ends after a delay = CAS latency

Figure 8-9. Read Timing Diagram Table 8-11. Pin State During a Read Command
Pin MSx CAS RAS SDWE SDCKE SDA10 State Low Low High High High Low

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SDRAM Controller Commands

Write Commands For the write command, CAS, MSx, SDWE, and SDA10 are asserted low to enable the SDRAM to latch the column address. Data is also asserted in the same cycle. The start address is set according to the column address. The write timing is shown in Figure 8-10

T0 2xCLKIN

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

DQM

Cmd

Pre

NOP

Act

NOP

Write A

Write B

NOP

NOP

Bstop

NOP

NOP

NOP

tRP CAS latency = 1, 2, 3 DQs

tRCD

Data
A0

Data
B0

Data
B1

Data
B2

masked data

Figure 8-10. Write Timing Diagram The SDRAM pin state during the Write command is shown in Table 8-12 below: Table 8-12. Pin State During Write Command
Pin MSx CAS RAS SDWE State Low Low High Low

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SDRAM INTERFACE

Table 8-12. Pin State During Write Command (Contd)

Pin SDCKE SDA10 State High Low

DMA Transfers In cases where a DMA channel is performing reads from SDRAM, the SDRAM controller issues a read command if at least one location is available in the external port DMA buffer (EPBx) FIFO. Whenever the FIFO is full, a NOP command is issued. In cases where a DMA channel is performing writes to SDRAM, the SDRAM controller issues a write command if at least one word is available in the EPBx buffer. Whenever no data is available to write, an NOP command is issued.

Refresh (REF) Command

This command is a request to the SDRAM to perform a CBR (CAS before RAS) transaction. REF causes all addresses to be generated internally in the SDRAM. This command is issued to all the external banks having SDRAMs as defined by the SDEM bits. Before executing the REF command, the SDRAM controller executes a precharge (PRE) command to the active bank (after meeting tRAS min). The next active (ACT) command is given by the controller only after a minimum delay equal to tRC. Setting the Delay Between Refresh Commands The SDRDIV register in the ADSP-21161 processor is used to set the number of clock cycles between two REF commands. Program the SDRDIV register before writing to the SDCTL register. An internal CBR REF request is

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Controller Commands

made to the SDRAM controller based on this refresh divisor value. The controller completes the present burst before servicing the refresh request. The master ADSP-21161 processor always performs the refresh command. Understanding Multiprocessing Operation In a multiprocessing environment, all ADSP-21161 processors share the SDRAM. While the ADSP-21161 processor bus master always drives SDRAM input signals (including the clock), the slave ADSP-21161 processors track the commands the master processor issues to the SDRAM. This tracking helps to synchronize the SDRAM refresh counters and to prevent needless refreshing operations. Whenever a ADSP-21161 processor needs to transfer the bus mastership to other ADSP-21161 processor, it transfers the bus only after meeting tRAS min - 1 number of cycles for the presently active row. If the refresh timer makes a refresh request during this process, the present bus master executes a refresh command (after executing precharge command to SDRAM). The current bus master continues to hold the bus for tRAS min 1 cycles before giving up the bus to the new bus master. If the REF request arrives from the refresh counter during a bus transition cycle, the new bus master immediately issues a REF command. The new bus master becomes aware of this request because the refresh counter is running on all ADSP-21161 processors. The reloading of the refresh counter occurs synchronously on all processors, as the slaves watch the external SDRAM control pins to see when the refresh command is executed by the master. When a processor receives the bus mastership, it executes a PRE command prior to the first access to the SDRAM. The current ADSP-21161 processor bus master retains mastership of the control pins of the SDRAM (RAS, CAS, SDWE, SDCKE, SDCLK, MSx, SDA10) when the host assumes control of the system bus - HBG is asserted. This enables the master ADSP-21161 processor to issue a REF command as required.

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ADSP-21161 SHARC Processor Hardware Reference

SDRAM INTERFACE

The SDRAM pin state during the REF command is shown in Table 8-13 below: Table 8-13. Pin State During REF Command
Pin MSx CAS RAS SDWE SDCKE State Low Low Low High High

Self Refresh Command (SREF)

The SREF command causes the SDRAM to perform refresh operations internally, without any external control. Before executing the SREF command, the SDRAM precharges the active bank.
SREF

mode is enabled by writing a 1 to the SDSRF bit of the SDCTL register.

During entry into SREF, make sure that no SDRAM accesses are occurring and the SDRAM has stopped bursting data. The controller automatically asserts a SREF exit cycle if a SDRAM access occurs during the SREF period. After executing a SREF exit command, the controller waits for 2 + tRC cycles to execute a CBR (CAS before RAS) refresh cycle if the refresh counter is expired already. After the CBR refresh command, the SDRAM controller waits for tRC number of cycle before executing a bank activate command. The SDRAM pin state during the SREF command is shown in Table 8-14.

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Controller Commands

Table 8-14. Pin State During SREF Command

Pin MSx CAS RAS SDWE SDCKE State Low Low Low High Low

Programming Example
This section provides a programming example written for the ADSP-21161 processor. The example shown in Listing 8-1 demonstrates how to set up the SDRAM controller to work with the ADSP-21161 processor EZ-KIT Lite. Listing 8-1. SDRAM Controller Setup for 21161 EZ-KIT Lite
/************************************************************** * * * * * * * * * * * * ***************************************************************/ Setup for the SDRAM Controller for 21161 EZ-KIT Lite * Assumes SDRAM part# Micron MT48LC16M16A1-7SE * SDCLK=100MHz tCK=8ns min @ CL=2 tRAS=50ns min tRP=20ns min tRCD=20 ns min tREF=64ms/4K rows ->SDRDIV=(2(30MHz)-CL-tRP-4)64ms/4096=937cycles 3 SDRAMs by 16 bits wide total = 16Mbit x 48 Mapped to MS0 addresses 0x00200000-0x002fffff -> SDCL=1 [CAS Latency] -> SDTRP=2 [precharge delay] -> SDTRCD=2 [CAS-to-RAS delay] * * * * * * * -> SDTRAS=3 [active command delay] *

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ADSP-21161 SHARC Processor Hardware Reference

SDRAM INTERFACE

#include "def21161.h" .SEGMENT/PM .GLOBAL pm_code; init_21161_SDRAM_controller;

init_21161_SDRAM_controller: ustat1=dm(WAIT); bit clr ustat1 0x000FFFFF; dm(WAIT)=ustat1; ustat1=0x1000; dm(SDRDIV)=ustat1; ustat1=dm(SDCTL); // SDCTL = 0x02214231; // SDCLKx = CCLK frequency, no SDRAM buffering option, 2 SDRAM banks // SDRAM mapped to bank 0 only, no self-refresh, page size 256 words // SDRAM powerup mode is prechrg, 8 CRB refs, and then mode reg set cmd // tRCD = 2 cycles, tRP=2 cycles, tRAS=3 cycles, SDCL=1 cycle // SDCLK0, SDCLK1, RAS, CAS and SDCLKE activated bit set ustat1 SDTRCD2|SDCKRx1|SDBN2|SDEM0|SDPSS|SDPGS256|SDTRP2|SDTRAS3|SDCL1; bit clr ustat1 SDBUF|SDEM3|SDEM2|SDEM1|SDSRF|SDPM|DSDCK1|DSDCTL; dm(SDCTL)=ustat1; rts; // Mask in SDRAM settings //Refresh rate // Clear MSx waitstate and mode

ADSP-21161 SHARC Processor Hardware Reference

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SDRAM Controller Commands

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ADSP-21161 SHARC Processor Hardware Reference

9 LINK PORTS

The ADSP-21161 processor has two 8-bit wide link ports, which can connect to other processor or peripheral link ports. These bidirectional ports have eight data lines, an acknowledge line, and a clock line. Link ports can operate at frequencies up to the same speed as the processors internal clock, letting each port transfer up to 8 bits of data per internal clock cycle. Link ports also have the following features: Operate independently and simultaneously. Pack data into 32- or 48-bit words; this data can be directly read by the processor or DMA-transferred to or from on-chip memory. Are accessible by the external host processor, using direct reads and writes. Have double-buffered transmit and receive data registers. Include programmable clock and acknowledge controls for link port transfers. Each link port has its own dedicated DMA channel. Provide high-speed, point-to-point data transfers to other processors, allowing differing types of interconnections between multiple DSPs. ADSP-21161 processor link ports are logically (but not electrically) compatible with previous SHARC processor (ADSP-2106x family) link ports. For more information, see Link Data Path and Compatibility Modes on page 9-9.

ADSP-21161 SHARC Processor Hardware Reference

9-1

Table 9-2 lists the pins associated with each link port. Each link port consists of eight data lines (LxDAT7-0), a link clock line (LxCLK), and a link acknowledge line (LxACK). The LxCLK line allows asynchronous data transfers and the LxACK line provides handshaking. When configured as a transmitter, the port drives both the data and LxCLK lines. When configured as a receiver, the port drives the LxACK line. Figure 9-1 shows link port connections. Table 9-1. Link Port Pins
Link Port Pin(s) LxDAT7-0 LxCLK LxACK Link Port Function Link Port x Data Link Port x Clock Link Port x Acknowledge

x denotes the link port number, 0-1

TRANSMITTER
LXDAT7-0 EACH LINK PORT LXCLK LXACK 8

RECEIVER
LXDAT7-0 LXCLK LXACK EACH LINK PORT

X DENOTES THE LINK PORT NUMBER, 0-5.

Figure 9-1. Link Port Pin Connections The link port data pins (L0DAT7-0 and L1DAT7-0)are multiplexed internally with data lines DATA15-0. If link ports are used, you cannot execute full instruction width (48-bit) transfers. To perform 48-bit transfers, you must set the correct bits IPACK[1:0] in the SYSCON register and disable the link ports.

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ADSP-21161 SHARC Processor Hardware Reference

Link Ports

Link Port to Link Buffer Assignment

There are two buffers, LBUF0 and LBUF1, that buffer the data flow through the link ports. These buffers are independent of the link ports and may be connected to any of the two link ports. The link ports receive and transmit data on their LxDAT7-0 data pins. Any of the two link buffers may be assigned to handle data for a particular link port. The data in the link buffers can be accessed with DMA or processor core control. Link port x does not necessarily connect to link buffer x. One link control register (LCTL) controls the two link ports. The link assignment register and common control information have been combined into the link control register in the ADSP-21161 processor. Link assignment bits in LCTL (similar to the LAR functionality in the ADSP-21160) assign the link buffer-to-port connections. Memory-to-memory transfers may be accomplished by assigning the same link port to two buffers, setting up a loopback mode. Figure 9-2 shows a block diagram of the link ports and link buffers.

ADSP-21161 SHARC Processor Hardware Reference

9-3

Link Port DMA Channels

Link Buffers 0-1

8/4 LDAT 7-0 8/4 External Packing Register

LBUF0 LBUF1

Link Ports 0-1

10

Cross-Bar Connection

Link Port 0 Link Port 1

mx Link Clock (1x, 1/2x, 1/3x, 1/4x) 32/48

LAB[0,1] Link Assignment bits in LCTL

Internal IOP Register

32/48 32/48/64 DM Data Bus PM Data Bus I/O Data

Figure 9-2. Link Ports and Buffers

Link Port DMA Channels

DMA channels 8 and 9 support buffers 0 and 1. The buffer channel pairings are listed in Table 9-2. For more information, see Link Port DMA on page 6-81. Do not enable SPI and link port DMA simultaneously. SPI and link port are mutually exclusive when one of the peripherals is enabled.

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ADSP-21161 SHARC Processor Hardware Reference

Link Ports

Table 9-2. DMA Channel/Link Buffer Pairing

DMA Channel # DMA Channel 8 DMA Channel 9 Link Buffer Supported Link Buffer 0 Link Buffer 1

Link Port Booting

Systems may boot the processor through a link port. For more information, see Bootloading Through The Link Port on page 6-88.

Setting Link Port Modes

The SYSCON and LCTL registers (Figure 9-3) control the link ports operating modes for the I/O processor. Table A-18 on page A-60 lists all the bits in SYSCON and Table A-25 on page A-93 lists all the bits in LCTL. The following bits control link port modes. Bits in the SYSCON and LCTL registers setup DMA and I/O processor related link port features. For information on these features, see Link Port DMA on page 6-81.

ADSP-21161 SHARC Processor Hardware Reference

9-5

Setting Link Port Modes

LCTL
0xCC
LRERR1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

L1CLKD
CCLK Divide Ratio 1 - LBUF1 00=divide by 4, 01=divide by 1 10=divide by 2, 11=divide by 3

Rcv. Pack Error Status for Link Buffer 1 1=incomplete, 0=complete

LRERR0
Rcv. Pack Error Status for Link Buffer 0 1=incomplete, 0=complete

L1PDRDE
Link Port 1 Pulldown Resister Disable

L1STAT[1:0]
Link Buffer 1 Status (Read- Only) 11=Full, 00=Empty, 10=one word

L1DPWID
Link Buffer 1 Data Path Width 1=8-bits, 0=4-bits

L0STAT[1:0]
Link Buffer 0 Status (Read-Only) 11=Full, 00=Empty, 10=one word

LAB0
Link Port Assignment for LBUF0 0=Link Port 0, 1=Link Port 1

LAB1
Link Port Assignment for LBUF1 0=Link Port 0, 1=Link Port 1

15 14 13 12 0 L1CLKD
CCLK Divide Ratio 0 - LBUF1

11 10 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

L0EN
Link Buffer 0 Enable 1=enable, 0=disable

L1EXT
Link Buffer 1 Extended Word Size 1=48-bit transfers, 0=32-bit transfers

L0DEN
Link Buffer 0 DMA Enable 1=enable DMA 0=disable DMA

L1TRAN
Link Buffer 1 Data Direction 1=Transmit, 0=Receive

L0CHEN
Link Buffer 0 DMA Chaining Enable 1=enable chaining, 0=disable chaining

L1CHEN
Link Buffer 1 DMA Chaining Enable 1=enable chaining, 0=disable chaining

L0TRAN
Link Buffer 0 Data Direction 1=Transmit, 0=Receive

L1DEN
Link Buffer 1 DMA Enable 1=enable DMA, 0=disable DMA

L0EXT
Link Buffer 0 Extended Word Size 1=48 -bit transfers, 0=32 -bit transfers

L1EN
Link Buffer 1 Enable 1=enable DMA, 0=disable DMA

L0CLKD[1:0]
CCLK Divide Ratio- LBUF0 00=divide by 4, 01=divide by 1, 10=divide by 2, 11=divide by 3

L0DPWID
Link Buffer 0 Data Path Width 1=8-bits, 0=4-bits

L0PDRDE
Link Port 0 Pulldown Resister Disable

Figure 9-3. LCTL Register

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ADSP-21161 SHARC Processor Hardware Reference

Link Ports

Link Port Control Register (LCTL) Bit Descriptions

Note: x denotes 0 for LBUF0-related control bits, or 1 for LBUF1-related control bits. Link Buffer Enable. Bits 0 and 10 (LxEN). This bit enables (if set, =1) or disables (if cleared, =0) the corresponding link buffer (LBUF0 or LBUF1). When the processor disables the buffer (LxEN transitions from high to low), the processor clears the corresponding LxSTAT and LxRERR bits. Link Buffer DMA Enable. Bits 1 and 11 (LxDEN). This bit enables (if set, =1) or disables (if cleared, =0) DMA transfers for the corresponding link buffer (LBUF0 or LBUF1). Link Buffer DMA Chaining Enable. Bits 2 and 12 (LxCHEN). This bit enables (if set, =1) or disables (if cleared, =0) DMA chaining for the corresponding link buffer (LBUF0 or LBUF1) Link Buffer Transfer Direction. Bits 3 and 13 (LxTRAN). This bit selects the transfer direction (transmit if set, =1) (receive if cleared, =0) for corresponding link buffer (LBUF0 or LBUF1). Link Buffer Extended Word Size. Bits 4 and 14 (LxEXT). This bit selects the transfer extended word size (48-bit if set, =1) (32-bit if cleared, =0) for the corresponding link buffer (LBUF0 or LBUF1). Programs must not change a buffers LxEXT setting while the buffer is enabled. The buffers LxEXT setting overrides the internal memory blocks setting IMDWx for Normal word width. Whether buffer is set for 48or 32- bit words, programs must index (IIx) the corresponding DMA channel with a Normal word address.

ADSP-21161 SHARC Processor Hardware Reference

9-7

Setting Link Port Modes

Link Port Clock Divisor. Bits 6-5 and 16-15 (LxCLKD). These bits select the transfer clock divisor for link buffer x (LBUF0 or LBUF1). The transfer clock equals the processor core clock divided by LxCLKD, where L0CLKD[6-5] and L1CLKD[16-15]is: 01=1, 10=2, 11=3, or 00=4. Link Port Pulldown Resistor Disable. Bit 8 and 18 (LxPDRDE).This bit disables (if set, =1) or enables (if cleared, =0) the internal pulldown resistors on the LxCLK, LxACK, and LxDAT7-0 pins of the corresponding unassigned or disabled link port; this bit applies to the port which is not necessarily the port assigned to link buffer x (LBUF0 or LBUF1). For revisions 0.3, 1.0 and 1.1, LxCLK,LxDAT7-0 and LxACK have a 50k internal pulldown resistor. For revisions 1.2 and greater, LxDAT7-0 has a 20k internal pulldown resistor. See Table 13-3 for a description of resistor values of the pins. Systems should not leave link port pins (LxCLK, LxACK, and LxDAT7-0) unconnected without clearing the corresponding LxPDRDE bit or applying an external pulldown. In systems where several DSPs share a link port, only one processor should have this bit cleared. Link Port Data Path Width. Bits 9 and 19 (LxPDPWID). This bit selects the link port data path width (8-bit if set, =1) (4-bit if cleared, =0) for the corresponding link buffer (LBUF0 or LBUF1). Systems using a 4-bit width should connect the lower link port data pins (LxDAT3-0) for data transfers and leave the upper pins (LxDAT7-4) unconnected. In the 4-bit mode, the processor applies pulldowns to the upper pins. Link Port Assignments for LBUF0. Bit 20 (LAB0). This bit assigns link buffer 0 to link port 1 if set (=1) or link port 0 if cleared (=0). Link Port Assignments for LBUF1. Bit 21 (LAB1). This bit assigns link buffer 1 to link port 1 if set (=1) or link port 0 if cleared (=0).

9-8

ADSP-21161 SHARC Processor Hardware Reference

Link Ports

Link Buffer Status. Bits 23-22 and 25-24 (LxSTAT). These bits identify the status of the corresponding link buffer as follows: 11=full, 00=empty, 10=one word. Receive Packing Error Status. Bit 27 and 26 (LRERRx). This bit indicates if the packed bits in the corresponding link buffer were receive completely (=0), without error, or incompletely (=1). If multiple link ports are bussed together and the link port pulldown resistor is enabled on all the processors, the line is heavily loaded. Ensure only one processor has this functionality. The processors internal clock (CCLK) is the CLKIN frequency multiplied by a clock ratio (CLK_CFG1-0)and the CLKDBL pin (1:1 or 2:1 ratio). For more information, see the clock ratio pin description in Table 13-1 on page 13-4. When link buffers are enabled or disabled, the I/O processor may generate unwanted interrupt service requests if Link Service Request (LSRQ) interrupts are unmasked. To avoid unwanted interrupts, programs should mask the LSRQ interrupts while enabling or disabling link buffers. For more information, see Using Link Port Interrupts on page 9-17.

Link Data Path and Compatibility Modes

The link ports can transmit and received data using all eight of the link ports data pins (LxDAT7-0) or the four lower data pins (LxDAT3-0). The LxDPWID bit in the LCTL register selects the link port data path width (8-bit if set, =1) (4-bit if cleared, =0). Before changing the mode of the link port, disable the link port. After the port is disabled, a new control word can be written to LCTL. When LxDPWID is cleared (4-bit data path), the ADSP-21161 processor can be connected to link ports of previous SHARC processors (ADSP-2106x family). The link port receiver must run

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9-9

Using Link Port Handshake Signals

at the same speed or faster than the transmitter. Connecting to an ADSP-2106x may require that the ADSP-21161 processor be configured for 1/2 core clock rate operation. For more information, see Using Link Port Handshake Signals on page 9-10.

Using Link Port Handshake Signals

The LxCLK and LxACK pins of each link port allow handshaking for asynchronous data communication between DSPs. Other devices that follow the same protocol may also communicate with these link ports. The processor link ports are backward compatible with the SHARC link ports for basic transfers, including LSRQ functions. A SHARC compatible link can be enabled by adjusting the upper LxCLKD bit in the LCTL register and by clearing the LxDPWID bit in the LCTL register, enabling the 4-bit data path. The link port receiver must run at the same speed or faster than the transmitter. Connecting to an ADSP-2106x may require that the ADSP-21161 processor be configured for 1/2 core clock rate operation. A link-port-transmitted word consists of 4 bytes (for a 32-bit word) or 8 nibbles or 6 bytes (for a 48-bit word) or 12 nibbles. The transmitter asserts the clock (LxCLK) high with each new byte of data. The falling edge of LxCLK is used by the receiver to latch the byte. The receiver asserts LxACK when it is ready to accept another word in the buffer. The transmitter samples LxACK at the beginning of each word transmission (that is, after every 4 or 6 bytes). If LxACK is deasserted at that time, the transmitter does not transmit the new word. For more information, see Figure 9-4. The transmitter leaves LxCLK high and continues to drive the first byte if LxACK is deasserted. When LxACK is eventually asserted again, LxCLK goes low and begins transmission of the next word. If the transmit buffer is empty, LxCLK remains low until the buffer is refilled, regardless of the state of LxACK. 9-10 ADSP-21161 SHARC Processor Hardware Reference

Link Ports

LCLK STAYS HIGH AT BYTE 0 I F LACK IS SAMPLED LOW ON PREVI OUS LCLK RISING EDGELCLK HIGH INDICATES A STALL

LXCLK

MINIMUM LACK SET-UP TIME

LXACK TRANSMI TTER SAMPLES LACK WILL REASSERT LACK HERE TO DETERMINE AS SOON AS THE LINK WHETHER TO TRANSMIT BUFFER IS "NOT FULL " NEXT WORD BYTE 2 BYTE 3 (32-BIT) OR BYTE 5 (48-BIT) (LSBS) BYTE 0 (MSBS)

LXACK MAY DEASSERT AF TER BYTE 0

LXDAT7-0

BYTE 1

RECEIVER WILL ACCEPT REMAINING B YTES IN THE CURRENT WORD EVEN IF LACK IS DEASSERTED. THE TRANSMITTER WILL NOT SEND TH E FOLLOWI NG WO RD.

TRANSMIT DATA FOR NEXT WORD IS HELD UNTIL LACK IS ASSERTED

Figure 9-4. Link Port Handshake Timing The receive buffer may fill if a higher priority DMA, core I/O processor register access, direct read, direct write or chain loading operation is occurring. LxACK may de-assert when it anticipates the buffer may fill. LxACK is reasserted by the receiver as soon as the internal DMA grant signal has occurred, freeing a buffer location. Data is latched in the receive buffer on the falling edge of LxCLK. The receive operation is purely asynchronous and can occur at any frequency up to the processor clock frequency. When a link port is not enabled, LxDAT7-0, LxCLK and LxACK are three-stated. When a link port is enabled to transmit, the data pins are driven with whatever data is in the output buffer, LxCLK is driven high and LxACK is three-stated. When a port is enabled to receive, the data pins and LxCLK are three-stated and LxACK is driven high.

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Using Link Buffers

To allow a transmitter and a receiver to be enabled (assigned and link buffer enabled) at different times, LxACK, LxCLK, and LxDAT7-0 may be held low with their internal pull-down resistor if LxPDRDE is cleared when the link port is disabled. LxDAT7-0 is kept at the previously driven value by internal keeper latches on the link port data lines if LxPDRDE is cleared when the link port is disabled. If the transmitter is enabled before the receiver, LxACK is low and the transmission is held off. If the receiver is enabled before the transmitter, LxCLK is held low by the pulldown and the receiver is held off. If many link ports are bused together, the systems may need to enable only one of the internal resistors to pull down each bused pin, so the bused lines are not pulled down too strongly or too heavily loaded. Refer to Table 13-1 on page 13-4 for detailed pin descriptions and Table 13-3 on page 13-22 for more information on pull down resistors.
LxACK, LxCLK,

and LxDAT7-0 should not be left unconnected unless external pull-down resistors are used.

Using Link Buffers

Each link buffer consists of an external and an internal 48-bit register. For more information, see Figure 9-2 on page 9-4. When transmitting, the internal register is used to accept core data or DMA data from internal memory. When receiving, the external register performs the packing and unpacking for the link port, most significant nibble or byte first. These two registers form a two-stage FIFO for the LBUFx buffer. Two writes (32or 48-bit) can occur to the register by the DMA or the core, before it signals a full condition. As each word is unpacked and transmitted, the next location in the FIFO becomes available and a new DMA request is made. If the register becomes empty, the LxCLK signal is de-asserted. When transmitting, only the number of words written are transmitted.

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ADSP-21161 SHARC Processor Hardware Reference

Link Ports

Full/empty status for the link buffer FIFOs is given by the LxSTAT bits of the LCTL register. This status is cleared for a link buffer when its LxEN enable bit is cleared in the LCTL register. During receiving, the external buffer is used to pack the receive link port data (most significant nibble or byte first) and pass it to the internal register before DMA-transferring it to internal memory. This buffer is a two-deep FIFO. If the processors DMA controller does not service it before both locations are filled, the LxACK signal is de-asserted. The link buffer width may be selected to be either 32 or 48 bits. This selection is made individually for each buffer with the LxEXT bits in the LCTLx register. For 40-bit extended precision data or 48-bit instruction transfers, the width must be set to 48 bits.

Core Processor Access To Link Buffers

In applications where the latency of link port DMA transfers to and from internal memory is too long, or where a process is continuous and has no block boundaries, the processor core may read or write link buffers directly using the full or empty status bit of the link buffer to automatically pace the operation. The full or empty status of a particular LBUFx buffer can be determined by reading the LxSTATx bits in LCTL. DMA should be disabled when using this capability (LxDEN=0). If a read is attempted from an empty receive buffer, the core stalls (hangs) until the link port completes reception of a word. If a write is attempted to a full transmit buffer, the core stalls until the external device accepts the complete word. Up to four words (2 in the receiver and 2 in the transmitter) may be sent without a stall before the receiver core or DMA must read a link buffer register.

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9-13

Using Link Buffers

To support debugging buffer transfers, the processor has a Buffer Hang Disable (BHD) bit. When set (=1), this bit prevents the processor core from detecting a buffer-related stall condition, permitting debugging of this type of stall condition. For more information, see the BHD discussion on page on page 6-43.

Host Processor Access To Link Buffers

When a 32-bit, 16-bit, or 8-bit host processor normally accesses IOP register space (with the exception of LBUFx and EPBx buffers), the ADSP-21161 defaults to pack and unpack data internally (independent of the setting of the PMODE bits in the DMACx register) to a 32-bit access. The link buffers LBUF0 and LBUF1 can also be accessed by an external host processor, using direct reads and writes to IOP register space. However, there is a difference in how data is accessed with the link buffers compared to other IOP registers accessed as 32-bit data. Host accessing link port buffers pack or unpack to 48-bits internally, ignoring the value of PMODE in DMACx, but using the HBW bits in SYSCON to set the external packing mode. In the case where a host processor reads or writes to the LBUF0 and LBUF1 link buffers, the PMODE bits in DMACx external port DMA control register are ignored and are hardwired to a special 48-bit internal packing mode. A fixed packing mode for an 8-, 16-, or 32-bit (corresponding to the host bus width (HBW) bits in SYSCON) external host to 48-bits internal is selected. This fixed 48-bit internal packing mode is required due to the fact that the ADSP-21161 link port buffers can transmit/receive 48-bit words. It may be desirable in some applications for a host processor to transfer instruction opcodes to another SHARC indirectly via the directly connected SHARC's link port by reading or writing the opcode data to or from the LBUF0 and LBUF1 link buffers through the external port. For example, with a 16-bit host, the packing mode internally defaults to 48-bit packed transfers. The packing mode is 16 external to 48-bit internal.

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ADSP-21161 SHARC Processor Hardware Reference

Link Ports

Depending on the HBW (host bus width) bits in SYSCON, the appropriate 48-bit internal packing mode is selected. Table 6-7 on page 6-36 summarizes the packing mode bit settings for access to link port buffers. Host packing examples are shown below for host direct read/write access to LBUFx link port data buffers. When interfacing to a host processor, the HMSWF bit determines whether the I/O processor packs to most significant 16-bit word first (=1)or least significant 16-bit word first (=0). The packing mode defaults to 48-bit internal packing for host accesses to LBUFx, ignoring PMODE value in DMACx. Table 9-3. Packing Sequence for 16-Bit Bus (MSW First)
Transfer First Second Third Data Bus Pins 31-16 Word 1; bits 47-32 Word 1; bits 31-16 Word 1; bits 15-0

Table 9-4. Packing Sequence for 16-Bit Bus (LSW First)

Transfer First Second Third Data Bus Pins Word 1; bits 15-0 Word 1; bits 31-16 Word 1; bits 47-32

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Using Link Port DMA

Table 9-5. Packing Sequence from 8-bit bus (MSW first)

Transfer First Second Third Fourth Fifth Sixth Data Bus Pins 23-16 Word 1; bits 47-40 Word 1; bits 39-32 Word 1; bits 31-24 Word 1; bits 23-16 Word 1; bits 15-8 Word 1; bits 7-0

Table 9-6. Packing sequence from 8-bit bus (LSW first)

Transfer First Second Third Fourth Fifth Sixth Data Bus Pins 23-16 Word 1; bits 7-0 Word 1; bits 15-8 Word 1; bits 23-16 Word 1; bits 31-24 Word 1; bits 39-32 Word 1; bits 47-40

To write a single 48-bit word or an odd number of 48-bit words to LBUFx, write a dummy access to completely fill the packing buffer, or write the HPFLSH bit in SYSCON to flush the partially filled packing buffer and remove the unused word. The HPFLSH bit clears the HPS bits in SYSTAT as well.

Using Link Port DMA

DMA channels 8-9 support link buffers 0-1. These DMA channels are shared with the SPI transmit and receive buffers. A maskable interrupt is generated when the DMA block transfer has completed. For more infor-

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Link Ports

mation on link port interrupts, see Using Link Port Interrupts on page 9-17. For more information on link port DMA, see Link Port DMA on page 6-81. The link port channels share DMA channels 8 and 9 with the SPI transmit and receive buffers. Do not enable SPI and link port DMA simultaneously. SPI and link port are mutually exclusive when one of the peripherals is enabled. In chained DMA operations, the processor automatically sets up another DMA transfer when the current DMA operation completes. The chain pointer register (CPLB0, and CPLB1) is used to point to the next set of buffer parameters stored in memory. The processors DMA controller automatically downloads these buffer parameters to set up the next DMA sequence. For information on setting up DMA chaining, see Chaining DMA Processes on page 6-25.

Using Link Port Interrupts

Three types of interrupts are dedicated to the link ports: The I/O processor generates a DMA channel interrupt when a DMA block transfer through the link port with DMA enabled (LxDEN=1) finishes. The I/O processor generates a DMA channel interrupt when DMA for the link buffer channel is disabled (LxDEN=0) and the buffer is not full (for transmit) or the buffer is not empty (for receive). The I/O processor generates a Link Services Request (LSRQ) interrupt when an external source accesses a disabled link port, an unassigned link port or assigned port with buffer disabled. Although the link ports and the SPI port share DMA channels 8 and 9, there are different interrupt vector locations dedicated for these two peripherals. The LIRPTL register controls both the link port and SPI transADSP-21161 SHARC Processor Hardware Reference 9-17

Using Link Port Interrupts

mit/receive interrupt latching and masking functions. The IRPTL register controls a single global link port interrupt that latches the LPISUM bit. This bit indicates whether at least one of the two unmasked link port interrupt is latched. Refer to Figure 9-5 and Table A-10 on page A-34 for complete bit description of the LIRPTL register. During reset, if a link port boot is enabled, the mask bit for LBUF0 (bit 16) is set (for example, the interrupt is unmasked). If a SPI boot is enabled, the mask bit for SPI receive (bit 18) is set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LIRPTL
SPITMSKP

LP0MSK
Link Buffer 0 DMA Interrupt Mask

SPI Transmit DMA Interrupt Mask Pointer

LP1MSK
Link Buffer 1 DMA Interrupt Mask

SPIRMSKP
SPI Receive DMA Interrupt Mask Pointer

SPIRMSK
SPI Receive DMA Interrupt Mask

LP1MSKP
Link Buffer 1 DMA Interrupt Mask Pointer

SPITMSK
SPI Transmit DMA Interrupt Mask

LP0MSKP
Link Buffer 0 DMA Interrupt Mask Pointer 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 4 0 3 2 1 0 0 0

0 0

SPITI
SPI Transmit DMA Interrupt Latch (0x44)

LP0I
Link Buffer 0 DMA Interrupt Latch Interrupt Vector Address Offset- 0x38

SPIRI
SPI Receive DMA Interrupt Latch (0x40)

LP1I
Link Buffer 1 DMA Interrupt Latch (0x3c)

Figure 9-5. LIRPTL Register

Link Port Interrupts With DMA Enabled

A link port interrupt is generated when the DMA operation is done when the block transfer has completed and the DMA count register is zero.

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ADSP-21161 SHARC Processor Hardware Reference

Link Ports

One way programs can use this interrupt is to send additional control information at the end of a block transfer. Because the receive DMA buffer is empty when the DMA block has completed, the external bus master can send up to two additional words to the slave processors buffer, which has space for the two words. When the slavess DMA completes, there is an interrupt. In the associated interrupt service routing, the buffer can be read in order to use these control words to determine the next course of action.

Link Port Interrupts With DMA Disabled

If DMA is disabled for a link port buffer, then the buffer may be written or read by the processor core as a memory-mapped I/O processor register. If the DMA is disabled but the associated link buffer is enabled, then a maskable interrupt is generated whenever a receive buffer is not empty or when a transmit buffer is not full. This interrupt is the same interrupt vector associated with the completion of the DMA block transfers. The interrupt latch bit in LIRPTL may be unmasked by the corresponding mask bit in the same register. When initially enabling the mask bit, the corresponding latch bit in LIRPTL should be cleared first to clear out any request that may have been inadvertently latched. The interrupt service routine should test the buffer status after each read or write to check when the buffer is empty or full, in order to determine when it should return from interrupt. This will reduce the number of interrupts it must service.

Link Port Service Request Interrupts (LSRQ)

Link port service requests let a disabled (unassigned or assigned with buffer disabled) link port cause an interrupt when an external access is attempted. The transmit and receive request status bits of the LSRQ register indicate when another processor is attempting to send or receive data

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Using Link Port Interrupts

through a particular link port. Two processors can communicate without prior knowledge of the transfer direction, link port number, or exactly when the transfer is to occur. The LRSQ register is shown in Figure 9-6 and described in Table A-26 on page A-98.
LSRQ 0xD0
L1RRQ
Link Port 1 Receive Request

31 0

30 29 0 0

28 0

27 0

26 25 24 0 0 0

23 22 0 0

21 0

20 0

19 0

18 0

17 0

16 0

L0TRQ
Link Port 0 Transmit Request

L1TRQ
Link Port 1 Transmit Request

L0RRQ
Link Port 0 Receive Request

15 14 0 L1RM 0

13 0

12 0

11 0

10 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0 L0TM
Link Port 0 Transmit Mask

Link Port 1 Receive Mask

L1TM
Link Port 1 Transmit Mask

L0RM
Link Port 0 Receive Mask

Figure 9-6. LSRQ Register In Figure 9-6, for transmit request status bits, LxTRQ=1 means LxACK=1, LxTM=1, and LxEN=0; for receive request status bits, LxRRQ=1 means LxCLK=1, LxRM=1, and LxEN= When LxACK or LxCLK is asserted externally, a link service request (LSR) is generated in a disabled (unassigned or assigned with buffer disabled) link port. LSRs are not generated for a link port that is disabled by loopback mode. Each LSR is gated by mask bits before being latched in the LSRQ register. The two possible receive LSRs and the two possible transmit LSRs are gated by mask bits and then ORed together to generate the link service request interrupt. The LSRQ interrupt request may be masked by

9-20

ADSP-21161 SHARC Processor Hardware Reference

Link Ports

the LSRQI mask bit of the IMASK register. When the mask bit is set, the interrupt is allowed to pass into the interrupt priority encoder. A diagram of this logic appears in Figure 9-7.
LSRQ IMASK, LSRQ I

LXRRQ

LSR STATUS

LINK SER VICE REQUEST INTERRUPT

LXTRQ

LSR MASK

IRPTL, LSRQI MO DE1, IRPTEN

Figure 9-7. Logic for Link Port Interrupts The interrupt routine must read the LSRQ register to determine which link port to service and whether it is a transmit or receive request. LSR interrupts have a latency of two cycles. Note that the link service request interrupt is different from the link receive and transmit interruptthis is also true in IMASK. The 32-bit LSRQ register holds the masked link status of each link port and the corresponding interrupt mask bits. The link service request status of the port is set whenever the port is not enabled and one of LxACK or LxCLK is asserted high. The LSRQ status bits are read-only. Table A-26 on page A-98 shows the individual bits of the LSRQ register. To determine which link port to service, programs can transfer LSRQ to a register Rx (in the register file) and use the leading 0s detect instruction: Rn=LEFTZ Rx. Here, Rn indicates which link port is active in order of priority. If link service requests are in use, they should be masked out when the assigned link buffers are being enabled, disabled, or when the link port is being unassigned in LCTL. Otherwise, spurious service requests may be generated.

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Detecting Errors on Link Transmissions

The need for masking is due to a delay before LxCLK or LxACK (if already asserted) signals are pulled (if pulldowns enabled) or driven externally (if pulldowns disabled) below logic threshold. During this delay, these signals are sampled asserted and generate an LSRQ. To avoid the possibility of spurious interrupts, programs should mask the LSRQ interrupt or the appropriate request bit in the LSRQ register and allow a delay before unmasking. Alternatively, programs can mask the LSRQ interrupt and poll the appropriate request status bit until it is cleared and then unmask the interrupt.

Detecting Errors on Link Transmissions

Transmission errors on the link ports may be detected by reading the LRERRx bits (bits 26 and 27) in the LCTL register. These bits reflects the status of each nibble or byte counter. The LRERRx bit is cleared (=0) if the pack counter of the corresponding link buffer is zeroa multiple of 8 or 12 nibbles or bytes have been received. If LRERR is set (=1) when a transmission has completed, then an error occurred during transmission. The DMA word count provides an exact count of the number of words to be transferred. To allow checking of this status, the transmitter and receiver should follow a protocol such as the following: Transmitter ProtocolTo make use of the LRERRx status, one additional dummy word should always be transmitted at the end of a block transmission. The transmitter must then deselect the link port and re-enable as a receiver to allow the receiver to send an appropriate message back to the transmitter. Receiver ProtocolWhen the receiver has received the data block, indicated by a the same interrupt vector associated with the completion of the link port DMA, it checks that it has received an

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Link Ports

additional word in the link buffer and then reads the LRERR bit. The receiver may then clear the link buffer (LxEN=0) and transmit the appropriate message back to the transmitter on the same, or a different, link port.

Link Port Programming Examples

This section provides two programming examples written for the ADSP-21161 processor. The example shown in Listing 9-1 demonstrates how the core directly writes to the link port transmit buffer and reads from the link port receive buffer after an interrupt. The example shown in Listing 9-2 demonstrates how the core directly reads from the link port receive buffer and writes to the link port transmit buffer. Listing 9-1. Interrupt Core-Driven Link Loopback Example
/*______________________________________________________________ ADSP-21161 Interrupt Core-Driven LINK Loopback Example This example shows an internally looped-back link port 32-bit transfer. The core directly writes to the transfer link buffer (LBUF1) and reads from the receive link buffer (LBUF0). The core will hang on the read of LBUF0 until the data is ready. Loopback is achieved by assigning the transmit and receive link buffers to the same port. (Port 0) ______________________________________________________________*/ #include "def21161.h" #define N 8 .section/pm seg_rth; nop; jump start; /* Reset vector from ldf file */

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Detecting Errors on Link Transmissions

.section/dm seg_dmda;

/* Data section from ldf file */

.var source[N]= 0X11111111, 0X22222222, 0X33333333, 0X44444444, 0X55555555, 0X66666666, 0X77777777, 0X88888888; .var dest[N]; .section/pm lp1i_svc; /*Link Port 1 interrupt vector from ldf file */ jump lpISR1; nop; nop; nop; .section/pm lp0i_svc; /*Link Port 0 interrupt vector from ldf file */ jump lpISR1; nop; nop; nop; /*_____________________Main Routine________________________*/ .section/pm seg_pmco; start: B0=source; L0=@source; B1=dest; L1=@dest; /*Enable Global, Link Port, and Link Port Buffer 1 interrupts*/ bit set imask LPISUMI; bit set lirptl LP1MSK; bit set mode1 IRPTEN | CBUFEN; ustat1=dm(LCTL); /* LCTL REGISTER--LBUF1=TX, LBUF0=RX, 1/2x CCLK RATE, LBUF 0 & 1ENABLED, LBUF 0 & 1 -> PORT 0 */ bit clr ustat1 L0TRAN | LAB0 | LAB1 | L0CLKD0 | L1CLKD0; bit set ustat1 L1TRAN | L1EN | L0EN | L0CLKD1 | L1CLKD1; dm(LCTL)=ustat1; /* Enable circular buffers */ /* Set pointers for source and dest */ /* Main code section from ldf file */

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Link Ports

wait: idle; jump wait; lpISR1: R0=dm(I0,1); dm(LBUF1)=R0; R1=dm(LBUF0); dm(I1,1)=R1; rti; /* Link Port Service Routine */ /* Get data for TX */ /* Write data to LBUF1 */ /* Read data-core will hang here until data is received. */ /* Store incoming data to dest buffer */

Listing 9-2. Core-Driven Link Loopback Example

/*____________________________________________________________ ADSP-21161 Core-Driven LINK Loopback Example This example shows an internally looped-back link port 32-bit transfer. The core directly writes to the transfer link buffer (LBUF1) and reads from the receive link buffer (LBUF0). The core will hang on the read of LBUF0 until the data is ready. Loopback is achieved by assigning the transmit and receive link buffers to the same port. (Port 0) ______________________________________________________________*/ #include "def21161.h" #define N 8 .section/pm seg_rth; nop; jump start; .section/dm seg_dmda; /* Data section from ldf file */ /* Reset vector from ldf file */

.var source[N]= 0X11111111, 0X22222222, 0X33333333, 0X44444444, 0X55555555, 0X66666666, 0X77777777, 0X88888888;

ADSP-21161 SHARC Processor Hardware Reference

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Detecting Errors on Link Transmissions

.var dest[N]; /*________________________Main Routine________________________*/ .section/pm seg_pmco; start: r0=0; DM(LCTL)=r0; B0=source; L0=@source; B1=dest; L1=@dest; ustat1=dm(LCTL); /* LCTL REGISTER-->LBUF1=TX, LBUF0=RX, 2x CLK RATE, LBUF 0 & 1 ENABLED, LBUF 0 & 1 -> PORT 0 */ bit clr ustat1 L0TRAN | L0CLKD0 | L1CLKD0 | LAB0 | LAB1; bit set ustat1 L1TRAN | L1EN | L0EN | L0CLKD1 | L1CLKD1; dm(LCTL)=ustat1; lcntr=N, do transfer until lce; R0=dm(I0,1); dm(LBUF1)=R0; R1=dm(LBUF0); /* Test data to TX */ /* Write data to LBUF1 */ /* Read data-core will hang here until data is received. */ transfer: dm(I1,1)=R1; wait: idle; jump wait; / *Store incoming data to dest buffer */ /* Clear LCTL register */ /* Set up pointers for source and dest */ /* Main code section from ldf

*/

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Link Ports

Using Token Passing With Link Ports

When two DSPs communicate using a link port only one can be the transmitter or receiver. Token passing is a protocol that assists the DSPs alternate control. Figure 9-8 shows a flow chart of the token passing process. In token passing, the token is a software flag that passes between the processors. At reset, the token (flag) is set to reside in the link port of one device, making it the master and the transmitter. When a receiver link port (slave) wants to become the master, it may assert its LxACK line (request data) to get the masters attention. The master knows, through software protocol, whether it is supposed to respond with actual data or whether it is being asked for the token. The token release word can be any user-defined value. Since both the transmitter and receiver are expecting a code word, this does not need to be exclusive of normal data transmission. If the master wishes to give up the token, it may send back a user-defined token release word and thereafter clear its token flag. Simultaneously, the slave examines the data sent back and if it is the token release word, the slave will set its token, and can thereafter transmit. If the received data is not the token release word, then the slave must assume the master was beginning a new transmission. Through software protocol, the master can also ask to receive data by sending the token release word without the LxACK (data request) going low first.

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Using Token Passing With Link Ports

ORIGINAL MASTER
DMA TRANSFER COMPLETE LBUF DISABLED LSRQ INTERRUPT ENABLED

ORIGINAL SLAVE
DMA TRANSFER COMPLETE LBUF DISABLED LBUF RX NON-DMA ENABLED

LACK ASSERTION CAUSES LSRQ INTERRUPT LBUF TX NON-DMA ENABLED SEND TRW 4 TIMES TO FILL LBUF FIFOS ON BOTH SIDES CHECK LCTL FOR SLAVE READ OF TRW BEFORE ACCEPTANCE TEST

READ LBUF TEST FOR TRW

CHECK LCTL TO SEE IF SLAVE ACCEPTED TOKEN BY EMPTYING FIFOS IN AN ALLOTTED TIME PERIOD

ACCEPT TOKEN BY EMPTYING LBUF FIFOS THROUGH 3 MORE READS WITHIN THE ALLOTTED TIME PERIOD

SETUP LBUF FOR RX NON-DMA TO ACCEPT DMA SIZE SETUP LBUF FOR RX DMA AND DMA COMPLETE IRQ

DISABLE LBUF AND LSRQ INTERRUPT POLL LSRQ STATUS FOR LINK PORT TRANSMIT REQUEST TO BE SURE THAT THE ORIGINAL MASTER IS NOW A SLAVE

LACK ASSERTION ASSURES THAT IT IS SAFE TO BEGIN TRANSMITTING SETUP LBUF FOR TX NON-DMA TO SEND DMA SIZE SETUP LBUF FOR TX DMA AND DMA COMPLETE INTERRUPT

DMA TRANSFER COMPLETE SETUP LBUF FOR RX NON-DMA

DMA TRANSFER COMPLETE SETUP LBUF FOR TX NON-DMA

Figure 9-8. Token Passing Flow Chart

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Link Ports

To use the example, the example code is to be loaded on both the original master and the original slave. The code is ID intelligent for multiprocessor systems: ID1 is the original master (transmitter) and ID2 is original slave (receiver). The master transmits a buffer via DMA through link port 0 using LBUF1 and the slave receives through link port 0 using LBUF0. The slave then requests the token by generating an LSRQ interrupt in the disabled link port of the master (LPORT0). The master responds by sending the token release word and waiting to see if it is accepted. The slave checks to see that it is the token release word and accepts the token by emptying the masters link buffer FIFO within a predetermined amount of time. If the token is accepted the slave becomes the master and transmits a buffer of data to the new slave. If the token is rejected, the master transmits a second buffer. When complete, the original master will finish by setting up LBUF0 to receive without DMA, and the original slave sets up LBUF1 to transmit without DMA. The following is a list of the areas of concern when a program implements a software protocol scheme for token passing: The program must make sure that both link buffers are not enabled to transmit at the same time. In the event that this occurs, data may be transmitted and lost due to the fact that neither link port is driving LxACK. In the example, the LSRQ register status bits are polled to ensure that the master becomes the slave before the slave becomes the master, avoiding the two transmitter conflict. The program must make sure that the link interrupt selection matches the application. If a status detection scheme using the status bits of the LSRQ register is to be used, it is important to note the following: If a link port that is configured to receive is disabled while LxACK is asserted, there is an RC delay before the 50k pulldown resistor1 on LxACK (if enabled) can pull the value below logic

LxACK has a 20k pulldown resistor for revisions 1.2 and higher.

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Designing Link Port Systems

threshold. If the appropriate request status bit is unmasked in the LSRQ register (in this instance), then an LSR is latched and the LSRQ interrupt may be serviced, even though unintended, if enabled. The program must make sure that synchronization is not disrupted by unrelated influences at critical sections where timing control loops are used to synchronize parallel code execution. Disabling of nested interrupts is one technique to control this.

Designing Link Port Systems

The ADSP-21161 processor link ports support I/O with peripherals and other processor link ports. While link ports require few connections, there are a number of design issues that systems using these ports must accommodate.

Terminations for Link Transmission Lines

The link ports are designed to allow long distance connections to be made between the driver and the receiver. This is possible because the links are self-synchronizingthe clock and data are transmitted together. Only relative delay, not absolute delay between clock and data is relevant. In addition, the LxACK signal inhibits transmission of the next word, not of the current nibble or byte. For example, the current word is always allowed to complete transmission. This allows delays of 3 to 5 cycles for the LxACK signal to reach the transmitter. The links are designed to drive transmission lines with characteristic impedances of 50 or greater. A higher transmission line impedance reduces the on-chip effect of driver impedance variations for distances longer than six inches.

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Link Ports

The ADSP-21161 processor contains internal series resistance equivalent to 50 on all I/O drivers except the CLKIN and XTAL pins. Therefore, for traces longer than six inches, external series resisters on control, link port data, clock or frame sync pins are not required to dampen reflections from transmission line effects for point-to-point connections.

Peripheral I/O Using Link Ports

The example shown in Figure 9-9 shows how a multiprocessing system can use link ports to connect to local memories and I/O devices. An ASIC implements the interface between the link port and DRAM or an I/O device. This minimal hardware solution frees the processors external bus for other shared-bus communication. The DRAM and ASIC may be implemented on a single 10-pin SIMM module. Accesses to the DRAM over a link is most efficient under DMA control. The ASIC receives DMA control information from the link port and sets up the access to the DRAM. It unpacks 16-bit data words from the DRAM or packs 8-bit bytes from the link. At the end of the DMA transfer, an interrupt lets the processor send new control information to the ASIC. The ASIC always reverts to receive mode at the end of a transfer. The LxACK signal is deasserted by the ASIC whenever a page change, memory refresh cycle, or any other access to the DRAM occurs. Memory modules may be shared by multiple DSPs when the link port is bused. Each link port supports 100 Mbyte per second access throughput for either instructions or data. The ASIC is responsible for generating the clock when transmitting to the processor. The ASIC is also responsible for generating sequential DMA addresses based on a start address and word count.

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Designing Link Port Systems

DRAM 0 20 MHZ CYCLE 16 DATA

LINK INTERFACE ASIC

ADSP-21161 L0DAT7-0 L0CLK L0ACK 10 I/O DEVICE EXTERNAL PORT LINK PORT 0 LINK PORT 1 EXTERNAL MEMORY

ADDRESS & CONTROL

CLK

LINK BUS 0

DRAM 1 20 MHZ CYCLE 16 DATA

LINK INTERFACE ASIC

LINK BUS 1

ADSP-21161

DMA DEVICE

L1DAT7-0 L1CLK L1ACK 10

EXTERNAL PORT LINK PORT 0 HOST

ADDRESS & CONTROL

LINK PORT 1

CLK

Figure 9-9. Local DRAM With Link Ports

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Link Ports

Data Flow Multiprocessing With Link Ports

Figure 9-10 shows examples of different link port communications schemes. For more information on the multiprocessor interface, see Multiprocessing System Architectures on page 7-90.

LINK PORTS ADSP-21161 EXTERNAL PORT

LINK PORTS ADSP-21161 EXTERNAL PORT

LINK PORTS ADSP-21161 EXTERNAL PORT

LINK PORTS ADSP-21161

LINK PORTS ADSP-21161

LINK PORTS ADSP-21161

DATAFLOW SHARC CLUSTER

ADSP-21161 LINK PORTS LINK PORTS ADSP-21161 EXTERNAL PORT LINK PORTS ADSP-21161 EXTERNAL PORT LINK PORTS ADSP-21161 EXTERNAL PORT LINK PORTS ADSP-21161 LINK PORTS ADSP-21161 LINK PORTS ADSP-21161 ADSP-21161 LINK PORTS ADSP-21161 LINK PORTS

EXPANDING CLUSTERS

RING TOPOLOGY

Figure 9-10. Link Port Communication Examples

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Designing Link Port Systems

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10 SERIAL PORTS

The ADSP-21161 processor has four independent, synchronous serial ports (SPORTs) that provide an I/O interface to a wide variety of peripheral devices: SPORT0, SPORT1, SPORT2 and SPORT3. Each serial port has its own set of control registers and data buffers. With a range of clock and frame synchronization options, the SPORTs allow a variety of serial communication protocols and provide a glueless hardware interface to many industry-standard data converters and CODECs. Serial ports can operate at half the full clock rate of the processor, at a maximum data rate of n/2 Mbit/s, where n equals the processor core-clock frequency. Bidirectional (transmit or receive) functions provide greater flexibility for serial communications. Serial port data can be automatically transferred to and from on-chip memory using DMA block transfers. In addition to standard synchronous serial mode, each serial port offers a Time Division Multiplexed (TDM) multichannel mode and I2S mode. Serial ports offer the following features and capabilities: Two bi-directional channels per serial port, configurable as either transmitters or receivers. Each serial port can be configured as two receivers or two transmitters, permitting two unidirectional streams into or out of the same serial port. This bi-directional functionality provides greater flexibility for serial communications. Two SPORTs can be combined to allow full-duplex, dual-stream communications.

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 Double-buffers data all serial data pins have programmable receive and transmit functions and thus have one transmit and one receive data buffer register and a bi-directional shift register associated with each serial data bin. Double-buffering provides additional time to service the SPORT. Compression/decompression A-law and -law hardware companding on transmitted and received words. Provides internally-generated serial clock and frame sync signals in a wide range of frequencies, or accepts clock and frame sync input from an external source. Performs interrupt-driven, single-word transfers to and from on-chip memory controlled by the processor core. Executes DMA transfers to and from on-chip memory. Each SPORT can automatically receive or transmit an entire block of data. Permits chaining of DMA operations for multiple data blocks. Three operation modes: standard DSP serial, I2S, and multichannel. In I2S mode, one or both channels on each SPORT can transmit or receive. Each channel either transmits or receives left and right channels. In standard DSP serial and I2S modes, when both A and B channels are used, they transmit or receive data simultaneously, sending or receiving bit 0 on the same edge of the serial clock, bit 1 on the next edge of the serial clock, and so on. In multichannel mode, SPORT0 or SPORT1 can receive A channel data, and SPORT2 or SPORT3 transmits A channel data selectively from up to 128 channels of a time-division-multiplexed serial bitstream. This mode is useful for T1 or H.100/H.110 interfaces. In multichannel mode, SPORT0 and SPORT2 work as a pair, and SPORT1 and SPORT3 work as a pair.

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Serial Ports

Can be configured to transfer data words between 3 and 32 bits in length, either MSB-first or LSB-first. Words must be between 8 and 32 bits in length for I2S mode. 128-channel TDM is supported in multichannel mode operation. Receive comparison and 2-dimensional DMA are not supported in the ADSP-21161 processor.

Serial Port Pins

Figure 10-1 shows the pin connections between serial ports. A serial port receives serial data on one of its bi-directional serial data pins configured as an input or transmits serial data on the bi-directional serial data pins configured as an output. It can receive or transmit on both channels simultaneously and uni-directionally, where the pair of data pins can both be configured as either transmitters or receivers.
SPORTS Pin List: D0a = SPORT0 channel A data (Rx or Tx) D0b = SPORT0 channel B data (Rx or Tx) SCLKx0 = SPORT0 Serial clock FS0 = SPORT0 Frame sync D1a = SPORT1 channel A data (Rx or Tx) D1b = SPORT1 channel B data (Rx or Tx) SCLKx1 = SPORT1 Serial clock FS1 = SPORT1 Frame sync D2a = SPORT2 channel A data (Rx or Tx) D2b = SPORT2 channel B data (Rx or Tx) SCLKx2 = SPORT2 Serial clock FS2 = SPORT2 Frame sync D3a = SPORT3 channel A data (Rx or Tx) D3b = SPORT3 channel B data (Rx or Tx) SCLKx3 = SPORT3 Serial clock FS3 = SPORT3 Frame sync

SPORT0 SPORT2 D0a D0b FS0 SCLK0 D1a D1b FS1 SCLK1 D2a D2b FS2 SCLK2 D3a D3b FS3 SCLK3

SPORT1 SPORT3

Figure 10-1. SPORT Pins

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Serial Port Pins

The A and B channel data pins on each SPORT cannot transmit and receive data simultaneously for full-duplex operation. Two SPORTs must be combined to achieve full-duplex operation. The DDIR bit in the SPCTL register controls the same direction for both the A and B channel pins. Therefore, the direction of the A and B channel on a particular SPORT must be the same. Serial communications are synchronized to a clock signal. Every data bit must be accompanied by a clock pulse. Each serial port can generate or receive its own clock signal (SCLKx). Internally-generated serial clock frequencies are configured in the DIVx registers. the A and B channel data pins shift data based on the rate of SCLKx. In addition to the serial clock signal, data may be signaled by a frame synchronization signal. The framing signal can occur at the beginning of an individual word or at the beginning of a block of words. The configuration of frame sync signals depends upon the type of serial device connected to the processor. Each serial port can generate or receive its own frame sync signal (FS) for transmitting or receiving data. Internally-generated frame sync frequencies are configured in the DIVx registers. Both the A and B channel data pins shift data based on the corresponding FSx pin. Figure 10-2 shows a block diagram of a serial port. The SCLKx and FSx signals are internally connected to all four A and B channel data buffers. The setting of the DDIR bit enables the data buffer path, which, once activated, responds by shifting data in response to a frame sync at the rate of SCLKx. Your application program must use the correct serial port data buffers, according to the value of DDIR bit. The DDIR bit enables the transmit data buffers for the transmission of A and B channel data, or it enables the receive data buffers for the reception of A and B channel data. Inactive data buffers are not used. The DDIR bit in the SPCTLx register affects the operation of the transmit data path or the receive data path. The data path includes the data buffers and the shift registers. When DDIR = 0, the primary and secondary RXx data registers and receive shift registers are acti-

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Serial Ports

vated, and the transmit path is disabled. When DDIR = 1, the primary and secondary TXx data register and transmit shift registers are activated, and the receive path is disabled.
DM, PM, I/O Data bus 32

32

32

32

32

TXxA Transmit Data Buffer

RXxA Receive Data Buffer

TXxB Transmit Data Buffer

RXxB Receive Data Buffer

Hardware Companding (compression) SPORTs 2 & 3 Only 32 Transmit Shift Register DDIR=1 TX Enable

Hardware Companding (expansion) SPORTs 0 and 1 Only 32 Receive Shift Register DDIR=0 RX Enable

32

32

Transmit Shift Register DDIR=1 TX Enable

Receive Shift Register DDIR=0 RX Enable

SCLKx FSx
DDIR CTL

DxA_out

DxA_in

Serial Port Control

DxB_out

DxB_in

DxA

FSx

SCLKx

DxB

Figure 10-2. Serial Port Block Diagram If the serial data pin is configured as a serial transmitter, the data to be transmitted is written to the TXxA/TXxB buffer. The data is (optionally) compressed in hardware on the primary A channel (SPORT2 and ADSP-21161 SHARC Processor Hardware Reference 10-5

Serial Port Pins

SPORT3 only), then automatically transferred to the transmit shift register. Companding is not supported on the secondary B channels, thus the data is automatically transferred from the TXxB buffer to the shift register. The data in the shift register is then shifted out on the SPORTs Dxy pin, synchronous to the SCLKx clock. If framing signals are used, the FSx signal indicates the start of the serial word transmission. The Dxy pin is always driven (for example, three-stated) if the serial port is enabled (SPEN_A or SPEN_B =1 in the SPCTLx control register), unless it is in multichannel mode and an inactive time slot occurs. When the SPORT is configured as a transmitter (DDIR=1), the TXxA and TXxB registers and the channel transmit shift registers respond to SCLKx and FSx for transmission of data. The receive RXxA and RXxB buffer registers and receive shift registers are inactive and do not respond to SCLKx and FSx signals. Since these registers are inactive, reading from an empty buffer will cause the core to hang indefinitely. Do not read from the inactive RXxA and RXxB registers (since the receive buffer status is always empty) if the SPORTs are configured as transmitters (DDIR bit = '1' in SPCTL), as this will cause a core hang indefinitely. If the serial data pin is configured as a serial receiver (DDIR=0), the receive portion of the SPORT shifts in data from the Dxy pin, synchronous to the SCLKx receive clock. If framing signals are used, the FSx signal indicates the beginning of the serial word being received. When an entire word is shifted in on the primary A channel, the data is (optionally) expanded (SPORT0 and SPORT1 only), then automatically transferred to the RXxA buffer. When an entire word is shifted in on the secondary channel, it is automatically transferred to the RXxB buffer (companding is not supported on the secondary B channels). When the SPORT is configured as a receiver (DDIR=0), the RXxA and RXxB registers, along with the corresponding A and B channel receive shift registers are activated, responding to SCLKx and FSx for reception of data. The transmit TXxA and TXxB buffer registers and transmit A and B shift registers

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Serial Ports

are inactive and do not respond to the SCLKx and FS. Since the TXxA and TXxB registers are inactive, writing to a transmit data buffer will cause the core to hang indefinitely. Do not write to the inactive TXxA and TXxB registers if the SPORTs are configured as receivers (DDIR bit = '0' in SPCTL). If the core keeps writing to the inactive buffer, the transmit buffer status will become full. Since data is never transmitted out of the deactivated transmit data buffers, this results in a core hang indefinitely. The SPORTs are not UARTs and cannot communicate with an RS-232 device or any other asynchronous communications protocol. One way to implement RS-232 compatible communications with the ADSP-21161 processor is to use two of the FLAG pins as asynchronous data receive and transmit signals. For an example, see Chapter 11 Software UART in the Digital Signal Processing Applications Using The ADSP-2100 Family, Volume 2.

SPORT Interrupts
Each serial port has a transmit DMA interrupt and a receive DMA interrupt. For each SPORT, both the A and B channel transmit or receive data buffers share the same interrupt vector. If a given SPORT is configured to transmit data, both the TXxA and TXxB data buffers use the interrupt vector when previous data has been transmitted. If the SPORT is configured to receive data, both the RXxA and RXxB data buffers use the interrupt vector when new data has been received. When serial port DMA is not enabled, interrupts occur based on the SPORT transmit or receive FIFO status. If

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SPORT Reset

on the transmit side the FIFO is empty or on the receive side the FIFO is full, interrupts is generated. The priority of the serial port interrupts is shown in Table 10-1. Table 10-1. Priority of the Serial Port Interrupts
Interrupt Name1 SP0I SP1I SP2I SP3I Interrupt SPORT0 DMA Channels 0 and 1 (Highest Priority) SPORT1 DMA Channels 2 and 3 SPORT2 DMA Channels 4 and 5 SPORT3 DMA Channels 6 and 7 (Lowest Priority)

1 The interrupt names are defined in the def21161.h file supplied with the ADSP-21xxx Development Software.

SPORT interrupts occur on the second system clock (CLKIN) after the last bit of the serial word is latched in or driven out.

SPORT Reset
There are two ways to reset the serial ports: a software reset and a hardware reset. Each method has a different effect on the serial port. A software reset of the SPEN enable bit(s) disables the serial port(s) and aborts any ongoing operations. Status bits are also cleared. The serial ports are ready to start transmitting or receiving data two SCLK cycles after they are enabled in the SPCTLx control register. No serial clocks are lost from this point on. A hardware reset (RESET) disables the whole processor including the serial ports by clearing the SPCTLx control register. Any ongoing operations are aborted.

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Serial Ports

SPORT Control Registers and Data Buffers

ADSP-21161 processor has four serial ports. Each SPORT has two data paths corresponding to the A and B Channel. These data buffers are TXxA and RXxA (primary) and TXxB and RXxB (secondary). Channel A and B in all four SPORTS operate in parallel, for example, they share clock and control signals. Companding is supported only on primary channels. For more information, see Serial Port Registers on page A-100. The following is the list of registers that each SPORT has (where x = 0, 1, 2, or 3): Four 32-bit, 2-deep data buffers (TXxA/RXxA and TXxB/RXxB) One 32-bit clock and frame sync divide register (DIVx) One 32-bit control register (SPCTLx) Four 32-bit multichannel select receive registers (MR1CSx, MR0CSx) Four 32-bit multichannel select transmit registers (MT2CSx, MT3CSx) Four 32-bit multichannel receive compand select signals (MR1CCSx, MR0CCSx) Four 32-bit multichannel transmit compand select signals (MT2CCSx, MT3CCSx) One multichannel control register (SPxyMCTL) The registers used to control and configure the serial ports are part of the IOP register set. Each SPORT has its own set of 32-bit control registers and data buffers. The SPORT control registers are programmed by writing to the appropriate address in memory. The symbolic names of the registers and individual control bits can be used in processor programs. The definitions for these

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SPORT Control Registers and Data Buffers

symbols are contained in the file def21161.h located in the INCLUDE directory of the ADSP-21xxx Development Software. The def21161.h file is shown in the registers appendix section Register and Bit #Defines (def21161.h) on page A-121. All control and status bits in the SPORT registers are active high unless otherwise noted. Since the SPORT registers are memory-mapped, they cannot be written with data directly from memory. Instead, they must be written from (or read into) core registers, usually one of the general-purpose universal registers of the(R15-R0) register file. The SPORT control registers can also be written or read by external devices (for example, another processor or a host processor) to set up a serial port DMA operation. Table 10-2 provides a complete list of the SPORT registers, showing the memory-mapped IOP address and a brief description of each register. Table 10-2. SPORT Registers
Register SPCTL0 TX0A TX0B RX0A RX0B DIV0 CNT0 MR0CS0 MR0CCS0 MR0CS1 IOP Address 0x1C0 0x1C1 0x1C2 0x1C3 0x1C4 0x1C5 0x1C6 0x1C7 0x1C8 0x1C9 Reset 0x0000 0000 None None None None None None None None None Description SPORT0 serial control register SPORT0 transmit data buffer; A channel data SPORT0 transmit data buffer; B channel data SPORT0 receive data buffer; A channel data SPORT0 receive data buffer; B channel data SPORT0 divisor for transmit/receive SCLKx0 and FS0 SPORT0 count register SPORT0 multichannel receive select 0 (Channels 31-0) SPORT0 multichannel receive compand select 0 (Channel 31-0) SPORT0 multichannel receive select 1 (Channels 63-32)

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Serial Ports

Table 10-2. SPORT Registers (Contd)

Register MR0CCS1 MR0CS2 MR0CCS2 MR0CS3 MR0CCS3 IOP Address 0x1CA 0x1CB 0x1CC 0x1CD 0x1CE 0x1CF SPCTL2 TX2A TX2B RX2A RX2B DIV2 CNT2 MT2CS0 MT2CCS0 MT2CS1 MT2CCS1 0x1D0 0x1D1 0x1D2 0x1D3 0x1D4 0x1D5 0x1D6 0x1D7 0x1D8 0x1D9 0x1DA 0x0000 0000 None None None None None None None None None None Reset None None None None None Description SPORT0 multichannel receive compand select 1 (Channel 63-32) SPORT0 multichannel receive select 2 (Channels 95-64) SPORT0 multichannel receive compand select 2 (Channel 95-64) SPORT0 multichannel receive select 3 (Channels 127-96) SPORT0 multichannel receive compand select 3 (Channel 127-96) Reserved SPORT2 serial control register SPORT2 transmit data buffer; A channel data SPORT2 transmit data buffer; B channel data SPORT2 receive data buffer; A channel data SPORT2 receive data buffer; B channel data SPORT2 divisor for transmit/receive SCLKx1 and FS1 SPORT2 Count Register SPORT2 multichannel transmit select 0 (Channels 31-0) SPORT2 multichannel transmit compand select 0 (Channel 31-0) SPORT2 multichannel transmit select 1 (Channels 63-32) SPORT2 multichannel transmit compand select 1 (Channel 63-32)

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SPORT Control Registers and Data Buffers

Table 10-2. SPORT Registers (Contd)

Register MT2CS2 MT2CCS2 MT2CS3 MT2CCS3 SP02MCTL SPCTL1 TX1A TX1B RX1A RX1B DIV1 CNT1 MR1CS0 MR1CCS0 MR1CS1 MR1CCS1 MR1CS2 IOP Address 0x1DB 0x1DC 0x1DD 0x1DE 0x1DF 0x1E0 0x1E1 0x1E2 0x1E3 0x1E4 0x1E5 0x1E6 0x1E7 0x1E8 0x1E9 0x1EA 0x1EB Reset None None None None None 0x0000 0000 None None None None None None None None None None None Description SPORT2 multichannel transmit select 2 (Channels 95-64) SPORT2 multichannel transmit compand select 2 (Channel 95-64) SPORT2 multichannel transmit select 3 (Channels 127-96) SPORT2 multichannel transmit compand select 3 (Channel 127-96) SPORTs 0/2 multichannel control register SPORT1 serial control register SPORT1 transmit data buffer; A channel data SPORT1 transmit data buffer; B channel data SPORT1 receive data buffer; A channel data SPORT1 receive data buffer; B channel data SPORT1 divisor for transmit/receive SCLKx0 and FS0 SPORT1 Count Register SPORT1 multichannel receive select 0 (Channels 31-0) SPORT1 multichannel receive compand select 0 (Channel 31-0) SPORT1 multichannel receive select 1 (Channels 63-32) SPORT1 multichannel receive compand select 1 (Channel 63-32) SPORT1 multichannel receive select 2 (Channels 95-64)

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Serial Ports

Table 10-2. SPORT Registers (Contd)

Register MR1CCS2 MR1CS3 MR1CCS3 IOP Address 0x1EC 0x1ED 0x1EE 0x1EF SPCTL3 TX3A TX3B RX3A RX3B DIV3 CNT3 MT3CS0 MT3CCS0 MT3CS1 MT3CCS1 MT3CS2 MT3CCS2 0x1F0 0x1F1 0x1F2 0x1F3 0x1F4 0x1F5 0x1F6 0x1F7 0x1F8 0x1F9 0x1FA 0x1FB 0x1FC 0x0000 0000 None None None None None None None None None None None None Reset None None None Description SPORT1 multichannel receive compand select 2 (Channel 95-64) SPORT1multichannel receive select 3 (Channels 127-96) SPORT1 multichannel receive compand select 3 (Channel 127-96) Reserved SPORT3 serial control register SPORT3 transmit data buffer; A channel data SPORT3 transmit data buffer; B channel data SPORT3 receive data buffer; A channel data SPORT3 receive data buffer; B channel data SPORT3 divisor for transmit/receive SCLKx1 and FS1 SPORT3 count register SPORT3 multichannel transmit select 0 (Channels 31-0) SPORT3 multichannel transmit compand select 0 (Channel 31-0) SPORT3 multichannel transmit select 1 (Channels 63-32) SPORT3 multichannel transmit compand select 1 (Channel 63-32) SPORT3 multichannel transmit select 2 (Channels 95-64) SPORT3 multichannel transmit compand select 2 (Channel 95-64)

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SPORT Control Registers and Data Buffers

Table 10-2. SPORT Registers (Contd)

Register MT3CS3 MT3CCS3 SP13MCTL IOP Address 0x1FD 0x1FE 0x1FF Reset None None None Description SPORT3 multichannel transmit select 3 (Channels 127-96) SPORT3 multichannel transmit compand select 3 (Channel 127-96) SPORTs 1/3 multichannel control register

Serial Port Control Registers (SPCTLx)

The main control register for each serial port is the serial port control register, SPCTLx. These registers are defined in Figure 10-3 through Figure 10-7. When changing operating modes, a serial port control register should be cleared before the new mode is written to the register. The Transmit Underflow Status bit (TUVF_A/DERR_A and TUVF_B/DERR_B) is set when the FSx signal occurs from either an external or internal source while the TXxA or TXxB buffer is empty. The internally generated FS may be suppressed whenever TXxA or TXxB is empty by clearing the DITFS control bit. When DITFS is cleared (the default setting) the frame sync signal (FSx) is dependent upon new data being present in the transmit buffer. The FSx signal is only generated for new data. Setting DITFS to 1 selects data-independent frame syncs which causes the FSx signal to be generated whether or not new data is present. With each FSx signal, the SPORT will transmit the contents of the transmit buffer. Serial port DMA typically keeps the transmit buffer full. When the DMA operation is complete the last bit in the transmit buffer is continuously transmitted. The DXS_A or DXS_B status bits indicate whether the DXA or DXB buffer is full (11), empty (00), or partially full (10). To test for space in DXA/DXB, test whether DXS_A (bit 30) is equal to zero for the A channel, or whether

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Serial Ports

(bit 27) is equal to zero for the B channel. To test for the presence of any data in DXA/DXB, test whether DXS_A (bit 31) is equal to one for the A channel, or whether DXS_B (bit 28) is equal to one for the B channel.
DXS_B

There is one global control and status register for each paired SPORT (SPORT0 and SPORT2, SPORT1 and SPORT3) for multichannel operation, SP02MCTL and SP13MCTL, to define the number of channels, provide status of the current channel, enable multichannel operation, and set the multichannel frame delay. Since ADSP-21161 processor supports 128 TDM operations, the number of bits is increased to seven and are stored in a separate register, SP02MCTL or SP13MCTL. The SPxyMCTL register is shown in Figure A-35 on page A-111. The SPCTLx registers control the serial ports operating modes for the I/O processor. Table 10-3 lists all the bits in SPCTLx. Table 10-3. SPCTLx Control Bits Comparison in Three SPORT Modes of Operation
Bit I2S Mode Standard DSP Serial Mode Multichannel Mode Receive Control Bits (SPORT0 and SPORT1) Reserved DTYPE DTYPE SENDN SLEN0 SLEN1 SLEN2 SLEN3 SLEN4 PACK Multichannel Mode Transmit Control Bits (SPORT2 and SPORT3) Reserved DTYPE DTYPE SENDN SLEN0 SLEN1 SLEN2 SLEN3 SLEN4 PACK

0 1 2 3 4 5 6 7 8 9

SPEN_A Reserved Reserved Reserved SLEN0 SLEN1 SLEN2 SLEN3 SLEN4 PACK

SPEN_A DTYPE DTYPE SENDN SLEN0 SLEN1 SLEN2 SLEN3 SLEN4 PACK

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SPORT Control Registers and Data Buffers

Table 10-3. SPCTLx Control Bits Comparison in Three SPORT Modes of Operation (Contd)
Bit I2S Mode Standard DSP Serial Mode Multichannel Mode Receive Control Bits (SPORT0 and SPORT1) ICLK OPMODE CKRE Reserved IRFS Reserved LRFS Reserved SDEN_A SCHEN_A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ROVF_A RXS_A RXS_A Multichannel Mode Transmit Control Bits (SPORT2 and SPORT3) Reserved OPMODE CKRE Reserved Reserved Reserved LTDV Reserved SDEN_A SCHEN_A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TUVF_A TXS_A TXS_A

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

MSTR OPMODE Reserved Reserved Reserved DITFS L_FIRST Reserved SDEN_A SCHEN_A SDEN_B SCHEN_B FS_BOTH Reserved SPEN_B DDIR DERR_B DXS_B DXS_B DERR_A DXS_A DXS_A

ICLK OPMODE CKRE FSR IFS DITFS LFS LAFS SDEN_A SCHEN_A SDEN_B SCHEN_B FS_BOTH Reserved SPEN_B DDIR DERR_B DXS_B DXS_B DERR_A DXS_A DXS_A

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SPCTL0 (0x01c0) SPCTL1 (0x01e0) SPCTL2 (0x01d0) SPCTL3 (0x01f0)

DXS_A
DXA Data Buffer Status 11=full, 10=partially full, 00=empty

DSP Serial Mode

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LFS

Active Low FS 0=active high, 1=active low

LAFS
Late FS 0=early FS, 1=late FS

DERR_A
DXA Error Status (sticky) DDIR=1,transmit underflow status DDIR=0, receive overflow status

SDEN_A
SPORT DMA enable A channel 1=enable, 0=disable

DXS_B*
DXB Data Buffer Status 11=full, 10=partially full ,00=empty

SCHEN_A
DMA chaining enable A channel 1=enable, 0=disable

DERR_B*
DXB Error Status (sticky)

SDEN_B
SPORT DMA enable B channel 1=enable, 0=disable

DDIR**
Data Direction Control 1=Active Transmit Buffers TXnB/TXnA 0=Enable Receive Buffers RXnB/RXnA

SCHEN_B
DMA chaining enable B channel 1=enable, 0=disable

SPEN_B
SPORT Enable B 1=enable, 0=disable * Status is read-only ** Do not read/write from/to inactive RXn/TXn buffers 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

FS_BOTH
1=issue WS only if data is present in both Tx 0=issue WS if data is present in either Tx

DITFS
Data Independent tx FS (if DDIR=1) 1=data independent, 0= data dependent

SPEN_A
SPORT Enable A (1=enable, 0=disable)

IFS
Internally generated FS 1=internal FS, 0=external FS

DTYPE
Data type 00=right-justify; fill MSB with 0s 01=right-justify; sign extend MSB 10=compand mu-law 11=compand A-law

FSR
FS requirement 1=FS required, 0=FS not required

SENDN
Endian word format 0=MSB first, 1=LSB first

CKRE
Clock edge for data Frame Sync sampling or driving (1=rising edge, 0=falling edge)

SLEN
Serial Word Length-1

OPMODE
SPORT Operation Mode 0=DSP serial mode/multichannel mode 1=I2S mode

PACK
16/32 packing 1=packing, 0=no packing

ICLK

Internally generated SCLK 1=internal clock, 0=external clock

Figure 10-3. SPCTL Register DSP Serial Mode

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SPORT Control Registers and Data Buffers

SPCTL0 SPCTL1 SPCTL2 SPCTL3

(0x01c0) (0x01e0) (0x01d0) (0x01f0)

DXS_A

I 2S Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DXA Data Buffer Status 11=full, 10=partially full, 00=empty

L_FIRST

Left or Right I2S channel RX/TX first 1=start left data first 0= start right data first

DERR_A
DXA Error Status (sticky) DDIR=1,transmit underflow status DDIR=0, receive overflow status

SDEN_A
SPORT Transmit DMA enable A ch. 1=enable, 0=disable

DXS_B*
DXB Data Buffer Status 11=full, 10=partially full, 00=empty

SCHEN_A

DMA chaining enable A channel 1=enable, 0=disable

DERR_B*
DXB Error Status (sticky)

SDEN_B
SPORT transmit DMA enable Bch . 1=enable, 0=disable

D DIR**
Data Direction Control 1=Active Transmit Buffers TXnA/TXnB 0=Enable Receive Buffers RXnA/RXnB

SCHEN_B
DMA Chaining enable B channel 1=enable, 0=disable

SPEN_B
SPORT Enable B 1=enable, 0=disable * Status is read-only ** Do not read/write from/to inactive RXn/TXn buffers 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 4 0 3 2 1 0 0 0

FS_BOTH
1=issue WS only if data is present in both Tx 0= issue WS if data is present in either Tx

0 0

DITFS
Data Independent tx FS (if DDIR=1) 1=data independent, 0=data dependent

SPEN_A
SPORT Enable A (1=enable, 0=disable)

OPMODE
SPORT Operation Mode 0=DSP serial mode/multichannel mode 1=I 2 S mode

SLEN
Serial Word Length- 1

PACK
16/32 packing 1=packing, 0=no packing

MSTR
I2S serial and L/R clock Master 1=internal SCLK and WS, TX/RX is master 0=external SLCK and WS, TX/RX is slave

(Reserved bits must be cleared for I 2 S operation)

Figure 10-4. SPCTLx Register I2S Mode

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Multichannel Mode
Receive Control Bits
31 30 29 28 27 26 0 0 25 24 23 22 21 20 0 0 0 0 0 0 19 18 17 0 0 0 16 0

SPCTL0 (0x01C0) SPCTL1 (0x01E0)

LRFS RXS_A*
RXA Data Buffer Status 11=full, 10=partially full, 00=em pty Active Low Multichannel Receive FS0/FS1 0=active high, 1=active low

SDEN_A
SPO RT receive DMA enable A 1=enable, 0=disable

R OVF_A*
RXA Underflow Status (sticky)

SCHEN_A
SPO RT receive DMA chaining enable A 1=enable, 0=disable

*Status is read-only

15 14 13 0 0 0

12 0

11 10 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

IRFS
Internally G enerated Multichannel rx FS 1=internal FS0/FS1, 0=external FS0/FS1

DTYPE

CKR E
Active clock edge for data & frame sync sampling (1=rising edge, 0=falling edge)

Data type 00=right-justify; fill MSB with 0s 01=right-justify; sign extend M SB 10=compand mu-law 11=compand A-law

SENDN
Endian word form at 0=MSB first, 1=LSB first

O PMOD E
SPORT Operation Mode 0=DSP serial mode/multichannel mode 1= I 2 S mode

SLEN
Serial W ord Length -1

ICLK
Internally -generated Receive clock 1=internal clock, 0=external clock

PACK
16/32 packing 1=packing, 0=no packing

(Reserved bits must be cleared for multichannel operation)

Figure 10-5. SPCTL Receive Control Bits in Multichannel Mode for SPORT0 and SPORT1

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SPORT Control Registers and Data Buffers

Multichannel Mode
Transmit Control Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0

SPCTL2 (0x01d0) SPCTL3 (0x01f0)

LTDV TXS_A*
TXA Data Buffer Status 11=full, 10=partially full, 00=empty Active Low MC Transmit Data Valid 0=active high TVD2/TDV3 1=active low TDV2/TDV3

SDEN_A
SPORT transmit DMA enable A 1=enable, 0=disable

TUVF_A*
TXA Underflow Status (sticky)

SCHEN_A
SPORT transmit DMA chaining enable A 1=enable, 0=disable 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

Reserved** OPMODE
SPORT Operation Mode 0=DSP serial mode/multichannel mode 1=I 2S mode

Data type x0=right-justify; fill MSB with 0s x1=right-justify; sign extend MSB 0x=compand mu-law 1x=compand A-law

DTYPE

PACK
16/32 packing 1=packing, 0=no packing

SENDN
Endian word format 0=MSB first, 1=LSB first

SLEN
Serial Word Length -1

(Reserved bits must be cleared for multichannel operation)

*Status is read-only **The CKRE values for SPCTL2 and SPCTL3 come from SPCTL0 and SPCTL1 (respectively) in multichannel mode.

Figure 10-6. SPCTL Transmit Control Bits in Multichannel Mode for SPORT2 and SPORT3

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SP02MCTL (0x01DF) SP13MCTL (0x01FF)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CHNL
Current Channel (read-only) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 0 6 5 4 0 3 2 1 0 0 0

0 0

0 0

SPL
SPORTLoopback SPORT0 & SPORT2 only SPORT1 & SPORT3 only

MCE
Multichannel enable (1=enable, 0=disable)

MFD
Multichannel Frame Delay

NCH
Number of Channels - 1

Figure 10-7. SPxyMCTL Control Bits for Multichannel Mode The following bits control serial port modes and are part of the SPCTLx control registers. Other bits in the SPCTLx registers set up DMA and I/O processor related serial port features. Current Channel Selected. SP02MCTL or SP13MCTL Bits 16-22 (CHNL). These read-only, sticky status bits identify the currently selected transmit channel slot (0 to 127). These bits apply to multichannel mode only. Clock Rising Edge Select. SPCTLx Bit 12 (CKRE).This bit selects whether the serial port uses the rising edge (if set, =1) or falling edge (if cleared, =0) of the clock signal for sampling data and the frame sync. This bit applies to DSP standard serial and multichannel modes only.

ADSP-21161 SHARC Processor Hardware Reference

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SPORT Control Registers and Data Buffers

Data Direction Control. SPCTLx Bit 25 (DDIR). This bit controls the data direction of the serial port channel A and B pins. 0 = SPORT is configured to receive on both channels A and B 1 = SPORT is configured to transmit on both channels A and B When configured to receive, the RXxA and RXxB buffers are activated, while the receive shift registers are controlled by SCLKx and FS. The TXxA and TXxB buffers are inactive. When configured to transmit, the TXxA and TXxB buffers are activated, while the transmit shift registers are controlled by SCLKx and FSx. The RXxA and RXxB buffers are inactive. This bit applies to all registers for I2S and DSP standard serial modes. Reading from or writing to inactive buffers will cause a core hang indefinitely until the SPORT is cleared. A hardware reset or host reset will clear the SPORT. Data Independent Transmit Frame Sync Select. SPCTLx Bit 15 (DITFS).This bit selects whether the serial port uses a data-independent transmit frame sync (sync at selected interval, if set to 1) or a data-dependent TFS (sync when data is in the transmit buffer, if cleared to 0) when DDIR=1. When DITFS =0, a transmit FSx signal is generated only when new data is in the SPORT channels transmit data buffer. Applications must also program the DIVx register. When DITFS = 1, a transmit FSx signal is generated, regardless of the validity of the data present in the SPORT channels transmit data buffer. The processor generates the transmit FSx signal at the frequency specified by the value loaded in the DIV register. This bit applies to all SPCTLx registers in I2S and DSP standard serial modes, and SPCTL2 and SPCTL3 register transmit control for multichannel mode. 10-22 ADSP-21161 SHARC Processor Hardware Reference

Serial Ports

DXS Data Buffer Status. SPCTLx Bits 30 and 31(DXS_A) and Bits 27 and 28 (DXS_B). These read-only, sticky bits indicate the status of the serial ports data buffer as follows: 11= buffer full, 00= buffer empty, 10=buffer partially full, 01= reserved. These bits apply to I2S and DSP standard serial modes. When the SPORT is configured as a transmitter, these bits reflect transmit buffer status for the TXxA and TXxB registers. When the SPORT is configured as a receiver, these bits reflect receive buffer status for the RXxA and RXxB registers. Data Buffer Error Status (sticky, read-only). SPCTLx Bit 29 and 26 (DERR).These bits indicate whether the serial transmit operation has underflowed (if set, =1 and DDIR=1) or a receive operation has overflowed (if cleared, =0 and DDIR=0) in the DXA and DXB data buffers. These bits apply to I2S and DSP standard serial modes. When the SPORT is configured as a transmitter, this bit provides transmit underflow status and indicates whether the FSx signal (from internal or external source) occurred while the DXS buffer was empty. The SPORTs transmit data whenever they detect a FSx signal. 0 = No FS signal occurred. 1=
FS

signal occurred.

When the SPORT is configured as a receiver, these bits provide receive overflow status. As a receiver, it indicates when the channel has received new data while the RXS_A buffer is full. New data overwrites existing data. 0 = No new data. 1 = New data.

ADSP-21161 SHARC Processor Hardware Reference

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SPORT Control Registers and Data Buffers

Data Type Select. SPCTLx Bits 2-1 (DTYPE).These bits select the companding and MSB data type formatting of serial words loaded into the transmit and receive buffers. The transmit shift register does not zero fill or sign-extend transmit data words. This bit applies to DSP standard serial and multichannel modes only. For standard mode, selection of companding mode and MSB format are exclusive: 00 = Right justify; fill unused MSBs with 0s. 01 = Right justify; sign-extend into unused MSBs. 10 = Compand using _law. (Primary channels only) 11 = Compand using A_law. (Primary channels only) For multichannel mode, selection of companding mode and MSB format are independent: x0 = Right justify; fill unused MSBs with 0s. x1 = Right justify; sign-extend into unused MSBs. 0x = Compand using _law. 1x = Compand using A_law. Frame Sync Both Enable. SPCTLx Bit 22 (FS_BOTH). This bit applies when the SPORTS channels A and B are configured to transmit data. If set (=1), this bit issues word select only when data is present in both transmit buffers, TX0A and TX0B. If cleared (=0), a word select is issued if data is present in either transmit buffers. This bit applies to I2S and DSP standard serial modes only. Internal Transmit Clock Select. SPCTLx Bit 10 (ICLK). This bit selects the internal (if set, =1) or external (if cleared, =0) transmit or receive clock. This bit applies to DSP standard serial and multi-

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Serial Ports

channel modes for SPCTL0 and SPCTL1 registers. In these modes only, set this parameter separately for all four SPORTs, where each SPCTL register contains an ICLK bit. Receive Multichannel Frame Sync Source. SPCTL0 and SPCTL1 Bit 14 (IRFS).This bit selects whether the serial port uses an internal clock generated frame sync (if set, =1) or an external (if cleared, =0) source. This bit applies to multichannel mode only. Internal Frame Sync Select. SPCTLx Bit 14 (IFS).This bit selects whether the serial port uses an internal clock generated frame sync (if set, =1) or an external (if cleared, =0) source. This bit applies to DSP standard serial mode only. Late Transmit Frame Sync Select. SPCTLx Bit 17 (LAFS). This bit selects when to generate the frame sync signal. This bit selects a late frame sync if set (=1) during the first bit of each data word. This bit selects an early frame sync if cleared (=0) during the serial clock cycle immediately preceding the first data bit. This bit applies to DSP standard serial mode only. Left/Right Channel Transmit or Receive First. SPCTLx Bit 16 (L_FIRST).This bit selects the left channel first (if set, =1) or right channel first (if cleared, =0) for transmit or receive. This bit applies to I2S mode only. Low Active Frame Sync Select. SPCTLx Bit 16 (LFS).This bit selects the logic level of the (transmit or receive) frame sync signals. Active high (0) is the default. This bit selects an active low frame sync (if set, =1) or active high frame sync (if cleared, =0). This bit applies to DSP standard serial mode only. Active State Multichannel Receive Frame Sync Select.SPCTL0 and SPCTL1 Bit 16 ( LRFS).This bit selects the logic level of the multichannel received frame sync signals as active low (inverted) if set (=1) or active high if cleared (=0). Active high (0) is the default. This bit applies to multichannel modes only. ADSP-21161 SHARC Processor Hardware Reference 10-25

SPORT Control Registers and Data Buffers

Active State Transmit Data Valid. SPCTL2 and SPCTL3 Bit 16 (LTDV).This bit selects the logic level of the transmit data valid signals (TDV2, TDV3) pins as active low (inverted) if set (=1) or active high if cleared (=0). These pins are actually FS2 and FS3 reconfigured as outputs during multichannel operation, indicating which timeslots have valid data to transmit. Active high (0) is the default. This bit applies to multichannel mode only.

Multichannel Mode Enable. SP02MCTL and SP13MCTL Bit 0 (MCE). Standard and multichannel modes only. in the registers. One of two configuration bits that enable and disable multichannel mode on both the receive or transmit serial port channels. If MCE is cleared (=0), then multichannel operation is disabled. If MCE is set (=1) and OPMODE is cleared (=0), then multichannel operation is enabled. This bit applies to DSP standard serial and multichannel modes only. Multichannel Frame Delay. SP02MCTL and SP13MCTL Bit 1-4 (MFD).These bits set the interval, in terms of serial clock cycles, between the multichannel frame sync pulse and the first data bit. These bits provide support for different types of T1 interface devices. Valid values range from 0 to 15. Values of 1 to 15 correspond to the number of intervening serial clock cycles. A value of 0 corresponds to no delay. The multichannel frame sync pulse is concurrent with first data bit. This bit applies multichannel mode only. SPORT Transmit or Receive Master Mode. SPCTLx Bit 10 (MSTR). This bit selects the clock and word-select source for transmitting or for receiving. If set (=1), the SPORT uses the internal clock, and the word-select source transmitter or receiver is the master. If cleared (=0), the SPORT transmitter or receiver is a slave. This bit applies to I2S mode only.

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Number of Multichannel Slots (minus one). SP02MCTL and SP13MCTL Bit 5 -11 (NCH).These bits select the number of channel slots (maximum of 128) to use for multichannel operation. Valid values for actual number of channel slots range from 1 to 128. This bit applies to multichannel mode only. Use the following formula to calculate the value for NCH: NCH = Actual number of channel slots -1. SPORT Operation Mode. SPCTLx Bit 11 (OPMODE). This bit enables if set (=1) or disables if cleared (=0) the I2S mode. When this bit is set, the processor ignores the MCE bit. When this bit is cleared, the MCE bit determines whether the SPORT is in DSP serial mode (MCE=0) or multichannel mode (MCE=1). 16-bit to 32-bit Word Packing Enable. SPCTLx Bit 9 (PACK).This bit enables (if set, =1) or disables (if cleared, =0) 16- to 32-bit word packing. This bit applies to all operation modes. Frame Sync Required Select. SPCTLx Bits 13 (FSR).This bit selects whether the serial port requires (if set, =1) or does not require (if cleared, =0) a transfer frame sync. Only a single frame sync signal is required to initiate communications. The frame sync is ignored after the first bit received. This bit applies to DSP standard serial mode only. Receive Overflow Status (read-only, sticky). SPCTL0 and SPCTL1 Bit 29 (ROVF). These bits indicate when the channel has received new data if set (=1) or not if cleared (=0) while the RXS_A buffer is full. New data overwrites existing data. This bit applies to multichannel mode only. Receive Data Buffer Status Channel A (read-only). SPCTL0 and SPCTL1 Bits 30 and 31 (RXS_A). These bits indicate the status of the channel's receive buffer contents as follows: 00 = buffer empty, 01 = reserved, 10 = buffer partially full, 11 = buffer full. These bits apply to multichannel mode only.

ADSP-21161 SHARC Processor Hardware Reference

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SPORT Control Registers and Data Buffers

Serial Port DMA Chaining Enable. SPCTLx Bits 19 and 21 (SCHEN_A and SCHEN_B).These bits enable (if set, =1) or disable (if cleared, =0) serial ports channels A and B DMA chaining. Bit 21 applies to I2S and DSP standard serial modes only for secondary (B) SPORT channels. Serial Port DMA Enable. SPCTLx Bits 18 and 20 (SDEN_A and SDEN_B).These bits enable (if set, =1) or disable (if cleared, =0) the serial ports channel DMA. Bit 20 applies to I2S and DSP standard serial modes only for secondary (B) SPORT channels. Serial Word Endian Select. SPCTLx Bit 3 (SENDN).This bit selects little endian words (LSB first, if set, =1) or big endian words (MSB first, if cleared, =0). This bit applies to DSP standard serial and multichannel modes only. Serial Word Length Select. SPCTLx Bit 4-8 (SLEN).These bits select the word length in bits. Word sizes can be from 3-bit (SLEN=2) to 32-bit (SLEN=31). These bits apply to all operation modes. Use the following formula to calculate the value for SLEN: SLEN = Actual serial word length 1
SLEN

cannot equal 0 or 1.

Serial Port Enable. SPCTLx Bits 0 and 24 (SPEN_A and SPEN_B).This bit enables (if set, =1) or disables (if cleared, =0) the corresponding serial port channel A or B. Clearing this bit aborts any ongoing operation and clears the status bits. The SPORTS are ready to transmit or receive two cycles after enabling. This bit apply to I2S and DSP standard serial modes only.

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Serial Ports

SPORT Loopback Mode. SP02MCTL or SP13MCTL Bit 12 (SPL). This bit enables, if set (=1), or disables, if cleared (=0), the channel loopback mode. Loopback mode enables you to run internal tests and to debug applications. Loopback works only under the following SPORT configurations: SPORT0 (configured as a receiver or transmitter) together with SPORT2 (configured as a transmitter or receiver). SPORT0 can only be paired with SPORT2, and controlled via the SPL bit in the SP02MCTL register. SPORT1 (configured as a receiver or transmitter) together with SPORT3 (configured as a transmitter or receiver). SPORT1 can only be paired with SPORT3, and controlled via the SPL bit in the SP13MCTL register. Either of the two paired SPORTs can be set up to transmit or receive, depending on their DDIR bit configurations. This bit applies to DSP standard serial and I2S modes only. Transmit Underflow Status (sticky, read-only). SPCTL2 and SPCTL3 Bit 29 ( TUVF_A).This bit indicates (if set, =1) whether the multichannel FSx signal (from internal or external source) occurred while the TXS buffer was empty. The SPORTs transmit data whenever they detect an FSx signal. If cleared (=0), No FSx signal occurred. This bit applies to multichannel mode only when the SPORTs are configures as transmitters. Transmit Data Buffer Status (sticky, read-only). SPCTL2 and SPCTL3 Bits 30 and 31(TXS_A). These bits indicate the status of the serial port channels transmit buffer as follows: 11=buffer full, 00=buffer empty, 10=buffer partially full. These bits apply to multichannel mode only.

ADSP-21161 SHARC Processor Hardware Reference

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SPORT Control Registers and Data Buffers

Register Writes and Effect Latency SPORT register writes are internally completed at the end of the same CLKIN cycle in which they occur. The newly written value to the SPORT register can be read back on the very next cycle. When a read of one of the SPCTLx control registers is immediately followed by a write to that register, the write may take two cycles to complete. After a write to a SPORT register, control and mode bit changes generally take effect in the second CLKIN cycle after the write is completed. The serial ports are ready to start transmitting or receiving two CLKIN cycles after they are enabled (in the SPCTLx control register). No serial clocks are lost from this point on.

Transmit and Receive Data Buffers

The transmit registers (TX0A, TX0B, TX1A, TX1B, TX2A, TX2B, TX3A, and TX3B) are the 32-bit transmit data buffers for SPORT0, SPORT1, SPORT2, and SPORT3, respectively. These buffers must be loaded with the data to be transmitted if the SPORT is configured to transmit on the A and B channels. The data is loaded automatically by the DMA controller or loaded manually by the program running on the processor core. The receive registers (RX0A, RX0B, RX1A, RX1B, RX2A, RX2B, RX3A, and RX3B) are the receive data buffers for SPORT0, SPORT1, SPORT2, and SPORT3 respectively. These 32-bit buffers become active when the SPORT is configured to receive data on the A and B channels. When a SPORT is configured as a receiver, the RXxA and RXxB registers are automatically loaded from the receive shifter when a complete word has been received. The data is then loaded to internal memory by the DMA controller or read directly by the program running on the processor core. Word lengths of less than 32 bits are automatically right-justified in the receive and transmit buffers.

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The transmit buffers act like a two-location FIFO because they have a data register plus an output shift register as shown in Figure 10-2 on page 10-5. Two 32-bit words may be stored in the transmit queue at any one time. When the transmit register is loaded and any previous word has been transmitted, the register contents are automatically loaded into the output shifter. An interrupt occurs when the output transmit shifter has been loaded, signifying that the transmit buffer is ready to accept the next word (for example, the transmit buffer is not full). This interrupt does not occur when serial port DMA is enabled or when the corresponding mask bit in the IMASK register is cleared. In I2S and DSP Standard serial port modes, the DERR_A and DERR_B overflow/underflow status bits are set when an overflow or underflow occurs. In multichannel mode, the DERR_A bits are redefined due to the fixed-directional functionality of the SPCTLx registers. When the SPCTL0 and SPCTL1 registers are configured for multichannel mode, the receive overflow bit ROVF_A indicates when the A channel has received new data while the RXS_A buffer is full. Similarly, when the SPCTL2 and SPCTL3 registers are configured for multichannel mode, the transmit overflow bit TUVF_A indicates that a new frame sync signal (FS0/FS1) occurred while the TXS_A buffer was empty. The DERR_A (Bit 29) overflow/underflow status bit in the SPCTLx register becomes fixed in multichannel mode only as either the RUVF_A overflow status bit (SPORTs 0 and 1) or TUVF_A underflow status bit (SPORTs 2 and 3). When the SPORT is configured as a transmitter (DDIR =1), a transmit underflow status bit is set in the serial port control register when a transmit frame sync occurs and no new data has been loaded into the transmit buffer. The TUVF_A/DERR_A status bit is sticky and is only cleared by disabling the serial port. When the SPORT is configured as a receiver (DDIR =0), the receive buffers are activated. The receive buffers act like a three-location FIFO because they have two data registers plus an input shift register. Two complete

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SPORT Control Registers and Data Buffers

32-bit words can be stored in the receive buffer while a third word is being shifted in. The third word overwrites the second if the first word has not been read out (by the processor core or the DMA controller). When this happens, the receive overflow status bit is set in the serial port control register. Almost three complete words can be received without the receive buffer being read before overflow occurs. The overflow status is generated on the last bit of the third word. The ROVF_A/DERR_A status bit is sticky and is cleared only by disabling the serial port. An interrupt is generated when the receive buffer has been loaded with a received word (for example, the receive buffer is not empty). When the corresponding bit in the IMASK register is set, this interrupt is unmasked. If your program causes the core processor to attempt to read from an empty receive buffer or a write to a full transmit buffer, the access is delayed until the buffer is accessed by the external I/O device. This delay is called a core processor hang. If you do not know whether the core processor can access the receive or transmit buffer without a hang, the buffer's status should be read first (in SPCTLx) to determine if the access can be made. To support debugging buffer transfers, the ADSP-21161 processor has a Buffer Hang Disable (BHD) bit. When set (=1), this bit prevents the processor core from detecting a buffer-related stall condition, permitting debugging of this type of stall condition. For more information, see the BHD discussion on on page 6-43. The status bits in SPCTLx are updated during reads and writes from the core processor even when the serial port is disabled. Disable the serial port when writing to the receive buffer or reading from the transmit buffer. When programming the serial port channel (A or B) as a transmitter, only the corresponding TXxA and TXxB buffers become active while the receive buffers RXxA and RXxB remain inactive. Similarly, when the SPORT channel A and B is programmed as receive only the corresponding RXxA and RXxB is activated. Do not attempt to

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read or write to inactive data buffers. If the ADSP-21161 processor operates on the inactive transmit or receive buffers while the SPORT is enabled, unpredictable results may occur.

Clock and Frame Sync Frequencies (DIV)

The DIVx registers contain divisor values that determine frequencies for internally generated clocks and frame syncs. These registers are shown Figure 10-8 and in SPORT Divisor Registers (DIVx) on page A-112
DIV0 (0x1C5) DIV1 (0x1E5) DIV2 (0x1D5) DIV3 (0x1F5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

FSDIV Frame Sync Divisor

15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 1 5 4 0 0 3 0 2 0 1 0 0 0

CLKDIV Clock Divisor

Figure 10-8. DIVx Register The bit field CLKDIV specifies how many times the processors internal clock (CCLK) is divided to generate the transmit and receive clocks. The frame sync FS is considered a receive frame sync if the data pins are configured as receivers. Likewise, the frame sync FS is considered a transmit

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SPORT Control Registers and Data Buffers

frame sync if the data pins are configured as transmitters. The divisor is a 16-bit value, allowing a wide range of serial clock rates. Use the following equation to calculate the serial clock frequency: f CCLK FSCLK = ---------------------------------------2 ( CLKDIV + 1 ) The maximum serial clock frequency is equal to half the processors internal clock (CCLK) frequency, which occurs when CLKDIV is set to zero. Use the following equation to determine the value of CLKDIV to use, given the CCLK frequency and desired serial clock frequency: f CCLK CLKDIV = --------------------- 1 2 ( f SCLK ) The processors internal clock (CCLK) is the clock ratio determined by the CLKDBL pin and the CLK_CFG[1-0] pins. The bit field FSDIV specifies how many transmit or receive clock cycles are counted before generating a FS pulse (when the frame sync is internally generated). In this way, a frame sync can initiate periodic transfers. The counting of serial clock cycles applies to internally or externally generated serial clocks. The formula for the number of cycles between frame sync pulses is: # of serial clocks between frame syncs = FSDIV + 1 Use the following equation to determine the value of FSDIV, given the serial clock frequency and desired frame sync frequency: f SCLK FSDIV = ------------- 1 f SFS

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The frame sync is continuously active when FSDIV = 0. The value of FSDIV should not be less than the serial word length minus one (the value of the SLEN field in the serial port control register), as this may cause an external device to abort the current operation or cause other unpredictable results. If the serial port is not being used, the FSDIV divisor can be used as a counter for dividing an external clock or for generating a periodic pulse or periodic interrupt. The serial port must be enabled for this mode of operation to work. Exercise caution when operating with externally generated transmit clocks near the frequency of half the processors internal clock. There is a delay between when the clock arrives at the SCLKx pin and when data is outputthis delay may limit the receivers speed of operation. Refer to the data sheet for exact timing specifications. For reliable operation, use full-speed serial clocks only when receiving with an externally generated clock and externally generated frame sync (ICLK = 0, IFS = 0). Externally-generated late transmit frame syncs also experience a delay from when they arrive to when data is output. This can also limit the maximum serial clock speed. Refer to the ADSP-21161N DSP Microcomputer Data Sheet for exact timing specifications.

Data Word Formats

The format of the data words transmitted over the serial ports is configured by the DTYPE, SENDN, SLEN, and PACK bits of the SPCTLx control registers.

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Word Length
Serial ports can process word lengths of 3 to 32 bits for serial and multichannel modes and 8 to 32 bits for I2S mode. Word length is configured using the 5-bit SLEN field in the SPCTLx control registers. The value of SLEN is given as follows:
SLEN

= serial word length 1

Do not set the SLEN value to zero or one. Words smaller than 32 bits are right-justified in the receive and transmit buffers, residing in the least significant bit positions. Although serial ports process word lengths of 3 to 32 bits, transmitting or receiving words smaller than 7 bits at half the full clock rate of the processor may cause incorrect operation when DMA chaining is enabled. Chaining disables the processors internal I/O bus for several cycles while the new TCB parameters are being loaded. Receive data may be lost (for example, overwritten) during this period. Transmitting or receiving words smaller than five bits may cause incorrect operation when all the DMA channels are enabled with no DMA chaining.

Endian Format
Endian format determines whether serial words transmit MSB-first or LSB-first. Endian format is selected by the SENDN bit in the SPCTLx control registers. When SENDN = 0, serial words transmit (or receive) MSB-first. When SENDN = 1, serial words transmit (or receive) LSB-first.

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Data Packing and Unpacking

Received data words of 16 bits or less may be packed into 32-bit words, and 32-bit words being transmitted may be unpacked into 16-bit words. Word packing and unpacking is selected by the PACK bit in the SPCTLx control registers. When PACK = 1 in the control register, two successive words received are packed into a single 32-bit word, and each 32-bit word is unpacked and transmitted as two 16-bit words. The first 16-bit (or smaller) word is right-justified in bits 15-0 of the packed word, and the second 16-bit (or smaller) word is right-justified in bits 31-16. This applies to both receive (packing) and transmit (unpacking) operations. Companding may be used when word packing or unpacking is being used. When serial port data packing is enabled, the transmit and receive interrupts are generated for the 32-bit packed words, not for each 16-bit word. When 16-bit received data is packed into 32-bit words and stored in normal word space in processor internal memory, the 16-bit words can be read or written with short word space addresses. Data Type The DTYPE field of the SPCTLx control registers specifies one of four data formats (for non-multichannel operation) shown in Table 10-4. This bit field is reserved for I2S mode. Table 10-4. DTYPE and Data Formatting (DSP Serial Mode)
DTYPE 00 01 Data Formatting Right-justify, zero-fill unused MSBs Right-justify, sign-extend into unused MSBs

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Table 10-4. DTYPE and Data Formatting (DSP Serial Mode) (Contd)
DTYPE 10 11 Data Formatting Compand using -law (primary A channels only) Compand using A-law (primary A channels only)

These formats are applied to serial data words loaded into the receive and transmit buffers. Transmit data words are not zero-filled or sign-extended, because only the significant bits are transmitted. For multichannel operation, the companding selection and MSB-fill selection is independent (Table 10-5). Table 10-5. DTYPE and Data Formatting (Multichannel)
DTYPE x0 x1 0x 1x Data Formatting Right-justify, zero-fill unused MSBs Right-justify, sign-extend into unused MSBs Compand using -law (primary A channels only) Compand using A-law (primary A channels only)

Linear transfers occur if the channel is active and companding is not selected for that channel. Companded transfers occur if the channel is active and companding is selected for that channel. The multichannel compand select registers, MTzCCSx and MRzCCSx, specify the transmit and receive channels that are companded. Transmit or receive sign extension is selected by bit 0 of DTYPE in the SPCTLx register and is common to all transmit or receive channels. If bit 0 of DTYPE is set, sign extension occurs on selected channels that do not have companding selected. If this bit is not set, the word contains zeros in the MSBs.

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Companding
Companding (compressing/expanding) is the process of logarithmically encoding and decoding data to minimize the number of bits that must be sent. The serial ports support the two most widely used companding algorithms, A-law and -law, performed according to the CCITT G.711 specification. The type of companding can be selected independently for each SPORT. Companding is selected by the DTYPE field of the SPCTLx control register. Companding is supported on the A channel only. SPORTs 2 and 3 primary channels are capable of compression, while SPORTs 0 and 1 primary channels are capable of expansion. When companding is enabled, the data in the RX0A and RX1A buffers is the right-justified, sign-extended expanded value of the eight received LSBs. A write to TX2A and TX3A compresses the 32-bit value to eight LSBs (zero-filled to the width of the transmit word) before it is transmitted. If the 32-bit value is greater than the 13-bit A-law or 14-bit -law maximum, it is automatically compressed to the maximum value. Since the values in the transmit and receive buffers are actually companded in-place, the companding hardware can be used without transmitting (or receiving) any data, for example during testing or debugging. This operation requires one cycle of overhead, as described below. For companding to execute properly, program the SPORT registers prior to loading data values into the SPORT buffers. To compand data in-place, without transmitting: 1. Enable companding in the DTYPE field (bits 21) and enable the DDIR bit (bit 25) of the SPCTLx transmit control register. 2. Write a 32-bit data word to the transmit buffer. The companding is calculated in this cycle.

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Clock Signal Options

3. Wait one cycle. A NOP instruction can be used to do this; if a NOP is not inserted, the core is held off for one cycle anyway. This allows the serial port companding hardware to reload the transmit buffer with the companded value. 4. Read the 8-bit companded value from the transmit buffer. The following is an example for companding data in-place.
R0=0x2000004; Dm(0x1f0)=r0; Nop;nop;nop;nop; R0=0x1234; Dm(0x1f1)=r0; Nop; R0=dm(0x1f1); // Read compressed value (0x8D) from TX3A // Write 0x1234 to TX3A //Set up SPCTL3

To expand data in-place, use the same sequence of operations with the receive buffer instead of the transmit buffer. When expanding data in this way, set the appropriate serial word length (SLEN) in the SPCTLx control register. With companding enabled, interfacing the serial port to a codec requires little additional programming effort. If companding is not selected, two formats are available for received data words of fewer than 32 bits: one that fills unused MSBs with zeros, and another that sign-extends the MSB into the unused bits.

Clock Signal Options

Each serial port has a clock signal (SCLKx) for transmitting and receiving data on the two associated data pins. The clock signals are configured by the ICLK and CKRE bits of the SPCTLx control registers. The serial clock frequency is configured in the DIVx. A single clock pin clocks both data pins (either configured as inputs or outputs) to receive or transmit data at the same rate.

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The serial clock can be independently generated internally or input from an external source. The ICLK bit of the SPCTLx control registers determines the clock source. When ICLK is set (=1), the clock signal is generated internally by the processor and the SCLKx pins are outputs. The clock frequency is determined by the value of the serial clock divisor (CLKDIV) in the DIVx registers. When ICLK is cleared (=0), the clock signal is accepted as an input on the SCLKx pins, and the serial clock divisors in the DIVx registers are ignored. The externally generated serial clock does not need to be synchronous with the system clock.

Frame Sync Options

Framing signals indicate the beginning of each serial word transfer. A variety of framing options are available on the SPORTs. The FSx signals are independent and are separately configured in the control register.

Framed Versus Unframed

The use of frame sync signals is optional in serial port communications. The FSR (transmit frame sync required) control bit determines whether frame sync signals are required. Active-low or active-high frame syncs are selected using the LFS bit in DSP serial mode and the LRFS bit in multichannel mode. These bits are located in the SPCTLx control registers. When FSR is set (=1), a frame sync signal is required for every data word. To allow continuous transmission from the processor, each new data word must be loaded into the transmit buffer before the previous word is shifted out and transmitted.

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Frame Sync Options

When FSR is cleared (=0), the corresponding frame sync signal is not required. A single frame sync is required to initiate communications but it is ignored after the first bit is transferred. Data words are then transferred continuously in what is referred to as an unframed mode. When DMA is enabled in a mode where frame syncs are not required, DMA requests may be held off by chaining or may not be serviced frequently enough to guarantee continuous unframed data flow. Figure 10-9 illustrates framed serial transfers.

SCLK

FRAMED DATA

B 3

B 2

B 1

B 0

B 3

B 2

B 1

B 0

UNFRAMED DATA B 3 B 2 B 1 B 0 B 3 B 2 B 1 B 0 B 3 B 2 B 1

Figure 10-9. Framed Versus Unframed Data

Internal Versus External Frame Syncs

Both transmit and receive frame syncs can be generated internally or input from an external source. The IFS bit of the SPCTLx control register determines the frame sync source.

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When IFS is set (=1), the corresponding frame sync signal is generated internally by the processor, and the FSx pin is an output. The frequency of the frame sync signal is determined by the value of the frame sync divisor (FSDIV) in the DIVx register. When IFS is cleared (=0), the corresponding frame sync signal is accepted as an input on the FSx pins, and the frame sync divisors in the DIVx registers are ignored. All of the frame sync options are available whether the signal is generated internally or externally.

Active Low Versus Active High Frame Syncs

Frame sync signals may be active high or active low (for example, inverted). Active-low or active-high frame syncs are selected using the LFS bit in DSP serial mode and the LRFS bit in multichannel mode. These bits are located in the SPCTLx control registers. LFS determines the frame syncs logic level: When LFS is cleared (=0), the corresponding frame sync signal is active high. When LFS is set (=1), the corresponding frame sync signal is active low. Active high frame syncs are the default. The LFS bit is initialized to 0 after a processor reset.

Sampling Edge for Data and Frame Syncs

Data and frame syncs can be sampled on the rising or falling edges of the serial port clock signals. The CKRE bit of the SPCTLx control registers selects the sampling edge.

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Frame Sync Options

For receive/transmit data and frame syncs, setting CKRE to 1 in SPCTLx selects the rising edge of SCLKx. When CKRE is cleared (=0), the processor selects the falling edge. Note that data and frame sync signals change state on the clock edge that is not selected. For example, the transmit and receive functions of any two serial ports connected together should always select the same value for CKRE so internally generated signals are driven on one edge and received signals are sampled on the opposite edge.

Early Versus Late Frame Syncs

Frame sync signals can be early or late. Frame sync signals can occur during the first bit of each data word or during the serial clock cycle immediately preceding the first bit. The LAFS bit of the SPCTLx control register configures this option. When LAFS is cleared (=0), early frame syncs are configured. This is the normal mode of operation. In this mode, the first bit of the transmit data word is available (and the first bit of the receive data word is latched) in the serial clock cycle after the frame sync is asserted. The frame sync is not checked again until the entire word has been transmitted (or received). In multi-channel operation, this is the case when frame delay is 1. If data transmission is continuous in early framing mode (for example, the last bit of each word is immediately followed by the first bit of the next word), the frame sync signal occurs during the last bit of each word. Internally generated frame syncs are asserted for one clock cycle in early framing mode. When LAFS is set (=1), late frame syncs are configured. In this mode, the first bit of the transmit data word is available (and the first bit of the receive data word is latched) in the same serial clock cycle that the frame sync is asserted. In multichannel operation, this is the case when frame delay is zero. Receive data bits are latched by serial clock edges, but the frame sync signal is checked only during the first bit of each word. Inter-

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nally generated frame syncs remain asserted for the entire length of the data word in late framing mode. Externally generated frame syncs are only checked during the first bit. They do not need to be asserted after that time period. Figure 10-10 illustrates the two modes of frame signal timing.
SCLK

LATE FRAME SYNC EARLY FRAME SYNC

DATA

B3

B2

B1

B0

Figure 10-10. Normal vs. Alternate Framing

Data-Independent Transmit Frame Sync

Normally, the internally generated frame sync signal, in the case of transmitting data out of the SPORT (DDIR = 1), is output only when the transmit buffer has data ready to transmit. The Data-Independent Transmit Frame Sync (DITFS) mode allows the continuous generation of the FSx signal, with or without new data in the transmit register. The DITFS bit of the SPCTLx control register configures this option. When DITFS is cleared (= 0), the internally generated (transmit) frame sync is only output when a new data word has been loaded into the transmit buffer. Once data is loaded into the transmit buffer, it is not transmitted until the next frame sync is generated. This mode of operation allows data to be transmitted only at specific times.

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SPORT Loopback

When DITFS is set (=1), the internally generated (transmit) frame sync is output at its programmed interval regardless of whether new data is available in the transmit buffer. Whatever data is present in the transmit buffer is retransmitted with each assertion of frame sync. Depending on the SPORT operating mode, the TUVF_A or DERR_A/DERR_B transmit underflow status bit is set when this occurs (for example, when old data is retransmitted). The TUVF_A or DERR_A/DERR_B status bit is also set if the transmit buffer does not have new data when an externally generated frame sync occurs. In this mode of operation, the first internally generated frame sync is delayed until data has been loaded into the transmit buffer. If the internally generated frame sync is used, a single write to the transmit data register is required to start the transfer.

SPORT Loopback
When the SPORT loopback bit (SPL) is set in the SP02MCTL or SP13MCTL control register, the serial port is configured in an internal loopback connection as follows: SPORT0 and SPORT2 work as a pair for internal loopback, SPORT1 and SPORT3 work as a pair for internal loopback. The loopback configuration allows the serial ports to be tested internally. When loopback is configured, the DxA, DxB, SCLKx, and FSx signals of the SPORT0 and SPORT1 are internally connected to the DyA, DyB, SCLKy, and FSy signals of SPORT2 and SPORT3 respectively where x = 0 or 1, and y = 2 or 3. In loopback mode, either of the two paired SPORTS can be a transmitter or receiver. One SPORT in the loopback pair must be configured as a transmitter, and the other must be configured as a receiver. For example, SPORT0 can be a transmitter and SPORT2 can be a receiver for internal loopback. Or, SPORT0 can be a receiver and SPORT2 can be the transmitter when setting up internal loopback. The processor ignores external

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activity on the SCLKx, FSx, A and B channel data pins when the SPORT is configured as the receiver. This prevents contention with the internal loopback data transfer. Only transmit clock and transmit frame sync options may be used in loopback modeprograms must ensure that the serial port is set up correctly in the SPCTLx control registers. Multichannel mode is not allowed. Only standard DSP serial and I2S modes support internal loopback.

SPORT Operation Modes

SPORTs operate in three modes: standard DSP serial mode, I2S mode, and multichannel mode. Depending on the operation mode, the control bits are redefined. The operating mode bit (OPMODE) of SPCTLx register selects between I2S mode and non I2S mode (DSP serial port/multichannel mode). In the non I2S mode, bit MCE in SPxyMCTL selects between the DSP serial port mode (standard mode) and multichannel mode. In addition to these bits, the data direction bit (DDIR) selects whether the port is a transmitter or receiver. The definition of all the control bits changes according to DDIR bit. The different operation modes are described in Table 10-6. Table 10-6. SPORT Operation Modes
OPMODE 0 0 1 1 MCE 0 1 X 1 Mode Standard DSP serial port Multichannel I2 S Reserved

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If DDIR bit is set (=1), the SPORT becomes a transmitter and all the other control bits are defined accordingly. Similarly for DDIR =0, the SPORT becomes a receiver. Multichannel mode and companding is not supported for I2S mode.

I 2 S Mode
I2S is a three-wire serial bus standard protocol for transmission of two channel (stereo) Pulse Code Modulation (PCM) digital audio data, in which each sample is sent MSB-first. Many of today's analog and digital audio front-end devices support the I2S protocol including: audio D/A and A/D converters, PC multimedia audio controllers, digital audio transmitters and receivers that support serial digital audio transmission standards such as AES/EBU, SP/DIF, IEC958, CP-340, and CP-1201, digital audio signal processors, dedicated digital filter chips, and sample rate converters. The I2S bus transmits audio data and control signals over separate lines. The data line carries two multiplexed data channels: the left channel and the right channel. In I2S mode, if both channels on a SPORT are set up to transmit, then SPORT transmit channels (TXxA and TXxB) transmit simultaneously, each transmitting left and right I2S channels. If both channels on a SPORT are set up to receive, the SPORT receive channels (RXxA and 2 RXxB) receive simultaneously, each receiving left and right I S channels. Data is transmitted in MSB format. Multichannel operation and companding are not supported in I2S mode. Each SPORT transmit or receive channel has channel enable, DMA enable, and chaining enable bits in its SPCTLx control register. The FSx signal is used as the transmit and/or receive word select signal. DMA-driven or interrupt-driven data transfers can also be selected using bits in the SPCTLx register.

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Setting Internal Serial Clock and Frame Sync Rates The serial clock rate (CLKDIV value) for internal clocks can be set using a bit field in the CLKDIV register. For details, see Clock and Frame Sync Frequencies (DIV) on page 10-33. I 2 S Control Bits Several bits in the SPCTLx control register enable and configure I2S operation: operation mode (OPMODE), word length (SLEN), I2S channel transfer order (L_FIRST), frame sync (word select) generation (FS_BOTH), master mode enable (MSTR), DMA enable (SDEN), and DMA chaining enable (SCHEN). Setting Word Length (SLEN) SPORTs handle data words containing 8 to 32 bits in I2S Mode. Set the bit length for transmit and receive data words. For details, see Word Length on page 10-36. The transmitter sends the MSB of the next word one clock cycle after the word select (TFS) signal changes. In I2S mode, load the FSDIV register with the same value as SLEN to transmit or receive words continuously. For example, for 8-bit data words (SLEN = 7), set FSDIV = 7. Selecting Transmit Receive Channel Order (L_FIRST) In master and slave modes, it is possible to configure the I2S channel that each SPORT channel transmits or receives first. By default, the SPORT channels transmit and receive on the right I2S channel first. The left and right I2S channels are time-duplexed data channels.

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To select the channel order, set the L_FIRST bit (= 1) to transmit or receive on left channel first, or clear the L_FIRST bit (= 0) to transmit or receive on right channel first. Selecting the Frame Sync Options (FS_BOTH) The processor uses FSx as transmit or receive word select signals, depending on configured direction of the data pins. When the processor generates the transmit word select signal (based on the data in the transmit channels), set FS_BOTH (= 1) to generate the word select signal when both transmit channels contain data. Clear FS_BOTH (= 0) to generate word select signal if either transmit channel contains data. The word select signal changes one clock cycle before the MSB of the data word transmits, enabling the slave transmitter to derive synchronous timing of the serial data and enabling the receiver to store the previous data word and clear its input for the next one. When using both SPORT channels (DxA and DxB) as transmitters (FS_BOTH = 1) and MSTR = 1 and DITFS = 0, the processor generates a frame sync signal only when both transmit buffers contain data because both transmitters share the same CLKDIV and FS. For continuous transmission, both transmit buffers must contain new data. When using both SPORT channels as transmitters and MSTR = 1 and DITFS = 1, the processor generates a frame sync signal at the frequency set by FSDIV = x whether or not the transmit buffers contain new data. In this case, the processor ignores the FS_BOTH bit. The DMA controller or the application is responsible for filling the transmit buffers with data. Enabling SPORT Master Mode (MSTR) The SPORTs transmit and receive channels can be configured for master or slave mode. In master mode, the processor generates the word select and serial clock signals for the transmitter or receiver. In slave mode, an external source generates the word select and serial clock signals for the

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transmitter or receiver. When MSTR is cleared (= 0), the processor uses an external word select and clock source. The SPORT transmitter or receiver is a slave. When MSTR is set (= 1), the processor uses the processors internal clock for word select and clock source. The SPORT transmitter or receiver is the master. Enabling SPORT DMA (SDEN) DMA can be enabled or disabled independently on any of the SPORTs transmit and receive channels. Set SDEN (= 1) to enable DMA and set channel in DMA-driven data transfer mode. Clear SDEN (= 0) to disable DMA and set the channel in an interrupt-driven data transfer mode.
Interrupt-Driven Data Transfer Mode

In this mode, both the A and B channels share a common interrupt vector, regardless of being configured as a transmitter or receiver. The SPORT generates an interrupt when the transmit buffer has a vacancy or the receive buffer has data. To determine the source of an interrupt, applications must check the TXSx or RXSx data buffer status bits, respectively.
DMA-Driven Data Transfer Mode

Each transmitter and receiver has its own DMA registers. For details, see Serial Port DMA on page 6-95. The same DMA channel drives the left and right I2S channels for the transmitter or the receiver. The software application must de-multiplex the left and right channel data received by the receive buffer, because the left and right data is interleaved in the DMA buffers. Channel A and B on each SPORT share a common interrupt vector. The DMA controller generates an interrupt at the end of DMA transfer only.

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Figure 10-11 shows the relationship between FS (word select), serial clock, and I2S data. Timing for word select is the same as for frame sync. Note that this example uses early frame sync.
SCLK

FS/WS

I2S DATA DxA OR DxB

L 3

L 2

L 1

R 3

R 2

R 1

LEFT CHANNEL

RIGHT CHANNEL

Figure 10-11. Word Select Timing in I2S Mode

Multichannel Operation
The serial ports offer a multichannel mode of operation which allows the SPORT to communicate in a time-division-multiplexed (TDM) serial system. In multichannel communications, each data word of the serial bit stream occupies a separate channel. Each word belongs to the next consecutive channel. For example, a 24-word block of data contains one word for each of 24 channels. The serial port can automatically select words for particular channels while ignoring the others. Up to 128 channels are available for transmitting or receiving or both. SPORT0 and SPORT1 receive and SPORT2 and SPORT3 transmit data selectively from any of the 128 channels. Data companding and DMA transfers can also be used in multichannel mode on channel A. Channel B is not used in multichannel mode.

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Although the four SPORTs are programmable for data direction in the standard mode of operation, their programmability is restricted for multichannel operations due to implementation and backward compatibility issues. See the configuration shown in Figure 10-12. The following points summarize these limitations: 1. The primary A channels of SPORT0 and SPORT1 are capable only of expansion, and the primary A channels of SPORT2 and SPORT3 are capable only of compression. 2. In multichannel mode, SPORT0 and SPORT2 work in pairs; SPORT0 is the receive channel, and SPORT2 is the transmit channel. The same is true for SPORT1 and SPORT3. 3. Receive comparison is not supported.

SPORT0 SPORT2 D0a D0b FS0 SCLK0 D1a D1b FS1 SCLK1 D2a D2b TDV2 SCLK2 D3a D3b TDV3 SCLK3

SPORT1 SPORT3

Figure 10-12. SPORT Multichannel Mode Pairings: SPORT0 and SPORT2, SPORT1 and SPORT3 In multichannel mode, the SCLKx2 and SCLKx3 pin is an input and is internally connected to its corresponding SCLKx0 and SCLKx1 pins. It is not necessary to externally connect SCLKx2 to SCLKx0 and SCLKx1 to SCLKx3.

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SPORT Operation Modes

Figure 10-13 shows example timing for a multichannel transfer with SPORT pairing. The transfer has the following characteristics: Uses the TDM method in which serial data is sent or received on different channels sharing the same serial bus.
FS0 FS2

signals start of frame for each multichannel SPORT pairings.

and FS3 are used as transmit data valid for external logic. These signals are active only during transmit channels. In a SPORT0/SPORT2 multichannel mode pairing, FS2 is the transmit data valid signal. In a SPORT1/SPORT3 multichannel mode pairing, FS3 is the transmit data valid signal.

Receive on channels 0 and 2; transmit on channels 1 and 2.

WORD 0

WORD 1

WORD 2

SCLK0 D0A FS0 D2A B3 B2 B1 B0 IGNORED B3 B2

B3

B2

B1

B0

B3

B2

TDV2

Figure 10-13. Multichannel Operation Frame Syncs in Multichannel Mode All receiving and transmitting devices in a multichannel system must have the same timing reference. The FS0 or FS1 signal is used for this reference, indicating the start of a block (or frame) of multichannel data words.

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When multichannel mode is enabled on a SPORT0/2 or SPORT1/3 pair, both the transmitter and receiver use FS0/FS1 signal as a frame sync. This is true whether FS0 or FS1 is generated internally or externally. The FS0/FS1 signal synchronizes the channels and restarts each multichannel sequence. FS0/FS1 assertion occurs at the beginning of the channel 0 data word. or FS3 is used as a transmit data valid signal, which is active during transmission of an enabled word. Because the serial ports D2A and D3A pins are three-stated when the time slot is not active, the FS2/FS3 signal specifies whether D2A/D3A is being driven by the ADSP-21161 processor. The processor drives FS2/FS3 in multichannel mode whether or not DITFS is cleared.
FS2

is renamed TDV2 and FS3 is renamed TDV3 in multichannel mode. These pins become outputs. Do not connect FS2 (TDV2) to FS0, and FS3 (TDV3) to FS1, in multichannel mode. Bus contention between the transmit data valid and multichannel frame sync pins will result.
FS2

After the TXxA transmit buffer is loaded, transmission begins and the FS2/FS3 signal is generated. When serial port DMA is used, this may happen several cycles after the multichannel transmission is enabled. If a deterministic start time is required, pre-load the transmit buffer. Multichannel Control Bits in SPCTL The SPCTLx control registers contain several bits that enable and configure multichannel operations. Multichannel mode is enabled by setting the MCE bit in the SP02MCTL or SP13MCTL control register: When MCE is set (= 1), multichannel operation is enabled. When MCE is cleared (= 0), all multichannel operations are disabled. Multichannel operation is activated three cycles after MCE is set. Internally generated frame sync signals activate four cycles after MCE is set.

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Setting the MCE bit enables multichannel operation for both receive and transmit sides of the SPORT0/2 or SPORT1/3 pair. A transmitting SPORT2 or SPORT3 must be in multichannel mode if the receiving SPORT0 or SPORT1 is in multichannel mode. The number of channels used in multichannel operation is selected by the 7-bit NCH field in the SP02MCTL and SP13MCTL multichannel control register. Set NCH to the actual number of channels minus one:
NCH

= Number of Channels 1

The 7-bit CHNL field in the SP02MCTL and SP13MCTL multichannel control registers indicates the channel that is currently selected during multichannel operation. This field is a read-only status indicator. CHNL(6:0) increments modulo NCH(6:0) as each channel is serviced. The 4-bit MFD field in the SP02MCTL and SP13MCTL multichannel control registers specifies a delay between the frame sync pulse and the first data bit in multichannel mode. The value of MFD is the number of serial clock cycles of the delay. Multichannel frame delay allows the processor to work with different types of T1 interface devices. A value of zero for MFD causes the frame sync to be concurrent with the first data bit. The maximum value allowed for MFD is 15. A new frame sync may occur before data from the last frame has been received, because blocks of data occur back to back. Use a multichannel frame delay of at least one pulse when the processor is generating frame syncs for the multichannel system and the serial clock of the system is equal to CLKIN (the processor clock). If MFD is not set to at least one, the master processor in a multiprocessing system does not recognize the first frame sync after multichannel operation is enabled. All succeeding frame syncs are recognized normally.

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Channel Selection Registers Specific channels can be individually enabled or disabled to select the words that are received and transmitted during multichannel communications. Data words from the enabled channels are received or transmitted, while disabled channel words are ignored. Up to 128 channels are available for transmitting and up to 128 channels for receiving. The multichannel selection registers enable and disable individual channels. The registers for each serial port are as shown in Table 10-7. Table 10-7. Multichannel Selection Registers
Register Names MR0CS(0-3) MR1CS(0-3) MT2CS(0-3) MT3CS(0-3) MR0CCS(0-3) MR1CCS(0-3) MT2CCS(0-3) MT3CCS(0-3) Function Multichannel Receive Select-specifies the active receive channels (4x32-bit registers for 128 channels) Multichannel Transmit Select-specifies the active transmit channels (4x32-bit registers for 128 channels) Multichannel Receive Compand Select-specifies which active receive channels (out of 128 channels) are companded Multichannel Transmit Compand Select-specifies which active transmit channels (out of 128 channels) are companded

Each of the four multichannel enable and compand select registers are 32-bits in length. These registers provide channel selection for 128 (32 x 4 = 128) channel. Setting a bit enables that channel so that the serial port selects its word from the multiple-word block of data (for either receive or transmit). For example, setting bit 0 in MR0CS0 or MT2CS0 selects word 0, setting bit 12 selects word 12, and so on. Setting bit 0 in MR0CS1 or MT2CS1 selects word 32, setting bit 12 selects word 44, and so on.

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Setting a particular bit to 1 in the MT2CS(0-3) or MT3CS(0-3) register causes SPORT2 or SPORT3 to transmit the word in that channels position of the data stream. Clearing the bit in the MT2CS(0-3) or MT3CS(0-2) register causes SPORT2s D2A or SPORT3s D3A data transmit pin to three-state during the time slot of that channel. Setting a particular bit to 1 in the MR0CS(0-3) or MR1CS(0-3) register causes the serial port to receive the word in that channels position of the data stream; the received word is loaded into the receive buffer. Clearing the bit in the MR0CS(0-3)/MR1CS(0-3) register causes the serial port to ignore the data. Companding may be selected on a per-channel basis. Setting a bit to 1 in any of the multichannel registers specifies that the data be companded for that channel. A-law or -law companding can be selected using the DTYPE bits in the SPCTLx control registers. SPORT0 and SPORT1 expand selected incoming time slot data, while SPORT2 and SPORT3 compress selected outgoing time slot data.

Transferring Data to Memory

Transmit and receive data can be transferred between the serial ports and on-chip memory with single-word transfers or with DMA block transfers. Both methods are interrupt-driven, using the same internally generated interrupts. When serial port DMA is not enabled in the SPCTLx control registers, the SPORT generates an interrupt every time it receives a data word or starts to transmit a data word. SPORT DMA provides a mechanism for receiving or transmitting an entire block of serial data before the interrupt is generated. The ADSP-21161 processors on-chip DMA controller handles the DMA transfer, allowing the processor core to continue running until the entire block of data is transmitted or received. Service routines can then operate on the block of data rather than on single words, significantly reducing overhead. 10-58 ADSP-21161 SHARC Processor Hardware Reference

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DMA Block Transfers

The ADSP-21161 processors on-chip DMA controller allows automatic DMA transfers between internal memory and the two serial ports. There are eight DMA channels for serial port operations. Each SPORT has one channel for receiving data and one channel for transmitting data. The serial port DMA channels are numbered as shown in Table 10-8. Table 10-8. Serial Port DMA Channels
Channel 0 1 2 3 4 5 6 7 Data Buffer RX0A/TX0A RX0B/TX0B RX1A/TX1A RX1B/TX1B RX2A/TX2A RX2B/TX2B RX3A/TX3A RX3B/TX3B Description SPORT0 A data SPORT0 B data SPORT1 A data SPORT1 B data SPORT2 A data SPORT2 B data SPORT3 A data SPORT3 B data Lowest Priority Highest

Data-direction programmability is supported in standard DSP serial mode and I2S mode. The value of the DDIR bit in SPCTL (0=RX, 1=TX) in SPCTLx determines whether the receive or transmit register for the SPORT becomes active. The SPORT DMA channels are assigned higher priority than all other DMA channels (for example, link ports and the external port) because of their relatively low service rate and their inability to hold off incoming data. Having higher priority causes the SPORT DMA transfers to be performed first when multiple DMA requests occur in the same cycle.

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Although the DMA transfers are performed with 32-bit words, serial ports can handle word sizes from 3 to 32 bits (8 to 32-bits for I2S mode). If serial words are 16 bits or smaller, they can be packed into 32-bit words for each DMA transfer; this is configured by the PACK bit of the SPCTLx control registers. When serial port data packing is enabled (PACK=1), the transmit and receive interrupts are generated for the 32-bit packed words, not for each 16-bit word. The following sections present an overview of serial port DMA operations; additional details are covered in the DMA chapter of this manual. For information on SPORT DMA Channel Setup, see Setting Up Serial Port DMA on page 6-100. For information on SPORT DMA Parameter Registers, see Serial Port DMA on page 6-95. For information on SPORT DMA Chaining, see Chaining DMA Processes on page 6-25. Setting Up DMA on SPORT Channels Each SPORT DMA channel has an enable bit (SDEN) in its SPCTLx control register. When DMA is disabled for a particular channel, the SPORT generates an interrupt every time it receives a data word or whenever there is a vacancy in the transmit buffer. For more information, see Single-Word Transfers on page 10-65. Each channel also has a DMA chaining enable bit (SCHEN) in its SPCTLx control register. To set up a serial port DMA channel, write a set of memory buffer parameters to the SPORT DMA parameter registers shown in Table 10-9. Load the II, IM, and C registers with a starting address for the buffer, an address modifier, and a word count, respectively. These registers can be written from the core processor or from an external processor.

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Table 10-9. SPORT DMA Parameter Registers

Register1 IIxY IMxY CxY CPxY GPxY 1 Description DMA channel. x index; Start address for data buffer DMA channel. x modify; Address increment DMA channel. x count; Number of words to transmit DMA channel. x chain pointer; Address next set of data buffer parameters DMA channel x general purpose

Y = A or B, and x = 0 - 3

Once serial port DMA is enabled, the processors DMA controller automatically transfers received data words in the receive buffer to the buffer in internal memory. Likewise, when the serial port is ready to transmit data, the DMA controller automatically transfers a word from internal memory to the transmit buffer. The controller continues these transfers until the entire data buffer is received or transmitted. When the count register of an active DMA channel reaches zero (0), the SPORT generates the corresponding interrupt.

SPORT DMA Parameter Registers

A DMA channel consists of a set of parameter registers that implements a data buffer in internal memory and the hardware that the serial port uses to request DMA service. The parameter registers for each SPORT DMA channel and their addresses are shown in Table 10-10. These registers are part of the processors memory-mapped IOP register set. The DMA channels operate similarly to the processors data address generators (DAGs). Each channel has an index register (IIx) and a modify register (IMx) for setting up a data buffer in internal memory. It is necessary to initialize the index register with the starting address of the data buffer. After it transfers each serial I/O word to (or from) the SPORT, the DMA controller adds the modify value to the index register to generate ADSP-21161 SHARC Processor Hardware Reference 10-61

Transferring Data to Memory

the address for the next DMA transfer. The modify value in the IM register is a signed integer, which provides capability for both incrementing and decrementing the buffer pointer. Each DMA channel has a count register CxA/CxB, which must be initialized with a word count that specifies the number of words to transfer. The count register decrements after each DMA transfer on the channel. When the word count reaches zero, the SPORT generates the interrupt for the channel and automatically disables the DMA channel. Each SPORT DMA channel also has a chain pointer register (CPxA/CPxB) and a general-purpose register (GPxA/GPxB). The CPx register functions in chained DMA operations. The general-purpose registers can be used for any purpose. For more information on SPORT DMA chaining, see Serial Port DMA on page 6-95. Table 10-10. SPORT DMA Parameter Registers Addresses
Register II0A IM0A C0A CP0A GP0A Reserved 0x65- 0x67 II0B IM0B C0B CP0B GP0B 0x80 0x81 0x82 0x83 0x84 1 1 1 1 1 RX0B or TX0B RX0B or TX0B RX0B or TX0B RX0B or TX0B RX0B or TX0B Address 0x60 0x61 0x62 0x63 0x64 DMA Channel 0 0 0 0 0 SPORT Data Buffer RX0A or TX0A RX0A or TX0A RX0A or TX0A RX0A or TX0A RX0A or TX0A

Reserved 0x85 - 0x87 II1A 0x68 2 RX1A or TX1A

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Table 10-10. SPORT DMA Parameter Registers Addresses (Contd)

Register IM1A C1A CP1A GP1A Address 0x69 0x6A 0x6B 0x6C DMA Channel 2 2 2 2 SPORT Data Buffer RX1A or TX1A RX1A or TX1A RX1A or TX1A RX1A or TX1A

Reserved 0x6D - 0x6F II1B IM1B C1B CP1B GP1B 0x88 0x89 0x8A 0x8B 0x8C 3 3 3 3 3 RX1B or TX1B RX1B or TX1B RX1B or TX1B RX1B or TX1B RX1B or TX1B

Reserved 0x8D - 0x8F II2A IM2A C2A CP2A GP2A 0x70 0x71 0x72 0x73 0x74 4 4 4 4 4 RX2A or TX2A RX2A or TX2A RX2A or TX2A RX2A or TX2A RX2A or TX2A

Reserved 0x75 - 0x77 II2B IM2B C2B CP2B GP2B 0x90 0x91 0x92 0x93 0x94 5 5 5 5 5 RX2B or TX2B RX2B or TX2B RX2B or TX2B RX2B or TX2B RX2B or TX2B

Reserved 0x95 - 0x97 II3A 0x78 6 RX3A or TX3A

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Table 10-10. SPORT DMA Parameter Registers Addresses (Contd)

Register IM3A C3A CP3A GP3A Address 0x79 0x7A 0x7B 0x7C DMA Channel 6 6 6 6 SPORT Data Buffer RX3A or TX3A RX3A or TX3A RX3A or TX3A RX3A or TX3A

Reserved 0x7D - 0x7F II3B IM3B C3B CP3B GP3B 0x98 0x99 0x9A 0x9B 0x9C 7 7 7 7 7 RX3B or TX3B RX3B or TX3B RX3B or TX3B RX3B or TX3B RX3B or TX3B

When programming the serial port channel (A or B) as a transmitter only the corresponding TXxA and TXxB become active, while the receive buffers (RXxA and RXxB) remain inactive. Similarly, when the SPORT channel A and B is programmed as receive, only the corresponding RX0A and RX0B is activated. When performing core-driven transfers, write to the buffer designated by the DDIR bit setting in the SPCTL register. For DMA-driven transfers, the serial port logic performs the data transfer from internal memory to/from the appropriate buffer depending on DDIR bit setting. If the inactive SPORT data buffers are read or written to by core while the port is already being enabled, the core will hang. For example, if a SPORT is programmed to be a transmitter, while at the same time the core reads from the receive buffer of the same SPORT, the core hangs just as it would if it were reading an empty buffer that is currently active. This locks up the core permanently until the SPORT is reset.

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Therefore, set the direction bit, the serial port enable bit, and DMA enable bits before initiating any operations on the SPORT data buffers. If the processor operates on the inactive transmit or receive buffers while the SPORT is enabled, it can cause unpredictable results. SPORT DMA Chaining In chained DMA operations, the processors DMA controller automatically sets up another DMA transfer when the contents of the current buffer have been transmitted (or received). The chain pointer register (CPx) functions as a pointer to the next set of buffer parameters stored in memory. The DMA controller automatically downloads these buffer parameters to set up the next DMA sequence. For more information on SPORT DMA chaining, see Serial Port DMA on page 6-95. DMA chaining occurs independently for the transmit and receive channels of each serial port. Each SPORT DMA channel has a chaining enable bit (SCHEN) that when set (= 1) enables DMA chaining and when cleared (= 0) disables DMA chaining. Writing all zeros to the address field of the chain pointer register (CPx) also disables chaining.

Single-Word Transfers
Individual data words may also be transmitted and received by the serial ports, with interrupts occurring as each 32-bit word is transmitted or received. When a serial port is enabled and DMA is disabled, the SPORT DMA interrupts are generated whenever a complete 32-bit word has been received in the receive buffer, or whenever the transmit buffer is not full. Single-word interrupts can be used to implement interrupt-driven I/O on the serial ports. When the processor cores program reads a word from a serial ports receive buffer or writes a word to its transmit buffer, check the buffer's full/empty status to avoid hanging the processor core. (This can also happen to an external device, for example a host processor, when it is reading

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SPORT Pin/Line Terminations

or writing a serial port buffer.) The full/empty status can be read in the DXS bits of the SPCTLx. Reading from an empty receive buffer or writing to a full transmit buffer causes the processor (or external device) to hang, waiting for the status to change. To support debugging buffer transfers, the processor has a Buffer Hang Disable (BHD) bit. When set (= 1), this bit prevents the processor core from detecting a buffer-related stall condition, permitting debugging of this type of stall condition. For more information, see the BHD discussion on page 6-43. Multiple interrupts can occur if both SPORTs transmit or receive data in the same cycle. Any interrupt can be masked in the IMASK register; if the interrupt is later enabled in IMASK, the corresponding interrupt latch bit in IRPTL must be cleared in case the interrupt has occurred in the meantime. When serial port data packing is enabled (PACK = 1 in the SPCTLx control registers), the transmit and receive interrupts are generated for 32-bit packed words, not for each 16-bit word.

SPORT Pin/Line Terminations

The ADSP-21161 processor has very fast drivers on all output pins including the serial ports. The edge rate occurs at low-speed serial clock rates. Unlike previous SHARC processors, the ADSP-21161 processor contains internal series resistance equivalent to 50 on all input drivers. Therefore, for traces longer than six inches, external series resisters on control, SPORT data, clock or frame sync pins are not required on the processor side of the serial paths to dampen reflections from transmission line effects on point-to-point connections.

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SPORT Programming Examples

This section provides two programming examples written for the ADSP-21161 processor. The example in Listing 10-1 demonstrates how the core directly reads from the SPORT receive buffer and writes to the SPORT transmit buffer. The example in Listing 10-2 demonstrates how the core directly writes to the SPORT transmit buffer and reads from the SPORT receive buffer after an interrupt. Listing 10-1. Core-Driven Sport Loopback Example
/*__________________________________________________________ ADSP-21161 Core-Driven SPORT Loopback Example This example shows an internally looped-back SPORT 32-bit transfer. The core directly writes to the transfer buffer (TX2A) and reads from the receive buffer (RX0A). ____________________________________________________________*/ #include "def21161.h" #define N 8 .section/pm seg_rth; nop; jump start; .section/dm seg_dmda; .var source[N]= 0X11111111, 0X22222222, 0X33333333, 0X44444444, 0X55555555, 0X66666666, 0X77777777, 0X88888888; .var dest[N]; /*---------------------Main Routine-------------------------*/ .section/pm seg_pmco; start: /* Pointers to source and dest, I0=B0 Automatically */ B0=source; /* Reset vector from ldf file */

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L0=@source; B1=dest; L1=@dest; ustat3=dm(SYSCON); bit clr ustat3 BHD; dm(SYSCON)=ustat3; bit set mode1 CBUFEN; r0 = 0x00001000; /*Set the SPL bit in the SPxxMCTL register to enable loopback*/ dm(SP02MCTL)=r0; r0 = 0x0; dm(DIV0) = r0; r0 = 0x000021f1; /* Set bits SPEN_A, SLEN = 32, FSR--enable the A channel, set the word length to 32 bits, and require frame synch. */ dm(SPCTL0)=r0; r0=0x00270004; /*TCLKDIV=[FCCLK(96Mhz)/2xFSCLKx((19.2Mhz)]-1=0x0004 */ /*TFSDIV=[FSCLKx(9.6Mhz)/TFS(.24Mhz)]-1=0x0027 */ dm(DIV2)=r0; r0=0x20065f1; /* Set bits SPEN_A, SLEN=32, ICLK, IFS, FSR, DDIR--enable the A channel, set the word length to 32 bits, generate internal framesynch and clock, require frame synch, and set for transmit. */ dm(SPCTL2)=r0; lcntr = N, do send until LCE; r1=dm(i0,1); dm(TX2A)=r1; r0=dm(RX0A); /*Test data to be transmitted*/ /*Send data to buffer*/ /*Read data from buffer*/ /*Externally generated clock and framesync*/ /*Enable Circular Buffers*/ /*Disable Core Buffer Hang*/

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send:dm(i1,1)=r0; wait: idle; jump wait;

/*Store data*/

Listing 10-2. Core-Driven Interrupt Sport Loopback Example

/*________________________________________________________ ADSP-21161 Core-Driven Interrupt SPORT Loopback Example This example shows an internally looped-back SPORT 32-bit transfer. After receiving an interrupt, the core directly writes to the transfer buffer (TX2A) and reads from the receive buffer (RX0A). ___________________________________________________________*/ #include "def21161.h" #define N 8 .section/pm seg_rth; nop; jump start; .section/dm seg_dmda; .var source[N]= 0X11111111, 0X22222222, 0X33333333, 0X44444444, 0X55555555, 0X66666666, 0X77777777, 0X88888888; .var dest[N]; .section/pm sp0i_svc; jump IRQ; rti; rti; rti; /*----------------Main Routine----------------------------*/ .section/pm seg_pmco; start: /* Set pointers for source and dest, I0=B0 automatically */ /*Sport 0 Interrupt*/ /*Reset vector from ldf file*/

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B0=source; L0=@source; B1=dest; L1=@dest; ustat3=dm(SYSCON); bit clr ustat3 BHD; dm(SYSCON)=ustat3; bit set imask SP0I |SP2I; bit set mode1 CBUFEN | IRPTEN; /*Unmask SPORT0&2 Interrupts*/ /*Enable Circ. buffs & Global inters*/ r0 = 0x00001000; /* Set the SPL bit in the SPxxMCTL register to enable loopback */ dm(SP02MCTL)=r0; r0 = 0x0; dm(DIV0) = r0; r0 = 0x000021f1; /* Set bits SPEN_A, SLEN-32, FSR--enable the A channel, set the word length to 32 bits, and require frame synch. */ dm(SPCTL0)=r0; r0=0x00270004; /* TCLKDIV=[FCCLK(96Mhz)/2xFSCLKx((19.2Mhz)] -1=0x0004 */ /* TFSDIV=[FSCLKx(9.6Mhz)/TFS(.24Mhz)]-1=0x0027 */ dm(DIV2)=r0; r0=0x20065f1; /* Set bits SPEN_A, SLEN=32, ICLK, IFS, FSR, DDIR--enable the A channel, set the word length to 32 bits, generate internal framesynch and clock require frame synch, and set for transmit. */ dm(SPCTL2)=r0; wait: idle; /* Externally generated clock and framesync */ /*Disable Core Buffer Hang*/

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jump wait; IRQ: r1=dm(i0,1); dm(TX2A)=r1; r0=dm(RX0A); dm(i1,1)=r0; rti; /*Interrupt Service Routine*/ /*Test data to be transmitted*/ /*Send data to buffer*/ /*Read data from buffer*/ /*Store data*/

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11 SERIAL PERIPHERAL INTERFACE (SPI)

The ADSP-21161 processor is equipped with a synchronous serial peripheral interface port that is compatible with the industry-standard Serial Peripheral Interface (SPI). The SPI port supports communication with a variety of different peripheral devices including CODECs, data converters, sample rate converters, SP/DIF or AES/EBU digital audio transmitters and receivers, LCDs, shift registers, microcontrollers, and FPGA devices with SPI emulation. The processors SPI port provides the following features and capabilities: A simple four wire interface consisting of two data pins, a device select pin, and a clock pin Full-duplex operation that allow the ADSP-21161 processor to transmit and receive data simultaneously on the same port Special data formats to accommodate little and big endian data, different word lengths, and packing modes Master and slave modes as well as multi-master mode in which the ADSP-21161processor can be connected to up to four other SPI devices Open drain outputs to avoid data contention and to support multi-master scenarios Programmable baud rates, clock polarities, and phases Slave booting from a master SPI device

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Functional Description

Functional Description
The SPI interface has two shift registers: the transmit shift register (TXSR) and the receive shift register (RXSR). TXSR serially transmits data and RXSR receives data synchronously with the SPI clock signal (SPICLK). Figure 11-1 provides a block diagram of the ADSP-21161 processor SPI interface. The data is shifted into or out of the shift registers on two separate pins: the Master In Slave Out (MISO) pin and the Master Out Slave In (MOSI) pin.
MOSI MISO SPICLK SPIDS FLAGx

S SPI INTERFACE LOGIC

SPI Internal Clock Generator SPISTAT SPICTL

RX Shift Register

TX Shift Register

SPIRX Receive Register

DM data bus PM data bus I/0 data bus

SPITX Transmit Register

SPI IRQ or DMA Request

32

Figure 11-1. SPI Block Diagram During data transfers one SPI device acts as the SPI master by controlling the data flow. It does this by generating the SPICLK and asserting the SPI device select signal (SPIDS). The SPI master receives data using the MISO pin and transmits using the MOSI pin. The other SPI device acts as the SPI

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Serial Peripheral Interface (SPI)

slave by receiving new data from the master into its receive shift register using the MOSI pin. It transmits requested data out the transmit shift register using the MISO pin. The SPI has two 2-deep FIFOs: the transmit data buffer (SPITX) and the receive data buffer (SPIRX). Data to be transmitted is written to SPITX and then automatically transferred into the transmit shift register. Once a full data word has been received in the receive shift register, the data is automatically transferred into SPIRX from which the data can be read from. Programmable FLAGx pins provide slave selection. These pins are connected to the SPIDS of the slave devices. In a multi-master or multi-device ADSP-21161 processor environment in which multiple ADSP-21161 processors are connected via their SPI ports, all MOSI pins are connected together, all MISO pins are connected together, and the SPICLK pins are connected together as well. The FLAGx pins are connected to each of the slave SPI devices in the system via the SPIDS pins.

SPI Interface Signals

This section describes the signals used to connect the SPI ports in a system that has multiple devices. Figure 11-2 shows the master-slave connections between two ADSP-21161 processors.

SPICLK
The Serial Peripheral Interface Clock (SPICLK) signal is driven by the master device and controls the data transfer rate. It is an output signal if the device is configured as a master and an input signal if the device is configured as a slave. The master transmits data at a variety of baud rates. The SPICLK signal cycles once for each bit transmitted. The SPICLK signal is a gated clock that is active during data transfers, only for the length of the transferred word. SPICLK is configured with the BAUDR bits in the SPCTL register. The SPICLK clock rate (baud rate) can go as high as the rate given by the expression: f-core clock/8. The number of active

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SPI Interface Signals

ADSP-21161 SPI-COMPATIBLE MASTER DEVICE

SPICLK FLAGN

ADSP-21161 SPI-COMPATIBLE SLAVE DEVICE

SPICLK SPIDS

MOSI TXSR SPITX SPIRX

MOSI RXSR SPIRX SPITX

RXSR MISO MISO

TXSR

Figure 11-2. Master-Slave Interconnections clock edges is equal to the number of bits driven on the data lines. Slave devices ignore the serial clock if the slave select input SPIDS is driven inactive. The SPICLK signal shifts out and shifts in the data driven on the MISO and MOSI lines. The data is shifted out on one clock edge and sampled on the opposite clock edge. To define the transfer format, clock polarity and clock phase relative to data can be programmed into the SPICTL control register.

SPIDS
The Serial Peripheral Interface Slave Device Select (SPIDS) signal is an active low signal used to enable an SPI port of an ADSP-21161 processor that is configured as a slave device. This input-only pin behaves like a chip select and is provided by the master device for the slave devices. For a master device, this signal can act as an error signal input in a multi-master environment. In multi-master mode, SPIDS can be asserted (driven low) to a master device to signal that another device is trying to be the master

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Serial Peripheral Interface (SPI)

device. In this case, the ADSP-21161 processors SPIDS signal is used as an input error signal from the slave device. If this signal is asserted low when the device is in master mode, it is considered a multi-master error. For a single-master, multiple-slave configuration in which FLAG0-3 are used as slave selects, SPIDS must be tied high to VDD. For ADSP-21161 processor to ADSP-21161 processor SPI interaction, any of the master processors FLAG0-3 pins can be used to drive the SPIDS signal on the SPI slave device.

FLAG
The Flag (FLAGx) pins are general-purpose bidirectional I/O data pins. Each FLAG pin can be programmed as an input or output. For SPI, FLAG3-0 pins are used to select slaves in a system that has multiple SPI devices. When FLAGS are used for SPI to select a slave using and the PSSE and FLS bits are enabled, SPI has higher priority than the core for use of the pins. If PSSE is set (= 1), all of the four flags become slave selects. If a particular GPIO is programmed as output, and the PSSE feature on that flag pin is enabled at the same time, the FLAG register bit is not reflected on the flag pin. However, if the pin is programmed as input, the status of the pin is reflected in the FLAG register. The SPI state machine drives this pin for the slave SPI device and the status is updated in the FLAG register. When using this pin to drive SPIDS while some other device is using it as GPIO, for example, the other device should not drive any data on this pin. For related flag discussions, see the following sections: Automatic Slave Selection on page 11-26 Core-Based Flag Pins on page 13-34

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SPI Interface Signals

MOSI
The Master Out Slave In (MOSI) pin is one of the bidirectional I/O data pins. If the ADSP-21161 processor is configured as a master, the MOSI pin is a data transmit pin used to transmit output data. If the ADSP-21161 processor is configured as a slave, the MOSI pin is a data receive pin used to receive input data. In a system that has multiple SPI devices, data shifts out from the MOSI output pin of the master and into the MOSI input(s) of the slave(s).

MISO
The Master In Slave Out (MISO) pin is one of the bidirectional I/O data pins. If the ADSP-21161 processor is configured as a master, the MISO pin is a data receive pin used to receive input data. If the ADSP-21161 processor is configured as a slave, the MISO pin is a data transmit pin used to transmit output data. In a system that has multiple SPI devices, the data shifts out from the MISO output pin of the slave and into the MISO input pin of the master. Only one slave may transmit data at any given time. The user application code must ensure that when multiple devices are selected to transmit data from the master, only one slave will respond with data to be transmitted back to the master during the active transfer. The DMISO bit in the SPICTL register can be programmed to accomplish this. Figure 11-3 illustrates an example of an ADSP-21161 processor SPI interface where the processor is the SPI master. When using the SPI interface, the processor can be directed to alter the conversion resources, mute, modify the volume, and power down the AD1855 stereo DAC.

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Serial Peripheral Interface (SPI)

ADSP-21161
Master Device

AD1855
Stereo 96 kHz DAC SPICLK FLAG0 MOSI CCLK CLATCH DATA

Figure 11-3. ADSP-21161 as SPI Master Another SPI configuration example, shown in Figure 11-4, illustrates how the ADSP-21161 processor can be used as the SPI slave device. The 8-bit host microcontroller is the SPI master. The processor can be booted via its SPI interface to download user application code and data prior to runtime.

8-bit Host Microcontroller

ADSP-21161
Slave SPI Device

SCLK S_SEL MOSI MISO

SPICLK SPIDS MOSI MISO

Figure 11-4. ADSP-21161 as Slave SPI Device

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SPI Interrupts

SPI Interrupts
The SPI port has two interrupts: a transmit interrupt and a receive interrupt. If DMA is enabled, a maskable interrupt occurs when the DMA block transfer has completed. If DMA is disabled, the core processor may read the SPIRX register from or write to the SPITX data buffer. To enable an interrupt, program the SPIRX interrupt enable (SPRINT) or the SPITX interrupt enable (SPTINT) in the SPICTL register. The SPIRX and SPITX buffers are memory mapped IOP registers. A maskable interrupt is generated when the receive buffer is not empty or the transmit buffer is not full. In order for the SPI hardware to work properly, interrupts must always be enabled in the SPICTL register. If interrupts are not wanted or needed, they can be masked at a higher level in the LIRPTL register or the IMASK registers. The transmit interrupt vector location (0x44) is used for both core driven transmit interrupts and DMA driven transmit interrupts. The receive interrupt vector location (0x40) is used for both core driven receive interrupts and DMA driven receive interrupts. In order to use SPI interrupts, unmask the IRPTEN bit in the MODE1 register, unmask the LPISUMI bit in the IRPTL register, and unmask the SPIRMSK bit or SPITMSK bit in the LIRPTL register. See Interrupt Latch Register (IRPTL) on page A-27 for IRPTL register bit descriptions. See Link Port Interrupt Register (LIRPTL) on page A-34 for LIRPTL register bit descriptions.

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Serial Peripheral Interface (SPI)

SPI IOP Registers

The SPI peripheral in the ADSP-21161 processor has two IOP registers and two data buffers: a control register (SPICTL), and a status register (SPISTAT), a receive data buffer (SPIRX) and a transmit data buffer (SPITX). The IOP addresses for the SPI registers are given in Table 11-1. Table 11-1. IOP Addresses for SPI Registers
Register SPICTL SPISTAT SPIRX SPITX IOP Address 0xB4 0xB5 0xB7 0xB6

SPI Control Register (SPICTL)

The SPI Control (SPICTL) register configures and operates the SPI system. It can be read or written to at any time. During active SPI transfers, writes to the SPICTL register are buffered and do not take effect until the current word transfer has completed in the SPI. This occurs prior to the start of the transfer of the next word on the SPI. The SPICTL register enables the SPI interface, selects the device as a master or slave, and determines the data transfer and word size. The SPICTL register includes the SPI port enable (SPIEN) and SPI DMA enable bits (TDMAEN/RDMAEN). The SPIEN bit can be cleared (=0) to flush the SPI FIFO status. This clears the SPI FIFO status and any error status in the SPISTAT register. It can also be used to disable SPI transmission immediately. Table 11-2 and provides bit descriptions for the SPICTL register. See Figure 11-5 for the SPICTL register diagram.

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SPI IOP Registers

For revisions 0.3, 1.0 and 1.1 silicon, the SPI transmit and receive FIFOs cannot be cleared by disabling the SPI port via SPICTL. In order to clear the SPI receive FIFO, the application program must execute up to two dummy core reads from the SPIRX register. The number of reads needed depends on the number of words in the FIFO as shown in the FIFO buffer status. To clear out the SPITX FIFOs, clear all the FLS bits and then poll the SPITX buffer status in the SPISTAT register. Note that when the FLS bits are not set, there are no slave devices selected. However, the data will still be driven on the appropriate data pin. This FIFO clear operation may be important if you need to reprogram the SPI port to communicate to a new slave, or to change from a master to a slave SPI device. The default value of the SPICTL register at reset is 0x00000000. The value of the SPICTL register at slave boot is 0x0A001F81

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Serial Peripheral Interface (SPI)

SPICTL
0xB4
GM
Fetch/Discard Incoming RXB data when RXB full 0=Discard incoming data 1=Overwrite with new data

31 30 29 28 27 26 25 24 23 22 21 20 0 0 0 0 0 0 0 0 0 0 0 0

19 18 17 16 0 0 0 0

FLS1
FLAG1 Slave Device Select 1=Enable, 0=Disable

SENDLW
Send Zero/Repeat Byte When TXB Empty 0=Send zero, 1=Repeat last data

FLS2
FLAG2 Slave Device Select 1=Enable, 0=Disable

SGN
Sign Extend Data 0=no sign extend, 1=sign extend

FLS3
FLAG3 Slave Device Select 1=Enable, 0=Disable

PACKEN
8-bit Packing Enable 0=no packing, 1=8 to 32-bit packing

NSMLS
Non-Seamless operation 0=no delay, 1=delay before next word starts

RDMAEN
Receive DMA Enable 1=Enable, 0=Disable

OPD
Open Drain Output Enable for Data Pins 0=Normal, 1=Open Drain

DCPH0
Deselect SPIDS in CPHASE =0 (master mode only, NSMLS bit=1) 0=No SPI device select 1=Deselects slaves between successive transfers

DMISO
Disable MISO Pin (Broadcast) 0=MISO Enabled, 1=MISO Disabled

15 14 13 12 11 10 1 0 0 0 0 1

9 1

8 1

7 0

6 1

5 0

4 0

3 0

2 0

1 0

0 0 SPIEN
SPI System Enable 1=enable, 0=disable

FLS0
FLAG0 Slave Device Select 1=Enable, 0=Disable

PSSE
Programmable Slave Select Enable 0=Disable, 1=Enable

SPRINT
SPI RX Buffer Interrupt Enable 1=enable SPI IRQ on RXB empty, 0=disable

TDMAEN
Transmit DMA Enable 1=Enable, 0=Disable

SPTINT
SPI TX Buffer Interrupt Enable 1=enable SPI IRQ on TXB not full, 0=disable

BAUDR
Baud Rate CCLK / (2**(2 + BR))

MS
Master/Slave Mode Bit 0=SPI slave device, 1=SPI Master Device

WL
Word Length 00=8 bits, 01=16 bits, 11=32 bits, 10=RESERVED

CP
Clock polarity 0=SPICLK active high, low in idle state 1=SPICLK active low, high in idle state

DF
Data Format 0=LSB sent / received first 1=MSB sent / received first

CPHASE
Clock phase 0=SPICLK toggles at middle of 1st data bit 1=SPICLK toggles at beginning of 1st data bit

Figure 11-5. SPICTL Register

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SPI IOP Registers

Table 11-2. SPI Control Register Bit Descriptions

Bit(s) 0 1 Name SPIEN SPRINT Function SPI Port Enable. This bit enables (if set, =1) or disables (if cleared, =0) the SPI system. SPIRX Interrupt Enable. This bit enables (if set, =1) or disables (if cleared, =0) an SPI interrupt. An interrupt is generated when the receive buffer is not empty. SPITX Interrupt Enable. This bit enables (if set, =1) or disables (if cleared, =0) an SPI interrupt. An interrupt is generated when the transmit buffer is not full. Master Select. This bit selects the device as a master device (if set, =1) or a slave device (if cleared, =0). Clock Polarity. This bit selects the clock polarity. SPICLK high is the idle state (if set, =1), or SPICLK low is the idle state (if cleared, =0). Clock Phase. This bit selects the clock phase transfer format. When set (=1), the SPICLK starts toggling at the beginning of the first data transfer bit. When cleared (=0), the SPICLK starts toggling at the middle of the first data transfer bit. For more information, see Figure 11-7 on page 11-22 6 DF Data Format. This bit selects the data format. When set (=1), the MSB is sent/received first. When cleared (=0), the LSB is sent/received first. Word Length. These bits selects the word length as follows: 00 = 8 bits, 01 = 16 bits, 11 = 32 bits,10 = reserved. Baud Rate. These bits define the SPICLK frequency per the following equation: SPICLK baud rate= Core clock / 2(2 + BR) 13 TDMAEN Transmit DMA Enable. This bit enables (if set, =1) or disables (if cleared, =0) DMA transfers to the transmit buffer. At SPI boot this bit is 0.

SPTINT

3 4

MS CP

CPHASE

7-8 9-12

WL BAUDR

Bits 14 to 24 are controlled during master mode.

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Serial Peripheral Interface (SPI)

Table 11-2. SPI Control Register Bit Descriptions (Contd)

Bit(s) 14 Name PSSE Function Programmable Slave Select Enable. This bit is used to program the controlled automatic generation of slave device select signals during SPI transfers. This bit enables (if set, =1) or disables (if cleared, =0) the programmable slave select mode. The slave selection is subsequently made using the FLS bits. Flag Select. These bits select which flag pins are used when multiple slaves are used (0=disable, 1=enable) as follows: Bit 15= FLAG0 Bit 16= FLAG1 Bit 17= FLAG2 Bit 18= FLAG3 Note: Only Flag[0] to Flag[3] can be used this way. Non-Seamless Operation. This bit, if set (=1), indicates that after each word transfer there is a delay before the next word transfer starts. The delay is 2.5 SPICLK cycles. When cleared (=0), this bit indicates no delay before the next word starts, a seamless operation. Deselect SPIDS in CPHASE = 0. This bit deselects when high (=1) the slaves between successive word transfers in CPhase 0. The slave is selected in master mode using PSSE functionality. This bit has no effect in slave mode for the SPI port. This functionality is valid only when NSMLS =1. It works for CPHASE =0 and CPHASE =1. The standard SPI peripherals use this mode only in CPHASE =0. This bit is cleared (=0) when not in use. 25 DMISO Disable MISO Pin. This bit three-states, (if set, =1) the master in slave out (MISO) pin or (if cleared, =0) enables MISO. This is needed in an environment where master wishes to transmit to various slaves at one time (broadcast). Except for the slave from which it wishes to receive, all other slaves should have this bit set. Open Drain Output Enable. This bit enables an open drain for SPICLK, MOSI and MISO pins if set (=1) or remains normal if cleared (=0). If enabled, the MISO, MOSI and SPICLK is driven only for logic low and pulled up by a 50k resistance for a logic high.

15-18

FLS

19

NSMLS

20

DCPH0

26

OPD

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SPI IOP Registers

Table 11-2. SPI Control Register Bit Descriptions (Contd)

Bit(s) 27 Name RDMAEN Function Receive DMA Enable. This bit enables (if set, =1) or disables (if cleared, =0) DMA transfers from the receive buffer. At SPI boot this bit is set to 1 to enable the booting process via the SPI port. 28 PACKEN Packing Enable. This bit enables, if set (=1), 8- to 32-bit packing or disables the packing, if cleared (=0). If this bit is enabled, the receiver packs the received byte whereas the transmitter unpacks the data before sending it. Fore more information on the packing, see SPI Word Packing on page 11-24. Note: This bit should be 1 only for 8-bit data word length (WL = 00). Sign Extend. This bit sign extends the word if set (=1) or does not extend the sign if cleared (=0). Send Last Data. When SPITX is empty, setting this bit(=1) re-transmits the last data. Clearing this bit (=0) sends zeros. Get Data. This bit fetches incoming data when set (=1) or discards incoming data when cleared (=0). The data that comes in overwrites the previous data in the SPIRX.

29 30 31

SGN SENDLW GM

Baud Rate Example The BAUDR bits of the SPICTL register set the baud rate using the following formula:
coreclock ---------------------------------f SPICLK = 2 2 + BAUDR

If the core clock is 100 MHz and the BAUDR bits are 0xD (13), the SPICLK frequency is determined as follows: 100MHz f = --------------------------= 3052 Hz SPICLK

2 2 + 13

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Serial Peripheral Interface (SPI)

Seamless Operation The SPI port can transmit words seamlessly without delay by clearing (=0) the NSMLS bit in the SPICTL register. When seamless operation is disabled (NSMLS=1), there is a delay between word transfers from the SPI master. During this delay, the state machine disables and enables the slaves for DCPH0 = 1. The delay between words is 2.5 SPICLK cycles. Some slower slaves need time between data transfers to receive data and move new data for transmitting into the shift register. Set the NSMLS bit in the master device in order to create enough delay for the slave to perform data transfers.

SPI Status Register (SPISTAT)

The SPISTAT register is a read-only register that detects when an SPI transfer is complete, if transmission/reception errors occur, and the status of the SPITX and SPIRX data buffers. For all revisions, a reset flushes the SPI FIFOS. For revisions 1.2 and higher, the SPITX and SPIRX buffers are flushed by disabling the SPI port via the SPIEN bit in the SPICTL register. Figure 11-6 and Table 11-3 describe the eight status bits of the SPISTAT register.

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SPI IOP Registers

3 1 30 2 9 2 8 2 7 2 6 2 5 2 4

23 2 2 2 1 20 0 0 0 0

1 9 18 17 1 6 0 0 0 0

SP IS TA T 0xB 5

1 5 1 4 13 1 2 0 0 0 0

1 1 10 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

RXS
SP IR X D a ta B u ffer Statu s (R ead -on ly ) 00=S PIR X em p ty 01=S PIR X p artially fu ll 11=S PIR X full 10=R es erve d

S P IF
SPI T ran sm it T ran s fer C o m p lete 1=tran sfer co m ple te , 0= ac tiv e tran sfer

MME
M u ltim aster E rro r 0= n o erro r, 1 = SP ID S~ as serted b y s lave

RBSY
R ec ep tio n E rro r (O verflow ) 1=n ew d ata receiv ed with fu ll R XB FIFO S PI en ters id le m o d e if m aster d evice

TXE
Tran sm iss ion E rror (U nd erflow ) 1= n o n ew d ata in T X F IF O , S PI en ters id le m o d e if m aster d evice

TXS
SP IT X D a ta B u ffer Statu s (read o n ly) 00= S PIT X em p ty 01= T X B p artially full 11= S PIT X full 10= R eserv ed

Figure 11-6. SPISTAT Register

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Serial Peripheral Interface (SPI)

Table 11-3. SPI Status Register Bit Descriptions

Bit(s) 0 Name SPIF Revisions prior to 1.2 Definition SPI Transmit or Receive Transfer Complete. This bit is set (=1) when an SPI transfer is complete. 1) This bit is updated only during interrupt or DMA driven SPI transfers. For example: SPRINT =1 or SPTINT=1 or TDMAEN=1 or RDMAEN =1 2) The bit is set when the transmit buffer status is empty or the receive buffer status is full. 3) This bit does not reflect the status of the transmit or receive shift register. 4) This bit is a sticky bit that can be reset only by disabling the SPI (SPIEN =0). 1 MME Multimaster Error. This bit is set when a device that is not currently the master device tries to become the master by driving a SPIDS signal while the current master device is communicating to SPI slave devices. Multimaster Error. Same Revision 1.2 or greater Definition SPI Transmit Transfer Complete. This bit is set (=1) when an SPI transfer is complete. 1) This bit is updated during all SPI data transfers. 2) The bit is set when the transmit data buffer is empty and the data has been transmitted out of the transmit shift register. 3) This bit is not sticky.

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SPI IOP Registers

Table 11-3. SPI Status Register Bit Descriptions (Contd)

Bit(s) 2 Name TXE Revisions prior to 1.2 Definition Transmission Error. This bit is set (=1) if there is a transmission error. 1) This bit is updated only during interrupt or DMA driven SPI transfers. For example: SPTINT=1 or TDMAEN=1 2) This bit is set (=1) when the transmit data buffer status is empty. 3) This bit does not reflect the status of the transmit shift register. This bit is set when the transmit buffer is empty and the data in the shift register is being transmitted. 4) This bit is a sticky bit. It can be reset only by disabling the SPI (SPIEN =0). 4-3 TXS Transmit Data Buffer Status. These bits Transmit Data Buffer Status. indicate the status (read only) of the Same SPITX data buffer. These bits are updated whenever an access (write by core/DMA or read by shift register) is made to the transmit data buffer. The status is as follows: 00 = empty 01 = partially full 11 = full Revision 1.2 or greater Definition Transmission Error. This bit is set (=1) if there is a transmission error. 1) This bit is updated whenever there is a transmit error during all SPI data transfers. 2) This bit is set when the transmit buffer status is empty and the last data has been transmitted out of the transmit shift register. 3) This bit is a sticky bit. It can be reset only by disabling the SPI (SPIEN =0).

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Serial Peripheral Interface (SPI)

Table 11-3. SPI Status Register Bit Descriptions (Contd)

Bit(s) 5 Name RBSY Revisions prior to 1.2 Definition Reception Error. This bit is set (=1) if there is a reception error. 1) This bit is updated only during interrupt or DMA driven SPI transfers. For example SPRINT =1 or RDMAEN =1 2) This bit is set if the receive buffer status is full. 3) This bit does not reflect the status of the receive shift register. This bit will show high when the receive buffer is full, and the next data is being received by the shift register. 4) This bit is a sticky bit. It can be reset only by disabling the SPI (SPIEN =0). 7-6 RXS Receive Data Buffer Status. These bits indicate the status of the SPIRX data buffer (read only) as follows: 00 = empty 01 = partially full 11 = full 1) These bits are updated whenever an access (read by the core/DMA or write by shift register) is made to the receive data buffer. 31-8 Reserved Reserved Receive Data Buffer Status. Same Revision 1.2 or greater Definition Reception Error. This bit is set (=1) if there is a reception error. 1) This bit is updated whenever there is a receive error during all SPI transfers. 3) This bit is set if the receive buffer status is full and the last data has been received completely in the receive shift register. 2) This bit is a sticky bit. It can be reset only by disabling the SPI (SPIEN =0).

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SPI IOP Registers

SPI Transmit Data Buffer (SPITX)

The SPITX transmit data buffer is a 32-bit data buffer which is part of the IOP register set. The buffer is 2-deep. The SPITX data buffer can be accessed by the core or the DMA controller. Data is loaded into SPITX before being transmitted. Once the SPI is enabled, data in SPITX is automatically loaded into the transmit shift register. Consecutive writes to the SPITX may cause incorrect buffer status. A write to SPITX instruction and a read from SPISTAT instruction must be separated by at least one instruction for TXS to be reflected properly in SPISTAT. For interrupt based data transfers, the write to SPITX instruction and the RTI instruction of the ISR should be separated by at least one instruction.

SPI Receive Data Buffer (SPIRX)

The SPIRX receive data buffer is a 32-bit read-only data buffer accessible by the core or DMA controller. The buffer is 2-deep. After a word is received completely in the shift register RXSR, it is automatically transferred to the SPIRX. Do not perform a normal core write of SPITX during DMA operation. A normal core read of SPITX can be done at any time and does not interfere with, or initiate, SPI transfers. Do not perform a normal core read of SPIRX during DMA operation. A normal core write of SPIRX can be done at any time and does not interfere with, or initiate, SPI transfers. A core hang results from writing to a full SPITX buffer or from reading from an empty SPITX buffer.

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SPI Shift Registers

The SPI interface has two shift registers: one that serially transmits data (TXSR) and the other that receives data (RXSR) synchronously with the SPI clock signal (SPICLK). These registers are not directly accessible by the core or DMA controller. The registers shift right or left depending on the direction of the data flow (LSB first or MSB first) as defined by the DF bit in the SPICTL register. These shift registers include 32 shift cells that can be configured to transfer 8-, 16-, and 32-bit words.

SPI Data Word Formats

The ADSP-21161 processor SPI supports two transfer formats with respect to clock phases and clock polarities: CPHASE = 0 and CPHASE =1. The user application code can select one of the four combinations of serial clock phase and polarity using the CP and CPHASE bits in the SPICTL register. This section describes the transfer format and word packing for SPI transfers. See Table 11-2 on page 11-12 for SPICTL register bit description. A master SPI transfer starts when the MS bit and the SPIEN bit are set (= 1) in the SPICTL register. If the CPHASE bit in the SPICTL register is cleared (=0), the SPICLK signal remains inactive for the first half of the first cycle of SPICLK. A slave SPI transfer starts as soon as the SPIDS signal from the master goes low without waiting for the SPICLK edge. When CPHASE is set (=1), the transfer starts with the first edge of SPICLK going from its inactive state to the active state for both slave and the master devices. A transfer for a slave device is ended with SPIDS negated (inactive on rising edge). For a master device, transfer is considered complete after it transmits the last data word or receives the last data word. Figure 11-7 and Figure 11-8 demonstrates the two basic transfer formats as defined by the CPHASE bit. Two waveforms are shown for SPICLK: one for CP = 0 and the other for CP=1. The diagram may be interpreted as a ADSP-21161 SHARC Processor Hardware Reference 11-21

SPI Data Word Formats

master or slave timing diagrams since the SPICLK, MISO, and MOSI pins are directly connected between the master and the slave. The MISO signal is the output from the slave (slave transmission), and the MOSI signal is the output from the master (master transmission). The SPICLK signal is generated by the master, and the SPIDS signal is the slave device select input to the slave from the master. The diagram represents an 8-bit transfer (WL=00) with MSB first (DF=1). Any combination of the WL and DF bits of the SPICTL register is allowed. For example, a 32-bit transfer with LSB first is also a possible configuration.

CLOCK CYCLE NUMBER

SPICLK CLKPL=0 SPICLK CLKPL=1

MOSI FROM MASTER MISO FROM SLAVE SPIDS FROM MASTER

MSB

LSB

* *

MSB

LSB

*UNDEFINED

Figure 11-7. SPI Transfer Protocol for CPHASE = 0 The clock polarity and the clock phase must be identical for the master device and the slave device involved in the communication link. The transfer format from the master may be changed between transfers to adjust to various requirements of a slave device.

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Serial Peripheral Interface (SPI)

CLO CK CYCLE NUMBER

SPICLK CLKPL=0 SPICLK CLKPL=1

MOSI FROM MASTER MISO FROM SLAVE SPIDS TO SLAVE

MSB

LSB

MSB

LSB

* = UNDEF INED

Figure 11-8. SPI Transfer Protocol for CPHASE = 1 Enable DCPH0 (bit 20) (=1) to make the slave select line, SPIDS, inactive (HIGH) between each serial transfer. This is controlled automatically by hardware logic. This feature is available in both CPHASE=0 and CPHASE=1. The standard SPI peripherals use this mode only in CPHASE=0. Clearing the DCPH0 bit (=0) keeps SPIDS active low throughout the entire data transfer for both CPHASE=0 and CPHASE=1. Table 11-4. SPICLK Driving and Latching Edges for SPI Data Transfers
Phase 0 0 1 1 Polarity 0 1 0 1 Driving Edge of SPICLK Falling Edge Rising Edge Rising Edge Falling Edge Latching Edge of SPICLK Rising Edge Falling Edge Falling Edge Rising Edge

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SPI Operation Modes

SPI Word Packing

The SPI packs two 8-bit words in a 32-bit word as shown below. This packing is set by the PACKEN bit in the SPICTL register. These words may be sign extended depending on the SGN bit in the SPICTL register as shown below.
31 SSSSSSSS1 1 Second 8-bit word S S S S S S S S1 First 8-bit word 0

if SGN=1, S is the sign bit. if SGN=0, S is 0.

SPI Operation Modes

The SPI in the ADSP-21161 processor can be used in a single master or multi-master mode. The MOSI, MISO, and the SPICLK signals of all SPI devices are connected together in both modes. The following sections describe the SPI operation as a master and as a slave. Figure 11-2 on page 11-4 shows the master-slave interconnections. The ADSP-21161 processor is intended to be full-duplex. The SPICLK will stall on the transmit buffer becoming empty OR on the receive buffer becoming full. Dummy reads are necessary from the receive buffer even if programs are not interested in the transmitting data.

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Serial Peripheral Interface (SPI)

Master Mode Operation

When SPI is in master mode the interface operates in the following manner: 1. Configure the SPICTL register enabling the device as a master, specifying the appropriate word length, baud rate and any other options needed. 2. The SPI interface sends SPIDS signal to the desired slaves using one or more of the FLAG0-3 pins. For more information, see Automatic Slave Selection on page 11-26. 3. Write a data word to the SPITX data buffer using the core. This starts the SPICLK generation. 4. SPI generates the programmed clock pulses SPICLK and simultaneously shifts data from the transmit shift register (TXSR) out of the MOSI pin and into the receive shift register (RXSR) via the MISO pin. Before starting the shift, TXSR is loaded with the contents of the transmit data buffer register SPITX. At the end of the transfer, the receive data buffer register SPIRX is loaded with the contents of RXSR. 5. For interrupt driven core transfers to or from SPITX or SPIRX, enable bits SPTINT and SPRINT in the SPICTL register. An SPI interrupt occurs when SPITX is partially empty or when SPIRX is partially full. The interrupt service routine then transfers data to or from SPI data buffers. 6. For duplex DMA transfers, enable bits RDMAEN and TDAMEN in SPICTL. DMA requests are generated when SPITX is partially empty or when SPIRX is partially full. The DMA controller then transfers data between internal memory and the SPI data buffers.

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SPI Operation Modes

Interrupt and DMA Driven Transfers For interrupt driven transfers, the SPTINT or SPRINT bit should be set in the SPICTL. The interrupt routine in the user software is expected to perform the data transfer. For DMA driven transfers, the RDMAEN or TDMAEN bits must be set in the SPICTL. The DMA controller does the data transfer automatically. An interrupt is generated at the end of the DMA transfer. For more information on interrupts, see section SPI Interrupts on page 11-8. Interrupts or DMA requests are automatically generated when the transmit buffer is partially empty or when the receive buffer is partially full. In the event that the SPITX and SPIRX interrupts are not serviced, or a higher priority DMA occurs, resulting in the transmit buffer becoming empty or the receive buffer becoming full, the SPI device will stall the SPI clock until all the data is read from the receive buffer or a piece of data is written to the transmit buffer. Core Driven Transfers For core driven SPI transfers, SPTINT and SPRINT are enabled in the SPI, and the corresponding interrupt masks SPIRMSK and SPITMSK are disabled in the LIRPTL register. The user software has to read from or write to SPIRX and SPITX in the transmit buffer becoming empty or the receive buffer becoming full, the SPI device will stall the SPI clock until all the data is read from the receive buffer or a piece of data is written to the transmit buffer. Automatic Slave Selection Multiple slaves are automatically controlled (selected and deselected) during the SPI transfer by enabling the PSSE bit in the SPICTL register. This bit locks all the four flag pins (FLAG0,FLAG1,FLAG2 and FLAG3) as SPI slave selects. By writing to the FLS bits (bits 15-18) in the SPICTL register, the corresponding FLAG bits are programmed as outputs for slave selection.

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Serial Peripheral Interface (SPI)

To enable the different slaves, connect the slave SPIDS pins to the programmable flag pins FLAG0-3 of the master ADSP-21161. Since these flags are NOT open drain, slave select pins (FLAGS) cannot be shorted together in multimaster environment. To control slave selects, an external glue logic is required in a multi-master environment. Enable the SPI port by setting the SPIEN bit in the SPICTL. The masters flag pins are asserted low and the SPIDS signals of the slaves are asserted. Upon completion of the transfer, the FLAG pins are de-asserted, and slave selection is subsequently disabled. During data transfers, if the SPI clock is stalled, the slaves are automatically deselected by de-asserting the flags in the master. Once data transmission becomes possible, the slaves are automatically selected again by asserting the flags in the master. When DCPH0 is set, the slaves are automatically deselected and selected again by de-asserting and asserting the flags in the master. This is done automatically in the SPI. There is a one cycle latency for a flag output to change after writing to the SPICTL register (when PSSE is set and the flag is enabled). To use the PSSE feature, systems can have five SPI devices with ADSP-21161 as the master. The PSSE is programmed for slave selection of the other four devices. The ADSP-21161 processor can broadcast to all the four slaves at once or can write to individual slaves by appropriately programming the FLS bits. User Controlled Slave Selection The user can also control the slaves without enabling the PSSE bit in the SPI. The user can set or clear the I/O flags directly by writing a 1 or 0 into the FLAG register. The user can also emulate DCPH0 operation by setting or clearing the values in the FLAG register at the appropriate time.

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SPI Operation Modes

When using this mode, the following sequence should be followed to ensure proper data transfer according to the SPI protocol. 1. Enable the SPI by writing into the SPICTL register. 2. Assert the required slave select by writing a zero into the appropriate bit in the FLAG register. 3. Load SPITX with the required data by enabling DMAs, interrupts, or by performing core writes to SPITX.

Slave Mode Operation

To prepare for the data transfer, a slave processor writes the data to be transmitted into the transmit data buffer. The following steps illustrate SPI operation in slave mode. 1. Configure the SPICTL register enabling the device as a slave and specifying the appropriate word length and any other options needed to be compatible with the master device. 2. Once the core receives the SPIDS signal from the master, it starts sending or receiving data on the proper SPICLK edge. 3. Reception/transmission continues until SPIDS is negated. 4. SPI receives the programmed clock pulses SPICLK and shifts data out of MISO and in from MOSI. Before starting the shift, the transmit shift register (TXSR) is loaded with the contents of the transmit data buffer register SPITX. At the end of the transfer, the receive data buffer register SPIRX is loaded with the contents of the receive shift register (RXSR).

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Serial Peripheral Interface (SPI)

5. For interrupt driven core transfers to or from SPITX or SPIRX, enable bits SPTINT and SPRINT in the SPICTL register. An SPI interrupt occurs when SPITX is partially empty or when the receive buffer SPIRX is partially full. 6. For duplex DMA transfers, enable RDMAEN and TDAMEN in SPICTL need. DMA requests are generated when SPITX is partially empty or when SPIRX is partially full. The DMA controller then transfers data between internal memory and the SPI data buffers. Interrupts and DMA requests are automatically generated when the transmit buffer is partially empty or when the receive buffer is partially full. In case of DMA driven or core driven transfers, if the transmit buffer becomes empty or the receive buffer becomes full, the SPI device continues to operate based on the conditions of the SENDLW and GM bits. If the SENDLW bit is cleared (=0) and the transmit buffer is empty, the device repeatedly transmits 0s out on the MISO pin. If the SENDLW is set (=1) and the transmit buffer is empty, the device continues to transmit the last word written to SPITX that was transmitted. Retransmission of the data in SPITX occurs after the transmit buffer becomes empty. If the GM bit is set (=1) and the receive buffer is full, the device continues to receive new data from the MOSI pin, overwriting the previous (older) data in the SPIRX buffer. If the GM bit is reset (=0) and the receive buffer is full, the incoming data from the shift register is discarded and the SPIRX register is not updated. The register ignores the new data and retains the old information.

Error Signals and Flags

Please refer to the SPISTAT register definitions in Table 11-3 on page 11-17 for the following discussion. Note that the functionality of some bits differ in revisions prior to 1.2. These difference are described in Table 11-3.

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Error Signals and Flags

Multi-Master Error (MME)

The MME bit is set (=1) in the SPISTAT register when the SPIDS pin of a master ADSP-21161 processor is driven low by another device in the system. This occurs when another device is trying to be the master. This can cause contention between two drivers and push-pull CMOS drivers. When this error is detected, the following actions take place: 1. The MS control bit in SPICTL is cleared (= 0), configuring the SPI interface as a slave. 2. The SPIEN bit in SPICTL is also cleared, disabling the SPI system. 3. The MME status bit in SPISTAT is set. This bit can be polled to test whether this error condition has occurred.

Transmission Error (TXE)

For revisions 1.1 and earlier, this error bit is updated only when SPTINT or TDAMEN is enabled. This bit is set in the SPISTAT register when SPI is enabled and there is no data in the transmit data buffer (SPITX). This is true in both master and slave SPI devices. When the device is an SPI master, upon setting the error bit, the data in the transmit shift register (TXSR) is transmitted out. Then, the SPICLK is stalled automatically until new data is written into the SPITX data buffer. When the device is an SPI slave, upon setting the error bit, the data is still transmitted as specified by the SENDLW bit in the SPICTL register. The TXE bit is cleared (=0) only when SPIEN is disabled. For revisions 1.2 and later, this error bit is updated during any SPI transfer. This bit is set in the SPISTAT register when SPI is enabled and there is no data in SPITX and in TXSR. This is true in both master and slave SPI devices.

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Serial Peripheral Interface (SPI)

When the device is an SPI master, the working of the bit depends on the mode of data transfer. For DMA or interrupt driven data transfer, the SPICLK will stall as soon as both the SPITX and the TXSR become empty. There is NO transmission error in this case. For core driven data transfers, the error bit is set as soon as both the SPITX and the TXSR become empty. The SPI continues to transmit the next data as specified by the SENDLW bit in the SPICTL register.

Reception Error (RBSY)

For revisions 1.1 and earlier, this error bit is updated only when SPRINT or RDAMEN is enabled. This bit is set in the SPISTAT register when SPI is enabled and there is no space in the receive data buffer (SPIRX). This is true in both master and slave SPI devices. When the device is an SPI master, upon setting the error bit, one more data is fully received in the receive shift register (RXSR). Then, the SPICLK is stalled automatically until a data has been read out of the SPIRX data buffer. When the device is an SPI slave, upon setting the error bit, the data is still received as specified by the GM bit in the SPICTL. The RBSY bit is cleared (=0) only when SPIEN is disabled. For revisions 1.2 and later, this error bit is updated during all SPI data transfers. This bit is set in the SPISTAT register when SPI is enabled and there is no space in the SPIRX and in RXSR. This is true in both master and slave SPI devices. When the device is an SPI master, the working of the bit depends on upon the type of data transfer. For DMA or interrupt driven data transfer, the SPICLK is stalled as soon as the SPIRX becomes full. There is NO reception error in this case. For core driven data transfers, this error bit is set as soon as both the SPIRX and the RXSR become completely full. The next data is still received as specified by the GM bit in the SPICTL.

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SPI/Link Port DMA

SPI/Link Port DMA

The SPI shares DMA channels 8 and 9 with the link port. The receive DMA is shared with link port 0 DMA, and the transmit DMA is shared with link port 1 DMA. Do not enable SPI and link port DMA simultaneously. SPI and link port are mutually exclusive when one of the peripherals is enabled. SPI DMAs have higher priority than link port DMAs. If SPI DMAs must be enabled, disable link port DMAs and pending link port DMA requests. For more information, see SPI Port DMA on page 6-108.

DMA Operation in SPI Master Mode

For transmit DMA operations, if the DMA controller is unable to keep up with the transmit stream, due perhaps to heavy DMA channel activity, the data in the transmit shift register (TXSR) is transmitted out. Then the SPICLK is stalled automatically until a new data is written into the SPITX data buffer. For receive DMA operations, if the DMA controller is unable to keep up with the receive data stream, the receive buffer operates according to the state of the GM bit. If GM is set (=1) and the receive buffer is full, one more data is fully received in the receive shift register (RXSR). Then, the SPICLK is stalled automatically until data has been read out of the SPIRX data buffer.

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Serial Peripheral Interface (SPI)

Do not perform a normal core write of SPITX during DMA operation. A normal core read of SPITX can be done at any time and does not interfere with, or initiate, SPI transfers. Do not perform a normal core read of SPIRX during DMA operation. A normal core write of SPIRX can be done at any time and does not interfere with, or initiate, SPI transfers. Interrupts are generated based on DMA events that are configured in the SPICTL register.

DMA Operation in Slave Mode

When the DMA controller transmits or receives data in slave mode, the start of a transfer is triggered by a transition of the SPIDS signal to the active-low state or by the first active edge of SPICLK. For transmit DMA operations, if the DMA engine is unable to keep up with the transmit stream, the transmit port operates according to the state of the SENDLW bit. Once the transmit buffer is empty and the last word has been transmitted completely out of the TXSR, if SENDLW is cleared (=0), the device repeatedly transmits 0s on the MISO pin. If SENDLW is set (=1), it repeatedly transmits the last word transmitted before the transmit buffer became empty. For receive DMA operations, if the DMA controller is unable to keep up with the receive data stream, the receive buffer operates according to the state of the GM bit. If GM is set (=1) and the receive buffer is full, one more data is fully received in the receive shift register (RXSR). The SPICLK is stalled automatically until a data has been read out of the SPIRX data buffer.

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SPI Booting

Do not perform a normal core write of SPITX during DMA operation. A normal core read of SPITX can be done at any time and does not interfere with, or initiate, SPI transfers. Do not perform a normal core read of SPIRX during DMA operation. A normal core write of SPIRX can be done at any time and does not interfere with, or initiate, SPI transfers.

SPI Booting
The ADSP-21161 processor allows a host SPI device to boot the processor on power-up RESET de-assertion. To enable the SPI booting mode, the EBOOT and BMS pins must be tied low, and the LBOOT pin must be tied high. When the processor comes out of reset, it starts the SPI boot process. The SPI is configured as a slave upon power-up. Therefore, after reset, the SPI waits for SPIDS and SPICLK from the SPI host to download the boot program. The default value of the SPICTL register when the processor is configured for SPI boot is 0x0A00 1F81. The SPI port is enabled as a slave to receive 32-bit words in LSB-first format. DMA is enabled to facilitate loading the boot kernel. The DMISO bit is also enabled to avoid contention in the MISO pin in systems where multiple slave devices are to be booted simultaneously. DMA channel 8 is used when downloading the boot kernel information to the processor. At reset, the DMA parameter registers for DMA channel 8 are initialized to their required values. Table 11-5 lists the initial values for these registers. The ADSP-21161 SPI booting mode supports boots from 8-, 16-, or 32-bit host SPI devices. In SPI boot mode, the data word size in the shift register defaults to 32 bits. Therefore, for 8- or 16-bit hosts, data words are packed into the shift register to generate 32-bit words, which can be shifted into internal program memory. 11-34 ADSP-21161 SHARC Processor Hardware Reference

Serial Peripheral Interface (SPI)

Table 11-5. Parameter Initialization Value

Parameter Register IISRX IMSRX CSRX GPSRX Initialization Value 0x0004 0000 0x0000 0001 0x0000 0180 uninitialized

The host initiates the booting operation by activating SPICLK and asserting the SPIDS signal to the active low state. The 256-word, boot-strapped instruction loader kernel is loaded 32 bits at a time, via the 32-bit SPI receive shift register (RXSR). To properly upload 256 instructions (48-bit words), the SPI DMA initially loads a DMA count of 0x180 (384) 32-bit words which is equivalent to 0x100 (256) 48-bit words. The relationship between the 32-bit words received into the SPIRX register and the instructions that need to be placed in internal memory is described in the Figure 11-9. After the first 256 words are loaded the interrupt associated with the SPI receive is activated. The processor jumps to the location for SPIRI_svc (0x40040) and executes the code located there. Typically, the first instruction at the SPI receive interrupt vector (SPIRI) is an RTI instruction in which case the processor jumps to location 0x40005 where normal program execution continues. Because most applications require more than 256 words of instructions and initialization data, a loader and a 256 word loader kernel are supplied with the tools. Use these tools to create code that automatically loads the rest of the application code and then overwrites itself with application code and data. For more information on the loader, see the development tools documentation. The boot loader kernel supplied with the tools loads a combination of instructions with DMA into scratch locations and then writes the instructions to internal memory using the core via the PX register. The 256-word, boot-strapped instruction loader kernel is loaded 32-bits at a time, via the

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SPI Booting

32-bit SPI receive shift register, using a normal-word addressing scheme with two-column memory addresses. Figure 11-9 shows how SPI data is packed in internal memory.
32-Bit receive SHIFT REGISTER

#384:DM[0x4017F] #384:DM[0x4017E] 0x400FF MSW LSW MSW LSW PM48 [0x400FF] [x400FE]

S P I R X

DMA (channel 8)

DMA #6: DM[40005] DMA #5: DM[40004] MSW LSW MSW LSW PM48 [0x40003] [x40002] DMA #4: DM[40003] DMA #3: DM[40002] MSW LSW MSW LSW PM48 [0x40002] PM48 [0x40001]

256 48-bit words

DMA #2: DM[40001] DMA #1: DM[40000] MSW LSW MSW LSW UW PM48 [0x40000] LW [x40001] 0x40000 MOSI

1
16

Figure 11-9. SPI Data Packing The SPI Control Register (SPICTL) is configured to 0x0A00 1F81 upon reset during SPI boot. SPI transfers occur with the following default bit settings:
SPIEN MS DF WL

= 1, SPI enabled

= 0, slave device = 0, LSB first = 11, 32-bit SPI receive shift register word length = 1, MISO disabled = 1, Receive DMA enabled

DMISO

RDMAEN

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Serial Peripheral Interface (SPI)

The SPIRX DMA channel 8 parameter registers are configured to DMA in 0x180 32-bit words into internal memory normal-word address space starting at 0x40000. Once the 32-bit DMA completes, the data is then accessed as 3-column 48-bit instruction accesses, for example, the processor executes a 256 (0x100) word loader kernel upon completion of the 32-bit, 0x180 word DMA. For 16-bit SPI hosts, two words are shifted into the 32-bit receive shift register ( RXSR) before a DMA transfer to internal memory occurs. For 8-bit SPI hosts, four words are shifted into the 32-bit receive shift register before a DMA transfer to internal memory occurs. By default, the booting SPI expects to receive words into SPIRX seemlessly. This means that bits are received continuously without breaks. For different SPI host sizes, the processor expects to receive instructions and data packed in an LSW format. Figure 11-10 shows a pair of instructions packed for SPI booting using a 32-, 16-, and an 8-bit host.
Words 32-bit host 16-bit host 8-bit host
33445566 5566 3344 CCDD1122 1122 CCDD 7788AABB AABB BB AA 7788

Instructions In Internal Memory [0x40000] 1122 33445566 [0x40001] 7788 AABBCCDD

66

55

44

33

22

11

DD

CC

88

77

Figure 11-10. Instruction Packing for 32-, 16-, or 8-Bit SPI Host Booting The following sections examine how data is packed into internal memory during SPI booting for SPI host word widths of 32-, 16-, or 8-bits.

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SPI Booting

32-Bit SPI Host Boot

Figure 11-11 shows 32-bit SPI host packing of 48-bit instructions. The 32-bit word is shifted to internal program memory during loading of the 256-word kernel.

0x40000
32-bit SPI WORD N

32

S P I R X

32

DMA Channel 8

32

Internal Memory (Loader Kernel) 0x400FF

MOSI

Figure 11-11. 32-Bit SPI Host Packing

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Serial Peripheral Interface (SPI)

The following is an example of 48-bit instructions to be executed at PM addresses 0x40000 and 0x40001: [0x40000] 1122 33445566 [0x40001] 7788 AABBCCDD The 32-bit SPI host would need to pack (prearrange data) as follows: SPI word 1 = 0x33445566 SPI word 2 = 0xCCDD1122 SPI word 3 = 0x7788AABB

16-Bit SPI Host Boot

Figure 11-12 shows 16-bit SPI host packing of 48-bit instructions. For 16-bit hosts, two 16-bit words are packed into the shift register to generate a 32-bit word. The 32-bit word is shifted to internal program memory during loading of the kernel.

WORD N

16- bit

0x40000 S P I R X Internal Memory

32

32

DMA Channel 8

32

WORD N + 1

(Loader Kernel) 0x400FF

MOSI

Figure 11-12. 16-Bit SPI Host Packing

ADSP-21161 SHARC Processor Hardware Reference

16- bit

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SPI Booting

The following is an example of 48-bit instructions to be executed at PM addresses 0x40000 and 0x40001: [0x40000] 1122 33445566 [0x40001] 7788 AABBCCDD The 16-bit SPI host would need to pack (prearrange data) as follows: SPI word 1 = 0x5566 SPI word 2 = 0x3344 SPI word 3 = 0x1122 SPI word 4 = 0xCCDD SPI word 5 = 0xAABB SPI word 6 = 0x7788 The initial boot of the 256-word loader kernel requires a 16-bit host to transmit 768 16-bit words. One 32-bit word is created from two packed 16-bit words. The SPI DMA count value of 0x180 is equivalent to 384 words. Therefore, the total number of 16-bit words loaded is 768.

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Serial Peripheral Interface (SPI)

8-Bit SPI Host Boot

Figure 11-13 shows 8-bit SPI host packing. For 8-bit hosts, four 8-bit words are packed into the shift register to generate a 32-bit word. The 32-bit word is then shifted to internal program memory during loading of the 256-instruction word kernel.

8-bit WORD N

8-bit WORD N+1

0x40000 S P I R X Internal Memory (Loader Kernel) 0x400FF

32

32

DMA Channel 8

32

Figure 11-13. 8-Bit SPI Host Packing The following is an example of 48-bit instructions to be executed at PM addresses 0x40000 and 0x40001: [0x40000] 1122 33445566 [0x40001] 7788 AABBCCDD

ADSP-21161 SHARC Processor Hardware Reference

8-bit WORD N+3

8-bit WORD N+2

MOSI

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SPI Booting

The 8-bit SPI host would need to pack (prearrange data) as follows: SPI word 1 = 0x66 SPI word 2 = 0x55 SPI word 3 = 0x44 SPI word 4 = 0x33 SPI word 5 = 0x22 SPI word 6 = 0x11 SPI word 7= 0xDD SPI word 8 = 0xCC SPI word 9 = 0xBB SPI word 10 = 0xAA SPI word 11 = 0x88 SPI word 12 = 0x77 The initial boot of the 256-word loader kernel requires an 8-bit host to transmit 1536 8-bit words. The SPI DMA count value of 0x180 is equal to 384 words. Since one 32-bit word is created from four packed 8-bit words, the total number of 8-bit words transmitted is 1536. Multiprocessor SPI Port Booting In systems where multiple ADSP-21161 processors are connected and configured for SPI booting, the master ADSP-21161 (or any SPI master device) can boot up to four processors configured as SPI slaves. The processor uses four programmable flags, FLAG0-3, as dedicated SPI device-select signals for the SPI slave devices. The FLS bits in the SPICTL register correspond to these flags. Figure 11-14 shows a single ADSP-21161 processor master with four slaves. The master processor selects each slave device using a dedicated FLAG pin. The master device communicates with one slave device at any given time, or it broadcasts data to multiple slaves by setting more than one FLS bit in SPICTL.

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Serial Peripheral Interface (SPI)

Slave Device
MISO SPICLK MOSI SPIDS MISO SPICLK

Slave Device
MOSI SPIDS MISO SPICLK

Slave Device
MOSI SPIDS MISO

Slave Device
SPICLK MOSI SPIDS

VDD

MISO FLAG1 FLAG2

SPICLK MOSI

SPIDS FLAG3

ASP-21161
SINGLE MASTER DEVICE

FLAG0

Figure 11-14. Single Master, Multiple Slaves Configuration All ADSP-21161 Processors The master ADSP-21161 processor can boot multiple slaves in the following ways: The ADSP-21161 processor transmits to all four SPI devices at the same time in a broadcast mode. Broadcast the 256-word loader kernel and identical application code simultaneously to all slaves. If the master is a ADSP-21161 processor, enable the FLSx bit in the SPICTL register, and disable the MISO pins. Otherwise, the master asserts the SPIDS pins of all the slaves to transmit the data. This feature can be enabled by setting the DMISO bit in the four slave processors. This DMISO feature may be available in some microcontrollers. Therefore, it is possible to use the DMISO feature with any SPI devices that include this functionality.

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SPI Programming Example

Load the bootstrap kernel and processor instructions and data one-at-a time for each processor. In this case, enable only one FLSx bit at a time in the SPICTL register to drive the flag pin connected to a slaves device select. The master device will assert the SPIDS pin of the slave to load the data. This ensures that each processor boots one after the other. It is also possible to use a combination of broadcast and individual processor booting to boot a multiprocessor system. SPI hosts can broadcast boot application code that will reside on several slaves and then complete the booting process by booting the individual slaves with slave specific application code. In this situation, the host SPI device asserts the SPIDS pins of all slaves during the broadcast portion of the boot. The host then asserts the SPIDS pins of specific slaves. If the ADSP-21161 processor is the master as is shown in Figure 11-14, the master enables the FLSx bit in the SPICTL register for the slave currently booting. Figure 11-14 shows one ADSP-21161 processor as a master and four ADSP-21161 processor (or other SPI-compatible devices) as slaves:

SPI Programming Example

This section provides two programming examples written for the ADSP-21161 processor. The core-driven interrupt SPI loopback example in Listing 11-1 demonstrates how the core reads from the SPI receive buffer and writes to the SPI transmit buffer after receiving an interrupt. The core-driven interrupt SPI loopback without interrupts example in Listing 11-2 demonstrates how the core reads from the SPI receive buffer and writes to the SPI transmit buffer after polling the buffer status. For an SPI DMA programming example, see Listing 6-7 on page 6-116.

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Serial Peripheral Interface (SPI)

Listing 11-1. Core-Driven Interrupt SPI Loopback

/*______________________________________________________________ ADSP-21161 Core-Driven Interrupt SPI Loopback Example This example shows looped-back SPI 32-bit transfer. On this peripheral loop-back is preformed by externally connecting the hardware MOSI and MISO pins on the processor. After receiving an interrupt, the core directly writes to the transfer buffer (SPITX) and reads from the receive buffer (SPIRX). Hardware loop-back does not require the use of flags as device selects so the FLS bits do not need to be used as they would in an SPI transfer between two different SPI devices (non-loop-back.) _____________________________________________________________*/ #include <def21161.h> #define size 10 // reserved vector location .section/pm seg_rsvd1; Reserved_1: rti; nop; nop; nop;

// vector code for reset vector from ldf file .section/pm Chip_Reset: seg_rth; idle; jump start; nop; nop;

// vector code for receive interrupt vector from ldf file .section/pm spiri_svc; nop; nop; jump receive; rti; .section/dmseg_dmda; .var spi_tx_buf[size] =0x11111111,0x22222222, 0x33333333, 0x44444444, 0x55555555,0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xaaaaaaaa; .var spi_rx_buf[size]; .section/pm seg_pmco;

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SPI Programming Example

start: //Set pointers for source and dest, I0=B0 automatically b0=spi_tx_buf; l0=@spi_tx_buf; m0=1; b1=spi_rx_buf; l1=@spi_rx_buf; m1=1; // set circular buffer enable and allow global interrupts bit set MODE1 CBUFEN | IRPTEN; bit set LIRPTL SPIRMSK ; bit set IMASK LPISUMI; r0=0x00000000; dm(SPICTL)=r0; // prime SPITX register r0=dm(i0,m0); dm(SPITX)=r0; ustat1=dm(SPICTL); bit set ustat1 | BAUDR5 | SGN | GM; /* Enable spi port, spitx and spirx interrupts, master device spiclk toggles at beginning of first data transfer bit, MSB first format, 32 bit word length, baud rate sign extend and get more new data even if receive buffer is full */ dm(SPICTL) = ustat1; // start transfer by configuring SPICTL // set up options for the SPI port // enable SPI RX interrupts // unmask spi interrupts // initially clear SPI control register // 32-bit SPI datawords // 32-bit SPI datawords

SPIEN | SPRINT | SPTINT | MS | CPHASE | DF | WL32

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ADSP-21161 SHARC Processor Hardware Reference

Serial Peripheral Interface (SPI)

wait: idle;jump wait; receive: r0=dm(SPIRX); dm(i1,m1)=r0; r0=dm(i0,m0); //read SPIRX

//write value to internal memory buffer //get new value to transmit from internal // transmit buffer

dm(SPITX)=r0;//write value to SPITX rti;

Listing 11-2. Core-Driven Interrupt SPI Loopback Without Interrupts

/* ADSP-21161 Core-Driven Interrupt SPI Loopback without InterruptsThis examples shows a looped-back SPI 32-bit transfer. the hardware MOSI and MISO pins on the processor. Hardware On this peripheral loop-back is performed by externally connecting loop-back doesnot require the use of flags as device selects so the FLS bits do not need to be used as they would in an SPI transfer between two different SPI devices (non-loop-back.) In this example, interruptsare not used to determine buffer status, instead polling of the buffer status is implemented to allow the code to know when it can Rev 1.1 1/22/02 */ safely read from the SPIRX register.

#include <def21161.h> #define size 10 // vector code for reset vector from ldf file .section/pm Chip_Reset: seg_rth; idle; jump start; nop; nop;

.SECTION/DM seg_dmda; .var spi_tx_buf[size] =0x11111111, 0x22222222,

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SPI Programming Example

0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xaaaaaaaa; .var spi_rx_buf[size]; .SECTION/PM seg_pmco; start: bit set MODE1 IRPTEN | CBUFEN;// set circular buffer enable and allow global interrupts b0=spi_tx_buf; // 32-bit SPI datawords l0=@spi_tx_buf; m0=1; b1=spi_rx_buf; // 32-bit SPI datawords l1=@spi_rx_buf; m1=1; r0=0x00000000;// initially clear SPI control register dm(SPICTL)=r0; ustat1=dm(SPICTL); bit set ustat1 SPIEN | MS | DF | WL32 | BAUDR5 | SGN | GM;

/* The SPI transmit buffer must be fed with the first two data words before enabling SPI if SPRINT/SPTINT will not be enabled for interrupt usage */ r0=dm(i0,m0); dm(SPITX)=r0; //write to TX buffer

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Serial Peripheral Interface (SPI)

r0=dm(i0,m0); dm(SPITX)=r0; //write to TX buffer //enable port

dm(SPICTL) = ustat1;

lcntr = 0x8, do looping until lce; r0=dm(i0,m0); dm(SPITX)=r0; // test receive buffer status to determine when it is ok to read from SPIRX test:ustat1=dm(SPISTAT); bit tst USTAT1 RXS0; if Not TF jump test; r0=dm(SPIRX); dm(i1,m1)=r0; looping: nop; r0=dm(SPIRX); dm(i1,m1)=r0; r0=dm(SPIRX); dm(i1,m1)=r0; wait: jump wait; idle; //read from RX buffer //read from RX buffer //read from RX buffer //write to TX buffer

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SPI Programming Example

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12 JTAG TEST-EMULATION PORT

A boundary scan allows a system designer to test interconnections on a printed circuit board with minimal test-specific hardware. The scan is made possible by the ability to control and monitor each input and output pin on each chip through a set of serially scannable latches. Each input and output is connected to a latch, and the latches are connected as a long shift register so that data can be read from or written to them through a serial test access port (TAP). The ADSP-21161 processor contains a test access port compatible with the industry-standard IEEE 1149.1 (JTAG) specification. Only the IEEE 1149.1 features specific to the ADSP-21161 processor are described here. For more information, see the IEEE 1149.1 specification and other the documents listed in References on page 12-29. The boundary scan allows a variety of functions to be performed on each input and output signal of the ADSP-21161 processor. Each input has a latch that monitors the value of the incoming signal and can also drive data into the chip in place of the incoming value. Similarly, each output has a latch that monitors the outgoing signal and can also drive the output in place of the outgoing value. For bidirectional pins, the combination of input and output functions is available. Every latch associated with a pin is part of a single serial shift register path. Each latch is a master/slave type latch with the controlling clock provided externally. This clock (TCK) is asynchronous to the ADSP-21161 processor system clock (CLKIN).

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12-1

The ADSP-21161 processor emulation features halt the processor at a pre-defined point to examine the state of the processor, execute arbitrary code, restore the original state, and continue execution. The ADSP-21161 processor emulation features are a superset of the ADSP-21160 emulation features. All emulation features supported by previous SHARCs are supported on the ADSP-21161 processor, except the ICSA output signal and function. The set of features on which JTAG ICE designs rely are supported in an identical fashion on ADSP-21161 processor. The ADSP-21161 processor can be used with the ADSP-2106x SHARC JTAG ICE hardware. There are several changes/extensions to the base functionality of the ADSP-2106x emulation capability, which require changes in the JTAG ICE software for ADSP-21161 processor support. These extensions include: 1. The emulation breakpoint address start/end registers have moved from UREG space to IOP register space. This change did not effect the TSTEMU block directly, only the address decodes to gain access to it. 2. has been added to the IR decode space. This shift register provides access to the full 64-bit wide PX register of ADSP-21161 processor.
EMU64PX

3. A memory test shift register has been added to the IR decode space. This feature is for Analog Devices internal use ONLY. Several on-chip facilities are directly accessed through the JTAG interface. These facilities are listed in Table 12-2 on page 12-4. Other emulation facilities are only indirectly accessible. To indirectly access the facilities that do not appear in Table 12-2 on page 12-4, scan the instruction which moves data of interest to/from the PX register, scan the PX data (if the instruction is a PX read), let the core execute the instruction, then scan the PX register out (if the instruction was a PX write). 12-2 ADSP-21161 SHARC Processor Hardware Reference

JTAG Test-Emulation Port

The breakpoint start/end registers are mapped into the IOP register space of the ADSP-21161 processor. For specific addresses, see Register and Bit #Defines (def21161.h) on page A-121. The EMUN, EMUCLK, and EMUCLK2 registers occupy the same UREG address space as on the ADSP-2106x. These facilities are read-only by the ADSP-21161 processor core in normal operation.

JTAG Test Access Port

The emulator uses JTAG boundary scan logic for ADSP-21161 processor communications and control. This JTAG logic consists of a state machine, a five pin Test Access Port (TAP), and shift registers. The state machine and pins conform to the IEEE 1149.1 specification. The TAP pins appear in Table 12-1. A special pin (EMU) is used by Analog Devices Inc. JTAG emulators. and is not defined in the IEEE-1149.1 specification. This signal notifies the JTAG ICE that the processor has completed an operation. Table 12-1. JTAG Test Access Port (TAP) Pins
Pin TCK TMS TDI TDO TRST 1 2 Function (input) Test Clock: pin used to clock the TAP state machine.1 (input) Test Mode Select: pin used to control the TAP state machine sequence.2 (input) Test Data In: serial shift data input pin. (output) Test Data Out: serial shift data output pin. (input) Test Logic Reset: resets the TAP state machine

Asynchronous with CLKIN Synchronous to CLKIN

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Instruction Register

A Boundary Scan Description language (BSDL) file for the ADSP-21161 processor is available on Analog Devices website. Set your browser to:
http://www.analog.com/techsupt/documents/bsdl

Refer to the IEEE 1149.1 JTAG specification for detailed information on the JTAG interface. The many sections of this appendix assume a working knowledge of the JTAG specification.

Instruction Register
The instruction register allows an instruction to be shifted into the processor. This instruction selects the test to be performed and/or the test data register to be accessed. The instruction register is 5 bits long with no parity bit. A value of 10000 binary is loaded (LSB nearest TDO) into the instruction register whenever the TAP reset state is entered. Table 12-2 lists the binary code for each instruction. Bit 0 is nearest TDO and bit 4 is nearest TDI. No data registers are placed into test modes by any of the public instructions. The instructions affect the ADSP-21161 processor as defined in the 1149.1 specification. The optional instructions RUNBIST, IDCODE and USERCODE are not supported by the ADSP-21161 processor. Table 12-2. JTAG Instruction Register Codes
43210 11111 00000 10000 01000 11000 00100 Register Bypass Boundary Boundary EMUPMD Boundary EMUCTL Instruction BYPASS EXTEST SAMPLE EMULATION INTEST EMULATION 48-bit scan length Comment Type Public Public Public Private Public Private

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JTAG Test-Emulation Port

Table 12-2. JTAG Instruction Register Codes (Contd)

43210 10100 10110 01100 11100 00010 10101 All others Register EMUPX EMU64PX EMUSTAT BRKSTAT EMUPC MEMTST Reserved Instruction EMULATION EMULATION EMULATION EMULATION EMULATION TEST Reserved Memory test Comment 48-bit shift register 64-bit shift register Type Private Private Private Private Private Private Private

The entry under Register is the serial scan path, either Boundary or Bypass in this case, enabled by the instruction. Figure 12-1 shows these register paths. The 1-bit Bypass register is fully defined in the 1149.1 specification. For more information on the Boundary register, see Boundary Register on page 12-17. No special values need be written into any register prior to selection of any instruction. As Table 12-2 shows, certain instructions are reserved for emulator use. For more information, see Table 12-7.

EMUPMD Shift Register

The EMUPMD serial shift register is located in the system unit. EMUPMD is 48 bits wide and is accessed by the emulator through TAP. When the TAP enters the UPDATE state and EMUPMD is selected, a 48-bit slave register is updated from this register. The EMUPMD register is used to force the ADSP-21161 processor to execute emulator supplied instructions. The register accomplishes this by driving the instruction bus while in emulation space.

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Instruction Register

BOUNDARY REGISTER 478 479 2 1 0 BYPASS REGISTER TDI 1 TDO

480

3 2

INSTRUCTION REGISTER

Figure 12-1. Serial Scan Paths

EMUPX Shift Register

The EMUPX serial shift register is located in the system unit. The EMUPX register is 48 bits wide and is accessed by the emulator through the TAP. When the TAP goes into the UPDATE state and EMUPX is selected, the most significant 48-bits of PX is updated from EMUPX. When the TAP goes

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JTAG Test-Emulation Port

into the CAPTURE state and EMUPX is selected, EMUPX is updated with the most significant 48-bits of PX. The EMUPX register is used to transfer data between the emulator and the target system. The EMUPX register is provided for backwards compatibility with the SHARC ICE hardware and is 64 bits wide. To provide compatibility, only the most significant 48 bits of PX are mapped to EMUPX. 48-bit instructions, and 40-bit extended precision data, are always aligned to the most significant bit. When transferring 32-bit data to/from PX register, PX2 must be specified as the source/destination to ensure that the 32-bits is aligned to the most significant bit.

EMU64PX Shift Register

The EMU64PX serial shift register is located in the system unit. The EMU64PX register is 64 bits wide and is accessed by the emulator through the TAP. When the TAP goes into the UPDATE state and EMU64PX is selected, PX is updated from EMU64PX. When the TAP goes into the CAPTURE state and EMU64PX is selected, EMU64PX is updated from PX. The EMU64PX register transfers data between the emulator and the target system. The most significant 48-bits of EMU64PX are redundantly available in EMUPX.

EMUPC Shift Register

The EMUPC serial shift register is located in the system unit. The EMUPC register is 24 bits wide and is accessed by the emulator through the TAP. It captures addresses from the PC register. This data can be used to statistically profile the users code. Addresses cannot be forced into the PC register from the EMUPC register.

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Instruction Register

EMUCTL Shift Register

The EMUCTL serial shift register is located in the system unit. The EMUCTL register is 40 bits wide and is accessed by the emulator through the TAP. It controls all of the ADSP-21161 processor emulation functionality. Table 12-3 lists this registers bits and describes their function. Table 12-3. Emulation Control Register (EMUCTL) Definition
Bit # 0 Name EMUENA Function Emulator Function Enable. The EMUENA bit enables ADSP-21161 processor emulation functions. (0=ignore breakpoints and emulator interrupts, 1=respond to breakpoints and emulator interrupts) Emulator Interrupt Enable. The EIRQENA bit enables the emulation logic to recognize external emulator interrupts. (0=disable, 1=enable) Enable Autostop on Breakpoint. The BKSTOP bit enables the ADSP-21161 processor to generate an external emulator interrupt when any breakpoint event occurs. (0=disable, 1=enable) Enable Single Step Mode. The SS bit enables single-step operation. (0=disable, 1=enable) Software Reset of the ADSP-21161 processor. The SYSRST bit resets the ADSP-21161 processor in the same manner as the external RESET pin. The SYSRST bit must be cleared by the emulator. (0=normal operation, 1=reset) Enable the BRKOUT pin. The ENBRKOUT bit enables the BRKOUT pin operation. (0=BRKOUT pin at high-impedance state, 1=BRKOUT pin enabled)

EIRQENA

BKSTOP

3 4

SS SYSRST

ENBRKOUT

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JTAG Test-Emulation Port

Table 12-3. Emulation Control Register (EMUCTL) Definition (Contd)

Bit # 6 Name IOSTOP Function Stop IOP DMAs in EMU space. The IOSTOP bit disables all DMA requests when the DSP is in emulation space. Data that is currently in the EP, LINK, or SPORT DMA buffers is held there unless the internal DMA request was already granted. IOSTOP causes incoming data to be held off and outgoing data to cease. Because SPORT receive data cannot be held off, it is lost and the overrun bit is set. The direct write buffer (internal memory write) and the EP pad buffer are allowed to flush any remaining data to internal memory. (0=IO continues, 1=IO Stops) Stop I/O Processor EP operation in emulation space. The EPSTOP bit disables all EP requests when the DSP is in emulation space. After an emulation interrupt is acknowledged, EPSTOP deasserts ACK (deasserts REDY if host access) to prevent further data from being accepted if the EP is accessed. The emulator may clear this bitallowing I/O to continue and the bus to clearso that the emulator may use the EP (through BR and bus lock). Note that the EP bus clears only if accesses are direct writes or IOP register writes, because all other IOP functions are halted. The EP bus does not clear if accesses to any of the DMA buffers are extended due to a buffer full or empty condition. (0=EP IO continues, 1=EP IO Stops) Negate program memory data address breakpoint. The NEG* bits enable breakpoint events if the address is greater than the end register value OR less than the start register value. This function is useful to detect index range violations in user code. (0=disable breakpoint, 1=enable breakpoint) Negate data memory address breakpoint #1. For more information, see NEGPA1 bit description. Negate data memory address breakpoint #2. For more information, see NEGPA1 bit description. Negate instruction address breakpoint #1. For more information, see NEGPA1 bit description. Negate instruction address breakpoint #2. For more information, see NEGPA1 bit description.

EPSTOP

NEGPA1

9 10 11 12

NEGDA1 NEGDA2 NEGIA1 NEGIA2

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Instruction Register

Table 12-3. Emulation Control Register (EMUCTL) Definition (Contd)

Bit # 13 14 15 16 17 Name NEGIA3 NEGIA4 NEGIO1 NEGEP1 ENBPA Function Negate instruction address breakpoint #3. For more information, see NEGPA1 bit description. Negate instruction address breakpoint #4. For more information, see NEGPA1 bit description. Negate I/O address breakpoint. For more information, see NEGPA1 bit description. Negate EP address breakpoint. For more information, see NEGPA1 bit description. Enable program memory data address breakpoints. The ENB* bits enable each breakpoint group. Note that when the ANDBKP bit is set, breakpoint types not involved in the generation of the effective breakpoint must be disabled. (0=disable breakpoints, 1=enable breakpoints) Enable data memory address breakpoints. For more information, see ENBPA bit description. Enable instruction address breakpoints. For more information, see ENBPA bit description. Enable I/O address breakpoint. For more information, see ENBPA bit description. Enable external port address breakpoint. For more information, see ENBPA bit description. PA1 breakpoint triggering mode. The breakpoint triggering mode bits trigger on the following conditions: Triggering condition Mode 00 Breakpoint is disabled 01 WRITE accesses only 10 READ accesses only 11 any access DA1 breakpoint triggering mode. For more information, see PA1MODE bit description. DA2 breakpoint triggering mode. For more information, see PA1MODE bit description.

18 19 20 21 22-23

ENBDA ENBIA ENBIO ENBEP PA1MODE

24-25 26-27

DA1MODE DA2MODE

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JTAG Test-Emulation Port

Table 12-3. Emulation Control Register (EMUCTL) Definition (Contd)

Bit # 28-29 30-31 32 Name IO1MODE EP1MODE ANDBKP Function IO1 breakpoint triggering mode. For more information, see PA1MODE bit description. EP1 breakpoint triggering mode. For more information, see PA1MODE bit description. AND composite breakpoints. The ANDBKP bit enables ANDing of each breakpoint type to generate an effective breakpoint from the composite breakpoint signals. (0=OR breakpoint types, 1=AND breakpoint types) Reserved. The ICSA function and DMDSEL bit used by that function not supported on ADSP-21161 processor. NOBOOT No power-up boot on reset. The NOBOOT bit forces the ADSP-21161 processor into the No boot mode. In this mode, the processor does not boot load, but begins fetching instructions from 0x0080 0004 in external memory. (0=disable, 1=force No boot mode) Test mode enable. The TMODE bit is for Analog Devices usage only. Do NOT set this bit. (0=normal operation) Buffer Hang Override bit. The BHO control bit overrides the BHD bit in SYSCON, disabling BHDs control over core access of data buffer behavior. Note that the default (reset) state of BHD is now set for ADSP-21161 processor, a change from ADSP-2106x. (0=normal BHD operation, 1=override BHD operation) Memory Test Enable Bit. The MTST bit enables scanning of data for to the latches used for memory test. (0=normal operation, 1=enable memory test) Reserved

33 34

35 36

TMODE BHO

37

MTST

38, 39

EMUSTAT Shift Register

The EMUSTAT serial shift register is located in the system unit. It is 8 bits wide and is accessed by the emulator through the TAP. This register is updated by the ADSP-21161 processor when the TAP is in the CAP-

ADSP-21161 SHARC Processor Hardware Reference

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Instruction Register

TURE state. The emulator reads EMUSTAT to determine the state of the ADSP-21161 processor. None of the bits in this register can be written by the emulator. All bits are active high. Table 12-4 lists the EMUSTAT registers bits. Table 12-4. Emulation Status (EMUSTAT) Register Definition
Bit # 0 1 2 3 4 5-7 Name EMUSPACE EMUREADY INIDLE COMHALT EPHALT Function (If bit=1...) Indicates that the next instruction is to be fetched from the emulator. Indicates that the ADSP-21161 processor has finished executing the previous emulator instruction. Indicates that the ADSP-21161 processor was in IDLE prior to the latest emulator interrupt. Indicates a core access to a SPORT or a LINK is hung because of an external device. Indicates a core access to a DMA buffer is hung because of the external port. Reserved

BRKSTAT Shift Register

The BRKSTAT serial shift register is located in the system unit. It is 16 bits wide and is accessed by the emulator through the TAP. This register monitors the status of the emulation breakpoints and is updated on every clock cycle. None of the bits of this register can be written by the emulator. Table 12-5 lists the BRKSTAT registers bits. A high bit indicates a breakpoint hit. When a breakpoint hit occurs, the register ceases updating. Stopping allows the emulator to see which breakpoint was triggered. When the ADSP-21161 processor leaves emulation space the BRKSTAT register is cleared and resumes updating. All status bits are synchronized to TCLK before being scanned out.

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JTAG Test-Emulation Port

Table 12-5. BRKSTAT (Breakpoint Status) Register Definition

Bit # 0 1 2 3 4 5 6 7 8 9-15 Name STATPA STATDA0 STATDA1 STATIA0 STATIA1 STATIA2 STATIA2 STATIO STATEP Reserved Function (If bit=1...) Program Memory Data breakpoint hit Data Memory breakpoint hit Data Memory breakpoint hit Instruction Address breakpoint hit Instruction Address breakpoint hit Instruction Address breakpoint hit Instruction Address breakpoint hit I/O Address breakpoint hit EP Address breakpoint hit

MEMTST Shift Register

The MEMTST serial shift register is for Analog Devices usage only. Do not attempt to use this registerincorrect usage of this feature can result in permanent damage to the ADSP-21161 processor being tested.

PSx, DMx, IOx, and EPx (Breakpoint) Registers

The PSx, DMx, IOx, and EPx (Breakpoint) registers are located in the I/O processor register set. The emulation breakpoint registers are not user accessible and can be written only when the ADSP-21161 processor is in emulation space or test mode. The breakpoint registers vary in size according to the address type: instruction (24-bit address), data (32-bit address), or I/O data (19-bit address)Table 12-6 shows the sizes.

ADSP-21161 SHARC Processor Hardware Reference

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Instruction Register

The ADSP-21161 processor contains nine sets of emulation breakpoint registers. Each set consists of a start and end register which describe an address range, with the start register setting the lower end of the address range. Each breakpoint set monitors a particular address bus. When a valid address is in the address range, than a breakpoint signal is generated. The address range includes the start and end addresses. The nine breakpoint sets are grouped into five types: instruction (IA), DM data (DA), PM data (PA), IO data (IO), and EP data (EP). The individual breakpoint signals in each type are ORed together to create five composite breakpoint signals. These composite signals can be optionally ANDed or ORed together to create the effective breakpoint event signal used to generate an emulator interrupt. The ANDBKP bit in the EMUCTL register selects the function used. Each breakpoint type has an enable bit in the EMUCTL register. When set, these bits add the specified breakpoint type into the generation of the effective breakpoint signal. If cleared, the specified breakpoint type is not used in the generation of the effective breakpoint signal. This allows the user to trigger the effective breakpoint from a subset of the breakpoint types. To provide further flexibility, each individual breakpoint can be programmed to trigger if the address is in range AND one of these conditions is met: READ access, WRITE access, ANY access, or NO access. The control bits for this feature are also located in EMUCTL. For more information, see PA1MODES bit description in Table 12-3 on page 12-8. The address ranges of the emulation breakpoint registers are negated by setting the appropriate renege negation bits in the EMUCTL register. For more information, see NEGPA1 bit description Table 12-3 on page 12-8. Each breakpoint can be disabled by setting the start address larger than the end address.

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JTAG Test-Emulation Port

Four of the breakpoints monitor the instruction address. Two monitor the data memory address. One monitors the program memory data address, one monitors the I/O address bus and one monitors the EP address bus. The instruction address breakpoints monitor the address of the instruction being executed, not the address of the instruction being fetched. If the current execution is aborted, the breakpoint signal does not occur even if the address is in range. Data address breakpoints (DA and PA only) are also ignored during aborted instructions. The nine breakpoint sets appear in Table 12-6. Table 12-6. PSx, DMx, IOx, and EPx (Breakpoint) Registers
Register PSA1S PSA1E PSA2S PSA2E PSA3S PSA3E PSA4S PSA4E DMA1S DMA1E DMA2S DMA2E PMDAS PMDAE IOAS IOAE Function Instruction Address Start #1 Instruction Address End #1 Instruction Address Start #2 Instruction Address End #2 Instruction Address Start #3 Instruction Address End #3 Instruction Address Start #4 Instruction Address End #4 Data Address Start #1 Data Address End #1 Data Address Start #2 Data Address End #2 Program Data Address Start Program Data Address End I/O Address Start I/O Address End Group1 IA IA IA IA IA IA IA IA DA DA DA DA PA PA IO IO

ADSP-21161 SHARC Processor Hardware Reference

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Instruction Register

Table 12-6. PSx, DMx, IOx, and EPx (Breakpoint) Registers (Contd)
Register EPAS EPAE 1 Function External Port Address Start External Port Address End Group1 EP EP

Group IA=24-bit addresses, Groups DA, PA, and EP=32-bit addresses, Group IO=19-bit addresses.

EMUN Register
The EMUN (Nth event counter) register is located in the I/O Processor register set. It is not user accessible and can be written only when the ADSP-21161 processor is in emulation space. The EMUN register is read-only from normal-space and can be written only when the ADSP-21161 processor is in emulation space. The Nth event counter allows an emulation breakpoint to occur on the Nth occurrence of the breakpoint event. This is accomplished by writing the desired Nth value to the EMUN register in UREG space. This register can be read from normal space, but it can be written only in emulation space. The counter decrements on each occurrence of the breakpoint event, asserting the interrupt when the counter is equal to zero and the hardware breakpoint event occurs.

EMUCLK and EMUCLK2 Registers

The EMUCLK (clock counter) and EMUCLK2 (clock counter scaling) registers are located in the universal (UREG) register set. EMUCLK and EMUCLK2 are not user accessible and can be written only when the ADSP-21161 processor is in emulation space. These registers are read-only from normal-space and can be written only when the ADSP-21161 processor is in emulation space. The Emulation Clock Counter consists of a 32-bit count register (EMUCLK) and a 32-bit scaling register (EMUCLK2). The EMUCLK counts clock cycles while the user has control of the ADSP-21161 processor and stops counting when the emulator gains control. These registers let you gauge

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JTAG Test-Emulation Port

the amount of time spent executing a particular section of code. The EMUCLK2 register extends the time EMUCLK can count by incrementing each time the EMUCLK value rolls over to zero. The combined emulation clock counter can count accurately for thousands of hours.

EMUIDLE Instruction
The EMUIDLE instruction places the ADSP-21161 processor in the idle state and triggers an emulator interrupt. This operation lets you use the EMUIDLE instruction to be used as a software breakpoint. When EMUIDLE is executed, the emulation clock counter immediately halts.

In Circuit Signal Analyzer (ICSA) Function

This function is NOT supported in the ADSP-21161 processor.

Boundary Register
The Boundary register is 481 bits long. This section defines the latch type and function of each position in the scan path. The positions are numbered with 0 being the first bit output (closest to TDO) and 480 being the last (closest to TDI). The following are some notes about boundary registers: Scan position 0 (NC_0) is the end is closest to TDO (scan in first) Scan position 480 (SPARE); this end is closest to TDI (scan in last) Output Enables: 1 = Drive the associated signals during the EXTEST and INTEST instructions 0 = Three-state the associated signals during the EXTEST and INTEST instructions

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Boundary Register

Table 12-7. JTAG Boundary Register

Scan # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 46 Signal Name NC(I) NC(I) NC(I) BMSTR(O) BMSTR(O) BMSTR(O) EMU(O) EMU(O) EMU(O) RESET(I) RESET(I) RESET(I) FLAG[11](I/O) FLAG[11](I/O) FLAG[11](I/O) FLAG[10](I/O) FLAG[10](I/O) FLAG[10](I/O) FLAG[9](I/O) FLAG[9](I/O) FLAG[9](I/O) FLAG[8](I/O) FLAG[8](I/O) FLAG[0](I/O) Latch Type OUTP Closest to TDO scan in first OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE OE Scan # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 70 Signal Name FLAG[8](I/O) FLAG[7](I/O) FLAG[7](I/O) FLAG[7](I/O) FLAG[6](I/O) FLAG[6](I/O) FLAG[6](I/O) FLAG[5](I/O) FLAG[5](I/O) FLAG[5](I/O) FLAG[4](I/O) FLAG[4](I/O) FLAG[4](I/O) FLAG[3](I/O) FLAG[3](I/O) FLAG[3](I/O) FLAG[2](I/O) FLAG[2](I/O) FLAG[2](I/O) FLAG[1](I/O) FLAG[1](I/O) FLAG[1](I/O) FLAG[0](I/O) ADDR[23](I/O) Latch Type IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE

12-18

ADSP-21161 SHARC Processor Hardware Reference

JTAG Test-Emulation Port

Table 12-7. JTAG Boundary Register (Contd)

Scan # 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 94 Signal Name FLAG[0](I/O) IRQ0(I) IRQ0(I) IRQ0(I) IRQ1(I) IRQ1(I) IRQ1(I) IRQ2(I) IRQ2(I) IRQ2(I) ID0(I) ID0(I) ID0(I) ID1(I) ID1(I) ID1(I) ID2(I) ID2(I) ID2(I) TIMEXP(O) TIMEXP(O) TIMEXP(O) ADDR[23](I/O) ADDR[15](I/O) Latch Type IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE Scan # 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 118 Signal Name ADDR[23](I/O) ADDR[22](I/O) ADDR[22](I/O) ADDR[22](I/O) ADDR[21](I/O) ADDR[21](I/O) ADDR[21](I/O) ADDR[20](I/O) ADDR[20](I/O) ADDR[20](I/O) ADDR[19](I/O) ADDR[19](I/O) ADDR[19](I/O) ADDR[18](I/O) ADDR[18](I/O) ADDR[18](I/O) ADDR[17](I/O) ADDR[17](I/O) ADDR[17](I/O) ADDR[16](I/O) ADDR[16](I/O) ADDR[16](I/O) ADDR[15](I/O) ADDR[7](I/O) Latch Type IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE

ADSP-21161 SHARC Processor Hardware Reference

12-19

Boundary Register

Table 12-7. JTAG Boundary Register (Contd)

Scan # 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 142 Signal Name ADDR[15](I/O) ADDR[14](I/O) ADDR[14](I/O) ADDR[14](I/O) ADDR[13](I/O) ADDR[13](I/O) ADDR[13](I/O) ADDR[12](I/O) ADDR[12](I/O) ADDR[12](I/O) ADDR[11](I/O) ADDR[11](I/O) ADDR[11](I/O) ADDR[10](I/O) ADDR[10](I/O) ADDR[10](I/O) ADDR[9](I/O) ADDR[9](I/O) ADDR[9](I/O) ADDR[8](I/O) ADDR[8](I/O) ADDR[8](I/O) ADDR[7](I/O) MS3(I/O) Latch Type IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE Scan # 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 165 Signal Name ADDR[7](I/O) ADDR[6](I/O) ADDR[6](I/O) ADDR[6](I/O) ADDR[5](I/O) ADDR[5](I/O) ADDR[5](I/O) ADDR[4](I/O) ADDR[4](I/O) ADDR[4](I/O) ADDR[3](I/O) ADDR[3](I/O) ADDR[3](I/O) ADDR[2](I/O) ADDR[2](I/O) ADDR[2](I/O) ADDR[1](I/O) ADDR[1](I/O) ADDR[1](I/O) ADDR[0](I/O) ADDR[0](I/O) ADDR[0](I/O) MS3(I/O) BR4(I/O) Latch Type IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OUTP

12-20

ADSP-21161 SHARC Processor Hardware Reference

JTAG Test-Emulation Port

Table 12-7. JTAG Boundary Register (Contd)

Scan # 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 188 Signal Name MS3(I/O) MS2(I/O) MS2(I/O) MS2(I/O) MS1(I/O) MS1(I/O) MS1(I/O) MS0(I/O) MS0(I/O) MS0(I/O) SBTS(I) SBTS(I) SBTS(I) PA(I/O) PA(I/O) PA(I/O) BR6(I/O) BR6(I/O) BR6(I/O) BR5(I/O) BR5(I/O) BR5(I/O) SDCLK1(O) Latch Type IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP (Formerly CPA) OE (Formerly CPA) IN (Formerly CPA) OUTP OE IN OUTP OE IN IN Scan # 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 212 Signal Name BR4(I/O) BR4(I/O) BR3(I/O) BR3(I/O) BR3(I/O) BR2(I/O) BR2(I/O) BR2(I/O) BR1(I/O) BR1(I/O) BR1(I/O) WR(I/O) WR(I/O) WR(I/O) RD(I/O) RD(I/O) RD(I/O) BRST(I/O) BRST(I/O) BRST(I/O) SDCLK1(O) SDCLK1(O) HBG(I/O) Latch Type OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN

ADSP-21161 SHARC Processor Hardware Reference

12-21

Boundary Register

Table 12-7. JTAG Boundary Register (Contd)

Scan # 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 236 Signal Name SDA10(O) SDA10(O) SDA10(O) SDCKE(I/O) SDCKE(I/O) SDCKE(I/O) CLKOUT(O) CLKOUT(O) CLKOUT(O) SDCLK0(I/O) SDCLK0(I/O) SDCLK0 (I/O) CAS(I/O) CAS(I/O) CAS(I/O) RAS(I/O) RAS(I/O) RAS(I/O) HBR(I) HBR(I) HBR(I) HBG(I/O) HBG(I/O) CLK_CFG0(I) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN Scan # 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 260 Signal Name REDY(O) REDY(O) REDY(O) ACK(I/O) ACK(I/O) ACK(I/O) CS(I) CS(I) CS(I) CLKDBL(I) CLKDBL(I) CLKDBL(I) DQM(O) DQM(O) DQM(O) SDWE(I/O) SDWE(I/O) SDWE(I/O) CLK_CFG1(I) CLK_CFG1(I) CLK_CFG1(I) CLK_CFG0(I) CLK_CFG0(I) DATA[19](I/O) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN

12-22

ADSP-21161 SHARC Processor Hardware Reference

JTAG Test-Emulation Port

Table 12-7. JTAG Boundary Register (Contd)

Scan # 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 284 Signal Name DMAR2(I) DMAR2(I) DMAR2(I) DMAG2(O) DMAG2(O) DMAG2(O) DMAR1(I) DMAR1(I) DMAR1(I) DMAG1(O) DMAG1(O) DMAG1(O) DATA[16](I/O) DATA[16](I/O) DATA[16](I/O) DATA[17](I/O) DATA[17](I/O) DATA[17](I/O) DATA[18](I/O) DATA[18](I/O) DATA[18](I/O) DATA[19](I/O) DATA[19](I/O) DATA[27](I/O) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN Scan # 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 308 Signal Name DATA[20](I/O) DATA[20](I/O) DATA[20](I/O) DATA[21](I/O) DATA[21](I/O) DATA[21](I/O) DATA[22](I/O) DATA[22](I/O) DATA[22](I/O) DATA[23](I/O) DATA[23](I/O) DATA[23](I/O) DATA[24](I/O) DATA[24](I/O) DATA[24](I/O) DATA[25](I/O) DATA[25](I/O) DATA[25](I/O) DATA[26](I/O) DATA[26](I/O) DATA[26](I/O) DATA[27](I/O) DATA[27](I/O) DATA[35](I/O) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN

ADSP-21161 SHARC Processor Hardware Reference

12-23

Boundary Register

Table 12-7. JTAG Boundary Register (Contd)

Scan # 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 332 Signal Name DATA[28](I/O) DATA[28](I/O) DATA[28](I/O) DATA[29](I/O) DATA[29](I/O) DATA[29](I/O) DATA[30](I/O) DATA[30](I/O) DATA[30](I/O) DATA[31](I/O) DATA[31](I/O) DATA[31](I/O) DATA[32](I/O) DATA[32](I/O) DATA[32](I/O) DATA[33](I/O) DATA[33](I/O) DATA[33](I/O) DATA[34](I/O) DATA[34](I/O) DATA[34](I/O) DATA[35](I/O) DATA[35](I/O) DATA[43](I/O) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN Scan # 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 356 Signal Name DATA[36](I/O) DATA[36](I/O) DATA[36](I/O) DATA[37](I/O) DATA[37](I/O) DATA[37](I/O) DATA[38](I/O) DATA[38](I/O) DATA[38](I/O) DATA[39](I/O) DATA[39](I/O) DATA[39](I/O) DATA[40](I/O) DATA[40](I/O) DATA[40](I/O) DATA[41](I/O) DATA[41](I/O) DATA[41](I/O) DATA[42](I/O) DATA[42](I/O) DATA[42](I/O) DATA[43](I/O) DATA[43](I/O) L1DAT[2](I/O) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN

12-24

ADSP-21161 SHARC Processor Hardware Reference

JTAG Test-Emulation Port

Table 12-7. JTAG Boundary Register (Contd)

Scan # 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 380 Signal Name DATA[44](I/O) DATA[44](I/O) DATA[44](I/O) DATA[45](I/O) DATA[45](I/O) DATA[45](I/O) DATA[46](I/O) DATA[46](I/O) DATA[46](I/O) DATA[47](I/O) DATA[47](I/O) DATA[47](I/O) RSTOUT(O)1 RSTOUT(O) RSTOUT(O) L1DAT[0](I/O) L1DAT[0](I/O) L1DAT[0](I/O) L1DAT[1](I/O) L1DAT[1](I/O) L1DAT[1](I/O) L1DAT[2](I/O) L1DAT[2](I/O) L0DAT[0](I/O) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN Scan # 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 404 Signal Name L1DAT[3](I/O) L1DAT[3](I/O) L1DAT[3](I/O) L1ACK(I/O) L1ACK(I/O) L1ACK(I/O) L1CLK(I/O) L1CLK(I/O) L1CLK(I/O) L1DAT[4](I/O) L1DAT[4](I/O) L1DAT[4](I/O) L1DAT[5](I/O) L1DAT[5](I/O) L1DAT[5](I/O) L1DAT[6](I/O) L1DAT[6](I/O) L1DAT[6](I/O) L1DAT[7](I/O) L1DAT[7](I/O) L1DAT[7](I/O) L0DAT[0](I/O) L0DAT[0](I/O) L0DAT[6](I/O) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN

ADSP-21161 SHARC Processor Hardware Reference

12-25

Boundary Register

Table 12-7. JTAG Boundary Register (Contd)

Scan # 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 428 Signal Name L0DAT[1](I/O) L0DAT[1](I/O) L0DAT[1](I/O) L0DAT[2](I/O) L0DAT[2](I/O) L0DAT[2](I/O) L0DAT[3](I/O) L0DAT[3](I/O) L0DAT[3](I/O) L0ACK(I/O) L0ACK(I/O) L0ACK(I/O) L0CLK(I/O) L0CLK(I/O) L0CLK(I/O) L0DAT[4](I/O) L0DAT[4](I/O) L0DAT[4](I/O) L0DAT[5](I/O) L0DAT[5](I/O) L0DAT[5](I/O) L0DAT[6](I/O) L0DAT[6](I/O) D2B(I/O) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN Scan # 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 452 Signal Name L0DAT[7](I/O) L0DAT[7](I/O) L0DAT[7](I/O) FS3(I/O) FS3(I/O) FS3(I/O) SCLK3(I/O) SCLK3(I/O) SCLK3(I/O) D3B(I/O) D3B(I/O) D3B(I/O) D3A(I/O) D3A(I/O) D3A(I/O) FS2(I/O) FS2(I/O) FS2(I/O) SCLK2(I/O) SCLK2(I/O) SCLK2(I/O) D2B(I/O) D2B(I/O) EBOOT(I) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN

12-26

ADSP-21161 SHARC Processor Hardware Reference

JTAG Test-Emulation Port

Table 12-7. JTAG Boundary Register (Contd)

Scan # 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 Signal Name D2A(I/O) D2A(I/O) D2A(I/O) FS1(I/O) FS1(I/O) FS1(I/O) LBOOT(I) LBOOT(I) LBOOT(I) SCLK1(I/O) SCLK1(I/O) SCLK1(I/O) D1B(I/O) D1B(I/O) D1B(I/O) D1A(I/O) D1A(I/O) D1A(I/O) FS0(I/O) FS0(I/O) FS0(I/O) EBOOT(I) EBOOT(I) EBOOT(I) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN Scan # 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 Signal Name SCLK0(I/O) SCLK0(I/O) SCLK0(I/O) D0B(I/O) D0B(I/O) D0B(I/O) D0A(I/O) D0A(I/O) D0A(I/O) SPIDS(I) SPIDS(I) SPIDS(I) SPICLK(I/O) SPICLK(I/O) SPICLK(I/O) MOSI(I/O) MOSI(I/O) MOSI(I/O) MISO(I/O) MISO(I/O) MISO(I/O) BMS(I/O) BMS(I/O) BMS(I/O) Latch Type OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN OUTP OE IN

ADSP-21161 SHARC Processor Hardware Reference

12-27

Device Identification Register

Table 12-7. JTAG Boundary Register (Contd)

Scan # 477 478 Signal Name RPBA(I) RPBA(I) Latch Type OUTP OE Scan # 479 480 Signal Name RPBA(I) SPARE Latch Type IN Closest to TDI scan in last

RSTOUT only exists for silicon revisions 1.2 and greater.

Device Identification Register

No device identification register is included in the ADSP-21161 processor.

Built-In Self-Test Operation (BIST)

No self-test functions are supported by the ADSP-21161 processor.

Private Instructions
Table 12-2 on page 12-4 lists the private instructions that are reserved for emulation and memory test. The ADSP-21161 processor JTAG ICE emulator uses the TAP and boundary scan as a way to access the processor in the target system. The JTAG ICE emulator requires a target board connector for access to the TAP. For more information, see Designing For JTAG Emulation on page 13-49.

12-28

ADSP-21161 SHARC Processor Hardware Reference

JTAG Test-Emulation Port

References
IEEE Standard 1149.1-1990. Standard Test Access Port and Boundary-Scan Architecture. To order a copy, contact IEEE at 1-800-678-IEEE. Maunder, C.M. and R. Tulloss. Test Access Ports and Boundary Scan Architectures. IEEE Computer Society Press, 1991. Parker, Kenneth. The Boundary Scan Handbook. Kluwer Academic Press, 1992. Bleeker, Harry, P. van den Eijnden, and F. de Jong. Boundary-Scan TestA Practical Approach. Kluwer Academic Press, 1993. Hewlett-Packard Co. HP Boundary-Scan Tutorial and BSDL Reference Guide. (HP part# E1017-90001.) 1992.

ADSP-21161 SHARC Processor Hardware Reference

12-29

References

12-30

ADSP-21161 SHARC Processor Hardware Reference

13 SYSTEM DESIGN

The ADSP-21161 processor supports many system design options. The options implemented in a system are influenced by cost, performance, and system requirements. This chapter provides the following system design information: Pin Descriptions on page 13-2 Dual-Voltage Power-up Sequencing on page 13-41 Designing For JTAG Emulation on page 13-49 Conditioning Input Signals on page 13-60 Designing For High Frequency Operation on page 13-62 Booting Single and Multiple Processors on page 13-71 Other chapters also discuss system design issues. Some other locations for system design information include: Setting External Port Modes on page 7-3 Setting Link Port Modes on page 9-5 SPORT Operation Modes on page 10-47 SPI Operation Modes on page 11-24 By following the guidelines described in this chapter, you can design the JTAG emulation interface for an Analog Devices target board. Development and testing of your application code and hardware can begin without debugging the debug port. ADSP-21161 SHARC Processor Hardware Reference 13-1

Pin Descriptions

Pin Descriptions
This section describes the pins of the ADSP-21161 processor and shows how these signals can be used in a ADSP-21161 processor system. All I/O pins except CLKIN and XTAL have an internal 50k resister that is enabled during reset. Figure 13-1 illustrates how the pins are used in a single-processor system. Figure 7-29 on page 7-91 shows a system diagram illustrating pin connections in an multiprocessor cluster.

13-2

ADSP-21161 SHARC Processor Hardware Reference

System Design

CONTROL

CLOCK 2

CLKIN XTAL CLK_CFG1-0 CLKDBL EBOOT LBOOT IRQ2-0 BMS

DATA
CS ADDR BOOT EPROM (OPTIONAL) DATA ADDR DATA MEMORY AND OE PERIPHERALS WE (OPTIONAL) ACK CS RAS CAS DQM WE CLK CKE A10 CS ADDR DATA SDRAM (OPTIONAL)

ADSP-21161

3 12

BRST

LINK DEVICES (2 MAX) (OPTIONAL) SERIAL DEVICE (OPTIONAL)

FLAG11-0 ADDR23-0 TIMEXP DATA47-16 RPBA ID2-0 RD LXCLK WR LXACK ACK LXDAT7-0 MS3-0 SCLK0 FS0 D0A D0B SCLK1 FS1 D1A D1B SCLK2 FS2 D2A D2B SCLK3 FS3 D3A D3B SPICLK SPDS MOSI MISO RAS CAS DQM SDWE SDCLK1-0 SDCKE SDA10

SERIAL DEVICE (OPTIONAL)

SERIAL DEVICE (OPTIONAL)

CLKOUT DMAR1-2 DMAG1-2

ADDRESS

DMA DEVICE (OPTIONAL) DATA

SERIAL DEVICE (OPTIONAL)

CS HBR HBG REDY BR1-6 PA SBTS

SPI COMPATIBLE DEVICE (HOST OR SLAVE) (OPTIONAL)

HOST PROCESSOR INTERFACE (OPTIONAL) ADDR DATA

RESET RSTOUT JTAG 7

Figure 13-1. Single Processor System

ADSP-21161 SHARC Processor Hardware Reference

13-3

Pin Descriptions

ADSP-21161 processor pin definitions are listed in Table 13-1. The following symbols appear in the Type column of Table 13-1: A G I O P S (a/d) (o/d) T Asynchronous Ground Input Output Power Supply Synchronous Active Drive Open Drain Three-State (when SBTS is asserted or the processor is bus slave)

Table 13-1. Pin Descriptions

Pin ACK Type I/O/S Function Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-21161 processor deasserts ACK as an output to add wait states to a synchronous access of its IOP registers. ACK has a 20k internal pull-up resistor that is enabled during reset or on processors with ID2-0=00x. External Bus Address. The ADSP-21161 processor outputs addresses for external memory and peripherals on these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the IOP registers of other ADSP-21161 processors while all other internal memory resources can be accessed indirectly via DMA control (that is, accessing IOP DMA parameter registers). The ADSP-21161 processor inputs addresses when a host processor or multiprocessing bus master is reading or writing its IOP registers. A keeper latch on the processors ADDR23-0 pins maintains the input at the level it was last driven. This latch is only enabled on processors with ID2-0=00x.

ADDR23-0

I/O/T

13-4

ADSP-21161 SHARC Processor Hardware Reference

System Design

Table 13-1. Pin Descriptions (Contd)

Pin AVDD Type P Function Analog Power Supply. Nominally +1.8V dc and supplies the processors internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. For more information, see Power Supplies in the ADSP-21161 Data Sheet. Analog Power Supply Return. Multiprocessing Bus Requests. Used by multiprocessing ADSP-21161 processors to arbitrate for bus mastership. An ADSP-21161 processor only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-21161 processors, the unused BRx pins should be pulled high; the processor's own BRx line must not be pulled high or low because it is an output. Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins; see Table 13-11 on page 13-72. This input is a system configuration selection that should be hardwired. For Host and PROM boot, DMA channel 10 (EPB0) is used. For Link Boot and SPI boot, DMA channel 8 is used. *Three-state only in EPROM boot mode (when BMS is an output). BMSTR O Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21161 processor is current bus master of the shared external bus. The ADSP-21161 processor drives BMSTR high only while it is the bus master. In a single-processor system (ID2-0 = 000), the processor drives this pin high.

AGND BR6-1

G I/O/S

BMS

I/O/T

ADSP-21161 SHARC Processor Hardware Reference

13-5

Pin Descriptions

Table 13-1. Pin Descriptions (Contd)

Pin BRST Type I/O/T Function Sequential Burst Access. BRST is asserted by ADSP-21161 processor to indicate that data associated with consecutive addresses is being read or written. A slave device samples the initial address and increments an internal address counter after each transfer. The incremented address is not pipelined on the bus. A master ADSP-21161 processor in a multiprocessor environment can read slave external port buffers (EPBx) using the burst protocol. BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that, except for the last data request cycle (denoted by RD or WR asserted and BRST negated). A keeper latch on the processors BRST pin maintains the input at the level it was last driven. This latch is only enabled on processors with ID2-0=00x. SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21161 processor clock input. It configures the ADSP-21161 processor to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21161 processor to use the external clock source such as an external clock oscillator.The ADSP-21161 processor external port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the CLKIN frequency; it is programmable at power-up via the CLK_CFG1-0 pins. CLKIN may not be halted, changed, or operated below the specified frequency. Core/CLKIN Ratio Control. ADSP-21161 processor core clock (instruction cycle) rate is equal to n x PLLICLK where n is user selectable to 2, 3, or 4, using the CLK_CFG1-0 inputs. These pins can also be used in combination with the CLKDBL pin to generate additional core clock rates of 6 x CLKIN and 8 x CLKIN (see Table 13-8 on page 13-29).

CAS

I/O/T

CLKIN

CLK_CFG1-0

13-6

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System Design

Table 13-1. Pin Descriptions (Contd)

Pin CLKDBL Type I Function Crystal Double Mode Enable. This pin is used to enable the 2x clock double circuitry, where CLKOUT can be configured as either 1x or 2x the rate of CLKIN. This CLKIN double circuit is primarily intended to be used for an external crystal in conjunction with the internal clock generator and the XTAL pin. The internal clock generator when used in conjunction with the XTAL pin and an external crystal is designed to support up to a maximum of 25 MHz external crystal frequency. CLKDBL can be used in XTAL mode to generate a 50 MHz input into the PLL. The 2x clock mode is enabled (during RESET low) by tying CLKDBL to GND, otherwise it is connected to VDDEXT for 1x clock mode. For example, this allows the use of a 25 MHz crystal to enable 100MHz core clock rates and a 50 MHz CLKOUT operation when CLK_CFG1=0 and CLKDBL=0. This pin can also be used to generate different clock rate ratios for external clock oscillators as well. The possible clock rate ratio options (up to 100 MHz) for either CLKIN (external clock oscillator) or XTAL (crystal input) are shown in Table 13-8 on page 13-29: Clock Rate Ratios. An 8:1 ratio allows the use of a 12.5 MHz crystal to generate a 100 MHz core (instruction clock) rate and a 25 MHz CLKIN (external port) clock rate. Note: When using an external crystal, the maximum crystal frequency cannot exceed 25 MHz. For all other external clock sources, the maximum CLKIN frequency is 50 MHz. For more information, see Clock Rate Ratios on page 13-29.

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Table 13-1. Pin Descriptions (Contd)

Pin CLKOUT Type O/T Function Local Clock Out. CLKOUT is 1x or 2x and is driven at either 1x or 2x the frequency of CLKIN frequency by the current bus master. The frequency is determined by the CLKDBL pin. The three programmable modes supported for CLKOUT by setting bit 22 (COD) and 23 (COPT) of the SYSCON register are: COPT 0 0 1 COD 0 1 x CLKOUT Description Free running Disabled Driven by MMS master

When the COPT bit is set, CLKOUT is driven by the master device. CLKOUT is three-stated during the bus transition cycle by the device giving up its bus master status. The new bus master then drives CLKOUT. During host accesses, the bus master that granted the bus to the host drives CLKOUT. A keeper latch on the processors CLKOUT pin maintains the output at the level it was last driven. This latch is only enabled on processors with ID2-0=00x. If CLKDBL enabled, CLKOUT = 2xCLKIN period If CLKDBL disabled, CLKOUT = 1xCLKIN period Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1xCLKIN or 2xCLKIN. For more information, see ADSP-21161 CLKOUT and CCLK Clock Generation Operation on page 13-27. CS I/A Chip Select. Asserted by host processor to select the ADSP-21161 processor.

13-8

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Table 13-1. Pin Descriptions (Contd)

Pin DATA47-16 Type I/O/T Function External Bus Data. The ADSP-21161 processor inputs and outputs data and instructions on these pins. Pull-up resistors on unused data pins are not necessary. A keeper latch on the processors DATA47-16 pins maintains the input at the level it was last driven. This latch is only enabled on the processors with ID2-0=00x. Note: DATA[15:8] pins (multiplexed with L1DATA[7:0]) can also be used to extend the data bus if the link ports are disabled and not used. In addition, DATA[7:0] pins (multiplexed with L0DATA[7:0]) can also be used to extend the data bus if the link ports are not used. This allows execution of 48-bit instructions from external SBSRAM (system clock speed-external port), SRAM (system clock speed-external port) and SDRAM (core clock or one-half the core clock speed). The IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1-0 = 0x1) to enable this full instruction Width/No-packing Mode of operation. DMAR1 I/A DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services. DMAR1 has a 20k internal pull-up resistor. DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has a 20k internal pull-up resistor. DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21161 processor to indicate that the requested DMA starts on the next cycle. Driven by bus master only. DMAG1 has a 20k internal pull-up resistor that is enabled for processors with ID2-0=00x. DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21161 processor to indicate that the requested DMA starts on the next cycle. Driven by bus master only. DMAG2 has a 20k internal pull-up resistor that is enabled for processors with ID2-0=00x. SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a precharge command and during SDRAM power-up initialization.

DMAR2

I/A

DMAG1

O/T

DMAG2

O/T

DQM

O/T

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Table 13-1. Pin Descriptions (Contd)

Pin DxA Type I/O Function Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has a 50k internal pull-up resistor. Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has a 50k internal pull-up resistor. Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. EPROM Boot Select. For a description of how this pin operates, see the table in the BMS pin description. This signal is a system configuration selection that should be hardwired. Emulation Status. Must be connected to the ADSP-21161 processor Analog Devices Tools product line of JTAG emulators target board connector only. EMU has a 50k internal pullup resistor. Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. It can be active high or low or an early or a late frame sync, in reference to the shifting of serial data. Power Supply Return (26 pins). Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21161 processors external bus. When HBR is asserted in a multiprocessing system, the ADSP-21161 processor that is bus master relinquishes the bus and asserts HBG. To relinquish the bus, the ADSP-21161 processor places the address, data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-21161 processor bus requests (BR6-1) in a multiprocessing system.

DxB

I/O

EBOOT

EMU

O (O/D)

FLAG11-0

I/O/A

FSx

I/O

GND HBR

G I/A

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Table 13-1. Pin Descriptions (Contd)

Pin HBG Type I/O Function Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of the external bus. HBG is asserted (held low) by the ADSP-21161 processor until HBR is released. In a multiprocessing system, HBG is output by the ADSP-21161 processor bus master and is monitored by all others. After HBR is asserted, and before HBG is given, HBG floats for 1 tCK (1 CLKIN cycle). To avoid erroneous grants, HBG should be pulled up with a 20k to 50k ohm external resistor. IRQ2-0 ID2-0 I/A I Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edge-triggered or level-sensitive. Multiprocessing ID. Determines which multiprocessing bus request (BR1 - BR6) is used by ADSP-21161 processor. ID2-0 = 001 corresponds to BR1, ID2-0 = 010 corresponds to BR2, and so on. Use ID2-0 = 000 or ID2-0 = 001 in single-processor systems. These lines are a system configuration selection that should be hardwired or only changed at reset. Link Port Data (Link Ports 0-1). Each LxDAT pin has a 20k internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register or a keeper latch when used as DATA pins. Note: L1DATA[7:0] are multiplexed with the DATA[15:8] pins L0DATA[7:0] are multiplexed with the DATA[7:0] pins. If link ports are disabled and are not be used, then these pins can be used as additional data lines for executing instructions at up to the full clock rate from external memory. For revisions 0.3, 1.0 and 1.1, LxDAT7-0 has a 50k internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register LxCLK I/O Link Port Clock (Link Ports 0-1). Each LxCLK pin has a 50k internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.

LxDAT7-0 [DAT15-0]

I/O [I/O/T]

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Table 13-1. Pin Descriptions (Contd)

Pin LxACK Type I/O Function Link Port Acknowledge (Link Ports 0-1). Each LxACK pin has a 50k internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register. Link Boot. For a description of how this pin operates, see the table in the BMS pin description. This signal is a system configuration selection that should be hardwired. SPI Master Out Slave In. If the ADSP-21161 processor is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21161 processor is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an ADSP-21161 processor SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 50k internal pull-up resistor. SPI Master In Slave Out. If the ADSP-21161 processor is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-21161 processor is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an ADSP-21161 processor SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 50k internal pull-up resistor. Note: Only one master is allowed to transmit data at any given time. MS3-0 I/O/T Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of external memory. Memory bank sizes are fixed to 16 Mwords for non-SDRAM and 64 Mwords for SDRAM. The MS3-0 outputs are decoded memory address lines. In asynchronous access mode, the MS3-0 outputs transition with the other address outputs. In synchronous access modes, the MS3-0 outputs assert with the other address lines; however, they de-assert after the first CLKIN cycle in which ACK is sampled asserted. In a multiprocessor systems, the MSx signals are tracked by slave SHARCs. MS3-0 has a keeper latched enabled for processors with ID2-0=00x.

LBOOT

MOSI

I/O

MISO

I/O

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Table 13-1. Pin Descriptions (Contd)

Pin NC PA I/O/T Type Function Do Not Connect. Reserved pins that must be left open and unconnected. (5 pins). Priority Access. Asserting its PA pin allows an ADSP-21161 processor bus slave to interrupt background DMA transfers and gain access to the external bus. PA is connected to all ADSP-21161 processors in the system. If access priority is not required in a system, the PA pin should be left unconnected. PA has a 20k internal pull-up resistor that is enabled for processors with ID2-0=00x. SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. Memory Read Strobe. RD is asserted whenever ADSP-21161 processor reads a word from external memory or from the IOP registers of other ADSP-21161 processors. External devices, including other ADSP-21161 processors, must assert RD for reading from a word of the ADSP-21161 processor IOP register memory. In a multiprocessing system, RD is driven by the bus master. RD has a 20k internal pull-up resistor that is enabled for processors with ID2-0=00x. Host Bus Acknowledge. The ADSP-21161 processor de-asserts REDY (low) to add waitstates to a host access of its IOP registers when CS and HBR inputs are asserted. Processor Reset. Resets the ADSP-21161 processor to a known state and begins execution at the program memory location specified by the hardware reset vector address. The RESET input must be asserted (low) at power-up. Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection that must be set to the same value on every ADSP-21161 processor. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-21161 processor.

RAS

I/O/T

RD

I/O/T

REDY

O (O/D)

RESET

I/A

RPBA

I/S

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Table 13-1. Pin Descriptions (Contd)

Pin RSTOUT
1

Type O

Function Reset Out. When RSTOUT is asserted, this pin is used to indicate to the external logic that the core blocks are in reset. It is deasserted 4096 cycles after RESET is deasserted allowing the PLL to stabilize and lock. For systems requiring a secondary reset for other devices needing to be simultaneously brought out of reset with the processor core reset, system designers can connect this pin to the reset pin of the other devices. This prevents other devices from driving data before the processor begins the booting process.

SDWE

I/O/T

SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. SDRAM Clock Output 0. Clock for SDRAM devices. SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices, handles the increased clock load requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet supplied with your SDRAM device. SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-SDRAM accesses or host accesses. Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21161processor attempts to access external memory while SBTS is asserted, the processor halts and the memory access is not completed until SBTS is de-asserted. SBTS should only be used to recover from host processor/ADSP-21161 processor deadlock. Transmit/Receive Serial Clock (Serial Ports 0, 1, 2, 3). Each SCLK pin has a 50k internal pull-up resistor. This signal can be either internally or externally generated.

SDCLK0 SDCLK1

I/O/S/T O/S/T

SDCKE

I/O/T

SDA10 SBTS

O/T I/S

SCLKx

I/O

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Table 13-1. Pin Descriptions (Contd)

Pin SPICLK Type I/O Function Serial Peripheral Interface Clock Signal. Driven by the master, controls the rate at which data is transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge of the clock and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 50k internal pull-up resistor. Serial Peripheral Interface Slave Device Select. An active low signal used to enable slave devices. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multi-master mode SPIDS signal can be asserted to a master device to signal that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multi-master error. For a Single-Master, Multiple-Slave configuration where FLAG3-0 are used, this pin must be tied high to V DDINT. For ADSP-21161 processor to ADSP-21161 processor SPI interaction, any of the master ADSP-21161 processors FLAG3-0 pins can be used to drive the SPIDS signal on the ADSP-21161 processor SPI slave device. Timer Expired. Asserted for four core clock cycles when the timer is enabled and TCOUNT decrements to zero. Test Clock (JTAG). Provides a clock for JTAG boundary scan. Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20k internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20k internal pull-up resistor. Test Data Output (JTAG). Serial scan output of the boundary scan path.

SPIDS

TIMEXP TCK TMS TDI TDO

O I I/S I/S O

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Table 13-1. Pin Descriptions (Contd)

Pin TRST Type I/A Function Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21161 processor. TRST has a 20k internal pull-up resistor. Core Power Supply. Nominally +1.8 V DC and supplies the processors core processor (14 pins). I/O Power Supply. Nominally +3.3 V DC. (13 pins). Memory Write Low Strobe. WR is asserted when ADSP-21161 processor writes a word to external memory or IOP registers of other ADSP-21161 processors. External devices must assert WR for writing to ADSP-21161 processors IOP registers. In a multiprocessing system, WR is driven by the bus master. WR has a 20k internal pull-up resistor that is enabled for processors with ID2-0=00x. Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the ADSP-21161 processors internal clock generator or to disable it to use an external clock source. See CLKIN.

VDDINT VDDEXT WR

P P I/O/T

XTAL

RSTOUT exists only for silicon revisions 1.2 and greater.

Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to VDDEXT or GND, except for ADDR23-0, DATA47-16, FLAG11-0, and inputs that have internal pull-up or pull-down resistors (PA, ACK, BRST, CLKOUT, RD, WR, DMARx, DMAGx, DxA, DxB, SCLKx, LxDAT7-0, MISO, MOSI, SPICLK, LxCLK, LxACK, TMS, TRST and TDI) these pins can be left floating. Some of these pins have a logic-level hold circuit (only enabled on the ADSP-21161 processor with ID2-0=00x) that prevents input from floating internally. See the pin list in Table 13-1.

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The TRST input of the JTAG interface must be asserted (pulsed low) or held low after power-up for proper operation of the ADSP-21161 processor. Do not leave this pin unconnected. Additional Notes: In single-processor systems, the processor owns the external bus during reset and does not perform bus arbitration to gain control of the bus. Operation of the RD and WR signals changes when CS is asserted by a host processor. For more information, see Asynchronous Transfers on page 7-48. Except during a Host Transition Cycle (HTC), the RD and WR strobes should not be deasserted (low-to-high transition) while ACK or REDY are deasserted (low)the processor hangs if this happens. In multiprocessor systems, the ACK signal is an input to the ADSP-21161 processor bus master and does not float when it is not being driven. It is not necessary to use an external pullup resistor on the ACK line during booting or at any other time. The ACK pin is pulled high internally with a 20k equivalent resistor and is activated under the following three conditions: 1. When the processor is in reset (regardless of the hardwired ID pin configuration) 2. After reset, in a single processor system (ID2-0 =000) 3. After reset, in a multiprocessor system, the processor having ID2-0 =001 Figure 13-2 shows how different data word sizes are transferred over the external port.

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Pin Descriptions

L1DATA[7:0] L0DATA[7:0] DATA 15-8 DATA 7-0

DATA 47-16
47 40 39 32 31 24 23 16 15

DATA 15-0
8 7 0

PROM BOOT 8-bit Packed DMA Data 8-bit Packed Instruction Execution 16-bit Packed DMA Data 16-bit Packed Instruction Execution Float or Fixed, D31-D0, 32-bit Packed 32-bit Packed Instruction 48-bit Instruction Fetch (No Packing) Extra Data Lines DATA[15-0] Are Only Accessible If Link Ports Are Disabled. Enable These Additional Data Lines By setting IPACK[1:0] = 01 In SYSCON.

Figure 13-2. External Port Data Alignment

Input Synchronization Delay

The ADSP-21161 processor has several asynchronous inputs: RESET, TRST, HBR, CS, DMAR1, DMAR2, IRQ2-0, and FLAG11-0 (when configured as inputs). These inputs can be asserted in arbitrary phase to the processor clock, CLKIN. The processor synchronizes the inputs prior to recognizing them. The delay associated with recognition is called the synchronization delay. Any asynchronous input must be valid prior to the recognition point in a particular cycle. If an input does not meet the setup time on a given cycle, it may be recognized in the current cycle or during the next cycle.

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To ensure recognition of an asynchronous input, it must be asserted for at least one full processor cycle plus setup and hold time, except for RESET, which must be asserted for at least four processor cycles. The minimum time prior to recognition (the setup and hold time) is specified in the ADSP-21161N SHARC DSP Microcomputer Data Sheet.

Pin States At Reset

Table 13-2 shows the processor pin states during and after reset. Table 13-2. Pin States at Reset
Pin ACK ADDR23-0 BMS BMSTR BR6-1 BRST CAS CLK_CFG1-0 CLKDBL CLKIN CLKOUT CS DATA47-16 DMAG1 DMAG2 Type I/O/S/T I/O/T I/O/T O I/O I/O/T I/O/T I I I O/T I I/O/T O/T O/T State During and After Reset Pulled high by bus master (w/ 20k internal pullup resistor)1 Driven1 Input2 Driven high for ID1, driven low for ID2-6 BR1 driven low if bus master, otherwise driven high1 Driven low1 Driven high Input Input Input Driven Input2 Three-state1 Driven high1 Driven high1

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Pin Descriptions

Table 13-2. Pin States at Reset (Contd)

Pin DMAR1 DMAR2 DQM DxA DxB EBOOT EMU FLAG11-0 FSx HBG HBR ID2-0 IRQ2-0 LBOOT LxACK LxCLK LxDAT7-0 MISO MOSI MS3-0 PA (o/d) RAS RD REDY (o/d) Type I I I/O/T O I I O (o/d) I/O/A I/O I/O/S/T I/A I I/A I I/O I/O I/O I/O I/O I/O/T I/O I/O/T I/O/T O State During and After Reset Input2 Input2 Driven high until SDRAM power-up sequence starts Three-state (for multichannel) Input4 Input2 Three-state3 Input2 Three-state4 Driven high1 Input2 Input2 Input2 Input2 Three-state4 Three-state4 Three-state4 Input4 Input4 Driven high1 Three-state2 Driven high Driven high1 Three-state2

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Table 13-2. Pin States at Reset (Contd)

Pin RESET RPBA RSTOUT SBTS SCLK SDA10 SDCKE SDCLK0 SDCLK1 SDWE SPICLK SPIDS TCK TDI TDO TIMEXP TMS TRST WR XTAL 1 2 3 4 Type I/A I/S O I/S I/O O/T I/O/T I/O/S/T O/S/T I/O/T I/O I I I/S O O I/S I/A I/O/T O/T State During and After Reset Input2 Input2 Driven low2 Input Three-state4 Driven Driven high Driven Driven Driven high Three-state4 Input4 Input3 Input3 Three-state3 Driven low2 Input3 Input3 Driven high1 Driven

For ID =0 or 1, driven only by processor bus master, otherwise three-stated Bus master independent JTAG interface Serial ports, SPI and link port

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Pin Descriptions

Pull-Up and Pull-Down Resistors

Table 13-3 shows the keeper latches, pull-up and pull-down resistor values associated with each pin. Table 13-3. Keeper Latches and Resistor Values
Pin ACK ADDR23-0 BMS BMSTR BR6-1 BRST CAS CLK_CFG1-0 CLKDBL CLKIN CLKOUT CLKx CS DATA47-16 DMAG1 DMAG2 DMAR1 DMAR2 DQM DxA DxB Resistor va1ue 20k pull-up enabled during reset or when ID2-0 = 00X Keeper latch (only for ID2-0 = 00X) N/A N/A N/A Keeper latch (only for ID2-0 = 00X) N/A N/A N/A N/A Keeper latch (only for ID2-0 = 00X) N/A N/A Keeper latch (only for ID2-0 = 00X) 20k Pull-up (only for ID2-0 = 00X) 20k Pull-up (only for ID2-0 = 00X) 20k Pull-up (only for ID2-0 = 00X) 20k Pull-up (only for ID2-0 = 00X) N/A 50k Pull-up 50k Pull-up

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Table 13-3. Keeper Latches and Resistor Values (Contd)

Pin EBOOT EMU FLAG11-0 FSx HBG HBR ID2-0 IRQ2-0 LBOOT LxACK LxCLK LxDAT7-0 Resistor va1ue N/A 50k Pull-up N/A N/A N/A N/A N/A N/A N/A 50k Pull-down that is enabled or disabled by the LxPDRDE bit of the LCTL register. 50k Pull-down that is enabled or disabled by the LxPDRDE bit of the LCTL register. For Revisions 0.3. 1.0, 1.1, 50k Pull-down For Revisions 1.2 and higher, a keeper latch is enabled when these pins are used as DATA lines or a 20k Pull-down resistor is enabled or disabled based on the LxPDRDE bit setting. MISO MOSI MS3-0 PA (o/d) RAS RD REDY (o/d) RESET RPBA 50k Pull-up 50k Pull-up Keeper latch (Only for ID2-0 = 00X) 20k Pull-up (only for ID2-0 = 00X) N/A 20k Pull-up (only for ID2-0 = 00X) N/A N/A N/A

ADSP-21161 SHARC Processor Hardware Reference

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Table 13-3. Keeper Latches and Resistor Values (Contd)

Pin SBTS SCLK SDA10 SDCKE SDCLK0 SDCLK1 SDWE SPICLK SPIDS TCK TDI TDO TIMEXP TMS TRST WR XTAL Resistor va1ue N/A 50k Pull-up N/A N/A N/A N/A N/A 50k Pull-up N/A N/A 20k Pull-up N/A N/A 20k Pull-up 20k Pull-up 20k Pull-up (only for ID2-0 = 00X) N/A

Clock Derivation
The ADSP-21161 processor employs a phase-locked loop on-chip, to provide clocks that switch at higher frequencies than the system clock (CLKIN). The PLL-based clocking methodology employed on the processor influences the clock frequencies and behavior for the serial, link, SDRAM, SPI, and external ports; in addition to the processor core and internal memory. In each case, the processor PLL provides a de-skewed clock to the port logic and I/O pins.

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For the external port, this clock is fedback to the PLL, such that the external port clock always switches at the 1x or 2x frequency CLKIN frequency depending on if CLKDBL is enabled. The PLL provides internal clocks that switch at multiples of the CLKIN frequency for the internal memory, processor core, link and serial ports, and to modify the external port timing as required (for example, read/write strobes in asynchronous modes). The ratio of processor core clock frequency and CLKIN/external port clock frequency is determined by the CLK_CFG1-0 pins and CLKDBL pin (as shown in Table 13-8 on page 13-29), during reset. The core clock ratio cannot be altered dynamically. The ADSP-21161 processor must be reset to alter the clock ratio. The PLL provides a clock that switches at the processor core frequency to the serial and link ports. Each of the serial and link ports can be programmed to operate at clock frequencies derived from this clock. The four serial ports transmit and receive clocks are divided down from the processor core clock frequency by setting the DIVx registers appropriately. In addition to the PLL ratios generated by the CLK_CFG1-0 pins, an additional CLKDBL pin can be used for additional clock ratio options. The (1x/2x CLKIN) rate set by the CLKDBL pin determines the rate of the PLL input clock and the rate at which the synchronous external port operates. With the combination of CLK_CFG[1:0] and CLKDBL, ratios of 2:1, 3:1, 4:1, 6:1, and 8:1 between the core and CLKIN are supported. Timing Specifications The ADSP-21161 processors internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, link ports, serial ports, SPI, SDRAM, and external port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the ADSP-21161 processors internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1-0 and CLKDBL pins. Even

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Pin Descriptions

though the internal clock is the clock source for the external port, it behaves as described in the Clock Rate Ratio chart (CLKDBL pin description). To determine switching frequencies for the serial and link ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports and LxCLKD1-0 for the link ports). For the SPI port, the BAUDR bit in the SPICTL register controls the SPICLK baud rate based on the core clock frequency. Each of the two link port clock frequencies are determined by programming the LxCLKDx parameters in the LCTL registers. For more information, see Link Port Buffer Control Register (LCTL) on page A-92. Note the following definitions of various clock periods that are a function of CLKIN and the appropriate ratio control. Figure 13-3 allows Core-to-CLKIN ratios of 2:1, 3:1, 4:1, 6:1, and 8:1 with external oscillator or crystal.
External Port Host, MMS, SRAM SBSRAM PLL External Port SDRAM x1, x1/2

PLLICLK

CLKIN
Crystal or Clock Oscillator

Input Clock Doubler 1:1, 2:1 If Bus Master

Tie to GND to enable 2x operation

CCLK
2:1, 3:1, 4:1 Core Clock

XTAL

CLKDBL

CLKOUT

CLK_CFG[1:0]

SDCLK[1:0]

Figure 13-3. Core Clock and System Clock Relationship to CLKIN

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Table 13-4 and Table 13-5 provide various definitions of clock inputs, outputs and uses in an ADSP-21161 processor system. Table 13-4. ADSP-21161 CLKOUT and CCLK Clock Generation Operation
Timing Requirements CLKIN CLKOUT PLLICLK CCLK = = = = Calculation 1/tCKIN 1/tTCK 1/tPLLIN 1/tCCLK = = = = Description Input Clock Local Clock Out PLL Input Clock Core Clock

If CLKDBL is enabled (tied low at reset), then CLKOUT = PLLICLK = 2xCLKIN. Otherwise, CLKOUT = PLLICLK = CLKIN. CCLK = Core Clock = PLLICLK x PLL Multiply Ratio (determined by CLK_CFG pins). Table 13-5. Clock Relationships
Timing Requirements tCK tPLLICK tCCLK tLCLK tSCLK tSDK tSPICLK = = = = = = = Description1 CLKOUT Clock Period PLL Input Clock (Processor) Core Clock Period Link Port Clock Period = (tCCLK) * LR Serial Port Clock Period = (tCCLK) * SR SDRAM Clock Period = (tCCLK) * SDCKR SPI Clock Period = (tCCLK) * SPIR

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Pin Descriptions

where: LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD) SR = serial port-to-core clock ratio (wide range, determined by CLKDIV) SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register) SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register) LCLK = Link Port Clock SCLK = Serial Port Clock SDK = SDRAM Clock SPICLK = SPI Clock

Table 13-6 describes clock ratio requirements. Table 13-7 shows an example clock derivation. Table 13-6. Clock Ratios
Timing Requirements cRTO lRTO sRTO = = = Description Core:CLKOUT ratio, (2, 3, or 4:1, determined by CLK_CFG) lport:core clock ratio (1:1, 1:2, 1:3, or 1:4, determined by LxCLKD) Sport:core clock ratio (wide range determined by xCLKDIV)

Table 13-7. Determining Clock Period

Timing Requirements tCCLK tLCLK tSCLK = = = Description (tCK): cRTO (tCCLK) * lRTO (tCCLK) * sRTO

RESET and CLKIN

The ADSP-21161 processor receives its clock input on the CLKIN pin. The processor uses an on-chip phase-locked loop to generate its internal clock, which is a multiple of the CLKIN frequency. Because the phase-locked loop requires some time to achieve phase lock, CLKIN must be valid for a mini-

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mum time period during reset before the RESET signal can be deasserted. For information on minimum clock setup, see the ADSP-21161N DSP Microcomputer Data Sheet. Table 13-8 describes the internal clock to CLKIN frequency ratios supported by the ADSP-21161 processor. Table 13-8. Clock Rate Ratios
CLKDBL 1 1 1 0 0 0 CLK_CFG1 0 0 1 0 0 1 CLK_CFG0 0 1 0 0 1 0 Core Clock Ratio 2:1 3:1 4:1 4:1 6:1 8:1 CLKOUT Ratio 1x 1x 1x 2x 2x 2x

When using an external crystal, the maximum crystal frequency cannot exceed 25 MHz. The internal clock generator when used in conjunction with the XTAL pin and an external crystal is designed to support up to a maximum of 25 MHz external crystal frequency. For all other external clock sources, the maximum CLKIN frequency is 50 MHz. Table 13-9 demonstrates the internal core clock switching frequency, across a range of CLKIN frequencies. The minimum operational range for any given frequency is constrained by the operating range of the phase

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Pin Descriptions

lock loop. Note that the goal in selecting a particular clock ratio for the application is to provide the highest internal frequency, given a CLKIN frequency. If an external master clock is used, it should not be driving the CLKIN pin when the processor is not powered. The clock must be driven immediately after powerup; otherwise, internal gates stay in an undefined (hot) state and can draw excess current. After powerup, there should be sufficient time for the oscillator to start up, reach full amplitude and deliver a stable CLKIN signal to the processor before the reset is released. This may take 100 ms depending on the choice of crystal, operating frequency, loop gain and capacitor ratios. For details on timing, refer to the ADSP-21161N DSP Microcomputer Data Sheet. After the external RESET signal is deasserted, the PLL starts operating. The rest of the chip is held in reset for 4096 CLKIN cycles after RESET is deasserted by an internal (or core) reset (RSTOUT1) signal. This sequence allows the PLL to lock and stabilize. Table 13-9. Selecting Core to CLKIN Ratio
Typical Crystal and Clock Oscillators Inputs 12.5 Clock Ratios 2:1 3:1 4:1 6:1 16.67 25 33.3 40 50

Core CLK (MHz) 25 37.5 50 75 33.3 50 66.6 100 50 75 100 N/A 66.6 100 N/A N/A 80 N/A N/A N/A 100 N/A N/A N/A

RSTOUT exists only for silicon revisions 1.2 and greater.

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Table 13-9. Selecting Core to CLKIN Ratio

Typical Crystal and Clock Oscillators Inputs 8:1 100 N/A N/A N/A N/A N/A

Reset Generators
It is important that an ADSP-21161 processor (or programmable device) have a reliable active RESET that is released once the power supplies and internal clock circuits have stabilized. The RESET signal should not only offer a suitable delay, but it should also have a clean monotonic edge. Analog Devices has a range of microprocessor supervisory ICs with different features. Features include one or more of the following: Powerup reset Optional manual reset input Power low monitor Back-up battery switching Part number series for Analog Devices supervisory circuits are as follows: ADM69x ADM70x ADM80x ADM1232 ADM181x ADM869x

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Pin Descriptions

A simple powerup reset circuit is shown in Figure 13-4, using the ADM809-RART reset generator. The ADM809 provides an active low RESET signal whenever the supply voltage is below 2.63V. At powerup, a 240ms active reset delay is generated to give the power supplies and oscillators time to stabilize.
+1.8V DDINT +3.3V DDEXT
10F

CC

V DDEXT

V DDINT

ADM809-RART
RESET RESET

ADSP-21161

a
S
GND

GND

Figure 13-4. Simple Reset Generator Another part, the ADM706TAR, provides power on RESET and optional manual RESET. It allows designers to create a more complete supervisory circuit that monitors the supply voltage. Monitoring the supply voltage allows the system to initiate an orderly shutdown in the event of power failure. The ADM706TAR also allows designers to create a watchdog timer that monitors for software failure. This part is available in an eight lead SOIC package. Figure 13-5 shows a typical application circuit using the ADM706TAR.

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VDDEXT +3.3V VSENSE 100nF

10F VDDEXT 100nF

2 Vt=+1.25V 4 1 6 RESET

VCC PFI MR WDI

RST PFO WDO GND

7 5 8 3

RESET IRQ0 IRQ1 FLAG0

ADSP-21161

a
S

ADM706TAR

GND

Figure 13-5. Reset Generator and Power Supply Monitor

Interrupt and Timer Pins

The ADSP-21161 processors external interrupt pins, flag pins, and timer pin can be used to send and receive control signals to and from other devices in the system. Hardware interrupt signals are received on the IRQ2-0 pins. Interrupts can come from devices that require the processor to perform some task on demand. A memory-mapped peripheral, for example, can use an interrupt to alert the processor that it has data available. For more information, see Interrupts and Sequencing on page 3-34. The TIMEXP output is generated by the on-chip timer. It indicates to other devices that the programmed time period has expired. For more information, see Timer and Sequencing on page 3-50.

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Core-Based Flag Pins

The FLAG3-0 pins allow single-bit signalling between the processor and other devices. For example, the ADSP-21161 processor can raise an output flag to interrupt a host processor. Each flag pin can be programmed to be either an input or output. In addition, many instructions can be conditioned on a flags input value, enabling efficient communication and synchronization between multiple processors or other interfaces. The flags are bidirectional pins, each with the same functionality. The bits in the MODE2 register program the direction of each flag pin. For more information, see Mode Control 2 Register (MODE2) on page A-10.
FLGxO

Flag Inputs When a flag pin is programmed as an input, its value is stored in a bit in the FLAGS register. The bit is updated in each cycle with the input value from the pin. Flag inputs can be asynchronous to the processor clock, so there is a one-cycle delay before a change on the pin appears in FLAGS (if the rising edge of the input misses the setup requirement for that cycle). For more information, see Flag Value Register (FLAGS) on page A-37. An flag bit is read-only if the flag is configured as an input. Otherwise, the bit is readable and writable. The flag bit states are conditions that code can specify in conditional instructions. Flag Outputs When a flag is configured as an output, the value on the pin follows the value of the corresponding bit in the FLAGS register. A program can set or clear the flag bit to provide a signal to another processor or peripheral. The FLAG outputs transition on rising edge of CLKIN. Because the processor core operates at least twice the frequency of CLKIN, the programmer must hold the FLAG state stable for at least one full CLKIN period, to insure that

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the output changes state. Figure 13-6 describes the relationship between instruction execution and a Flag pin, when the processor core to bus clock ratio is set to 2:1. Figure 13-6 also describes the flag in/out process. Note that at least two instructions execute each CLKIN cycle.
BIT SET MODE2 FLG0; BIT CLR FLAGS FLG0; BIT SET FLAGS FLG0; NOP; BIT CLR FLAGS FLG0; BIT CLR MODE2 FLG0; NOP; NOP; /* 1st cycle: set FLAG0 to output in Mode2 */ /* clear FLAG0 */ /* 1st cycle: set FLAG0 output high */ /* 2nd cycle: FLAG register updated here */ /* A NOP indicates a NOP or another instruction not related to FLAG. */ /* 2nd cycle: clear FLAG0 output */ /* earliest assertion of FLAG0 output, depends on CLKOUT phase */ /* 3rd cycle: set FLAG0 back to input */ /* 3rd cycle: */ /*4th cycle: earliest deassertion of FLAG0 output */
3RD CLKOUT CYCLE: 4TH CLKOUT CY CLE: 5TH CLKOUT CY CLE:

1ST C LKOUT CYCLE:

2ND CLKOUT CYCLE:

C LKOUT

OUTPUT ENABLED

FLA G HIGH

FLAG LOW

OUTPU T DISABLED, INPUT SAMPLE D

FLAGX

OUTPU T VALID

Figure 13-6. Flag Timing (At 2:1 Clock Ratio)

Programmable I/O Flags

The IOFLAG register is an IOP register created specifically for controlling the input/output flag pins. When a flag is configured as an output, the value on the pin follows the value of the corresponding bit in the FLAGS register. A program can set or clear the flag bit to provide a signal to another processor or peripheral. Some examples of assembly language instructions that demonstrate the use of macros to configure flag pins have been included at the end of this section. ADSP-21161 SHARC Processor Hardware Reference 13-35

Pin Descriptions

The ADSP-21161 processor has an additional eight IOP based general-purpose programmable input/output flag pins - FLAG[11:4]. As outputs, these pins can signal peripheral devices; as inputs, these pins can provide the test for conditional branching. These pins correspond to the FLAG11-4 pins listed in the datasheet of the device. All FLAG pins are configured as inputs on reset. When configuring IOFLAG register flag pins as outputs, do not set FLGx bits 0 to 7 in the same instruction cycle that the flag is configured as an output (setting the FLGxO bits 8 to 15 in the IOFLAG register). If your application requires that the flags be set after they are configured as outputs, two writes to the IOFLAG register are needed: one to configure the flag pin as an output, and another to set the flag pin high. The functionality of the FLAG11-4 pins is similar to that of the FLAG3-0 except for both the status and control information are included in one register, IOFLAG. The control and status bits for the FLAG3-0 are in the MODE2 register and FLAGS register, respectively. Bits 0-7 of IOFLAG reflect the status of the FLAG pins while bits 15-8 control the direction (input or output) of these flags. A value of 0 programs the flag as an input and a value of 1 programs it as an output. Although you cannot execute bit wise operations such as BIT TST, BIT CLR, on these flags directly in memory, you can execute these operations by first writing to a system register such as the USTAT1 - USTAT4. Figure 13-7 shows the IOFLAG register.

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31 30 29 28 27 26 25 24 23 22 21 20

19 18 17 16 0 0 0 0

IOFLAG
0x1B

15 14 0 0

13 12 0 0

11 10 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

FLG11O
0=FLAG11 Input 1=FLAG11 Output

FLG4
FLAG4 Value (Low=0, High=1)

FLG10O
0=FLAG10 Input 1=FLAG10 Output

FLG5
FLAG5 Value

FLG9O
0=FLAG9 Input 1=FLAG9 Output

FLG6
FLAG6 Value

FLG8O
0=FLAG8 Input 1=FLAG8 Output

FLG7
FLAG7 Value

FLG7O
0=FLAG7 Input 1=FLAG7 Output

FLG8
FLAG8 Value

FLG6O
0=FLAG6 Input 1=FLAG6 Output

FLG9
FLAG9 Value

FLG50
0=FLAG5 Input 1=FLAG5 Output

FLG10
FLAG10 Value

FLG40
0=FLAG4 Input 1=FLAG4 Output

FLG11
FLAG11 Value

Figure 13-7. IOFLAG Register Example #1: Configuring FLGx as Output Flags The following example shows how to configure the flags as output flags, set the flag pins high and write the bits to the IOFLAG register:
ustat2 = 0x00000000; bit set ustat2 FLG9O|FLG8O|FLG7O|FLG6O|FLG5O|FLG4O; dm(IOFLAG) = ustat2;

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After writing to the register, the flags can be toggled with the bit command:
bit tgl ustat2 FLG9|FLG8|FLG7|FLG6|FLG5|FLG4; dm(IOFLAG) = ustat2;

tgl

Example #2: Configuring FLGx as Input Flags The following example shows how to configure the flags as input flags, clear the flag pins, and write the modified flag settings to the IOFLAG register:
ustat2 = 0x00000000; bit clr ustat2 FLG9O|FLG8O|FLG7O|FLG6O|FLG5O|FLG4O; dm(IOFLAG) = ustat2;

System Design Considerations for Flags

Normally, if a flag is sampled or driven periodically, latency issues with respect to when flag pin change occurs are not a concern to the programmer. However, since the flag pins are sampled or driven with respect to the rising edge of CLKOUT (or CLKIN if CLKDBL is disabled), it is important that the application program allows enough time in certain programming situations for the flag state to be driven or sampled in the CLKOUT cycle boundary. This is especially true if the flags states are driven at a (core-clock) rate faster than the completion of the CLKOUT cycle boundary. The same also applies for the external device driving the flag pin as an input. The external device must drive the flag pin for at least 1 CLKOUT cycle to guarantee that it is latched properly by the processor. When setting (or toggling flag pins) in a loop, you must insert extra NOPs instructions to prevent an overrun of setting and clearing a flag pin every cycle (or every other cycle for the IOFLAG register flag pins). For example, if you are using 2:1 mode, the CCLK runs twice as fast as CLKOUT. Depending on where the CLKOUT cycle boundary is with respect to the instruction writing to I/O flag register, the processor can take up to two CCLK cycles 13-38 ADSP-21161 SHARC Processor Hardware Reference

System Design

before that change is received external to the processor based on the rising edge of CLKOUT. The same cycle effect applies to the 3:1 and 4:1 clock ratios. For the 3:1 clock ratio, the processor requires up to three CCLK cycles before the change is received external to the processor based on the rising edge of CLKOUT. For the 4:1 clock ratio, the processor requires up to four CCLK cycles. Since a core stall does not occur when writing to or reading from FLAG pins synchronized to the slower ADSP-21161 processor system clock, NOP instructions are required. In this case, write extra NOPs to ensure overruns do not occur in the higher clock rates. The ADSP-21161 processor samples FLAG inputs at the CLKIN frequency except when CLKDBL is enabled. When CLKDBL is enabled, the processor samples FLAG inputs at the CLKOUT frequency. FLAG outputs must be held stable for at least one full CLKIN cycle. Figure 13-9 shows the delay in setting (or toggling the flag pins) for clock modes 2:1, 3:1, and 4:1.

CCLK BIT SET USTAT BIT CLEAR USTAT DM (IOFLAG) =USTAT

DM (IOFLAG) =USTAT

CLKOUT 2:1

CLKOUT 3:1

CLKOUT 4:1

Figure 13-8. Delay in Setting Flag Pins for Clock Modes 2:1, 3:1 and 4:1

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Example #3: Programming 2:1 Clock Ratio The following example shows how to program an IOFLAG output with a 2:1 CCLK to CLKOUT ratio:
LCNTR = 100, DO flag_toggle UNTIL LCE; bit tgl ustat1 FLG4O; flag_toggle: dm(IOFLAG) = ustat1;

Since a CLKOUT transition occurs every two CCLK instruction cycles, no additional NOP instructions are required. Example #4: Programming 3:1 Clock Ratio The following example shows how to set an IOFLAG output with 3:1 CCLK to CLKOUT ratio:
LCNTR = 100, DO flag_toggle UNTIL LCE; bit tgl ustat1 FLG4O; dm(IOFLAG) = ustat1; flag_toggle:nop;

Since a CLKOUT transition occurs every three CCLK instruction cycles, one NOP instruction is required to prevent the flag output overrun. Example #5: Programming 4:1 Clock Ratio The following example shows how to set an IOFLAG output with 4:1 CCLK to CLKOUT ratio:
LCNTR = 100, DO flag_toggle UNTIL LCE; bit tgl ustat1 FLG4O; dm(IOFLAG) = ustat1; nop; flag_toggle:nop;

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JTAG Interface Pins

The JTAG test access port consists of the TCK, TMS, TDI, TDO, and TRST pins. The JTAG port can be connected to a controller that performs a boundary scan for testing purposes. This port is also used by the Analog Devices Tools product line of JTAG emulator and development software to access on-chip emulation features. To allow the use of the emulator, a connector for its in-circuit probe must be included in the target system. For more information, see Designing For JTAG Emulation on page 13-49. If TRST is not asserted (or held low) at power-up, the JTAG port is in an undefined state that may cause the processor to drive out on I/O pins that would normally be three-stated at reset. TRST can be held low with a jumper to ground on the target board connector.

Dual-Voltage Power-up Sequencing

The ADSP-21161 dual-voltage processor has special considerations related to power-up. Note that these are general recommendations, and specifics details on dual voltage power supply systems is beyond the scope of this book. When the system power is activated through the processors dual power supply system, both supplies should be brought up as quickly as possible. Ideally, the two supplies, VDDEXT and VDDINT should be powered up simultaneously. Many commercially available dual supply regulators address simultaneous powerup requirements of the core and I/O. When designing a dual supply system, the designer should consider the relative voltage and ramp-up timing between the core and I/O voltages in order to avoid potential issues with long-term reliability.

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Dual-Voltage Power-up Sequencing

The ADSP-21161 I/O pads have a network of internal diodes to protect the processor from damage by electrostatic discharge. These protection diodes connect the 1.8 V core and 3.3 V I/O supplies internally. Figure 13-9 shows how a network of protection diodes isolates the internal supplies and provides ESD protection for the I/O pins. During the power-up sequence of the processor, differences in the ramp up rates and activation time between the two supplies can cause current to flow in the I/O ESD protection circuitry. When applying power separately to the VDDEXT or VDDINT pins, take precautions to prevent or limit the maximum current and duration conducted through the isolation diodes if the un powered pins are at ground potential. Since the ESD protection diodes connect the 1.8 V core and 3.3 V I/O supplies internally, these diodes can be damaged at any time the 1.8 V core supply voltage is present without the presence of the 3.3 V I/O supply.

VDDEXT ( -3.3 V)

VDDINT (1 .8V )

ADSP-21161

I/O PIN

INPUT

INTERNAL LOGIC O UTPUT

Figure 13-9. Protection Diodes and IO Pin ESD Protection

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The ESD protection diodes connect the 1.8 V core and 3.3 V I/O supplies internally. Improper supply sequencing can cause damage to the ESD protection circuitry. If the 1.8 V supply is active for prolonged periods of time before the 3.3 V I/O supply is activated, there is a significant amount of loading on the I/O pins. Damage occurs because the I/O is powered from the 1.8 V supply through the ESD diodes. To prevent this damage to the ESD diode protection circuitry, Analog Devices recommends including a bootstrap Schottky diode. The bootstrap Schottky diode connected between the 1.8 V and 3.3 V power supplies protects the ADSP-21161 from partially powering the 3.3 V supply. Including a Schottky diode shortens the delay between the supply ramps and thus prevent damage to the ESD diode protection circuitry. With this technique, of the 1.8 V rail rises ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail along with the 1.8 V rail. For many power supply system designers, it may be easier to design the PLL clock gate workaround instead of shortening the VDDINT ramp time. Moving between revisions does not require any hardware modifications to gate the clock. As long as the tCLKVDD startup requirement is met then a reliable start-up reset of the PLL for revision 1.0/1.1 is assured. This requirement guarantees that the CLKIN source is present within 200 ms after the supplies are ramped. See the ADSP-21161N DSP Microcomputer Data Sheet for timing specifications. Holding off CLKIN up to a maximum of 200 ms is allowed. Figure 13-10 shows a basic block diagram of the Schottky diode connected between the core and I/O voltage regulators and the processor. The anode of the diode must be connected to the 1.8 V supply. The diode must have a forward biased voltage of 0.6 V or less and must have a current rating sufficient to supply the 3.3 V rail of the system. The use of a Schottky diode is the recommended method suggested by Analog Devices.

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DC input source

3.3V I/O Voltage Regulator

VDDEXT

ADSP -21161

1.8V Core Voltage Regulator

VDDINT

Figure 13-10. Dual 1.8 V/3.3 V Supplies With a Schottky Diode For recommendations on managing power-up sequencing for the core I/O dual voltage supply, refer to the Powerup Sequencing specifications in the ADSP-21161N SHARC DSP Microcomputer Data Sheet.

PLL Start-Up (Revisions 1.0/1.1)

Two circuit blocks are included in the PLL start-up circuit to enable the PLL to lock effectively on start-up: a Power On Reset (POR) circuit and a 9-bit CLKIN counter. Figure 13-11 shows silicon revision 1.0/1.1 startup block diagram. Power On Reset (POR) Circuit The POR circuit monitors the voltage level on VDDINT power supply and then generates a PLL pulse. This drives the PLL reset input circuit to reset the PLL to a default state. Figure 13-12 shows an example power-up and power-down waveform of VDDINT. The POR circuit tracks this voltage internally to generate a PLL reset pulse. The actual POR output pulse,

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VDDINT

POR
Output POR pulse is generated when VDDINT is between 0 and 1.2V

PLL_RESET

PLL
CLKIN ENA_CLK

9-BIT COUNTER CLKIN

CLKIN CLKIN_ENA

Internal Core

RESET

Processor Reset

Figure 13-11. Power On Reset Circuit Revisions 1.0 and 1.1

PLL_RESET, VDDINT

is generated as an active high pulse from the point at which begins to ramp up from 0 V. It is deactivated when VDDINT reaches

1.2 V. For revisions 1.0 and 1.1, VDDINT must ramp from 0 V to 1.8 V within 2 ms for the POR circuit to properly generate a PLL reset pulse Figure 13-12 shows three PLL reset-related input signals: the top one is VDDINT, the bottom two are derived from VDDINT and are related to the POR circuit. The POR input tracks VDDINT up to 1.2 V before it drops down. This is used to generate the PLL reset pulse. As the input is rising to 1.2 V, the output of the POR generates the reset pulse for the PLL. After the POR input voltage reaches 1.2 V, the POR voltage drops off, which then deactivates the reset pulse connected to the PLL. The duration of the POR circuit being driven active low is from 0 V to 1.2 V. If the system is powering down VDDINT and coming back up again, there are a few requirements that must be met to properly generate a PLL reset pulse on the subsequent powerup. First, the POR circuit requires

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Dual-Voltage Power-up Sequencing

that VDDINT voltage level is below 0.5 V. Secondly, re-ramp from 0.5 V to 1.2 V must occur within 1ms to guarantee another generated PLL_RESET pulse. PLL CLKIN Enable Circuit The 9-bit counter counts a certain number of CLKIN cycles before it allows the PLL to begin to lock to the incoming CLKIN frequency. This counter was added to allow the CLKIN source to amplify and oscillate to a stable fundamental frequency before the PLL begins to try to lock to the incoming frequency.

1 ms 3 ms

1.2 Volts VDDINT POR Input PLL_RESET (POR Output) 0.5 Volts

Figure 13-12. PLL Reset Because oscillator or crystal startup times can range from 5 to 10 ms, the internal 512 cycle counter in some startup cases does not allow the CLKIN oscillator source to run at its locked oscillator fundamental frequency before the PLL clock input is enabled. Some oscillators might have a slow frequency ramp up time for 10 ms.

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The revision 1.0 and 1.1 PLL can fail to lock or fail to continue to run if the CLKIN frequency goes below 15 MHz for more than 20 s or when using CLKDBL, the minimum CLKIN frequency cannot be less than 7.5 MHz. There are two ways in which the PLL can be reset for revisions 1.0 and 1.1: Ensure that the VDDINT ramp rate time is met (< 2 ms) with a stable CLKIN frequency applied when the POR circuit is enabled. When using an external clock oscillator powered by the VDDEXT supply, bring up VDDEXT for a recommended 25 ms before enabling VDDINT. This allows the external CLKIN source to come up and stabilize before the VDDINT power supply is brought up. The VDDINT POR circuit then activates and generates a PLL pulse. Hold off or gate the CLKIN source until the VDDINT/VDDEXT supplies are known to be stable. This negates the VDDINT ramp rate requirement if VDDINT is exceeding 2 ms. Holding off CLKIN low or high until the supplies are stable also resets the internal PLL circuitry and allows the PLL to start reliably. Once, the processor is up and running, if you stop the CLKIN source, the PLL can lock up and not restart when CLKIN is reapplied. If there is a brown-out situation in your system, the watchdog circuit power-downs to at least 0.5 V and power-up of the VDDINT supply within 1.0ms (to restart the POR circuit).

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PLL Start-Up (Revision 1.2)

The PLL reset input and PLL CLKIN enable input directly to the RESET pin (Figure 13-13). This allows a PLL reset on the RESET rising edge. The RESET pin can be held low long enough to guarantee a stable CLKIN source and stable VDDINT/VDDEXT power supplies before the PLL is reset.
PLL reset and PLL clock input enable occur on the rising edge of RESET

RESET

PLL_RESET ENA_CLK

CLKIN Core Reset Delay Circuit

ENA_CNT CLKIN CORE_RST

CLKIN

PLL

12-bit Counter Count 4096 CLKIN Cycles

Delayed Internal Core Processor Reset

RSTOUT

Figure 13-13. Power On Reset Circuit Revisions 1.2 The PLL must lock to the CLKIN frequency (around 100 s). Because the PLL resets on the rising edge of RESET, the PLL needs time to lock to CLKIN before the core can execute or begin the boot process. A delayed core reset has been added via the delay circuit. There is a 12-bit counter that counts up to 4096 CLKIN cycles after RESET is transitioned from low to high. The delay circuit is activated at the same time the PLL is reset. A secondary RSTOUT pin (B15 which previously was a NC) has been added to allow system designers the option to have the ADSP-21161 processor reset another device after the core is reset. Note that as in previous silicon revisions, the CLKOUT is active during a reset. During reset the processor is in PLL BYPASS mode. CLKOUT frequency during reset depends upon CLKDBL pin. During reset if CLKDBL is HIGH then CLKOUT frequency = 1/4 of CLKIN frequency and if CLKDBL = LOW then CLKOUT frequency = 1/2 of CLKIN frequency.

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The advantage of the delayed core reset is that the PLL can be reset any number of times without having to power-down the system. If there is a brown-out situation, the watchdog circuit only has to control the RESET pin to restart the PLL.

Designing For JTAG Emulation

The Analog Devices Tools product line of JTAG emulator is a development tool for debugging programs running in real time on target system hardware. The Analog Devices Tools product line of JTAG emulators provides a controlled environment for observing, debugging, and testing activities in a target system by connecting directly to the target processor through its JTAG interface. Because the Analog Devices Tools product line of JTAG emulator controls the target systems processor through the processors IEEE 1149.1 JTAG Test Access Port (TAP), non-intrusive in-circuit emulation is assured. The emulator uses the TAP to access the internal space of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, examine registers, and so on. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the system is set running at full speed with no impact on system timing.The emulator does not impact target loading or timing. The emulators in-circuit probe connects to a variety of host computers (PCI bus, or USB) with plug-in boards. Target systems must have a 14-pin connector in order to accept the Analog Devices Tools product line of JTAG emulator in-circuit probe, a 14-pin plug. Designs must add this connector to the target board if the board is intended for use with the ADSP-21161 processor JTAG Emulator. The total trace length between the JTAG connector and the furthest device sharing the emulators JTAG pins should be limited to 15 inches maximum for guaranteed operation. This length restriction must include the ADSP-21161 SHARC Processor Hardware Reference 13-49

Designing For JTAG Emulation

emulators JTAG signals, which are routed to one or more ADSP-21161 processor devices, or a combination of ADSP-21161 processor devices and other JTAG devices on the chain.

Target Board Connector

The emulator interface to an Analog Devices JTAG processor is a 14-pin header, as shown in Figure 13-14. The customer must supply this header on their target board in order to communicate with the emulator. The interface consists of a standard dual row 0.025" square post header, set on 0.1" x 0.1" spacing, with a minimum post length of 0.235". Pin 3 is the key position used to prevent the pod from being inserted backwards. This pin must be clipped on the target board. The clearance (length, width, and height) around the header must be as shown in Figure 13-19 on page 13-57. Maintain a minimum length of 0.15" and width of 0.10" for the target board header. The pod connector attaches the target board header in this area. Therefore, there must be clearance to attach and detach this connector. See the JTAG Pod Connector on page 13-57 for detailed drawings of the pod connector. As can be seen in Figure 13-14, there are two sets of signals on the header, including the standard JTAG signals TMS, TCK, TDI, TDO, TRST, EMU used for emulation purposes (via an emulator). Secondary JTAG signals BTMS, BTCK, BTDI, and BTRST are provided for optional use for board-level (boundary scan) testing. While they are rarely used, the B signals should be connected to a separate on-board JTAG boundary scan controller, if they are used. If the B signals are not used, tie them to ground as shown in Figure 13-15. can alternately be activated (for some older silicon) to VCC (+5 V, +3.3 V, or +2.5 V) using a 4.7 K resistor, as described in previous documents. Tying the signal to ground is universal and works for all silicon.
BTCK

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Figure 13-14. Emulator Interface for Analog Devices JTAG Processors When the emulator is not connected to this header, jumpers should be placed across BTMS, BTCK, BTRST, and BTDI as shown in Figure 13-15. This holds the JTAG signals in the correct state to allow the ADSP-21161 processor to run freely. All the jumpers should be removed when connecting the emulator to the JTAG header. For a list of the state of each standard JTAG signal refer to Table 13-11. Use the following legend: O=Output, I=Input, and NU=Not Used. The ADSP-21161 processor CLKIN signal is the clock signal line (typically 30 MHz or greater) that connects an oscillator to all processors in multiple processor systems requiring synchronization. In order for synchronous operations to work correctly the CLKIN signal on all the processors must be the same signal and the skew between them must be minimal (use clock drivers, or other means).

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Designing For JTAG Emulation

Figure 13-15. JTAG Target Board Connector With No Local Boundary Scan Table 13-10. State of Standard JTAG Signals
Signal TMS TCK TRST TDI TDO EMU CLKIN Description Test Mode Select Test Clock (10 MHz) Test Reset Test Data In Test Data Out Emulation Pin Processor Clock Input Emulator O O O O I I NU ADSP-21161 I I I I O O (Open Drain) I

Note that the CLKIN signal is not used by the emulator and can cause noise problems if connected to the JTAG header. Legacy documents show it connected to pin 4 of the JTAG header. Pin 4 should be tied to ground on the 14-pin JTAG header (do not connect the JTAG header pin to the pro-

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cessors CLKIN signal). If you have already connected it to the JTAG header pin, and are experiencing noise from this signal, simply clip this pin on the 14-pin JTAG header. The final connections between a single processor target and the emulation header (within 6 inches) are shown in Figure 13-16. A 4.7 K pull-up resistor has been added on TCK, TDI and TMS for increased noise resistance.

Figure 13-16. Single Connection to the JTAG Header If a design uses more than one processor (or other JTAG device in the scan chain), or if the JTAG header is more than 6 inches from the processor, use a buffered connection scheme as shown in Figure 13-17 on

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Layout Requirements

page 13-55 (no local boundary scan mode shown). To keep signal skew to a minimum, be sure the buffers are all in the same physical package (typical chips have 6, 8, or 16 drivers). Using a buffer that includes a series of resistors such as the 74ABT2244 family can reduce ringing on the JTAG signal lines. For low voltage applications (3.3 V, 2.5 V, and 1.8 V I/O), the 74ALVT, and 74AVC logic families is useful. Also, note the position of the pull-up resistor on EMU. This is required since the EMU line is an open drain signal. If more than one processor (or JTAG device) is on the target (in the scan chain), you must buffer the JTAG header. This keeps the signals clean and avoids noise problems that occur with longer signal traces (ultimately resulting in reliable emulator operation). Although the theoretical number of devices that can be supported (by the software) in one JTAG scan chain is large (50 devices or more) it is not recommended that you use more than eight physical devices in one scan chain. A physical device could however contain many JTAG devices such as inside a multi-chip module. The recommendation of not more than eight physical devices is mostly due to the transmission line effects that appear in long signal traces, and based on some field-collected empirical data. The best approach for large numbers of physical devices is to break the chain into several smaller independent chains, each with their own JTAG header and buffer. If this is not possible, at least add some jumpers that can reduce the number of devices in one chain for debug purposes, and pay special attention in the layout stage for transmission line effects.

Layout Requirements
All JTAG signals (TCK, TMS, TDI, TDO, EMU, TRST) should be treated as critical route signals. Specify a controlled impedance requirement for each route (value depends on your circuit board, typically 50-75 ). Keeping crosstalk and inductance to a minimum on these lines by using a good ground plane and by routing away from other high noise signals such as

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Figure 13-17. Multiple Connection to JTAG Header clock lines is also important. Keep these routes as short and clean as possible, and keep the bused signals (TMS, TCK, TRST, EMU) as close to the same length as possible. The JTAG TAP relies on the state of the TMS line and the TCK clock signal. If these signals have glitches (due to ground bounce, crosstalk, etc.) unreliable emulator operation results. When experiencing emulator problems, look at these signals using a high-speed digital oscilloscope. These lines must be clean, and may require special termination schemes. If you are buffering the JTAG header (most applications do) you must provide signal termination appropriate for your target board (series, parallel, R/C, etc.).

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Power Sequence for Emulation

Power Sequence for Emulation

The power-on sequence for your target and emulation system is as follows: 1. Apply power to the emulator first, then to the target board. This ensures that the JTAG signals are in the correct state for the ADSP-21161 processor to run free. 2. Upon power-on, the emulator drives the TRST signal low, keeping the processor TAP in the test-logic-reset state, until the emulation software takes control. Removal of power should be done in reverse: Turn off power to the target board then to the emulator.

Additional JTAG Emulator References

The IEEE 1149.1 JTAG standard is sponsored by the Test Technology Standards Committee of the IEEE Computer Society, and published by the IEEE. The latest versions at the time of this publication are IEEE Standard. 1149.1-1990 and IEEE Standard 1149.1a-1993. To order a copy, call the IEEE at 1-800-678-4333 in the US and Canada, 1-908-981-1393 outside of the US and Canada. Visit the IEEE standards web site at http://standards.ieee.org/.

Pod Specifications
This section contains design details on various emulator pod designs by the Analog Devices Tools product line. The emulator pod is the device that connects directly to the target board 14-pin JTAG header. See also Engineer-to-Engineer Notes EE-68.

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JTAG Pod Connector

Figure 13-18 details the dimensions of the JTAG pod connector at the 14-pin target end. Figure 13-19 displays the keep-out area for a target board header. The keep-out area allows the pod connector to properly seat onto the target board header. This board area should contain no components (chips, resistors, capacitors, and so on). The dimensions are referenced to the center of the 0.25 square post pin.

Figure 13-18. JTAG Pod Connector at the 14-pin Target End

Figure 13-19. Keep-Out Area for a Target Board Header

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Pod Specifications

3.3 V Pod Logic

A portion of the Analog Devices Tools product line 3.3 V emulator pod interface is shown in Figure 13-20. This figure describes the driver circuitry of the emulator pod. As can be seen, TMS, TCK and TDI are driven with a 33 series resistor. TRST is driven with a 100 series resistor. The TDO and CLKIN pins are terminated with an optional 91/120 parallel terminator. The EMU signal is pulled up with a 4.7 K resistor. The 74LVT244 chip drives the signals at 3.3 V, with a maximum current rating of 32 mA.

Figure 13-20. 3.3V JTAG Pod Driver Logic Parallel terminate the TMS, TCK, TRST, and TDI lines locally on your target board, if needed, since they are driven by the pod with sufficient current drive (32 mA). In order to use the terminators on the TDO line (CLKIN is not used), you MUST have a buffer on your target board JTAG header.

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The ADSP-21161 processor is not capable of driving the parallel terminator load directly with TDO. Assuming the proper buffers are included, use the optional parallel terminators by placing a jumper on J2.

2.5 V Pod Logic

A portion of the Analog Devices Tools product line 2.5 V emulator pod interface is shown in Figure 13-21. This figure describes the driver circuitry of the emulator pod. As can be seen, the TMS, TCK, and TDI liness are driven with a 33 series resistor. The TRST signal is driven with a 100 series resistor. The TDO line is pulled up with a 4.7 K resistor and terminated with an optional parallel terminator that can be configured by the user. EMU is pulled up with a 4.7 K resistor. The CLKIN signal is not used and not connected inside the pod. The 74ALVT16244 chip drives the signals at 2.5 V, with a maximum current rating of 8 mA.

Figure 13-21. 2.5 V JTAG Pod Driver Logic

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Conditioning Input Signals

You can terminate the TMS, TCK, TRST, and TDI lines locally on your target board, if needed, as long as the terminators current use does not exceed the driver's maximum current supply (8 mA). In order to use the terminator on the TDO line, include a buffer on your target board JTAG header. The ADSP-21161 processor is not capable of driving a parallel terminator load (typically 50-75 ) directly with TDO. Assuming you have the proper buffers, you may use the optional parallel terminator by adding the appropriate resistors and placing a jumper on J2.

Conditioning Input Signals

The ADSP-21161 processor is a CMOS device. It has input conditioning circuits which simplify system design by filtering or latching input signals to reduce susceptibility to glitches or reflections. The following sections describe why these circuits are needed and their effect on input signals. A typical CMOS input consists of an inverter with specific N and P device sizes that cause a switching point of approximately 1.4 V. This level is selected to be the midpoint of the standard TTL interface specification of VIL =0.8 V and VIH =2.0 V. This input inverter, unfortunately, has a fast response to input signals and external glitches wider than about 1 ns. Filter circuits and hysteresis are added after the input inverter on some processor inputs, as described in the following sections.

Link Port Input Filter Circuits

The ADSP-21161 processors link port input signals have on-chip filter circuits rather than glitch rejection circuits. Filtering is not used on most signals because it delays the incoming signal and the timing specifications.

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Filtering is implemented only on the link port data and clock inputs. This is possible because the link ports are self-synchronized. The clock and data are sent together. It is not the absolute delay but rather the relative delay between clock and data that determines performance margin. By filtering both LxCLK and LxDAT7-0 with identical circuits, response to LxCLK glitches and reflections are reduced but relative delay is unaffected. The filter has the effect of ignoring a full strength pulse (a glitch) narrower than approximately 2 ns. Glitches that are not full strength can be somewhat wider. The link ports do not use glitch rejection circuits because they can be used with longer, series-terminated transmission lines where the reflections do not occur near the signal transitions.

RESET Input Hysteresis

Hysteresis is used only on the RESET input signal. Hysteresis causes the switching point of the input inverter to be slightly above 1.4 V for a rising edge and slightly below 1.4V for a falling edge. The value of the hysteresis is approximately 0.1 V. The hysteresis is intended to prevent multiple triggering of signals which are allowed to rise slowly, as might be expected on a reset line with a delay implemented by an RC input circuit. Hysteresis is not used to reduce the effect of ringing on input signals with fast edges, because the amount of hysteresis that can be used on a CMOS chip is too small to make much difference. The small amount of hysteresis allowable is due to the restrictions on the tolerance of the VIL and VIH TTL input levels under worst case conditions. Refer to the data sheet for exact specifications.

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Designing For High Frequency Operation

Designing For High Frequency Operation

Because the processor can operate at very fast clock frequencies, signal integrity and noise problems must be considered for circuit board design and layout. The following sections discuss these topics and suggest various techniques to use when designing and debugging ADSP-21161 processor systems. All synchronous behavior is specified to CLKIN. System designers are encouraged to clock synchronous peripherals/memory (which are attached to the external port) with this same clock source (or a different low-skew output from the same clock driver). Alternatively, the clock output (CLKOUT) from the processor may be employed to clock synchronous peripherals/memory. Note the following behavior for CLKOUT: 1. The processor whose ID2-0=000 (uniprocessor), or 001 drives CLKOUT during reset. 2. is specified relative to CLKIN in the ADSP-21161N DSP Microcomputer Data Sheet. When using this output to clock system components, the phase and jitter terms associated with this output must be treated as additional derating factors in determining specs. The use of CLKOUT as a clock source to SBSRAMs can result in negative hold times and is not recommended.
CLKOUT

3. For systems not needing CLKOUT as a clock source, CLKOUT may be used to identify the current bus master. This requires that the outputs not be tied together. If and when this debug feature is not needed, the CLKOUT output can be disabled by setting the COD bit in the SYSCON register. The bus master can be identified by checking the BMSTR pin.

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Clock Specifications and Jitter

The clock signal must be free of ringing and jitter. Clock jitter can easily be introduced in a system where more than one clock frequency exists. High frequency jitter on the clock to the processor may result in abbreviated internal cycles. As shown in Figure 13-22, keep the portions of the system that operate at different frequencies as physically separate as possible. The clock supplied to the ADSP-21161 processor must have a rise time of 3 ns or less and must meet or exceed a high and low voltage of 2.3 V and 0.8 V, respectively.

FREQUENCY 1

CLOCK

ADSP-21160

a
S

NO CONNECT

NO CONNECT

Figure 13-22. Reducing Clock Jitter and Ring Never share a clock buffer IC with a signal of a different clock frequency. This introduces excessive jitter.

Clock Distribution
There must be low clock skew between processors in a multiprocessor cluster when communicating synchronously on the external bus. The clock must be routed in a controlled-impedance transmission line that can be properly terminated at either the end of the line or the source.

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Designing For High Frequency Operation

Figure 13-23 illustrates end-of-line termination for the clock. End-of-line termination is not usually recommended unless the distance between the processors is extremely small, because devices that are at a different wire distance from each other receive a skewed clock. This is due to the propagation delay of a PCB transmission line, which is typically 5 to 6 inches/ns.

CLOCK

+5 V

50 TRANSMISSION LINE

180

1.4V

70

ADSP-21160

a
S

ADSP-21160

a
S

ADSP-21160

a
S

Figure 13-23. End-Of-Line Termination for the Clock Caution Figure 13-24 illustrates source termination for the clock. Source termination allows delays in each path to be identical. Each device must be at the end of the transmission line because only there does the signal have a single transition. The traces must be routed so that the delay through each is matched to the others. Line impedance higher than 50 may be used, but clock signal traces should be in the PCB layer closest to the ground plane to keep delays stable and crosstalk low. More than one device may be at the end of the line, but the wire length between them must be short and the impedance (capacitance) of these must be kept high. The matched

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OCT AL INVE R T E R

ACT Q240 (NAT IONAL S E MICONDUCT OR ) OR IDT 49F CT 805/A OR CY7C992 40 50 TRANSMISSION LINE

ADS P -21160

a
S

CLOCK

40

50

TRANSMISSION LINE

ADS P -21160

a
S

40

50

TRANSMISSION LINE

ADS P -21160

a
S

BUFFER DRIVE IMPEDANCE = 10 A S E P AR AT E B UF F E R AND T R ANS MIS S ION L INE IS NE E DE D F OR E ACH GR OUP OF PR OCE S S OR S T HAT AR E F UR T HE R T HAN 4 INCHE S F R OM E ACH OT HE R .

Figure 13-24. Use Source Termination to Distribute the Clock inverters must be in the same IC and must be specified for a low skew (< 1 ns) with respect to each other. This skew should be as small as possible because it subtracts from the margin on most specifications.

Point-to-Point Connections
Unlike previous SHARC processors, the ADSP-21161 processor contains internal series resistance equivalent to 50 on all drivers except the CLKIN and XTAL pins. Therefore, for traces longer than six inches, external series resisters on control, data, clock or frame sync pins are not required to

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Designing For High Frequency Operation

dampen reflections from transmission line effects for point-to-point connections. However, for more complex networks such as a star configuration, a series termination is still recommended. Figure 13-26 shows an internal resistance in the driver of 10 . The additional 40 series resister at the driver pad results in a total resistance of 50 . For more specific guidance on related issues, see the reference source in Recommended Reading on page 13-71 for suggestions on transmission line termination. Also, see the ADSP-21161N DSP Microcomputer Data Sheet for output drivers rise and fall time data.

ADS P -21160

a
S
DRIVER IMPEDANCE = 17V ON LINK PORT TRANSMITTER

50 TRANSMISSION LINE, LONGER THAN 6" (15.25 cm)

D RIVE R IMPE DANCE = 17 ? ON L INK P ORT T R ANS MIT TE R

33

33
OF F

OP E N CIRCUIT

L INK P OR T T RANS MIT T E R

ADS P -21160

a
S
OPEN CIRCUIT

OFF REFLECTED WAVE IS ABSORBED AT THE SOURCE. LINK PORT RECEIVER

Figure 13-25. Source Termination for Point-to-Point Connectors For link port operation at the full internal clock rate it is important to maintain low skew between the data (LxDAT7-0) and clock (LxCLK). For full speed operation with a 100 MHz internal clock, a skew of less than 0.5 ns is required. Although the ADSP-21161 processors serial ports may be operated at a slow rate, the output drivers still have fast edge rates.

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Signal Integrity
The capacitive loading on high-speed signals should be reduced as much as possible. Loading of buses can be reduced by using a buffer for devices that operate with wait states, for example DRAMs. This reduces the capacitance on signals tied to the zero-wait-state devices, allowing these signals to switch faster and reducing noise-producing current spikes. Signal run length (inductance) should also be minimized to reduce ringing. Extra care should be taken with certain signals such as the read and write strobes (RD, WR) and acknowledge (ACK). In a multiprocessor cluster, each processor can drive the read or write strobes. In this case, some damping resistance should be put in the signal path if the line length is greater than 6 inches (Figure 13-26). This is at the expense of additional signal delay. The time budget for these signals should be carefully analyzed.

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ADS P-21160

a
S

ADS P -21160

a
S

10

10

10

10

STAR CONNECTION DAMPING RESISTORS

ADS P-21160

a
S

ADS P -21160

a
S

Figure 13-26. Star Connection Damping Resistors

Other Recommendations and Suggestions

The following are some additional suggestions for successfully designing an ADSP-21161 hardware platform. Use more than one ground plane on the PCB to reduce crosstalk. Be sure to use lots of vias between the ground planes. One VDD plane for each supply is sufficient. These planes should be in the center of the PCB. Keep critical signals such as clocks, strobes, and bus requests on a signal layer next to a ground plane and away from or layout perpendicular to other non-critical signals to reduce crosstalk. For example, data outputs switch at the same time that BRx inputs are sampled; if the layout permits crosstalk between them, the system could have problems with bus arbitration.

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Position the processors on both sides of the board to reduce area and distances if possible. Design for lower transmission line impedances to reduce crosstalk and to allow better control of impedance and delay. Use of 3.3 V peripheral components and power supplies to help reduce transmission line problems, because the receiver switching voltage of 1.5 V is close to the middle of the voltage swing. In addition, ground bounce and noise coupling is less. Experiment with the board and isolate crosstalk and noise issues from reflection issues. This can be done by driving a signal wire from a pulse generator and studying the reflections while other components and signals are passive.

Decoupling Capacitors and Ground Planes

Ground planes must be used for the ground and power supplies. Designs should use a minimum of eight bypass capacitors (six 0.1 F and two 0.01 F ceramic) each for IO and core. The capacitors should be placed very close to the VDDEXT and VDDINT pins of the package as shown in Figure 13-27. Use short and fat traces for this. The ground end of the capacitors should be tied directly to the ground plane inside the package footprint of the processor (underneath it, on the bottom of the board), not outside the footprint. A surface-mount capacitor is recommended because of its lower series inductance. Connect the power plane to the power supply pins directly with minimum trace length. The ground planes must not be densely perforated with vias or traces as their effectiveness is reduced. In addition, there should be several large tantalum capacitors on the board. Designs can use either bypass placement case shown in Figure 13-27 or combinations of the two. Designs should try to minimize signal feedthroughs that perforate the ground plane.

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ADSP-21160

a
S

CASE 1: BYPASS CAPACITORS ON NON-COMPONENT (BOTTOM) SIDE OF BOARD, BENEATH DSP PACKAGE

CASE 2: BYPASS CAPACITORS ON COMPONENT (TOP) SIDE OF BOARD, AROUND DSP PACKAGE

Figure 13-27. Bypass Capacitor Placement

Oscilloscope Probes
When making high-speed measurements, be sure to use a bayonet type or similarly short (< 0.5 inch) ground clip, attached to the tip of the oscilloscope probe. The probe should be a low-capacitance active probe with 3 pF or less of loading. The use of a standard ground clip with 4 inches of ground lead causes ringing to be seen on the displayed trace and

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makes the signal appear to have excessive overshoot and undershoot. A 1 GHz or better sampling oscilloscope is needed to see the signals accurately.

Recommended Reading
The text High-Speed Digital Design: A Handbook of Black Magic is recommended for further reading. This book is a technical reference that covers the problems encountered in state-of-the-art, high-frequency digital circuit design, and is an excellent source of information and practical ideas. Topics covered in the book include: High-Speed Properties of Logic Gates Measurement Techniques Transmission Lines Ground Planes and Layer Stacking Terminations and Vias Power Systems Ribbon Cables and Connectors Clock Distribution and Clock Oscillators High-Speed Digital Design: A Handbook of Black Magic, Johnson and Graham, Prentice Hall, Inc., ISBN 0-13-395724-1.

Booting Single and Multiple Processors

Programs can be automatically downloaded to the internal memory of an ADSP-21161 processor after power-up or after a software reset. This process is called booting. The processor supports four booting modes: EPROM, host, SPI, and link port. For cases when the processor must exeADSP-21161 SHARC Processor Hardware Reference 13-71

Booting Single and Multiple Processors

cute instructions from external memory without booting, a No boot mode may also be configured. For information on the setup and DMA processes for booting a single processor, see Bootloading Through The External Port on page 6-70 and Bootloading Through The Link Port on page 6-88 and Bootloading Through the SPI Port on page 6-113. Multiprocessor systems can be booted from a host processor, from external EPROM, through a link port, SPI port, or from external memory. Table 13-11. Booting Modes
Booting Mode EPROM Connect BMS to EPROM chip select Host processor Serial boot via SPI Link port No booting Processor executes from external memory Reserved EBOOT 1 LBOOT 0 BMS Output

0 0 0 0

0 1 1 0

1 (Input) 0 (Input) 1 (Input) 0 (Input)

x (Input)

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Multiprocessor Host Booting

To boot multiple ADSP-21161 processors from a host, each processor must have its EBOOT, LBOOT, and BMS pins configured for host booting: EBOOT=0, LBOOT=0, and BMS=1. After system powerup, each processor is in the idle state and the BRx bus request lines are deasserted. The host must assert the HBR input and boot each processor by: Asserting its CS pin (for asynchronous). The CS pin of all processors can be asserted to select and boot them simultaneously by host broadcast writes. Downloading instructions as described in Booting Another processor on page 7-108

Multiprocessor EPROM Booting

There are two methods of booting a multiprocessor system from an EPROM. Processors perform the following steps in these methods: Arbitrate for the bus DMA the 256-word boot stream, after becoming bus master Release the bus Execute the loaded instructions Booting From a Single EPROM The BMS signals from each processor may be wire-ORed together to drive the chip select pin of the EPROM. Each processor can boot in turn, according to its priority. When the last one has finished booting, it must inform the others (which may be in the idle state) that program execution can begin (if all processors are to begin executing instructions simultaneously). An example system that uses this alternating technique appears in Figure 13-28. When multiple processors boot from one EPROM, the

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processors can boot either identical code or different code from the EPROM. If the processors load differing code, a jump table (based on processor ID) can be used to select the code for each processor.

EBOOT LBOOT

ADDR23-0 DATA23-16 DATA47-16 RD ACK BMS

ADDR DATA RD

ADSP-21161 (S1)

CS

EPROM

ADDR23-0 EBOOT LBOOT DATA47-16 RD ACK

ADDRESS

HERE, MULTIPLE SHARCS BOOT FROM THE SAME EPROM. FOR THIS CONFIGURATION, THE LOADER ROUTINE USES A JUMP TABLE. THIS TABLE INDICATES THE ADDRESS OF THE IMAGE THAT LOADS INTO EACH PROCESSOR. THE PROCESSORS CAN LOAD THE SAME IMAGE OR INDIVIDUAL IMAGES.

ADSP-21161 (S2)

BMS
CONTROL DATA

EBOOT LBOOT

ADDR23-0 DATA47-16 RD ACK

ADSP-21161 (S6)

BMS

Figure 13-28. Alternating Booting From an EPROM Sequential Booting The EBOOT pin of the ADSP-21161 processor with IDx=1 must be set high for EPROM booting. All other processors should be configured for host booting (EBOOT=0, LBOOT=0, and BMS=1), which leaves them in the idle state at startup and allows the processor with IDx=1 to become bus master

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System Design

and boot itself. Only the BMS pin of processor #1 is connected to the chip select of the EPROM. When processor #1 has finished booting, it can boot the remaining processors by writing to their external port DMA buffer 0 (EPB0) via multiprocessor memory space. An example system that uses this sequential technique appears in Figure 13-29.

Multiprocessor Link Port Booting

In systems where multiple processors are not connected by the parallel external bus, booting can be accomplished from a single source through the link ports. To sequentially boot all of the processors, a parallel common connection should be made to link port buffer 0 (LBUF0) on each of the processors. If only a daisy chain connection exists between the processors link ports, then each processor can boot the next one in turn. Link buffer 0 must always be used for booting. If you want to boot multiple processors simultaneously, you must add glue logic to handle multiple LxACK signals.

Multiprocessor Booting From External Memory

If external memory contains a program after reset, then the processor with IDx=1 should be set up for no boot mode. It begins executing from address 0x0020 0004 in external memory. When booting has completed, the other processors may be booted by processor #1 if they are set up for host booting, or they can begin executing out of external memory if they are set up for no boot mode. Multiprocessor bus arbitration allows this booting to occur in an orderly manner. The bus arbitration sequence after reset is described in Multiprocessor Bus Arbitration on page 7-93.

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Data Delays, Latencies, and Throughput

EBOOT LBOOT

ADDR23-0 DATA23-16 DATA47-16 RD ACK B MS

ADDR DATA RD

ADSP-21161 (S1, MASTER) BMS EBOOT LBOOT

CS EPROM

ADDR23-0 DATA47-16 RD ACK

CONTROL ADDRESS

ADSP-21161 (S2, SLAVE)

BMS EBOOT LBOOT

ADDR23-0 DATA47-16 RD ACK

ADSP-21161 (S6, SLAVE)

Figure 13-29. Sequential Booting from an EPROM

Data Delays, Latencies, and Throughput

Table 13-13 specifies data delays, latencies and throughput for the ADSP-21161 processor. Data delay and latency are defined as the number cycles after the first cycle required to complete the operation. A zero waitstate memory has a data delay of zero. A single waitstate memory has a

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DATA

System Design

data delay of one. Throughput is the maximum rate at which the operation is performed. Data delay and throughput are the same whether the access is from a host processor or from another ADSP-21161 processor.

Execution Stalls
The following events can cause an execution stall for the ADSP-21161 processor: 1 cycle on a program memory data access with instruction cache miss 2 cycles on non-delayed branches 2 cycles on normal interrupts 5 cycles on vector interrupts 1-2 cycles on short loops with small iterations n cycles on an IDLE instruction

DAG Stalls
1 cycle hold on register conflict

Memory Stalls
1 cycle on PM and DM bus access to the same block of internal memory n cycles if conflicting accesses to external memory n cycles if access to external memory (until I/O buffers are cleared out)

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Data Delays, Latencies, and Throughput

n cycles if external access and ADSP-21161 processor does not control the external bus n cycles until external access is complete (for example, waitstates, idle cycles, and so on.)

IOP Register Stalls

n cycles if PM and DM bus access IOP registers (both must complete) n cycles if conflict occurs with slave access

DMA Stalls
1 cycle if an access to a DMA parameter register conflicts with the DMA address generation (for example, writing to the register while a register update is taking place) or reading while a DMA register conflicts with DMA chaining 1 cycle if an access to a DMA parameter register or the DMASTAT register conflicts with DMA address generation. For example, one cycle stall occurs when writing to a DMA register while a register update is taking place. Similarly, a one cycle stall occurs when reading from a DMA register while DMA chaining is taking place. n cycles if writing (or reading) to a DMA buffer when the buffer is full (or empty)

Link Port and Serial Port Stalls

1 cycle if two link buffer reads back-to-back n cycles if write to a full buffer or read from an empty buffer

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Table 13-12. Data Delay and Throughput

Operation Minimum Data Delay (cycles) 0
1

Maximum Throughput (cycles/ transfer) 1 2 1 22 1 1 1 1 1

Core processor access to external memory Synchronous access to slaves IOP registers Read (Transfer out) Write (Transfer in) Slave mode DMA Read (Transfer out) Write (Transfer in) Master mode DMA Transfer out Transfer in Handshake mode DMA3 Read/Write (Transfer in/out) External-Handshake mode DMA4 Read/Write (Transfer in/out)

0 2 3 3

1 The delay is between data in the IOP register and at the external port. For example, an IOP register is written in the second cycle after a write completes at the external port. 2 These transfer rates are limited by the speed of the read of the DMA FIFO buffer. When bursting is enabled, the first read requires three cycles. The maximum burst read throughput is 3-2-2-2. 3 The delay is between DMA and DMARx. 4 The delay is between DMARx and the external transfer.

Table 13-13. Latencies and Throughput

Operation Minimum Data Delay (cycles) 3 1 2 1 Maximum Throughput (cycles/ transfer) -

Interrupts (IRQ2-0) Multiprocessor bus requests (BR1-6) Host bus request SYSCON effect latency

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Data Delays, Latencies, and Throughput

Table 13-13. Latencies and Throughput (Contd)

Operation Minimum Data Delay (cycles) 0 1 7-11 6 35 7 11 15 19 Maximum Throughput (cycles/ transfer) 32 4 8 12 16

Host packing status update in SYSTAT register DMA packing status update in DMACx register DMA chain initialization Vector interrupt Serial ports1 Link ports 1x CCLK speed 1/2x CCLK speed 1/3x CCLK speed 1/4x CCLK speed 1
1

ADSP-21161 processor to ADSP-21161 processor transfers using 32-bit words. Link port throughput is decreased and cycle time increased when the link port clock divisor bits are set in the LCTL register.

The link port control register LCTL and the serial port control register SPCTLx share the same internal bus for reads and writes. Therefore, when a read of one of these registers followed by a write occurs, the write will require two processor cycles to complete.

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A REGISTERS

The ADSP-21161 processor has general-purpose and dedicated registers in each of its functional blocks. The register reference information for each functional block includes bit definitions, initialization values, and memory-mapped addresses (for I/O processor registers). Information on each type of register is available at the following locations: Control and Status System Registers on page A-2 Processing Element Registers on page A-23 Program Sequencer Registers on page A-25 Data Address Generator Registers on page A-46 I/O Processor Registers on page A-47 When writing programs, it is often necessary to set, clear, or test bits in the processors registers. While these bit operations can all be done by referring to the bits location within a register or (for some operations) the registers address with a hexadecimal number, it is much easier to use symbols that correspond to the bits or registers name. For convenience and consistency, Analog Devices provides a header file that provides these bit and registers definitions. For more information, see the Register and Bit #Defines (def21161.h) on page A-121. Many registers have reserved bits. When writing to a register, programs may only clear (write zero to) the registers reserved bits.

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Control and Status System Registers

Control and Status System Registers

The processors control and status system registers determine how the processor core operates and indicate the status of many processor core operations. In the ADSP-21160 SHARC DSP Instruction Set Reference, these registers are referred to as System Registers (SREG), which are a subset of the processors Universal Registers (UREG). Not all registers are valid in all assembly language instructions. In the assembly syntax descriptions, the register group name (UREG, SREG, and others) indicates which type of register is valid within the instructions context. Table A-1 lists the processor cores control and status registers with their initialization values. Descriptions of each register follow. Other system registers (SREG) are in the I/O processor. For more information, see I/O Processor Registers on page A-47. Table A-1. Control and Status System Registers (SREG and UREG)
Register Name and Page Reference Mode Control 1 Register (MODE1) on page A-3 Mode Mask Register (MMASK) on page A-8 Mode Control 2 Register (MODE2) on page A-10 Arithmetic Status Registers (ASTATx and ASTATy) on page A-13 Sticky Status Registers (STKYx and STKYy) on page A-18 User-Defined Status Registers (USTATx) on page A-22 1 Initialization After Reset 0x0000 00001 0x0020 0000 0xXX00 00002 0x0000 0000 0x0540 0000 0x0000 0000

MODE 1 register initialization value is 0x0000 0000 for revisions less than 1.0. For revisions greater than or equal to 1.0, the initialization value is 0x0100 0000 because circular buffering (CBUFEN) is enabled. MODE2_SHDW bits 31-25 are the processor ID and silicon revision number, so the initialization value varies with the processors ID2-0 pins input and the silicon revision.

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Registers

Mode Control 1 Register (MODE1)

The Mode Control 1 register is a non-memory-mapped, universal, system register (UREG and SREG). The reset value for this register is 0x0000 00001. Table A-2 and Figure A-1 provide bit information for the MODE1 register. Table A-2. Mode Control 1 Register (MODE1) Bit Definitions
Bit(s) 0 Name BR8 Definition Bit Reverse Addressing For Index I8 Enable. This bit enables (bit reversed if set, =1) or disables (normal if cleared, =0) bit reversed addressing for accesses that are indexed with DAG2 register I8. Bit Reverse Addressing For Index I0 Enable. This bit enables (bit reversed if set, =1) or disables (normal if cleared, =0) bit reversed addressing for accesses that are indexed with DAG1 register I0. Secondary Registers For Computational Units Enable. This bit enables (use secondary if set, =1) or disables (use primary if cleared, =0) secondary result (MR) registers in the computational units. Secondary Registers For DAG1 High Enable. This bit enables (use secondary if set, =1) or disables (use primary if cleared, =0) secondary DAG1 registers for the upper half (I, M, L, B7-4) of the address generator. Secondary Registers For DAG1 Low Enable. This bit enables (use secondary if set, =1) or disables (use primary if cleared, =0) secondary DAG1 registers for the lower half (I, M, L, B3-0) of the address generator. Secondary Registers For DAG2 High Enable. This bit enables (use secondary if set, =1) or disables (use primary if cleared, =0) secondary DAG2 registers for the upper half (I, M, L, B15-12) of the address generator.

BR0

SRCU

SRD1H

SRD1L

SRD2H

MODE 1 register initialization value is 0x0000 0000 for revisions less than 1.0. For revisions greater than or equal to 1.0, the initialization value is 0x0100 0000 because circular buffering (CBUFEN) is enabled.

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Control and Status System Registers

Table A-2. Mode Control 1 Register (MODE1) Bit Definitions (Contd)

Bit(s) 6 Name SRD2L Definition Secondary Registers For DAG2 Low Enable. This bit enables (use secondary if set, =1) or disables (use primary if cleared, =0) secondary DAG2 registers for the lower half (I, M, L, B11-8) of the address generator. Secondary Registers For Register File High Enable. This bit enables (use secondary if set, =1) or disables (use primary if cleared, =0) secondary data registers for the upper half (R15-8) of the computational units. Reserved SRRFL Secondary Registers For Register File Low Enable. This bit enables (use secondary if set, =1) or disables (use primary if cleared, =0) secondary data registers for the lower half (R7-0) of the computational units. Nesting Multiple Interrupts Enable. This bit enables (nest if set, =1) or disables (no nesting if cleared, =0) interrupt nesting in the interrupt controller. When interrupt nesting is disabled, a higher priority interrupt can not interrupt a lower priority interrupts service routine. Other interrupts are latched as they occur, but they are processed after the active routine finishes. When interrupt nesting is enabled, a higher priority interrupt can interrupt a lower priority interrupts service routine. Lower interrupts are latched as they occur, but they are processed after the nested routines finish. 12 13 IRPTEN ALUSAT Global Interrupt Enable. This bit enables (if set, =1) or disables (if cleared, =0) all maskable interrupts. ALU Saturation Select. This bit selects whether the computational units saturate results on positive or negative fixed-point overflows (if 1) or return unsaturated results (if 0). Fixed-Point Sign Extension Select. This bit selects whether the computational units sign extend short-word, 16-bit data (if 1) or zero-fill the upper 32 bits (if 0).

SRRFH

9-8 10

11

NESTM

14

SSE

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Registers

Table A-2. Mode Control 1 Register (MODE1) Bit Definitions (Contd)

Bit(s) 15 Name TRUNC Definition Truncation Rounding Mode Select. This bit selects whether the computational units round results with round-to-zero (if 1) or round-to-nearest (if 0). Rounding For 32-bit Floating-Point Data Select. This bit selects whether the computational units round floating-point data to 32 bits (if 1) or round to 40 bits (if 0). Bus Master Code Selection. These bits indicate whether the processor has control of the external bus as follows: 00=processor is bus master or 01, 10, 11=processor is not bus master. Reserved PEYEN Processor Element Y Enable. This bit enables computations in PEySIMD mode(if 1) or disables PEySISD mode(if 0). When set, Processing Element Y (computation units and register files) accepts instruction dispatches. When cleared, Processing Element Y goes into a low power mode. 22 BDCST9 Broadcast Register Loads Indexed With I9 Enable. This bit enables (broadcast I9 if set, =1) or disables (no I9 broadcast if cleared, =0) broadcast register loads for loads that use the data address generator I9 index. When the BDCST9 bit is set, data register loads from the PM data bus that use the I9 DAG2 index register are broadcast to a register or register pair in each PE. 23 BDCST1 Broadcast Register Loads Indexed With I1 Enable. This bit enables (broadcast I1 if set, =1) or disables (no I1 broadcast if cleared, =0) broadcast register loads for loads that use the data address generator I1 index. When the BDCST1 bit is set, data register loads from the DM data bus that use the I1 DAG1 index register are broadcast to a register or register pair in each PE.

16

RND32

18-17

CSEL

20-19 21

ADSP-21161 SHARC Processor Hardware Reference

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Control and Status System Registers

Table A-2. Mode Control 1 Register (MODE1) Bit Definitions (Contd)

Bit(s) 24 Name CBUFEN Definition Circular Buffer Addressing Enable. This bit enables (circular if set, =1) or disables (linear if cleared, =0) circular buffer addressing for buffers with loaded I, M, B, and L data address generator register. Reserved

31-25

A-6

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Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MODE1
CBUFEN
0=Disable Circular 1=Enables Circular

RND32
0=Round Floating-Point Data to 40 bits 1=Round Floating-Point Data to 32 bits

BDCST1
0= Disable I1 Broadcast 1= Enable I1 Broadcast

CSEL
Condition Code Select 00=Bus Master Condition

BDCST9
0= Disable I9 Broadcast 1= Enable I9 Broadcast 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0

PEYEN
0= Disable PEy- SISD mode 1= Enable PEy- SIMD mode 1 0 0 0

TRUNC
0=Floating-Point Round-to-Nearest 1=Floating-Point Truncation SSE 0=Disable Short Word Sign Extension 1=Enable Short Word Sign Extension

0=Disable I8 Bit-Reversing (DAG 2) 1=Enable I8 Bit-Reversing (DAG 2)

BR8 BR0

0=Disable I0 Bit-Reversing (DAG 1) 1=Enable I0 Bit-Reversing (DAG 1)

SRCU ALUSAT
0=Disable ALU Saturation 1=Enable ALU Saturation 0=Enable MR Primary 1=Enable MR Alternative 0=Enable DAG1 7-4 Primary 1=Enable DAG1 7-4 Alternate 0=Enable DAG1 3-0 Primary 1=Enable DAG1 3-0 Alternate

SRD1H SRD1L

IRPTEN
0=Disable Interrupts 1=Enable Interrupts

NESTM
0=Disable Interrupt Nesting 1=Enable Interrupt Nesting

SRD2H
0=Enable DAG2 15-12 Primary 1=Enable DAG2 15-12 Alternate 0=Enable DAG2 11-8 Primary 1=Enable DAG2 11-8 Alternate 0=Enable R15-R8 Primary 1=Enable R15-R8 Alternate

SRRFL
0=Enable R7-R0 Primary 1=Enable R7-R0 Secondary

SRD2L

SRRFH

Figure A-1. MODE1 Register

ADSP-21161 SHARC Processor Hardware Reference

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Control and Status System Registers

Mode Mask Register (MMASK)

This is a non-memory-mapped, universal, system register (UREG and SREG). The reset value for this register is 0x0020 0000. Each bit in the MMASK register corresponds to a bit in the MODE1 register. Bits that are set in MMASK are used to clear bits in MODE1 when the processors status stack is pushed. This effectively disables different modes upon servicing an interrupt, or when executing a PUSH STS instruction. The processor's status stack is pushed in two cases: 1. When you execute a PUSH
STS

instruction explicitly in your code.

2. When an IRQ2-0 timer expires or a VIRPT interrupt occurs. Example Before the PUSH STS instruction, MODE1 is set to 0x01202811. This MODE1 value corresponds to the following settings being enabled: Bit Reversing for I8 Secondary Registers for DAG2 (high) Interrupt Nesting, ALU Saturation Processor Element Y (SIMD) Circular Buffering The MMASK register (Figure A-2) is set to 0x0020 2001 indicating that you want to disable ALU Saturation, SIMD, and bit reversing for I8 after pushing the status stack. The value in MODE1 after PUSH STS is 0x0100 0810. The other settings that were previously in MODE1 remain the same. The only bits that are affected are those that are set both in MMASK and in MODE1. These bits are cleared after the status stack is pushed.

A-8

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Registers

Note also that the reset value of MMASK is 0x0020 0000. If you do not make any changes to the MMASK register, the default setting automatically disables SIMD when servicing any of the hardware interrupts mentioned above, or during any push of the status stack.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MMASK
CBUFEN
0=Disable Linear 1=Enables Circular

RND32
0=Round Floating-Point Data to 40 bits 1=Round Floating-Point Data to 32 bits

BDCST1
0=Disable I1 Broadcast 1=Enable I1 Broadcast

CSEL
Condition Code Select 00=Bus Master Condition

BDCST9
0=Disable I9 Broadcast 1=Enable I9 Broadcast 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0

PEYEN
0=Disable PEy-SISD mode 1=Enable PEy-SISD mode 0 0

0=Floating-point Rount-to-Nearest 1=Floating-Point Truncation SSE 0=Disable Short Word Sign Extension 1=Enable Short Word Sign Extension

TRUNC

BR8
0=Disable I8 Bit-Reversing (DAG 2) 1=Enable I8 Bit-Reversing (DAG 2)

BR0
0=Disable I0 Bit-Reversing (DAG 1) 1=Enable I0 Bit-Reversing (DAG 1)

SRCU
0=Enable MR Primary 1=Enable MR Alternative

ALUSTAT
0=Disable ALU Saturation 1=Enable ALU Saturation

SRD1H SRD1L

IRPTEN
0=Disable Interrupts 1=Enable Interrupts

0=Enable DAG1 7-4 Primary 1=Enable DAG1 7-4 Alternate

NESTM
0=Disable Interrupt Nesting 1=Enable Interrupt Nesting

0=Enable DAG1 3-0Primary 1=Enable DAG1 3-0 Alternate

SRD2H
0=Enable DAG2 15-12 Primary 1=Enable DAG2 15-12 Alternate

SRRFL
0=Disable R7-R0 Primary 1=Enable R7-R0 Alternate

SRD2L
0=Enable DAG2 11-8 Primary 1=Enable DAG2 11-8 Alternate

SRRFH
0=Enable R15-R8 Primary 1=Enable R15-R8 Alternate

Figure A-2. MMASK Register

ADSP-21161 SHARC Processor Hardware Reference

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Control and Status System Registers

Mode Control 2 Register (MODE2)

This is a non-memory-mapped, universal, system register (UREG and SREG). The reset value for this register is 0x0000 0000. Table A-3 and Figure A-3 provide bit information for the MODE2 register. The MODE2_SHDW register contains silicon revision information in bits 31-25. The corresponding bits in the MODE2 register are reserved. For more information, see MODE2 Shadow Register (MODE2_SHDW) on page A-78. Table A-3. Mode Control 2 Register (MODE2) Bit Definitions
Bit 0 1 2 3 4 5 6 CADIS TIMEN BUSLK Name IRQ0E IRQ1E IRQ2E Definition IRQ0 Sensitivity Select. This bit selects sensitivity for IRQ0 as edge-sensitive (if set, =1) or level-sensitive (if cleared, =0). IRQ1 Sensitivity Select. This bit selects sensitivity for IRQ1 as edge-sensitive (if set, =1) or level-sensitive (if cleared, =0). IRQ2 Sensitivity Select. This bit selects sensitivity for IRQ2 as edge-sensitive (if set, =1) or level-sensitive (if cleared, =0). Reserved Cache Disable. This bit disables the instruction cache (if set, =1) or enables the cache (if cleared, =0). Timer Enable. This bit enables the timer (starts, if set, =1) or disables the timer (stops, if cleared, =0). Bus Lock Request. This bit requests bus lock (ADSP-21161 processor retains bus master control, if set, =1) or does not request bus lock (normal bus master control, if cleared, =0). Reserved FLG0O FLG1O FLAG0 Output Select. This bit selects the I/O direction for FLAG0 as an output (if set, =1) or an input (if cleared, =0). FLAG1 Output Select. This bit selects the I/O direction for FLAG1 as an output (if set, =1) or an input (if cleared, =0).

14-7 15 16

A-10

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Registers

Table A-3. Mode Control 2 Register (MODE2) Bit Definitions (Contd)

Bit 17 18 19 Name FLG2O FLG3O CAFRZ Definition FLAG2 Output Select. This bit selects the I/O direction for FLAG2 as an output (if set, =1) or an input (if cleared, =0). FLAG3 Output Select. This bit selects the I/O direction for FLAG3 as an output (if set, =1) or an input (if cleared, =0). Cache Freeze. This bit freezes the instruction cache (retains contents, if set, =1) or thaws the cache (allows new input, if cleared, =0). Illegal I/O Processor Register Access Enable. This bit enables detection of I/O processor register accesses (if set, =1) or disables detection of I/O processor register accesses (if cleared, =0). If IIRAE is set, the processor flags an illegal access by setting the IIRA bit in the STKYx register. 21 U64MAE Unaligned 64-bit Memory Access Enable. This bit enables detection of unaligned long word accesses (if set, =1) or disables detection of unaligned long word accesses (if cleared, =0). If U64MAE is set, the processor flags an unaligned long word accesses by setting the U64MA bit in the STKYx register. 31-22 Reserved

20

IIRAE

ADSP-21161 SHARC Processor Hardware Reference

A-11

Control and Status System Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MODE2
U64MAE

0 FLG1O
0=FLAG1 Input 1=FLAG1 Output

0=Disable detection of unaligned LW accesses 1=Enable detection of unaligned LW accesses

FLG2O
0=FLAG2 Input 1=FLAG2 Output

IIRAE
0=Disable detection of Illegal IOP access 1=Enable detection of Illegal IOP access

FLG3O
0=FLAG3 Input 1=FLAG3 Output

CAFRZ
0=Cache Updates 1=Cache Freeze (No Updates)

15 14 13 12 11 10 9 0 0 0 0 0 0 0

8 0

7 0

6 0

5 0

4 0

1 0

0 0

0 0

FLG0O
0=FLAG0 Input 1=FLAG0 Output

IRQ0E
0=IRQ O Level-Sensitive 1=IRQ O Edge-Sensitive

BUSLK
0=No External Bus Lock 1=External Bus Lock

IRQ1E
0=IRQ 1 Level-Sensitive 1=IRQ 1 Edge-Sensitive

TIMEN
0=Disable Timer 1=Enable Timer

IRQ2E
0=IRQ 2 Level-Sensitive 1=IRQ 2 Edge-Sensitive

CADIS
0=Enable Cache 1=Disable Cache

Figure A-3. MODE2 Register

A-12

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Registers

Arithmetic Status Registers (ASTATx and ASTATy)

and ASTATy are non-memory-mapped, universal, system registers (UREG and SREG). The reset value for these registers is 0x0000 0000. Each processing element has its own ASTAT register. ASTATx indicates status for PEx operations while ASTATy indicates status for PEy operations. Table A-4 and Figure A-4 provide bit information for the ASTAT register.
ASTATx

If a program loads the ASTATx register manually, there is a one cycle effect latency before the new value in ASTATx can be used in a conditional instruction. Table A-4. Arithmetic Status Registers (ASTATx/y) Bit Definitions
Bit(s) 0 Name AZ Definition ALU Zero/Floating-Point Underflow. Indicates whether the last ALU operations result was zero (if set, =1) or non-zero (if cleared, =0). The ALU updates AZ for all fixed-point and floating-point ALU operations. AZ can also indicate a floating-point underflow. During an ALU underflow (indicated by a set (=1) AUS bit in the STKYx/y register), the processor sets AZ if the floating-point result is smaller than can be represented in the output format. 1 AV ALU Overflow. Indicates whether the last ALU operations result overflowed (if set, =1) or did not overflow (if cleared, =0). The ALU updates AV for all fixed-point and floating-point ALU operations. For fixed-point results, the processor sets AV and the AOS bit in the STKYx/y register when the XOR of the two most significant bits is a 1. For floating-point results, the processor sets AV and the AVS bit in the STKYx/y register when the rounded result overflows (unbiased exponent > 127). 2 AN ALU Negative. Indicates whether the last ALU operations result was negative (if set, =1) or positive (if cleared, =0). The ALU updates AN for all fixed-point and floating-point ALU operations.

ADSP-21161 SHARC Processor Hardware Reference

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Control and Status System Registers

Table A-4. Arithmetic Status Registers (ASTATx/y) Bit Definitions (Contd)

Bit(s) 3 Name AC Definition ALU Fixed-Point Carry. Indicates whether the last ALU operation had a carry out of most significant bit of the result (if set, =1) or had no carry (if cleared, =0). The ALU updates AC for all fixed-point operations. The processor clears AC during fixed-point logic operations: PASS, MIN, MAX, COMP, ABS, and CLIP. The ALU reads the AC flag for fixed-point accumulate operations: addition with carry and fixed-point subtraction with carry. 4 AS ALU X-Input Sign (for ABS and MANT). Indicates whether the last ALU ABS or MANT operations input was negative (if set, =1) or positive (if cleared, =0). The ALU updates AS only for fixed-point and floating-point ABS and the MANT operations. The ALU clears AS for all operations other than ABS and MANT. 5 AI ALU Floating-Point Invalid Operation. Indicates whether the last ALU operations input was invalid (if set, =1) or valid (if cleared, =0). The ALU updates AI for all fixed-point and floating-point ALU operations. The processor sets AI and the AIS bit in the STKYx/y register if the ALU operation: 6 MN Receives a NAN input operand Adds opposite-signed infinities Subtracts like-signed infinities Overflows during a floating-point to fixed-point conversion when saturation mode is not set Operates on an infinity when the saturation mode is not set

Multiplier Negative. Indicates whether the last multiplier operations result was negative (if set, =1) or positive (if cleared, =0). The multiplier updates MN for all fixed-point and floating-point multiplier operations.

A-14

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Registers

Table A-4. Arithmetic Status Registers (ASTATx/y) Bit Definitions (Contd)

Bit(s) 7 Name MV Definition Multiplier Overflow. Indicates whether the last multiplier operations result overflowed (if set, =1) or did not overflow (if cleared, =0). The multiplier updates MV for all fixed-point and floating-point multiplier operations. For floating-point results, the processor sets MV and the MVS bit in the STKYx/y register if the rounded result overflows (unbiased exponent > 127). For fixed-point results, the processor sets MV and the MOS bit in the STKYx/y register if the result of the multiplier operation is: Twos-complement, fractional with the upper 17 bits of MR not all zeros or all ones Twos-complement, integer with the upper 49 bits of MR not all zeros or all ones Unsigned, fractional with the upper 16 bits of MR not all zeros Unsigned, integer with the upper 48 bits of MR not all zeros

If the multiplier operation directs a fixed-point result to an MR register, the processor places the overflowed portion of the result in MR1 and MR2 for an integer result or places it in MR2 only for a fractional result.

ADSP-21161 SHARC Processor Hardware Reference

A-15

Control and Status System Registers

Table A-4. Arithmetic Status Registers (ASTATx/y) Bit Definitions (Contd)

Bit(s) 8 Name MU Definition Multiplier Floating-Point Underflow. Indicates whether the last multiplier operations result underflowed (if set, =1) or did not underflow (if cleared, =0). The multiplier updates MU for all fixed-point and floating-point multiplier operations. For floating-point results, the processor sets MU and the MUS bit in the STKYx/y register if the floating-point result underflows (unbiased exponent < 126). Denormal operands are treated as Zeros, therefore they never cause underflows. For fixed-point results, the processor sets MU and the MUS bit in the STKYx/y register if the result of the multiplier operation is: Twos-complement, fractional: upper 48 bits all zeros or all ones, lower 32 bits not all zeros Unsigned, fractional: upper 48 bits all zeros, lower 32 bits not all zeros

If the multiplier operation directs a fixed-point, fractional result to an MR register, the processor places the underflowed portion of the result in MR0. 9 MI Multiplier Floating-Point Invalid Operation. Indicates whether the last multiplier operations input was invalid (if set, =1) or valid (if cleared, =0). The multiplier updates MI for floating-point multiplier operations. The processor sets MI and the MIS bit in the STKYx/y register if the ALU operation: 10 AF Receives a NAN input operand Receives an Infinity and Zero as input operands

ALU Floating-Point Operation. Indicates whether the last ALU operation was floating-point (if set, =1) or fixed-point (if cleared, =0). The ALU updates AF for all fixed-point and floating-point ALU operations.

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Table A-4. Arithmetic Status Registers (ASTATx/y) Bit Definitions (Contd)

Bit(s) 11 Name SV Definition Shifter Overflow. Indicates whether the last shifter operations result overflowed (if set, =1) or did not overflow (if cleared, =0). The shifter updates SV for all shifter operations. The processor sets SV if the shifter operation: Shifts the significant bits to the left of the 32-bit fixed-point field Tests, sets, or clears a bit outside of the 32-bit fixed-point field Extracts a field that is past or crosses the left edge of the 32-bit fixed-point field Performs a LEFTZ or LEFTO operation that returns a result of 32 Shifter Zero. Indicates whether the last shifter operations result was zero (if set, =1) or non-zero (if cleared, =0). The shifter updates SZ for all shifter operations. The processor also sets SZ if the shifter operation performs a bit test on a bit outside of the 32-bit fixed-point field. 13 SS Shifter Input Sign. Indicates whether the last shifter operations input was negative (if set, =1) or positive (if cleared, =0). The shifter updates SS for all shifter operations. Reserved BTF Bit Test Flag for System Registers. Indicates whether the system register bit is true (if set, =1) or false (if cleared, =0). The processor sets BTF when the bit(s) in a system register and value in the Bit Tst instruction match. The processor also sets BTF when the bit(s) in a system register and value in the Bit Xor instruction match. 23-19 31-24 CACC Reserved Compare Accumulation Shift Register. Bit 31 of CACC indicates which operand was greater during the last ALU compare operation: X input (if set, =1) or Y input (if cleared, =0). The other seven bits in CACC form a right-shift register, each storing a previous compare accumulation result. With each new compare, the processor right shifts the values of CACC, storing the newest value in bit 31 and the oldest value in bit 24.

12

SZ

17-14 18

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A-17

Control and Status System Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ASTATx/y
CCAC

BTF
Bit Test Flag for System Registers

Compare Accumulation Shift Register

15 14 13 12 11 10 9 0 0 0 0 0 0 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

SS
Shifter Input Sign

AZ

ALU Zero/ Floating-Point Underflow

SZ
Shifter Zero

AV
ALU Overflow

SV
Shifter Overflow

AN AC AS

ALU Negative ALU Fixed-Point Carry ALU X Input Sign (for ABS and MANT)

AF
ALU Floating-Point Operation

MI
Multiplier Floating-Point Invalid Operation

AI
ALU Floating-Point Invalid Operation

MU
Multiplier Floating-Point Underflow

MN

MV
Multiplier Overflow

Multiplier Negative

Figure A-4. ASTAT Register

Sticky Status Registers (STKYx and STKYy)

These are non-memory-mapped, universal, system registers (UREG and SREG). The reset value for these registers is 0x0000 0000. Each processing element has its own STKY register. The STKYx register indicates status for PEx operations and some program sequencer stacks. The STKYy register

A-18

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Registers

only indicates status for PEy operations. Table A-5, Figure A-5 and Figure A-6 lists bits for both STKYx and STKYy, noting with an the bits that apply only to STKYx. bits do not clear themselves after the condition they flag is no longer true. They remain sticky until cleared by the program.
STKY

The ADSP-21161 processor sets a STKY bit in response to a condition. For example, the processor sets the AUS bit in the STKY register when an ALU underflow set AZ in the ASTAT register. The processor clears AZ if the next ALU operation does not cause an underflow. The bit AUS remains set until a program clears the STKY bit. Interrupt service routines should clear their interrupts corresponding STKY bit so the processor can detect a re-occurrence of the condition. For example, an interrupt service routine for the floating-point underflow exception interrupt (FLTUI) would clear the AUS bit in the STKY register near the beginning of the routine. Table A-5. Sticky Status Registers (STKYx/y) Bit Definitions
Bit(s) 0 1 2 4-3 5 6 7 AIS MOS MVS Name AUS AVS AOS Definition At right: shows bits in both STKYx/y shows bits in STKYx only

ALU Floating-Point Underflow. A sticky indicator for the ALU AS bit. For more information, see AZ on page A-13. ALU Floating-Point Overflow. A sticky indicator for the ALU AV bit. For more information, see AV on page A-13. ALU Fixed-Point Overflow. A sticky indicator for the ALU AV bit. For more information, see AV on page A-13. Reserved ALU Floating-Point Invalid Operation. A sticky indicator for the ALU AI bit. For more information, see AI on page A-14. Multiplier Fixed-Point Overflow. A sticky indicator for the multiplier MV bit. For more information, see MV on page A-15. Multiplier Floating-Point Overflow. A sticky indicator for the multiplier MV bit. For more information, see MV on page A-15.

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Control and Status System Registers

Table A-5. Sticky Status Registers (STKYx/y) Bit Definitions (Contd)

Bit(s) 8 Name MUS Definition At right: shows bits in both STKYx/y shows bits in STKYx only

Multiplier Floating-Point Underflow. A sticky indicator for the multiplier MU bit. For more information, see MU on page A-16. Multiplier Floating-Point Invalid Operation. A sticky indicator for the multiplier MI bit. For more information, see MI on page A-16. Reserved

MIS

16-10 17 CB7S

DAG1 Circular Buffer 7 Overflow. Indicates whether a circular buffer being addressed with DAG1 register I7 has overflowed (if set, =1) or has not overflowed (if cleared, =0). A circular buffer overflow occurs when DAG circular buffering operation increments the I register past the end of buffer. DAG2 Circular Buffer 15 Overflow. Indicates whether a circular buffer being addressed with DAG2 register I15 has overflowed (if set, =1) or has not overflowed (if cleared, =0). A circular buffer overflow occurs when DAG circular buffering operation increments the I register past the end of buffer. Illegal IOP Register Access. Indicates if set (=1) whether a core, host, or multiprocessor access to I/O processor registers has occurred or has not occurred (if 0). Unaligned 64-Bit Memory Access. Indicates if set (=1) whether a Normal word access with the LW mnemonic addressing an uneven memory address has occurred or has not occurred (if 0). PC Stack Full. Indicates whether the PC stack is full (if 1) or not full (if 0)Not a sticky bit, cleared by a Pop. PC Stack Empty. Indicates whether the PC stack is empty (if 1) or not empty (if 0)Not sticky, cleared by a Push. Status Stack Overflow. Indicates whether the status stack is overflowed (if 1) or not overflowed (if 0)A sticky bit. Status Stack Empty. Indicates whether the status stack is empty (if 1) or not empty (if 0)Not sticky, cleared by a Push.

18

CB15S

19

IIRA

20

U64MA

21 22 23 24

PCFL PCEM SSOV SSEM

A-20

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Registers

Table A-5. Sticky Status Registers (STKYx/y) Bit Definitions (Contd)

Bit(s) 25 Name LSOV Definition At right: shows bits in both STKYx/y shows bits in STKYx only

Loop Stack Overflow. Indicates whether the loop counter stack and loop stack are overflowed (if 1) or not overflowed (if 0)A sticky bit. Loop Stack Empty. Indicates whether the loop counter stack and loop stack are empty (if 1) or not empty (if 0)Not sticky, cleared by a Push. Reserved

26

LSEM

31-27

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

STKYx
LSEM
Loop Stack Empty (read - only)

CB7S
DAG1 Circular Buffer 7 Overflow

CB15S
DAG2 Circular Buffer 15 Overflow

LSOV
Loop Stack Overflow (read- only)

IIRA
Illegal IOP Register Access 1= illegal access occured, 0= no illegal access

SSEM
Status Stack Empty (read - only)

SSOV
Status Stack Overflow (read-only)

U64MA
Unaligned 64-bit Memory Access 1=unaligned access has occured, 0=no access occured

PCEM
PC Stack Empty (read - only) Not sticky, cleared by PUSH

PCFL
PC Stack Full (read -only) Not sticky, cleared by POP

15 14 13 12 11 10 0 0 0 0 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

MIS
Multiplier Floating -Point Invalid Operation

AUS AVS

ALU Floating - Point Underflow ALU Floating - Point Overflow

MUS
Mulitplier Floating -Point Underflow

AOS AIS

MVS
Multiplier Floating -Point Overflow

ALU Fixed - Point Overflow ALU Floating - Point Invalid Operation

MOS
Multiplier Fixed -Point Overflow

Figure A-5. STKYx Registers

ADSP-21161 SHARC Processor Hardware Reference

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Control and Status System Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

STKYy

15 14 13 12 11 10 0 0 0 0 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

MIS
Multiplier Floating - Point Invalid Operation

AUS AVS

ALU Floating -Point Underflow ALU Floating -Point Overflow

MUS
Mulitplier Floating -Point Underflow

AOS AIS

ALU Fixed - Point Overflow Multiplier Floating - Point Overflow Multiplier Fixed - Point Overflow

MVS

ALU Floating - Point Invalid Operation

MOS

Figure A-6. STKYy Register

User-Defined Status Registers (USTATx)

These are non-memory-mapped, universal, system registers (UREG and SREG). The reset value for these registers is 0x0000 0000. The USTATx registers (Figure A-7) are user-defined, general-purpose status registers. Programs can use these 32-bit registers with bitwise instructions (SET, CLEAR, TEST, and others). Often, programs use these registers for low-overhead, general-purpose flags or for temporary 32-bit storage of data.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USTAT1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USTAT2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USTAT3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USTAT4

Figure A-7. USTAT Registers

A-22

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Registers

Processing Element Registers

Except for the PX register, the processors processing element registers store data for each elements ALU, multiplier, and shifter. The inputs and outputs for processing element operations go through these registers. The PX register lets programs transfer data between the data buses, but cannot be an input or output in a calculation. Table A-6. Processing Element Universal Registers (UREG)
Register Name and Page Reference Data File Data Registers (Rx, Fx, Sx) on page A-23 Multiplier Results Registers (MRFx, MRBx) on page A-24 Program Memory Bus Exchange Register (PX) on page A-25 Initialization After Reset Undefined Undefined Undefined

Data File Data Registers (Rx, Fx, Sx)

The Data File Data Registers are non-memory-mapped, universal, data registers (UREG and DREG). Each of the ADSP-21161s processing elements has a data register filea set of 40-bit data registers that transfer data between the data buses and the computation units. These registers also provide local storage for operands and results. The R, F, and S prefixes on register names do not effect the 32-bit or 40-bit data transfer; the naming convention determines how the ALU, multiplier, and shifter treat the data and determines which processing elements data registers are being used. For more information on how to use these registers, see Data Register File on page 2-30.

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Processing Element Registers

Multiplier Results Registers (MRFx, MRBx)

The MRFx and MRBx registers are non-memory-mapped, universal, data registers (UREG and DREG). Each of the processors multipliers has a primary or foreground (MRF) register and alternate or background (MRB) results register. Fixed-point operations place 80-bit results in the multipliers foreground MRF register or background MRB register, depending on which is active. For more information on selecting the result register, see Alternate (Secondary) Data Registers on page 2-32. For more information on result register fields, see Data Register File on page 2-30.
Integer M u l t i p l i e r Fixed-Point Result Placement

Integer Multiplier Fixed Point Result Placement

79 63 MR2 OVERFLOW MR1 INTEGER RESULT 31 MR0 INTEGER RESULT 32 bits ureg OVERFLOW (is lost) INTEGER RESULT 0

Binary Point

MRF or MRB Placement

MV set Register File Placement

8 bits ZEROS

Fractional Multiplier Fixed-Point Result Placement

79 63 MR2 OVERFLOW MR1 31 MR0 FRACTIONAL RESULT 8 bits ZEROS t UNDERFLOW (is lost) 0

MRF or MRB Placement

MV set Register File Placement Binary Point

FRACTIONAL RESULT 32 bits ureg FRACTIONAL RESULT

Figure A-8. MRFx and MRBx Registers

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Program Memory Bus Exchange Register (PX)

The PX register (Figure A-9) is a non-memory-mapped, universal registers (UREG only). The PM Bus Exchange (PX) register permits data to flow between the PM and DM data buses. The PX register can work as one 64-bit register or as two 32-bit registers (PX1 and PX2). PX1 is the lower 32 bits of the PX register and PX2 is the upper 32 bits of PX. See the section Internal Data Bus Exchange on page 5-10 for more information about the PX register.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

PX2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PX1

Figure A-9. PX Register

Program Sequencer Registers

The ADSP-21161 processors program sequencer registers direct the execution of instructions. These registers include support for the: Instruction pipeline Program and loop stacks Timer Interrupt mask and latch

ADSP-21161 SHARC Processor Hardware Reference

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Program Sequencer Registers

Table A-7. Program Sequencer System Registers (UREG and SREG)

Register Interrupt Latch Register (IRPTL) on page A-27 Interrupt Mask Register (IMASK) on page A-31 Interrupt Mask Pointer Register (IMASKP) on page A-32 Link Port Interrupt Register (LIRPTL) on page A-34 Flag Value Register (FLAGS) on page A-37 1 Initialization After Reset 0x0000 0000 (cleared) 0x0000 0003 0x0000 0000 (cleared) 0x0000 0000 (cleared) 0x0000 000n1

FLAGS bits 0-3 are equal to the values of the FLAG0-3 input pins after reset; the flag pins are configured as inputs after reset.

Table A-8. Program Sequencer Universal Registers (UREG only)

Register Program Counter Register (PC) on page A-41 Program Counter Stack Register (PCSTK) on page A-44 Program Counter Stack Pointer Register (PCSTKP) on page A-44 Fetch Address Register (FADDR) on page A-44 Decode Address Register (DADDR) on page A-44 Loop Address Stack Register (LADDR) on page A-45 Current Loop Counter Register (CURLCNTR) on page A-45 Loop Counter Register (LCNTR) on page A-45 Timer Period Register (TPERIOD) on page A-46 Timer Count Register (TCOUNT) on page A-46 Initialization After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

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Interrupt Latch Register (IRPTL)

The IRPTL register is a non-memory-mapped, universal, system register (UREG and SREG). The reset value for this register is 0x0000 0000. The IRPTL register indicates latch status for interrupts. Table A-9 and Figure A-10 provide bit definitions for the IRPTL register. Table A-9. Interrupt Latch Register (IRPTL) Bit Definitions
Bit(s) 0 Name EMUI Definition Emulator Interrupt. Indicates whether an EMUI is latched and is pending (if set, =1) or no EMUI is pending (if cleared, =0). An EMUI occurs on reset and when an external device asserts the EMU pin. Reset Interrupt. Indicates whether an RSTI is latched and is pending (if set, =1) or no RSTI is pending (if cleared, =0). An RSTI occurs on reset as an external device asserts the RESET pin. Illegal Input Condition Detected Interrupt. Indicates whether an IICDI is latched and is pending (if set, =1) or no IICDI is pending (if cleared, =0). An IICDI occurs when a TRUE results from the logical Oring of the Illegal I/O Processor Register Access (IIRA) and Unaligned 64-bit Memory Access bits in the STKYx registers. Stack Overflow/Full Interrupt. Indicates whether a SOVFI is latched and is pending (if set, =1) or no SOVFI is pending (if cleared, =0). An SOVFI occurs when a stack in the program sequencer overflows or is full. For more information, see PCFL on page A-20, SSOV on page A-20, and LSOV on page A-21.

RSTI

IICDI

SOVFI

ADSP-21161 SHARC Processor Hardware Reference

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Program Sequencer Registers

Table A-9. Interrupt Latch Register (IRPTL) Bit Definitions (Contd)

Bit(s) 4 Name TMZHI Definition Timer Expired High Priority. Indicates whether a TMZHI is latched and is pending (if set, =1) or TMZHI is not pending (if cleared, =0). A TMZHI occurs when the timer decrements to zero. Note that this event also triggers a TMZLI. The timer operations are controlled as follows: The TCOUNT register contains the timer counter. The timer decrements the TCOUNT register each clock cycle. The TPERIOD value specifies the frequency of timer interrupts. The number of cycles between interrupts is TPERIOD + 1. The maximum value of TPERIOD is 232 1. The TIMEN bit in the MODE2 register starts and stops the timer.

Since the timer expired event (TCOUNT decrements to zero) generates two interrupts, TMZHI and TMZLI, programs should unmask the timer interrupt with the desired priority and leave the other one masked. 5 VIRPTI Multiprocessor Vector Interrupt. Indicates whether a VIRPTI is latched and is pending (if set, =1) or no VIRPTI is pending (if cleared, =0). A VIRPTI occurs when one of the DSPs in a multiprocessor system writes an address (the vector) to the processors VIRPT register. IRQ2 Hardware Interrupt. Indicates whether an IRQ2I is latched and is pending (if set, =1) or no IRQ2I is pending (if cleared, =0). An IRQ2I occurs when an external device asserts the IRQ2 pin. IRQ1 Hardware Interrupt. Indicates whether an IRQ1I is latched and is pending (if set, =1) or no IRQ1I is pending (if cleared, =0). An IRQ1I occurs when an external device asserts the IRQ1 pin. IRQ0 Hardware Interrupt. Indicates whether an IRQ0I is latched and is pending (if set, =1) or no IRQ0I is pending (if cleared, =0). An IRQ0I occurs when an external device asserts the IRQ0 pin. Reserved

IRQ2I

IRQ1I

IRQ0I

A-28

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Registers

Table A-9. Interrupt Latch Register (IRPTL) Bit Definitions (Contd)

Bit(s) 10 Name SP0I Definition SPORT0 DMA Interrupt. Indicates whether a SP0I is latched and is pending (if set, =1) or no SP0I is pending (if cleared, =0). A SP0I occurs two cycles after the last bit of an input the serial word is latched into RX0A or RX0B or two cycles after data is shifted out of TX0A or TX0B. SPORT1 DMA Interrupt. Indicates whether a SP1I is latched and is pending (if set, =1) or no SP1I is pending (if cleared, =0). A SP1I occurs two cycles after the last bit of an input the serial word is latched into RX1A or RX1B or two cycles after data is shifted out of TX1A or TX1B. SPORT2 DMA Interrupt. Indicates whether a SP2I is latched and is pending (if set, =1) or no SP2I is pending (if cleared, =0). An SP2I occurs two cycles after the last bit of an output the serial word is latched from RX2A or RX2B or two cycles after data is shifted out of TX2A or TX2B. SPORT3 DMA Interrupt. Indicates whether a SP3I is latched and is pending (if set, =1) or no SP3I is pending (if cleared, =0). An SP3I occurs two cycles after the last bit of an output the serial word is latched from RX3A or RX3B or two cycles after data is shifted out of TX3A or TX3B. Link or SPI Buffer DMA Summary Interrupt. Indicates whether an LPISUMI is latched and is pending (if set, =1) or no LPISUMI is pending (if cleared, =0). An LPISUMI occurs when a TRUE results from the logical Oring of unmasked link port and SPI interrupts, which are configured in the LIRPTL register. Indicates whether at least one unmasked link port (LBUF0 or LBUF1) or SPI port (SPIRX or SPITX) interrupt is latched. To enable link or SPI interrupts this bit must be unmasked in addition to unmasking the individual interrupts.

11

SP1I

12

SP2I

13

SP3I

14

LPISUMI

ADSP-21161 SHARC Processor Hardware Reference

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Program Sequencer Registers

Table A-9. Interrupt Latch Register (IRPTL) Bit Definitions (Contd)

Bit(s) 15 Name EP0I Definition External Port Buffer 0 DMA Interrupt. Indicates whether an EP0I is latched and is pending (if set, =1) or no EP0I is pending (if cleared, =0). An EP0I occurs when the external port buffers DMA is disabled (DEN=0) and either: 16 EP1I The buffer is set to receive (TRAN=0), and the buffer is not empty The buffer is set to transmit (TRAN=1), and the buffer is not full

External Port Buffer 1 DMA Interrupt. Indicates whether an EP1I is latched and is pending (if set, =1) or no EP1I is pending (if cleared, =0). For more information, see EP0I on page A-30. External Port Buffer 2 DMA Interrupt. Indicates whether an EP2I is latched and is pending (if set, =1) or no EP2I is pending (if cleared, =0). For more information, see EP0I on page A-30. External Port Buffer 3 DMA Interrupt. Indicates whether an EP3I is latched and is pending (if set, =1) or no EP3I is pending (if cleared, =0). For more information, see EP0I on page A-30. Link Port Service Request Interrupt. Indicates whether an LSRQI is latched and is pending (if set, =1) or no LSRQI is pending (if cleared, =0). An LSRQI occurs when an external source accesses an unassigned link port or accesses an assigned link port that has its link buffer disabled. DAG1 Circular Buffer 7 Overflow Interrupt. Indicates whether a CB7I is latched and is pending (if set, =1) or no CB7I interrupt is pending (if cleared, =0). For more information, see CB7S on page A-20. DAG2 Circular Buffer 15 Overflow Interrupt. Indicates whether a CB15I is latched and is pending (if set, =1) or no CB15I is pending (if cleared, =0). For more information, see CB15S on page A-20. Timer Expired (Low Priority) Interrupt. Indicates whether a TMZLI is latched and is pending (if set, =1) or no TMZLI is pending (if cleared, =0). For more information, see TMZHI on page A-28.

17

EP2I

18

EP3I

19

LSRQI

20

CB7I

21

CB15I

22

TMZLI

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Registers

Table A-9. Interrupt Latch Register (IRPTL) Bit Definitions (Contd)

Bit(s) 23 Name FIXI Definition Fixed-Point Overflow Interrupt. Indicates whether a FIXI is latched and is pending (if set, =1) or no FIXI is pending (if cleared, =0). For more information, see AOS on page A-19. Floating-Point Overflow Interrupt. Indicates whether a FLTOI is latched and is pending (if set, =1) or no FLTOI is pending (if cleared, =0). Floating-Point Underflow Interrupt. Indicates whether a FLTUI is latched and is pending (if set, =1) or no FLTUI is pending (if cleared, =0). Floating-Point Invalid Operation Interrupt. Indicates whether a FLTII is latched and is pending (if set, =1) or no FLTII is pending (if cleared, =0). For more information, see AIS on page A-19. User Software Interrupt 0. Indicates whether a SFT0I is latched and is pending (if set, =1) or no SFT0I is pending (if cleared, =0). An SFT0I occurs when a program sets (=1) this bit. User Software Interrupt 1. Indicates whether a SFT1I is latched and is pending (if set, =1) or no SFT1I is pending (if cleared, =0). For details, see SFT0I bit description. User Software Interrupt 2. Indicates whether a SFT2I is latched and is pending (if set, =1) or no SFT2I is pending (if cleared, =0). For details, see SFT0I bit description. User Software Interrupt 3. Indicates whether a SFT3I is latched and is pending (if set, =1) or no SFT3I is pending (if cleared, =0). For details, see SFT0I bit description. Reserved

24

FLTOI

25

FLTUI

26

FLTII

27

SFT0I

28

SFT1I

29

SFT2I

30

SFT3I

31

Interrupt Mask Register (IMASK)

The IMASK register is a non-memory-mapped, universal, system register (UREG and SREG). The reset value for this register is 0x0000 0003. Each bit in the IMASK register corresponds to a bit with the same name in the

ADSP-21161 SHARC Processor Hardware Reference

A-31

Program Sequencer Registers

registers. The bits in IMASK unmask (enable if set, =1) or mask (disable if cleared, =0) the interrupts that are latched in the IRPTL register. Except for RESET, all interrupts are maskable.
IRPTL

When IMASK masks an interrupt, the masking disables the processors response to the interrupt. The IRPTL register still latches an interrupt even when masked, and the processor responds to that latched interrupt if it is later unmasked. Table A-10 and Figure A-10 provide bit definitions for the IMASK register.

Interrupt Mask Pointer Register (IMASKP)

The IMASKP register is a non-memory-mapped, universal, system register (UREG and SREG). The reset value for this register is 0x0000 0000. Each bit in the IMASKP register corresponds to a bit with the same name in the IRPTL registers. This register supports an interrupt nesting scheme that lets higher priority events interrupt an interrupt service routine and keeps lower priority events from interrupting. Table A-9 and Figure A-10 provide bit definitions for the IMASKP register. When interrupt nesting is enabled, the bits in the IMASKP register mask interrupts having lower priority than the interrupt that is currently being serviced. Other bits in this register unmask interrupts having higher priority than the interrupt that is currently being serviced. Interrupt nesting is enabled using NESTM in the MODE1 register. The IRPTL register latches a lower priority interrupt even when masked, and the processor responds to that latched interrupt if it is later unmasked. When interrupt nesting is disabled (NESTM=0 in the MODE1 register), the bits in IMASKP mask all interrupts while an interrupt is currently being serviced. The IRPTL register still latches these interrupts even when masked, and the processor responds to the highest priority latched interrupt after servicing the current interrupt. For more information, see NESTM on page A-4.

A-32

ADSP-21161 SHARC Processor Hardware Reference

Registers

IRPTL IMASK IMASKP

SFT3I
User Software Interrupt 3 (0x8C) User Software Interrupt 2 (0x88) User Software Interrupt 1 (0x84) User Software Interrupt 0 (0x80) Floating - Point Invalid Operation (0x7C) Floating - Point Underflow (0x78) Floating - Point Overflow (0x74)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EP1I EP2I

Ext.Port Buffer 1 DMA (0x54) Ext.Port Buffer 2 DMA (0x58)

SFT2I SFT1I SFT0I

EP3I

Ext.Port Buffer 3 DMA (0x5C)

LSRQI
Link Port Service Request (0x60)

CB7I

DAG1 Circular Buffer 7 Overflow (0x64)

FLTII

CB15I

DAG2 Circular Buffer 15 Overflow (0x68)

FLTUI

TMZLI FIXI
15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

Timer Expired (Low Priority) (0x6C) Fixed-Point Overflow (0x70)

FLTOI

EP0I
Ext.Port Buffer 0 DMA(0x50)

EMUI RSTI IICDI

Emulator Interrupt (int vector address 0x00) Reset ( int vector address 0x04) Illegal Input Condition Detected (0x08)

LPISUMI
Link or SPI Buffer DMA Summary

SP3I
SPORT3 DMA (0x34)

SP2I
SPORT2 DMA (0x30)

SOVFI

Stack Full/Overflow (0x0C)

SP1I
SPORT1 DMA (0x2C)

TMZHI

Timer Expired (High Priority) (0x10)

SP0I
SPORT0 DMA (0x28) IRQ0 Asserted (0x20)

VIRPTI IRQ2I IRQ1I

Multiprocessor Vector Interrupt (0x14) IRQ2 Asserted (0x18) IRQ1 Asserted (0x1C)

IRQ0I

Figure A-10. IMASK, IMASKP, IRPTL Registers

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Program Sequencer Registers

Link Port Interrupt Register (LIRPTL)

The LIRPTL register is a non-memory-mapped, universal, system register (UREG and SREG). The reset value for these registers is 0x0000 0000. The LIRPTL register indicates latch status, select masking, and displays mask pointers for link port interrupts. Table A-10 and Figure A-11 provide bit definitions for the LIRPTL register. Note that the LPISUM bit in the IRPTL register contains a logical Oring of the link port and SPI port latch bits in the LIRPTL register. For more information, see LPISUMI on page A-29. Table A-10. Link Port Interrupt Latch, Mask, and Mask Pointer Register (LIRPTL) Bit Definitions
Bit 0 Name LP0I Definition Link Port Buffer 0 DMA Interrupt. Indicates whether an LP0 interrupt is latched and is pending (if set, =1) or no LP0 interrupt is pending (if cleared, =0). An LP0 interrupt occurs when the link port buffers DMA is disabled (DEN=0) and either: The buffer is set to receive (TRAN=0), and the buffer is not empty The buffer is set to transmit (TRAN=1), and the buffer is not full

Note that LP0 is set irrespective of whether the link port is enabled in core mode or DMA mode. 1 LP1I Link Port Buffer 1 DMA Interrupt. Indicates whether an LP1 interrupt is latched and is pending (if set, =1) or no LP1 interrupt is pending (if cleared, =0). SPI Receive DMA Interrupt Latch. Indicates whether an SPIRI is latched and is pending (if set, =1) or no SPIRI is pending (if cleared, =0). SPI Transmit DMA Interrupt Latch. Indicates whether an SPITI is latched and is pending (if set, =1) or no SPITI is pending (if cleared, =0).

SPIRI

SPITI

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Registers

Table A-10. Link Port Interrupt Latch, Mask, and Mask Pointer Register (LIRPTL) Bit Definitions (Contd)
Bit 15-4 16 LP0MSK Name Definition Reserved Link Buffer 0 DMA Interrupt Mask. This bit unmasks the LP0 interrupt (if set, =1) or masks the LP0 interrupt (if cleared, =0). For more information on how interrupt masking works, see Interrupt Latch Register (IRPTL) on page A-27. Link Buffer 1 DMA Interrupt Mask. This bit unmasks the LP1 interrupt (if set, =1) or masks the LP1 interrupt (if cleared, =0). For more information on how interrupt masking works, see Interrupt Latch Register (IRPTL) on page A-27. SPI Receive DMA Interrupt Mask. This bit unmasks the SPIR interrupt (if set, =1) or masks the SPIR interrupt (if cleared, =0). For more information on how interrupt masking works, see Interrupt Latch Register (IRPTL) on page A-27. SPI Transmit DMA Interrupt Mask. This bit unmasks the SPIT interrupt (if set, =1) or masks the SPIT interrupt (if cleared, =0). For more information on how interrupt masking works, see Interrupt Latch Register (IRPTL) on page A-27. Reserved LP0MSKP Link Buffer 0 DMA Interrupt Mask Pointer. When the ADSP-21161 processor is servicing another interrupt, indicates whether the LP0 interrupt is unmasked (if set, =1) or the LP0 interrupt is masked (if cleared, =0). For more information on how interrupt mask pointers works, see Interrupt Mask Pointer Register (IMASKP) on page A-32. Link Buffer 1 DMA Interrupt Mask Pointer. When the processor is servicing another interrupt, this bit indicates whether the LP1 interrupt is unmasked (if set, =1) or the LP1 interrupt is masked (if cleared, =0). For more information on how interrupt mask pointers works, see Interrupt Mask Pointer Register (IMASKP) on page A-32.

17

LP1MSK

18

SPIRMSK

19

SPITMSK

23-20 24

25

LP1MSKP

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Program Sequencer Registers

Table A-10. Link Port Interrupt Latch, Mask, and Mask Pointer Register (LIRPTL) Bit Definitions (Contd)
Bit 26 Name SPIRMSKP Definition SPI Receive DMA Interrupt Mask Pointer. When the processor is servicing another interrupt, this bit indicates whether the SPIR interrupt is unmasked (if set, =1) or the SPIR interrupt is masked (if cleared, =0). For more information on how interrupt mask pointers works, see Interrupt Mask Pointer Register (IMASKP) on page A-32. SPI Transmit DMA Interrupt Mask Pointer. When the processor is servicing another interrupt, this bit indicates whether the SPIT interrupt is unmasked (if set, =1) or the SPIT interrupt is masked (if cleared, =0). For more information on how interrupt mask pointers works, see Interrupt Mask Pointer Register (IMASKP) on page A-32. Reserved

27

SPITMSKP

31-28

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LIRPTL
SPITMSKP

LP0MSK
Link Buffer 0 DMA Interrupt Mask

SPI Transmit DMA Interrupt Mask Pointer

LP1MSK
Link Buffer 1 DMA Interrupt Mask

SPIRMSKP
SPI Receive DMA Interrupt Mask Pointer

SPIRMSK
SPI Receive DMA Interrupt Mask

LP1MSKP
Link Buffer 1 DMA Interrupt Mask Pointer

SPITMSK
SPI Transmit DMA Interrupt Mask

LP0MSKP
Link Buffer 0 DMA Interrupt Mask Pointer 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 4 0 3 2 1 0 0 0

0 0

SPITI
SPI Transmit DMA Interrupt Latch (0x44)

LP0I
Link Buffer 0 DMA Interrupt Latch Interrupt Vector Address Offset- 0x38

SPIRI
SPI Receive DMA Interrupt Latch (0x40)

LP1I
Link Buffer 1 DMA Interrupt Latch (0x3c)

Figure A-11. LIRPTL Register

A-36

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Registers

Flag Value Register (FLAGS)

The FLAGS register is a non-memory-mapped, universal, system register (UREG and SREG). The reset value for these registers is 0x0000 0000. The FLAGS register indicates the state of the FLG[3:O] pins. When a FLG[3:O] pin is an output, the processor outputs a high in response to a program setting the pins bit in FLAGS. The I/O direction (input or output) selection of each bit is controlled by its FLG[3:O] bit in the MODE2 register. For more information, see FLG0O on page A-10. The FLAG register bit definitions are given in Table A-11 and Figure A-12. Table A-11. FLAGS Register (FLAGS) Bit Definitions
Bit 0 1 2 3 31-4 Name FLG0 FLG1 FLG2 FLG3 Definition FLAG0 Value. Indicates the state of the FLAG0 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG1 Value. Indicates the state of the FLAG1 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG2 Value. Indicates the state of the FLAG2 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG3 Value. Indicates the state of the FLAG3 pin, whether the pin is high (if set, =1) or low (if cleared, =0). Reserved

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Program Sequencer Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FLAGS

15 14 13 12 11 10 9 0 0 0 0 0 0 0

8 0

7 0

6 0

5 0

4 0

1 0

0 0

0 0

FLG2
0=FLG2 pin cleared 1=FGL2 pin set 0=FLG3 pin cleared 1=FGL3 pin set

FLG0
0=FLG0 pin cleared 1=FGL0 pin set 0=FLG1 pin cleared 1=FGL1 pin set

FLG3

FLG1

Figure A-12. FLAGS Register

IOFLAG Value Register

The IOFLAG register (Figure A-13 and Table A-12) is a memory-mapped, IO processor register. The reset value for this register is 0x0000 0000. The IOFLAG register indicates status and control information for the FLG pins. When a FLG[11:4] pin is an output, the processor outputs a high when a program sets the pins bit in IOFLAG. Bits 7-0 of the IOFLAG register reflect the status of FLG[11:4] pins and bits 15-8 control the direction (input or output) of these flags. A value of 0 programs the flag as an input while a value of 1 programs it as an output. You cannot directly execute bit wise operations such as BIT TST or BIT CLR

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Registers

on these flags. However, it is possible to execute these operations indirectly by writing to system registers such as USTAT1, USTAT2, USTAT3 or USTAT4. Table A-12. IOFLAG Register (IOFLAG) Bit Definitions
Bit 0 1 2 3 4 5 6 7 8 Name FLG4 FLG5 FLG6 FLG7 FLG8 FLG9 FLG10 FLG11 FLG4O Definition FLAG4 Value. Indicates the state of the FLAG4 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG5 Value. Indicates the state of the FLAG5 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG6 Value. Indicates the state of the FLAG6 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG7 Value. Indicates the state of the FLAG7 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG8 Value. Indicates the state of the FLAG8 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG9 Value. Indicates the state of the FLAG9 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG10 Value. Indicates the state of the FLAG10 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG11 Value. Indicates the state of the FLAG11 pin, whether the pin is high (if set, =1) or low (if cleared, =0). FLAG4 Output Select. This bit selects the I/O direction for the FLAG4 pin; the flag is programmed as an output (if set, =1) or input (if cleared, =0). FLAG5 Output Select. This bit selects the I/O direction for the FLAG5 pin; the flag is programmed as an output (if set, =1) or input (if cleared, =0). FLAG6 Output Select. This bit selects the I/O direction for the FLAG6 pin; the flag is programmed as an output (if set, =1) or input (if cleared, =0). FLAG7 Output Select. This bit selects the I/O direction for the FLAG7 pin; the flag is programmed as an output (if set, =1) or input (if cleared, =0).

FLG5O

10

FLG6O

11

FLG7O

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Program Sequencer Registers

Table A-12. IOFLAG Register (IOFLAG) Bit Definitions (Contd)

Bit 12 Name FLG8O Definition FLAG8 Output Select. This bit selects the I/O direction for the FLAG8, the flag is programmed as an output (if set, =1) or input (if cleared, =0). FLAG9 Output Select. This bit selects the I/O direction for the FLAG9, the flag is programmed as an output (if set, =1) or input (if cleared, =0). FLAG10 Output Select. This bit selects the I/O direction for the FLAG10, the flag is programmed as an output (if set, =1) or input (if cleared, =0). FLAG11 Output Select. This bit selects the I/O direction for the FLAG11pin, the flag is programmed as an output (if set, =1) or input (if cleared, =0). Reserved

13

FLG9O

14

FLG10O

15

FLG11O

31-16

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ADSP-21161 SHARC Processor Hardware Reference

Registers

31 30 29 28 27 26 25 24 23 22 21 20

19 18 17 16 0 0 0 0

IOFLAG
0x1B

15 14 0 0

13 12 0 0

11 10 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

FLG11O
0=FLAG11 Input 1=FLAG11 Output

FLG4
FLAG4 Value (Low=0, High=1)

FLG10O
0=FLAG10 Input 1=FLAG10 Output

FLG5
FLAG5 Value

FLG9O
0=FLAG9 Input 1=FLAG9 Output

FLG6
FLAG6 Value

FLG8O
0=FLAG8 Input 1=FLAG8 Output

FLG7
FLAG7 Value

FLG7O
0=FLAG7 Input 1=FLAG7 Output

FLG8
FLAG8 Value

FLG6O
0=FLAG6 Input 1=FLAG6 Output

FLG9
FLAG9 Value

FLG50
0=FLAG5 Input 1=FLAG5 Output

FLG10
FLAG10 Value

FLG40
0=FLAG4 Input 1=FLAG4 Output

FLG11
FLAG11 Value

Figure A-13. IOFLAG Register

Program Counter Register (PC)

The PC register is a non-memory-mapped, universal register (UREG only). The Program Counter register is the last stage in the fetch-decode-execute instruction pipeline and contains the 24-bit address of the instruction that the ADSP-21161 processor executes on the next cycle. The PC couples with the Program Counter Stack, PCSTK, which stores return addresses and top-of-loop addresses. All addresses generated by the sequencer are 24-bit program memory instruction addresses. The amount of addressable space is 62.5 Mwords for Non-SDRAM and 254 Mwords for SDRAM.

ADSP-21161 SHARC Processor Hardware Reference

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Program Sequencer Registers

As shown in Figure A-14, the address buses can handle 32-bit addresses, but the program sequencer only generates 24-bit addresses over the PM bus. Since the sequencer generates 24-bit addresses, sequencing is limited to the low 64 Mwords of the processors 254 Mword memory map. PM and DM Address Buses and DAGs Can Handle 32-Bit Addresses Program Sequencer Handles 24-Bit Addresses

V Field

E Field

M Field S Field

Bits 19-17, System (Internal) Memory Bits 20, Multiprocessor Memory Bits 23-21, External Memory Bits 27-24, External Banked Memory Four fields in the address identify the type of memory being addressed.

Figure A-14. PM and DM Bus Addresses Versus Sequencing Addresses

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Registers

Table A-13 describes the three fields that appear in Figure A-14. The content of the External (E), Multiprocessor (M), and System (S) fields in the address route the data or instruction access to the memory space. Table A-13. PM and DM Address Bus E, M, and S Fields
Bit Field E Description External Address Values in this field have the following meaning: all zeros non-zero M The address is in the IOP registers of another ADSP-21161 processor (M and S activated) The address is in external memory; with the E bits active, remaining bits [20-0] are a valid address

Multiprocessor Values in this field have the following meaning: non-zero 1 0 ID of another ADSP-21161 processor Write to IOP register of an ADSP-21161 processor. This field is only set for accesses between ADSP-21161 processors. Address in the processors own internal memory

System Values in this field have the following meaning: 000 001 01x 1xx Address of an IOP register Address in Long Word Addressing space Address in Normal Word Addressing space Address in Short Word Addressing space

Virtual Values in this field have the following meaning: 00 Depends on E, S1-0, and M bits; address corresponds to locals internal or external (bank 0) memory or to remote processors IOP space. External memory bank 1, local processor External memory bank 2, local processor External memory bank 3, local processor

01 10 11

ADSP-21161 SHARC Processor Hardware Reference

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Program Sequencer Registers

Program Counter Stack Register (PCSTK)

This is a non-memory-mapped, universal register (UREG only). The Program Counter Stack register contains the address of the top of the PC stack. This register is a readable and writable register.

Program Counter Stack Pointer Register (PCSTKP)

The PCSTKP register is a non-memory-mapped, universal register (UREG only). The Program Counter Stack Pointer register contains the value of PCSTKP. This value is given as follows: 0 when the PC stack is empty, 1...30 when the stack contains data, and 31 when the stack overflows. This register is readable and writable. A write to PCSTKP takes effect after a one-cycle delay. If the PC stack is overflowed, a write to PCSTKP has no effect.

Fetch Address Register (FADDR)

The FADDR register is a non-memory-mapped, universal register (UREG only). The Fetch Address register is the first stage in the fetch-decode-execute instruction pipeline and contains the 24-bit address of the instruction that the processor fetches from memory on the next cycle.

Decode Address Register (DADDR)

The DADDR register is a non-memory-mapped, universal register (UREG only). The Decode Address register is the second stage in the fetch-decode-execute instruction pipeline and contains the 24-bit address of the instruction that the processor decodes on the next cycle.

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Registers

Loop Address Stack Register (LADDR)

The LADDR register is a non-memory-mapped, universal register (UREG only). The Loop Address Stack is six levels deep by 32 bits wide. The 32-bit word of each level consists of a 24-bit loop termination address, a 5-bit termination code, and a 2-bit loop type code. Table A-14. Loop Address Stack Register (LADDR)
Bits 0-23 24-28 29 30-31 Value

Lloop termination address

Termination code Reserved (always reads 0) Loop type code 00 = arithmetic condition-based (not LCE) 01 = counter-based, length 1 10 = counter-based, length 2 11 = counter-based, length > 2

Current Loop Counter Register (CURLCNTR)

The CURLCNTR register is a non-memory-mapped, universal register (UREG only). The Current Loop Counter register provides access to the loop counter stack and tracks iterations for the DO UNTIL LCE loop being executed. For more information on how to use CURLCNTR, see Loop Counter Stack on page 3-30.

Loop Counter Register (LCNTR)

The LCNTR register is a non-memory-mapped, universal register (UREG only). The Loop Counter register provides access to the loop counter stack and holds the count value before the DO UNTIL LCE loop is executed. For more information on how to use LCNTR, see Loop Counter Stack on page 3-30.

ADSP-21161 SHARC Processor Hardware Reference

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Data Address Generator Registers

Timer Period Register (TPERIOD)

The TPERIOD register is a non-memory-mapped, universal register (UREG only). The Timer Period register contains the decrementing timer count value, counting down the cycles between timer interrupts. For more information on how to use the timer, see Timer and Sequencing on page 3-50.

Timer Count Register (TCOUNT)

The TCOUNT register is a non-memory-mapped, universal register (UREG only). The Timer Count register contains the timer period, indicating the number of cycles between timer interrupts. For more information on how to use the timer, see Timer and Sequencing on page 3-50.

Data Address Generator Registers

The ADSP-21161 processors Data Address Generator (DAG) registers hold data addresses, modify values, and circular buffer configurations. Using these registers, the DAGs can automatically increment addressing for ranges of data locations (a buffer). Table A-15. Data Address Generator Universal Registers (UREG only)
Register Index Registers (Ix) on page A-47 Modify Registers (Mx) on page A-47 Length and Base Registers (Lx,Bx) on page A-47 Initialization After Reset Undefined Undefined Undefined

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Registers

Index Registers (Ix)

The Ix registers are non-memory-mapped, universal registers (UREG only). The Data Address Generators store addresses in Index registers (I0-I7 for DAG1 and I8-I15 for DAG2). An index register holds an address and acts as a pointer to a memory location. For more information, see Data Address Generator on page 4-1.

Modify Registers (Mx)

The Mx register are non-memory-mapped, universal registers (UREG only). The Data Address Generators update stored addresses using Modify registers (M0-M7 for DAG1 and M8-M15 for DAG2). A modify register provides the increment or step size by which an index register is pre- or post-modified during a register move. For more information, see Data Address Generator on page 4-1.

Length and Base Registers (Lx,Bx)

The Lx and Bx registers are non-memory-mapped, universal registers (UREG only). The Data Address Generators control circular buffering operations with Length and Base registers (L0-L7 and B0-B7 for DAG1 and L8-L15 and B8-B15 for DAG2). Length and base registers setup the range of addresses and the starting address for a circular buffer. For more information, see Data Address Generator on page 4-1.

I/O Processor Registers

The I/O processors registers are accessible as part of the processors memory map. Table A-17 on page A-51 lists the I/O processors memory-mapped registers in address order and provides a cross reference to a description of each register. These registers occupy addresses 0x0000

ADSP-21161 SHARC Processor Hardware Reference

A-47

I/O Processor Registers

0000 through 0x0000 01FF of the memory map. The I/O registers control the following operations: External port DMA, Link port DMA, Serial port DMA and SPI port DMA. I/O processor registers have a one cycle effect latency (changes take effect on the second cycle after the change). Since the I/O processors registers are part of the processors memory map, buses access these registers as locations in memory. While these registers act as memory-mapped locations, they are separate from the processors internal memory and have different bus access. One bus can access one I/O processor register from one I/O processor register group at a time. Table A-16 lists the I/O processor register groups. When there is contention among the buses for access to registers in the same I/O processor register group, the processor arbitrates register access as follows: External Port (EP) bus accesses (highest priority) Data Memory (DM) bus accesses Program Memory (PM) bus accesses I/O processor (I/O) bus (lowest priority) accesses DMA parameter register or DMASTAT register conflicts There is a one cycle DMA stall if an access to a DMA parameter register or the DMASTAT register conflicts with DMA address generation. For example, one cycle stall occurs when writing to a DMA register while a register update is taking place. Similarly, a one cycle stall occurs when reading from a DMA register while DMA chaining is taking place. The bus with highest priority gets access to the I/O processor register group, and the other buses are held off from accessing that I/O processor register group until that access been completed.

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Registers

There is one exception to this access contention rule. The I/O bus and EP bus can simultaneously access the EP (External Port) group of registers, allowing DMA transfers to internal memory at full speed. Table A-16. I/O Processor Register Groups
Register Group System Control (SC) Registers DMA Address (DA) Registers I/O Processor Registers In This Group SYSCON, VIRPT, WAIT, SYSTAT, MSGR0, MSGR1, MSGR2, MSGR3, MSGR4, MSGR5, MSGR6, MSGR7, BMAX, BCNT, PC_SHDW, IOFLAG, MODE2_SHDW, DMASTAT II0A, II0B, IM0A, IM0B, C0A, C0B, CP0A, CP0B, GP0A, GP0B, II1A, II1B, IM1A, IM1B, C1A, C1B, CP1A, CP1B, GP1A, GP1B, II2A, II2B, IM2A, IM2B, C2A, C2B, CP2A, CP2B, GP2A, GP2B, II3A, II3B, IM3A, IM3B, C3A, C3B, CP3A, CP3B, GP3A, GP3B, IILB0 (IISRX), IMLB0 (IMSRX), CLB0 (CSRX), GPLB0 (GPSRX), IILB1(IISTX), IMLB1 (IMSTX), CLB1, GPLB0 (GPSTX), IIEP0, IMEP0, CEP0, CPEP0, GPEP0, EIEP0, EMEP0, ECEP0, IIEP1, IMEP1, CEP1, CPEP1, GPEP1, EIEP1, EMEP1, ECEP1, IIEP2, IMEP2, CEP2, CPEP2, GPEP2, EIEP2, EMEP2, ECEP2, IIEP3, IMEP3, CEP3, CPEP3, GPEP3, EIEP3, EMEP3, ECEP3, EI13, EM13, EC13 EPB0, EPB1, EPB2, EPB3, DMAC10,DMAC11,DMAC12,DMAC13

External Port (EP) Registers

ADSP-21161 SHARC Processor Hardware Reference

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I/O Processor Registers

Table A-16. I/O Processor Register Groups (Contd)

Register Group SDRAM Controller (SD) Link, SPI & Serial Port (LSP) Registers I/O Processor Registers In This Group SDCTL, SDRDIV LBUF0, LBUF1, LCTL, LSRQ SPIRX, SPITX, SPICTL, SPISTAT RX0A, RX0B, TX0A, TX0B, SPCTL0, DIV0, CNT0, MR0CS0, MR0CCS0, MR0CS1, MR0CCS1, MR0CS2, MR0CCS2, MR0CS3, MR0CCS3 RX1A, RX1B, TX1A, TX1B, SPCTL1, DIV1, CNT1, MT1CS0, MT1CCS0, MT1CS1, MT1CCS1, MT1CS2, MT1CCS2, MT1CS3, MT1CCS3 RX2A, RX2B, TX2A, TX2B, SPCTL2, DIV2, CNT2, MR2CS0, MR2CCS0, MR2CS1, MR2CCS1, MR2CS2, MR2CCS2, MR2CS3, MR2CCS3 RX3A, RX3B, TX3A, TX3B, SPCTL3, DIV3, CNT3, MT3CS0, MT3CCS0, MT3CS1, MT3CCS1, MT3CS2, MT3CCS2, MT3CS3, MT3CCS3 SP02MCTL, SP13MCTL

Since the I/O processor registers are memory-mapped, the ADSP-21161 processors architecture does not allow programs to directly transfer data between these registers and other memory locations, except as part of a DMA operation. To read or write I/O processor registers, programs must use the processor core registers. The following example code shows a value being transferred from memory to the USTAT1 register, then the value is transferred to the I/O processor WAIT registers.
USTAT2= 0x108421; /* 1st instr. to be executed after reset */ DM(WAIT)=USTAT2; /* Set external memory waitstates to 0 */

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Registers

The register names for I/O processor registers are not part of the processors assembly syntax. To ease access to these registers, programs should use the #include command to incorporate a file containing the registers symbolic names and addresses. An example #include file appears in the Register and Bit #Defines (def21161.h) on page A-121. Table A-17. I/O Processor Registers Memory Map
Register Address 0x000 0x001 0x002 0x003 0x004 0x006 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x014 Register Name SYSCON VIRPT WAIT SYSTAT EPB0 EPB1 MSGR0 MSGR1 MSGR2 MSGR3 MSGR4 MSGR5 MSGR6 MSGR7 PC_SHDW MODE2_ SHDW EPB2 Initialization After Reset 0x0001 0020 0x0004 0014 0x01ce 739c 0x000n 0nn0 ni ni ni ni ni ni ni ni ni ni ni 0xnn00 0000 ni Register Group Reference SC SC SC SC EP EP SC SC SC SC SC SC SC SC SC SC EP page A-60 page A-63 page A-65 page A-69 page A-76 page A-76 page A-77 page A-77 page A-77 page A-77 page A-77 page A-77 page A-77 page A-77 page A-77 page A-78 page A-76

Notes: An ni in the Initialization column indicates that the register is Not Initialized. For information on Register Groups, see Table A-16 on page A-49.

ADSP-21161 SHARC Processor Hardware Reference

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I/O Processor Registers

Table A-17. I/O Processor Registers Memory Map (Contd)

Register Address 0x016 0x018 0x019 0x01B 0x01C 0x01D 0x01E 0x01F 0x030 0x031 0x032 0x033 0x034 0x037 0x038 0x039 0x03A 0x03B 0x03C 0x040 0x041 0x042 Register Name EPB3 BMAX BCNT IOFLAG DMAC10 DMAC11 DMAC12 DMAC13 IILB0/IISRX IMLB0/IMSRX CLB0/CSRX CPLB0 GPLB0/GPSRX DMASTAT IILB1/IISTX IMLB1/IMSTX CLB1/CSTX CPLB1 GPLB1/GPSTX IIEP0 IMEP0 CEP0 Initialization After Reset ni 0x0000 0000 0x0000 0000 0x0000 0000 ni
1

Register Group Reference EP SC SC SC EP EP EP EP DA DA DA DA DA SC DA DA DA DA DA DA DA DA page A-76 page A-79 page A-79 page A-38 page A-80 page A-80 page A-80 page A-80 page A-90 -

0x0000 0000 0x0000 0000 0x0000 0000 ni ni ni ni ni ni ni ni ni ni ni ni1 ni

1

ni1

Notes: An ni in the Initialization column indicates that the register is Not Initialized. For information on Register Groups, see Table A-16 on page A-49.

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Registers

Table A-17. I/O Processor Registers Memory Map (Contd)

Register Address 0x043 0x044 0x045 0x046 0x047 0x048 0x049 0x04A 0x04B 0x04C 0x04D 0x04E 0x04F 0x050 0x051 0x052 0x053 0x054 0x055 0x056 0x057 0x058 Register Name CPEP0 GPEP0 EIEP0 EMEP0 ECEP0 IIEP1 IMEP1 CEP1 CPEP1 GPEP1 EIEP1 EMEP1 ECEP1 IIEP2 IMEP2 CEP2 CPEP2 GPEP2 EIEP2 EMEP2 ECEP2 IIEP3 Initialization After Reset ni1 ni1 ni
1

Register Group Reference DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA -

ni1 ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni
1

Notes: An ni in the Initialization column indicates that the register is Not Initialized. For information on Register Groups, see Table A-16 on page A-49.

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Table A-17. I/O Processor Registers Memory Map (Contd)

Register Address 0x059 0x05A 0x05B 0x05C 0x05D 0x05E 0x05F 0x060 0x061 0x062 0x063 0x064 0x067-65 0x068 0x069 0x06A 0x06B 0x06C 0x06F-6D 0x070 0x071 0x072 Register Name IMEP3 CEP3 CPEP3 GPEP3 EIEP3 EMEP3 ECEP3 II0A IM0A C0A CP0A GP0A Reserved II1A IM1A C1A CP1A GP1A Reserved II2A IM2A C2A ni ni ni DA DA DA ni ni ni ni ni DA DA DA DA DA Initialization After Reset ni ni ni ni ni ni ni ni ni ni ni ni Register Group Reference DA DA DA DA DA DA DA DA DA DA DA DA -

Notes: An ni in the Initialization column indicates that the register is Not Initialized. For information on Register Groups, see Table A-16 on page A-49.

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Registers

Table A-17. I/O Processor Registers Memory Map (Contd)

Register Address 0x073 0x074 0x078 0x079 0x07A 0x07B 0x07C 0x080 0x081 0x082 0x083 0x084 0x088 0x089 0x08A 0x08B 0x08C 0x090 0x091 0x092 0x093 0x094 Register Name CP2A GP2A II3A IM3A C3A CP3A GP3A II0B IM0B C0B CP0B GP0B II1B IM1B C1B CP1B GP1B II2B IM2B C2B CP2B GP2B Initialization After Reset ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni ni Register Group Reference DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA -

Notes: An ni in the Initialization column indicates that the register is Not Initialized. For information on Register Groups, see Table A-16 on page A-49.

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I/O Processor Registers

Table A-17. I/O Processor Registers Memory Map (Contd)

Register Address 0x098 0x099 0x09A 0x09B 0x09C 0x0B4 0x0B5 0x0B6 0x0B7 0x0B8 0x0B9 0x0C0 0x0C2 0x0CC 0x0D0 0x0D7 0x0DF 0x1C0 0x1C1 0x1C2 0x1C3 0x1C4 0x1C5 Register Name II3B IM3B C3B CP3B GP3B SPICTL SPISTAT SPITX SPIRX SDCTL SDRDIV LBUF0 LBUF1 LCTL LSRQ Reserved SPCTL0 TX0A TX0B RX0A RX0B DIV0 0x0000 0000 ni ni ni ni ni SC SC SC SC SC SC page A-114 page A-112 page A-112 page A-112 page A-112 page A-112 Initialization After Reset ni ni ni ni ni 0x0000 0000 ni ni ni ni ni ni ni 0x0000 0000 0x0000 0000 Register Group Reference DA DA DA DA DA LSP LSP LSP LSP SD SD LSP LSP LSP LSP page A-117 page A-115 page A-121 page A-121 page A-73 page A-72 page A-92 page A-92 page A-92 page A-98

Notes: An ni in the Initialization column indicates that the register is Not Initialized. For information on Register Groups, see Table A-16 on page A-49.

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Registers

Table A-17. I/O Processor Registers Memory Map (Contd)

Register Address 0x1C6 0x1C7 0x1C8 0x1C9 0x1CA 0x1CB 0x1CC 0x1CD 0x1CE 0x1D0 0x1D1 0x1D2 0x1D3 0x1D4 0x1D5 0x1D6 0x1D7 0x1D8 0x1D9 0x1DA 0x1DB 0x1DC Register Name CNT0 MR0CS0 MR0CCS0 MR0CS1 MR0CCS1 MR0CS2 MR0CCS2 MR0CS3 MR0CCS3 SPCTL2 TX2A TX2B RX2A RX2B DIV2 CNT2 MT2CS0 MT2CCS0 MT2CS1 MT2CCS1 MT2CS2 MT2CCS2 Initialization After Reset ni ni ni ni ni ni ni ni ni 0x0000 0000 ni ni ni ni ni ni ni ni ni ni ni ni Register Group Reference SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC page A-113 page A-113 page A-113 page A-113 page A-113 page A-113 page A-114 page A-114 page A-114 page A-114 page A-114 page A-114 page A-114 page A-114 page A-100 page A-112 page A-112 page A-112 page A-112 page A-112

Notes: An ni in the Initialization column indicates that the register is Not Initialized. For information on Register Groups, see Table A-16 on page A-49.

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Table A-17. I/O Processor Registers Memory Map (Contd)

Register Address 0x1DD 0x1DE 0x1DF 0x1E0 0x1E1 0x1E2 0x1E3 0x1E4 0x1E5 0x1E6 0x1E7 0x1E8 0x1E9 0x1EA 0x1EB 0x1EC 0x1ED 0x1EE 0x1F0 0x1F1 0x1F2 0x1F3 Register Name MT2CS3 MT2CCS3 SP02MCTL SPCTL1 TX1A TX1B RX1A RX1B DIV1 CNT1 MR1CS0 MR1CCS0 MR1CS1 MR1CCS1 MR1CS2 MR1CCS2 MR1CS3 MR1CCS3 SPCTL3 TX3A TX3B RX3A Initialization After Reset ni ni 0x0000 0000 0x0000 0000 ni ni ni ni ni ni ni ni ni ni ni ni ni ni 0x0000 0000 ni ni ni Register Group Reference SC SC SC LSP LSP LSP LSP LSP LSP LSP LSP LSP LSP LSP LSP LSP LSP LSP SC LSP LSP LSP page A-113 page A-113 page A-109 page A-109 page A-112 page A-112 page A-112 page A-112 page A-112 page A-114 page A-114 page A-114 page A-114 page A-114 page A-114 page A-114 page A-114 page A-100 page A-112 page A-112 page A-112

Notes: An ni in the Initialization column indicates that the register is Not Initialized. For information on Register Groups, see Table A-16 on page A-49.

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Registers

Table A-17. I/O Processor Registers Memory Map (Contd)

Register Address 0x1F4 0x1F5 0x1F6 0x1F7 0x1F8 0x1F9 0x1FA 0x1FB 0x1FC 0x1FD 0x1FE 0x1FF Register Name RX3B DIV3 CNT3 MT3CS0 MT3CCS0 MT3CS1 MT3CCS1 MT3CS2 MT3CCS2 MT3CS3 MT3CCS3 SP13MCTL Initialization After Reset ni ni ni ni ni ni ni ni ni ni ni 0x0000 0000 Register Group Reference LSP LSP LSP LSP LSP LSP LSP LSP LSP LSP LSP SC page A-112 page A-112 page A-113 page A-113 page A-113 page A-113 page A-113 page A-113 page A-113 page A-113 page A-109

Notes: An ni in the Initialization column indicates that the register is Not Initialized. For information on Register Groups, see Table A-16 on page A-49. 1 Initialization depends on the booting mode.

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System Configuration Register (SYSCON)

The SYSCON register, described in Table A-18 and Figure A-15, is used to set up system configuration selections. This registers address is 0x00. The reset value for this register is 0x0001 0020, based on HBW configured for an 8-bit host. Table A-18. System Configuration Register (SYSCON) Bit Definitions
Bit(s) 0 Name SRST Definition Software Reset. This bit resets (when set, =1) the processor. When a program sets (=1) SRST, the processor responds to the non-maskable RSTI interrupt and clears (=0) SRST. Boot Select Override. This bit enables (if set, =1) or disables (if cleared, =0) access to Boot Memory Space. When BSO is set, the processor uses the BMS select line (instead of MS3-0) to perform DMA channel 10 accesses of external memory. The processor uses 8-to 48-bit packing when reading from 8-bit boot memory space, but does no packing on writes to this space. Internal Interrupt Vector Table. This bit forces placement of the interrupt vector table at address 0x0004 0000 regardless of booting mode (if 1) or allows placement of the interrupt vector table as selected by the booting mode (if 0). Reserved HBW Host Bit Width. These bits select the bit width for host access as follows: 00= 32-bit, 01= 16-bit, 10=8-bit (default), 11=reserved. Reserved HMSWF Host Most Significant Word First Packing Select. This bit selects the word packing order for host accesses as most-significant-word first (if set, =1) or least-significant-word first (if cleared, =0). Reserved IMDW0 Internal Memory Block 0 Data Width. This bit selects the normal word data access size for internal memory Block 0 as 40-bit data (if set, =1) or 32-bit data (if cleared, =0).

BSO

IIVT

3 5-4 6 7

8 9

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Registers

Table A-18. System Configuration Register (SYSCON) Bit Definitions (Contd)

Bit(s) 10 Name IMDW1 Definition Internal Memory Block 1 Data Width. This bit selects the normal word data access size for internal memory Block 1 as 40-bit data (if set, =1) or 32-bit data (if cleared, =0). Active Drive REDY. This bit selects line driver type for the processors REDY pin as active drive (a/d) (if set, =1) or open drain (o/d) (if cleared, =0). Reserved BHD Buffer Hang Disable. This bit controls whether the processor core proceeds (hang disabled if set, =1) or is held-off (hang enabled if cleared, =0) when the core tries to read from an empty EPBx, RXx, SPIRX, or LBUFx buffer or tries to write to a full EPBx, TXx, SPITX, or LBUFx buffer. Is cleared by default at reset. External Bus Priority. These bits select the priority for the I/O processors EP bus when arbitrating access to the processors external port as follows: 00priority rotates between DM or PM and IO buses, 01the winning DM or PM bus has priority over the IO bus, 10the IO bus has priority over the winning DM or PM bus. External Port DMA Channel Priority Rotation Enable. This bit enables (rotates if set, =1) or disables (fixed if cleared, =0) priority rotation among external port DMA channels (channel 10-13). Link Port DMA Channel Priority Rotation Enable. This bit enables (rotates if set, =1) or disables (fixed if cleared, =0) priority rotation among link port DMA channels (channel 8-9). LinkExternal Port DMA Channel Priority Rotation Enable. This bit enables (rotates if set, =1) or disables (fixed if cleared, =0) priority rotation between link port DMA channels (channel 8-9) and external port DMA channels (channel10-13). CLKOUT Disable. This bit disables (if set, =1) or enables (if cleared, =0) the processor clock output on the CLKOUT pin. If enabled, the processor outputs the clock signal on CLKOUT. If disabled, the processor three-states the CLKOUT pin. Note: Is ignored if bit 23 COPT is set.

11

ADREDY

15-12 16

18-17

EBPR

19

DCPR

20

LDCPR

21

PRROT

22

COD

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Table A-18. System Configuration Register (SYSCON) Bit Definitions (Contd)

Bit(s) 23 Name COPT Definition CLKOUT Option. This bit enables (if set, =1) the master device in a multiprocessor system to drive the CLKOUT pin. If cleared (=0), CLKOUT is controlled by bit 22 COD. Reserved IPACK External Packed Instruction Execution Mode. This bit sets the packing of instructions as follows: 00=32- to 48-bit packing, 01=no packing, 10=16- to 48-bit packing, 11=8- to 48-bit packing.

29-24 31-30

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Registers

SYSCON (0x0000)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IPACK
External Packed Instruction Execution Mode 00=32 to 48 packed instruction execution 01=Full 48-bit instruction execution /No-Packing Mode 10=16 to 48 packed instruction execution 11=8 to 48 packed instruction execution

BHD
Buffer Hang Disable 0=buffer hang enabled (DEFAULT), 1=disabled buffer hang

EBPR
External Bus Priority 00=even priority between core processor and IOP bus 01=core processor priority, 10=I/O processor priority

COPT
CLKOUT Option 0=CLKOUT controlled by COD bit 1=CLKOUT driven by MMS master

DCPR
DMA rotating access priority DMA channels 10-13, 1= rotating, 0=sequential

COD
Clock Out Disable 0=CLKOUT Enabled, 1=CLKOUT Disabled

LDCPR
DMA rotating access priority DMA channels 8 & 9 1=rotating, 0=sequential

PRROT
Link Port/External Port Rotating Priority 1=rotating priority, 0=fixed priority between DMA chs 8/9 & 10/11/12/13 15 14 13 12 11 10 9 1 1 0 1 0 0 0

8 0

7 0

6 0

5 1

4 0

3 0

2 0

1 0

0 0

ADREDY
Active Drive REDY 0=open drain (o/d), 1=active drive (a/d)

SRST
Soft Reset

IMDW1
Internal Memory Block 1 Data Width 0=32-bit data, 1=40-bit data Internal Memory Block 0 Data Width 0=32-bit data, 1=40-bit data

BSO IIVT

Boot Select Override Internal Interrupt Vector Table (no boot mode)

IMDW0

HBW

Host Bus Width 00=32-bit host, 01=16-bit host, 10=8-bit host

HMSWF

Host Packing Order 0=LSW First, 1=MSW First

Figure A-15. SYSCON Register

Vector Interrupt Address Register (VIRPT)

The VIRPT registers address is 0x01. The reset value for this register is 0x0004 0014. In no boot mode, the reset value is 0x0020 0014 because the interrupt resides in external memory. The sequencer uses the VIRPT register (Table A-19 and Figure A-16)to support multiprocessor vector interrupts. The vector interrupt (VIRPTI) permits passing interprocessor

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I/O Processor Registers

commands in multiple-processor systems. This interrupt occurs when an external processor (a host or another processor) writes an address to the VIRPT register, inserting a new vector address for VIRPT. Table A-19. Vector Interrupt Address Register (VIRPT) Bit Definitions
Bit(s) 23-0 Name VIRPTA Definition Vector Interrupt Address. These bits contain the multiprocessor interrupts vector (address). When an external processor loads an address into this register, the processor pushes the status stack and starts executing the routine at the vector address. Vector Interrupt (optional) Data. These bits contain optional data that the external processor may pass to the interrupt service routine.

31-24

VIRPTD

VIRPT
(0x01)

31 30 29 28 27 26 25 24 23 22 21 20 0 0 0 0 0 0 0 0 0 0 0 0

19 18 17 16 0 1 0 0

VIRPTD
Vector Interrupt (optional) Data (contains optional data from extern processor for ISR)

15 14 13 12 0 0 0 0

11 10 0 0

9 0

8 0

7 0

6 0

5 0

4 1

3 0

2 1

1 0

0 0

VIRPTA
Vector Interrupt Address (contains interrupt vector address loaded by extern processor)

Figure A-16. VIRPT Register

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External Memory Waitstate and Access Mode Register (WAIT)

The WAIT register, shown in Table A-20 and Figure A-17, has an address of 0x02. The reset value for this register is 0x01ce 739c, which equates to the following processor external memory settings: asynchronous access mode for all external memory banks, seven waitstates with a hold cycle for all accesses to external memory banks, external DRAM page size of 256 words (if installed), and disable idle cycle for DMA handshake.

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Table A-20. External Memory Setup Register (WAIT) Bit Definitions

Bit(s) 1-0 Name EB0AM Definition External Bank 0 Access Mode. These bits select the access mode for external memory Bank 0 as follows: EBxAM 00 External Bank Access Mode Asynchronousprocessor RD and WR strobes change before CLKOUTs edgeaccesses use the waitstate count setting from EBxWS and require external acknowledge (ACK), allowing a de-asserted ACK to extend the access time. Synchronousprocessor RD and WR strobes change on CLKOUTs edgereads use the waitstate count setting from EBxWS (minimum EBxWS=001); writes are 0-wait state. Synchronousprocessor RD and WR strobes change on CLKOUTs edgereads use the waitstate count setting from EBxWS (minimum EBxWS=001); writes are 1-wait state. Reserved

01

10

11 4-2 EB0WS

External Bank 0 Waitstates. These bit fields select the waitstates for external memory Bank 0 as follows: EBxWS 000 001 010 011 100 101 110 111 # of Waitstates 0 1 2 3 4 5 6 7 Hold Time Cycle? no no yes yes yes yes yes yes

Note that Hold Cycles applies to asynchronous mode only. 6-5 9-7 11-10 EB1AM EB1WS EB2AM External Bank 1 Access Mode. (see EB0AM definition) External Bank 1 Waitstates. (see EB0WS definition) External Bank 2 Access Mode. (see EB0AM definition)

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Table A-20. External Memory Setup Register (WAIT) Bit Definitions (Contd)
Bit(s) 14-12 16-15 19-17 21-20 24-22 29-25 30 HIDMA Name EB2WS EB3AM EB3WS RBAM RBWS Definition External Bank 2 Waitstates. (see EB0WS definition) External Bank 3 Access Mode. (see EB0AM definition) External Bank 3 Waitstates. (see EB0WS definition) ROM Boot Access Mode. (see EB0AM definition) ROM Boot Waitstates. (see EB0WS definition) Reserved Handshake and Idle for DMA Enable. This bit enables (if set, =1) or disables (if cleared, =0) adding an idle cycle after every memory access for DMAs with handshaking (DMAR-DMAG). The added cycle reduces bus contention by accommodating devices with a slow three-state time. Also, the added cycle accommodates long write recovery time by de-asserting DMAG longer. 31 Reserved

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WAIT (0x0002)

1 1

HIDMA
Handshake and Idle for DMA enable 0 =no idle cycle 1=adds an idle cycle after every handshake DMA DMAG asserted longer reduces bus contention for slower devices

EB3AM
External Bank 3 Access Mode

EB3WS
External Bank 3 waitstates

RBAM
ROM Boot Access Mode

RBWS
ROM Boot Waitstates

15 14 13 12 11 10 9 0 1 1 1 0 0 1

8 1

7 1

6 0

5 0

4 1

3 1

2 1

1 0

0 0

EB2WS
External Bank 2 waitstates

EB0AM
External Bank 0 Access Mode 00=Async, uses both internal waitstate& ext ACK 01=Sync (RD~ and WR~ change on CLKOUTsedge) min 2 cycle reads, 1 cycle writes (EP0WS=001) 10=Sync (RD~ and WR~ change on CLKOUTsedge) min 2 cycle reads, 2 cycles writes (EP0WS=001) 11= reserved External Bank 0 Waitstates 000= 0 waitstates , no hold time cycle 001=1 waitstate, no hold time cycle, minimum for sync 010=2 waitstates, hold time cycle 011=3 waitstates, hold time cycle 100=4 waitstates, hold time cycle 101=5 waitstates, hold time cycle 110=6 waitstates, hold time cycle 111=7 waitstates, hold time cycle (hold time cycles for Async Mode only)

EB2AM
External Bank 2 Access Mode

EB1WS
External Bank 1 waitstates

EB1AM
External Bank 1 Access Mode

EB0WS

Figure A-17. WAIT Register

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System Status Register (SYSTAT)

The SYSTAT registers address is 0x03. The reset value has all bits initialized to zero, except for the IDC, CRBM, CRAT fields, which are set from values on the ADSP-21161 processors pins. This register is described in Table A-21 and Figure A-18. Table A-21. System Status Register (SYSTAT) Bit Definitions
Bit(s) 0 Name HSTM Definition Host Bus Master. Indicates whether the Host processor has control of the external bus (host bus master if set, =1) or does not have control of the bus (host not bus master if cleared, =0, reset value). Bus Synchronized. Indicates whether the processors bus arbitration logic is synchronized (if set, =1) or is not synchronized (if cleared, =0, reset value). Reserved (reset value =0) CRBM Current Bus Master. These bits indicate the ID of the processor that currently is the bus master in a multiprocessor system. Because CRBM is only valid for DSPs with ID inputs other than zero (e.g. a multiprocessor system), the processor keeps CRBM set to 001 when ID equals 000. The reset value of CRBM is undefined. Reserved (reset value =0) IDC ID Code. These bits indicate the state of the ID pins on the processor. The reset value of IDCID is undefined. Reserved (reset value =0) VIPD Vector Interrupt Pending. Indicates whether a vector interrupt is pending (if set, =1) or is not pending (if cleared, =0, reset value). A vector interrupt occurs when an address is written to the VIRPT register. The processor clears VIPD on return from the VIRPT interrupt service routine. Systems using vector interrupts should monitor VIPD to determine that the processor has serviced the VIRPT interrupt and is ready for another vector interrupt. 15-14 Reserved

BSYN

3-2 6-4

7 10-8 12-11 13

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Table A-21. System Status Register (SYSTAT) Bit Definitions

Bit(s) 18-16 Name CRAT Definition Core Clock-to-CLKIN ratio. These bits indicate the state of the CLK_CFG[1:0] pins (clock ratio) on the processor as follows 010 = 2:1 ratio, 011 = 3:1 ratio, 100 = 4:1 ratio. The reset value of CRAT is undefined. Reserved SSWPD Synchronous Slave Write FIFO Data Pending. Indicates if set (=1) that a synchronous slave IOP register write is pending. This bit indicates, if cleared (=0), that no slave write is pending. Slave Write FIFO Pending. Indicates whether a direct write (synchronous or asynchronous) to processors IOP register is pending (if set, =1) or is not pending (if cleared, =0, reset value). The processor clears SWPD when the direct write is complete. If an external device attempts a direct write during a DMA chaining operation or if higher priority DMA request occurs, the direct IOP register write may be delayed for several cycles. The maximum delay for a pending direct write is 12 cycles. 24-22 HPS Host Packing Status. These bits indicate the hosts packing status as follows: 000 = pack complete (reset value) and 6th stage of 8- to 48-bit packing, 4th stage of 8- to 32-bit packing etc. 001 = 1st stage pack/unpack 010 = 2nd stage multi-stage pack/unpack 011 = 3rd stage multi-stage pack/unpack 100 = 5th stage multi-stage pack/unpack 101 = 110 = 111 = reserved These bits are read-only. The processor clears these bits when DEN is cleared (changes from 1 to 0). 31-25 Reserved (reset value =0)

19 20

21

SWPD

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SYSTAT
0x03
HPS
Host Packing Status 000=packing complete [6th stage of 8-to -48, 4th stage of 8 -to-32, etc.] 001=1st stage pack/unpack 010=2nd stage pack/unpack 011=3rd stage pack/unpack 100=5th stage of 8- to -48 bit packing 101=110=111=reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0

CRAT
CCLK-to-CLKIN ratio Indicate state of CLKCFG[1:0] pins Undefined at RESET~

SSWPD
Synchronous Slave Write FIFO Data Pending 1=sync slave IOP register write pending 0=no sync slave IOP register write pending

SWPD
Slave Write FIFO Data Pending any data (sync or async) 1=slave write pending to IOP register 0=slave no write pending to IOP register

15 14 13 12 11 10 9 0 0 0 0 0

7 0

1 0

0 0

0 0

Vector Interrupt Pending 1=Vector interrupt pending ID Code Displays state of the ID[2:0] pins

VIPD

HSTM

Host Bus Master 1=host bus master controls ext bus 0=no host bus master

IDC

Bus Synchronized 1=bus arbitration logic synchronized 0=not synchronized

BSYN

CRBM
Current ADSP- 21161 Bus Master Status of ID of DSP who is Bus Master CRPM=001 when ID=000

Figure A-18. SYSTAT Register

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SDRDIV Register (SDRDIV)

This registers address is 0xb9. The reset value for this register is undefined. The SDRDIV register is a programmable refresh counter used to coordinate the supplied clock rate with the SDRAM devices required refresh rate. This register is described in Figure A-19.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SDRDIV 0xB9
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDRDIV=

fCCLK SDRAM refresh rate cycle

CL

RP

Figure A-19. SDRDIV Register

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Registers

SDRAM Control Register (SDCTL)

This registers addresses is 0xb8. The reset value for this register is undefined. At reset, all the SDCTL bits are cleared to zero. The SDCTL register is an IOP register for the SDRAM controller. This register is described in Table A-22 and Figure A-20. This register does not support bitwise operations. Table A-22. SDCTL Control Register Bits
Bit Number 1-0 Name SDCL Description SDRAM CAS Latency. Set the CAS delay as follows: 01= 1 latency, 10 = 2 latency, 11 = 3 latency, 00 = reserved. The CAS latency is the delay, in clock cycles, between when the SDRAM detects the read command and when it provides the data at its output pins. Disable SDCLK0 and Control Signals. This bit disables if set (=1) or enables if cleared (=0) the following signals: SDCLK0, RAS, CAS, SDWE, SDCKE. Disable SDCLK1. This bit disables if set (=1) or enables if cleared (=0), the SDCK1 signals. SDRAM TRAS Specification. Set the SDRAM tRAS specification in number of clock cycle (0-15 cycles). TRAS is the required delay between issuing an activate command and issuing a precharge command. SDRAM TRP Specification. Set the SDRAM tRAS specification in number of clock cycle (0-7 cycles). TRP is the required delay between issuing a precharge command and issuing an activate command.

DSDCTL

3 7-4

DSDCK1 SDTRAS

10-8

SDTRP

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I/O Processor Registers

Table A-22. SDCTL Control Register Bits (Contd)

Bit Number 11 Name SDPM Description SDRAM Power-Up Mode. This bit enables if set (=1) or disables if cleared (=0) the following commands as generated by the SDRAM controller: 0 = PRE/ 8 CBR /MRS, 1= PRE/ MRS/ 8 CBR. PRE - Precharge- closes an active bank. CBR - Automatic Refresh - the SDRAM drives its own refresh cycle with no external control input. MRS- Mode Register Set - initializes the SDRAM operation parameters during the power-up sequence. 13-12 14 15 SDPGS SDPSS SDSRF SDRAM Page Size. Set the SDRAM page size as follows: 00= 256 words, 01 = 512 words, 10 = 1k words, 11 = 2k words. SDRAM Power-Up Sequence. This bit enables if set (=1) or disables if cleared (=0) the SDRAM power up sequence start. SDRAM Self Refresh Mode. This bit enables if set (=1) or disables if cleared (=0) SDRAM self refresh mode. In this mode, the SDRAM drives its own refresh cycle with no external control input. At cycle end, both SDRAM banks are precharged (idle). This control bit always reads zero. 161 SDEM0 External Memory Bank 0. Indicates, if set (=1), that external memory bank 0 has SDRAM or, if cleared (=0), that external memory bank 0 does not have SDRAM. External Memory Bank 1. Indicates, if set (=1), that external memory bank 1 has SDRAM or, if cleared (=0), that external memory bank 1 does not have SDRAM. External Memory Bank 2. Indicates, if set (=1), that external memory bank 2 has SDRAM or, if cleared (=0), that external memory bank 2 does not have SDRAM. External Memory Bank 3. Indicates, if set (=1), that external memory bank 3 has SDRAM or, if cleared (=0), that external memory bank 3 does not have SDRAM.

171

SDEM1

181

SDEM2

191

SDEM3

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Table A-22. SDCTL Control Register Bits (Contd)

Bit Number 20 Name SDBN Description SDRAM Bank Number. Indicates the number of banks your SDRAM device contains. If set (=1), there are four bank in SDRAM. If cleared (=0), there are two banks in SDRAM. SDRAM Clock to Core Clock Ratio. Indicates the SDRAM clock to core clock ratio as follows: 1 = full core clock, 0 = half core clock. Reserved SDBUF External Register Buffer. Indicates, if set (=1), the existence of an external register buffer for address and control of SDRAM. If this bit is cleared (=0), there is no external register buffer. SDRAM TRCD Specification. Set the SDRAM tRCD specification in number of clock cycle (0-7 cycles). TRCD is the required delay between an ACT command and the start of the first read or write operation. Reserved

21

SDCKR

22 23

26-24

SDTRCD

31-27 1

The CS pin of a SDRAM chip should be connected to MSx pin of the ADSP-21161 processor for the corresponding memory bank in which you want to map the SDRAM device. All four memory banks can have SDRAM simultaneously.

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SDCTL
(0x00B8)
SDTRCD
SDRAM tRCD spec RAS to CAS delay [# of SDCLK cycles: 1 to 7 cycles] Pipelining option with external reg buffer [1=ext SDRAM ctl/addr buffer enable 0=no buffer option]

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDEM0
Ext mem Bank0 SDRAM enable

SDEM1
Ext mem Bank1 SDRAM enable

SDBUF

SDEM2
Ext mem Bank2 SDRAM enable

SDCKR
SDCLK-to-CCLK ratio 0=Half CCLK (core clock) freq. (1:2) 1=CCLK Core clock freq. (1:1)

SDEM3
Ext mem Bank 3 SDRAM enable 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

SDBN
SDRAM # of SDRAM device mem banks 0=2 banks, 1=4 banks 15 14 13 12 11 10 9 0 0 0 0 0 0 0

SDSRF
SDRAM self refresh command enable

SDCL
SDRAM CAS Latency spec 01=1 cycle, 10=2 cycles, 11=3 cycles Disable SDCLK0 &Control Signals 1=Disable SDCLK0, RAS~, CAS~ & SDCLKE 0=Activate SDCLK0, RAS~, CAS~ & SDCLKE SDCLK1 Disable 1=disable SDCLK1, 0=SDCLK active

SDPSS
SDRAM Power- up sequence

DSDCTL

SDPGS
SDRAM Page Size 00=256 words 01=512 words 10=1k words 11=2k words

DSDCK1

SDTRAS
SDRAMtRAS spec Active Command Delay [# of SDCLK cycles: 0 to 15 cycles]

SDPM
SDRAM Power- up mode 0=prechg , 8 CBR refs., mode reg. set 1=prechg, mode reg. set, 8 CBR refs.

SDTRP
SDRAMtRP spec PrechargeDelay [# of SDCLK cycles: 1 to 7 cycles]

Figure A-20. SDCTL Register

External Port DMA Buffer Registers (EPBx)

The EPBx registers addresses are: EPB00x04, EPB10x06, EPB20x14, and EPB30x16. The reset value for these registers is undefined. External port buffers are 8 levels deep and 64 bits wide. The buffers contain 40/48- or 32/64-bit words, depending on the external port buffers data type selected with the DTYPE bit in the ports DMACx register. If the buffer contains 32-, 40- or 48-bit words, the port aligns the data with the lower bits of the buffer and zero fills the upper 32, 24 or 16 bits. A-76 ADSP-21161 SHARC Processor Hardware Reference

Registers

Normally, a DMA process automatically accesses the buffer register for memory transfer. Programs can also access these buffers as registers. However, programs must use the PX register to access the full width of the buffer. A PX register move can access the entire 64 bits of an external port buffer using the full width PX.

Message Registers (MSGRx)

The MSGRx registers addresses are: MSGR00x08, MSGR10x09, MSGR20x0a, MSGR30x0b, MSGR40x0c, MSGR50x0d, MSGR60x0e, and MSGR70x0f. The reset value for these registers is undefined.

PC Shadow Register (PC_SHDW)

The PCSHDW registers address is 0x10. The reset value for this register matches the PC register. PC_SHDW contains a read-only mirror of the 24-bit address in the Program Counter (PC) register. External devices can poll this PC_SHDW for the contents of PC. Note that the value in PC_SHDW may lag behind the current PC by one or more core clock cycles. This register is shown in Figure A-21.
31 30 29 28 27 26 25 24 23 22 21 20 0 7 0 0 6 0 0 5 0 0 4 0 19 18 17 16 0 3 0 0 2 0 0 1 0 0 0 0

PC_SHDW
(0x10)

0 9 0

0 8 0

15 14 0 0

13 12 0 0

11 10 0 0

PC IOP Shadow of Program Counter PC[24:0]

Figure A-21. PC Shadow Register

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MODE2 Shadow Register (MODE2_SHDW)

This registers address is 0x11. Because MODE2_SHDW register bits 31-25 are the ADSP-21161 processor ID and silicon revision, the reset value varies with the system setting and silicon revision. External devices can poll this MODE2_SHDW for the processors processor ID and silicon revision. This register is described in Table A-23 and Figure A-22. Table A-23. Mode2 Shadow Register (MODE2_SHDW) Bit Definitions
Bit 24-0 27-25 29-28 31-30 PID4-3 PID2-0 Name Definition Reserved Processor Identification (Read only) PID2-0. Silicon Revision number. Silicon revision 1.0 and 1.1 are both 01. Silicon revision 0.3 is 00. Processor Identification (Read only) PID4-3.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MODE2_SHDW 0x11
PID4- 3
Processor Identification (Read Only)

PID 2-0
Processor Identification (Read Only)

Silicon Revision
(Read Only) Revision 0.3=00 Revision 1.0/1.1=01 Revision 1.2=10

15 14 13 12 11 10 9 0 0 0 0 0 0 0

8 0

7 0

6 0

5 0

4 0

1 0

0 0

0 0

Figure A-22. MODE2 Shadow Register

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Bus Time-Out Maximum Register (BMAX)

This registers address is 0x18 and it is shown in Figure A-23. The reset value for this register is 0x0000 0000. The lower 16 bits of this register hold the value for the maximum number of cycles -2 that the processor can retain bus mastership. The upper 16 bits of this register are reserved.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 0

BMAX (0x18)

15 14 13 12 0 0 0 0

11 10 0 0

BMAX = (maximum # of bus mastership cycles -2)

Figure A-23. BMAX Register For more information describing how BMAX and BCNT work, see Bus Mastership Timeout on page 7-101.

Bus (Time-Out) Counter Register (BCNT)

This registers address is 0x19 and it is shown in Figure A-24. The reset value for this register is 0x0000 0000. The lower 16 bits of this register hold the count of the number of cycles remaining for the processor to retain bus mastership. The upper 16 bits of this register are reserved. For more information describing how BMAX and BCNT work, see Bus Mastership Timeout on page 7-101.

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31 30

29 28 0 13 0 0 12 0

27 0

26 0

25 0 9 0

24 0 8 0

23 22 0 7 0 0 6 0

21 20 0 5 0 0 4 0

19 18 0 3 0 0 2 0

17 0 1 0

16 0 0 0

BCNT
(0x19)

15 14 0 0

11 10 0 0

BCNT=# CCLK cycles r e m a i n i n g for DSP to retain bus m astership (decrem ents every cycle)

Figure A-24. BCNT Register

External Port DMA Control Registers (DMACx)

These registers addresses are: DMAC100x1C, DMAC110x1D, DMAC120x1E, DMAC130x1F. The reset value for these registers is 0x0000 0000 unless you are booting from a host processor or PROM booting. Each external port DMA channel has its own control register. The registers, DMAC10, DMAC11, DMAC12, and DMAC13 correspond to DMA channels 10, 11, 12, and 13. Table A-24 and Figure A-25 provide bit definitions for the DMACx registers. Except for the FLSH bit, the control bits in the DMACx registers have a one cycle effect latency. The FLSH bit has a two cycle effect latency. Table A-24. External Port DMA Control Registers (DMACx) Bit Definitions
Bit(s) 0 Name DEN Definition External Port DMA Enable. This bit enables (if set, =1) or disables (if cleared, =0) DMA for the corresponding external port FIFO buffer (EPBx). External Port DMA Chaining Enable. This bit enables (if set, =1) or disables (if cleared, =0) DMA chaining for the corresponding external port FIFO buffer (EPBx).

CHEN

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Table A-24. External Port DMA Control Registers (DMACx) Bit Definitions (Contd)
Bit(s) 2 Name TRAN Definition External Port Transmit/Receive Select. This bit selects the transfer direction (transmit if set, =1) (receive if cleared, =0) for the corresponding external port FIFO buffer (EPBx). Reserved DTYPE External Port Data Type Select. This bit selects the transfer data type (40/48=bit, 3-column if set, =1) (32/64-bit, 4-column if cleared, =0) for the corresponding external port FIFO buffer (EPBx). Programs must not change a buffers DTYPE setting while the buffer is enabled. The buffers DTYPE setting overrides the internal memory blocks setting IMDWx for Normal word width. Whether buffer is set for 48- or 64- bit words, programs must index (IIx) the corresponding DMA channel with a Normal word address; always an even address 64-bit. 8-6 PMODE External Port Packing Mode. These bits select the packing mode for the corresponding external port FIFO buffer (EPBx) as follows: 001=16 external to 32/64 internal packing, 010=16 external to 48 internal packing, 011=32 external to 48 internal packing, 101=8 external to 48 internal packing, 100=32 external to 32/64 internal packing (No pack), 110=8 external to 32/64 internal packing, 000 =111=reserved. Programs must not change a buffers PMODE setting while the buffer is enabled. For host processor accesses through the external port, the buffers PMODE setting must match the Host Bus Width (HBW) setting in the SYSCON registers. 9 MSWF Most Significant 16-bit Word First During Packing. When the buffers PMODE is 001 or 010, this bit selects the packing order of 16-bit words (most significant first set, =1) (least significant first cleared, =0) for the corresponding external port FIFO buffer (EPBx). Programs must not change a buffers MSWF setting while the buffer is enabled.

4-3 5

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Table A-24. External Port DMA Control Registers (DMACx) Bit Definitions (Contd)
Bit(s) 10 Name MASTER Definition Master Mode Enable. This bit enables (if set, =1) or disables (if cleared, =0) master mode for the corresponding external port FIFO buffer (EPBx). Programs must not change a buffers MASTER setting while the buffer is enabled. The MASTER, HSHAKE, and EXTERN bits work together to select the external port buffers mode. 11 HSHAKE Handshake Mode Enable. This bit enables (if set, =1) or disables (if cleared, =0) handshake mode for the corresponding external port FIFO buffer (EPBx). Programs must not change a buffers HSHAKE setting while the buffer is enabled. The MASTER, HSHAKE, and EXTERN bits work together to select the external port buffers mode. 12 INTIO Single-Word Interrupt Enable. This bit enables (if set, =1) or disables (if cleared, =0) single-word, non-DMA, interrupt-driven transfers for the corresponding external port FIFO buffer (EPBx). To avoid spurious interrupts, programs must not change a buffers INTIO setting while the buffer is enabled. External Handshake Mode Enable. This bit enables (if set, =1) or disables (if cleared, =0) external handshake mode for the corresponding external port FIFO buffer (EPBx). Programs must not change a buffers EXTERN setting while the buffer is enabled. The MASTER, HSHAKE, and EXTERN bits work together to select the external port buffers mode.

13

EXTERN

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Table A-24. External Port DMA Control Registers (DMACx) Bit Definitions (Contd)
Bit(s) 14 Name FLSH Definition Flush DMA Buffers & Status. This bit flushes (when set, =1) settings for the corresponding external port FIFO buffer (EPBx). Flushing these settings does the following: Clears (=0) the FS and PS status bits Clears (=0) the FIFO buffer and DMA request counter Clears (=0) any partially packed words

When a program sets (=1) FLSH, the processor flushes the settings and clears (=0) FLSH. There is a two-cycle effect latency in completing the flush operation. Programs must not set a buffers FLSH during the same write that enables the buffer. Also, programs must not set a buffers FLSH bit while the DMA channel is active. Programs should determine the channels active status by reading the corresponding bit in the DMASTAT register. 15 PRIO External Port Bus Priority. This bit selects the external bus access priority level (high if set, =1) (low if cleared, =0) for the corresponding external port FIFO buffer (EPBx). Programs must not change a buffers PRIO setting while the buffer is enabled. When PRIO is set, the processor asserts the PA pin as part of external bus arbitration for DMA accesses using this buffer. The PRIO bit does not effect internal DMA priority arbitration.

ADSP-21161 SHARC Processor Hardware Reference

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I/O Processor Registers

Table A-24. External Port DMA Control Registers (DMACx) Bit Definitions (Contd)
Bit(s) 17-16 Name FS Definition External Port FIFO Buffer Status. These bits indicate the corresponding FIFO buffers status as 00=buffer empty, 01=buffer-not-full, 10=buffer-not-empty, 11=buffer full. For transmit (TRAN=1), buffer-not-full means that the buffer has space for one Normal word, and buffer-not-empty means that the buffer has space for two-or-more Normal words. For receive (TRAN=0), buffer-not-full means that the buffer contains one Normal word, and buffer-not-empty means that the buffer contains two-or-more Normal words. Any type of full status (01, 10, or 11) in receive mode indicates that new (unread) data is in the buffer. These bits are read-only. The processor clears these bits when DEN is cleared (changes from 1 to 0). 18 INT32 Internal Memory 32-bit Transfers Select. This bit selects the external bus access width (32-bit transfers only if set, =1) (64-bit transfers when possible if cleared, =0) for the corresponding external port FIFO buffer (EPBx). Programs must not change a buffers INT32 setting while the buffer is enabled. Note that the buffers DTYPE and internal memory blocks IMDWx setting (either can select 40/48-bit transfers) overrides a 32-bit transfers only (INT32 =1) setting. 20-19 MAXBL Maximum Burst Length Select. These bits select the maximum burst transfer length for the corresponding external port FIFO buffer (EPBx) as follows: 00=burst disabled, 01=burst limit of 4, 10=11=reserved. Processors may perform burst accesses to external memory banks only when the bank is configured for synchronous access (EBxAM field in WAIT register). For burst writes, the memory banks EBxAM must be configured for the one-wait state write, synchronous access mode.

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Table A-24. External Port DMA Control Registers (DMACx) Bit Definitions (Contd)
Bit(s) 23-21 Name PS Definition External Port Packing Status. These bits indicate the corresponding FIFO buffers packing status as 000=pack complete, 001=1st stage pack/unpack, 010=2nd stage multi-stage pack/unpack, 011= 3rd stage, 100=5th stage of 8 to 48-bit packing, 101=110=111=reserved. These bits are read-only. The processor clears these bits when DEN is cleared (changes from 1 to 0). 31-24 Reserved

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DMAC10 DMAC11 DMAC12 DMAC13

0x1c 0x1d 0x1e 0x1f

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PS
Ext Port EPBx FIFO Buffer Packing Status (read-only) 000=packing complete 001=1st stage pack/unpack 010=2 nd stage pack/unpack 011=3rd stage 100=5 th stage of 8 to 48 -bit packing 101=110=111=reserved

FS
Ext. Port FIFO Buffer Status (read-only) 00=buffer empty 01=buffer-not- full 10=buffer-not - empty 11=buffer full

INT32
Internal Memory 32 -bit Transfers Select 1=32-bit transfers/EPBx access width 0=64-bit transfers/EPBx access width

MAXBL
Maximum Burst Length Select 00=burst disabled 01=burst limit of 4 10=11=reserved 15 14 13 12 11 10 9 0 0 0 0 0 0 0

8 0

7 0

6 0

5 0

4 0

1 0

0 0

0 0

External Port Bus Priority Access 1=DSP asserts PA~ for external bus access 0=PA~ not asserted Flush EPBx FIFO Buffers & Status 1=flush EPBx External Handshake Mode Enable 1=enable, external devices to external memory 0=disable

PRIO

DEN
Ext. Port DMA Enable 1=enable, 0=disable

FLSH

CHEN
Ext. Port DMA Chaining Enable 1=enable, 0=disable

EXTERN

TRAN
Ext. Port EPBx Transmit/Rcv. Select 1=transmit data from intern memory 0=receive data from ext memory

INTIO
Single Word Interrupts for EPBx FIFO Buffers 1=enable single - wd non -DMA interrupt-driven xfers 0=disabled, FIFO fully enabled

DTYPE
EPBx FIFO Buffer Data Type Select 1=40/48 - bit, 3-column data 0=32/64 - bit, 4- column data

HSHAKE
EPBx DMA Handshake Mode Enable 1=enable, 0=disable

PMODE
Ext Port EPBx FIFO Packing Mode 000, 111= reserved 001=16 ext- to- 32/64 int 010=16 ext-to-48 int 011=32 ext- to -48 int 100=no pack (32 ext -to - 32/64 int) 101=8 ext-to -48 int 110=8 ext - to- 32/64int

MASTER
EPBx DMA Master Mode Enable 1=enable, 0=disable

MSWF
Most Significant Word First During Packing 1=enable, MSW first 0=disable, LSW first

Figure A-25. DMAC Register

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Registers

Internal Memory DMA Index Registers (IIx)

The IIx registers addresses are: II0A0x60, II0B0x80, II1A0x68, II1B0x88, II2A0x70, II2B0x90, II3A0x78, II3B0x98, IILB00x30, IISRX0x30, IILB10x38, IISTX0x38, IIEP00x40, IIEP10x48, IIEP20x50, IIEP30x58. The reset value for these registers is undefined. The IIx register is an 18-bit wide register that holds an address and acts as a pointer to memory for a DMA transfer. For more information, see I/O Processor on page 6-1.

Internal Memory DMA Modifier Registers (IMx)

The IMx registers addresses are: IM0A0x61, IM0B0x81, IM1A0x69, IM1B0x89, IM2A0x71, IM2B0x91,IM3A0x79, IM3B0x99, IMLB00x31, IMSRX0x31, IMLB10x39, IMSTX0x39, IMEP00x41, IMEP10x49, IMEP20x51, IMEP30x59. The reset value for these registers is undefined. The IMx register is a 16-bit wide register that provides the increment or step size by which an IIx register is post-modified during a DMA operation. For more information, see I/O Processor on page 6-1.

Internal Memory DMA Count Registers (Cx)

The Cx registers addresses are: C0A0x62, C0B0x82, C1A0x6a, C1B0x8a, C2A0x72, C2B0x92, C3A0x7a, C3B0x9a, CLB00x32, CSRX0x32, CLB10x3a, CSTX0x3a, CEP00x42, CEP10x4a, CEP20x52, CEP30x5a. The reset value for these registers is undefined. The Cx registers are 16 bits wide and hold the word count for a DMA transfer. For more information, see I/O Processor on page 6-1.

ADSP-21161 SHARC Processor Hardware Reference

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I/O Processor Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

IIx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IMx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Cx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CPx
Program -Controlled Interrupt Bit If this bit is set, the I/O processor will generate a DMA interrupt on completion of a chained DMA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCI Bit

GPx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EIEPx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EMEPx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ECEPx
(Reserved bi ts must always be set to zero when programming DMA parameter registers)

Figure A-26. IOP Parameter Registers

Chain Pointer For Next DMA TCB Registers (CPx)

These registers addresses are CP0A0x63, CP0B0x83, CP1A0x6B, CP1B0x8B, CP2A0x73, CP2B0x93, CP3A0x7B, CP3B0x9B, CPLB00x33, CPLB10x3B, CPEP00x43, CPEP10x4B CPEP20x53, CPEP30x5B. The reset value for these registers is undefined. The CPx registers are 19 bits wide and hold the address for the next transfer control block in a chained DMA operation. For more information, see I/O Processor on page 6-1. A-88 ADSP-21161 SHARC Processor Hardware Reference

Registers

General Purpose DMA Registers (GPx)

The GPx registers addresses are GP0A0x64, GP0B0x84, GP1A0x6C, GP1B0x8C, GP2A0x74, GP2B0x94, GP3A0x7C, GP3B0x9C, GPLB0 0x34, GPSRX0x34, GPLB10x3C, GPSTX0x3C, GPEP00x44, GPEP10x4C, GPEP20x54, GPEP30x5C. The GPx registers are 17 bits wide. The reset value for these registers is undefined.

External Memory DMA Index Registers (EIEPx)

These registers addresses are: EIEP00x45, EIEP10x4D, EIEP20x55, EIEP30x5D. The reset value for these registers is undefined. The EIEPx registers hold an external memory address and acts as a pointer to memory for an external port DMA transfer. The 32-bit wide EIEPx registers have more bit space than required to generate external memory addresses. When programming these registers, write zeros to the upper address bits ADDR28 through ADDR31. The lower 28 bits contain a valid address field while the upper MSBs are never generated off-chip in the processors 254 Mword address space. For more information, see I/O Processor on page 6-1. Only External Port DMA channels have EIEPx registers, because these channels exclusively address ADSP-21161 processor external memory.

External Memory DMA Modifier Registers (EMEPx)

The EMEPx registers addresses are: EMEP00x46, EMEP10x4E, EMEP20x56, EMEP30x5E. The reset value for these registers is undefined. The EMEPx registers provide the increment or step size by which an EIEPx register is post-modified during an external port DMA operation.

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I/O Processor Registers

The value of EMEPx should be such that after being modified with EMEPx, the value of EIEPx does not fall outside the valid memory range. For more information, see I/O Processor on page 6-1. Only External Port DMA channels have EMEPx registers, because these channels exclusively address processor external memory.

External Memory DMA Count Registers (ECEPx)

The ECEPx registers addresses are: ECEP00x47, ECEP10x4F, ECEP20x57, ECEP30x5F. The reset value for these registers is undefined. The ECEPx registers hold the word count for an external port DMA transfer. When doing multiple transfers, the word count indicated by ECEPx should be such that the value of EIEPx doesnt go beyond the valid memory range. For more information, see I/O Processor on page 6-1. Only External Port DMA channels have ECx registers, because these channels exclusively address processor external memory.

DMA Channel Status Register (DMASTAT)

The DMASTAT registers address is 0x37. The reset value for this register is undefined. The lower bits in the DMASTAT register indicate DMA channel activity. Bits 0 through 13 correspond to channels 0 through 13 and indicate DMA status for each channel as active (if set, =1) or inactive (if cleared, =0). The upper bits in the DMASTAT register indicate DMA chaining status. Bits 16 through 29 correspond to channels 0 through 13 and indicate DMA chaining status for each channel as enabled/pending (if set, =1) or disabled (if cleared, =0). This register is shown in Figure A-27.

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ADSP-21161 SHARC Processor Hardware Reference

Registers

Note that there is a single cycle of read latency between a change in a DMA channels status and the update of its DMASTAT bit(s).
DMASTAT
0x37
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0

DMA13CHST
Channel 13(EPB3) Chaining Status

DMA0CHST
Channel 0 (RX0A/TX0A) Chaining Status

DMA12CHST
Channel 12 (EPB2) Chaining Status Channel 11 (EPB1) Chaining Status Channel 10 (EPB0) Chaining Status

DMA2CHST
Channel 2 (RX1A/TX1A) Chaining Status

DMA11CHST DMA10CHST DMA7CHST

DMA4CHST DMA6CHST

Channel 4 (RX2A/TX2A) Chaining Status Channel 6 (RX3A/TX3A) Chaining Status

Channel 7 (RX3B/TX3B) Chaining Status

DMA8CHST
Channel 8 (LBUF0) Chaining Status

DMA5CHST
Channel 5 (RX2B/TX2B) Chaining Status

DMA9CHST DMA1CHST

Channel 9 (LBUF1) Chaining Status Channel 1 (RX0B/TX0B) Chaining Status

DMA3CHST
Channel 3 (RX1B/TX1B) Chaining Status 15 14 13 12 11 10
0 0

DMA13ST
Channel 13 (EPB3) Status

DMA0ST
Channel 0 (RX0A/TX0A) Status Channel 2 (RX1A/TX1A) Status

DMA12ST
Channel 12 (EPB2) Status

DMA2ST DMA4ST

DMA11ST
Channel 11 (EPB1) Status

Channel 4 (RX2A/TX2A) Status

DMA10ST
Channel 10 (EPB0) Status

DMA6ST
Channel 6 (RX3A/TX3A) Status

DMA7ST
Channel 7 (RX3B/TX3B) Status

DMA8ST
Channel 8 (LBUF0/SPIRX) Status

DMA5ST
Channel 5 (RX2B/TX2B) Status

DMA9ST
Channel 9 (LBUF1/SPITX) Status

DMA3ST
Channel 3 (RX1B/TX1B) Status

DMA1ST
Channel 1 (RX0B/TX0B) Status

* Channel Active Status: 1=Active [ transferring data or waiting to transfer current block, and not transferring TCB ] 0= Inactive [DMA transter complete, or in TCB chain loading] ** Channel Chaining Status: 1=Chaining is Enabled and currently transferring TCB, or is Pending to transfer TCB, 0 = Chaining Disabled Status does not change on the master ADSP-21161 processor during external port DMA until the external portion is completed (for example, the EPBx buffers are emptied). If in chain insertion mode (DEN=0, CHEN=1), then channel chaining status will never go to a 1. Therefore, test channel status to see if it is ready so that your program can rewrite the chain pointer (CPx) register.

Figure A-27. DMASTAT Register

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I/O Processor Registers

Link Port Buffer Registers (LBUFx)

These registers addresses are: LBUF00xc0, LBUF10xc2. The reset value for these registers is undefined. These registers are shown in Figure A-28. Link port buffers are two levels deep and 48 bits wide. The buffers contain 32- or 48-bit words, depending on the link ports extended word size selected with the LxEXT bit in the ports LCTL register. If the buffer contains 32-bit words, the port aligns the data with the lower 32 bits of the buffer and zero fills the upper 16 bits. Normally, a DMA process automatically accesses the buffer register for memory transfer. Programs can also access these buffers as registers. However, programs must use the PX register to access the full width of the buffer. A PX register move can access the entire 48 bits of a link buffer using the lower 48 bits of PX.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

LBUF0 (0xc0)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

LBUF1 (0xc2)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Figure A-28. LBUFx Register

Link Port Buffer Control Register (LCTL)

This registers address is 0xCC. The reset value for this register is 0x0020 0000. Table A-25 and Figure A-29 on page A-97 describe the bit fields within this register. To avoid spurious interrupts, programs should

A-92

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Registers

mask Link Service Requests (LSRQ) before modifying the LCTL register. For more information, see Link Port Service Request & Mask Register (LSRQ) on page A-98. Table A-25. Link Port Buffer Control Registers (LCTL) Bit Definitions
Bit(s) 0 Name L0EN Definition Link Buffer Enable. This bit enables (if set, =1) or disables (if cleared, =0) link buffer 0 (LBUF0). When the processor disables the buffer (L0EN transitions from high to low), the processor clears the corresponding L0STAT and L0RERR bits. Link Buffer DMA Enable. This bit enables (if set, =1) or disables (if cleared, =0) DMA transfers link buffer 0 (LBUF0). Link Buffer DMA Chaining Enable. This bit enables (if set, =1) or disables (if cleared, =0) DMA chaining link buffer 0 (LBUF0) Link Buffer Transfer Direction. This bit selects the transfer direction (transmit if set, =1) (receive if cleared, =0) for link buffer 0 (LBUF0). Link Buffer Extended Word Size. This bit selects the transfer extended word size (48-bit if set, =1) (32-bit if cleared, =0) for link buffer 0(LBUF0). Programs must not change a buffers L0EXT setting while the buffer is enabled. The buffers L0EXT setting overrides the internal memory blocks setting IMDWx for Normal word width. Whether buffer is set for 48- or 32- bit words, programs must index (IIx) the corresponding DMA channel with a Normal word address. 6-5 L0CLKD Link Port Clock Divisor. These bits select the transfer clock divisor for link buffer 0 (LBUF0). The transfer clock equals the processor core clock divided by L0CLKD, where L0CLKD[6-5] is: 01=1, 10=2, 11=3, or 00=4. Reserved

1 2 3

L0DEN L0CHEN L0TRAN

L0EXT

ADSP-21161 SHARC Processor Hardware Reference

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I/O Processor Registers

Table A-25. Link Port Buffer Control Registers (LCTL) Bit Definitions (Contd)
Bit(s) 8 Name L0PDRDE Definition Link Port Pulldown Resistor Disable. This bit disables (if set, =1) or enables (if cleared, =0) the internal pulldown resistors on the L0CLK, L0ACK, and L0DAT7-0 pins of the corresponding unassigned or disabled link port for silicon revisions 0.3, 1.0 and 1.1 and L0CLK and L0ACK for silicon revisions 1.2 and higher. this bit applies to the port which is not necessarily the port assigned to link buffer 0 (LBUF0). For revisions 0.3, 1.0 and 1.1 systems should not leave link port pins (L0CLK, L0ACK, and L0DAT7-0) unconnected without clearing the corresponding L0PDRDE bit or applying an external pulldown. For silicon revisions 1.2 or higher, this applies to L0CLK and L0ACK pins only. In systems where several processors share a link port, only one processor should have this bit cleared. For complete pin descriptions, see Table 13-1 on page 13-4. 9 L0DPWID Link Port Data Path Width. This bit selects the link port data path width (8-bit if set, =1) (4-bit if cleared, =0) for link buffer 0 (LBUF0). Systems using a 4-bit width should connect the lower link port data pins (L0DAT3-0) for data transfers and leave the upper pins (L0DAT7-4) unconnected. In the 4-bit mode, the processor applies pulldowns to the upper pins. 10 L1EN Link Buffer Enable. This bit enables (if set, =1) or disables (if cleared, =0) link buffer 1 (LBUF1). When the processor disables the buffer (L1EN transitions from high to low), the processor clears the corresponding L1STAT and L1RERR bits. Link Buffer DMA Enable. This bit enables (if set, =1) or disables (if cleared, =0) DMA transfers link buffer 1(LBUF1). Link Buffer DMA Chaining Enable. This bit enables (if set, =1) or disables (if cleared, =0) DMA chaining link buffer 1(LBUF1). Link Buffer Transfer Direction. This bit selects the transfer direction (transmit if set, =1) (receive if cleared, =0) link buffer 1(LBUF1).

11 12 13

L1DEN L1CHEN L1TRAN

A-94

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Table A-25. Link Port Buffer Control Registers (LCTL) Bit Definitions (Contd)
Bit(s) 14 Name L1EXT Definition Link Buffer Extended Word Size. This bit selects the transfer extended word size (48-bit if set, =1) (32-bit if cleared, =0) for link buffer 1(LBUF1). Programs must not change a buffers L1EXT setting while the buffer is enabled. The buffers L1EXT setting overrides the internal memory blocks setting IMDWx for Normal word width. Whether buffer is set for 48- or 32- bit words, programs must index (IIx) the corresponding DMA channel with a Normal word address. 16-15 L1CLKD Link Port Clock Divisor. These bits select the transfer clock divisor for link buffer 1(LBUF1). The transfer clock equals the processor core clock divided by L1CLKD, where L1CLKD[16-15] is: 01=1, 10=2, 11=3, or 00=4. Reserved L1PDRDE Link Port Pulldown Resistor Disable. This bit disables (if set, =1) or enables (if cleared, =0) the internal pulldown resistors on the L1CLK, L1ACK, and L1DAT7-0 pins of the corresponding unassigned or disabled link port for silicon revisions 0.3, 1.0 and 1.1 and L1CLK and L1ACK for silicon revisions 1.2 and higher. This bit applies to the port, which is not necessarily the port assigned to link buffer 1 (LBUF1). For revisions 0.3, 1.0 and 1.1 systems should not leave link port pins (L1CLK, L1ACK, and L1DAT7-0) unconnected without clearing the corresponding L1PDRDE bit or applying an external pulldown. For silicon revisions 1.2 or higher, this applies to L1CLK and L1ACK pins only. In systems where several DSPs share a link port, only one processor should have this bit cleared. For complete pin descriptions, see Table 13-1 on page 13-4.

17 18

ADSP-21161 SHARC Processor Hardware Reference

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I/O Processor Registers

Table A-25. Link Port Buffer Control Registers (LCTL) Bit Definitions (Contd)
Bit(s) 19 Name L1DPWID Definition Link Port Data Path Width. This bit selects the link port data path width (8-bit if set, =1) (4-bit if cleared, =0) for link buffer 1 (LBUF1). Systems using a 4-bit width should connect the lower link port data pins (L1DAT3-0) for data transfers and leave the upper pins (L1DAT7-4) unconnected. In the 4-bit mode, the processor applies pulldowns to the upper pins. 20 21 23-22 25-24 26 LAB0 LAB1 L0STAT L1STAT LRERR0 Link Port Assignments for LBUF0. This bit assigns link buffer 0 to link port 1 if set (=1) or link port 0 if cleared (=0). Link Port Assignments for LBUF1. This bit assigns link buffer 1 to link port 1 if set (=1) or link port 0 if cleared (=0). Link Buffer 0 Status. These bits identify the status of link buffer 0 as follows: 11=full, 00=empty, 10=one word. Link Buffer 1 Status. These bits identify the status of link buffer 1 as follows: 11=full, 00=empty, 10=one word. Receive Packing Error Status for Link Buffer 0. Indicates if the packed bits in link buffer 0 were receive completely (=0), without error, or incompletely (=1). Receive Packing Error Status for Link Buffer 1. Indicates if the packed bits in link buffer 1 were received completely (=0), without error, or incompletely (=1). Reserved

27

LRERR1

31-28

A-96

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LCTL
0xCC
LRERR1

31 30 29 28 27 26 25 24 23 22 21 20 0 0 0 0 0 0 0 0 0 0 1 0

19 18 17 16 0 0 0 0

L1CLKD
CCLK Divide Ratio 1 - LBUF1 00=divide by 4, 01=divide by 1 10=divide by 2, 11=divide by 3

Rcv. Pack Error Status for Link Buffer 1 1=incomplete, 0=complete

LRERR0
Rcv. Pack Error Status for Link Buffer 0 1=incomplete, 0=complete

L1PDRDE
Link Port 1 Pulldown Resister Disable

L1STAT[1:0]
Link Buffer 1 Status (Read- Only) 11=Full, 00=Empty, 10=one w ord

L1DPW ID
Link Buffer 1 Data Path Width 1=8-bits, 0=4-bits

L0STAT[1:0]
Link Buffer 0 Status (Read-Only) 11=Full, 00=Empty, 10=one w ord

LAB0
Link Port Assignment for LBUF0 0=Link Port 0, 1=Link Port 1

LAB1
Link Port Assignment for LBUF1 0=Link Port 0, 1=Link Port 1

15 14 0 L1CLKD
CCLK Divide Ratio 0 - LBUF1

13 0

12 0

11 10 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

L0EN
Link Buffer 0 Enable 1=enable, 0=disable

L1EXT
Link Buffer 1 Extended Word Size 1=48-bit transfers, 0=32-bit transfers

L0DEN
Link Buffer 0 DMA Enable 1=enable DMA 0=disable DMA

L1TRAN
Link Buffer 1 Data Direction 1=Transmit, 0=Receive

L0CHEN
Link Buffer 0 DMA Chaining Enable 1=enable chaining, 0=disable chaining

L1CHEN
Link Buffer 1 DMA Chaining Enable 1=enable chaining, 0=disable chaining

L0TRAN
Link Buffer 0 Data Direction 1=Transmit, 0=Receive

L1DEN
Link Buffer 1 DMA Enable 1=enable DMA, 0=disable DMA

L0EXT
Link Buffer 0 Extended Word Size 1=48 -bit transfers, 0=32 -bit transfers

L1EN
Link Buffer 1 Enable 1=enable DMA, 0=disable DMA

L0CLKD[1:0]
CCLK Divide Ratio - LBUF0 00=divide by 4, 01=divide by 1, 10=divide by 2, 11=divide by 3

L0DPW ID
Link Buffer 0 Data Path W idth 1=8-bits, 0=4-bits

L0PDRDE
Link Port 0 Pulldow n Resister Disable

Figure A-29. LCTL Register

ADSP-21161 SHARC Processor Hardware Reference

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I/O Processor Registers

Link Port Service Request & Mask Register (LSRQ)

The LSRQ registers address is 0xD0. This register is described in Table A-26 and Figure A-30. The reset value for this register is 0x0000 0000. The LSRQ register contains transmit and receive mask and status bits for each link port. The mask bits in LSRQ mask (disable if set, =1) or unmask (enable if cleared, =0) the status bits in LSRQ register. The status bits indicate whether a disabled link port (DEN=0) has a pending service request to receive or transmit data. When an LSRQ receive request status bit is set (LxRRQ=1), another ADSP-21161 processor has requested to send data by setting the link ports clock (LxCLK=1). When an LSRQ transmit request status bit is set (LxTRQ=1), another ADSP-21161 processor has requested more data by setting the link ports acknowledge (LxACK=1). Table A-26. Link Port Service Request Register (LSRQ) Bit Definitions
Bit(s) 3-0 4 5 6 7 19-8 20 L0TRQ L0TM L0RM L1TM L1RM Name Definition Reserved Link Port 0 Transmit Mask. This bit masks (if set, =1) or unmasks (if cleared, =0) the L0TRQ status bit. Link Port 0 receive mask. This bit masks (if set, =1) or unmasks (if cleared, =0) the L0RRQ status bit. Link Port 1 Transmit Mask. This bit masks (if set, =1) or unmasks (if cleared, =0) the L1TRQ status bit. Link Port 1 Receive Mask. This bit masks (if set, =1) or unmasks (if cleared, =0) the L1RRQ status bit. Reserved Link Port 0 Transmit Request Status (Read-Only). If set (=1), indicates that link port 0 is disabled, but L0ACK is set (indicating an external transmit request).

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Table A-26. Link Port Service Request Register (LSRQ) Bit Definitions (Contd)
Bit(s) 21 Name L0RRQ Definition Link Port 0 Receive Request Status (Read-Only). If set (=1), indicates that link port 0 is disabled, but L0CLK is set (indicating an external receive request). Link Port 1 Transmit Request Status (Read-Only). If set (=1), indicates that link port 1 is disabled, but L1ACK is set (indicating an external transmit request). Link Port 1 Receive Request Status (Read-Only). If set (=1), indicates that link port 1 is disabled, but L1CLK is set (indicating an external receive request). Reserved

22

L1TRQ

23

L1RRQ

31-24

LSRQ 0xD0
L1RRQ

31 30 29 28 27 0 0 0 0 0

26 25 24 23 22 21 20 19 18 17 0 0 0 0 0 0 0 0 0 0

16 0

L0TRQ
Link Port 0 Transmit Request

Link Port 1 Receive Request

L1TRQ
Link Port 1 Transmit Request

L0RRQ
Link Port 0 Receive Request

15 14 13 12 0 L1RM
Link Port 1 Receive Mask

11 10 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0 L0TM
Link Port 0 Transmit Mask

L1TM
Link Port 1 Transmit Mask

L0RM
Link Port 0 Receive Mask

Figure A-30. LSRQ Register

ADSP-21161 SHARC Processor Hardware Reference

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Serial Port Registers

This section provides bit descriptions for all ADSP-21161 SPORT registers. SPORT Serial Control Registers (SPCTLx) These registers addresses are: SPCTL00x1C0, SPCTL10x1E0, SPCTL20x1D0, SPCTL30x1F0. The reset value for these registers is 0x0000 0000. The SPCTLx registers are transmit and receive control registers for the corresponding serial port (SPORT 0, 1, 2 and 3). Table A-27 provides bit descriptions for the SPORT registers. Some these bits are reserved or have different names when the SPORT is in multichannel or I2S mode. The table notes these difference. Figure A-31 on page A-105 provides bit definitions for the SPCTLx register in serial mode. Figure A-32 on page A-106 provides bit definitions for the SPCTLx register in I2S mode. Figure A-33 on page A-107 provides bit definitions for SPORTS 0 and 1 (receive) in multichannel mode. Figure A-34 on page A-108 provides bit definitions for SPORTS 2 and 3 (transmit) in multichannel mode. When changing SPORT operating modes, programs should clear a serial ports control register before writing new settings to the control register.

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Table A-27. Serial Port Control Registers (SPCTLx) Bit Definitions

Bit(s) 0 Name SPEN_A Definition Serial Port Enable A. This bit enables (if set, =1) or disables (if cleared, =0) the corresponding serial port A channel. This bit is reserved when the SPORT is in multichannel mode. 2-1 DTYPE Data Type Select. These bits select the data type formatting for normal and multi-channel transmissions as follows: Normal 00 01 10 11 3 SENDN Multi x0 x1 0x 1x Data Type Formatting Right-justify, zero-fill unused MSBs Right-justify, sign-extend unused MSBs Compand using -law Compand using A-law

Serial Word Endian Select. This bit selects little endian words (LSB first, if set, =1) or big endian words (MSB first, if cleared, =0). Serial Word Length Select. These bits select the word length in bits. Word sizes can be from 3-bit (SLEN=2) to 32-bit (SLEN=31). 16-bit to 32-Bit Word Packing Enable. This bit enables (if set, =1) or disables (if cleared, =0) 16- to 32-bit word packing. Internal Transmit Clock Select. This bit selects the internal transmit clock (if set, =1) or external transmit clock (if cleared, =0). This bit applies to processor serial and multichannel modes for SPCTL0 and SPCTL1 registers. In I2S mode, this bit selects the word source and internal transmit clock (if set, =1) or external transmit clock (if cleared, =0) Sport Operation Mode. This bit selects the I2S mode if set (=1) or processor Serial mode/Multichannel mode if cleared (=0). Clock Rising Edge Select. This bit selects whether the serial port uses the rising edge (if set, =1) or falling edge (if cleared, =0) of the clock signal for sampling data and the frame sync. This bit is reserved when the SPORT is in I2S mode.

8-4

SLEN

9 10

PACK ICLK

MSTR (I2S mode only) 11 12 OPMODE CKRE

ADSP-21161 SHARC Processor Hardware Reference

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I/O Processor Registers

Table A-27. Serial Port Control Registers (SPCTLx) Bit Definitions (Contd)
Bit(s) 13 Name FSR Definition Frame Sync Required Select. This bit selects whether the serial port requires (if set, =1) or does not require (if cleared, =0) a transfer frame sync. This bit is reserved when the SPORT is in I2S mode and multichannel mode. 14 IFS (IRFS) Internally Frame Sync Select. This bit selects whether the serial port uses an internal generated FS (if set, =1) or uses an external FS (if cleared, =0). This bit is reserved when the SPORT is in I2S mode and multichannel transmit mode. 15 DITFS Data Independent Transmit Frame Sync Select. This bit selects whether the serial port uses a data-independent transmit FS (sync at selected interval, if set, =1) or uses a data-dependent TFS (sync when data in TX, if cleared, =0) when DDIR=1. This bit is reserved when the SPORT is in multichannel mode. 16 17 LFS (LRFS, LTDV) LAFS Low Active Frame Sync Select. This bit selects an active low FS (if set, =1) or active high FS (if cleared, =0). Late Transmit Frame Sync Select. This bit selects a late FS (FS during first bit, if set, =1) or an early FS (FS before first bit, if cleared, =0). This bit is reserved when the SPORT is in I2S mode and multichannel mode. 18 19 SDEN_A SCHEN_A Serial Port DMA Enable A. This bit enables (if set, =1) or disables (if cleared, =0) the serial ports A channel DMA. Serial Port DMA Chaining Enable A. This bit enables (if set, =1) or disables (if cleared, =0) serial ports channel A DMA chaining.

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Table A-27. Serial Port Control Registers (SPCTLx) Bit Definitions (Contd)
Bit(s) 20 Name SDEN_B Definition Serial Port DMA Enable B. This bit enables (if set, =1) or disables (if cleared, =0) the serial ports channel B DMA. This bit is reserved when the SPORT is in multichannel mode. 21 SCHEN_B Serial Port DMA Chaining Enable B. This bit enables (if set, =1) or disables (if cleared, =0) serial ports channel B DMA chaining. This bit is reserved when the SPORT is in multichannel mode. 22 FS_BOTH FS Both Enable. This bit issues WS if data is present in both transmit buffers if set (=1). If cleared (=0), WS is issued if data is present in either transmit buffers. This bit is reserved when the SPORT is in multichannel mode. 23 24 SPEN_B Reserved Serial Port Enable B. This bit enables (if set, =1) or disables (if cleared, =0) the corresponding serial port B channel. This bit is reserved when the SPORT is in multichannel mode. 25 DDIR Data Direction Control. This bit activates transmit buffers TXnA or TXnB if set (=1) or enables receive buffers RXnA or RXnB if cleared (=0). This bit is reserved when the SPORT is in multichannel mode. 26 DERR_B DXB Error Status (Sticky, Read-Only). This bit indicates whether the serial transmit operation has underflowed (if set, =1 and DDIR=1) or a receive operation has overflowed (if cleared, =0 and DDIR=0) in the DXB data buffer. This bit is reserved when the SPORT is in multichannel mode.

ADSP-21161 SHARC Processor Hardware Reference

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I/O Processor Registers

Table A-27. Serial Port Control Registers (SPCTLx) Bit Definitions (Contd)
Bit(s) 28-27 Name DXS_B Definition DXB Data Buffer Status (Read-Only). These bits indicate the status of the serial ports DXB data buffer as follows: 11=full, 00=empty, 10=partially full. This bit is reserved when the SPORT is in multichannel mode. 29 DERR_A (ROVF_A, TUVF_A) DXS_A (RXS_A, TXS_A) DXA Error Status (Sticky, Read-Only). This bit indicates whether the serial transmit operation has underflowed (if set, =1 and DDIR=1) or a receive operation has overflowed (if cleared, =0 and DDIR=0) in the DXA data buffer. DXA Data Buffer Status (Read-Only). These bits indicate the status of the serial ports DXA data buffer as follows: 11=full, 00=empty, 10=partially full.

31-30

A-104

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Registers

S PC TL0 (0x01c0) S PC TL1 (0x01e0) S PC TL2 (0x01d0) S PC TL3 (0x01f0)

D XS _ A
D XA D ata B uffer S tatus 11=full, 10=partially full, 00=em pty

D S P Serial M ode
31 30 29 28 27 26 25 24 23 22 21 20 0 0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 0 0 0 0

LFS

A ctive Low FS 0=active high, 1=active low

L AFS
Late F S 0=early F S , 1=late FS

D ER R _ A
D X A E rror S tatus (sticky) D D IR =1,transm it underflow status D D IR =0, receive overflow status

S D EN _ A
S P O R T D M A enable A channel 1=enable, 0=disable

D X S _B *
D X B D ata B uffer S tatus 11=full, 10=partially full ,00=em pty

S C H EN _ A
D M A chaining enable A channel 1=enable, 0=disable

D E R R _B *
D X B E rror S tatus (sticky)

S D EN _ B
S P O R T D M A enable B channel 1=enable, 0=disable

D D IR **
D ata D irection C ontrol 1=A ctive Transm it B uffers T X nB /T XnA 0=E nable R eceive B uffers R X nB /R X nA

S C H EN _ B
D M A chaining enable B channel 1=enable, 0=disable

S P E N _B
S P O R T E nable B 1=enable, 0=disable * S tatus is R ead-only ** D o not read/write from /to inactive R Xn/TX n buffers 15 14 13 12 0 0 0 0 11 10 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

FS _B O TH
1=issue W S only if data is present in both Tx 0=issue W S if data is present in either T x

D IT FS
D ata Independent tx F S (if D D IR =1) 1=data independent, 0= data dependent

S P E N _A
S P O R T E nable A (1=enable, 0=disable)

IF S
Internally generated FS 1=internal FS , 0=external FS

D T YP E
D ata type 00=right-justify; fill M S B w ith 0s 01=right-justify; sign extend M S B 10=com pand m u-law 11=com pand A -law

FS R
FS requirem ent 1=F S required, 0=FS not required

SENDN
E ndian w ord form at 0=M S B first, 1=LS B first

CKRE
C lock edge for data Fram e S ync sam pling or driving (1=rising edge, 0=falling edge)

S LE N
S erial W ord Length-1

OPMODE
S P O R T O peration M ode 0=D S P serial m ode/m ultichannel m ode 1=I 2 S m ode

P AC K
16/32 packing 1=packing, 0=no packing

IC LK

Internally generated S C LK 1=internal clock, 0=external clock

Figure A-31. SPCTL Register DSP Serial Mode

ADSP-21161 SHARC Processor Hardware Reference

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I/O Processor Registers

SPCTL0 SPCTL1 SPCTL2 SPCTL3

(0x01c0) (0x01e0) (0x01d0) (0x01f0)

DXS_A

I 2S Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DXA Data Buffer Status 11=full, 10=partially full, 00=empty

L_FIRST

Left or Right I2S channel RX/TX first 1=start left data first 0= start right data first

DERR_A
DXA Error Status (sticky) DDIR=1,transmit underflow status DDIR=0, receive overflow status

SDEN_A
SPORT Transmit DMA enable A ch. 1=enable, 0=disable

DXS_B*
DXB Data Buffer Status 11=full, 10=partially full, 00=empty

SCHEN_A

DMA chaining enable A channel 1=enable, 0=disable

DERR_B*
DXB Error Status (sticky)

SDEN_B
SPORT transmit DMA enable Bch . 1=enable, 0=disable

D DIR**
Data Direction Control 1=Active Transmit Buffers TXnA/TXnB 0=Enable Receive Buffers RXnA/RXnB

SCHEN_B
DMA Chaining enable B channel 1=enable, 0=disable

SPEN_B
SPORT Enable B 1=enable, 0=disable * Status is Read-only ** Do not read/write from/to inactive RXn/TXn buffers 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 4 0 3 2 1 0 0 0

FS_BOTH
1=issue WS only if data is present in both Tx 0=issue WS if data is present in either Tx

0 0

DITFS
Data Independent tx FS (if DDIR=1) 1=data independent, 0=data dependent

SPEN_A
SPORT Enable A (1=enable, 0=disable)

OPMODE
SPORT Operation Mode 0=DSP serial mode/multichannel mode 1=I2S mode

SLEN
Serial Word Length- 1

PACK
16/32 packing 1=packing, 0=no packing

MSTR
I2S serial and L/R clock Master 1=internal SCLK and WS, TX/RX is master 0=external SLCK and WS, TX/RX is slave

(Reserved bits must be cleared for I 2 S operation)

Figure A-32. SPCTLx RegisterI2S Mode

A-106

ADSP-21161 SHARC Processor Hardware Reference

Registers

Multichannel Mode
Receive Control Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0

SPCTL0 (0x01C0) SPCTL1 (0x01E0)

LRFS RXS_A*
RXA Data Buffer Status 11=full, 10=partially full, 00=empty Active Low Multichannel Receive FS0/FS1 0=active high, 1=active low

SDEN_A
SPORT receive DMA enable A 1=enable, 0=disable

ROVF_A*
RXA Underflow Status (sticky)

SCHEN_A
SPORT receive DMA chaining enable A 1=enable, 0=disable

*Status is Read-only

15 14 13 12 11 10 0 0 0 0 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

IRFS
Internally Generated Multichannel rx FS 1=internal FS0/FS1, 0=external FS0/FS1

DTYPE

CKRE
Active clock edge for data & frame sync sampling (1=rising edge, 0=falling edge)

Data type 00=right-justify; fill MSB with 0s 01=right-justify; sign extend MSB 10=compand mu-law 11=compand A-law

SENDN
Endian word format 0=MSB first, 1=LSB first

OPMODE
SPORT Operation Mode 0=DSP serial mode/multichannel mode 1=I2S mode

SLEN
Serial Word Length -1

ICLK
Internally -generated Receive clock 1=internal clock, 0=external clock

PACK
16/32 packing 1=packing, 0=no packing

(Reserved bits must be cleared for multichannel operation)

Figure A-33. SPCTL0 and SPCTL1 Registers

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Multichannel Mode
Transmit Control Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0

SPCTL2 (0x01d0) SPCTL3 (0x01f0)

LTDV TXS_A*
TXA Data Buffer Status 11=full, 10=partially full, 00=empty Active Low MC Transmit Data Valid 0=active high TVD2/TDV3 1=active low TDV2/TDV3

SDEN_A
SPORT transmit DMA enable A 1=enable, 0=disable

TUVF_A*
TXA Underflow Status (sticky)

SCHEN_A
SPORT transmit DMA chaining enable A 1=enable, 0=disable 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

Reserved** OPMODE
SPORT Operation Mode 0=DSP serial mode/multichannel mode 1=I 2S mode

DTYPE

Data type x0=right-justify; fill MSB with 0s x1=right-justify; sign extend MSB 0x=compand mu-law 1x=compand A-law

PACK
16/32 packing 1=packing, 0=no packing

SENDN
Endian word format 0=MSB first, 1=LSB first

SLEN
Serial Word Length -1

(Reserved bits must be cleared for multichannel operation)

*Status is Read-only **The CKRE values for SPCTL2 and SPCTL3 come from SPCTL0 and SPCTL1 (respectively) in multichannel mode.

Figure A-34. SPCTL2 and SPCTL3 Registers

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SPORT Multichannel Control Registers (SPxyMCTL) These registers addresses are SP02MCTL0x1DF, SP13MCTL0x1FF. The SP02MCTL register is the multichannel control register for SPORTs 0 and 2. The SP13MCTL register is the multichannel control register for SPORTs 1 and 3. The reset value for these registers is undefined. These registers are described in Table A-28 and Figure A-35. Table A-28. SPORT Multichannel Control Register Bit Definitions
Bit(s) 0 Name MCE Definition Multichannel Mode Enable. Standard and multichannel modes only. Bit 0 in the SP02MCTL and SP13MCTL registers.One of two configuration bits that enable and disable multichannel mode on both the receive or transmit serial port channels. See also, OPMODE. 0 = Disable multichannel operation. 1 = Enable multichannel operation if OPMODE=0. Multichannel Frame Delay. These bits set the interval, in number of serial clock cycles, between the multichannel frame sync pulse and the first data bit. These bits provide support for different types of T1 interface devices. Valid values range are from 0 to 15 with bits SP02MCTL[4:1] or SP13MCTL[4:1]. Values of 1 to15 correspond to the number of intervening serial clock cycles. A value of 0 corresponds to no delay. The multichannel frame sync pulse is concurrent with first data bit. 11-5 NCH Number of Multichannel Slots (minus one).These bits select the number of channel slots (maximum of 128) to use for multichannel operation.Valid values for actual number of channel slots range from 1 to 128. Use this formula to calculate the value for NCH: NCH = Actual number of channel slots -1.

4-1

MFD

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Table A-28. SPORT Multichannel Control Register Bit Definitions

Bit(s) 12 Name SPL Definition SPORT Loopback Mode. This bit enables if set (=1) or disables if cleared (=0) the channel loopback mode. Loopback mode enables developers to run internal tests and to debug applications. Loopback only works under the following SPORT configurations: SPORT0 (configured as a receiver or transmitter) together with SPORT2 (configured as a transmitter or receiver). SPORT0 can only be paired with SPORT2, controlled via the SPL bit in the SP02MCTL register. SPORT1 (configured as a receiver or transmitter) together with SPORT3 (configured as a transmitter or receiver). SPORT1 can only be paired with SPORT3, controlled via the SPL bit in the SP13MCTL register. Either of the two paired SPORTs can be set up to transmit or receive, depending on their DDIR bit configurations. 15-13 22-16 CHNL Reserved Current Channel Selected (Read-Only, Sticky). These bits identify the currently selected transmit channel slot (0 to 127). Reserved

31-23

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SP02MCTL (0x01DF) SP13MCTL (0x01FF)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CHNL
Current Channel (read-only) 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 5 4 0 3 2 1 0 0 0

0 0

0 0

SPL
SPORTLoopback SPORT0 & SPORT2 only SPORT1 & SPORT3 only

MCE
Multichannel enable (1=enable, 0=disable)

MFD
Multichannel Frame Delay

NCH
Number of Channels - 1

Figure A-35. SP02MCTL and SP13MCTL Registers SPORT Transmit Buffer Registers (TXx) The TXx registers addresses are: TX0A0x1C1, Tx0B0x1C2, Tx1A0x1E1, Tx1B0x1E2, Tx2A0x1D1, Tx2B0x1D2, Tx3A0x1F1, Tx3B0x1F2. The reset value for these registers is undefined. The 32-bit TXx registers hold the output data for serial port transmit operations. For more information on how transmit buffers work, see Transmit and Receive Data Buffers on page 10-30. SPORT Receive Buffer Registers (RXx) The RXx registers addresses are: Rx0A0x1C3, Rx0B0x1C4, Rx1A0x1E3, Rx1B0x1E4, Rx2A0x1D3, Rx2B0x1D4, Rx3A0x1F3, Rx3B0x1F4. The reset value for these registers is undefined. The 32-bit RXx registers hold the input data from serial port receive operations. For more information on how receive buffers work, see Transmit and Receive Data Buffers on page 10-30.

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SPORT Divisor Registers (DIVx) The DIVx registers addresses are: DIV00x1C5, DIV10x1E5, DIV20x1D5, DIV30x1F5 (shown in Figure A-36). The reset value for these registers is undefined. These registers contain two fields: Bits 15-0 are CLKDIV. These bits select the Serial Clock Divisor for internally generated SCLK as follows: f CCLK CLKDIV = ------------------- 1 2 ( f SCLK ) Bits 31-16 are FSDIV. These bits select the Frame Sync Divisor for internally generated TFS as follows: f SCLK FSDIV = ----------- 1 f SFS

DIV0 (0x1C5) DIV1 (0x1E5) DIV2 (0x1D5) DIV3 (0x1F5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

FSDIV Frame Sync Divisor

15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 1 5 4 0 0 3 0 2 0 1 0 0 0

CLKDIV Clock Divisor

Figure A-36. DIVx Register

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SPORT Count Registers (CNTx) The CNTx registers addresses are: CNT00x1C6, CNT10x1E6, CNT20x1D6, CNT30x1F6. The reset value for these registers is undefined. The CNTx registers provides status information for the internal clock and frame sync. SPORT Transmit Select Registers (MT2CSx and MT3CSx) The MT2CSx and MT3CSx registers addresses are: MT2CS00x1D7, MT2CS10x1D9, MT2CS20x1DB, MT2CS30x1DD, MT3CS00x1F7, MT3CS10x1F9, MT3CS20x1FB, MT3CS30x1FD. The reset value for these registers is undefined. Each bit, 31-0, set (=1) in one of four MTxCSx registers correspond to an active transmit channel, 127-0, on a multichannel mode serial port. When the MT2CSx and MT3CSx registers activate a channel, the serial port transmits the word in that channels position of the data stream. When a channels bit in the MTCSx register is cleared (=0), the serial ports DT (data transmit) pin three-states during the channels transmit time slot. SPORT Transmit Compand Registers (MT2CCSx and MT3CCSx) The MT2CCSx and MT3CCSx registers addresses are: MT2CCS00x1D8,
MT2CCS10x1DA, MT2CCS20x1DC, MT2CCS30x1DE, MT3CCS00x1F8, MT3CCS10x1FA, MT3CCS20x1FC, MT3CCS30x1FE.

The reset value for

these registers is undefined. Each bit, 31-0, set (=1) in one of four MTxCCSx registers correspond to an companded transmit channel, 127-0, on a multichannel mode serial port. When the MTCCSx register activates companding for a channel, the serial port applies the companding from the serial ports DTYPE selection to the transmitted word in that channels position of the data stream. When a channels bit in the MTCCSx register is cleared (=0), the serial port does not compand the output during the channels receive time slot.

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SPORT Receive Select Registers The MRCSx registers addresses are: MR0CS00x1C7, MR0CS10x1C9, MR0CS20x1CB, MR0CS30x1CD, MR1CS00x1E7, MR1CS10x1E9, MR1CS20x1EB, MR1CS30x1ED. The reset value for these registers is undefined. Each bit, 31-0, set (=1) in one of the four MRCSx registers corresponds to an active receive channel, 127-0, on a multichannel mode serial port. When the MRCSx register activates a channel, the serial port receives the word in that channels position of the data stream and loads the word into the RXx buffer. When a channels bit in the MRCSx register is cleared (=0), the serial port ignores any input during the channels receive time slot. SPORT Receive Compand Registers These registers addresses are: MR0CCS00x1C8, MR0CCS10x1CA, MR0CCS20x1CC, MR0CCS30x1CE, MR1CCS00x1E8, MR1CCS10x1EA, MR1CCS20x1EC, MR1CCS30x1EE. The reset value for these registers is undefined. Each bit, 31-0, set (=1) in the MR0CCSx and MR1CCSx registers correspond to an companded receive channel, 127-0, on a multichannel mode serial port. When one of the four MR0CCSx and MR1CCSx registers activate companding for a channel, the serial port applies the companding from the serial ports DTYPE selection to the received word in that channels position of the data stream. When a channels bit in the MR0CCSx and MR1CCSx registers are cleared (=0), the serial port does not compand the input during the channels receive time slot.

Serial Peripheral Interface Registers

The following sections provide descriptions of the registers used in setting up the processors SPI interface.

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SPI Port Status Register

This registers address is 0xB5 and it is described in Table A-29 and Figure A-37. The reset value for this register is undefined.The SPISTAT register is a read-only register used to detect when an SPI transfer is complete, if transmission or reception errors occur, and the status of the SPITX and SPIRX FIFOs. Table A-29. SPI Status Register Bit Descriptions
Bit(s) 0 Name SPIF Definition SPI Transmit or Receive Transfer Complete. This bit is set (=1) when the SPI transfer is complete and one of the following conditions is met: SPRINT = 1 and receive buffer full or RDMAEN = 1 and receive buffer full or SPTINT = 1 and transmit buffer empty or TDMAEN = 1 and transmit buffer empty 1 MME Multimaster Error. This bit is set when a device that is not currently the master device tries to become the master by driving a SPIDS signal while the current master device is communicating to SPI slave devices. Transmission Error. This bit is set when SPI is Slave/Master, SPTINT = 1 or TDMAEN = 1, but there is no data in SPITX FIFO. If you are not servicing the interrupt quickly enough and not updating the contents of SPITX, this bit is set. In master mode, this means an end of operation and SPI going into idle mode. Transmit Data Buffer Status. These bits indicate the status of the SPITX data buffer status (read only) as follows: 00 = empty, 01 = partially full, 11 = full.

TXE

4-3

TXS

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Table A-29. SPI Status Register Bit Descriptions (Contd)

Bit(s) 5 Name RBSY Definition Reception Error. This bit is set when a data is received with receive buffer full. Either RDMAEN = 1 or SPRINT = 1 and the receive buffer is full. In master mode, this means an end of operation and SPI going into idle mode. Receive Data Buffer Status. These bits indicate the status of the SPIRX data buffer status (read only) as follows: 00 = empty, 01 = partially full, 11 = full. 31-8 Reserved

7-6

RXS

3 1 30 2 9 2 8 2 7 2 6 2 5 2 4

23 2 2 2 1 20 0 0 0 0

1 9 18 17 1 6 0 0 0 0

SP IS TA T 0xB 5

1 5 1 4 13 1 2 0 0 0 0

1 1 10 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

RXS
SP IR X D a ta B u ffer Statu s (R ead -on ly ) 00=S PIR X em p ty 01=S PIR X p artially fu ll 11=S PIR X full 10=R es erve d

S P IF
SPI T ran sm it T ran s fer C o m p lete 1=tran sfer co m ple te , 0= ac tiv e tran sfer

MME
M u ltim aster E rro r 0= n o erro r, 1 = SP ID S~ as serted b y s lave

RBSY
R ec ep tio n E rro r (O verflow ) 1=n ew d ata receiv ed with fu ll R XB FIFO S PI en ters id le m o d e if m aster d evice

TXE
Tran sm iss ion E rror (U nd erflow ) 1= n o n ew d ata in T X F IF O , S PI en ters id le m o d e if m aster d evice

TXS
SP IT X D a ta B u ffer Statu s (read o n ly) 00= S PIT X em p ty 01= T X B p artially full 11= S PIT X full 10= R eserv ed

Figure A-37. SPISTAT Register

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SPI Control Register (SPICTL)

This registers address is 0xB4 and it is described in Table A-30 and Figure A-38. The reset value for these registers is undefined. The SPI Control Register (SPICTL) register is used to configure and enable the SPI system. This register is used to set up SPI configurations such as selecting the device as a master or slave or determining the data transfer rate and word size. Table A-30. SPI Control Register Bit Descriptions
Bit(s) 0 1 Name SPIEN SPRINT Function SPI Port Enable. This bit enables (if set, =1) or disables (if cleared, =0) the SPI system. SPIRX Interrupt Enable. This bit enables (if set, =1) or disables (if cleared, =0) an SPI interrupt. An interrupt is generated when the receive buffer is not empty. SPITX Interrupt Enable. This bit enables (if set, =1) or disables (if cleared, =0) an SPI interrupt. An interrupt is generated when the transmit buffer is not full. Master Select. This bit selects the device as a master device (if set, =1) or a slave device (if cleared, =0). Clock Polarity. This bit selects the clock polarity. SPICLK high is the idle state (if set, =1), or SPICLK low is the idle state (if cleared, =0). Clock Phase. This bit selects the clock phase transfer format. When set (=1), the SPICLK starts toggling at the beginning of the first data transfer bit. When cleared (=0), the SPICLK starts toggling at the middle of the first data transfer bit. For more information, see Figure 11-7 on page 11-22. 6 DF Data Format. This bit selects the data format. When set (=1), the MSB is sent/received first. When cleared (=0), the LSB is sent/received first. Word Length. This bit selects the word length as follows: 00 = 8 bits, 01 = 16 bits, 11 = 32 bits,10 = reserved.

SPTINT

3 4

MS CP

CPHASE

7-8

WL

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Table A-30. SPI Control Register Bit Descriptions (Contd)

Bit(s) 9-12 Name BAUDR Function Baud Rate. These bits define the SPICLK frequency per the following equation: SPICLK baud rate= Core clock / 2(2 + BR) 13 TDMAEN Transmit DMA Enable. This bit enables (if set, =1) or disables (if cleared, =0) DMA transfers to the transmit buffer. At SPI boot this bit is 0.

Bits 14 to 24 are controlled during master mode. 14 PSSE Programmable Slave Select Enable. This bit is used to program the controlled automatic generation of slave device select signals during SPI transfers. This bit enables (if set, =1) or disables (if cleared, =0) the programmable slave select mode. The slave selection is subsequently made using the FLS bit. Flag Select. These bits select which flag pins are asserted when multiple slaves are used (0=Disable, 1=Enable) as follows: Bit 15= FLAG0 Bit 16= FLAG1 Bit 17= FLAG2 Bit 18= FLAG3 Note: Only Flag[0] to Flag[3] can be used this way. 19 NSMLS Non-Seamless Operation. This bit, if set (=1), indicates that after each word transfer there is a delay before the next word transfer starts. When cleared (=0), indicates no delay before the next word starts, a seamless operation. Deselect SPIDS in CPHASE = 0. This bit deselects when high (=1) the slaves between successive word transfers in CPhase 0. The slave is selected in master mode using PSSE functionality. This bit has no effect in slave mode for the SPI port. This functionality is valid only when NSMLS =1 and CPHASE =0. This bit is cleared (=0) when not in use.

15-18

FLS

20

DCPH0

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Table A-30. SPI Control Register Bit Descriptions (Contd)

Bit(s) 25 Name DMISO Function Disable MISO Pin. This bit three-states, (if set, =1) the master in slave out (MISO) pin or (if cleared, =0) enables MISO. This is needed in an environment where master wishes to transmit to various slaves at one time (broadcast). Except for the slave from which it wishes to receive, all other slaves should have this bit set. Open Drain Output Enable. This bit enables an open drain for data pins if set (=1) or remains normal if cleared (=0). If enabled, the MISO, MOSI and SPICLK is driven only for logic low and pulled up by a 50 k resistance for a logic high. Receive DMA Enable. This bit enables (if set, =1) or disables (if cleared, =0) DMA transfers from the receive buffer. At SPI boot this bit is set to 1 to enable the booting process via the SPI port. 28 PACKEN Packing Enable. This bit enables, if set (=1), 8- to 32-bit packing or disables the packing, if cleared (=0). If this bit is enabled, the receiver packs the received byte whereas the transmitter unpacks the data before sending it. Fore more information on the packing, see SPI Word Packing on page 11-24. Note: This bit should be 1 only for 8-bit data word length (WL = 00). 29 30 31 SGN SENDLW GM Sign Extend. This bit sign extends the word if set (=1) or does not extend the sign if cleared (=0). Send Last Data. When SPITX is empty, setting this bit(=1) re transmits the last data. Clearing this bit (=0) sends zeros. Get Data. This bit fetches incoming data when set (=1) or discards incoming data when cleared (=0). The data that comes in overwrites the previous data in the SPIRX.

26

OPD

27

RDMAEN

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SPICTL
0xB4
GM
Fetch/Discard Incoming RXB data when RXB full 0=Discard incoming data 1=Overwrite with new data

31 30 29 28 27 26 25 24 23 22 21 20 0 0 0 0 0 0 0 0 0 0 0 0

19 18 17 16 0 0 0 0

FLS1
FLAG1 Slave Device Select 1=Enable, 0=Disable

SENDLW
Send Zero/Repeat Byte When TXB Empty 0=Send zero, 1=Repeat last data

FLS2
FLAG2 Slave Device Select 1=Enable, 0=Disable

SGN
Sign Extend Data 0=no sign extend, 1=sign extend

FLS3
FLAG3 Slave Device Select 1=Enable, 0=Disable

PACKEN
8-bit Packing Enable 0=no packing, 1=8 to 32-bit packing

NSMLS
Non-Seamless operation 0=no delay, 1=delay before next word starts

RDMAEN
Receive DMA Enable 1=Enable, 0=Disable

OPD
Open Drain Output Enable for Data Pins 0=Normal, 1=Open Drain

DCPH0
Deselect SPIDS in CPHASE =0 (master mode only, NSMLS bit=1) 0=No SPI device select 1=Deselects slaves between successive transfers

DMISO
Disable MISO Pin (Broadcast) 0=MISO Enabled, 1=MISO Disabled

15 14 13 12 11 10 1 0 0 0 0 1

9 1

8 1

7 0

6 1

5 0

4 0

3 0

2 0

1 0

0 0 SPIEN
SPI System Enable 1=enable, 0=disable

FLS0
FLAG0 Slave Device Select 1=Enable, 0=Disable

PSSE
Programmable Slave Select Enable 0=Disable, 1=Enable

SPRINT
SPI RX Buffer Interrupt Enable 1=enable SPI IRQ on RXB empty, 0=disable

TDMAEN
Transmit DMA Enable 1=Enable, 0=Disable

SPTINT
SPI TX Buffer Interrupt Enable 1=enable SPI IRQ on TXB not full, 0=disable

BAUDR
Baud Rate CCLK / (2**(2 + BR))

MS
Master/Slave Mode Bit 0=SPI slave device, 1=SPI Master Device

WL
Word Length 00=8 bits, 01=16 bits, 11=32 bits, 10=RESERVED

CP
Clock polarity 0=SPICLK active high, low in idle state 1=SPICLK active low, high in idle state

DF
Data Format 0=LSB sent / received first 1=MSB sent / received first

CPHASE
Clock phase 0=SPICLK toggles at middle of 1st data bit 1=SPICLK toggles at beginning of 1st data bit

Figure A-38. SPICTL Register

SPI Receive Buffer Register (SPIRX)

This registers address is 0xB7. The reset value for this register is undefined. This is a 32-bit read-only register accessible by the core or DMA controller. At the end of a data transfer, SPIRX is loaded with the data in the shift register. During a DMA receive operation, the data in SPIRX is

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automatically loaded into the internal memory. For core or interrupt driven transfer, you can also use the RXS status bits in the SPISTAT register to determine if the receive buffer is full. Reading from an empty SPIRX buffer causes a core hang if the buffer hang disable bit is cleared in the SYSCON register.

SPI Transmit Buffer Register (SPITX)

This registers address is 0xB6.The reset value for this register is undefined. This SPI transmit data register is a 32-bit register which is part of the IOP register set and can be accessed by the core or the DMA controller. Data is loaded into this register before being transmitted. Prior to the beginning of a data transfer, data in SPITX is automatically loaded into the transmit shift register. During a DMA transmit operation, the data in SPITX is automatically loaded from internal memory.

Register and Bit #Defines (def21161.h)

The following example definitions file is for the ADSP-21161 processor. For the most current definitions file, programs should use the version of this file included with the software development tools. The version of the file that appears here is provided as a guide only.
/***************************************************************/ * * def21161.h * * (c) Copyright 2001 Analog Devices, Inc. All rights reserved. * /*****************************************************************/ /*---------------------------------------------------------------def21161.h - SYSTEM & IOP REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-21161 Last updated 5/14/01 This include file contains a list of macro defines to enable the programmer to use symbolic names for the following ADSP-21161 facilities: - instruction condition codes - system register bit definitions - IOP register address memory map - *most* IOP control/status register bit definitions Changes from def21160 include new I/O flags, SDRAM and SPI interfaces, changes to SPORT, Link Port, and DMA.

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Register and Bit #Defines (def21161.h)

Here are some example uses: bit set mode1 BR0|IRPTEN|ALUSAT; ustat1=BSO|HPM01|HMSWF; DM(SYSCON)=ustat1; ----------------------------------------------------------------------------- */ #ifndef __DEF21161_H_ #define __DEF21161_H_ /*----------------------------------------------------------------------------*/ /* System Register bit definitions */ /*----------------------------------------------------------------------------*/ /* MODE1 and MMASK registers */ #define BR8 0x00000001 /* Bit 0: Bit-reverse for I8 */ #define BR0 0x00000002 /* Bit 1: Bit-reverse for I0 (uses DMS0- only ) */ #define SRCU 0x00000004 /* Bit 2: Alt. register select for comp. units */ #define SRD1H 0x00000008 /* Bit 3: DAG1 alt. register select (7-4) */ #define SRD1L 0x00000010 /* Bit 4: DAG1 alt. register select (3-0) */ #define SRD2H 0x00000020 /* Bit 5: DAG2 alt. register select (15-12) */ #define SRD2L 0x00000040 /* Bit 6: DAG2 alt. register select (11-8) */ #define SRRFH 0x00000080 /* Bit 7: Register file alt. select for R(15-8) */ #define SRRFL 0x00000400 /* Bit 10: Register file alt. select for R(7-0) */ #define NESTM 0x00000800 /* Bit 11: Interrupt nesting enable */ #define IRPTEN 0x00001000 /* Bit 12: Global interrupt enable */ #define ALUSAT 0x00002000 /* Bit 13: Enable ALU fixed-pt. saturation */ #define SSE 0x00004000 /* Bit 14: Enable short word sign extension */ #define TRUNCATE 0x00008000 /* Bit 15: 1=fltg-pt. truncation 0=Rnd to nearest */ #define RND32 0x00010000 /* Bit 16: 1=32-bit fltg-pt.rounding 0=40-bit rnd */ #define CSEL 0x00060000 /* Bit 17-18: CSelect: Bus Mastership */ #define PEYEN 0x00200000 /* Bit 21: Processing Element Y enable */ #define SIMD 0x00200000 /* Bit 21: Enable SIMD Mode */ #define BDCST9 0x00400000 /* Bit 22: Load Broadcast for I9 */ #define BDCST1 0x00800000 /* Bit 23: Load Broadcast for I1 * #define CBUFEN 0x01000000 /* Bit 23: Circular Buffer Enable */ /* MODE2 register */ #define IRQ0E 0x00000001 /* Bit 0: IRQ0- 1=edge sens. 0=level sens. */ #define IRQ1E 0x00000002 /* Bit 1: IRQ1- 1=edge sens. 0=level sens. */ #define IRQ2E 0x00000004 /* Bit 2: IRQ2- 1=edge sens. 0=level sens. */ #define CADIS 0x00000010 /* Bit 4: Cache disable */ #define TIMEN 0x00000020 /* Bit 5: Timer enable */ #define BUSLK 0x00000040 /* Bit 6: External bus lock */ #define FLG0O 0x00008000 /* Bit 15: FLAG0 1=output 0=input */ #define FLG1O 0x00010000 /* Bit 16: FLAG1 1=output 0=input */ #define FLG2O 0x00020000 /* Bit 17: FLAG2 1=output 0=input */ #define FLG3O 0x00040000 /* Bit 18: FLAG3 1=output 0=input */ #define CAFRZ 0x00080000 /* Bit 19: Cache freeze */ #define IIRAE 0x00100000 /* Bit 20: Illegal IOP Register Access Enable */ #define U64MAE 0x00200000 /* Bit 21: Unaligned 64-bit Memory Access Enable */ /* bits 31-30, 27-25 are Processor ID[4:0], read only, value: 0b01001 bits 29-28 are silicon revision[1:0], read only, value: 0 These bits (only) are routed to Mode2 Shadow register (IOP register 0x11)*/ /* FLAGS register */ #define FLG0 0x00000001 #define FLG1 0x00000002 #define FLG2 0x00000004 #define FLG3 0x00000008

/* /* /* /*

Bit Bit Bit Bit

0: 1: 2: 3:

FLAG0 FLAG1 FLAG2 FLAG3

value value value value

*/ */ */ */

/* ASTATx and ASTATy registers */ #ifdef SUPPORT_DEPRECATED_USAGE /* Several of these (AV, AC, MV, SV, SZ) are assembler-reserved keywords, so this style is now deprecated. If these are defined, the assemblerreserved keywords are still available in lowercase, e.g., IF sz JUMP LABEL1.*/

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# # # # # # # # # # # # # # # # # # # # # # #

define define define define define define define define define define define define define define define define define define define define define define define

AZ AV AN AC AS AI MN MV MU MI AF SV SZ SS BTF CACC0 CACC1 CACC2 CACC3 CACC4 CACC5 CACC6 CACC7

0x00000001 0x00000002 0x00000004 0x00000008 0x00000010 0x00000020 0x00000040 0x00000080 0x00000100 0x00000200 0x00000400 0x00000800 0x00001000 0x00002000 0x00040000 0x01000000 0x02000000 0x04000000 0x08000000 0x10000000 0x20000000 0x40000000 0x80000000

/* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /*

Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit

0: 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: 13: 18: 24: 25: 26: 27: 28: 29: 30: 31:

ALU result zero or fltg-pt. underflow ALU overflow ALU result negative ALU fixed-pt. carry ALU X input sign (ABS and MANT ops) ALU fltg-pt. invalid operation Multiplier result negative Multiplier overflow Multiplier fltg-pt. underflow Multiplier fltg-pt. invalid operation ALU fltg-pt. operation Shifter overflow Shifter result zero Shifter input sign Bit test flag for system registers Compare Accumulation Bit 0 Compare Accumulation Bit 1 Compare Accumulation Bit 2 Compare Accumulation Bit 3 Compare Accumulation Bit 4 Compare Accumulation Bit 5 Compare Accumulation Bit 6 Compare Accumulation Bit 7

*/ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */

#endif #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define ASTAT_AZ ASTAT_AV ASTAT_AN ASTAT_AC ASTAT_AS ASTAT_AI ASTAT_MN ASTAT_MV ASTAT_MU ASTAT_MI ASTAT_AF ASTAT_SV ASTAT_SZ ASTAT_SS ASTAT_BTF ASTAT_CACC0 ASTAT_CACC1 ASTAT_CACC2 ASTAT_CACC3 ASTAT_CACC4 ASTAT_CACC5 ASTAT_CACC6 ASTAT_CACC7 0x00000001 0x00000002 0x00000004 0x00000008 0x00000010 0x00000020 0x00000040 0x00000080 0x00000100 0x00000200 0x00000400 0x00000800 0x00001000 0x00002000 0x00040000 0x01000000 0x02000000 0x04000000 0x08000000 0x10000000 0x20000000 0x40000000 0x80000000 /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 0: 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: 13: 18: 24: 25: 26: 27: 28: 29: 30: 31: ALU result zero or fltg-pt. u'flow*/ ALU overflow */ ALU result negative */ ALU fixed-pt. carry */ ALU X input sign(ABS and MANT ops)*/ ALU fltg-pt. invalid operation */ Multiplier result negative */ Multiplier overflow */ Multiplier fltg-pt. underflow */ Multiplier fltg-pt. invalid op. */ ALU fltg-pt. operation */ Shifter overflow */ Shifter result zero */ Shifter input sign */ Bit test flag for system registers*/ Compare Accumulation Bit 0 */ Compare Accumulation Bit 1 */ Compare Accumulation Bit 2 */ Compare Accumulation Bit 3 */ Compare Accumulation Bit 4 */ Compare Accumulation Bit 5 */ Compare Accumulation Bit 6 */ Compare Accumulation Bit 7 */

/* STKYx and STKYy registers */ /* bits 0 to 9 in both STKYx and STKYY, bits 17 to 26 in STKYx only */ #define AUS 0x00000001 /* Bit 0: ALU fltg-pt. underflow #define AVS 0x00000002 /* Bit 1: ALU fltg-pt. overflow #define AOS 0x00000004 /* Bit 2: ALU fixed-pt. overflow #define AIS 0x00000020 /* Bit 5: ALU fltg-pt. invalid operation #define MOS 0x00000040 /* Bit 6: Multiplier fixed-pt. overflow #define MVS 0x00000080 /* Bit 7: Multiplier fltg-pt. overflow #define MUS 0x00000100 /* Bit 8: Multiplier fltg-pt. underflow #define MIS 0x00000200 /* Bit 9: Multiplier fltg-pt. invalid operation /* STKYx register *ONLY* */ #define CB7S 0x00020000 /* Bit 17: DAG1 circular buffer 7 overflow #define CB15S 0x00040000 /* Bit 18: DAG2 circular buffer 15 overflow #define IIRA 0x00080000 /* Bit 19: Illegal IOP Register Access #define U64MA 0x00100000 /* Bit 20: Unaligned 64-bit Memory Access #define PCFL 0x00200000 /* Bit 21: PC stack full */ #define PCEM 0x00400000 /* Bit 22: PC stack empty */ #define SSOV 0x00800000 /* Bit 23: Status stack overflow (MODE1 and ASTAT)

*/ */ */ */ */ */ */ */ */ */ */ */

*/

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Register and Bit #Defines (def21161.h)

#define SSEM #define LSOV #define LSEM

0x01000000 /* Bit 24: Status stack empty */ 0x02000000 /* Bit 25: Loop stack overflow */ 0x04000000 /* Bit 26: Loop stack empty */

/* IRPTL and IMASK and IMASKP registers */ #define EMUI 0x00000001 /* Bit 0: Offset: 00: Emulator Interrupt */ #define RSTI 0x00000002 /* Bit 1: Offset: 04: Reset */ #define IICDI 0x00000004 /* Bit 2: Offset: 08: Illegal Input Condition Detected */ #define SOVFI 0x00000008 /* Bit 3: Offset: 0c: Stack overflow */ #define TMZHI 0x00000010 /* Bit 4: Offset: 10: Timer = 0 (high priority) */ #define VIRPTI 0x00000020 /* Bit 5: Offset: 14: Vector interrupt */ #define IRQ2I 0x00000040 /* Bit 6: Offset: 18: IRQ2- asserted */ #define IRQ1I 0x00000080 /* Bit 7: Offset: 1c: IRQ1- asserted */ #define IRQ0I 0x00000100 /* Bit 8: Offset: 20: IRQ0- asserted */ #define SP0I0x00000400 /* Bit 10: Offset: 28: SPORT0 DMA channel */ #define SP1I0x00000800 /* Bit 11: Offset: 2c: SPORT1 DMA channel */ #define SP2I0x00001000 /* Bit 12: Offset: 30: SPORT2 DMA channel */ #define SP3I0x00002000 /* Bit 13: Offset: 34: SPORT3 DMA channel */ #define LPISUMI0x00004000 /* Bit 14: Offset: na: LPort Interrupt Summary */ #define EP0I0x00008000 /* Bit 15: Offset: 50: External port channel 0 DMA */ #define EP1I0x00010000 /* Bit 16: Offset: 54: External port channel 1 DMA */ #define EP2I0x00020000 /* Bit 17: Offset: 58: External port channel 2 DMA */ #define EP3I0x00040000 /* Bit 18: Offset: 5c: External port channel 3 DMA */ #define LSRQI 0x00080000 /* Bit 19: Offset: 60: Link service request */ #define CB7I 0x00100000 /* Bit 20: Offset: 64: Circ. buffer 7 overflow */ #define CB15I 0x00200000 /* Bit 21: Offset: 68: Circ. buffer 15 overflow */ #define TMZLI 0x00400000 /* Bit 22: Offset: 6c: Timer = 0 (low priority) */ #define FIXI 0x00800000 /* Bit 23: Offset: 70: Fixed-pt. overflow */ #define FLTOI 0x01000000 /* Bit 24: Offset: 74: fltg-pt. overflow */ #define FLTUI 0x02000000 /* Bit 25: Offset: 78: fltg-pt. underflow */ #define FLTII 0x04000000 /* Bit 26: Offset: 7c: fltg-pt. invalid */ #define SFT0I 0x08000000 /* Bit 27: Offset: 80: user software int 0 */ #define SFT1I 0x10000000 /* Bit 28: Offset: 84: user software int 1 */ #define SFT2I 0x20000000 /* Bit 39: Offset: 88: user software int 2 */ #define SFT3I 0x40000000 /* Bit 30: Offset: 8c: user software int 3 */ /* LIRPTL register */ #define LP0I 0x00000001 /* Bit 0: Offset: 38: Link port channel 0 DMA */ #define LP1I 0x00000002 /* Bit 1: Offset: 3C: Link port channel 1 DMA */ #define SPIRI 0x00000004 /* Bit 2: Offset: 40: SPI Receive DMA */ #define SPITI 0x00000008 /* Bit 3: Offset: 44: SPI Transmit DMA */ #define LP0MSK 0x00010000 /* Bit 16: Link port channel 0 Interrupt Mask */ #define LP1MSK 0x00020000 /* Bit 17: Link port channel 1 Interrupt Mask */ #define SPIRMSK 0x00040000 /* Bit 18: SPI Receive Interrupt Mask */ #define SPITMSK 0x00080000 /* Bit 19: SPI Transmit Interrupt Mask */ #define LP0MSKP 0x01000000 /* Bit 24: Link port channel 0 Interrupt Mask Pointer */ #define LP1MSKP 0x02000000 /* Bit 25: Link port channel 1 Interrupt Mask Pointer */ #define SPIRMSKP 0x04000000 /* Bit 26: SPI Receive Interrupt Mask Pointer */ #define SPITMSKP 0x08000000 /* Bit 27: SPI Transmit Interrupt Mask Pointer */ /* LSRQ #define #define #define #define #define #define #define #define register */ L0TM 0x00000010 L0RM 0x00000020 L1TM 0x00000040 L1RM 0x00000080 L0TRQ 0x00100000 L1TRQ 0x00200000 L0RRQ 0x00400000 L1RRQ 0x00800000

/* Link Port 0 Transmit Mask /* Link Port 0 Receive Mask /* Link Port 1 Transmit Mask /* Link Port 1 Receive Mask /* Link Port 0 Transmit Request /* Link Port 1 Receive Request /* Link Port 0 Transmit Request /* Link Port 1 Receive Request

*/ */ */ */ */ */ */ */

/*------------------------------------------------------------------------------*/ /* */ /* I/O Processor Register Address Memory Map */ /* */ /*------------------------------------------------------------------------------*/ #define SYSCON 0x00 /* System configuration register */ #define VIRPT 0x01 /* Vector interrupt register */ #define WAIT 0x02 /* External Port Wait register - renamed to EPCON */

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Registers

#define EPCON 0x02 /* External Port configuration register */ #define SYSTAT 0x03 /* System status register */ /* the upper 32-bits of the 64-bit epbxs are only accessible as 64-bit reference*/ #define EPB0 0x04 /* External port DMA buffer 0 */ #define EPB1 0x06 /* External port DMA buffer 1 */ #define MSGR0 0x08 /* Message register 0 */ #define MSGR1 0x09 /* Message register 1 */ #define MSGR2 0x0a /* Message register 2 */ #define MSGR3 0x0b /* Message register 3 */ #define MSGR4 0x0c /* Message register 4 */ #define MSGR5 0x0d /* Message register 5 */ #define MSGR6 0x0e /* Message register 6 */ #define MSGR7 0x0f /* Message register 7 */ /* IOP shadow registers of the core control regs #define PC_SHDW 0x10 /* PC IOP shadow register (PC[23-0]) #define MODE2_SHDW 0x11 /* Mode2 IOP shadow register (MODE2[31-25]) #define EPB2 0x14 /* External port DMA buffer 2 #define EPB3 0x16 /* External port DMA buffer 3 #define BMAX 0x18 /* Bus time-out maximum */ #define BCNT 0x19 /* Bus time-out counter */ #define DMAC10 0x1c /* EP DMA10 control register */ #define DMAC11 0x1d /* EP DMA11 control register */ #define DMAC12 0x1e /* EP DMA12 control register */ #define DMAC13 0x1f /* EP DMA13 control register */ #define DMASTAT 0x37 /* DMA channel status register */ /* SPI Registers #define SPICTL #define SPISTAT #define SPIRX #define SPITX */ */ */ */ */

IOP Register Addresses*/ 0xb4 /* Serial peripheral-compatible interface control register */ 0xb5 /* Serial periipheral-compatible interface status register */ 0xb7 /* SPI receive data buffer */ 0xb6 /* SPI transmit data buffer */

/* IOFLAG Register Address */ #define IOFLAG 0x1b /* Address of programmable I/O flags 4-11 */ /* IOP registers for SDRAM controller. */ #define SDCTL 0xb8 /* SDRAM control reg. #define SDRDIV 0xb9 /* Refresh counter div reg. /* Link #define #define #define #define

*/ */

Port Registers */ LBUF0 0xc0 /* Link buffer 0 */ LBUF1 0xc2 /* Link buffer 1 */ LCTL 0xcc /* Link buffer control */ LSRQ 0xd0 /* Link service request and mask registers

*/

/* SPORT0 */ #define SPCTL0 0x1c0 #define TX0A 0x1c1 #define TX0B 0x1c2 #define RX0A 0x1c3 #define RX0B 0x1c4 #define DIV0 0x1c5 #define CNT0 0x1c6 /* SPORT2 */ #define SPCTL2 0x1d0 #define TX2A 0x1d1 #define TX2B 0x1d2 #define RX2A 0x1d3 #define RX2B 0x1d4 #define DIV2 0x1d5 #define CNT2 0x1d6 /* SPORT1 */ #define SPCTL1 0x1e0 #define TX1A 0x1e1 #define TX1B 0x1e2 #define RX1A 0x1e3

/* /* /* /* /* /* /*

SPORT0 SPORT0 SPORT0 SPORT0 SPORT0 SPORT0 SPORT0

serial port control register */ serial port control register */ transmit secondary B channel data buffer */ receive primary A channel data buffer */ receive secondary B channel data buffer */ divisor for transmit/receive SLCK0 and FS0 */ count register */

/* /* /* /* /* /* /*

SPORT2 SPORT2 SPORT2 SPORT2 SPORT2 SPORT2 SPORT2

serial port control register */ serial port control register */ transmit secondary B channel data buffer */ receive primary A channel data buffer */ receive secondary B channel data buffer */ divisor for transmit/receive SLCK2 and FS2 */ count register */

/* /* /* /*

SPORT1 SPORT1 SPORT1 SPORT1

serial port control register */ serial port control register */ transmit secondary B channel data buffer */ receive primary A channel data buffer */

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Register and Bit #Defines (def21161.h)

#define RX1B #define DIV1 #define CNT1

0x1e4 0x1e5 0x1e6

/* SPORT1 receive secondary B channel data buffer */ /* SPORT1 divisor for transmit/receive SLCK1 and FS1 */ /* SPORT1 count register */

/* SPORT3 */ #define SPCTL3 0x1f0 /* SPORT3 serial port control register */ #define TX3A 0x1f1 /* SPORT3 serial port control register */ #define TX3B 0x1f2 /* SPORT3 transmit secondary B channel data buffer */ #define RX3A 0x1f3 /* SPORT3 receive primary A channel data buffer */ #define RX3B 0x1f4 /* SPORT3 receive secondary B channel data buffer */ #define DIV3 0x1f5 /* SPORT3 divisor for transmit/receive SLCK3 and FS3 */ #define CNT3 0x1f6 /* SPORT3 count register */ /* SPORT0 - MCM Receive (Works in pair with SPORT2) */ #define MR0CS0 0x1c7 /* SPORT0 multichannel rx select, channels 31 - 0 */ #define MR0CCS0 0x1c8 /* SPORT0 multichannel rx compand select, channels 31 - 0 */ #define MR0CS1 0x1c9 /* SPORT0 multichannel rx select, channels 63 - 32 */ #define MR0CCS1 0x1ca /* SPORT0 multichannel rx compand select, channels 63 - 32 */ #define MR0CS2 0x1cb /* SPORT0 multichannel rx select, channels 95 - 64 */ #define MR0CCS2 0x1cc /* SPORT0 multichannel rx compand select, channels 95 - 64 */ #define MR0CS3 0x1cd /* SPORT0 multichannel rx select, channels 127 - 96 */ #define MR0CCS3 0x1ce /* SPORT0 multichannel rx compand select, channels 127 - 96 */ /* SPORT2 - MCM Transmit (Works in pair with SPORT0) #define MT2CS0 0x1d7 /* SPORT2 multichannel tx #define MT2CCS0 0x1d8 /* SPORT2 multichannel tx #define MT2CS1 0x1d9 /* SPORT2 multichannel tx #define MT2CCS1 0x1da /* SPORT2 multichannel tx #define MT2CS2 0x1db /* SPORT2 multichannel tx #define MT2CCS2 0x1dc /* SPORT2 multichannel tx #define MT2CS3 0x1dd /* SPORT2 multichannel tx #define MT2CCS3 0x1de /* SPORT2 multichannel tx #define SP02MCTL 0x1df */ select, compand select, compand select, compand select, compand

channels 31 - 0 */ select, channels 31 - 0 */ channels 63 - 32 */ select, channels 63 - 32 */ channels 95 - 64 */ select, channels 95 - 64 */ channels 127 - 96 */ select, channels 127 - 96 */

/* SPORTs 0 & 2 Multichannel Control Register */

/* SPORT1 - MCM Receive (Works in pair with SPORT3) */ #define MR1CS0 0x1e7 /* SPORT1 multichannel rx select, channels 31 - 0 */ #define MR1CCS0 0x1e8 /* SPORT1 multichannel rx compand select, channels 31 - 0 */ #define MR1CS1 0x1e9 /* SPORT1 multichannel rx select, channels 63 - 32 */ #define MR1CCS1 0x1ea /* SPORT1 multichannel rx compand select, channels 63 - 32 */ #define MR1CS2 0x1eb /* SPORT1 multichannel rx select, channels 95 - 64 */ #define MR1CCS2 0x1ec /* SPORT1 multichannel rx compand select, channels 95 - 64 */ #define MR1CS3 0x1ed /* SPORT1 multichannel rx select, channels 127 - 96 */ #define MR1CCS3 0x1ee /* SPORT1 multichannel rx compand select, channels 127 - 96 */ /* SPORT3 - MCM Transmit (Works in pair with SPORT1) #define MT3CS0 0x1f7 /* SPORT3 multichannel tx #define MT3CCS0 0x1f8 /* SPORT3 multichannel tx #define MT3CS1 0x1f9 /* SPORT3 multichannel tx #define MT3CCS1 0x1fa /* SPORT3 multichannel tx #define MT3CS2 0x1fb /* SPORT3 multichannel tx #define MT3CCS2 0x1fc /* SPORT3 multichannel tx #define MT3CS3 0x1fd /* SPORT3 multichannel tx #define MT3CCS3 0x1fe /* SPORT3 multichannel tx #define SP13MCTL */ select, compand select, compand select, compand select, compand

channels 31 - 0 */ select, channels 31 - 0 */ channels 63 - 32 */ select, channels 63 - 32 */ channels 95 - 64 */ select, channels 95 - 64 */ channels 127 - 96 */ select, channels 127 - 96 */

0x1ff /* SPORTs 1 & 3 Multichannel Control Register */

/*------ DMA Parameter Register Assignments - New Naming Conventions -------*/ /* DMA Channel 0 - Serial Port 0, A channel data */ #define II0A 0x60 /* Internal DMA0 memory address */ #define IM0A 0x61 /* Internal DMA0 memory access modifier */ #define C0A 0x62 /* Contains number of DMA0 transfers remaining */ #define CP0A 0x63 /* Points to next DMA0 parameters */ #define GP0A 0x64 /* DMA0 General purpose */ /* DMA Channel 1 - Serial Port 0, B channel data */ #define II0B 0x80 /* Internal DMA1 memory address

*/

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Registers

#define #define #define #define

IM0B C0B CP0B GP0B

0x81 0x82 0x83 0x84

/* /* /* /*

Internal DMA1 memory access modifier */ Contains number of DMA1 transfers remaining */ Points to next DMA1 parameters */ DMA1 General purpose */

/* DMA Channel 2 - Serial Port 1, A channel data */ #define II1A 0x68 /* Internal DMA2 memory address */ #define IM1A 0x69 /* Internal DMA2 memory access modifier */ #define C1A 0x6a /* Contains number of DMA2 transfers remaining */ #define CP1A 0x6b /* Points to next DMA2 parameters */ #define GP1A 0x6c /* DMA2 General purpose */ /* DMA Channel 3 - Serial Port 1, B channel data */ #define II1B 0x88 /* Internal DMA3 memory address */ #define IM1B 0x89 /* Internal DMA3 memory access modifier */ #define C1B 0x8a /* Contains number of DMA3 transfers remaining */ #define CP1B 0x8b /* Points to next DMA3 parameters */ #define GP1B 0x8c /* DMA3 General purpose */ /* DMA Channel 4 - Serial Port 2, A channel data */ #define II2A 0x70 /* Internal DMA4 memory address */ #define IM2A 0x71 /* Internal DMA4 memory access modifier */ #define C2A 0x72 /* Contains number of DMA4 transfers remaining */ #define CP2A 0x73 /* Points to next DMA4 parameters */ #define GP2A 0x74 /* DMA4 General purpose */ /* DMA Channel 5 - Serial Port 2, B channel data */ #define II2B 0x90 /* Internal DMA5 memory address */ #define IM2B 0x91 /* Internal DMA5 memory access modifier */ #define C2B 0x92 /* Contains number of DMA5 transfers remaining */ #define CP2B 0x93 /* Points to next DMA5 parameters */ #define GP2B 0x94 /* DMA5 General purpose */ /* DMA Channel 6 - Serial Port 3, A channel data */ #define II3A 0x78 /* Internal DMA6 memory address */ #define IM3A 0x79 /* Internal DMA6 memory access modifier */ #define C3A 0x7a /* Contains number of DMA6 transfers remaining */ #define CP3A 0x7b /* Points to next DMA6 parameters */ #define GP3A 0x7c /* DMA6 General purpose */ /* DMA Channel 7 - Serial Port 3, B channel data */ #define II3B 0x98 /* Internal DMA7 memory address */ #define IM3B 0x99 /* Internal DMA7 memory access modifier #define C3B 0x9a /* Contains number of DMA7 transfers remaining #define CP3B 0x9b /* Points to next DMA7 parameters */ #define GP3B 0x9c /* DMA7 General purpose */ /* DMA Channel 8 - Link #define IILB0 0x30 #define IMLB0 0x31 #define CLB0 0x32 #define CPLB0 0x33 #define GPLB0 0x34 /* DMA Channel 8 - SPI #define IISRX 0x30 #define IMSRX 0x31 #define CSRX 0x32 #define GPSRX 0x34 /* DMA Channel 9 - Link #define IILB1 0x38 #define IMLB1 0x39 #define CLB1 0x3a #define CPLB1 0x3b #define GPLB1 0x3c

*/ */

Buffer 0 (or SPI Receive) */ /* Internal DMA8 memory address */ /* Internal DMA8 memory access modifier */ /* Contains number of DMA8 transfers remaining */ /* Points to next DMA8 parameters */ /* DMA8 General purpose */ Receive (or Link Buffer 0) - No DMA Chain Pointer reg */ /* Internal DMA8 memory address */ /* Internal DMA8 memory access modifier */ /* Contains number of DMA8 transfers remaining */ /* DMA8 General purpose */ Buffer 1 (or SPI Transmit) */ /* Internal DMA9 memory address */ /* Internal DMA9 memory access modifier */ /* Contains number of DMA9 transfers remaining */ /* Points to next DMA9 parameters */ /* DMA9 General purpose */

/* DMA Channel 9 - SPI Transmit (or Link Buffer 1) - No DMA Chain Pointer reg */ #define IISTX 0x38 /* Internal DMA9 memory address */

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Register and Bit #Defines (def21161.h)

#define IMSTX #define CSTX #define GPSTX

0x39 0x3a 0x3c

/* Internal DMA9 memory access modifier */ /* Contains number of DMA9 transfers remainnig */ /* DMA9 General purpose */

/* DMA Channel 10 - External Port FIFO Buffer 0 */ #define IIEP0 0x40 /* Internal DMA10 memory address */ #define IMEP0 0x41 /* Internal DMA10 memory access modifier */ #define CEP0 0x42 /* Contains number of DMA10 transfers remaining */ #define CPEP0 0x43 /* Points to next DMA10 parameters */ #define GPEP0 0x44 /* DMA10 General purpose */ #define EIEP0 0x45 /* External DMA10 address */ #define EMEP0 0x46 /* External DMA10 address modifier */ #define ECEP0 0x47 /* External DMA10 counter */ /* DMA Channel 11 - External Port FIFO Buffer 1 */ #define IIEP1 0x48 /* Internal DMA11 memory address */ #define IMEP1 0x49 /* Internal DMA11 memory access modifier */ #define CEP1 0x4a /* Contains number of DMA11 transfers remaining */ #define CPEP1 0x4b /* Points to next DMA11 parameters */ #define GPEP1 0x4c /* DMA11 General purpose */ #define EIEP1 0x4d /* External DMA11 address */ #define EMEP1 0x4e /* External DMA11 address modifier */ #define ECEP1 0x4f /* External DMA counter */ /* DMA Channel 12 - External Port FIFO Buffer 2 */ #define IIEP2 0x50 /* Internal DMA12 memory address */ #define IMEP2 0x51 /* Internal DMA12 memory access modifier */ #define CEP2 0x52 /* Contains number of DMA12 transfers remaining */ #define CPEP2 0x53 /* Points to next DMA12 parameters */ #define GPEP2 0x54 /* DMA12 General purpose */ #define EIEP2 0x55 /* External DMA12 address */ #define EMEP2 0x56 /* External DMA12 address modifier */ #define ECEP2 0x57 /* External DMA12 counter */ /* DMA Channel 13 - External Port FIFO Buffer 3 */ #define IIEP3 0x58 /* Internal DMA13 memory address */ #define IMEP3 0x59 /* Internal DMA13 memory access modifier */ #define CEP3 0x5a /* Contains number of DMA13 transfers remaining */ #define CPEP3 0x5b /* Points to next DMA13 parameters */ #define GPEP3 0x5c /* DMA13 General purpose */ #define EIEP3 0x5d /* External DMA13 address */ #define EMEP3 0x5e /* External DMA13 address modifier */ #define ECEP3 0x5f /* External DMA13 counter */

/*---- DMA Parameter Register Assignments - Old Legacy ADSP-21160 Naming Conventions ---- */ /* NOTE: For backwards compatibility, we can retain the old DMA parameter register names used in the ADSP-21160. However, the naming conventions used for DMA channels of the ADSP-21160 do not necessarily correspond to the actual DMA channel priority assigment for the ADSP-21160 Ex) DMA Channel 4 IOP addresses on the ADSP-21160 are now DMA channel 8 on the ADSP-21161 DMA Channel 5 IOP addresses on the ADSP-21160 are now DMA channel 9 on the ADSP-21161 To clear any confusion, we recommend using the new IOP naming conventions for the DMA parameter registers as defined above */ #define #define #define #define #define #define #define #define #define #define II0 IM0 C0 CP0 GP0 II1 IM1 C1 CP1 GP1 0x60 0x61 0x62 0x63 0x64 0x68 0x69 0x6a 0x6b 0x6c /* /* /* /* /* /* /* /* /* /* Internal DMA0 memory address */ Internal DMA0 memory access modifier Contains number of DMA0 transfers remaining Points to next DMA0 parameters */ DMA0 General purpose */ Internal DMA1 memory address */ Internal DMA1 memory access modifier Contains number of DMA1 transfers remaining Points to next DMA1 parameters */ DMA1 General purpose */

*/ */

*/ */

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Registers

#define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define

II2 IM2 C2 CP2 GP2 II3 IM3 C3 CP3 GP3 II6 IM6 C6 CP6 GP6 II7 IM7 C7 CP7 GP7 II8 IM8 C8 CP8 GP8 II9 IM9 C9 CP9 GP9 II4 IM4 C4 CP4 GP4 II5 IM5 C5 CP5 GP5 II10 IM10 C10 CP10 GP10 EI10 EM10 EC10 II11 IM11 C11 CP11 GP11 EI11 EM11 EC11

0x70 0x71 0x72 0x73 0x74 0x78 0x79 0x7a 0x7b 0x7c 0x80 0x81 0x82 0x83 0x84 0x88 0x89 0x8a 0x8b 0x8c 0x90 0x91 0x92 0x93 0x94 0x98 0x99 0x9a 0x9b 0x9c 0x30 0x31 0x32 0x33 0x34 0x38 0x39 0x3a 0x3b 0x3c 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52

/* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /*

Internal DMA2 memory address */ Internal DMA2 memory access modifier Contains number of DMA2 transfers remaining Points to next DMA2 parameters */ DMA2 General purpose */ Internal DMA3 memory address */ Internal DMA3 memory access modifier Contains number of DMA3 transfers remaining Points to next DMA3 parameters */ DMA3 General purpose */ Internal DMA6 memory address */ Internal DMA6 memory access modifier Contains number of DMA6 transfers remaining Points to next DMA6 parameters */ DMA6 General purpose */ Internal DMA7 memory address */ Internal DMA7 memory access modifier Contains number of DMA7 transfers remaining Points to next DMA7 parameters */ DMA7 General purpose */ Internal DMA8 memory address */ Internal DMA8 memory access modifier Contains number of DMA8 transfers remaining Points to next DMA8 parameters */ DMA8 General Purpose */ Internal DMA9 memory address */ Internal DMA9 memory access modifier Contains number of DMA9 transfers remaining Points to next DMA9 parameters */ DMA9 General purpose */ Internal DMA4 memory address */ Internal DMA4 memory access modifier Contains number of DMA4 transfers remaining Points to next DMA4 parameters */ DMA4 General purpose */ Internal DMA5 memory address */ Internal DMA5 memory access modifier Contains number of DMA5 transfers remaining Points to next DMA5 parameters */ DMA5 General purpose */ Internal DMA10 memory address */ Internal DMA10 memory access modifier Contains number of DMA10 transfers remaining Points to next DMA10 parameters */ DMA10 General purpose */ External DMA10 address */ External DMA10 address modifier */ External DMA10 counter */ Internal DMA11 memory address */ Internal DMA11 memory access modifier Contains number of DMA11 transfers remaining Points to next DMA11 parameters */ DMA11 General purpose */ External DMA11 address */ External DMA11 address modifier */ External DMA counter */

*/ */

*/ */

*/ */

*/ */

*/ */

*/ */

*/ */

*/ */

*/ */

*/ */

#define II12 #define IM12 #define C12

/* Internal DMA12 memory address */ /* Internal DMA12 memory access modifier /* Contains number of DMA12 transfers remaining

*/ */

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Register and Bit #Defines (def21161.h)

#define #define #define #define #define #define #define #define #define #define #define #define #define

CP12 GP12 EI12 EM12 EC12 II13 IM13 C13 CP13 GP13 EI13 EM13 EC13

0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f

/* /* /* /* /* /* /* /* /* /* /* /* /*

Points to next DMA12 parameters DMA12 General purpose External DMA12 address External DMA12 address modifier External DMA12 counter

*/ */ */ */ */

Internal DMA13 memory address */ Internal DMA13 memory access modifier Contains number of DMA13 transfers remaining Points to next DMA13 parameters */ DMA13 General purpose */ External DMA13 address */ External DMA13 address modifier */ External DMA13 counter */

*/ */

/* Emulation/Breakpoint Registers (remapped from UREG space) */ /* NOTES: - These registers are ONLY accessible by the core - It is *highly* recommended that these facilities be accessed only through the ADI emulator routines */ /* Core Emulation HWBD Registers */ #define PSA1S 0xa0 /* Instruction address start #1 #define PSA1E 0xa1 /* Instruction address end #1 #define PSA2S 0xa2 /* Instruction address start #2 #define PSA2E 0xa3 /* Instruction address end #2 #define PSA3S 0xa4 /* Instruction address start #3 #define PSA3E 0xa5 /* Instruction address end #3 #define PSA4S 0xa6 /* Instruction address start #4 #define PSA4E 0xa7 /* Instruction address end #4 #define PMDAS 0xa8 /* Program Data address start #define PMDAE 0xa9 /* Program Data address end #define DMA1S 0xaa /* Data address start #1 #define DMA1E 0xab /* Data address end #1 #define DMA2S 0xac /* Data address start #2 #define DMA2E 0xad /* Data address end #2 #define EMUN 0xae /* hwbp hit-count register /* IOP Emulation HWBP Bounds Registers */ #define IOAS 0xb0 /* IOA Upper Bounds #define IOAE 0xb1 /* IOA Lower Bounds #define EPAS 0xb2 /* EPA Upper Bounds #define EPAE 0xb3 /* EPA Lower Bounds

*/ */ */ */ */ */ */ */ */ */ */ */ */ */ */

Register Register Register Register

*/ */ */ */

/*----------------------------------------------------------------------------*/ /* */ /* IOP Control/Status Register Bit Definitions */ /* */ /*----------------------------------------------------------------------------*/ /* SYSCON Register */ #define SRST 0x00000001 #define BSO 0x00000002 #define IIVT 0x00000004 #define IWT 0x00000008 #define HBW32 0x00000000 #define HBW16 0x00000010 #define HBW8 0x00000020 #define HMSWF 0x00000080 #define HPFLSH 0x00000100 #define IMDW0X 0x00000200 #define IMDW1X 0x00000400 #define ADREDY 0x00000800 #define BHD 0x00010000 #define EBPR00 0x00000000 #define EBPR01 0x00020000 #define EBPR10 0x00040000

/* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /*

Soft Reset */ Boot Select Override */ Internal Interrupt Vector Table */ Instruction word transfer (0 = data, 1 = inst) */ Host bus width: 32 */ Host bus width: 16 */ Host bus width: 8 */ Host packing order (0 = LSW first, 1 = MSW) */ Host pack flush */ Internal memory block 0, extended data (40 bit) */ Internal memory block 1, extended data (40 bit) */ Active Drive Ready */ Buffer Hand Disable */ External bus priority: Even */ External bus priority: Core has priority */ External bus priority: IO has priority */

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Registers

#define #define #define #define #define #define

DCPR LDCPR PRROT COD IPACK0 IPACK1

0x00080000 0x00100000 0x00200000 0x00400000 0x40000000 0x80000000

/* /* /* /* /* /*

Select rotating access priority on DMA10 - DMA13*/ Select rotating access priority on DMA8 - DMA9 */ Select rotating prio between LPort and EPort */ Clock Out Disable */ External instruction execution packing mode bit 0 */ External instruction execution packing mode bit 1 */

/* SYSTAT Register */ #define HSTM 0x00000001 #define BSYN 0x00000002 #define CRBM 0x00000070 #define IDC 0x00000700 #define VIPD 0x00002000 #define CRAT 0x00070000 #define SSWPD 0x00100000 #define SWPD 0x00200000 #define HPS 0x01c00000

/* /* /* /* /* /* /* /* /*

Host is the Bus Master */ Bus arbitration logic is synchronized */ Current ADSP211xx Bus Master */ ADSP211xx ID Code */ Vector interrupt pending (1 = pending) */ CLK_CFG(3-0), Core:CLKIN clock ratio */ Sync slave write pending... SSWPD bit added for 21161 */ Any (sync + Async) slave write pending */ Host pack status... HPS modified for 21161 */

/* MODE2_SHDW Register - IOP register adrees 0x11 */ /* bits 31-30, 27-25 are Processor ID[4:0], read only, value: 01010 bits 29-28 are silicon revision[1:0], read only, value: 01 These former MODE2 register bitfields (only) are now routed to the MODE2 Shadow register (IOP register 0x11). Bits 25-31 now reserved in MODE2. */ #define PID20 0x0E000000 /* PID[2:0] Processor Identification (read-only)*/ #define SIREV 0x30000000 /* Silicon Revision (read-only) */ #define PID43 0xC0000000 /* PID[4:3] Processor Identification (read-only) */

/* WAIT Register */ /* generic WAIT bitfields */ #define EB0AM 0x00000003 /* External Bank 0 Access Mode */ #define EB0WS 0x0000001C /* External Bank 0 Waitstate Configuration */ #define EB1AM 0x00000060 /* External Bank 1 Access Mode */ #define EB1WS 0x00000380 /* External Bank 1 Waitstate Configuration */ #define EB2AM 0x00000C00 /* External Bank 1 Access Mode */ #define EB2WS 0x00007000 /* External Bank 2 Waitstate Configuration */ #define EB3AM 0x00018000 /* External Bank 1 Access Mode */ #define EB3WS 0x000E0000 /* External Bank 3 Waitstate Configuration */ #define RBAM 0x00300000 /* ROM Boot Access Mode */ #define RBWS 0x01C00000 /* ROM Boot Waitstate Configuration */ #define HIDMA 0x80000000 /* Single idle cycle for DMA handshake */ /* specific wait access mode settings */ #define EB0A0 0x00000000 /* Ext Bank 0 Async, internal AND external ACK */ #define EB0S1 0x00000001 /* Ext Bank 0 Sync, 2-cycle reads, 1-cycle writes */ #define EB0S2 0x00000002 /* Ext Bank 0 Sync, 2-cycle reads, 2-cycle writes */ #define EB1A0 0x00000000 /* Ext Bank 1 Async, internal AND external ACK */ #define EB1S1 0x00000020 /* Ext Bank 1 Sync, 2-cycle reads, 1-cycle writes */ #define EB1S2 0x00000040 /* Ext Bank 1 Sync, 2-cycle reads, 2-cycle writes */ #define EB2A0 0x00000000 /* Ext Bank 2 Async, internal AND external ACK */ #define EB2S1 0x00000400 /* Ext Bank 2 Sync, 2-cycle reads, 1-cycle writes */ #define EB2S2 0x00000800 /* Ext Bank 2 Sync, 2-cycle reads, 2-cycle writes */ #define EB3A0 0x00000000 /* Ext Bank 3 Async, internal AND external ACK */ #define EB3S1 0x00008000 /* Ext Bank 3 Sync, 2-cycle reads, 1-cycle writes */ #define EB3S2 0x00010000 /* Ext Bank 3 Sync, 2-cycle reads, 2-cycle writes */ #define RBWA0 0x00000000 /* ROM boot: Async, internal AND external ACK */ #define RBWS1 0x00100000 /* ROM boot: Sync, 2-cycle reads, 1-cycle writes */ #define RBWS2 0x00200000 /* ROM boot: Sync, 2-cycle reads, 2-cycle writes */ /* individual waitstate combinations */ #define EB0WS0 0x00000000 /* External Bank 0: 0 waitstates, no hold cycle */ #define EB0WS1 0x00000004 /* External Bank 0: 1 waitstates, no hold cycle */ #define EB0WS2 0x00000008 /* External Bank 0: 2 waitstates, hold cycle */ #define EB0WS3 0x0000000C /* External Bank 0: 3 waitstates, hold cycle */ #define EB0WS4 0x00000010 /* External Bank 0: 4 waitstates, hold cycle */ #define EB0WS5 0x00000014 /* External Bank 0: 5 waitstates, hold cycle */ #define EB0WS6 0x00000018 /* External Bank 0: 6 waitstates, hold cycle */ #define EB0WS7 0x0000001C /* External Bank 0: 7 waitstates, hold cycle */ #define EB1WS0 0x00000000 /* External Bank 1: 0 waitstates, no hold cycle */

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Register and Bit #Defines (def21161.h)

#define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define

EB1WS1 EB1WS2 EB1WS3 EB1WS4 EB1WS5 EB1WS6 EB1WS7 EB2WS0 EB2WS1 EB2WS2 EB2WS3 EB2WS4 EB2WS5 EB2WS6 EB2WS7 EB3WS0 EB3WS1 EB3WS2 EB3WS3 EB3WS4 EB3WS5 EB3WS6 EB3WS7 RBWST0 RBWST1 RBWST2 RBWST3 RBWST4 RBWST5 RBWST6 RBWST7

0x00000080 0x00000100 0x00000180 0x00000200 0x00000280 0x00000300 0x00000380 0x00000000 0x00001000 0x00002000 0x00003000 0x00004000 0x00005000 0x00006000 0x00007000 0x00000000 0x00020000 0x00040000 0x00060000 0x00080000 0x000A0000 0x000C0000 0x000E0000 0x00000000 0x00400000 0x00800000 0x00C00000 0x01000000 0x01400000 0x01800000 0x01C00000

/* External Bank 1: 1 waitstates, no hold cycle /* External Bank 1: 2 waitstates, hold cycle /* External Bank 1: 3 waitstates, hold cycle /* External Bank 1: 4 waitstates, hold cycle /* External Bank 1: 5 waitstates, hold cycle /* External Bank 1: 6 waitstates, hold cycle /* External Bank 1: 7 waitstates, hold cycle /* External Bank 2: 0 waitstates, no hold cycle /* External Bank 2: 1 waitstates, no hold cycle /* External Bank 2: 2 waitstates, hold cycle /* External Bank 2: 3 waitstates, hold cycle /* External Bank 2: 4 waitstates, hold cycle /* External Bank 2: 5 waitstates, hold cycle /* External Bank 2: 6 waitstates, hold cycle /* External Bank 2: 7 waitstates, hold cycle /* External Bank 3: 0 waitstates, no hold cycle /* External Bank 3: 1 waitstates, no hold cycle /* External Bank 3: 2 waitstates, hold cycle /* External Bank 3: 3 waitstates, hold cycle /* External Bank 3: 4 waitstates, hold cycle /* External Bank 3: 5 waitstates, hold cycle /* External Bank 3: 6 waitstates, hold cycle /* External Bank 3: 7 waitstates, hold cycle /* ROM boot wait state 0, no hold cycle */ /* ROM boot wait state 1, no hold cycle */ /* ROM boot wait state 2, hold cycle */ /* ROM boot wait state 3, hold cycle */ /* ROM boot wait state 4, hold cycle */ /* ROM boot wait state 5, hold cycle */ /* ROM boot wait state 6, hold cycle */ /* ROM boot wait state 7, hold cycle */

*/ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */

/* DMAC10, DMAC11, DMAC12, DMAC13 Register Bitfield Definitions */ #define DEN 0x00000001/* External Port DMA Enable */ #define CHEN 0x00000002/* External Port DMA Chaining Enable */ #define TRAN 0x00000004/* External Port EPBx Transmit/Receive Select */ #define DTYPE 0x00000020/* EPBx FIFO Buffer Data Type Select */ #define PMODE1 0x00000040/* EPBx FIFO Pack Modes.16-bit ext to 32/64-bit int packing */ #define PMODE2 0x00000080/* 16-bit external to 48-bit internal packing */ #define PMODE3 0x000000C0/* 32-bit external to 48-bit internal packing */ #define PMODE4 0x00000100/* No Pack Mode-32-bit external to 32/64-bit internal packing */ #define PMODE5 0x00000140/* 8-bit external to 48-bit internal packing */ #define PMODE6 0x00000180/* 8-bit external to 32/64-bit internal packing */ #define MSWF 0x00000200/* Most Significant Word First During Packing */ #define MASTER 0x00000400/* EPBx DMA Master Mode Enable */ #define HSHAKE 0x00000800/* EPBx DMA Handshake Mode Enable */ #define INTIO 0x00001000/* Single Word Interrupts for EPBx FIFO Buffers */ #define EXTERN 0x00002000/* External Handshake Mode Enable */ #define FLSH 0x00004000/* Flush EPBx FIFO Buffers and Status */ #define PRIO 0x00008000/* External Port Bus Priority Access */ #define FS 0x00030000/* External Port FIFO Buffer Status (read-only) */ #define INT32 0x00040000/* Internal Memory 32-bit Transfer Select */ #define MAXBL0 0x00000000/* Maximum Burst Length Select Disabled */ #define MAXBL1 0x00080000/* Bit 19 set; Maximum Burst Length Limit of 4 Enabled*/ #define PS 0x00E00000/* Ext. Port EPBx FIFO Buffer Pack Status (read-only)*/ /* DMASTAT Register (read-only) */ #define DMA0ST 0x00000001 /* DMA channel 0 #define DMA2ST 0x00000002 /* DMA channel 2 #define DMA4ST 0x00000004 /* DMA channel 4 #define DMA6ST 0x00000008 /* DMA channel 6 #define DMA8ST 0x00000010 /* DMA channel 8 #define DMA9ST 0x00000020 /* DMA channel 9 #define DMA1ST 0x00000040 /* DMA channel 1 #define DMA3ST 0x00000080 /* DMA channel 3 #define DMA5ST 0x00000100 /* DMA channel 5 #define DMA7ST 0x00000200 /* DMA channel 7 #define DMA10ST 0x00000400/* DMA channel 10

(RX0A/TX0A) Active Status (RX1A/TX1A) Active Status (RX2A/TX2A) Active Status (RX3A/TX3A) Active Status (LBUF0) Active Status */ (LBUF1) Active Status */ (RX0B/TX0B) Active Status (RX1B/TX1B) Active Status (RX2B/TX2B) Active Status (RX3B/TX3B) Active Status (EPB0) Active Status */

*/ */ */ */

*/ */ */ */

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Registers

#define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define

DMA11ST 0x00000800 /* DMA channel 11 (EPB1) Active Status */ DMA12ST 0x00001000 /* DMA channel 12 (EPB2) Active Status */ DMA13ST 0x00002000 /* DMA channel 13 (EPB3) Active Status */ DMA0CHST 0x00010000/* DMA channel 0 (RX0A/TX0A) Chaining Status DMA2CHST 0x00020000/* DMA channel 2 (RX1A/TX1A) Chaining Status DMA4CHST 0x00040000/* DMA channel 4 (RX2A/TX2A) Chaining Status DMA6CHST 0x00080000/* DMA channel 6 (RX3A/TX3A) Chaining Status DMA8CHST 0x00100000/* DMA channel 8 (LBUF0) Chaining Status */ DMA9CHST 0x00200000/* DMA channel 9 (LBUF1) Chaining Status */ DMA1CHST 0x00400000/* DMA channel 1 (RX0B/TX0B) Chaining Status DMA3CHST 0x00800000/* DMA channel 3 (RX1B/TX1B) Chaining Status DMA5CHST 0x01000000/* DMA channel 5 (RX2B/TX2B) Chaining Status DMA7CHST 0x02000000/* DMA channel 7 (RX3B/TX3B) Chaining Status DMA10CHST 0x04000000/* DMA channel 10 (EPB0) Chaining Status */ DMA11CHST 0x08000000/* DMA channel 11 (EPB1) Chaining Status */ DMA12CHST 0x10000000/* DMA channel 12 (EPB2) Chaining Status */ DMA13CHST 0x20000000/* DMA channel 13 (EPB3) Chaining Status */

*/ */ */ */

*/ */ */ */

/* SDCTL - SDRAM Control Register bit definitions */ #define SDCL1 0x00000001/* SDCL[1:0] - CAS Latency field */ #define SDCL2 0x00000002/* (delay between RD cmd and data at o/p pins) */ #define SDCL3 0x00000003/* configurable between 1 and 3 SDCLK cycles */ #define DSDCTL #define DSDCK1 #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define 0x00000004 /* disable SDCLK0, /RAS, /CAS & SDCKE pins 0x00000008/* disable SDCLK1 pin */ SDTRAS0 SDTRAS1 SDTRAS2 SDTRAS3 SDTRAS4 SDTRAS5 SDTRAS6 SDTRAS7 SDTRAS8 SDTRAS9 SDTRAS10 SDTRAS11 SDTRAS12 SDTRAS13 SDTRAS14 SDTRAS15 SDTRP0 SDTRP1 SDTRP2 SDTRP3 SDTRP4 SDTRP5 SDTRP6 SDTRP7 SDPM SDPGS256 SDPGS512 SDPGS1024 SDPGS2048 SDPSS SDSRF SDEM0 SDEM1 SDEM2 SDEM3 SDBN2 SDBN4 SDCKRx1 SDCKR_DIV2 SDBUF */

0x00000000/* SDTRAS[3:0] - tRAS spec (active command delay)*/ 0x00000010 /* (required delay between a Bank Activate */ 0x00000020/* command to a Precharge command) */ 0x00000030 /* configurable between 0 to 15 SDCLK cycles */ 0x00000040 0x00000050 0x00000060 0x00000070 0x00000080 0x00000090 0x000000a0 0x000000b0 0x000000c0 0x000000d0 0x000000e0 0x000000f0 0x00000000/* SDTRP[2:0] - tRP spec (precharge delay) */ 0x00000100/* (required delay between a precharge command */ 0x00000200/* to a Bank Activate command) */ 0x00000300 /* configurable between 1 to 7 cycles */ 0x00000400 0x00000500 0x00000600 0x00000700 SDRAM power-up mode bit */ SDRAM Page Size - 256 words */ SDRAM Page Size - 512 words */ SDRAM Page Size - 1024 words */ SDRAM Page Size - 2048 words */ SDRAM power-up sequence start command */ Self refresh command */ Memory Bank 0 SDRAM Enable */ Memory Bank 1 SDRAM Enable */ Memory Bank 2 SDRAM Enable */ Memory Bank 3 SDRAM Enable */ SDRAM contains 2 memory banks */ SDRAM contains 4 memory banks */ 1:1 (full) SDCLK-to-CCLK (core-clock) ratio */ 1:2 (one-half) SDCLK-to-CCLK ratio */ Pipeline (reg. buf) option */

0x00000800/* 0x00000000/* 0x00001000/* 0x00002000/* 0x00003000/* 0x00004000/* 0x00008000/* 0x00010000/* 0x00020000/* 0x00040000/* 0x00080000/* 0x00000000/* 0x00100000/* 0x00200000/* 0x00000000/* 0x00800000/*

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Register and Bit #Defines (def21161.h)

#define #define #define #define #define #define #define #define

SDTRCD0 SDTRCD1 SDTRCD2 SDTRCD3 SDTRCD4 SDTRCD5 SDTRCD6 SDTRCD7

0x00000000/* SDTRCD[2:0] - tRCD spec. (RAS-to-CAS delay)*/ 0x01000000/* (required delay between a Bank Activate cmd */ 0x02000000/* and the start of the first RD or WR) */ 0x03000000/* configurable between 1 to 7 SDCLK cycles*/ 0x04000000 0x05000000 0x06000000 0x07000000

/* IOFLAG - programmable I/O status macro definitions */ #define FLG4 0x00000001 /* FLAG4 value (Low = '0', High = '1') */ #define FLG5 0x00000002 /* FLAG5 value (Low = '0', High = '1') */ #define FLG6 0x00000004 /* FLAG6 value (Low = '0', High = '1') */ #define FLG7 0x00000008 /* FLAG7 value (Low = '0', High = '1') */ #define FLG8 0x00000010 /* FLAG8 value (Low = '0', High = '1') */ #define FLG9 0x00000020 /* FLAG9 value (Low = '0', High = '1') */ #define FLG10 0x00000040 /* FLAG10 value (Low = '0', High = '1') */ #define FLG11 0x00000080 /* FLAG11 value (Low = '0', High = '1') */ /* IOFLAG - programmable I/O control macro definitions */ #define FLG4O 0x00000100 /* FLAG4 control ('0' = flag input, '1' = flag output) */ #define FLG5O 0x00000200 /* FLAG5 control ('0' = flag input, '1' = flag output) */ #define FLG6O 0x00000400 /* FLAG6 control ('0' = flag input, '1' = flag output) */ #define FLG7O 0x00000800 /* FLAG7 control ('0' = flag input, '1' = flag output) */ #define FLG8O 0x00001000 /* FLAG8 control ('0' = flag input, '1' = flag output) */ #define FLG9O 0x00002000 /* FLAG9 control ('0' = flag input, '1' = flag output) */ #define FLG10O 0x00004000 /* FLAG10 control ('0' = flag input, '1' = flag output) */ #define FLG11O 0x00008000 /* FLAG11 control ('0' = flag input, '1' = flag output) */

/*SPICTL register */ #define SPIEN 0x00000001 #define SPRINT 0x00000002 #define SPTINT 0x00000004 #define MS 0x00000008 #define CP 0x00000010 #define CPHASE 0x00000020 #define DF 0x00000040 #define WL8 0x00000000 #define WL16 0x00000080 #define WL32 0x00000180 #define BAUDR1 0x00000200 #define BAUDR2 0x00000400 #define BAUDR3 0x00000600 #define BAUDR4 0x00000800 #define BAUDR5 0x00000A00 #define BAUDR6 0x00000C00 #define BAUDR7 0x00000E00 #define BAUDR8 0x00001000 #define BAUDR9 0x00001200 #define BAUDR100x00001400 #define BAUDR110x00001600 #define BAUDR120x00001800 #define BAUDR130x00001A00 #define BAUDR140x00001C00 #define BAUDR150x00001E00 #define TDMAEN 0x00002000 #define PSSE 0x00004000 #define FLS0 0x00008000 #define FLS1 0x00010000 #define FLS2 0x00020000 #define FLS3 0x00040000 #define SMLS 0x00080000 #define NSMLS 0x00080000 #define DCPH0 0x00100000 #define DMISO 0x02000000 #define OPD 0x04000000 #define RDMAEN 0x08000000

/* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /*

SPI system enable */ SPIRX buffer interrupt enable */ SPITX buffer interrupt enable */ Master/Slave Mode bit */ SPICLK Polarity */ SPICLK Phase */ Data Format */ SPI Word Length = 8 */ SPI Word Length = 16 */ SPI Word Length = 32 */ BAUDRATE = CCLK / 2**(2 + 1) = CCLK/8 */ BAUDRATE = CCLK / 2**(2 + 2) = CCLK/16 */ BAUDRATE = CCLK / 2**(2 + 3) = CCLK/32 */ BAUDRATE = CCLK / 2**(2 + 4) = CCLK/64 */ BAUDRATE = CCLK / 2**(2 + 5) = CCLK/128 */ BAUDRATE = CCLK / 2**(2 + 6) = CCLK/512 */ BAUDRATE = CCLK / 2**(2 + 7) = CCLK/1024 */ BAUDRATE = CCLK / 2**(2 + 8) = CCLK/2048 */ BAUDRATE = CCLK / 2**(2 + 9) = CCLK/4096 */ BAUDRATE = CCLK / 2**(2 + 10) = CCLK/8192 */ BAUDRATE = CCLK / 2**(2 + 11) = CCLK/16384 */ BAUDRATE = CCLK / 2**(2 + 12) = CCLK/32768 */ BAUDRATE = CCLK / 2**(2 + 13) = CCLK/65536 */ BAUDRATE = CCLK / 2**(2 + 14) = CCLK/131072 */ BAUDRATE = CCLK / 2**(2 + 15) = CCLK/262144 */ SPITX transmit buffer DMA enable, DMA channel 9 */ Programmable slave device select */ FLAG0 slave device select enable */ FLAG1 slave device select enable */ FLAG2 slave device select enable */ FLAG3 slave device select enable */ Seamless operation Seamless operation */ Select or deselect SPIDS~ between transfers */ Disable MISO Pin for Broadcast Mode */ Open drain output enable for data pins */ SPIRX recevie buffer DMA enable, DMA channel 8 */

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Registers

#define #define #define #define #define

PACKEN SGN SENDZ SENDLW GM

0x10000000 0x20000000 0x40000000 0x40000000 0x80000000

/* /* /* /* /*

8-to-16 Bit Packing Enable */ Sign-extend SPIRX/SPITX data */ Send zero or repeat previous data when SPITX empty */ Send zero or repeat previous data when SPITX empty */ Retrieve or discard incoming data when SPIRX full */

/* SPISTAT register */ #define SPIF 0x00000001 #define SRS 0x00000001 #define MME 0x00000002 #define TXE 0x00000004 #define TXS0 0x00000008 #define TXS1 0x00000010 #define RBSY 0x00000020 #define RXS0 0x00000040 #define RXS1 0x00000080

/* /* /* /* /* /* /* /* /*

SPI transmit or receive transfer complete (in pre 1.2 Si)*/ SPI shift register status (in 1.2 Si and above)*/ Multimaster error */ SPITX transmission error (underflow) */ TXS[0] - SPITX data buffer status */ TXS[1] - SPITX data buffer status */ SPIRX reception error (overflow) */ RXS[0] - SPIRX data buffer status */ RXS[1] - SPIRX data buffer status */

/* LCTL #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define

register - 0xcc */ L0EN 0x00000001 L0DEN 0x00000002 L0CHEN 0x00000004 L0TRAN 0x00000008 L0EXT 0x00000010 L0CLKD00x00000020 L0CLKD10x00000040 L0PDRDE0x00000100 L0DPWID0x00000200 L1EN 0x00000400 L1DEN 0x00000800 L1CHEN 0x00001000 L1TRAN 0x00002000 L1EXT 0x00004000 L1CLKD00x00008000 L1CLKD10x00010000 L1PDRDE0x00040000 L1DPWID0x00080000 A0LB 0x00100000 A1LB 0x00200000 LAB0 0x00100000 LAB1 0x00200000 L0STAT00x00400000 L0STAT10x00800000 L1STAT00x01000000 L1STAT10x02000000 LRERR0 0x04000000 LRERR1 0x08000000

/* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /*

Link buffer 0 enable */ Link buffer 0 DMA enable */ Link buffer 0 DMA chaining enable */ Link buffer 0 data direction */ Link buffer 0 extended word size */ L0CLKD[0] Link buffer 0 CCLK divide ratio */ L0CLKD[1] Link buffer 0 CCLK divide ratio */ Link Port 0 pulldown resister disable */ Link buffer 0 data path width */ Link buffer 1 enable */ Link buffer 1 DMA enable */ Link buffer 1 DMA chaining enable */ Link buffer 1 data direction */ Link buffer 1 extended word size */ L1CLKD[0] Link buffer 1 CCLK divide ratio */ L1CLKD[1] Link buffer 1 CCLK divide ratio */ Link Port 1 pulldown resister disable */ Link buffer 1 data path width */ Link Port Assignment for LBUF0 - 2106x/21160 compatibility */ Link Port Assignment for LBUF1 - 2106x/21160 compatibility */ Link Port Assignment for LBUF0 -new naming conventions */ Link Port Assignment for LBUF1 - new naming conventions */ L0STAT[0] - link buffer 0 status (read-only) */ L0STAT[1] - link buffer 0 status (read-only) */ L1STAT[0] - link buffer 1 status (read-only) */ L1STAT[1] - link buffer 1 status (read-only) */ Link Buffer 0 receive pack error status */ Link Buffer 1 receive pack error status */

/* SP02MCTL & #define MCE #define MFD0 bit */ #define MFD1 #define MFD2 #define MFD3 #define MFD4 #define MFD5 #define MFD6 #define MFD7 #define MFD8 #define MFD9 #define MFD10 #define MFD11 #define MFD12 #define MFD13 #define MFD14 #define NCH

SP13MCTL registers */ 0x00000001 /* Multichannel Mode Enable */ 0x00000000 /* no frame delay, multichannel FS pulse in same SCLK cycle as first data 0x00000002 0x00000004 0x00000006 0x00000008 0x0000000A 0x0000000C 0x0000000E 0x00000010 0x00000012 0x00000014 0x00000016 0x00000018 0x0000001A 0x0000001C 0x00000FE0 /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* multichannel mode 1 cycle frame sync delay */ multichannel mode 2 cycle frame sync delay */ multichannel mode 3 cycle frame sync delay */ multichannel mode 4 cycle frame sync delay */ multichannel mode 5 cycle frame sync delay */ multichannel mode 6 cycle frame sync delay */ multichannel mode 7 cycle frame sync delay */ multichannel mode 8 cycle frame sync delay */ multichannel mode 9 cycle frame sync delay */ multichannel mode 10 cycle frame sync delay */ multichannel mode 11 cycle frame sync delay */ multichannel mode 12 cycle frame sync delay */ multichannel mode 13 cycle frame sync delay */ multichannel mode 14 cycle frame sync delay */ Number of MCM channels - 1 */

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Register and Bit #Defines (def21161.h)

#define SPL #define CHNL

0x00001000 0x007F0000

/* SPORT 0&2 or SPORT 1&3 Internal Loopback Mode */ /* Current Channel Status (read-only) */

/* SPCTL0, SPCTL1, SPCTL2 and SPCTL3 registers */ #define SPEN_A 0x00000001/* SPORT enable primary A channel */ #define DTYPE0 0x00000000/* right justify, fill unused MSBs with 0s */ #define DTYPE1 0x00000002/* right justify, sign-extend into unused MSBs */ #define DTYPE2 0x00000004/* compand using mu law */ #define DTYPE3 0x00000006/* compand using a law */ #define SENDN 0x00000008/* MSB or LSB first */ #define SLEN3 0x00000020/* serial length 3 */ #define SLEN4 0x00000030/* serial length 4 */ #define SLEN5 0x00000040/* serial length 5 */ #define SLEN6 0x00000050/* serial length 6 */ #define SLEN7 0x00000060/* serial length 7 */ #define SLEN8 0x00000070/* serial length 8 */ #define SLEN9 0x00000080/* serial length 9 */ #define SLEN10 0x00000090/* serial length 10 */ #define SLEN11 0x000000A0/* serial length 11 */ #define SLEN12 0x000000B0/* serial length 12 */ #define SLEN13 0x000000C0/* serial length 13 */ #define SLEN14 0x000000D0/* serial length 14 */ #define SLEN15 0x000000E0/* serial length 15 */ #define SLEN16 0x000000F0/* serial length 16 */ #define SLEN17 0x00000100/* serial length 17 */ #define SLEN18 0x00000110/* serial length 18 */ #define SLEN19 0x00000120/* serial length 19 */ #define SLEN20 0x00000130/* serial length 20 */ #define SLEN21 0x00000140/* serial length 21 */ #define SLEN22 0x00000150/* serial length 22 */ #define SLEN23 0x00000160/* serial length 23 */ #define SLEN24 0x00000170/* serial length 24 */ #define SLEN25 0x00000180/* serial length 25 */ #define SLEN26 0x00000190/* serial length 26 */ #define SLEN27 0x000001A0/* serial length 27 */ #define SLEN28 0x000001B0/* serial length 28 */ #define SLEN29 0x000001C0/* serial length 29 */ #define SLEN30 0x000001D0/* serial length 30 */ #define SLEN31 0x000001E0/* serial length 31 */ #define SLEN32 0x000001F0/* serial length 32 */ #define PACK 0x00000200/* 16-to-32 data packing */ #define MSTR 0x00000400/* I2S Mode only... TX/RX is master or slave */ #define ICLK 0x00000400/* internally 1 or externally 0 generated transmit or recieve SCLKx */ #define OPMODE 0x00000800/* I2S mode enable ('1') or DSP Serial Mode/Multichannel mode ('0') */ #define CKRE 0x00001000/* Clock edge for data and frame sync sampling (rx) or driving (tx) */ #define FSR 0x00002000/* transmit or receive frame sync (FSx) required */ #define IFS 0x00004000/* internally generated transmit or receive frame sync (FSx) */ #define IRFS 0x00004000/* internally generated receive FS0 or FS1 in multichannel mode */ #define DITFS 0x00008000/* (I2S/DSP serial mode only) Data Independent tx FSx when DDIR bit=1 */ #define LFS 0x00010000/* Active Low transmit or receive frame sync (FSx) */ #define LRFS 0x00010000/* SPORT0 and SPORT1 active low TDM frame sync FS0/FS1 in MC mode */ #define LTDV 0x00010000/* (MC Mode only) SPORT2/SPORT3 tx data valid ena in TDM mode-TDV2/TDV3 alternate pin config */ #define LFIRST 0x00010000/* (I2S Mode Only) transmit left channel first 1, or right channel first 0 */ #define LAFS 0x00020000/* (DSP Serial Mode only) Late (vs early) frame sync FSx */ #define SDEN_A 0x00040000/* SPORT TXnA/RXnA DMA enable primary A channel */ #define SCHEN_A 0x00080000/* SPORT TXnA/RXnA DMA chaining enable primary A channel */ #define SDEN_B 0x00100000/* SPORT TXnB/RXnB DMA enable primary B channel */ #define SCHEN_B 0x00200000/* SPORT TXnB/RXnB DMA chaining enable primary B channel */ #define FS_BOTH 0x00400000/* (DSP Serial & I2S modes only) Issue FSx only if data is in both TXnA & TXnB regs */

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Registers

#define SPEN_B 0x01000000/* #define DDIR 0x02000000/* receiver */ #define DERR_B 0x04000000/* serial & I2S modes (read-only) */ #define DXS0_B 0x08000000/* modes read-only)*/ #define DXS1_B modes (read-only)*/ #define DERR_A I2S modes (read-only) */ #define TUVF_A (read-only, sticky)*/ #define ROVF_A (read-only, sticky)*/ #define DXS0_A modes (read-only)*/ #define DXS1_A modes (read-only)*/ #define RXS0_A (read-only)*/ #define RXS1_A (read-only)*/ #define TXS0_A (read-only)*/ #define TXS1_A (read-only) */ #endif

SPORTx secondary B channel enable */ SPORT data buffer data dirrection 1 = transmitter, 0 = SPORTx secondary B overflow/underflow error status in DSP SPORTx secondary B data buffer status in DSP Serial & I2S

0x10000000/* SPORTx secondary B data buffer status in DSP Serial & I2S 0x20000000/* SPORTx primary A over/underflow error status in DSP Serial & 0x20000000/* SPORT2/SPORT3 TX2A/TX3A underflow status in MC mode 0x20000000/* SPORT0/SPORT1 RX0A/RX1A overflow status in MC mode 0x40000000/* SPORTx primary A data buffer status in DSP serial and I2S 0x80000000/* SPORTx primary A data buffer status in DSP serial and I2S 0x40000000/* SPORT0/SPORT1 RX0A/RX1A data buffer status in MC mode 0x80000000/* SPORT0/SPORT1 RX0A/RX1A data buffer status in MC mode 0x40000000/* SPORT2/SPORT3 TX2A/TX3A data buffer status in MC mode 0x80000000/* SPORT2/SPORT3 TX2A/TX3A data buffer status in MC mode

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Register and Bit #Defines (def21161.h)

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B INTERRUPT VECTOR ADDRESSES

Table B-1 shows all ADSP-21161 processor interrupts, listed according their bit position in the IRPTL, LIRPTL, and IMASK registers. For more information, see Interrupt Latch Register (IRPTL) on page A-27 and Interrupt Mask Register (IMASK) on page A-31. Also shown is the address of the interrupt vector. Each vector is separated by four memory locations. The addresses in the vector table represent offsets from a base address. For an interrupt vector table in internal memory, the base address is 0x0004 0000. For an interrupt vector table in external memory, the base address is 0x0020 0000. The interrupt name column in Table B-1 lists a mnemonic name for each interrupt as they are defined by the def21161.h file that comes with the software development tools. For more information, see Register and Bit #Defines (def21161.h) on page A-121. Table B-1. Interrupt Vector Addresses
Register IRPTL/ IMASK, LIRPTL Bit# 0 1 2 3 4 Vector Address Interrupt Name Function

IRPTL IRPTL IRPTL IRPTL IRPTL

0x00 0x04 0x08 0x0C 0x10

EMUI RSTI IICDI SOVFI TMZHI

Emulator (read-only, non-maskable) HIGHEST PRIORITY Reset (read-only, non-maskable) Illegal Input Condition Detected Status, loop, or mode stack overflow; or PC stack full Timer=0 (high priority option)

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Table B-1. Interrupt Vector Addresses (Contd)

Register IRPTL/ IMASK, LIRPTL Bit# 5 6 7 8 9 10 11 12 13 0/16 1/17 2/18 3/19 15 16 17 18 19 20 21 22 Vector Address Interrupt Name Function

IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL LIRPTL LIRPTL LIRPTL LIRPTL LIRPTL LIRPTL IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL

0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4c 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C

VIRPTI IRQ2I IRQ1I IRQ0I SP0I SP1I SP2I SP3I LP0I LP1I SPIRI SPITI EP0I EP1I EP2I EP3I LSRQI CB7I CB15I TMZLI

Multiprocessor Vector Interrupt IRQ2 asserted IRQ1 asserted IRQ0 asserted Reserved SPORT0 DMA SPORT1 DMA SPORT2 DMA SPORT3 DMA Link Buffer 0 DMA Interrupt Link Buffer 1 DMA Interrupt SPI Receive DMA Interrupt SPI Transmit DMA Interrupt Reserved Reserved DMA Channel 10 - Ext. Port Buffer 0 DMA Channel 11 - Ext. Port Buffer 1 DMA Channel 12 - Ext. Port Buffer 2 DMA Channel 13 - Ext. Port Buffer 3 Link Port Service Request Circular Buffer 7 overflow Circular Buffer 15 overflow Timer=0 (low priority option)

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Interrupt Vector Addresses

Table B-1. Interrupt Vector Addresses (Contd)

Register IRPTL/ IMASK, LIRPTL Bit# 23 24 25 26 27 28 29 30 31 Vector Address Interrupt Name Function

IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL IRPTL

0x70 0x74 0x78 0x7C 0x80 0x84 0x88 0x8C 0x90

FIXI FLTOI FLTUI FLTII SFT0I SFT1I SFT2I SFT3I -

Fixed-point overflow Floating-point overflow exception Floating-point underflow exception Floating-point invalid exception User software interrupt 0 User software interrupt 1 User software interrupt 2 User software interrupt 3 Reserved - lowest priority

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B-4

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C NUMERIC FORMATS

The ADSP-21161 processor supports the 32-bit single-precision floating-point data format defined in the IEEE Standard 754/854. In addition, the processor supports an extended-precision version of the same format with eight additional bits in the mantissa (40 bits total). The processor also supports 32-bit fixed-point formatsfractional and integerwhich can be signed (twos-complement) or unsigned.

IEEE Single-Precision Floating-Point Data

IEEE Standard 754/854 specifies a 32-bit single-precision floating-point format, shown in Figure C-1. A number in this format consists of a sign bit s, a 24-bit significand, and an 8-bit unsigned-magnitude exponent e. For normalized numbers, the significand consists of a 23-bit fraction f and a hidden bit of 1 that is implicitly presumed to precede f22 in the significand. The binary point is presumed to lie between this hidden bit and f22. The least significant bit (LSB) of the fraction is f0; the LSB of the exponent is e0. The hidden bit effectively increases the precision of the floating-point significand to 24 bits from the 23 bits actually stored in the data format. It also insures that the significand of any number in the IEEE normalized number format is always greater than or equal to 1 and less than 2.

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IEEE Single-Precision Floating-Point Data

The unsigned exponent e can range between 1 e 254 for normal numbers in the single-precision format. This exponent is biased by +127 (254 2). To calculate the true unbiased exponent, 127 must be subtracted from e.

31 s

30 e 7

23 e 0

22 1.f 22

0 f 0

Hidden Bit

Binary Point

Figure C-1. IEEE 32-Bit Single-Precision Floating-Point The IEEE Standard also provides for several special data types in the single-precision floating-point format: An exponent value of 255 (all ones) with a nonzero fraction is a Not-A-Number (NAN). NANs are usually used as flags for data flow control, for the values of uninitialized variables, and for the results of invalid operations such as 0 * . Infinity is represented as an exponent of 255 and a zero fraction. Note that because the fraction is signed, both positive and negative Infinity can be represented. Zero is represented by a zero exponent and a zero fraction. As with Infinity, both positive Zero and negative Zero can be represented. The IEEE single-precision floating-point data types supported by the processor and their interpretations are summarized in Table C-1.

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Numeric Formats

Table C-1. IEEE Single-Precision Floating-Point Data Types

Type NAN Infinity Normal Zero Exponent 255 255 1 e 254 0 Fraction Nonzero 0 Any 0 (1)s Zero Value Undefined (1)s Infinity (1)s (1.f22-0 ) 2 e127

Extended-Precision Floating-Point
The extended-precision floating-point format is 40 bits wide, with the same 8-bit exponent as in the standard format but a 32-bit significand. This format is shown in Figure C-2. In all other respects, the extended floating-point format is the same as the IEEE standard format.

39 s

38 e 7

31 e 0

30 1.f 30 f

0 0

Hidden Bit

Binary Point

Figure C-2. 40-Bit Extended-Precision Floating-Point Format

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Short Word Floating-Point Format

Short Word Floating-Point Format

The ADSP-21161 processor supports a 16-bit floating-point data type and provides conversion instructions for it. The short float data format has an 11-bit mantissa with a four-bit exponent plus sign bit, as shown in Figure C-3. The 16-bit floating-point numbers reside in the lower 16 bits of the 32-bit floating-point field.

15 s

14 e 3

11 e 0

10 1.f 10

0 f 0

Hidden Bit

Binary Point

Figure C-3. 16-Bit Floating-Point Format

Packing for Floating-Point Data

Two shifter instructions, FPACK and FUNPACK, perform the packing and unpacking conversions between 32-bit floating-point words and 16-bit floating-point words. The FPACK instruction converts a 32-bit IEEE floating-point number to a 16-bit floating-point number. FUNPACK converts the 16-bit floating-point numbers back to 32-bit IEEE floating-point. Each instruction executes in a single cycle. The results of the FPACK and FUNPACK operations appear in Table C-2 and Table C-3. The short float type supports gradual underflow. This method sacrifices precision for dynamic range. When packing a number which would have underflowed, the exponent is set to zero and the mantissa

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Numeric Formats

(including hidden 1) is right-shifted the appropriate amount. The packed result is a denormal which can be unpacked into a normal IEEE floating-point number. During the FPACK operation, an overflow sets the SV condition and non-overflow will clear it. During the FUNPACK operation, the SV condition is cleared. The SZ and SS conditions are cleared by both instructions. Table C-2. FPACK Operations
Condition 135 < exp 120 < exp 135 Result Largest magnitude representation. Exponent is MSB of source exponent concatenated with the three LSBs of source exponent. The packed fraction is the rounded upper 11 bits of the source fraction. Exponent=0. Packed fraction is the upper bits (source exponent 110) of the source fraction prefixed by zeros and the hidden 1. The packed fraction is rounded. Packed word is all zeros.

109 < exp 120

exp < 110

exp = source exponent sign bit remains the same in all cases

Table C-3. FUNPACK Operations

Condition 0 < exp 15 Result Exponent is the 3 LSBs of the source exponent prefixed by the MSB of the source exponent and four copies of the complement of the MSB. The unpacked fraction is the source fraction with 12 zeros appended. Exponent is (120 N) where N is the number of leading zeros in the source fraction. The unpacked fraction is the remainder of the source fraction with zeros appended to pad it and the hidden 1 stripped away.

exp = 0

exp = source exponent sign bit remains the same in all cases

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C-5

Fixed-Point Formats

Fixed-Point Formats
The ADSP-21161 processor supports two 32-bit fixed-point formats: fractional and integer. In both formats, numbers can be signed (twos-complement) or unsigned. The four possible combinations are shown in Figure C-4. In the fractional format, there is an implied binary point to the left of the most significant magnitude bit. In integer format, the binary point is understood to be to the right of the LSB. Note that the sign bit is negatively weighted in a twos-complement format. ALU outputs always have the same width and data format as the inputs. The multiplier, however, produces a 64-bit product from two 32-bit inputs. If both operands are unsigned integers, the result is a 64-bit unsigned integer. If both operands are unsigned fractions, the result is a 64-bit unsigned fraction. These formats are shown in Figure C-5. If one operand is signed and the other unsigned, the result is signed. If both inputs are signed, the result is signed and automatically shifted left one bit. The LSB becomes zero and bit 62 moves into the sign bit position. Normally bit 63 and bit 62 are identical when both operands are signed. (The only exception is full-scale negative multiplied by itself.) Thus, the left shift normally removes a redundant sign bit, increasing the precision of the most significant product. Also, if the data format is fractional, a single-bit left shift renormalizes the MSP to a fractional format. The signed formats with and without left shifting are shown in Figure C-6. The multiplier has an 80-bit accumulator to allow the accumulation of 64- bit products. For more information on the multiplier and accumulator, see MultiplyAccumulator (Multiplier) on page 2-15.

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Numeric Formats

S IG N E D IN T E G E R
B IT W E IG H T

31 -2 31 2

30 30

29 2 29 2

2 2 2

1 1 2

0 0

S IG N B IT B IN A R Y P O IN T

B IT W E IG H T

31

30

S IG N E D F R A C T IO N A L 29 2 2 -2 2 -29 2

1 -30 2

0 -31

-0 -1 -2 2
S IG N B IT

B IN A R Y P O IN T

B IT W E IG H T

31 2 31

30 2 30

U N S IG N E D IN T E G E R 29 2 2 29 2 2 2

1 1 2

0 0

B IN A R Y P O IN T

B IT W E IG H T

31 2 -1

30 2 -2

U N S IG N E D F R A C TI O N A L 29 2 1 2 -3 2 -30 2 -31 2

0 -32

B IN A R Y P O IN T

Figure C-4. 32-Bit Fixed-Point Formats

ADSP-21161 SHARC Processor Hardware Reference

C-7

Fixed-Point Formats

BIT WEIGHT

63 2 63

62 2 62

UNSIGNED INTEGER 61 2 2 61 2 2 2

1 1

0 2 0

BINARY POINT

BIT WEIGHT

63
BINARY POINT

62 2 -2

UNSIGNED FRACTIONAL 61 2 1 2 -3 2 -62 2

-1

-63 -64 2

Figure C-5. 64-Bit Unsigned Fixed-Point Product

SIGNED INTEGER, NO LEFT SHIFT
BIT WEIGHT

63

62

61

2 2 2 2 2

1 1 1 2 2

0 0 0 2 2
BINARY POINT

63 30 29 62 62 -2 2 2 2 2
SIGN BIT

SIGNED FRACTIONAL, WITH LEFT SHIFT

BIT WEIGHT SIGN BIT

63

62

61 -2 2 2

2 -61 2

1 -62 2

0 -63

0 -1 -2 2
BINARY POINT

Figure C-6. 64-Bit Signed Fixed-Point Product

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G GLOSSARY

Autobuffering Unit (ABU). (See I/O processor and DMA) Arithmetic Logic Unit (ALU). This part of a processing element performs arithmetic and logic operations on fixed-point and floating-point data. Asynchronous transfers. Asynchronous host accesses of the processor. After acquiring control of the processors external bus, the host must assert the CS pin of the processor it wants to access. Auxiliary registers. (See Index Registers) Base address. The starting address of a circular buffer to which the DAG wraps around. This address is stored in a DAG Bx register. Base registers. A base (Bx) register is a Data Address Generator (DAG) register that sets up the starting address for a circular buffer. Bit-reverse addressing. The Data Address Generator (DAG) provides a bit-reversed address during a data move without reversing the stored address. Block repeat. (See Do/Until instructions in the ADSP-21160 DSP Instruction Set Reference) Block size register. (See Length Registers) Boot Memory Space. The processor supports an external boot EPROM mapped to external memory and selected with the BMS pin. The boot EPROM provides one of the methods for automatically loading a program into the internal memory of the processor after power-up or after a software reset. ADSP-21161 SHARC Processor Hardware Reference G-1

Broadcast data moves. The Data Address Generator (DAG) performs dual data moves to complementary registers in each processing element to support SIMD mode. Buffered serial port. (See Serial ports) Burst transfers. Multi-cycle synchronous transfers that contains a packet of at least two 64-bit transfers. For a master, only a DMA channel can master a burst transaction. As a slave, supports burst read transfers from internal memory, or the EPBx data buffers. Bus slave or slave mode. A processor can be a bus slave to another processor or to a host processor. The processor becomes a host bus slave when the HBG signal is returned. Bus Transition Cycle (BTC). A cycle in which control of the external bus is passed from one processor to another (in a multiprocessor system). Circular buffer addressing. The DAG uses the Ix, Mx and Lx register settings to constrain addressing to a range of addresses. This range contains data that the DAG steps through repeatedly, wrapping around to repeat stepping through the range of addresses in a circular pattern. Cluster multiprocessing. This is a multiprocessing system architecture in which the processor uses its link ports and external port for inter-processor communication. Companding (compressing/expanding). This is the process of logarithmically encoding and decoding data to minimize the number of bits that must be sent. Conditional branches. These are JUMP or CALL/return instructions whose execution is based on testing an IF condition. Conflict resolution ratio. Because the external port must arbitrate accesses over three internal buses to one external bus, there is a 3:1 conflict resolution ratio at the external port interface. This ratio plus the 2:1 or greater clock ratio between the processors internal clock and the external system G-2 ADSP-21161 SHARC Processor Hardware Reference

Glossary

clock forces systems that fetch instructions or data through the external port must tolerate at least one cycleand usually many additional cyclesof latency. DAGEN, Data address generator (See DAGs) Data Address Generator (DAG). The Data Address Generators (DAGs) provide memory addresses when data is transferred between memory and registers. Data flow multiprocessing. This is a multiprocessor system architecture in which the processor uses its link ports for inter-processor communication. Data register file. This is the set of data registers that transfer data between the data buses and the computation units. These registers also provide local storage for operands and results. Data registers (Dreg). These are registers in the PEx and PEy processing elements. These registers are hold operands for multiplier, ALU, or shifter operations and are denoted as Rx when used for fixed point operations or Fx when used for floating-point operations. Deadlock resolution. When both theprocessor subsystem and the system try to access each others bus in the same cycle, a deadlock may occur in which neither access can complete. Techniques for resolving deadlock vary with the interface: DRAM, host, or multiprocessor system. Delayed branches. These are JUMPS and CALL/return instructions with the delayed branches (DB) modifier. In delayed branches, no instruction cycles are lost in the pipeline, because the processor executes the two instructions after the branch while the pipeline fills with instructions from the new branch. Direct branches. These are JUMP or CALL/return instructions that use an absolutenot changing at runtimeaddress (such as a program label) or use a PC-relative address.

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G-3

Direct reads and writes. A direct access of the processors internal memory or I/O processor registers by another processor or by a host processor. DMA (Direct Memory Accessing). The processors I/O processor supports DMA of data between processor memory and external memory, host, or peripherals through the external, link, and serial ports. Each DMA operation transfers an entire block of data. DMA chaining. The processor supports chaining together multiple DMA sequences. In chained DMA, the I/O processor loads the next Transfer Control Block (DMA parameters) into the DMA parameter registers when the current DMA finishes and auto-initializes the next DMA sequence. DMA parameter registers. These registers function similarly to data address generator registers, setting up a memory access process. These registers include Internal Index registers ( IIx), Internal Modify registers (IMx), Count registers (Cx), Chain Pointer registers (CPx), General Purpose registers (GPx), External Index registers (EIEPx), External Modify registers (EMEPx), and External Count registers (ECEPx). DMA TCB chain loading. This is the process that the I/O processor uses for loading the TCB of the next DMA sequence into the parameter registers during chained DMA. DMACx control registers. The DMA control registers for the EPBx external port buffers: DMAC10, DMAC11, DMAC12, and DMAC13. These correspond respectively to EPB0, EPB1, EPB2, and EPB3. Edge-sensitive interrupt. The processor detects this type of interrupt if the input signal is high (inactive) on one cycle and low (active) on the next cycle when sampled on the rising edge of CLKIN. Endian format, little versus big. The processor uses big-endian format moves data starting with most-significant-bit and finishing with least significant bitin almost all instances. The two exceptions are bit order for data transfer through the serial port and word order for packing through the external port. For compatibility with little-endian (least signifi-

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Glossary

cant-first) peripherals, the processor supports both big- and little-endian bit order data transfers. Also for compatibility little-endian hosts, the processor supports both big- and little endian word order data transfers. Explicit Versus Implicit operations. In SIMD mode, identical instructions execute on the PEx and PEy computational units; the difference is the data. The data registers for PEy operations are identified (implicitly) from the PEx registers in the instruction. This implicit relation between PEx and PEy data registers corresponds to complementary register pairs. External bus. The processor extends the following signals off-chip as an external bus: DATA47-16, ADDR23-0, RD, WR, MS3-0, BMS, CLKOUT, BRST, ACK, and SBTS. External memory space. This space ranges from address 0x0200 0000 through 0x0CFF FFFF (Normal word) for Non-SDRAM and from address 0x0020 0000 through 0x0FFF FFFF (Normal word) for SDRAM. External memory space refers to the off-chip memory or memory mapped peripherals that are attached to the processors external address (ADDR23-0) and data (DATA47-16) buses. External port FIFO buffers (EPB0, EPB1, EPB2, and EPB3). The I/O processor registers used for external port DMA transfers and single-word data transfers (from other processors or from a host processor). These buffers are eight-deep FIFOs. External port. This port extends the internal address and data buses off chip, providing the processors interface to off-chip memory and peripherals. Field deposit (Fdep) instructions. These shifter instructions take a group of bits from the input register (starting at the LSB of the 32-bit integer field) and deposit the bits as directed anywhere within the result register. Field extract (Fext) instructions. These shifter extract a group of bits as directed from anywhere within the input register and place them in the result register (aligned with the LSB of the 32-bit integer field).

ADSP-21161 SHARC Processor Hardware Reference

G-5

Programmable Flag pins. These pins (FLGx) can be programmed as input or output pins using bit settings in the MODE2 register. The status of the flag pins is given in the FLAGS or IOFLAG register. General-purpose input/output pins. (See Programmable Flag pins) Flag update. The processors update to status flags occurs at the end of the cycle in which the status is generated and is available on the next cycle. Harvard architecture. A memory architectures that has separate buses for program and data storage. The two buses allow a data word and an instruction simultaneously. Hold time cycle. This is an inactive bus cycle that is automatically generates at the end of a read or write (depending on the external port access mode) to allow a longer hold time for address and data. The addressand data, if a writeremains unchanged and is driven for one cycle after the read or write strobes are deasserted. Host transition cycle (HTC). A cycle in which control of the external bus is passed from the ADSP-21161 processor to the host processor. During this cycle the processor stops driving the RD, WR, ADDR23-0, MS3-0, CLKOUT, PA, and DMAGx signals, which must then be driven by the host. I/O processor register. One of the control, status, or data buffer registers of the processors on-chip I/O processor. Idle cycle. This is an inactive bus cycle that is automatically generated (depending on the external port access mode) to avoid data bus driver conflicts. Such a conflict can occur when a device with a long output disable time continues to drive after RD is deasserted while another device begins driving on the following cycle. IDLE. An instruction that causes the processor to cease operations, holding its current state until an interrupt occurs. Then, the processor services the interrupt and continues normal execution.

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Glossary

Index registers. An index register is a Data Address Generator (DAG) register that holds an address and acts as a pointer to memory. Indirect branches. These are JUMP or CALL/return instructions that use a dynamicchanges at runtimeaddress that comes from the PM data address generator. Interleaved data. To take advantage of the processors data accesses to 4and 3-column locations, programs must adjust the interleaving of data into (not necessarily sequential) memory locations to accommodate the memory access mode. Internal memory space. This space ranges from address 0x0000 0000 through 0x0005 3FFF (Normal word). Internal memory space refers to the ADSP-21161 processors on-chip SRAM and memory mapped registers. Interrupts. Subroutines in which a runtime event (not an instruction) triggers the execution of the routine. JTAG port. This port supports the IEEE standard 1149.1 Joint Test Action Group (JTAG) standard for system test. This standard defines a method for serially scanning the I/O status of each component in a system. Jumps. Program flow transfers permanently to another part of program memory. Link ports. The processor has two 8-bit wide link ports, which can connect to other processors or peripherals link ports. These bidirectional ports have eight data lines, an acknowledge, and a clock line. Length registers. A length registers is a Data Address Generator (DAG) register that sets up the range of addresses a circular buffer. Level-sensitive interrupts. This type of interrupt is detected if the signal input is low (active) when sampled on the rising edge of CLKIN.

ADSP-21161 SHARC Processor Hardware Reference

G-7

Loops. One sequence of instructions executes several times with zero overhead. McBSP, multichannel buffered serial port. (See Serial port) MCM, multichannel mode. (See Multichannel mode) Memory access modes. The processor supports Asynchronous and Synchronous modes for accessing external memory space. In asynchronous access mode, the processors RD and WR strobes change before CLKINs edge. In synchronous access mode, the processors RD and WR strobes change on CLKINs edge. Memory blocks and banks. Memory is divided into blocks that are each associated with different data address generators. The processors external memory spaces is divided into banks, which may be addressed by either data address generator. Modified addressing. The DAG generates an address that is incremented by a value or a register. Modify address. The Data Address Generator (DAG) increments the stored address without performing a data move. Modify registers. A modify register is a Data Address Generator (DAG) register that provides the increment or step size by which an index register is pre- or post-modified during a register move. Multichannel mode. In this mode, each data word of the serial bit stream occupies a separate channel. Multifunction computations. Using the many parallel data paths within its computational units, the processor supports parallel execution of multiple computational instructions. These instructions complete in a single cycle, and they combine parallel operation of the multiplier and the ALU or dual ALU functions. The multiple operations perform the same as if they were in corresponding single-function computations.

G-8

ADSP-21161 SHARC Processor Hardware Reference

Glossary

Multiplier. This part of a processing element does floating-point and fixed-point multiplication and executes fixed-point multiply/add and multiply/subtract operations. Multiprocessor memory space. The portion of the memory map that includes the I/O processor registers of in a multiprocessing system. This address space is mapped into the unified address space of the ADSP-21161 processor. Multiprocessor system. A system with multiple processors, with or without a host processor. The processors are connected by the external bus and/or link ports. Multiprocessor vector interrupt. The vector interrupt (VIRPT) permits passing interprocessor commands in multiple-processor systems. One processor writes a vector address to another processors VIRPT register. Writing the address initiates the vector interrupt on the processor that receives the write. The ADSP-21161 processor executes (vectors to) the interrupt service routine at that address. Neighbor registers. In Long word addressed accesses, data is moved to or from two neighboring data registers. The least-significant-32-bits moves to or from the explicit (named) register in the neighbor register pair. In forced Long word accesses (Normal word address with LW mnemonic), the the Normal word address is converted to Long word, placing the even Normal word location in the explicit register and the odd Normal word location in the other register in the neighbor pair. PAGEN, Program address generation logic. (See the Program Sequencer chapter) Peripherals. This refers to everything outside the processor core. The ADSP-21161 processors peripherals include internal memory, external port, I/O processor, JTAG port, and any external devices that connect to the ADSP-21161.

ADSP-21161 SHARC Processor Hardware Reference

G-9

Precision. The precision of a floating-point number depends on the number of bits after the binary point in the storage format for the number. The processor supports two high precision floating-point formats: 32-bit IEEE single-precision floating-point (which uses 8 bits for the exponent and 24 bits for the mantissa) and a 40-bit extended precision version of the IEEE format. Post-modify addressing. The Data Address Generator (DAG) provides an address during a data move and auto-increments the stored address for the next move. Pre-modify addressing. The Data Address Generator (DAG) provides a modified address during a data move without incrementing the stored address. Registers swaps. This special type of register-to-register move instruction uses the special swap operator, <->. A register-to-register swap occurs when registers in different processing elements exchange values. Saturation (ALU saturation mode). In this mode, all positive fixed-point overflows return the maximum positive fixed-point number (0x7FFF FFFF), and all negative overflows return the maximum negative number (0x8000 0000). Semaphore. This is a flag that can be read and written by any of the processors sharing the resource. Semaphores can be used in multiprocessor systems to allow the processors to share resources such as memory or I/O. The value of the semaphore tells the processor when it can access the resource. Semaphores are also useful for synchronizing the tasks being performed by different processors in a multiprocessing system. Serial ports. The ADSP-21161 processor has four synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices.

G-10

ADSP-21161 SHARC Processor Hardware Reference

Glossary

SHARC. This is an acronym for Super Harvard Architecture. This architecture balances a high performance processor core with high performance buses (PM, DM, IO). Shifter. This part of a processing element completes logical shifts, arithmetic shifts, bit manipulation, field deposit, and field extraction operations on 32-bit operands. Also, the Shifter can derive exponents. SMUL, Saturation on multiplication. (See Multiplier Saturation modes) SST, Saturation on store. (See Multiplier Saturation modes) Subroutines. The processor temporarily interrupts sequential flow to execute instructions from another part of program memory. Single-word data transfers. Reads and writes to the EPBx external port buffers, performed externally by the bus master (or host) or internally by the slave's core. These occur when DMA is disabled in the DMACx control register. Synchronous transfers. Synchronous host accesses of the ADSP-21161 processor. When CS is not asserted, the host must act like another processor in a multiprocessor system, by generating an address in multiprocessor memory space, asserting PA and WR or RD, and driving out or latching in the data. TADD, TDM address. (See the section Multichannel Mode) TCB chain loading. The process in which the DMA controller downloads a Transfer Control Block from memory and autoinitializes the DMA parameter registers. Time Division Multiplexed (TDM) mode. The serial ports support TDM or multichannel operations. In multichannel mode, each data word of the serial bit stream occupies a separate channel each word belongs to the next consecutive channel so that, for example, a 24-word block of data contains one word for each of 24 channels.

ADSP-21161 SHARC Processor Hardware Reference

G-11

Transfer control block (TCB). A set of DMA parameter register values stored in memory that are downloaded by the DMA controller for chained DMA operations. Tristate versus three-state. Analog Devices documentation uses the term three-state instead of tristate because Tristate is a trademarked term, which is owned by National Semiconductor. Universal registers (Ureg). These are any processing element registers (data registers), any Data Address Generator (DAG) registers, any program sequencer registers, and any I/O processor registers. Von Neumann architecture. This is the architecture used by most (non-DSP) microprocessors. This architecture uses a single address and data bus for memory access. Waitstates. Waitstates are applied to each external memory access depending on the banks external memory access mode (EBxAM). The External Bank Waitstate (EBxWS) field in the WAIT register sets the number of waitstates for each bank.

G-12

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Numerics
16-bit floating-point format, C-4 32-bit data (See normal word) 40-bit extended-precision floating-point format, C-3

A
Abs function, 2-9 Absolute address, 3-14, G-3 Acknowledge (ACK) pin, 5-42, 6-54, 6-56, 7-6, 7-40, 7-89, 13-4, 13-16 Acknowledge controls, 1-12 Active drive REDY (ADREDY) bit, 7-44, 7-51, A-61 Active low versus active high frame syncs, 10-43 Add instruction, 2-1, 2-9, 2-36 Address bus (ADDR) pin, 5-21, 7-6, 7-38, 7-49, 7-89, 7-96, 8-26, 8-29, 13-4, 13-16 Address buses, 1-2 Address fields, A-42 PM and DM, A-43 Address fields for asynchronous host accesses, 5-21, 7-49 Addressing (See post-modify, pre-modify, modify, bit-reverse, or circular buffer) Storing top-of-loop addresses, A-41 Addressing, DSP external memory registers, A-90

Alternate registers (See secondary registers) ALU carry (AC) bit, 2-11, 3-54, A-14 ALU fixed-point overflow (AOS) bit, 2-11, A-19 ALU floating-point (AF) bit, 2-11, A-16 ALU floating-point invalid (AI) bit, 2-11, A-14 ALU floating-point invalid status (AIS) bit, 2-11, A-19 ALU floating-point overflow status (AVS) bit, 2-11, A-19 ALU floating-point underflow status (AUS) bit, 2-11, A-19 ALU negative (AN) bit, 2-11, A-13 ALU overflow (AV) bit, 2-11, 3-54, A-13 ALU saturation (ALUSAT) bit, 2-4, 2-10, A-4 ALU x-input sign (AS) bit, 2-11, A-14 ALU zero (AZ) bit, 2-11, A-13 AND, logical, 2-9 And breakpoints (ANDBKP) bit, 12-11 Arithmetic logic unit (ALU), 1-6, 2-1, 2-9 Instructions, 2-9, 2-12 Interrupts, 3-43 Operations, 2-9 Saturation, 2-10 Status, 2-4, 2-8, 2-10, 2-11, 2-20, 3-43 Arithmetic operations, 1-3, 2-9, 2-10 Arithmetic shifts, 2-1, G-11 Arithmetic status (ASTATx/y) registers, 2-8, A-13 Assembly language, 2-2

ADSP-21161 SHARC Processor Hardware Reference

I-1

INDEX

Asymmetric data moves, 2-39 Asynchronous access mode, 5-43, 7-6, 7-12, 7-13, 7-44, 7-50, 7-94, 13-16, G-8 Direct write, 7-56 For all external memory banks, A-65 Interface Timing, 7-14 Interface timing, 7-14 Readbus master, 7-15 Read/Writebus slave, 7-14 Slave write FIFO, 7-50 Starting a transfer, 7-48 Timing derivation, 7-17 Transfers, 7-42, 7-48 transfers, 7-48 Writebus master, 7-17 Asynchronous transfers, G-1 Average instructions, 2-9, 2-36

B
Background registers (See Secondary registers) Background registers (See secondary registers) Bank activate (ACT) command, 8-2, 8-20, 8-32 Barrel-shifter (See shifter) Base (Bx) registers, 4-2, 4-16, A-47, G-1 Bidirectional functions, 10-1 Binary log (floating-point operation), 2-9 Bit (bit manipulation) instruction, 3-5 Bit manipulation, 2-1, 2-23, G-11 Bit-reverse addressing, 4-1, 4-4, 4-8, A-3, G-1 Bit-reverse addressing (BRx) bits, 4-4, 4-8, A-3 Bit-reverse (Bitrev) instruction, 4-8, 4-17, 4-23 Bit test flag (BTF) bit, 3-54, A-17 BIT TST instruction, 2-8

Bit XOR instruction, 3-54 Booting, 1-14, 5-23, 5-35, 5-37, 13-71 16-bit SPI host boot, 11-39 32-bit SPI host boot, 11-38 8-bit SPI host boot, 11-41 Another DSP, 7-108 External port booting, 6-70 From a 16-bit SPI host, 11-39 From a 32-bit SPI host, 11-38 From a 8-bit SPI host, 11-41 From an EPROM, 6-71, 13-73, 13-74, 13-75 From the link port, 6-88, 6-89, 6-113, 6-114 Mode selection, 6-70, 6-89, 6-114 Multiple DSPs, 13-73 Multiprocessor booting from external memory, 13-75 Multiprocessor EPROM booting, 13-73 Multiprocessor host booting, 13-73 Multiprocessor link port booting, 13-75 Multiprocessor SPI booting, 11-42 Sequential booting, 13-74 Single and multiple processors, 13-71 SPI, 11-34 Boot memory select (BMS) pin, 5-35, 6-42, 6-70, 6-89, 6-114, 7-10, 13-5, 13-12 Boot select override (BSO) bit, 5-32, 5-35, 6-31, 6-42, A-60 Boundary scan, 12-1, 12-29 Branch Conditional, 3-15 Delayed, 3-15 to 3-18 Direct, 3-14, G-3 Indirect, 3-14 Branches and sequencing, 3-13 Branching execution, 3-13 Direct and indirect branches, 3-14 Immediate branches, 3-16 Breakpoint output (BRKOUT) pin, 12-8

I-2

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Breakpoint status shift (BRKSTAT) register, 12-12 Breakpoint status (STATx) bit, 12-13 Breakpoint stop (BKSTOP) bit, 12-8 Breakpoint triggering mode (xMODE) bit, 12-10 Broadcast load, 4-1, 4-2, 4-3, 4-5, 5-51, A-5, G-2 Broadcast load enable (BDCSTx) bits, 4-2, 4-4, 4-5, 5-40, A-5 Broadcast writes, 7-50, 7-57 BSDL file, 12-4 BSDL Reference Guide, 12-29 Buffer hang disable (BHD) bit, 6-31, 6-43, 12-11, A-61 Buffer hang override (BHO) bit, 12-11 Buffer overflow, circular, 4-9, 4-12, 4-15 Buffers Link port, 6-83, 6-133 Reading from an empty buffer, A-61 SDRAM buffering, 8-16 Buffer status, 6-129, 6-136, 6-139 Built-in self-test operation (BIST), 12-28 Burst length, 8-22 Burst length, setting, A-84 Bursts Sequential bursts, external port, 7-58 Burst transfer (BRST) pin, 7-6, 7-38, 7-89, 7-96, 13-6, 13-16 Burst transfers, 7-26, 7-29, G-2 Buses, 1-2, 1-10 Accessing the DSP bus, 7-79 Acquiring the bus, 7-45 addressing operations, 5-7 Arbitration, 7-93, 7-95, 7-96 arbitration, 5-7 Bus contention, A-48 Bus lock, 7-83, 7-92, 7-110 Bus master, 7-44, 7-79, 7-97 Timeout, 7-101

Buses (continued) Bus slave, 7-79, 7-97 Bus slave defined, G-2 Bus synchronization, 7-105, 7-108 Conflict resolution ratio, 7-3 Data access types, 5-47 Deadlock, 7-44, 7-54, 7-82 DSP bus, 7-79 Enhancements, 1-17 Multiprocessor bus arbitration, 7-93 Priority, 5-39 Processor core, 1-17 Bus exchange (See program memory bus exchange (PX) register) Bus lock and semaphores, 7-110 Bus lock (BUSLK) bit, 7-102, 7-111, A-10 Bus master, current (CRBMx) bit, A-69 Bus master (Bm) condition, 3-55, 7-95, 7-111 Bus master count (BCNT) register, 7-102, A-79 Bus master max time-out (BMAX) register, 7-101, A-79 Bus master output (BMSTR) pin, 13-5 Bus master select (CSEL) bit, A-5 Bus Request, multiprocessor (BRx) pins, 7-89, 7-94, 7-111, 13-5 Bus synchronized (BSYN) bit, 7-106, A-69 Bus Transition Cycle (BTC), 7-20, 7-45, 7-96, G-2 BYPASS instruction, 12-4

C
Cache disable (CADIS) bit, 3-11, A-10 Cache efficiency, 3-11 Cache freeze (CAFRZ) bit, 3-11, A-11 Cache hit/miss (See cache efficiency) CALL instructions, 3-13

ADSP-21161 SHARC Processor Hardware Reference

I-3

INDEX

Capacitors Bypass, 13-69 Decoupling capacitors, 13-69 Loading, 13-67 CAPTURE state, 12-7 CAS before RAS transaction (CBR), 8-3, 8-37, 8-39 CAS latency, 8-2, 8-8, 8-17, 8-24 CAS-to-RAS delay (SDTRCD), 8-4, 8-21 Chained DMA External port, 6-46 Link ports, 6-85 Serial ports, 6-99 Chained DMA enable, external port (CHEN) bit, 6-32, A-80 Chained DMA enable (SCHEN_A and SCHEN_B) bit, serial port, A-102 Chained DMA sequences, 6-25 Chain insertion mode, 6-29, 6-130 Chain pointer (CPx) registers, 6-7, 6-12, 6-25, A-88 Chip select (CS) pin, 7-42, 7-44, 7-79, 7-89, 13-8, A-75 Circular buffer addressing, 1-8, 4-2, 4-4, 4-12, A-6, G-2 Registers, 4-15 Setup, 4-13 SIMD and Long word accesses, 4-17 Wrap around, 4-15 Circular buffer addressing enable (CBUFEN) bit, 4-2, 4-4, 4-14, A-6 Circular buffering, length and base registers, A-47 Circular buffer x overflow interrupt (CBxI) bit, A-30 Circular buffer x overflow status (CBxS) bit, A-20 Clear, bit, 2-23 Clear interrupt (CI) Jump instruction, 3-14

Clip function, 2-9 CLKOUT disable (COD) bit, A-61 Clock and frame sync frequencies (DIV), 10-33 Clock cycles delays, 8-2, A-73 Clock derivation, 13-24 Clock distribution, 13-63 Clock divisor (CLKDIV) bits, A-112 Clock double (CLKDBL) pin, 13-6, 13-25, 13-26 Clock input (CLKIN) pin, 7-38, 7-89, 10-8, 12-1, 13-16, 13-24, 13-28 Clock output (CLKOUT) pin, 7-7, 7-96, 13-8, 13-62 Clock ratio, 13-28 Clock ratio configuration (CLK_CFGx) pins, 13-25, A-70 Clock relationships, 13-27 Clock rising edge (CKRE) bit, 10-21, A-101 Clocks CLKOUT and CCLK clock generation, 13-27 Coordinating the SDRAM CLK rate, 8-3 Core clock and system clock relationship to CLKIN, 13-27 Core clock ratio, 8-12, 13-28 Determining switching frequencies, 13-26 Determining the period, 13-28 Jitter, 13-63 Programming clock ratio example, 13-40 SPICLK, 11-3 System clock CLKIN, 10-8 Clock signal options, 10-40 Cluster multiprocessing, G-2 CODECs, 10-1 Code select (CSEL) bit, 3-56, 7-95, A-5

I-4

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Commands, SDRAM Active command tRAS, 8-4 Bank activate (ACT), 8-2, 8-20, 8-21, 8-32, A-73 CBR automatic refresh, 8-3 Mode register set (MRS), 8-19 Precharge, 8-20, 8-29, 8-33, 8-37, A-74 Refresh, 8-29, 8-30, 8-37 Self refresh (SREF), 8-3, 8-20, 8-39 Companding (compressing/expanding), 1-14, 10-2, 10-39, G-2 Compare accumulation (CACCx) bits, 2-11, A-17 Compare function, 2-9 Complementary conditions, 3-59 Complementary registers, 2-40, G-5 COM port, McBSP (See Link Ports) COM port, McBSP (See link ports) Computational mode, 2-42 Computational mode, setting, 2-4 Computational status, using, 2-8 Computational units (See processing elements) Conditional Branches, 3-15, 3-59, G-2 Complementary conditions, 3-59 Compute operations, 3-58 Conditions list, 3-54 Execution summary, 3-58 Instructions, 3-3, 3-53 Sequencing, 3-53 SIMD mode and conditionals, 3-57 Condition codes, 3-54 Conditioning input signals, 13-60 Configuration register, 8-3 Configuring and enabling the SPI system, 11-9 Configuring frame sync signals, 10-4 Conflict resolution ratio, G-2 Context switch, 1-9, 2-32

Core clock ratio, 8-12 Core hang, causes, A-121 Core-memory halt (COMHALT) bit, 12-12 Core-to-CLKIN ratio (CRAT) bit, A-70 Count (Cx) registers, 6-7, 6-11, A-87 Counter-based loops, 3-26, 3-27 (See also Non-counter-based loops) Crosstalk, 13-68 Current Bus Master (CRBMx) bits, 7-95, 7-96 Current loop counter (CURLCNTR) register, 3-31, A-45

D
Data, fixed- and floating-point, 2-1, G-1 Data access conflicts, 5-7 Dual-data accesses, 5-5 Dual-data access restrictions, 5-5 Options, 5-52 (See also data moves) Settings, 5-32 Data Address Generators (DAGs), 1-8, 4-1, 5-8, 5-40, 8-22, G-3 Data alignment, 4-19 Data move restrictions, 4-21 Data moves, 4-18 Enhancements, 1-17 Features, 1-5 Instructions, 4-23 Operations, 4-9 Setting Modes, 4-2 SIMD mode, 4-18 Status, 4-8 Data addressing mode, 2-42 Data alignment, 5-10, 5-25, 5-48, 7-1 Data alignment, link data, 9-12 Data buffers, 6-13

ADSP-21161 SHARC Processor Hardware Reference

I-5

INDEX

Data bus (DATA) pins, 7-8, 7-38, 7-89, 13-9, 13-16 Data (Dreg) registers, G-3 Data fetch, external port, 7-3, G-3 Data file registers, listed, A-23 Data flow, 1-3, 2-1 Data flow multiprocessing, G-3 Data format, 2-2 Extended-precision normal word, 40-bit floating-point, 2-5 External data, 6-46 Link data, 6-86 Normal word, 32-bit fixed-point, 2-6 Normal word, 32-bit floating-point, 2-4 Serial data, 6-99 Short word, 16-bit floating-point, 2-6 Data hold cycle, 7-12 Data independent transmit frame sync (DITFS) bit, 10-22 Data I/O mask DQM (data I/O mask) pin, 8-3, 8-29 Data memory data select (DMDSEL) bit, 12-11 Data Memory (DM) bus, 1-2 Data moves, 1-10 Conditional, 3-59 Moves to/from PX, 5-14 Data packing, 1-12, 7-56, 7-58, 7-59, 7-110, 10-37 Data registers, 1-6, 2-30, 2-42, G-3 Data registers, secondary hi/lo (SRRFH/L) bits, 2-33 Data transfers, using EPBx buffers, 7-58 Data type, external port (DTYPE) bit, 6-32, 6-43, 6-46, A-81 Data type, serial port (DTYPE) bit, 6-96, 6-109, 10-24, A-101 Data type and formatting (multichannel and non-multichannel), 10-37, 10-38 Data types, 5-47

Deadlock resolution, 7-82, G-3 Deadlock (See bus deadlock) Debugging, tools, 13-49 Decode address (DADDR) register, 3-5, A-44 Decode address register, 3-2 Decode cycle, 3-7 Delayed branch (DB) instruction, 3-15 to 3-18, 3-19 (DB) Jump or Call instruction, 3-17, G-3 limitations, 3-19 Denormal operands, 2-5 Deposit bit field, 2-23 Divisor (DIVx) register, serial port, 10-4 DMA Bus slave versus bus master, 7-59 Defined, G-4 DSP DMA Access To System Bus, 7-84 External port, 7-58 Interrupt-driven DMA, 6-125 Serial port, 6-108 SPI, 11-32 SPI master mode, 11-32 SPI slave mode, 11-33 Transfers, 7-58 DMA Address (DA) Registers, listed, A-49 DMA block transfers, 10-59 DMA channel Buffer registers, listed, 6-13 Interrupt priorities, 6-126 Latency, 6-125 Parameter registers, listed, 6-13 Priority, 6-12, 6-22, 6-24, 6-44, 6-83, 6-99, 6-112 Status, 6-124 DMA channel priority rotation, external port (DCPR) bit, 6-31, 6-43, A-61 DMA channel status (DMASTAT) register, 6-125, A-90

I-6

ADSP-21161 SHARC Processor Hardware Reference

INDEX

DMA control (DMACx) registers, 6-6, 6-30, 7-103, A-80, G-4 DMA controller, 1-2, 1-15 Enhancements, 1-18, 1-19 Priority pathways, 6-22 DMA data 16-bit external transfers, 6-52 32-bit external transfers, 6-51 32-bit internal transfers, 6-54 48-bit internal transfers, 6-53 64-bit internal transfers, 6-53 DMA enable, external port (DEN) bit, 6-15, 6-32, A-80 DMA external request counter, 6-61 DMA grant (DMAGx) pins, 6-57, 6-67, 7-59, 7-96, 13-9, 13-16 DMA hardware handshake, 6-59, 6-63, A-65 DMA hardware interface, 6-140 DMA hold off, 6-56, 6-62 DMA internal request & grant paths, 6-22 DMA parameter registers, defined, G-4 DMA pipeline, 6-61 DMA request (DMARx) pins, 6-54 to 6-67, 7-59, 13-9, 13-16 DMA sequences Chaining sequences, 6-25 Chain insertion, 6-28 Chain set up and start, 6-28 Sequence complete interrupt, 6-126 Sequence end, 6-21 TCB loading, 6-26, G-4 DMA slave, interrupts, 9-19 DMA targets External memory, 6-49 Internal memory, 6-139 DMx register, 12-13, 12-15 DO UNTIL instruction, 3-24 (See also loops)

DSP Architecture overview, 1-5 Design advantages, 1-1 DSP serial mode, 10-59 Dual add and subtract, 2-36 Dual-data accesses, 5-52 Dual processing element moves (See broadcast load) .D unit (See DAGs or ALU) D unit (See DAGs or ALU)

E
Edge-sensitive interrupts, 3-40, A-10, G-4 Effect latency (See latency) E field, address, A-42 EMULATION instruction, 12-4 Emulation (JTAG), 1-2 Emulation status EMU pin, 13-10, 13-54 Emulator 48-bit PX shift (EMUPX) register, 12-6 Emulator 64-bit PX shift (EMU64PX) register, 12-7 Emulator clock2 (EMUCLK2) register, 12-3, 12-16 Emulator clock (EMUCLK) register, 12-16 Emulator control shift (EMUCTL) register, 12-8 Emulator enable (EMUENA) bit, 12-8 Emulator idle (EMUIDLE) instruction, 12-17 Emulator interface illustrated for ADI JTAG processors, 13-50 Emulator Interrupt (EMUI) bit, A-27 Emulator interrupt enable (EIRQENA) bit, 12-8 Emulator Nth event counter (EMUN) register, 12-3, 12-16 Emulator PC shift (EMUPC) register, 12-7 Emulator PM data shift (EMUPMD) register, 12-5

ADSP-21161 SHARC Processor Hardware Reference

I-7

INDEX

Emulator pod, connection, 13-56 Emulator ready (EMUREADY) bit, 12-12 Emulator shift (EMUPC) register, 12-7 Emulator space (EMUSPACE) bit, 12-12 Emulator status shift (EMUSTAT) register, 12-11 Enable breakpoint (ENBx) bit, 12-10 Enable (BRKOUT) pin, 12-8 Endian format, 1-14, 10-36, G-4 End-of-loop, 3-25 EPROM booting, 6-70, 6-71 EPROM boot select (EBOOT) pin, 13-10 Equals (EQ) condition, 3-54 Examples bit reverse addressing, 4-8 Cache inefficient code, 3-12 Clock derivation, 13-28 Configuring flags, 13-37 Direct branch, 3-14 DO UNTIL loop, 3-23 Dual processor system example, 8-25 External port DMA programming example, 6-76 Interrupt service routine, 3-48 Long word moves, 5-49 Programming clock ratio, 13-40 PX register transfers, 5-10 to 5-15 Rotating Priority Arbitration, 7-101 SDRAM programming examples, 8-40 Serial port programming examples, 10-67 Single and dual data access, 5-52 SPI programming examples, 11-44 Token passing, 9-27 Examples, timing Framed vs. unframed data, 10-45 Host acquisition of bus, 7-46 Link port handshake, 9-10 Normal vs. alternate framing, 10-45 Serial port multichannel transfer, 10-52

Examples, tming (continued) Serial port word select, 10-52 Typical synchronous write, 7-23 Execute cycle, 3-7 Execution stalls, bus transition, 7-97 Explicit versus implicit operations, G-5 Exponent derivation, 2-1, G-11 Extended precision normal word, 5-25, 5-50 Data access, 5-70 Data storage, 5-2 Mixed data access, 5-50 SIMD mode access, 5-74 External bank access mode (EBxAM) bits, 5-34, 5-42, A-66 External bank x waitstates (EBxWS) bits, 5-35, 5-45, 7-20, A-66, G-12 External bus arbitration, 6-24 External bus priority (EBPRx) bits, 5-33, A-61 External handshake mode, 6-49, 6-66 DMA exceptions, 6-66 (EXTERN) bit, 6-33, 6-47 to 6-66, A-82 program control (PCI) interrupt, 6-67 External instruction execution packing modes, 5-102 External memory, 1-18, 5-16, 5-22, G-5 Access modes, 5-42, G-8 Access timing, 7-13 Addressing registers, A-90 Banks, 7-9 Interface, 7-3, 7-6 External memory addresses, A-43 External memory DMA count (ECEPx) registers, 6-8, 6-12, 6-55, 6-66, A-90 External memory DMA index (EIEPx) registers, 6-7, 6-12, 6-55, 6-66, A-89 External memory DMA modifier (EMEPx) registers, 6-8, 6-12, 6-55, 6-66, A-89

I-8

ADSP-21161 SHARC Processor Hardware Reference

INDEX

External port, 1-2, 1-12, 5-7, 7-1, G-5 Buffer modes, 6-42 Buffer status, 6-129 Conflict resolution, 7-3, G-3 Data packing, 1-12 DMA channel priority modes, 6-43 DMA channel priority swap, 6-24 DMA channel transfer modes, 6-46 DMA handshake modes, 6-47 DMA programming examples, 6-76 DMA setup, 6-68 Enhancements, 1-18 Latency, G-2 Modes, 6-30, 7-3 Packing status, 6-129 Selecting the external port buffers mode, A-82 Setting External Port Modes, 7-3 Single-word transfers, 7-58 Status, 6-127 Termination values, 13-16 External port address (EPAx) register, 12-16 External port boot (EBOOT) pin, 6-70, 6-89, 6-114 External port buffer (EPBx) register data transfers, 7-58 External port buffer (EPBx) registers, 6-4, A-61, A-76 External port buffer x DMA interrupt (EPxI) bit, A-30 External port bus priority (PRIO) bit, 6-33 External port DMA Channels, 6-49 DMA hardware interface, 6-140 DMA setup, 6-68 Modes, 6-46, 6-47 External port DMA channel priority rotation (DCPR) bit, A-61 External port (EP) registers, listed, A-49

External port FIFO buffers, 6-130, G-5 External port halt (EPHALT) bit, 12-12 External port-link port rotating DMA channel priority (PRROT) bit, A-61 External port packing mode (PMODE) bits, 6-32 External port stop (EPSTOP) bit, 12-9 EXTEST instruction, 12-4 Extract bit field, 2-23 Extract exponent, 2-23

F
False always (FOREVER) Do/Until condition, 3-56 FAX for information, 1-21 Fetch address (FADDR) register, 3-2, A-44 Fetch cycle, 3-7 Fetched address, 3-2 Field deposition/extraction, 2-1, G-11 FIFO buffer status, external port (FS) bit, 6-128, A-84 File Transfer Protocol (FTP) site, 1-21 Fixed-point ALU instructions, 2-12 Data, 2-1, G-1 Multiplier instructions, 2-21, 2-36 Operands, 2-10, A-14 Operations, 2-31 Saturation values, 2-19 Fixed-point overflow interrupt (FIXI) bit, 3-43, A-31 Fixed priority, 6-22, 6-44, 6-84, 6-99, 6-112 Flag input (FLAGx_IN) conditions, 3-55 Flag input/output (FLAGx) pins, 7-82, 10-7, 13-10, 13-16, 13-34, 13-39 Flag input/output (FLGx) bits, 13-34, A-10, A-37 Flag input/output select (FLGxO) bits, A-10

ADSP-21161 SHARC Processor Hardware Reference

I-9

INDEX

Flag input/output value (FLAGS) register, 13-34, A-37 Flag pins, configuration example, 13-37 Flag update, 2-12, 2-20, 2-27, 2-46, 3-43, 4-9, 5-46, 7-82, 13-39, G-6 Floating-point ALU instructions, 2-14 Data, 2-1, 2-7, G-1 Data format (RND32) bit, 2-4 Invalid operation (FLTII) interrupt, 3-43 Multiplier instructions, 2-21 Operations, 2-31, 2-36 Floating-point invalid interrupt (FLTII) bit, A-31 Floating-point overflow interrupt (FLTOI) bit, 3-43, A-31 Floating-point underflow interrupt (FLTUI) bit, 3-43, A-13, A-31 Flow-through SBSRAM (See SBSRAM) Flush DMA buffers/status (FLSH) bit, 6-30, 6-128, A-83 Format conversion, 2-9 Format packing (Fpack/Funpack) instructions, 2-6 Fractional Data, 2-6, 2-7 Input(s), 2-22 Results, 2-17, C-6 Framed versus unframed data, 10-42 Frame sync early versus late, 10-44 (FSx) pins, 10-4, 13-10 internal vs. external, 10-42 options, 10-41 rates, setting, 10-49 required (FSR) bit, A-102 signals, configuration, 10-4 Full-duplex operation, specifications, 10-4 Functions, ABS (absolute value), 2-9

G
General-purpose (GPx) registers, 6-7, 6-12, 6-26, A-89 Global interrupt enable (IRPTEN) bit, A-4 Greater or Equals (GE) condition, 3-54 Greater Than (GT) condition, 3-54 Ground plane, 13-68

H
Handshake and idle for DMA enable (HIDMA) bit, 6-31, A-67 Handshake mode, 6-48, 6-57, 6-144 DMA, A-65 Enable/disable transition, 6-62 Operation, 6-60 Register handshake/write-back messaging, 7-77 Transfer Size, 6-58, 6-68 Handshake mode (HSHAKE) bit, 6-33 to 6-66, A-82 Handshaking External port, 7-4, 7-42, 7-87 External port DMA, 6-47 Link port, 9-2, 9-10 Harvard architecture, 5-4, G-6 Hold off DSP, bus transition, 7-97 DSP, during DMA, 6-62 External device, during DMA, 6-56 SBSRAM, 7-40 Hold time, inputs, 13-19 Hold time cycle, 5-45, 7-12, G-6 Host bus acknowledge (REDY) pin, 13-13 Host Bus Grant (HBG) pin, 7-42, 7-44, 7-79, 7-89, 7-96, 7-107, 13-11 Host bus master (HSTM) bit, A-69 Host bus request HBR pin, 7-42, 7-44, 7-111, 8-29, 13-10 Host bus width (HBW) bit, A-60

I-10

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Host interface, 1-13 Access to link buffers, 9-14 Booting, 6-70 Deadlock resolution See bus deadlock Deadlock Resolution With SBTS, 7-54 Enhancements, 1-18 signals, 7-44 Status, 7-76 Uniprocessor, 7-50 Host most significant word first packing (HMSWF) bit, 6-31, A-60 Host packing mode (HPM) bits, 6-31, 6-42, 7-43 Host packing status (HPS) bit, 6-127, A-70 Host Processor Interface, 7-42 Host Transfer Timing, 7-51 Host Transition Cycle (HTC), 7-45, 13-17, G-6 Hysteresis on Reset (RESET) pin, 13-61

I
I2S control bits, 10-49 I2S mode, 10-48, 10-59 I2S support, 1-14 IDCODE instruction, unsupported, 12-4 Identification, processor (PIDx) bit, A-78 Identification code (IDC) bit, A-69 Identification (ID2-0) pin, 7-94, 13-11, 13-16 Idle cycle, 7-10, 7-12, G-6 IDLE instruction, 3-1, 3-48 IDLE instruction, defined, G-6 Idle mode (INIDLE) bit, 12-12 IEEE 1149.1 JTAG specification, 1-16, G-7 IEEE 1149.1 JTAG standard, 13-56 IEEE 754/854 floating-point data format, 2-4, C-1

IEEE floating-point number conversion, 2-6 Illegal input condition detected (IICD) bit, 5-41, A-27 Illegal IOP register access (IIRA) bit, A-20 Illegal I/O processor register access enable (IIRAE) bit, 5-34, 5-41, A-11 Immediate branch, 3-16 Implicit operations, 5-41 Broadcast load, 4-5 Complementary registers, 2-40 Long Word (LW) accesses, 5-48 Neighbor registers, 5-49 SIMD mode, 2-40 In circuit signal analyzer (ICSA) function, 12-11, 12-17 INCLUDE directory, 10-10 Increment instruction, 2-9 Index (Ix) registers, 4-2, 4-15, A-47, G-7 Indirect addressing, 1-8 Indirect branch, 3-15, G-7 Inductance (run length), 13-67 Infinity, round-to, 2-5 Input filtering, link port, 13-60 Input/Output (IO) bus, 1-2 Input setup and hold time, 13-19 Input signal conditioning, 13-60 Input Synchronization Delay, 13-33 Instruction External memory fetch, 7-3, 7-56, G-3 Moves, 7-56 Transfers, 7-56, 7-110 Instruction (bit), 3-5 Instruction cache, 1-9, 3-9, 5-5 Instruction dispatch/decode (See program sequencer) Instruction Execution Mode, external packed (IPACK) bit, A-62 Instruction pipeline, 3-2, 3-7 Instruction register, 12-4

ADSP-21161 SHARC Processor Hardware Reference

I-11

INDEX

Instructions ADD, 2-1, 2-9, 2-36 AVE, 2-9, 2-36 BIT CLR, 2-23 BIT TST, 2-8 Computational, 2-1 Conditional, 2-8, 2-42 , 7-10 conditional, 2-44 Decrement, 2-9 delayed branch (DB), 3-19 FDEP, 2-25 Multiplier, 2-15, 2-20 Instruction set Changes, 1-20 Enhancements, 1-20 Instruction word Data access, 5-50 Storage, 5-2 Word Rotations, 5-25 Instruction Word Transfer (IWT) bit, 7-49 Integer Input(s), 2-22 Results, 2-16, C-6 Integer data, 2-6 Interleaved data, 5-100, G-7 Internal address bus (IA), 8-26 Internal Buses, 1-10 Internal interrupt vector table (IIVT) bit, 5-32, 5-37, A-60 Internal I/O bus arbitration (request & grant), 6-22 Internal memory, 5-2, 5-16, 5-18, 5-24, G-7 Internal memory 32-bit transfers (INT32) bit, A-84 Internal memory data width (IMDWx) bits, 5-12, 5-32, 5-37, 5-47, 6-86, A-60

Internal memory DMA Count (Cx) registers, A-87 Internal memory DMA index (IIx) registers, 6-7, 6-9, A-87 Internal memory DMA modifier (IMx) registers, 6-7, 6-9, A-87 Internal serial clock (ICLK) bit, 10-24 Internal timer, 8-3 Internal transmit frame Sync (ITFS) bit, 10-25 Interprocessor Messages and Vector Interrupts, 7-76 Interrupt and Timer Pins, 13-33 Interrupt controller, 3-2 Interrupt-driven I/O, external port (INTIO) bit, 6-43, 6-128, 6-130, A-82 Interrupt-driven transfers External port, 6-130 Link port, 6-134 Serial port, 6-136 Interrupt enable, global (IRPTEN) bit, 3-41, A-4 Interrupting IDLE, 3-48 Interrupt input (IRQ2-0) pins, 13-11, 13-33 Interrupt input x interrupt (IRQxI) bit, A-28 Interrupt latch (IRPTL) register, A-27 Interrupt latency, 3-36 Cache miss, 3-36 Delayed branch, 3-36 IRQx and multiprocessor vector standard, 3-38 Single-cycle instruction, 3-36 Writes to IRPTL, 3-35 Interrupt mask (IMASK) register, 3-41, A-31 Interrupt mask/mask pointer, link port (LIRPTL) register, 3-42, 3-46, A-34

I-12

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Interrupt mask pointer (IMASKP) register, 3-45, A-32 Interrupt nesting enable (NESTM) bit, 3-45 Interrupts, 1-9, 2-8, 3-1, 3-34, 4-9, 5-41, 5-42, 5-46, A-28, G-7 Arithmetic, 3-43 Clear interrupt (CI) Jump, 3-48 Conditions for generating interrupts, 10-60 Data Address Generators (DAGs), 4-14 Delayed branch, 3-18 DMA interrupts, 6-125 to 6-130 DMA slave, 9-19 Hold off, 3-39 Idle instructions, 3-48 Inputs (IRQ2-0), 3-34 Interrupt sensitivity, 3-40, A-10, G-7 Interrupt vector table, 5-37, B-1 IRPTL write timing, 3-35 Latch status for, A-27 Latency (See interrupt latency) Link port, spurious interrupts, 9-9, 9-22 Link ports, 9-17 Masking and latching, 3-41, 3-42, 6-126, 9-19 Multiprocessing, 3-49 Nested interrupts, 3-45, A-4 Non-maskable RSTI, A-60 PC stack full, 3-53 Program control (PCI) interrupts, 6-67 Response, 3-34 Re-using, 3-47 Sensitivity, interrupts, A-10 Software, 3-35 Spurious, link port, 9-9, 9-22 Timer, 3-51 Vector interrupts, 7-76, G-9 VIRPT, 3-45 Interrupts and sequencing, 3-34

Interrupt vector, sharing, 10-7 Interrupt x edge/level sensitivity (IRQxE) bits, 3-40, A-10 Interval timer, 3-50 INTEST instruction, 12-4 IO architecture, 1-19 IOFLAG value register, A-38 I/O interface to peripheral devices, 10-1 I/O interrupt conditions, 6-124 IOP addresses for SPI registers, 11-9 I/O processor, 1-2, 1-14, 5-16, 6-1, 6-9, 6-81, 6-96 DMA channel priority, 6-22 External port modes, 6-29 Link port modes, 6-81 Registers, G-6 Serial port modes, 6-95 Shadow registers, 7-55 Status, 6-121 I/O processor registers, listed, A-48 IOP Shadow Registers, 7-55 I/O stop (IOSTOP) bit, 12-9 IR decode space, 12-2

J
Joint Electronic Device Engineering Council (JEDEC), 8-9 JTAG boundary register, 12-18 data output (TDO) pin, 13-15 emulation, designing for, 13-49 emulator references, 13-56 in circuit emulator (ICE), 12-3 instruction register codes, 12-4 interface, access to features, 12-2 interface pins, 13-41 logic, 12-3 pod connector, illustrated, 13-58 port, 1-2, 1-16, 12-1, 12-3, 13-49

ADSP-21161 SHARC Processor Hardware Reference

I-13

INDEX

JTAG (continued) port, defined, G-7 references, additional documents, 13-56 scan chain, restrictions, 13-54 signals, 13-54 signals, listed, 13-52 specification, IEEE 1149.1, 12-1, 12-3, 12-4, 12-29 test access port (TAP), 12-3, 13-49, 13-55 test clock (TCK) pin, 13-15 test data input (TDI) pin, 13-15 test-emulation port, 12-1 to 12-29 test mode select (TMS) pin, 13-15 test reset (TRST) pin, 13-16 JUMP instructions, 3-1, 3-13, G-7 Clear interrupt (CI), 3-14, 3-48 Loop abort (LA), 3-14, 3-24 Pops status stack with (CI), 3-45

L
Latch, characteristics, 12-1 Latch status for interrupts, A-27 Latchup, 13-60 Late frame sync (LAFS) bit, 10-25 Latency, 3-5, 3-11, 3-36, 6-30, 6-96, 6-108, 6-125, G-3 Direct read, 7-57 DMA status, A-91 Input Synchronization, 13-33 Instruction fetch, external memory, 7-3 I/O processor registers, A-48 Link ports, 9-13 Shadow registers, 7-55 Slave write FIFO, 7-56 Synchronous write, 7-22 System registers, 3-5 Vector interrupt, 3-38 Least significant bits (LSB), 3-9

LEFTO operation, A-17 LEFTZ operation, A-17 Length (Lx) registers, 4-2, 4-16, A-47, G-7 Less or Equals (LE) condition, 3-54 Less than (LT) condition, 3-54 Level-sensitive interrupts, 3-40, A-10, G-7 Line run length (inductance), 13-67 Line termination, link port, 9-30 Link buffer assignment (LARx) bits, 6-82 Link buffer DMA chaining enable (LxCHEN) bit, 6-82, 6-85, 9-7, A-93 Link buffer DMA enable (LxDEN) bit, 6-15, 6-82, 6-85, 9-7, 9-13, A-93 Link buffer enable (LxEN) bit, 6-82, 6-83, 9-7, A-93, A-94 Link buffer extended word size (LxEXT) bit, 6-83, 9-7, 9-13, A-92, A-93, A-95 Link buffer receive packing error status (LRERRx) bits, 9-22, A-96 Link buffer status (LxSTATx) bits, 9-13, A-96 Link buffer-to-port connections, 9-3 Link buffer transmit/receive (LxTRAN) bit, 6-82, 6-86, 9-7, A-93, A-94 Link buffer x DMA interrupt mask (LPxMSK) bit, A-35 Link buffer x DMA interrupt mask pointer (LPxMSKP) bit, A-35 Link (LSP) registers, listed, A-50 Link port, 1-2, 1-15, 1-19, 9-1, 9-10, G-7 Booting, 6-85, 6-88, 6-89, 6-113, 6-114 Buffers, 6-83, 6-133, 9-3 Data transfers, cluster, 7-93 Designing for link ports, 9-30 DMA, 6-85, 6-86, 6-112, 9-4, 9-16 Enhancements, 1-19 Handshake timing, 9-10 Identifying the one to service, 9-21 Interrupt-driven transfers, 6-134

I-14

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Link port (continued) Interrupts, 9-17 to 9-22 Line termination, 9-30 Priority modes, 6-83 Status, 6-131, 6-133 Throughput, 9-31 Token passing, 9-27 Transmission errors, 9-22 Link port acknowledge (LxACK) pins, 9-2 to 9-12, 13-12, 13-16 Link port assignments (LABx) bits, A-96 Link port boot (LBOOT) pin, 6-70, 6-89, 6-114, 13-12 Link port buffer (LBUFx) registers, 6-4, 9-3, 9-12, A-92 Link port buffer x DMA interrupt (LPxI) bit, A-34 Link port clock divisor (LxCLKD) bit, A-93, A-95 Link port clock divisor (LxCLKDx) bits, 9-8, 9-10, 13-26, 13-28 Link port clock (LxCLK) pins, 9-2, 9-10, 9-12, 13-11, 13-16 Link port control (LCTL) register, 6-6, 6-81, 9-9, 9-13, A-92, A-93 Link port data (LxDAT7-0) pins, 7-8, 9-2, 9-3, 9-12, 13-11, 13-16 Link port data path width (LxDPWID) bit, 9-8, 9-10, A-94, A-96 Link port DMA channel priority rotation (LDCPR) bit, 6-82, 6-83, A-61 Link port DMA interrupts, latch and mask bits, 3-43 Link port-external port rotating DMA channel priority (PRROT) bit, A-61 Link port input filter circuits, 13-60 Link port interrupt DMA summary interrupt (LPISUMI) bit, 3-43, 6-126, A-29, A-34

Link port interrupt (LIRPTL) register, 3-46, A-34 Link port pulldown resistor, caution when enabled, 9-9 Link port pulldown resistor disable/enable (LxPDRDE) bit, 9-8, 9-12, A-94, A-95 Link port receive mask (LxRM)) bits, 6-131, A-98 Link port receive request status (LxRRQ) bits, 6-131, A-99 Link port service request interrupt (LSRQI) bit, 6-126, 6-133, 9-9, 9-17, A-30 Link port service request (LSRQ) register, 6-134, 9-19, A-93, A-98 Link port transmit mask (LxTM) bits, 6-131, A-98 Link port transmit request status (LxTRQ) bits, 6-131, A-98 Logical operations, 2-9 Logical shifts, 2-1, G-11 Long word, 5-25, 5-48, 5-50 Data access, 5-10, 5-48, G-9 Data moves, 5-48 Data storage, 5-2 SIMD mode, 5-80 Single Data, 5-76 SISD Mode, 5-78 Loop, 3-1, 3-22, G-8 Address stack, 3-5, 3-29 Conditional loops, 3-23 Counter stack, 3-30, 3-31 End restrictions, 3-25 Status, 3-30 Termination, 3-3, 3-24, 3-30, 3-31, 3-54 Loop abort (LA) Jump, 3-14, 3-24 Loop address stack, 3-29 Loop address stack (LADDR) register, A-45 Loopback mode, 9-3

ADSP-21161 SHARC Processor Hardware Reference

I-15

INDEX

Loop counter expired (LCE) condition, 3-22, 3-56 Loop counter (LCNTR) register, 3-31, 3-32, A-45 Loop counter stack, 3-30 Loop counter stack, access, A-45 Loops and sequencing, 3-22 Loop stack empty (LSEM) bit, 3-31, A-21 Loop stack overflow (LSOV) bit, 3-31, A-21 Low active transmit frame sync (LFS, LTFS and LTDV) bit, 10-25, A-102 .L unit (See ALU) L unit (See ALU)

M
Mantissa (floating-point operation), 2-9 Masking interrupts, 3-41 Masking interrupts, link port, 9-19 Master In Slave Out (MISO) pin, 11-6 Master mode, 6-48, 6-50 16-bit external transfers, 6-52 32-bit external transfers, 6-51 32-bit internal transfers, 6-54 48-bit internal transfers, 6-53 64-bit internal transfers, 6-53 Controls, 6-51 Internal address/transfer size generation, 6-52 SPI, 11-25 Transfer Size, 6-52 Master mode enable (MASTER) bit, 6-32, 6-47 to 6-66, A-82 Master Out Slave In (MOSI) pin, 11-6, 11-22 Maximum burst length (MAXBL) bit, A-84 Max/Min function, 2-9

Memory, 1-2, 1-11, 5-1, 5-8, 5-16, 5-24, G-7 Access priority, 5-5, 5-39, 5-82 access priority, 5-7 Access types, 5-40, 5-46, G-8 Access word size, 5-47 addressing external memory, A-90 Asynchronous interface, 5-43, G-8 Banked external memory, 7-9 Banks, 5-2, 5-22, 5-38 banks, 5-2 Banks of memory, 7-9, G-8 blocks, 5-2 to 5-8, 5-18, 5-37 blocks, defined, G-8 Booting, 5-23, 5-35 Boot memory, 5-23, 7-10 Boot memory, defined, G-1 Columns of memory, 5-8 Data types, 5-47 Enhancements, 1-18 internal memory addresses, A-43 Mixing 32-Bit & 48-Bit Words, 5-26 mixing 32-Bit and 48-Bit Words, 5-26 mixing 40/48-bit and 16/32/64-bit data, 5-24, 5-31 Mixing word width SIMD mode, 5-84 SISD mode, 5-82 Multiprocessor, 5-19 Synchronous interface, 5-43, G-8 Transition from 32-bit/48-bit data, 5-30 Unbanked memory, 5-22 Memory map restrictions, A-42 Memory mapped devices, 6-12 Memory mapped registers, 5-16, A-47, A-51 Memory read RD pin, 6-54, 7-9, 7-38, 7-89, 7-96, 13-13, 13-16

I-16

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Memory select (MSx) pins, 5-22, 5-39, 7-8, 7-9 to 7-96, 7-97, 7-107, 8-4, 8-8, 8-32, 13-12, A-75 Memory test (MTST) bit, 12-11 Memory test shift (MEMTST) register, 12-2, 12-13 Memory test shift (MEMTST) register , 12-13 Memory transfers, 5-53 16-bit (Short word), 5-54 32-bit (Normal word), 5-62 40-bit (extended-precision normal word), 5-70 64-bit (Long word), 5-76 Message (MSGRx) registers, 7-76, 7-77, A-77 M field, address, A-42 Microprocessor interface, 7-85 -law companding Mnemonics (See instructions) Mode control 1 (MODE1) register, A-3 Mode control 2 (MODE2) register, A-10 Mode control 2 shadow (MODE2_SHDW) register, A-78 Mode mask (MMASK) register, 3-44, 4-14, A-8 Mode register Defined for SDRAM, 8-3 Mode register set (MRS) command, 8-19 Modes, multichannel, 10-2 Modified addressing, 4-10, G-8 Modify address, 4-1, G-8 Modify instruction, 4-14, 4-17 Modify (Mx) registers, 4-2, 4-15, A-47, G-8 Modulo addressing, 1-8 Most significant word first, packing (MSWF) bit, 6-32, 6-42, A-81 Multichannel buffered serial port, McBSP (See serial ports)

Multichannel mode, 10-2, G-11 Multichannel receive channel select (MRCSx) registers, A-114 Multichannel selection registers, 10-57 Multichannel transmit compand select (MTCCSx) registers, A-113 Multifunction computations, 2-34, G-8 Multi-master error (MME) bit, 11-30 Multiple DSP connection to JTAG header illustrated, 13-54 Multiple DSP systems, 13-51 Multiplier, 1-6, 2-1, G-9 Clear operation, 2-18 Input modifiers, 2-21 Instructions, 2-15, 2-20 Operations, 2-15, 2-19 Result (MRF/B) registers, 2-15, 2-16 Rounding, 2-18 Saturation, 2-18 Status, 2-8, 2-19, 2-20 Multiplier fixed-point overflow status (MOS) bit, 2-20, A-19 Multiplier floating-point invalid (MI) bit, 2-19, A-16 Multiplier floating-point invalid status (MIS) bit, 2-20, A-20 Multiplier floating-point overflow status (MVS) bit, 2-20, A-19 Multiplier floating-point underflow (MU) bit, 2-19, A-16 Multiplier floating-point underflow status (MUS) bit, 2-20, A-20 Multiplier negative (MN) bit, 2-19, A-14 Multiplier overflow (MV) bit, 2-19, 3-55, A-15 Multiplier results (MRFx and MRBx) registers, listed, A-24 Multiplier signed (MS) bit, 3-55 Multiplyaccumulator (See multiplier)

ADSP-21161 SHARC Processor Hardware Reference

I-17

INDEX

Multiprocessing Booting, 6-71, 7-108 Bus arbitration, 7-93 Cluster Multiprocessing, 7-90, 7-91 Data flow multiprocessing, 7-90 Direct read and write, 7-109 DSP Interface, 7-87 Interface, 1-14, 1-19 Interface Status, 7-112 Interrupts, 3-49 Local memory, 7-85 Memory, 5-16, 7-3, 7-12, A-43, G-9 Multiprocessing pins, 7-94 Multiprocessing System Architectures, 7-90 SDRAM Dual processor system example, 8-24 SIMD processing, 7-93 SPI booting, 11-42 System, G-9 System architectures, 7-90 Vector interrupt, 3-49, G-9 wand local memory, 7-85 Multiprocessing operation, SDRAM, 8-24, 8-38 .M unit (See multiplier) M unit (See multiplier)

Normal word, 5-25, 5-50 Accesses with LW, G-9 Data access, 5-50 Data storage, 5-2 Mixing 32-bit data and 48-bit instructions, 5-25 Multiprocessor memory, 5-21 SIMD mode, 5-64, 5-68 SISD mode, 5-62, 5-66 Not, Logical, 2-9 Not-a-number (NAN), 2-5 Not Equal (NE), 3-54

O
Open drain drivers Support, 1-15 Operands, 2-5, 2-9, 2-15, 2-23, 2-30, G-3 Operands and results Storage for, A-23 Optimizing cache usage, 3-11 Optimizing DMA throughput, 6-139 Or, Logical, 2-9 Overflow (See ALU, multiplier, or shifter)

P
Paced master mode, 6-48, 6-54 Packed instruction mode (IPACK) bit, A-62 Packing 16- to 32-bit, 7-69 16- to 48-bit, 7-75 32- to 64-bit from host, 7-66 40- to 48-bit from host, 7-74 8- to 48-bit, 7-68, 7-76 Data, 1-12, 6-12, 6-42, 6-49, 6-67, 7-56 External port status, 6-129

N
Nearest, round-to, 2-5 Negate breakpoint (NEGx) bit, 12-9 Nested interrupt routines, 3-3 Nesting Multiple interrupts (NESTM) bit, A-4 No boot mode (NOBOOT) bit, 12-11 Non-counter-based loops, 3-27, 3-28 (See also counter-based loops) NOP command, 8-22, 8-37

I-18

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Packing (continued) Host data packing, 7-59 Link port status, 6-133 Packing mode combinations, 5-102, 7-60 SPI word packing, 11-37 Packing 16-bit to 32-bit Words (PACK) bit, 6-97, 6-98, 6-111, A-101 Packing enable (PACKEN) bit, SPI port, 11-14, A-119 Packing mode (PMODE) bits, 5-36, 6-42, 7-110, A-81 Packing status, external port (PS) bits, 6-127, A-85 Parallel assembly code (See Multifunction computation or SIMD operations) Parallel operations, 2-34, G-8 Pass function, 2-9 PCB transmission line, 13-64 PC stack pointer (PCSTKP) register, 3-20 Peripherals, 1-2, 1-11, 5-7, 7-4, 7-9, 9-1, 9-30, G-7, G-9 connecting to link ports, 9-31 I/O interface to, 10-1 Pin, reset states, 13-22 Pin connections, SDRAM, 8-7 Pin descriptions, 13-2 Pin states at reset, 13-19, 13-22 Pipelined SBSRAMs (See SBSRAM), 7-40 Pipelining with the SDBUF bit, A-75 Plane, ground, 13-68 PLL-based clocking, 13-24 PLL ratios, 13-25 Pod logic DSP 2.5V pod logic, 13-58 Pod logic, DSP 2.5V pod logic, 13-57, 13-59

Pop Loop counter stack, 3-31 Program counter (PC) stack, 3-13 Status stack, 3-45 Porting from previous SHARCs Assembly syntax, 2-31 Booting, 6-70, 6-88 Bus lock, 7-54 Circular Buffer Enable (CBUFEN) bit, 4-4, 4-14 Conditional instructions, 7-10 Instruction Word Transfer (IWT) bit, 7-49 Link ports, 9-1, 9-9 Multiprocessor Memory Space Waitstates (MMSWS) bit, 7-13 Paged DRAM boundary, 7-12 Performance, 2-39 Symbol changes, 1-20 Port rotate rotating DMA channel priority, linkexternal ports (PRROT) bit, 6-24, 6-82, 6-85, A-61 Post-modify addressing, 1-8, 4-1, 4-10, 4-23, G-10 Power sequence, JTAG emulator, 13-56 Power supply, analog (AVDD) pin, 13-5 Power supply, analog return (AGND) pin, 13-5 Power supply, core (VDDINT) pin, 13-16 Power supply, ground (GND) pin, 13-10 Power supply, I/O (VDDEXT) pin, 13-16 Power-up options, SDRAM, 8-19 Precharge command, 8-29, 8-32, 8-33, 8-37, A-74 Precharge command, defined, 8-3 Precision, 1-5, 2-4, 2-5, 2-6, G-10 Pre-modify addressing, 1-8, 4-1, 4-10, 4-23, G-10 Primary registers, 1-9, 2-30

ADSP-21161 SHARC Processor Hardware Reference

I-19

INDEX

Priority Access, 7-103 Fixed and rotating, 7-92 Rotating priority, 7-92 Rotating Priority Arbitration Example, 7-101 Priority, DMA requests (See also DMA channel priority, Rotating priority, and Fixed priority), 6-43 Priority, external port-bus (PRIO) bit, 7-103, A-83 Priority access (PA) pin, 7-89, 7-94, 7-103, 13-13, 13-16, A-83 Priority bus arbitration select, rotating (RPBA) pin, 13-13 Probes, oscilloscope, 13-70 Processing elements, 1-1, 1-6, 1-7, 2-1, 2-31 Processing element Y enable (PEYEN) bit, SIMD mode, 2-4, 2-38, 4-3, 4-6, 4-18, 5-34, 5-39, A-5 Processor clock frequency, 10-1 Processor core, 1-5 Access to link buffers, 9-13 Buses, 1-10, 1-17 Enhancements, 1-17 Program control interrupt (PCI) bit, 6-25, 6-26, 6-67, 6-126 Program counter (PC) register, 3-2, A-41 Program counter (PC) relative address, 3-14, G-3 Program counter (PC) stack, 3-52 Program counter (PC) stack empty (PCEM) bit, 3-53 Program counter (PC) stack full (SOVFI) interrupt, 3-53 Program counter shadow (PC_SHDW) register, A-77 Program counter stack empty (PCEM) bit, 3-53, A-20

Program counter stack full (PCFL) bit, 3-53, A-20 Program counter stack (PCSTK) register, 3-5, A-44 Program counter stack pointer (PCSTKP) register, 3-5, 3-53, A-44 Program fetch (See program sequencer) Program flow, 3-8 Program memory address (PMDAx) register, 12-15 Program memory bus exchange (PX) register, 1-11, 5-10, 5-38, A-25, A-77 Program Memory (PM) bus, 1-2 Program sequence address (PSAx) register, 12-15 Program sequencer, 3-1 to 3-66 Control, 1-7 Latency, 3-5 PSx, DMx, IOx, & EPx (Breakpoint) register, 12-13, 12-15 Pull-down resistors, link port, 9-12 Push Loop counter stack, 3-32 Program counter (PC) stack, 3-13 Status stack, 3-44

R
RAS-to-CAS delay, 8-4, 8-12 Read command, SDRAM, 8-34 Read command, SDRAM, pin state during, 8-35 Read commands, SDRAM, 8-34 Read (RD) pin, 6-54, 7-9, 7-38, 7-89, 7-96, 13-13, 13-16 Reads Direct read latencies, 7-57 Direct reads, 7-109 Direct reads & writes, 7-57 Slave, 7-55

I-20

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Ready-Host Acknowledge (REDY) pin, 6-56, 7-42, 7-44, 7-51, 7-79, 7-89, A-61 Receive clock (RCLKx) pins, 13-16 Receive data buffer status (RXS) bits, 6-138 Receive data (RXx) registers, 6-4 Receive overflow status (ROVF) bit, 6-137 Reciprocal function, 2-9 Refresh command (REF), 8-2, 8-29, 8-30, 8-37, 8-39 Refresh cycle, 8-3, A-74 Register codes JTAG instruction, 12-4 Registers, A-1 to A-121 Boundary, 12-17 data file registers, listed, A-23 Data (R0-R15, S0-S15) registers, A-23 Decode address, 3-2 files, 2-30, 10-10, G-3 files, (See also data register files), 2-30 groups (I/O Processor), A-49 I/O processor registers, listed, A-48 JTAG boundary, 12-18 latency (See latency) load broadcasting (See broadcast load) Memory mapped, A-47, A-51 Neighbor, 5-48, 5-49, 5-76, 5-78, 5-80 Universal (Ureg) registers, 2-40 write file precedence, 2-30 Registers, complementary (See Complementary registers) Registers, neighbor (See neighbor registers) Register-to-register Moves, 2-45, 5-11 Swaps, 2-44, G-10 Transfers, 2-43 Register writes and effect latency, 10-30 Reset interrupt (RSTI) bit, A-27 Reset out (RSTOUT) pin, 13-14

Reset (RESET) pin, 7-89, 13-13, 13-29, 13-61 Input hysteresis, 13-61 Pin states at reset, 13-19 Resistors, Pull-up/down, 13-16, 13-22, 13-54 restrictions on ending loops, 3-25 on short loops, 3-26 restrictions, delayed branch, 3-19 Restrictions on short loops, 3-26 Results (MRF/MRB) registers, 2-32 Return (RTI/RTS) instructions, 3-13, 3-35 ROM boot accessmode (RBAM) bit, A-67 ROM boot waitstates (RBWS) bit, A-67 Rotate bits, 2-23 Rotate (See swap operator) Rotating priority, 6-22, 6-24, 6-44, 6-84 Rotating Priority Bus Arbitration (RPBA) pin, 7-94, 7-98 Rounded output, 2-22 Rounding 32-bit data (RND32) bit, A-5 Rounding mode, 2-4, 2-7, A-5 RS-232 device, restrictions, 10-7 RUNBIST instruction, 12-4

S
SAMPLE instruction, 12-4 Sampling edge for data and frame syncs, 10-43 Saturation (ALU saturation mode), G-10 Saturation maximum values, 2-19 SBSRAM DSP pins, 7-37 Hold off, 7-40 Partial Truth table , 7-39 Signal mapping figure , 7-37 Support, 7-39 Using External SBSRAM, 7-36 Scale (floating-point operation), 2-9

ADSP-21161 SHARC Processor Hardware Reference

I-21

INDEX

SDRAM Accessing, 8-25 Block diagram, 8-24 Calculating the refresh counter, 8-13 Configuring, 8-10 Controller commands, 8-31 controller interface, illustrated, 8-5 Controller standard operation, 8-22 Device densities and page size combinations, 8-28 DMA transfers, 8-37 Dual processor system example, 8-24 page size (SDPGS), 8-18 Page sizes supported, 8-10 Pin connections, 8-7 Powering up after reset, 8-30 Selecting the active command delay, 8-20 Specifications, 8-1 Timing specifications, 8-8 SDRAM A10 (SDA10) pin, 8-8, 13-14 SDRAM address mapping 128 Mbit, 8-28 256 Mbit, 8-28 64 Mbit, 8-27 SDRAM bank cycle time tRTP, 8-4 SDRAM buffer (SDBUF) bit, 8-16, 8-17, A-75 SDRAM burst length, 8-2 SDRAM CAS latency (SDCL) bit, A-73 SDRAM clock enable (SDCKE) pin, 8-8, 8-32, 13-14 SDRAM clock ratio (SDCKR) bit, 8-12, A-75 SDRAM clock (SDCLK) pin, 8-1, 8-6, 8-8, 8-15, 13-14 SDRAM column address select CAS pin, 8-7, 8-32, 13-6 SDRAM controller, 8-22

SDRAM controller (SD) registers, listed, A-50 SDRAM control (SDCTL) register, 8-2 to 8-39, A-73 SDRAM control (SDCTL) register, bit definitions, A-73 SDRAM data mask pin (DQM), 8-7, 13-9 SDRAM device memory bank (SDBN) bit, 8-15, A-75 SDRAM external address (EA) pin, 8-26 SDRAM external memory bank 0 enable (SDEMx) bit, 8-16, 8-37, A-74 SDRAM external memory bank (SDBS), 8-16 SDRAM interface, 1-13, 8-29 SDRAM interface, storing configuration data, 8-11 SDRAM latency mode, 8-33 SDRAM page length, specifying, 8-19 SDRAM page size, defined, 8-3 SDRAM page size (SDPGS) bit, 8-18, 8-19, A-74 SDRAM Parallel refresh command, 8-29 SDRAM power up mode (SDPM) bit, 8-19, 8-32, A-74 SDRAM power up sequence (SDPSS) bit, 8-19, 8-32, A-74 SDRAM refresh counters, 8-24, 8-38 SDRAM refresh counter value (SDRDIV) register, 8-3, 8-13, 8-34, A-72 SDRAM row address select (RAS) pin, 8-8, 8-32, 13-13 SDRAM SDCLK0 disable (DSDCTL) bit, 8-15, A-73 SDRAM SDCLK1 disable (DSDCK1) bit, A-73 SDRAM Self-refresh mode Entering and exiting, 8-31 SDRAM self refresh (SDSRF) bit, 8-20, 8-31, 8-39, A-74

I-22

ADSP-21161 SHARC Processor Hardware Reference

INDEX

SDRAM tras (SDTRAS) bit, 8-21, A-73 SDRAM trcd (SDTRCD) bit, A-75 SDRAM trp (SDTRP) bit, 8-21, A-73 SDRAM write enable SDWE pin, 8-8, 8-32, 13-14 Secondary processing element, 2-37 Secondary registers, 1-9, 2-32, 2-43, 4-4, 4-6, A-4 Secondary registers for computational units (SRCU) bit, 2-33, A-3 Secondary registers for DAGs (SRDxH/L) bits, 4-4, A-3, A-4 Secondary registers for register file (SRRFH/L) bit, A-4 Selecting the frame sync options (FS_BOTH), 10-50 Selecting the I2S transmit and receive channel order (L_FIRST), 10-49 Self refresh command (SREF), 8-3, 8-20, 8-39 Semaphores, 7-57, 7-110, G-10 Sensing interrupts, 3-40 Serial clock (SCLKx) pins, 10-4, 13-14 Serial peripheral interface( See SPI) Serial port, 10-1 to 10-67 Data types, 10-37 Disabling the serial port(s), 10-8 Enabling DMA (SDEN), 10-51 Enabling I2S mode (OPMODE, MCE), 10-49 Enabling master mode (MSTR), 10-50 Interrupts, 10-60 timing example, word select timing in I2S mode, 10-52 Word formats, 10-35 Serial port block diagram, 10-3 Serial port chained DMA enable (SCHEN) bit, 6-97, 6-99, 10-28, A-102 Serial port clock, internal clock (ICLK) bit, A-101

Serial port clock, internal clock ( MSTR) bit, I2S mode only, A-101 Serial port connections, 10-3 Serial port control registers and data buffers, 10-9 Serial port control (SPCTLx) registers, 6-6, 6-96, 10-14, 10-15, A-100, A-101 Serial port count (CNTx) registers, A-113 Serial port current channel selected (CHNL), A-110 Serial port data bufferstatus (DXS_A) bit, A-104 Serial port data direction control (DDIR) bit, A-103 Serial port data independent transmit frame sync (DITFS) bit, A-102 Serial port divisor (DIVx) registers, 10-4, A-112 Serial port DMA chaining, 10-65 Serial port DMA channels, 10-59 Serial port DMA enable (SDEN) bit, 6-15, 6-97, 6-99, 6-109, 10-28, A-102 Serial port DMA interrupt (SPxI) bit, A-29 Serial port DMA parameter registers, 10-61 Serial port DXA data buffer status (DXS_A) bit, 13-10 Serial port DXA error status (DERR_A) bit, A-104 Serial port DXB data buffer status (DXS_B) bit, 13-10, A-104 Serial port DXB error status (DERR_B) bit, A-103 Serial port enable (SPEN) bit, 6-96, 6-109, 6-136, 10-28, A-101 Serial port frame sync ( IFS or IRFS) bit, internal, A-102 Serial port FS both enable (FS_BOTH) bit, A-103 Serial port interrupts, 10-7 Serial port interrupts, priority of, 10-8

ADSP-21161 SHARC Processor Hardware Reference

I-23

INDEX

Serial port interrupt (SPxI) bit, 10-8, A-29 Serial port late frame sync (LAFS) bit, A-102 Serial port loopback, 10-46 Serial port loopback mode (SPL) bit, A-110 Serial Port (LSP) registers, listed, A-50 Serial port multichannel frame delay (MFD) bit, A-109 Serial port multichannel mode enable (MCE) bit, A-109 Serial port multichannel mode pairings SPORT0 and SPORT2, SPORT1 and SPORT3, 10-52 Serial port number of multichannel slots (NCH) bit, A-109 Serial port operation mode (OPMODE), A-101 Serial port operation modes, 10-14, 10-47 Serial port pin/line terminations, 10-66 Serial port receive compand registers (MRxCCSx), A-114 Serial port receive control (SRCTLx) registers, 6-6 Serial port receive data status (RXS_A) bit, A-104 Serial port receive select registers (MRxCSx), A-114 Serial port receive underflow status (ROVF_A) bit, A-104 Serial port registers, listed, 10-10 Serial port reset, 10-8 Serial ports Features, 10-1 Moving data between SPORTS and memory, 10-58 Named, 10-1 Serial port (SPORT), 1-14, G-10 Buffers, 6-97, 6-136, 6-139 DMA, 6-99, 6-100, 6-112 Interrupt-driven transfers, 6-136

Serial port (SPORT) (continued) Multichannel operation, G-11 Priority modes, 6-99 Status, 6-135 Transfer modes, 6-99 Serial port transmit buffer (TXx) registers, A-111 Serial port transmit compand registers (MT2CCSx and MT3CCSx), A-113 Serial port transmit data status (TXS_A) bit, A-104 Serial port transmit select registers (MT2CSx and MT3CSx), A-113 Serial port transmit underflow status (TUVF_A) bit, A-104 Serial port Word length, 10-36 Serial scan path, 12-5 Serial scan paths, 12-5 Serial shift register (EMUPX), 12-6 Serial test access port (TAP), 12-1 Serial word endian (SENDN) bit, 6-96, 6-97, 10-28, A-101 Serial word length (SLEN) bits, 6-96, 6-97, 6-109, 6-111, 10-28, 10-49, A-101 Set, bit, 2-23 Setting serial port modes, 10-9 Setup time, inputs, 13-19 S field, address, A-42 Shadow write FIFO, 5-23, 7-58 SHARC, G-11 Background information, 1-16 (See also Porting from previous SHARCs) SHARC ICE hardware, compatibility, 12-7 Shift bits, 2-23 Shifter, 1-6, 2-1, 2-23, G-11 Instructions, 2-28 Operations, 2-23, 2-27 Status flags, 2-27 Shifter input sign (SS) bit, A-17 Shifter operations, A-17

I-24

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Shifter overflow (SV) bit, 3-55, A-17 Shifter zero (SZ) bit, 3-55, A-17 Short (16-bit data) sign extend (SSE) bit, 2-4, 5-51, A-5 Short word, 5-25, 5-51 Data access, 5-51 Data storage, 5-2 SIMD mode, 5-56, 5-60 SISD mode, 5-54, 5-58 Signal For Cluster Multiprocessor Systems , 7-89 Signal integrity, 13-66 Signal skew, minimizing, 13-54 Signed data, 2-6 Signed input, 2-22 Sign extension, A-5 Silicon revision number, A-78 SIMD mode, 3-54, 5-51, A-5 Complementary registers, 2-40 Computational operations, 2-43 Defined, 2-37 Implicit operations, 2-40 Multiprocessing, 7-93 Status flags, 2-46 Single serial shift register path, 12-1 Single-step (SS) bit, 12-8 Single-word transfers, 10-65, G-11 SISD mode, 5-51 Defined, 1-7 Unidirectional register transfer, 2-45 Slave direct reads and writes (See direct read and direct write) Slave mode, 6-48, 6-55, 6-144 Operation, 6-55 SPI, 11-28 Transfer size, 6-57 Slave reads and writes, 7-55 Slave write FIFO, 7-50 Slave write FIFO data pending (SSWPD) bit, synchronous, A-70

Slave write latency, 7-56 Slave write pending (SWPD) bit, 7-112, A-70 Software interrupt x, user (SFTxI) bit, A-31 Software reset (SRST) bit, A-60 Software reset (SYSRST) bit, 12-8 Specifications, timing, 13-25 SPI Block diagram, 11-2 Boot loader kernel, 11-35 Configuring and enabling, 11-9 Data word formats, 11-21 Disabling the SPI system, 11-30 DMA, 11-32 Error signals and flags, 11-29 Examples, programming, 11-44 Features, 11-1 Functional description, 11-2 hang in receive data buffer, A-121 Interface, enabling, 11-9 IOP registers, 11-9 Master mode, 11-25 Master mode DMA operation, 11-32 Master mode operation, 11-25 Slave mode, 11-28 Slave mode DMA operation, 11-28, 11-33 system, configuring and enabling, A-117 Transfer formats, 11-15, 11-21 SPI baud rate (BAUDR) bit, 11-12, A-118 SPI clock phase (CPHASE) bit, 11-12, A-117 SPI clock polarity (CP) bit, 11-12, A-117 SPI clock rate (SPICLK) pin, 11-3, 11-22, 13-15 SPI control (SPICTL) register, 11-4, 11-9, 11-21, 11-25, 11-42, A-117 SPI data fetch (GM) bit, 11-14, A-119 SPI data format (DF) bit, 11-12, A-117

ADSP-21161 SHARC Processor Hardware Reference

I-25

INDEX

SPI device select SPIDS pins, 11-4 to 11-33, 13-15 SPI enable (SPIEN) bit, 11-12, A-117 SPI flag select (FLS) bit, 11-13, A-118 SPI interrupt (LIRPTL) register, A-34 SPI master in slave out (MISO) pin, 13-12 SPI master out slave (MOSI) pin, 13-12 SPI master select (MS) bit, 11-12, A-117 SPI MISO pin disable (DMISO) bit, 11-13, A-119 SPI multimaster error (MME) bit, 11-17, A-115 SPI open drain output enable (OPD), 11-13, A-119 SPI packing enable (PACKEN) bit, 11-14, A-119 SPI Port (LSP) registers, listed, A-50 SPI programmable slave select enable (PSSE) bit, 11-13, A-118 SPI receive data buffer (SPIRX), 11-9, 11-20, A-120 SPI receive DMA enable (RDMAEN) bit, 11-14, A-119 SPI receive DMA interrupt latch (SPIRI) bit, A-34 SPI receive DMA interrupt mask pointer (SPIRMSKP) bit, A-36 SPI receive DMA interrupt mask (SPIRMSK) bit, A-35 SPI reception error (RBSY) bit, 11-19, 11-31, A-116 SPIRX interrupt enable (SPRINT) bit, 11-12, A-117 SPI seamless operation (SMLS) bit, 11-13, A-118 SPI selection of SPIDS (DCPH0), 11-13, A-118 SPI send zero (SENDZ) bit, 11-14, A-119 SPI shift register, 11-21, 11-25 SPI sign extend (SGN) bit, 11-14, A-119

SPI status (SPISTAT) register, 11-9, 11-15, 11-30, A-115, A-121 SPI transfer complete (SPIF) bit, 11-17, A-115 SPI transmission error (TXE) bit, 11-30 SPI transmit buffer (SPITX) register, 11-9, 11-20, A-121 SPI transmit DMA enable (TDMAEN) bit, 11-12, A-118 SPI transmit DMA interrupt latch (SPITI) bit, A-34 SPI transmit DMA Interrupt mask pointer (SPITMSKP) bit, A-36 SPI transmit DMA interrupt mask (SPITMSK) bit, A-35 SPITX interrupt enable (SPTINT) bit, 11-12, A-117 SPI word length (WL) bit, 11-12, A-117 SRAM (memory), 1-2 SREF command, pin state during, 8-40 Stacking status during interrupts, 3-44 Stack overflow/full interrupt (SOVFI) bit, A-27 Stacks and sequencing, 3-52 Status, 5-46 Host interface, 7-76 Link port, 9-13 Status registers, 3-3 Status stack, 3-44 Pop, 3-45 Push, 3-44 Status stack empty (SSEM) bit, 3-44, A-20 Status stack overflow (SSOV) bit, 3-44, A-20 Sticky status (STKYx/y) registers, 2-8, 2-20, A-16, A-18, A-19 Subroutines, 3-1, G-11 Subtract/add, 2-9 Subtract instructions, 2-36 Subtract/multiply, 2-1, G-9

I-26

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Subtract with borrow, 2-9 .S unit (See shifter) S unit (See shifter) Suspend Bus Three-state (SBTS) pin, 7-44, 7-54, 7-83, 7-89, 13-14 Swap register operator, 2-44, G-10 Switching frequencies, determining, 13-26 Synchronous access mode, 5-43, 7-6, 7-11, 7-12, 7-14, 7-44, 7-94, 13-16, G-8 Burst Interface timing, 7-26 Burst Length determination, 7-29 Burst Mode Interface Timing, 7-26 Burst read, external port buffers, 7-58 Burst Readsbus master, 7-31 Burst Read/Writebus slave, 7-26 Burst Stall Criteria, 7-29 Burst Writesbus master, 7-33 example of synchronous write followed by synchronous read, 7-25 Interface timing, 7-18 Readbus master, 7-20 Read/Writebus slave, 7-18 Synchronous Mode Interface Timing, 7-18 Write, One Waitstate Mode, 7-25 Write, Zero-Waitstate Mode, 7-22 Synchronous Burst Static RAM (See SBSRAM) Synchronous transfers, G-11 System, multiprocessor system diagram, 7-87 System bus, processor core access to system bus, 7-82 System bus interfacing, 7-78 System configuration (SYSCON) register, 6-6, A-60 System control (SC) registers, listed, A-49

System design Considerations for flags, 13-38 Designing for high frequency operation, 13-62 Designing for JTAG emulation, 13-49 Determining clock period, 13-28 Layout requirements, 13-54 layout requirements for routing signals, 13-54 Pod specifications, 13-56 Point-to-point connections, 13-65 Recommendations and suggestions, 13-68 System (Sreg) registers, A-2 System (Sreg) registers, program sequencer, A-26 System status (SYSTAT) register, 7-76, A-69

T
TAP pin, 12-3 Target board connector, 13-50 Target board connector, for emulator probe, 13-50 TCB chain loading, 6-24, 6-25, 6-26, G-11 Termination, end-of-line termination restrictions, 13-64 Termination codes (See condition codes and loop termination) Termination values, link port, 9-30 Test, bit, 2-23 Test access port (TAP) (See JTAG port) Test clock (TCK) pin, 12-3, 13-41 Test data input (TDI) pin, 12-3, 13-41 Test Data Output (TDO) pin, 13-41 Test flag (TF) condition, 3-54, 3-55 Test logic reset (TRST) pin, 12-3, 13-16, 13-41 Test mode select (TMS) pin, 12-3, 13-16, 13-41

ADSP-21161 SHARC Processor Hardware Reference

I-27

INDEX

Test mode (TMODE) bit, 12-11 Time-Division-Multiplexed (TDM) mode, 1-14, 10-1, G-11 Timed release bus mastership, 7-92 Timeout, bus mastership, 7-101 Timer, 1-9, 3-50, 8-3 Timer and sequencing, 3-50 Timer count (TCOUNT) register, 3-50, A-46 Timer enable (TIMEN) bit, 3-50, A-10 Timer expired high priority (TMZHI) bit, 3-51, A-28 Timer expired low priority (TMZLI) bit, 3-51, A-30 Timer expired (TIMEXP) pin, 13-15, 13-33 Timer period (TPERIOD) register, 3-50, A-46 Timing External Memory Accesses, 7-13 External port, 7-1 Link port handshake, 9-10 SDRAM, 8-8 Specifications, System design, 13-25 Toggle, bit, 2-23 Token passing Link ports, 9-27 Token passing, link ports, 9-27 Top-of-loop address, 3-23 Top-of-PC stack, 3-53 Transfer control block (TCB), 6-12, 6-26, G-12 Transmit and receive data buffers (TXA/B, RXA/B), 10-30 Transmit data status (TXS) bit, 10-23 Transmit data (TXx) registers, 6-4 Transmit frame synch divisor (TFSDIV) bit, A-112 Transmit frame sync required (TFSR) bit, 10-27

Transmit/receive DMA, external port (TRAN) bit, 6-32, A-81 Transmit underflow status (TUVF) bit, 6-137, 10-23 Tristate versus three-state, G-12 True always (TRUE) if condition, 3-56 Truncate, rounding (TRUNC) bit, 2-4, A-5 Twos-complement data, 2-6, 2-10 Type, data (See data types)

U
Unaligned 64-bit memory access (U64MA) bit, 5-34, 5-41, A-11, A-20 Underflow exception, 2-5 Underflow (See multiplier) Unified address space, 1-12 Universal (Ureg) registers, 1-10, 2-40, 5-10, A-26, A-46, G-12 Control and status, A-2 Data Address Generator, A-46 Processing element, A-23 Program Sequencer, A-26 Unpacked data, 6-42, 7-56 Unsigned data, 2-6 Unsigned input, 2-22 Unsupported instructions, IPCODE, 12-4 UPDATE state, 12-5 USERCODE instruction, unsupported, 12-4 User-defined status (USTATx) registers, A-22 Using the cache, 3-11

V
Values, saturation maximum, 2-19 Vector interrupt, 1-13, G-9 Vector interrupt, multiprocessor (VIRPTI) bit, A-28

I-28

ADSP-21161 SHARC Processor Hardware Reference

INDEX

Vector interrupt address (VIRPTA) bit, A-64 Vector interrupt address (VIRPT) register, 3-49, 6-126, 7-77, 7-78, A-63 Vector interrupt data optional (VIRPTD) bit, A-64 Vector interrupt pending (VIPD) bit, A-69 Vector interrupts, 7-77 Host, 7-78 Interprocessor, 7-76 Von Neumann architecture, 5-4, G-12

Word rotations, 5-25 Wrap around, buffer, 4-9, 4-12, 4-15 Write commands, SDRAM, 8-34, 8-36 Writes Direct reads & writes, 7-110 direct write, asynchronous interface, 7-56 Slave, 7-55 Write (WR) pin, 6-54, 7-9, 7-38, 7-89, 7-96, 13-16

X W
Waitstates, 1-12, 5-42, 5-45, 7-12, 7-19, G-12 Waitstates and access mode (WAIT) register, 6-6, 8-16, A-65, A-66 Web site, 1-21 Xor, Logical, 2-9

Z
Zero, round-to, 2-5

ADSP-21161 SHARC Processor Hardware Reference

I-29

INDEX

I-30

ADSP-21161 SHARC Processor Hardware Reference