Scribd
Upload
226 views

4-Tap FIR Flter VHDL Error-HELP!!!!

Hi, I wrote a vhdl code for a 4 tap fir filter. I am not getting errors when I compile using altium designer. But when I put in Xilinx ISE 9.2i i'm getting an error saying " Line 34. Choices for an array aggregate (Attribute name) must be locally static unless there is only one choice. (LRM 7.3.2.2) which I don't understand. Can someone please help!!

Uploaded by

Tottem Ramana
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
226 views

4-Tap FIR Flter VHDL Error-HELP!!!!

Hi, I wrote a vhdl code for a 4 tap fir filter. I am not getting errors when I compile using altium designer. But when I put in Xilinx ISE 9.2i i'm getting an error saying " Line 34. Choices for an array aggregate (Attribute name) must be locally static unless there is only one choice. (LRM 7.3.2.2) which I don't understand. Can someone please help!!

Uploaded by

Tottem Ramana
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

User Name

Password

Log in

Register

Lost password?

Resend activation?

Remember Me?

Forum
New Posts Blogs

Activity Stream
Unansw ered Posts What's New?

Search
FAQ

Help

Rules
Com m unity

Groups

Albums

Forum Actions

Quick Links Advanced Rules Forum Search

Forum

Digital Design and Programming

PLD, SPLD, GAL, CPLD, FPGA Design

4-tap FIR flter vhdl error-HELP!!!!

+ Post New Thread


Thread: 4-tap FIR flter vhdl error-HELP!!!!
LinkBack Thread Tools

Results 1 to 3 of 3

Search Thread

08-04-10, 18:41

#1

vampiro
Newbie level 3 Join Date: Posts: Helped: Feb 2010 4 0/0

4-tap FIR flter vhdl error-HELP!!!!


Hi, I wrote a VHDL code for a 4 tap fir filter. I am not getting errors when I compile using altium designer. but when I put in Xilinx ISE 9.2i I'm getting an error saying " Line 34. Choices for an array aggregate (Attribute name) must be locally static unless there is only one choice. (LRM 7.3.2.2) which I don't understand. Can someone please help!! I need to solve this ASAP this is the whole code... Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity FIR_Test is GENERIC (n:INTEGER:=4; m: INTEGER :=4); Port (x:in SIGNED(m-1 downto 0); clk,rst:in std_logic; y:out SIGNED(2*m-1 downto 0)); end FIR_Test; ARCHITECTURE RT1 of FIR_Test is TYPE registers IS ARRAY (n-2 DOWNTO 0) OF SIGNED(m1 DOWNTO 0); TYPE coefficients IS ARRAY (n-1 DOWNTO 0) OF SIGNED (m-1 DOWNTO 0); SIGNAL reg : registers; CONSTANT coef: coefficients :=("0001" , "0010" , "0011" , "0100"); BEGIN PROCESS(clk,rst) VARIABLE acc, prod: SIGNED(2*M-1 DOWNTO 0) := (OTHERS=> '0'); VARIABLE sign : STD_LOGIC; BEGIN IF (rst='1') THEN FOR i IN n-2 DOWNTO 0 LOOP

FOR i IN n-2 DOWNTO 0 LOOP FOR j IN m-1 DOWNTO 0 LOOP reg(i)(j) <= '0'; END LOOP; END LOOP; ELSIF (clk'EVENT AND clk = '1') THEN acc := coef(0)*x; FOR i IN 1 TO n-1 LOOP sign := acc(2*m-1); prod := coef(i) * reg(n-1-i); acc := acc + prod; IF (sign=prod(prod'left)) AND (acc(acc'left) /= sign)THEN acc := (acc'LEFT => sign, OTHERS => NOT sign); END IF; END LOOP; reg<= x & reg(n-2 DOWNTO 1); END IF; y<= acc; END PROCESS; END rt1;
Reply With Quote

09-04-10, 08:58

#2

devas
Full Member level 2 Join Date: Posts: Helped: Jun 2009 129 40 / 40

Re: 4-tap FIR flter vhdl error-HELP!!!!


Hi, The width of the variable 'acc' depends on the generic M. As you use 'LEFT to assign a value to acc, the bit number of this assignment depends on the generic M and can be different for several instantiations of this fir_test and is therefor not "locally" static. Devas

Reply With Quote

07-06-10, 19:39

#3

MarcosMedeiros
Newbie level 2

4-tap FIR flter vhdl error-HELP!!!!


VAMPIRO, What did you do to run that filter? I had this same problem on ISE 10.1 to run on a STARTAN 3-E The code, that is generic, it's no more generic, because I declared the generics m and n inside the architecture, and I replaced the integer values of m and n inside some parts of the process. I'm looking for a solution for make this code generic again. Do you know how? Here I used my fixed-point version: ----------------------------------------------------------------------------------------------------------------LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.std_logic_arith.ALL; ----------------------------------------------------------------------------------------------------------------LIBRARY work; USE work.fixed_pkg.all; USE work.math_utility_pkg.all; ----------------------------------------------------------------------------------------------------------------entity Fir_Circular_Fixo is -- GENERIC( m: INTEGER := 2; -- Nmero de bits das entradas e dos coeficientes() -- NumCoef: INTEGER := 8; -- Nmero de coeficientes -- dec: INTEGER := 6 -- Nmero de bits da parte decimal do nmero -- ); PORT( ClockFIR, Reset: IN STD_LOGIC; x: IN UFIXED (2-1 DOWNTO -6); y: OUT UFIXED (2*2-1 DOWNTO -(2*6)) );

Join Date: Location: Posts: Helped:

Jun 2010 Fortaleza, Brazil 2 0/0

end Fir_Circular_Fixo; architecture Behavioral of Fir_Circular_Fixo is TYPE Registradores IS ARRAY (8-2 DOWNTO 0) OF UFIXED ((2+6-1) DOWNTO 0); TYPE Coeficientes IS ARRAY (8-1 DOWNTO 0) OF UFIXED (2-1 DOWNTO -6); SIGNAL Vetor_Retardo: Registradores; SIGNAL m: INTEGER := 2; -- Nmero de bits das entradas e dos coeficientes SIGNAL NumCoef: INTEGER := 8; -- Nmero de coeficientes SIGNAL dec: INTEGER := 6; -- Nmero de bits da parte decimal do nmero CONSTANT Coef : Coeficientes := ("00000000", "01000000", "10000000", "11100000", -- Impulso "11000000", "10000000", "01000000", "00000000"); ----------------------------------------------------------------------------------------------------------------BEGIN PROCESS (ClockFIR, Reset) VARIABLE accum, prod: UFIXED(2*2-1 DOWNTO -(2*6));- := (OTHERS => '0'); VARIABLE sinal : STD_LOGIC; BEGIN -- Reset: Zera a linha de retardo do filtro FIR IF (Reset = '1') THEN FOR i IN 8-2 DOWNTO 0 LOOP FOR j IN (2+6)-1 DOWNTO 0 LOOP Vetor_Retardo (i)(j) <= '0'; END LOOP; END LOOP; -- Incrementa o estado e desloca o vetor de retardo. ELSIF (ClockFIR'EVENT AND ClockFIR = '1') THEN accum := coef(0) * x; FOR ii IN 1 TO 8-1 LOOP sinal := accum(2*m-1); prod := coef(ii) * Vetor_Retardo(NumCoef-1-ii); accum := resize(accum + prod, y'high, y'low); -- Verificao de overflow IF (sinal = prod(prod'LEFT)) AND (accum(accum'LEFT) /= sinal) THEN accum := (accum'LEFT => sinal, OTHERS => NOT sinal); END IF; END LOOP; Vetor_Retardo <= x & Vetor_Retardo(8-2 DOWNTO 1); END IF; y <= accum; END PROCESS;

end Behavioral;

Reply With Quote

+ Post New Thread


Trouble using Spartan 3A Starter Kit and USB to JTAG cable | 1553 decoder implementation on fpga
Similar Threads
need help in these Flter Questions (1) Why I have If-then VHDL errors in my code? (15) Help: EN5360 EMI flter?? (0) narraw band active bandpass flter (1) Reson for loss of highpass flter (6)

-- Edaboard Classic

Contact Us Forum for Electronics Privacy Statement Terms of Service Top


All times are GMT +1. The time now is 16:41. Powered by vBulletin Copyright 2010 vBulletin Solutions, Inc. All rights reserved. SEO by vBSEO 2011, Crawlability, Inc.

You might also like