CHAPTER - 3 DESIGN

CHAPTER 3 DESIGN 3.1 Design of Secure hash algorithm: The main object of the secure hash algorithm (SHA-x) is to implement Security as well as digest of the given input data for the data integrity. The secure hash algorithm (SHA-x) can be described in three stages: preprocessing, message schedule, and message digest calculation. Preprocessing involves padding a message, parsing the padded message into 512-bit blocks, and setting initialization values used in the hash computation. Each padded 512-bit block is then expanded to form the message schedule. The message digest uses the message schedule, along with functions, constants, and word operations to iteratively generate a series of hash values. Each schedule is added to the current intermediate hash value, where the initialization vectors determine the initial hash value. The final hash value generated by the hash computation is used to determine the message digest. The security is done by padding and message schedule process based hash algorithm. In the message digest calculation are done by word computation (Wt), non linear function and standard initial hash values of secure hash algorithm. 3.2 Specifications: Security Padding Parsing Message schedule Message digest

3.3 General block diagram of SHA-1: Input message or data length is 64-bit data, this 64-bit data is generated by the preprocessor block. The output of preprocessor block

produced 512-bits data. That 512-bit is applied to an input for message scheduler block. Then message scheduler block expanding a 512-bit input message block into 2560-bit output block. Then 2560-bit and internal hash values (160-bit) are applied to Message digest (MD) block as input. Then message digest generated and produced an output of 160-bit fixed hash value which is shown in Fig 3.1.

Fig 3.1: GENERAL BLOCK DIAGRAM OF SHA-x

3.4 Pre-Processing: Pre-processing means performed on raw data to prepare it for another processing procedure. This preprocessing consists of three steps: 1. Padding the message 2. Parsing the padding message into message blocks. 3. Setting the initial hash values. 3.4.1 Padding the message: The purpose of padding is to ensure that the message is a multiple of the block size; 512-bits before hash computation begin. For a message, M, of length l bits, padding is carried out in the following manner. First 3-bits are given as abc in ASCII format. Afterwards

append the bit 1 to the end of the message, followed by k zero bits, where k is the smallest, non-negative solution to the equation: l +1+k=512 mod 448.Then append the 64-bit block representing the size of the original message at last as shown in Fig 3.2 and Fig 3.3.

Fig 3.2: Padding the message block

Fig 3.3: Padding the message as stream of bits

3.4.2 Parsing the padding message into message blocks:

After message is padded, it must be divided into N into M-bit blocks before the hash computation begin. The padded message is divided into N * M-bits equal to 512-bits block i.e. M1, M2, M3 ..M16. Since the 512 bits of the input block may be expressed as sixteen 32bit words, the first 32-bits of message block is M1, second is M2, so on up to last is M16. For example 512-bits are parsing into 16 * 32-bits as shown in Fig 3.4. Input 512-bits:-61626310000000000000..0510a4571337890b2 M1=61626310, M2=00000000, M3 =00000000, M4 =00000000, M5 =00000000, M6 =00000000, M7 =00000000, M8 =00000000, M9 =00000000, M10=00000000 M11 =00000000, M12 =00000000, M13 =00000000, M14 =00000000 M15=510a4571, M16 =337890b2.

Fig 3.4: Parsing the message block

3.4.3 Setting the initial hash values: Before hash computation begins for each of the secure hash algorithms, the initial hash value must be set. These initial hash values are standard hash values developed by National Institute of Standards Hash Buffer H0 H1 H2 H3 H4 Hash Value X67452301 XEFCDAB89 X98BADCFE X10325476 XC3D2E1F0

and Technology (NIST). The size and number of words depends on the message digest size. The initial hash values are hexadecimal values as shown in below Table 1.

Table 1: Initial hash values.

3.5 Developed Architecture of Message scheduler block: With the help of below equation, the message scheduler block diagram is design which is shown in Fig 3.5. Mt Wt = ROTL1 (Wt-3 Wt-8 Wt-14 Wt-16) 0<t<15 16<t<79

Message scheduler block diagram consist of one multiplexer, 16 registers, one xor gate and one rotate left module. The messagescheduling unit of the SHA-x algorithm consists of expanding a 512-bit message block into 2560-bit block. One 32-bit word, (Wt) will be delivered to the message digest unit for digest in each of the 80 iterations. The multiplexer (MUX) is used for selection purpose of data. When multiplexer (MUX = 1 )the data(i.e. 512 -bits input) will stored in registers , in each register it stores 32-bits data , total 16 registers (i.e.R1,R2,R3,.. R16) it stores 512-bits data .the first 32-bits data will be stored in last R16 register, second 32-bits data will be stored in R15 register and so on up to last 32-bits data will be stored in first R1 register. The message schedule is prepared by expanding the divided 512-bit data block to a sequence of eighty 32-bit words. After storing the data in registers the output is taken from 4 register (i.e. R3, R8, R14, R16) and each resister is 32-bit, given to the input for xor gate. The xor gate produced an output of 32-bits data, that 32-bits data is given an input for rotate left one bit module (ROTL1) here the rotate left module rotates one bit to most significant position, that output is given to multiplexer .when multiplexer (MUX = 0 ) the output of data will be stored in register R1. Before when (MUX = 1 )in register (R1) there will be some other data that data will be move to register (R2),(R2 move to R3) then( R3 move to R4) then (R4 move to R5) so on

up to (R15 move to R16) just like first in first out (FIFO) process . This process will be continued up to another 64 iterations to find word computation (Wt) for message digest unit.

M e ssa g e W o rd Mt
R0 R1

Wt

R2 R3 R4 R5 R6 R7 R8 R9 R 10 R 11 R 12 R 13 R 14 R 15

R O X

R O T 1L

Fig 3.5: Message scheduler block diagram

3.5 Developed Architecture of Word computation block: Input to the word computation (Wt) is 32-bits which is taken from 16 words i.e 512-bits. From the block of 16 words selecting 4 words with the of equation as shown in above fig 3.5 and generated then afterward xored. The xored gate output is 32-bits which are given as input for rotate left block. Rotate left one bit module (ROTL 1) rotates one bit to most significant position, that output is stored in register (i.e. 17th word). This operation will be done for up to another 64-times as shown in fig 3.6.

Fig 3.6: Word computation block diagram

3.6 Developed Architecture of Message digest single round: The message digest computation for single round is described using two buffers, each consisting of five 32-bit words. The words of the first 5-word buffer are labeled A, B, C, D, and E. The words of the second 5word buffer are labeled working variables temporally A, B, C, D, and E. Before processing any blocks, the initial hash values are initialized as follows in hexadecimal.

A = 67452301 B = EFCDAB89 C = 98BADCFE D = 10325476 E = C3D2E1F0. With the help of below equation, the message digest single round architecture is developed. . For t = 0 to 79 do TEMP = ROTL5 (A) + Ft (B, C, D) + E + Wt + Kt; E = D; D = C; C = ROTL30 (B); B = A; A = TEMP; Here word computation (Wt) is an external input for message digest i.e. is 32-bits and internal input is 160-bits i.e. are standard initial hash values. The message digest sequentially processes each message schedule under a set of operations, are used to forming intermediate hash values. The set of operation are rotate left module, word computation (Wt), constant (Kt), and non linear function (Ft). The output of single round message digest is 160-bits hash value which is stored in second 5-word buffer are labeled working variables temporally A, B, C, D, and E as shown in Fig 3.7. SHA-1 uses a sequence of eighty constant 32-bit words, K0, K1.. K79 and eighty non-linear functions which are shown in the table 2 and table 3. The constant values are in hexadecimal format, which are standard values.

Fig 3.7: Message digest single round diagram

Constant Value X5A827999 X6ED9EBA1 X8F1BBCDC XCA62C1D6

Step (0 -to -19) (20 -to -39) (40 -to -59) (60 -to -79)

Table 2: SHA-x constants values

Fig 3.8: SHA-x non-linear functions

Table 3: SHA-x non- linear functions

3.7 Developed Architecture of Message digest N round: The message digest N round architecture is shown in Fig 3.9. Input data length is 160-bit data given as initial hash value (IV 0, IV1, IV2, IV3 and IV4) this 160-bit data is generated by the first round and produced an output of 160-bits. That first round output of 160-bits is given as input for second round and produced an output of 160-bits and so on up to N rounds. Finally the N round output is added with initial hash values and produced hash output of 160-bits (H0, H1, H2, H3, and H4).

Fig 3.9: Message digest N diagram.

3.8 Developed VLSI Architecture of Secure hash algorithm (SHA-x): The VLSI architecture of secure hash algorithm (SHA-x)is shown in Fig 3.10. Here the external input data length of message block size (Mi) is 512-bits and standard initial hash values (Hi) is 160-bits length is applied.SHA-x requires the operation of 80 rounds which can be grouped into 4 groups, 20 rounds each. Each round operates on five 32 bits hashing words (H0 to H4 which have A to E as their temporary versions. Functions and constants are basic operation of each round.

Those constants are round constants (Kt) and message word computation (Wt).Total four groups, each group it uses different function, different constant value (Kt) and different word computation (Wt).The output of 80th round is added with initial hash value (A, B, C, D and E) to get final output.

Fig 3.10: VLSI architecture of secure hash algorithm (SHA-x):

Table 4: Secure hash algorithm inputs-outputs