M

Author: Rick Stoneking, Anadigics, Inc.

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SYSTEM DESCRIPTION
Overview
Figure 1 shows the block diagram of the overall system. There are two functional blocks. The first is the Control Logic block. This function is performed by the PIC12C672 microcontroller. The PIC12C672 was chosen because of the low pin count and powerful feature set, which includes an internal oscillator, on-board, multi-channel, 8-bit analog-to-digital converter (ADC), multiple interrupt sources and low power sleep mode. The second is the CAN interface block. This block is comprised of the MCP2510 CAN controller and the MCP2551 transceiver. The MCP2510 provides a full CAN 2.0 implementation with message filtering, which relieves the host microcontroller from having to perform any CAN bus related overhead. This is a key feature given the limited available code space of the PIC12C672.

A Simple CAN Node Using the MCP2510 and PIC12C67X

INTRODUCTION
This application note describes the design, development and implementation of a smart, low cost, standalone Controller Area Network (CAN) node. It combines the Microchip 8-pin PIC12C672 microcontroller with the Microchip 18-pin MCP2510 stand-alone CAN controller. This creates a fully autonomous CAN node, which supports both time-based and event driven message transmission. The node is interrupt driven, capable of monitoring five external inputs (two analog and three digital) and automatically generating messages based upon their value, controlling two digital outputs, responding to message requests via the CAN network and generating a repeating, time-based message. The system supports a maximum CAN bus speed of 125 kbits per second, with both standard or extended frames. The system is presented using standard frames. Some code changes would be required to implement extended frames. This application note focuses on the design and development of the node from the system level. No discussion of the nature of the analog signals is presented. The digital inputs are, simply, switch contacts whose purpose is left for the reader to define. This application note concentrates on the unique requirements of implementing the CAN node functions using an I/O limited microcontroller and a stand-alone CAN protocol controller.

FIGURE 1:
Control Logic

CAN NODE BLOCK DIAGRAM

CAN Interface

PIC12C672

MCP2510

MCP2551 CAN Bus

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Communication between the Control Logic block and the CAN interface block implements the MCP2510s built-in support for the SPI protocol. The PIC12C672 does not have a hardware SPI interface, so the necessary functions are implemented in firmware. Two external analog signals are tied directly to the analog input pins of the PIC12C672. An A/D conversion is performed automatically for analog channel 0 (AN0), based upon the internal timer setup. The value is automatically transmitted over the CAN bus once the conversion is completed. The node also utilizes the MCP2510s multiple filters to respond to four additional CAN Message Identifiers received via the CAN bus. The masks and filters are set to accept messages into receive buffer 1 only. The identifiers are interpreted as one of the following, depending upon which filter is matched: Read Analog Channel 1 - Perform A/D conversion for analog channel 1 (AN1) and initiate transmission of the value back to the requesting node Read Digital Inputs - Read the value of the MCP2510 input pins and transmit the value back to the requesting node Update Digital Output 1 - Write the received value to the MCP2510 digital output 1 Update Digital Output 2 - Write the received value to the MCP2510 digital output 2 Since only receive buffer 1 is used, the mask registers for receive buffer 0 must all be set to a 1. This action should be followed by setting the filter bits to match an unused message indentifier (typically all '0' or all '1') in order to take advantage of the greater number of filters associated with that receive buffer.

TABLE 1:
ID 3F0 3F1 3F2 3F3 3F8 3F9 3FA 3FB 3FE 3FF Tx/Rx Rx Rx Rx Rx Tx Tx Tx Tx Tx Tx

MESSAGE IDENTIFIERS
Description Read Analog Channel 1 Read Digital Inputs Change Digital Output 1 Change Digital Output 2 Analog Channel 1 value Current values of digital inputs 3F2 Command Acknowledgement 3F3 Command Acknowledgement Analog Channel 0 value System Error

HARDWARE DESCRIPTION
Design/Performance Considerations
When designing a system, there are a number of design considerations/tradeoffs/limitations that must be taken into account. Proper selection allows the system to achieve optimal performance from available resources and to determine if the desired performance can be achieved. The overall performance of the system is a function of several things: The system clock rate The throughput of the SPI bus Interrupt latency External interrupt request frequency

System Clock
The PIC12C672 has only six available I/O pins and all of these are used. Two for analog inputs and four (three SPI and one INT) to interface to the MCP2510. This requires the system to take advantage of the internal RC oscillator of the PIC12C672. The internal RC oscillator provides a 4 MHz system clock to the microcontroller, which translates to a 1 s instruction cycle. The instruction cycle time directly affects the achievable speed of the SPI bus. This, in turn, determines the interrupt latency time as SPI communication makes up the majority of the time required for the Interrupt Service Routing (ISR).

Message Identifier Format

As presented, the system requires that messages intended for the node have a standard identifier which has a value of 0x3F0 to 0x3F3, with each of the four filters configured to accept one of these messages. For messages the node returns, it uses the same identifier as the received message, with the exception that the ID3 bit is set to a 1. Therefore, when the Read Analog Channel 1 message is received (ID=0x3F0), the node returns the data using a message ID of 0x3F8. The time-based message for the value of analog channel 0 is transmitted with an identifier of 0x3FE. If a system error is detected, the system error message uses the identifier 0x3FF. Table 1 summarizes the various transmit and receive message identifiers used. All transmitted messages use data byte 1 of the CAN message to hold the data to be sent.

SPI Bus
The standard SPI interface has been modified in this application to use a common signal line for both Serial In (SI) and Serial Out (SO) lines, isolated from each other via a resistor. This method requires only three I/O pins to implement the SPI interface, instead of the usual four. Using this configuration does not support the full duplex mode of SPI communications, which is not an issue in this application.

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The system achieves an overall SPI bus rate of slightly more than 80 kbps, with the raw SPI clock rate averaging 95 kbps. The clock low time is a fixed 5 s, and the clock high time is either 5 s or 6 s, depending upon whether a 0 or a 1 is being sent/received, which gives a worst case (sending the value 0xFF) of 90.9 kbps raw clock rate. The overall effective speed achieved includes the additional software overhead of bitbanging the SPI protocol.

CAN Bus
The CAN bus is configured to run at 125 kbps. The clock source for the MCP2510 is a standard 8 MHz crystal connected to the OSC1 and OSC2 inputs. The CAN physical layer has been implemented using an industry standard CAN transceiver chip (e.g., Microchip MCP2551). This device supports CAN bus rates of up to 1 Mbps and is more than adequate for the application presented here.

Interrupts
There are two interrupt sources in the system. The first is the PIC12C672 Timer0 interrupt, which occurs every 10.16 ms. The second interrupt source is the INT pin of the PIC12C672 and is connected to the INT output of the MCP2510. This interrupt occurs anytime a valid message is received, or if the MCP2510 detects a CAN bus related error. This external interrupt is completely asynchronous with respect to the rest of the system.

FIRMWARE DESCRIPTION
The firmware is written in PICmicro microcontroller (MCU) assembly code. The relative simplicity and small size of this application makes assembly language a more than suitable choice. Figure 2 shows the top level flowchart for the overall system operation. The PICmicro MCU, after going through self initialization and initializing the MCP2510, goes to sleep and waits for an interrupt to occur. The following sections provide more detailed discussion of the operation of each of the major blocks in the firmware.

Interrupt Latency
It is necessary to carefully consider the interrupt latency requirements during the system design/development phase. This system has two interrupt sources: the internal timer interrupt, which occurs approximately every 10 ms, and the external INT pin interrupt, which is generated by the MCP2510 CAN controller, and may occur anytime. The latency time for the Timer ISR is essentially fixed. This parameter is a function of the time it takes for the ADC to perform a conversion on both channels, write the values to the transmit buffer and issue a Request-to-Send (RTS) command to the MCP2510 via the SPI interface. This takes approximately 428 s to complete.

Digital Inputs and outputs

The MCP2510 has three pins that can be configured as general purpose inputs, and two pins that can be configured as digital outputs. Both are implemented in this design. These are discussed only at the simplest level within the scope of this application note. The inputs shown are connected to switch contacts, with the outputs being connected to LED indicators. The MCP2510 inputs have internal pull-up resistors. They will read high when the attached switch is open, and low when it is closed. The MCP2510 has two I/O pins (RX0BF and RX1BF) that can be configured as general purpose outputs. These pins are configured as outputs and are connected to LEDs to function as some type of indicator lights, controlled via the CAN bus.

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FIGURE 2: NODE OPERATION
System POR Initialize PICmicro MCU and MCP2510

Sleep

No Interrupt Occurred? Yes Yes Timer Interrupt? No

Perform A/D conversion on AN0

Read MCP2510 Interrupt Flags

Write A/D value to MCP2510 Transmit Buffer

Yes Error Interrupt?

Error Handler Routine

No Send Request to Send Command to MCP2510 Read MCP2510 Rx Filters

Clear Interrupt flags in PIC12C672

No Filter Match?

SysErr(InvMsg)

Yes Process Request Clear Interrupt flags in PIC12C672 and MCP2510

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PICmicro MCU Initialization
Initialization of the PIC12C672 is straightforward. There are three major functions that need to be properly configured within the PIC12C672: General Purpose I/O pins (GPIO) Timer0 module A/D converter module Additionally, the configuration word must also be programmed to enable/disable code protection and select the oscillator type. for the ISR execution gives a total time between messages of 10.156 ms, which is within 2% of the target.

ANALOG-TO-DIGITAL CONVERTER MODULE

The Timer0 module is configured to use the FOSC/8 option for the conversion clock, which gives a TAD value of 2 s, and an overall conversion time of 19 s (TAD 9.5). This is more than adequate when compared to the amount of time spent on SPI communications during the ISR.

GENERAL PURPOSE I/O PINS

The GPIO pins are the six I/O pins that are used to interface the PIC12C672 to the MCP2510 and sample the analog signals. The PICmicro MCU OPTION, TRIS and INTCON registers are used to control the setup of the GPIO pins. In this case, the OPTION register is programmed to disable the internal pull-up resistors on GP0/GP1/GP3, and configure GP2 to generate an interrupt on the negative going edge (to match the MCP2510s active low INT output). The TRIS register, which controls whether each I/O pin is configured as an input or an output, is configured to set GP0/GP1/GP3 as inputs, and GP2 and GP5 as outputs. With the exception of GP4, all of the GPIO pins will remain in their initially configured state. GP4 will be changed between input and output mode, depending on whether an SPI read or write operation is being performed by the PIC12C672. The final step of configuring the port pins is to program the INTCON register to enable the interrupt-on-change feature for GP2. This allows the MCP2510 to generate an interrupt for the PIC12C672.

MCP2510 Initialization
Before the system can communicate on the CAN bus, the MCP2510 must be properly configured. Configuration of the MCP2510 is accomplished by loading the various control registers with the desired values. The firmware is written to take advantage of the table read functionality of the PICmicro MCU. The values for each register are stored at the top of the PICmicro ROM memory. During the MCP2510 initialization, the values are sequentially read by the table read function and then written to the MCP2510 via the SPI interface.

CAN BUS TIMING

The CAN bit rate configuration is controlled by the CNF1, CNF2 and CNF3 registers. The details behind determining what the best configuration of these registers, for a given CAN bus system, is beyond the scope of this application note. The MCP2510 is configured to operate at a CAN bus rate of 125 kbps, using the following parameters: 8 MHz oscillator Baud rate prescaler equivalent to divide by four 8 TQ per bit time Sync segment: 1 TQ Prop segment: 1 TQ Phase Segment 1: 3 TQ Phase Segment 2: 3 TQ Sync Jump Width: 1 TQ

TIMER0 MODULE
The Timer0 module operation is controlled by the OPTION register and the TMR0 register. The OPTION register contains the control bits for the Timer0 prescaler, which is set to divide by 256. The TMR0 register is the counting register for Timer0 and generates an interrupt when it rolls over from 0xFF to 0x00. This register must be reloaded as part of the ISR in order to correctly control the time period between Timer0 interrupts. The target time period between Timer0 messages is 10 ms. In order to approach that target, it is necessary to determine the amount of time required to complete the Timer0 ISR, since the time between messages will be the sum of the Timer0 value and the ISR execution time. The A/D conversion takes approximately 19 s. The SPI communication to write the A/D result to the MCP2510 transmit buffer and then send the RTS command requires approximately 409 s to complete. This implies a total of approximately 428 s for the ISR to execute. Subtracting the ISR execution time from the 10 ms target yields 9.572 ms. Given the prescaler configured in, divide by 256 mode, the closest value is 9.728 ms (256 s 38). Adding the 428 s

Refer to the MCP2510 data sheet (DS21291) for more detailed information regarding the setting of these parameters. In order to make use of the MCP2510s general purpose input and output pins, it is necessary to configure the TXRTSCTRL and BFPCTRL registers, respectively.

TXTRSCTRL
To enable the use of the TXnRTS pins as general purpose inputs, the mode control bit <BnRTSM> is cleared. This register also holds the current state of each of the inputs pins in bits 3:5, which can be read by the microcontroller at any time via the SPI interface.

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BFPCTRL
To use the RXnBF pins of the MCP2510 as output pins it is necessary to functionally enable the pin by setting the BnBFE bits and then selecting the general purpose output mode of operation by clearing the BnBFM bits. Once the register has been configured, it is used to control the state of the output pins by toggling the BnBFS bits, which is accomplished via the MCP2510s built-in Bit Modify Command, which only allows the desired bit to be modified.

Interrupt Service Routine

Once an interrupt occurs, the PICmicro MCU begins executing the ISR routine. Figure 3 shows the flow chart for the ISR. The ISR first determines the source of the interrupt (Timer0 or external INT pin) then branches to the appropriate code to process the interrupt. Figure 4 and Figure 5 show the program flow for the Timer0 and CAN message received interrupts, respectively.

CANINTE
The MCP2510s CANINTE register controls the individual interrupt source enables. For this application only, the error interrupt (ERRIE) and the receive buffer 1 interrupts (RX1IE) are enabled. In this configuration, the MCP2510 will generate an interrupt when a valid message is accepted into the receive buffer, or when any of the various error conditions in the EFLG register occur.

TIMER0 INTERRUPT
When the Timer0 interrupt occurs (see Figure 4), the PICmicro MCU initiates an A/D conversion on AN0, constantly polling the ADDONE bit until the conversion is complete. Once the conversion is completed, the ADRES value is loaded into the MCP2510 transmit buffer 0, data byte 0 and an RTS command is issued for buffer 0. The TMR0 register is then reloaded and the interrupt flag is cleared. The interrupts are re-enabled by the execution of the RETIE command at the end of the ISR.

FIGURE 3:

INTERRUPT SERVICE ROUTINE (ISR) FLOWCHART

ISR

Yes

INT pin Interrupt Occurred?

No

Timer0 Interrupt? Yes

No SysErr (Invalid INT)

Read MCP2510 CANINTF Register

Timer0 Time Out

Yes Msg Rx INT?

CAN Msg Received

No Yes SysErr (CANErr)

CAN Bus Error? No SysErr(Invalid INT)

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MESSAGE RECEIVED INTERRUPT
When an interrupt is generated by the MCP2510, the PIC12C672 reads the CANINTF register of the MCP2510 to determine the source of the interrupt. If a valid message has been received, the MsgRcvd subroutine is executed (see Figure 5). If an error has occurred, the error handling subroutine is executed (see Figure 6). When a valid message is received, the FILHIT<2:0> bits of the RXB1CTRL register are read to determine which message has been received. If the match occurred on Filter 2, the PICmicro MCU initiates an A/D conversion on AN1, waits for the conversion to complete, loads the ADRES register value into the MCP2510 transmit buffer 0, data byte 0 and sends the RTS command. If the match occurred on Filter 3, the PICmicro MCU reads the TXRTSCTRL register for the value of the three input pins, loads this value into the MCP2510 transmit buffer and sends the RTS command. A match on Filter 4 or Filter 5 causes the PICmicro MCU to read the first byte of the received message and write it to the appropriate output pin via the MCP2510 BFPCTRL register.
Interrupt Occurred? No

FIGURE 4:

TIMER0 ISR FLOW

Timer0 Time Out

Start Conversion on AN0

Yes Store AN0 value into RAM variable

Load AN0 value into MCP2510 TxMsg Buffer

Send RTS command to MCP2510

Clear Interrupt Flag

Reload Timer0

Re-enable Interrupts

Exit ISR

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FIGURE 5: CAN MSG RECEIVED FLOW
INT pin (CAN Msg Rx)

Read MCP2510 Rx Filter

Filter Match = 2?

Yes

Perform A/D conversion on AN1

No Yes Filter Match = 3? Read value of three MCP2510 digital inputs Write A/D value to MCP2510 Transmit Buffer

No Read MCP2510 Rx Buffer for digital output 1 data Sent Request to Send command to MCP2510

Sent Request to Send command to MCP2510

Yes

Filter Match = 4?

No Yes Filter Match = 5?

Update MCP2510 Digital Output Control Register

Read MCP2510 Rx Buffer for digital output 2 data

No SysErr(InvMsg)

Clear Interrupt flags in PIC12C672 and MCP2510

Exit ISR

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FIGURE 6: ERROR HANDLER FLOW
Error Handler

Read ERRIF Register

RxB1 Overflow?

Yes

Send Error Msg 0x3FF, error code 0x11

No Yes No

Error Warning Flag Set?

Rx Warning Flag Set?

Send Error Msg 0x3FF, error code 0x02

Yes No Send Error Msg 0x3FF, error code 0x01

Rx Error Passive Flag Set No

Yes

Send Error Msg 0x3FF, error code 0x03

Tx Error Passive Flag Set

Yes

Send Error Msg 0x3FF, error code 0x04

No Yes No

Bus Off Flag Set?

1st Bus Off Occurrence?

No Send Error Msg 0x3FF, error code 0x13

Yes Set Bus Off Flag and re initialize MCP2510

Send Error Msg 0x3FF, error code 0x12

Yes

Message transmitted successfully

No

Idle PICmicro MCU must RESET system node

Done

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Error Handling
The system also provides for error detection for a number of different types of errors that may occur. This includes CAN bus errors detected by the MCP2510 and invalid system state errors (see Figure 6). When any of these errors are detected, the system transmits a message with the ID of 0x3FF. This message contains one data byte, which is a code used to represent the type of error that occurred. Refer to Appendix B for a listing of various errors and the associated code. The one exception to this is the Bus-Off condition that the MCP2510 may enter if a large number of transmit errors are detected. If the Bus-Off condition is detected, the PICmicro MCU performs a re-initialization of the MCP2510 and then attempts to transmit the error message (ID=0x3FF) with an error code of 0x12. After initiating a request to send for the error message, the PICmicro MCU checks to ensure that the message was transmitted successfully. If it was successfully transmitted, the PICmicro MCU sets an internal flag to indicate that a Bus-Off condition has occurred, then resumes normal operation. If the error message fails to transmit correctly, or if the Bus-Off condition is detected a second time, the PICmicro MCU automatically enters an idle loop and remains there until a system reset occurs via power on.

REFERENCE DOCUMENTS
For additional information, the reader is directed to the following documents: PIC12C67X Data Sheet, DS30561; Microchip Technology, Inc. MCP2510 Stand-Alone CAN Controller Data Sheet, DS21291; Microchip Technology, Inc. Controller Area Network (CAN) Basics, AN713; DS00713; Microchip Technology, Inc. MCP2551 High-Speed CAN Transceiver Data Sheet, DS21667; Microchip Technology, Inc.

SUMMARY
This application note demonstrates that a smart CAN node can be implemented with low cost, low pin count devices, such as the PIC12C672 microcontroller and MCP2510 Stand-Alone CAN controller, providing a very flexible and effective solution for a variety of applications.

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APPENDIX A:

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VCC Vdd U3 Vss C2 0.1uF R2 10K U1 1 2 3 4 R1 4.7K 8 7 6 5 Vdd Vss GP5 GP0 GP4 GP1 GP3 GP2 PIC12C67X Analog Input 2 Analog Input 1 5 6 7 8 Ref RXD CANL Vcc CANH GND Rs TXD MCP2551 Vss U2 4 3 2 1 VCC C1 0.1uF Vss SW1 SW2 SW3 C3 30pF Y1 8MHz MCP2510 Vss C4 30pF Vss Digital Output 1 Digital Output 2 1 2 3 4 5 6 7 8 9 TXCAN RXCAN CLKOUT TX0RTS TX1RTS TX2RTS OSC2 OSC1 Vss Vdd RESET CS SO SI SCK INT RX0BF RX1BF 18 17 16 15 14 13 12 11 10

SCHEMATIC

CON1

5 9 4 8 3 7 2 6 1

Preliminary

CAN BUS

Vss

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Software License Agreement
The software supplied herewith by Microchip Technology Incorporated (the Company) for its PICmicro Microcontroller is intended and supplied to you, the Companys customer, for use solely and exclusively on Microchip PICmicro Microcontroller products. The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved. Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil liability for the breach of the terms and conditions of this license. THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

APPENDIX B:
; ; ; ; ; ; ; ; ; ; ; ; ;

SOURCE CODE

*********************************************** * 8pincan.asm * * Revision 1.0 September 2000 * * Developed by Rick Stoneking * * Developed using MPLAB V4.12 and MPASM V2.3 * * * * This code demonstrates how a very low cost * * CAN node can be implemented using a * * Microchip PIC12C672 8-pin microcontroller * * and a Microchip MCP2510 Stand-Alone CAN * * controller. * * * ***********************************************

; *********************************************** ; * Setup the MPASM assembler options * ; *********************************************** LIST p=12C672

; ; ; ;

*********************************************** * Include the standard PIC12C672 include file * * and the custom MCP2510 support files * ***********************************************

#include <p12c672.inc> #include mcp2510.inc

; *********************************************** ; * Setup the PIC12C672 configuration Word * ; *********************************************** __CONFIG _CP_OFF & _WDT_OFF & _MCLRE_OFF & _INTRC_OSC

; *********************************************** ; * Constants definitions * ; *********************************************** TMR_COUNT EQU 0xD9 ; Timer Reload value: ; 0xD9 = 38 * 256 * 1us = 9.728ms ; *********************************************** ; * Variable definitions * ; *********************************************** temp EQU 0x20 temp1 EQU 0x21 byte_cnt EQU 0x22

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addr tmp_data EQU EQU 0x23 0x24

; *********************************************** ; * PIC Initialization * ; *********************************************** org goto 0x00 start

; Jump around ISR vector

; *********************************************** ; * Interrupt service vector initialization * ; *********************************************** org 0x04 goto isr ; Point ISR vector to the ISR handler ; *********************************************** ; * Start of Main Code * ; *********************************************** start bsf STATUS,RP0 ; select bank1 movlw 0x87 ; Disable internal pullups ; Interrupt on negative going edge on GP2 ; Prescaler = 1:256 movwf movlw movwf bsf movlw movwf movlw bcf OPTION_REG 0x0B TRISIO INTCON,GPIE 0x04 ADCON1 0x04 STATUS,RP0 ; Load the OPTION register ; --001011 ; set all ports output except GP3/1/0 ; enable GPIO Interrupt on change ; GP4&2 = DIO, GP0&1= ADC, Vref=VDD ; ; GPIE set - interrupt on pin change ; GIE cleared - global interrupts disabled ; select bank0

; Initialize the A/D converter movlw movwf 0x40 ADCON0 ; AN0 conversion clock = Fosc/8 (TAD=2us) ; Turn off A/D module

; Initialize Timer0 movlw movwf TMR_COUNT TMR0 ; Initialize Timer0 ; Timer0 interrupt every 9.728mS

; Set up initial conditions for the SPI movlw movwf bsf bcf bcf call 0x24 GPIO GPIO,cs_pin GPIO,sck_pin GPIO,sdo_pin mcp2510_init ; CS high, INT high, data/clk low ; write to port ; set CS pin high ; clear the sck pin ; clear the sdo pin ; initialize the mcp2510

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; ******************************************* ; * Main wait loop * ; ******************************************* wait sleep nop nop goto ; ; ; ; ; wait for interrupt to occur sleep while not processing a message NOP executed when waking up from sleep NOP executed after ISR completes go back to sleep and wait

wait

; *********************************************** ; * MCP2510 Initialization * ; *********************************************** mcp2510_init movlw bcf call movlw call movlw call bsf bcf bcf movlw movwf movlw bcf call movlw call movlw movwf seq_wr movlw movwf movfw decf movf call call incf incf decfsz goto bsf movlw bcf call movlw call movlw call bsf movlw movwf bsf return HIGH reg_init_tbl PCLATH addr addr, 1 addr, W reg_init_tbl spi_send addr,1 addr,1 byte_cnt,1 seq_wr GPIO,cs_pin CAN_WRITE GPIO,cs_pin spi_send CANCTRL spi_send REQOP_NORMAL spi_send GPIO,cs_pin 0x00 byte_cnt INTCON,GIE

CAN_WRITE GPIO,cs_pin spi_send CANCTRL spi_send REQOP_CONFIG spi_send GPIO,cs_pin GPIO,sck_pin GPIO,sdo_pin 0x71 byte_cnt CAN_WRITE GPIO,cs_pin spi_send 0x00 spi_send 0x01 addr

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

write command lower CS to enable MCP2510 send command select CANCTRL register address and send it Request Config Mode send data raise CS to terminate operation set clock and data pins low number of addresses to be written load into byte counter write command enable MCP2510 send command start writing at address 0x00 send address

; ; ; ; ; ; ; ; ; ; ; ; ;

sequential write loop get high byte of reg_int_tbl address load into high byte of PC counter write into jump table pointer (addr)

fetch byte to be written send it to MCP2510 increment the jump table pointer twice to point to the next byte decrement the byte counter and test for zero not done so repeat raise CS to terminate operation

; write command ; enable MCP2510 ; write to CANCTRL register ; Normal Mode ; terminate operation ; clear byte_cnt variable

; Enable Interrupts

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; ******************************************************************* ; * Interrupt Service Routine * ; * The ISR determines whether a TMR0 interrupt or an external INT * ; * pin interrupt occurs and then proceeds accordingly * ; ******************************************************************* isr bcf STATUS,RP1 ; select bank 0/1 btfss goto movlw movwf bcf call bcf movlw call movlw call movfw call bsf bcf movlw call bsf bcf return intpin movlw bcf call CAN_READ GPIO,cs_pin spi_send INTCON,T0IE intpin TMR_COUNT TMR0 ADCON0,CHS0 adc_cnv GPIO,cs_pin CAN_WRITE spi_send TXB0D0 spi_send ADRES spi_send GPIO,cs_pin GPIO,cs_pin CAN_RTS_TXB0 spi_send GPIO,cs_pin INTCON, T0IF ; Timer0 interrupt? ; No, so jump to external interrupt pin ISR ; reload ; Timer0 ; select ADC channel 0 ; go do the conversion ; enable MCP2510 ; send write command to MCP2510 ; ; set write address to TXB0D0 ; ; write ADC conversion result ; ; terminate SPI operation ; enable MCP2510 ; Send RTS command for TXB0 ; terminate operation ; clear TMR0 interrupt flag ; exit isr ; Message received interrupt

; lower CS line ; send read command to MCP2510 ; Check for RXB1IF flag by reading ; the interrupt flag register (CANINTF) ; read the data from the MCP2510 ; terminate SPI read ; save CANINTF value ; test CANINTF for RX1IF ; if RX1IF set go process message ; test CANINTF for ERRIF ; if ERRIF set go process CAN error ; mask off RXB1IF and ERRIF bits ; of CANINTF ; if any bit set process invalid interrupt ; Not an error interrupt so initiate an invalid interrupt ; occurred message. ; reset interrupt flag ; return to main routine

movlw call call bsf movwf btfsc call btfss call movlw andwf btfsc call

CANINTF spi_send spi_rx GPIO,cs_pin tmp_data tmp_data,1 msg_rcvd tmp_data,5 can_err B11011101 tmp_data,1 STATUS,Z sys_err

bcf retfie

INTCON,GPIF

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AN215
; ******************************************************************* ; * CAN Error routine * ; * This routine reads the value of the MCP2510 Error flag (EFLG) * ; * register, writes it to byte 0 of TXB1, and then transmits the * ; * TXB1 message * ; ******************************************************************* can_err movlw bcf call movlw call call bsf movwf movlw bcf call movlw call movfw call bsf movlw bcf call bsf retfie CAN_READ GPIO,cs_pin spi_send EFLG spi_send spi_rx GPIO,cs_pin tmp_data CAN_WRITE GPIO,cs_pin spi_send TXB1D0 spi_send tmp_data spi_send GPIO,cs_pin CAN_RTS_TXB1 GPIO,cs_pin spi_send GPIO,cs_pin ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; SPI Read operation enable MCP2510 EFLG register to be read read the data terminate SPI operation save the value of EFLG register now write to MCP2510

write to data byte 0 of TXB1 write EFLG register contents terminate SPI operation

; send request to send ; for transmit buffer 1

; exit isr and re-enable interrupts

; ******************************************************************* ; * System Error Handler Routine * ; * This routines transmits the TXB2 message to indicate that a * ; * unidentifiable system error has occurred. * ; ******************************************************************* sys_err movlw CAN_RTS_TXB2 ; send request to send bcf GPIO,cs_pin ; for transmit buffer 2 call spi_send ; when a system error occurs bsf GPIO,cs_pin retfie

; ******************************************************************* ; * CAN Msg Received Routine * ; * This routine is called when a message has been received into * ; * TXB0 of the MCP2510. This routine reads the filter bits to * ; * determine the type of message received and then initiates the * ; * appropriate response. * ; ******************************************************************* msg_rcvd movlw CAN_READ ; SPI read command bcf GPIO,cs_pin ; enable MCP2510 call spi_send movlw call call bsf RXB0CTRL spi_send spi_rx GPIO,cs_pin ; Read buffer 0 control register

; terminate function

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Preliminary

2002 Microchip Technology Inc.

AN215
andlw movwf movlw subwf btfsc goto movlw subwf btfsc goto movlw subwf btfsc goto movlw subwf btfsc goto filter1 call bsf call bcf movlw call movlw call movfw call bsf goto filter2 call bcf movlw call movlw call call bsf bcf movlw call movlw call bsf goto filter3 call movlw bcf wrt_txb0sidh CAN_READ GPIO,cs_pin ; load the transmit buffer SIDH register ; Read contents of receive buffer zero ; byte zero to get value to write to wrt_txb0sidh GPIO,cs_pin CAN_READ spi_send TXRTSCTRL spi_send spi_rx GPIO,cs_pin GPIO,cs_pin CAN_WRITE spi_send TXB0D0 spi_send GPIO,cs_pin filter_done ; load the transmit buffer SIDH register ; ; ; ; ; ; enable MCP2510 send read command to MCP2510 set read address to TXRTSCTRL read data wrt_txb0sidh ADCON0,CHS0 adc_cnv GPIO,cs_pin CAN_WRITE spi_send TXB0D0 spi_send ADRES spi_send GPIO,cs_pin filter_done ; load the transmit buffer SIDH register ; select ADC channel 1 ; go do the conversion ; ; ; ; ; ; ; ; enable MCP2510 send write command to MCP2510 set write address to TXB0D0 write ADC conversion result terminate SPI operation B00000111 temp 0x01 temp,1 STATUS,Z filter1 0x02 temp,1 STATUS,Z filter2 0x03 temp,1 STATUS,Z filter3 0x04 temp,1 STATUS,Z filter4 ; mask off all but the FILHIT bits ; store value in temp ; ; filter 1 match?

; filter 2 match

; filter 3 match

; filter 4 match

; ; ; ; ;

write TXTRTSCTRL value to data byte zero of transmit buffer zero terminate SPI operation

2002 Microchip Technology Inc.

Preliminary

DS00215B-page 17

AN215
call movlw call call bsf movwf movlw bcf call movlw call movlw call movlw btfss movlw call bsf goto filter4 call movlw bcf call movlw call call bsf movwf movlw bcf call movlw call movlw call movlw btfss movlw call bsf filter_done movlw bcf call bsf return wrt_txb0sidh CAN_READ GPIO,cs_pin spi_send RXB1D0 spi_send spi_rx GPIO,cs_pin tmp_data CAN_BIT_MODIFY GPIO,cs_pin spi_send BFPCTRL spi_send B1BFS spi_send 0xFF tmp_data,0 0x00 spi_send GPIO,cs_pin ; load the transmit buffer SIDH register ; Read contents of receive buffer zero ; byte zero to get value to write to ; GP output pin of MCP2510 ; spi_send RXB1D0 spi_send spi_rx GPIO,cs_pin tmp_data CAN_BIT_MODIFY GPIO,cs_pin spi_send BFPCTRL spi_send B0BFS spi_send 0xFF tmp_data,0 0x00 spi_send GPIO,cs_pin filter_done ; GP output pin of MCP2510 ;

; store value in tmp_data ; use bit modify command to ; set/reset the B0BFS bit of BFPCTRL register

; assume that B0BFS is to be set ; test the value received in message and if it is 0 ; load w register to reset bit in BFPCTRL register

; store value in tmp_data ; use bit modify command to ; set/reset the B0BFS bit of BFPCTRL register

; assume that B1BFS is to be set ; test the value received in message and if it is 0 ; load w register to reset bit in BFPCTRL register

CAN_RTS_TXB0 GPIO,cs_pin spi_send GPIO,cs_pin

; last step is to send the ; request to send command for ; transmit buffer zero

DS00215B-page 18

Preliminary

2002 Microchip Technology Inc.

AN215
; ******************************************************************* ; * write TXB0SIDH * ; * This routine reads the SIDH register from the received message * ; * and then sets the SID3 bit and writes the new value to the TX * ; * buffer. * ; ******************************************************************* wrt_txb0sidh movlw CAN_READ ; SPI read command bcf GPIO,cs_pin ; enable MCP2510 call spi_send movlw RXB0SIDH ; Read received SIDH register call spi_send call spi_rx bsf GPIO,cs_pin ; terminate function movwf bcf movlw call movlw call movfw bsf call bsf return tmp_data GPIO,cs_pin CAN_WRITE spi_send TXB0SIDH spi_send tmp_data W,0 spi_send GPIO,cs_pin ; store SIDH value in data

; write to the SIDH register ; ; retrieve SIDH value of received message ; set bit SID3 high ;

; ******************************************************************* ; * Analog to Digital Conversion Routine * ; * This routine initiates the A/D conversion. The ADC channel * ; * select bits (CHS1:0) have to be set prior to this routine being * ; * called. The routine waits for the conversion to complete * ; * before returning to the calling function. * ; ******************************************************************* adc_cnv bsf ADCON0,GO adc_busy btfsc ADCON0,GO_DONE ; wait for ADC to complete goto adc_busy movlw bcf call movlw call movf call bsf return CAN_WRITE GPIO,cs_pin spi_send TXB0D0 spi_send ADRES,0 spi_send GPIO,cs_pin ; ; ; ; ; ; ; ; SPI write command lower CS line send write command to MCP2510 data being written to data byte zero of buff 0 Move ADC value to W register send to MCP2510 terminate SPI command

; ************************************************** ; * Include the custom three wire SPI support file * ; ************************************************** #include spi.inc ; SPI routines

2002 Microchip Technology Inc.

Preliminary

DS00215B-page 19

AN215
; ; ; ; ; ; ******************************************************************* * MCP2510 register initialization table * * Store at the end of ROM memory * * Note that all addresses are initialized to simplify the * * initialization code. * ******************************************************************* 0x0700 PCL, 1 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x7e 0x00 0xff 0xff 0x3c 0x00 0x80 0x80 0x7e 0x20 0xff 0xff 0x7e 0x40 0xff 0xff 0x7e 0x50 0xff 0xff 0x00 0x00 0x80 0x80 0xff 0xff 0xff 0xff 0x7e 0x00 0x00 0x00 0x02 0x90 0x03 0x22 0x00 0x00 0x80 0x80 0x03 ; Initialization table address ; ; ; ; ; ; ; ; ; ; ; ; ; ; Register Addr --------- ---RXF0SIDH 0x00 RXF0SIDL 0x01 RXF0EID8 0x02 RXF0EID0 0x03 RXF1SIDH 0x04 RXF1SIDL 0x05 RXF1EID8 0x06 RXF1EID0 0x07 RXF2SIDH 0x08 RXF2SIDL 0x09 RXF2EID8 0x0A RXF2EID0 0x0B ; BFPCTRL 0x0C ; state hi ; TXRTSCTRL 0x0D ; CANSTAT 0x0E ; CANCTRL 0x0F ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; RXF3SIDH RXF3SIDL RXF3EID8 RXF3EID0 RXF4SIDH RXF4SIDL RXF4EID8 RXF4EID0 RXF5SIDH RXF5SIDL RXF5EID8 RXF5EID0 TEC REC CANSTAT CANCTRL 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F

org reg_init_tbl addwf retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw

Filter 2 matches 0x3f0

BFP pins as digital outputs, initial TXRTS pins as digital inputs

Filter 3 matches 0x3f1

Filter 4 matches 0x3f2

Filter 5 matches 0x3f3

RXM0SIDH 0x20 RXM0SIDL 0x21 RXM0EID8 0x22 RXM0EID0 0x23 ; RXM1SIDH 0x24 ; to 0x3ff ; RXM1SIDL 0x25 ; RXM1EID8 0x26 ; RXM1EID0 0x27 ; CNF3 0x28 ; CNF2 0x29 ; CNF1 0x2A ; CANINTE 0x2B ; CANINTF 0x2C ; EFLG 0x2D ; CANSTAT 0x2E ; CANCTRL 0x2F ; TXB0CTRL 0x30

Enable all mask bits so that no msgs are received into RXB0

Set RXM1 to match msg IDs of 0x3f0

PHSEG2 = 3TQ PHSEG1 = 3TQ, PRSEG = 1TQ SJW = 1TQ, BRP set to 4 MERRIE and RX1IE enabled

Highest priority

DS00215B-page 20

Preliminary

2002 Microchip Technology Inc.

AN215
retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw 0x7e 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x80 0x03 0x7e 0xe0 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x80 0x03 0x7e 0xe0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x80 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; TXB0SIDH TXB0SIDL TXB0EID8 TXB0EID0 TXB0DLC TXB0DB0 TXB0DB1 TXB0DB2 TXB0DB3 TXB0DB4 TXB0DB5 TXB0DB6 TXB0DB7 CANSTAT CANCTRL TXB1CTRL TXB1SIDH TXB1SIDL TXB1EID8 TXB1EID0 TXB1DLC TXB1DB0 TXB1DB1 TXB1DB2 TXB1DB3 TXB1DB4 TXB1DB5 TXB1DB6 TXB1DB7 CANSTAT CANCTRL TXB2CTRL TXB2SIDH TXB2SIDL TXB2EID8 TXB2EID0 TXB2DLC TXB2DB0 TXB2DB1 TXB2DB2 TXB2DB3 TXB2DB4 TXB2DB5 TXB2DB6 TXB2DB7 CANSTAT CANCTRL 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F Receive only Standard Ids that match Highest priority

; RXB0CTRL 0x60 Masks/Filters RXB0SIDH 0x61 RXB0SIDL 0x62 RXB0EID8 0x63 RXB0EID0 0x64 RXB0DLC 0x65 RXB0DB0 0x66 RXB0DB1 0x67 RXB0DB2 0x68 RXB0DB3 0x69 RXB0DB4 0x6A RXB0DB5 0x6B RXB0DB6 0x6C RXB0DB7 0x6D

2002 Microchip Technology Inc.

Preliminary

DS00215B-page 21

AN215
retlw retlw retlw Masks/Filters END 0x80 0x80 0x20 ; CANSTAT ; CANCTRL 0x6E 0x6F Receive only Standard Ids that match

; RXB1CTRL 0x70

DS00215B-page 22

Preliminary

2002 Microchip Technology Inc.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, K EELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Companys quality system processes and procedures are QS-9000 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001 certified.

2002 Microchip Technology Inc.

DS00215B - page 23

M
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DS00215B-page 24

2002 Microchip Technology Inc.