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UART (VHDL) && VGA (Verilog)

This document is a mid-term report submitted by Saurabh Shukla. It contains two chapters, the first providing an introduction and objectives. The second chapter is a literature review covering topics such as FPGAs, HyperTerminal, VHDL, and Verilog. It discusses the key components and features of FPGAs, as well as various concepts in VHDL and Verilog like entities, architectures, processes, data types, operators, and simulation functions.

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UART (VHDL) && VGA (Verilog)

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Mid Term Report

Saurabh Shukla

Saurabh Shukla

CHAPTER 1: Introduction
1. Organization
Samtel Group's journey began in 1973, with a vision to create a world-class organization. Today, Samtel Group is Indias largest integrated manufacturer of a wide range of displays for television, avionics, industrial, medical and professional applications, TV glass, components for displays, machinery and engineering services. The group employs 6000 people in nine world-class factories and has an annual turnover of Rs 12 billion (USD 300M) Samtel Group has strong design and development skills and is a dependable player with excellent technological capabilities and a long-term commitment to the display industry. Its products are known for ruggedness and reliability and conform to the latest relevant quality standards. The group has excellent relationships with suppliers of key components and the ability to design new products as well as set up hi-tech manufacturing facilities. Samtel has registered many patents for developments in display technology and also developed its own technology for automation.

Saurabh Shukla

1.2: Objectives:

1.2.1: UART: UART receiver / Transmitter have data bits, stop bits scalable. Baud
generator has its baud rate divisor scalable. Interface circuit (FIFO) its depth scalable. Tested in Spartan 3 starter kit board (FPGA). This Project focuses on the design of high speed UART. The project describing the behavior of UART circuit using VHDL. In the result and simulation part, in the baud rate generator part, UART receiver, UART transmitter. VHDL synthesis is for high reliability systems. UART baud rate of 19200, using 50 MHz system clock rate. The simulated waveforms in this Project have proven the reliability of the VHDL implementation to describe the characteristics and the architecture of the design UART with baud rate generator. UART provide serial asynchronous receiver data synchronization, parallel- to serial and serial to parallel data conversion for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital systems. Synchronization for the serial data stream is accomplished by adding start and stop bit to the transmit data to form a data character. UART include a transmitter and receiver. The transmitter is essentially a special shift register that loads data in parallel and then shifts it out bit by bit at specific rate. UART Receiver, on the other hand, shifts in data bit by bit and then reassembles the data. The serial line is high when it is idle. UART transmission starts with a start bit, which is low, followed by data bits and an optional parity bit and ends with stop bits, which is high. The LSB of the data word is transmitted first. No clock information is conveyed through the serial line. Before the transmission starts, the transmitter and receiver must agree on a set of parameters in advance, which include the baud rate. Baud rate , number of bits per second which is 19200.

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1.2.2: VGA:
Video Graphics Array is widely supported by PC graphics Hardware and monitors. Basic eight color 640 by 480 resolution interface for CRT monitors. Tested in Spartan- 3 starter kit board(FPGA). The VGA port has five active signal, including the horizontal and vertical synchronization signal. Three video signal for the Red, Green, blue. one horizontal synchronization signal and one vertical synchronization signal. A video signal is an analog signal and the video controller uses a digital to analog converter to convert the digital output to the desired analog level. It is physically connected to a 15 pin D subminiature connector. If a video signal is represented by a N bit word, it can be converted to 2^N analog levels. The three video signals can generate 2^3N different colors. This is also known as 3N bit color since a color is defined by 3N bits. In the S3 board, a 1 bit word is used for each video signal, this leads to only eight (i.e. , 2^3) possible colors. If we use the same 1 bit signal to drive the video signals, they become either 000 or 111 and the monitor functions as a black and white monochrome monitor.

Saurabh Shukla

2.1.3: Fast, Asynchronous SRAM:

The Spartan 3 starter kit board has a megabyte of fast asynchronous SRM, surface mounted to the back side of the board. The memory array includes two 256Kx16 ISSI 10ns SRAM devices. The SRAM array from either a signal 256Kx32 SRAM memory or two independent 256Kx16 array. Both SRAM devices share common write enable, output enable and address signal. Each device has a separate chip select enable control and individual byte enable controls to select the high or low byte in the 16 bit data word. The 256kx32 configuration is ideally suited to hold micro blaze instructions. However, it alternately provides high density data storage for a Varity of applications such as digital signal processing large data FIFO and graphics buffers.

External SRM address Bus connections to Spartan 3 FPGA

Address A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7

FPGA Pin L3 K5 K3 J3 J4 H4 H3 G5 E4 E3 F4

A1 Expansion connector Pin 35 33 34 31 32 29 30 27 28 25 26

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A6 A5 A4 A3 A2 A1 A0

F3 G4 L4 M3 M4 N3 L5

23 24 14 12 10 8 6

External SRAM Control Signal Connections to Spartan 3 FPGA: OE# WE# Output Enable Write Enable.

Signal OE# WE#

FPGA Pin K4 G3

A1 Expansion connector pin 16 18

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2.1.4: Four Digit, Seven Segment LED Display:

The Spartan 3 starter kit board has a four character, seven segment LED display controlled by FPGA user I/O pins. Each digit shares eight common control signals to light individual LED segments. The pin number for each FPGA pin connected to the LED display appears in parentheses. To light an individual signal, drive the individual segment control signal low along with the associated anode control signal for the individual character.

FPGA Connections To seven Segment Display:

Segment A B C D E F G DP

FPGA Pin E14 G13 N15 P15 R16 F13 N16 P16

Digit Enable (Anode control) Signal: Anode Control FPGA Pin AN3 E13 AN2 F14 AN1 G14 AN0 D14

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Display Characters and resulting LED Segment Control Values:

Character

A 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0

b 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 1

c 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1

d 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1

e 0 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0

f 0 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0

G 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0

0 1 2 3 4 5 6 7 8 9 A b C D E F

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The LED control signals are time multiplexed to display data on all four characters. Present the value to be displayed on the segment control inputs and select the specified character by driving the associated anode control signal LOW. Through persistence of vision, the human brain perceives that all four characters appear simultaneously, similar to the way the brain perceives a TV display. This scanning technique reduces the number of I/O pins required for the four characters. If an FPGA pin were dedicated for each individual segment, then 32 pins are required to drive four 7segment LED characters. The scanning technique reduces the required I/O down to 12 pins. The drawback to this approach is that the FPGA logic must continuously scan data out to the displays a small price to save 20 additional I/O pins.

2.1.5: Switches and LEDs:

2.1.5.1: Slide Switches:

The Spartan 3 starter kit board has eight slide switches. The switches are located along the lower edge of the board, toward the right edge.

Slider Switch Connections:

Switch FPGA Pin

SW7 K13

SW6 K14

SW5 J13

SW4 J14

SW3 H13

SW2 H14

SW1 G12

SW0 F12

When in the UP or ON position, a switch connects the FPGA pin to Vcco, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, logic LOW. The switches typically exhibit about 2 ms of mechanical bounce and there is no active denouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board.

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2.1.5.2: Push Button Switches:

Spartan 3 starter kit board has four momentary contact push buttons are located along the lower edge of the board, toward the right edge. Push Button Switch Connections: Push Button BTN3 BTN2 BTN1 BTN0 FPGA Pin L14 L13 M14 M13

Pressing a push button generates a logic high on the associated FPGA pin. Again, there is no active debouncing circuitry on the push button.

2.1.5.3: LEDs:
The Spartan 3 starter kit board has eight individual surface mount LEDs located above the push button switches. The LEDs are labeled LED7 through LED0. LED Connections To The Spartan 3 FPGA: LED LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 FPGA Pin P11 P12 N12 P13 N14 L12 P14 K12

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2.1.6: VGA Port:

The Spartan 3 starter kit board induces a VGA display port and DB15 connector. Connect this port directly to most PC monitors or flat panel LCD displays using a standard monitor cable. The Spartan 3 FPGA controls five VGA signals: Red, Green, Blue, Horizontal sync, Vertical sync, all available on the VGA connector. VGA port connections to the Spartan 3 FPGA.

Signal Red Green Blue Horizontal Sync Vertical Sync

FPGA Pin R12 T12 R11 R9 R10

Each color line has a series resistor to provide 3 bit color with one bit each for Red, Green, Blue. The series resistor uses the 75 ohm VGA cable termination to ensure that the color signal remain in the VGA specified 0 V to 0.7 V range. 3 Bit Display Color Codes:

Red
0 0 0 0 1 1 1 1

Green
0 0 1 1 0 0 1 1

Blue
0 1 0 1 0 1 0 1

Resulting Color
Black Blue Green Cyan Red Magenta Yellow White

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2.1.7: PS/2 Mouse/Keyboard Port:

The Spartan 3 starter kit board include a PS/2 mouse/Keyboard port and the standard 6 pin mini din connector, labeled J3 on the board. Only pins 1 and 5 of the connector attached to the FPGA.

PS/2 Din pin

1 2 3 4 5 6

Signal
Data Reserved GND Voltage Supply CLK Reserved

FPGA Pin
M15 ------GND ------M16 -------

Both a PC mouse and keyboard use the two wire PS/2 serial bus to communicate with a host device, the Spartan 3 FPGA in this case. The PS/2 bus includes both clock and data. Both a mouse and keyboard drive the bus with identical signal timings and both use 11 bit words that include a start, stop and add parity bit. However, the data packets are organized differently for a mouse and key board. Keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard. The clock and data signals are only driven when data transfers occur and otherwise they are held in the idle state at logic high. The timing define signal requirements for mouse to host communications and bidirectional keyboard communications. The keyboard uses open collector drivers so that either the keyboard or the host can drive the two wire bus. If the host never sends data to the keyboard, then the host use simple input pins. A PS/2 style keyboard uses scan codes to communicate key press data. Nearly all keyboards in use today are PS/2 style. Each key has a single unique scan code that is sent whenever the corresponding key is pressed. If the key is pressed and held the keyboard repeatedly send the scan code every 100 ms or so. When a key is released, the keyboard sends a F0 key up code, followed by the scan code of the released key. The key - board sends the same scan code, regardless if a key has different shift and non shift characters and regardless whether the shift key is pressed or not. The host determines which character is intended.

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A mouse generates a clock and data signal when moved, otherwise these signals remain high indicating the idle state. Each time the mouse is moved, the mouse send three 11 bit words to the host. Each of the 11- bit words contains a 0 start bit, followed by 8 data bits, fallowed by odd parity bit, and terminated with a 1 stop bit. Each data transmission contains 33 total bits, where bits 0, 11 and 22 are 0 start bits and bits 10, 21 and 32 are 1 stop bits. A PS/2 mouse employs a relative coordinate system where in moving the mouse to the right generates a positive value in the x field and moving to the left generates a negative value in the y field and moving down represents a negative value. The XS and YS bits in the status byte define the sign of each value, where a 1 indicates a negative value.

2.1.7: RS 232 Port:

The Spartan 3 starter kit board has an Rs 232 serial port. The Rs 232 transmit and receive signal appear on the female DB9 connector. The connector is a DCE style port and connects to the DB9 DTE style serial port connector available on most personal computers and work stations. Use a standard straight through derail cable to connect the Spartan 3 starter kit board to the PCs serial port. The connection between the FPGA and the DB9 connector, including the maxim MAX3232 RS - 232 voltage converter. The FPGA supplies serial output data as LVTLL or LVCMOS levels to the maxim device, which in turn, converts the logic value to the appropriate RS 232 voltage level.

Signal RxD TxD RxD A TxD A

FPGA Pin T13 R13 N10 T14

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An auxiliary Rs 232 serial channel from the maxim device is available on two 0.1 inch stake pins, indicated as J1 in the schematic. The J1 stake pins are in the lower left corner of the board, to the right of the DB9 serial connector, below the maxim RS 232 voltage translator and to the left of the individual LEDs. The transmitter output from the maxim device driver the bottom stake pin while the receiver input connects to the top stake pin.
2.1.8: Clock Sources:
The Spartan 3 starter kit board has a dedicated 50 Mhz series clock oscillator source and an optional socket for another clock oscillator source. The 50 Mhz clock oscillator is mounted on the bottom side of the board, indicated. Use the 50 Mhz clock frequency as is or derive other frequencies using the FPGAs digital clock managers (DCMS).

Clock Oscillator Sources:

Oscillator Source
50 MHz Socket

FPGA Pin
T9 D9

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2.2.1.1.2: Viewdata:
viewdata is a videotext implementation. It is a type of information retrieval service in which a subscriber can access a remote data base via a common carrier channel, receive requested data on a video display over a separate channel. Samuel fedida was credited as inventor of the system. The access, request and reception are usually via common carrier broadcast channels. This is in contrast with Tele text.

Viewdata Graphics used in the experimental phone directory of Post office telecommunications in 1977. The image is a graphical representation of the post office/ British Telecom research laboratories in Suffolk, England. Note the tecontinue rather than the correct # Te continue, showing a common rendering error.

2.2.1.1.3: VT100:
It was introduced in August 1987, following its predecessor, the VT52 and communicated with its host system over serial lone using the ASCII character set and control sequences standardized by ANSI. The VT100 was also the first digital mass market terminal to in corporate Graphic rendition as well as a selectable 80 or 132 column display.

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All setup of the VT100 was accomplished using interactive displays presented on the screen, the setup data was stored in non volatile memory within the terminal. The VT100 also introduced an additional character set that allowed the drawing of on screen forms.

2.2.1.1.4: VT52:
The VT52 was a CRT base computer terminal produced by digital equipment corporation introduced in September 1975. It provided a screen of 24 rows and 80 columns of text and supported all 95 ASCII characters as well as 32 graphics characters.

It supported asynchronous communication at baud rates up to 9600 bits per second and did not require any fill characters. The terminal also introduced a separate function keypad that allowed gold key editing.

2.2.1.2: File Transfer:

2.3: VHDL:

2.3.1: Entity:
Entity is a most basic building block in a design.

2.3.2: Architecture:
Architecture describes the behavior of the entity.

2.3.3: Configuration:
A configuration can be considered like a parts list for a design. It describes which behave to use for each entity, much like a parts to use for each part in the design.

2.3.4: Package:
Package is a collection of commonly used data types and subprograms used in a design.

2.3.5: Driver:
This is a source on a signal. If a signal is driven by two sources, then when both sources are active, the signal will have two drivers.

2.3.6: Bus:
Bus is a special kind of signal that may have its drivers turned off.

2.3.7: Attribute:
Attribute that are attached to objects or predefined data about objects.

2.3.8: Generic:
A generic is term for a parameter that passes information to an entity. If an entity is a gate level model with a rise and a fall delay values for the rise and fall delay could be passed into the entity with generics.

2.3.9: Process:
Process is the basic unit of execution in VHDL. All operations that are performed in a simulation are broken into single or multiple processes.

2.3.10: Logical Operators:

NOT,AND,NAND,OR,NOR,XOR,XNOR.

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2.3.11: Data Type:

2.3.11.1: Predefine Types:

Boolean : False , True. Bit : 0 , 1. Bit vector : 101010. Integers : range (2^(31 1)) to (2^(31-1)). Floating real : -1.E38 to 1.0E38. Time Character String Enumerated (User defind) Records, File, Access type (Used in simulation only) Note: U X 0 1 Z W L H Uninitialized. Forcing Unknown. Forcing 0. Forcing 1. High Impedance. weak Unknown. Weak 0. Weak 1. Do not care.

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2.3.16: Value Attributes:

Right returns right most value in array. Left returns left most value in array. high returns highest index of an array. low returns lowest index of an array. length returns the length of an array. ascending returns Boolean true if array is ascending.

2.3.17: Function Attributes:

event returns true if the signal had an immediate event on it. active returns true if the signal had a scheduled event on it in the current cycle. last_event returns time since the last event on a signal. last_value returns the value of a signal prior to an event. last_active returns the time since the last scheduled event on a signal. Note: rising_edge is a function pre defined, falling_edge also pre defined defined.

2.3.18: Constants:
Useful for look up tables, -- Holding circuit parameters, -- ROM functions. Most be declared before they can be used. Constants can be declared in entity, architecture, process, procedure, package or function.

2.3.19: Constant declaration:

Constant name_of_constant : type := value of constant;

2.3.20: Entity Ports and Mode:

The mode out problem: entity port signal of mode out can not feedback into the entity. Use a local signal for feedback. Buffer mode can be used for feedback. Using mode buffer can cause problems with nested entities. A wire running straight through multiple levels of entities must be mode buffer in all entities if it is mode buffer in any entity. examples in this class will use local feedback.

2.3.21: Enumerated Types:

Enumerated types can be user defined. All values must have unique names. It can be used to hold the states of state machine. Declare a new type with the type keyword ( specify the range of value the new type can have. Make a signal / Variable assigning it the new type. Syntax: Type <type_name> is (<string1>), <string2>, .);

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2.3.22: Recipe coding of state machines:

Use two state variables, one for present state create next state from present and one for next state. Write two processes: process 1 state and control inputs. Assign output based on present state. Process 2 Asynchronous reset, optional enables. Clock next state into present state.

2.3.23: Hierarchy:

2.3.23.1: Hierarchy a first look:

Using components and port maps, External design files, system supplied ports.

2.3.23.2: Component Declaration:

A declaration statements does not create new logic. Used inside the architecture before begin. Component must be declared before they can be used. Components are used to point the synthesis engine to other entities. Other entities can be in the design directory or located in libraries. Syntax: Component component_name Generic (generic_list); Port(Port_list); End component;

2.3.24: Port Map:

Used in conjunction with component to instantiated a port. Used to map signals into a component. Can map by position or name. Syntax: two methods positional and name association.

2.3.25: User defined Arrays:

array must be declared before use. Array members must have a type. Be careful with more then two dimensional arrays for synthesis, after works in simulation and not synthesis. Syntax: Type array_name is array (range) of type of array member;

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2.4: Verilog:
Verilog is a hardware description language (HDL). HDL is used to describe a digital system for example, a network switch, a microprocessor or a memory or simple flip flop. Verilog is case sensitive. All verilog keywords are lower case. Identifier are name used to given an object, such as a register or a function or a module, a name so that it can referenced from other places in a description. Design Styles: . Bottom up Design . Top down Design

2.4.1:Abstraction Level of Verilog:

. Behavioral level . Register Transfer level . Gate level

2.4.1.1: Behavioral level :

The level describes a system by concurrent algorithms (Behavioral). Each algorithm itself sequential, that means it consists of instructions that executed one after the other. Functions, tasks, always blocks are the main elements.

2.4.1.2: Register Transfer level:

Designs using the register transfer level specify the characteristics of a circuit by operations and the transfer of data b/w registers. Modern definition of RTL code is any code that is synthesizable is called RTL code. RTL design contains exact timing possibility, operations are scheduled to occur at certain times.

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2.4.1.3: Gate level:

Within the logic level the characteristics of a system are described by logical links and their timing properties. All signals are discrete signal. They can only have definite logical values (0,1,X,Z). The usable operation are predefined logic primitives (AND, OR, NOT). Using gate level modeling might not be a good idea for any level of logic design. Gate level code is generated by tools like synthesis tools and this net list is used for gate level simulation and for backend. Verilog has built in primitives like gates, transmission gates and switches. Gates have one scalar O/P and multiple scalar I/P. The 1st terminal in the list of gate terminals is an O/P and other terminals are I/P. transmission gates are bi directional and can be resistive or non resistive. Transmission gate tran and rtran are permanently on and do not have a control line. Tran used to interface two wire with separate drives and rtran can be used to weaken signals. Resistive devices reduce the signal strength which appears on the output by one level. All the switches only pass signals from source to drain, incorrect wiring of the devices will result in high impedance output.

2.4.2: Gate and Switch delays:

2.4.2.1: Rise delays:

Rise delay is associated with a gate output transition to 1 from another value (0, X, Z).

2.4.2.2: Fall delays:

The fall delay is associated with a gate O/P transition to 1, X, Z from another value.

2.4.2.3: Turn off delays:

Gate output transition to Z from another value (0, 1, X).

2.4.2.4: Minimal delays:

Minimum delay value that the gate is expected to have.

2.4.2.5: Typical delays:

Typical delay value that the gate is expected to have.

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2.4.2.6: Maximum delays:

Maximum delay value that the gate is expected to have. Verilog has built in primitives like gates, transmission gates and switches. This is rather small number of primitives, if we need more complex primitives, then verilog provides UDP or simply user defend primitives. By using UDP we can model Combinational logic and sequential logic.

2.4.3: Identifiers:
Identifiers must start begin with an alphabetic character or the underscore character(_). Identifiers may contain (a z, A Z, _ , $). Identifier can be long up to 1024 character.

2.4.4: Data Types:

2.4.4.1: Nets:
Represents structural connections between components.

2.4.4.2: Registers:
Represent variable used to store data.

2.4.4.3: Register data types:

Register store the last value assigned to them until another assignment statement changes their value. Register represent data storage constructs. You can create arrays of register called memories. Register data types are used as variables in procedural blocks. A register data type is required if a signal is assigned a value with in a procedural block. Procedural blocks begin with keyword initial and always. reg: unsigned variable. integer: signal variable 32 bits. time: unsigned integer 64 bits. Real: Double precision floating point variable.

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2.4.5: String: A string is a sequence of characters enclosed by double quotes and all
contained on signal line. One eight bit ASCII value representing one character. No extra bits are required to hold a termination character. \n \t \\ \ \ddd %% New line character. Tab character. Back slash (\) character. Double quote () character. A character specified in 1 3 octal digits. Percent (%) character.

2.4.6: Operators:

2.4.6.1: Logical Operators:

! (NOT), && (AND), || (OR).

2.4.6.2: Bit wise Operators:

~ (Negation), & (AND), | (Inclusive OR), ^ (Exclusive OR), ^~ or ~^ (Exclusive NOR).

2.4.6.3: Reduction Operators:

& (AND), ~& (NAND), | (OR), ~| (NOR), ^~ or ~^ (XNOR), ^ (XOR).

2.4.6.4: Shift Operators:

<< (Left Shift), >> (Right Shift). The left operand is shifted by the number of bit positions given by the right operand. The vacated bit positions are filled with zeroes.

2.4.6.5: Concatenation Operators:

{}.

2.4.6.6: Replication Operators:

{{}}.

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2.4.6.7: Conditional Operators:

Cond_expr ? True_expr : False_expr.

2.4.7: Procedural Blocks:

Two type of procedural blocks in verilog.

2.4.7.1: Initial:
Initial blocks execute only once at time zero.

2.4.7.2: Always:
Always blocks loop to execute over and over again, in other words as name means, it executes always. Always blocks waits for the event, here positive edge of clock, where as initial block without waiting just executed all the statements within begin and end statement. If a procedure block contain more than one statement, those statement must be enclosed within: a) Sequential begin end Block. b) Parallel Fork join Block.

2.4.8: Blocking Assignment:

Blocking assignment are executed in the order they are coded, hence they are sequential. Since they block the execution of next statement, till current statement is executed, they are called blocking assignments. Symbol =

2.4.9: Non Blocking Assignment:

Non Blocking assignment are executed in parallel. Since the execution of next statement is not blocked due to execution of current statement, they are called non blocking statement. Symbol <=

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2.4.10: Conditional Statement if else:

when more than one statement needs to be executed for a if conditions, then we need to use begin and end. We normally do not include reset checking in priority as this does not fall in the combo logic input to the flip flop. When we need priority logic, we use next if else statements. On other end if we do not to implement priority logic, knowing that only that only one I/P is active at a time.

2.4.11: Case Statement:

The case statement compares a expression to a series of cases and executes the statement or statement group associated with the first matching case. Case statement supports single or multiple statements. Group multiple statements using begin and end keywords.

2.4.12: Loop Statements:

2.4.12.1: Forever:
Forever statement executes continually, the loop never ends. Narmally we use forever statement in initial blocks. Syntax : forever <Statement>. If no timing construct is present in the forever statement, simulation could hang.

2.4.12.2: Repeat:
The repeat loop executes statement fixed <number> of times. Syntax: repeat <Number> <Statement>.

2.4.12.3: While:
The while loop executes as long as an evaluates as true. Syntax : while ().

2.4.12.4: For:
Syntax: for (initial assignment; expression; step assignment); Note : i ++ does not have in verilog. i = i + 1 in verilog.

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2.4.13: Continuous Assignment statements:

Continuous assignment statements drives nets. They represent structural connections. a) They are used for modeling tri state buffers. b) They can be used for modeling combinational logic. c) They are outside the procedural blocks. d) The continuous assign overrides any procedural assignments. e) The left hand side of a continuous assignment must be net data types. Syntax : Assign (strength, strength) # (delay) net = expression;

2.4.14: Propagation Delay :

Continuous assignments may be have a delay specified, only one delay for all transitions may be specified. Syntax : assign #(A minimum : Typical : maximum delay range may be specified) To model sequential logic, a procedure block must be sensitive to positive edge or negative edge of clock. Model asynchronous reset, procedure block must be sensitive to both clock and reset. All the assignments to sequential logic should be made through non blocking assignments. Some time it tempting to have multiple edge triggering variables in the sensitive list, this is fine for simulation, but for synthesis this does not make sense. Delays the execution of a procedural statement by specific simulation time. Syntax : # <Time> <Statement>. Delays the execution of the next statement until the specified transition on a signal. {edge sensitive event controls} Syntax: @(<Posedge > | <Negedge> signal) <statement>. Level Sensitive even controls (Wait statements) delay execution of the next statement until the evaluates as true. Syntax : Wait(). Intra assignment timing controls evaluate the right side expression right always and assigns the result after the delay or event control. In non intra assignment controls right side expression evaluated after delay or event control.
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Syntax: a = # 10 2.{intra assignment}. Modeling combo logic with continuous assignments, whenever any signal changes on the right hand side, the entire right hand side is re evaluated and the result is assigned to the left hand side.

2.4.15: Task :
Task are used in all programming languages, generally known as procedures or sub routines. Task are defined in the module in which they are used. It is possible to define task in separate file and use compile directive include to include the task in the file which instantiates the task. Task can include timing delays, like posedge, negedge, #delay and wait. Task can have any number of I/P and output. The variables declared within the task are local to that task. Task can take, drive and source global variables, when no local variables are used. Task can call another task or function. Task can be used for modeling both combinational and sequential logic. Task begin with keyword task and ends with keyword task. Local variables are declared after I/P and O/P declaration.

2.4.16: Function:
Function is same as task, with very little difference, like function can not drive more then one output, can not contain delays. Function can not include timing delays, like posedge, negedge, #delay. Function executed in zero time delay. Function can have any number of I/P but only one output. Function can call other functions, but can not call task.

2.4.17: $display:
Display once every time they are executed.

2.4.18: $monitor:
Display every time, one of its parameters changes.

2.4.19: $Strobe:
Display the parameters at the very end of the current simulation time unit rather than exactly where it is executed.

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2.4.20: $time :
Return the current simulation time as a 64 bit.

2.4.21: $Stime:
Return the current simulation time as a 32 bit.

2.4.22: $realtime:
Return the current simulation time a real number.

2.4.23: $reset:
It resets the simulation back to time 0.

2.4.24: $stop:
Halts the simulator and puts it in the interactive mode, where user can enter commands.

2.4.25: $finish:
exits the simulator back to the operating system.

2.4.26: $random:
it generates a random integer every time it is called. Note : %d %h %b %c %s %5d decimal hexadecimal binary character string gives exactly 5 spaces for the number.

2.4.27: Initializing Memories:

A memory array may be initialized by reading memory pattern file from disk and storing it on the memory array by using $ readmemb and $ readmemh.

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2.4.27.1: $redmemb:
It is used for binary representations of memory content.

2.4.27.2: $readmemh:
it is used for hex representation of memory content.

Syntax : $readmemh (file name, mem-array, start_adder, stop_addr).

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2.5: Xilinx ISE Design Suite 13.1: 2.5.1: Getting started:

2.5.1.1: Hardware Requirements:

Spartan -3 startup kit, Containing the Spartan 3 startup kit demo board.

2.5.1.2: Starting the ISE Software:

To start ISE, Double click the desktop icon OR Start All Programs Xilinx ISE 13.1 Project Navigator.

2.5.2: Create a New Project:

Select File New Project Type Project Name

Enter or Browse to allocation (directory path) for the new project. A tutorial subdirectory is created automatically. Verify that HDL is selected from the Top Level source type list click Next Fill in the properties in the table as shown below:

Product category Family Device Package Speed Grade Top Level Source Synthesis Tool Simulator Preferred Language

All Spartan 3 XC3S200 FT256 -4 HDL XST (VHDL/Verilog) ISE simulator (VHDL/Verilog) VHDL/Verilog

. Click Next.

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2.5.3: Create an HDL Source:

2.5.3.1: Creating a VHDL /Verilog Source: . Click the New Source button in the New Project Wizard.
. Select VHDL module/Verilog module. . Type the file name. . Verify that the Add to Project check box is selected. . Click Next. . Click Finish.

2.5.3.2: Checking the Syntax of the design source: . Verify that Synthesis/Implementation is selected from the drop down list in the
sources window.

. Select the design source in the sources window to display the related processes in the
processes window.

. Click the + next to the synthesize XST process to expand the process group. . Double Click the check syntax process. . Close the HDL file.

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2.5.4: Design Simulation:

L) Assign New configuration file dialog box appears to assign a configuration file to the XC3s200 device in the JTAG chain. M) If you get a warning message. Click ok. N) Select bypass to skip any remaining devices. O) Right click on the XC3s200 device image and select program. P) Click OK. Q) Close iMPACT without saving.

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Chapter 3: Research Methodology/Experimental Setup:

3.1: UART:

3.1.1:Introduction
An UART (universal asynchronous receiver/transmitter) is responsible for performing the main task in serial communications with computers. The device changes incoming parallel information to serial data which can be sent on a communication line. UART is circuit that sends parallel data through a serial line. UART are frequently used in conjunction with the electronic industries alliance RS-232 standard, ethic specifies the electrical, mechanical, functional and procedural characteristics of two data communication equipment. Because the voltage level defined in RS-232 is different from that of FPGA input/output, a voltage converter chip is needed between a serial port and an FPGAs input/output pins. The S3 board has RS232 port with the standard nine- pin connector. The board contains the necessary voltage converter chip and configures the various RS- 232s control signals to automatically generate acknowledgment for the PCs serial port. A standard straight through serial cable can be used to connect the S3 board and PCs serial port. The S3 board basically handles the RS- 232 standard and we only need to concentrate on the design of the UART circuit.

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3.1.2: Pin diagram of the UART:

LED_OUT[7:0] CLK

Pin Diagram Of UART

3.1.3: Pin description of the UART:

PIN Name CLK Rx Tx LED_OUT

3.1.8: Functional Description of FSM in each state:

State S0 : here count is input for state S0. When count >= 0 and count <= 81 then baud set to be Low. When count > 81 then it goes to next state S1.

State S1: here also count is input for state S1. When count > 81 and count < 163 then baud set to be high. When count = 163 then it goes to next state S0.

Initial value of count set to be 0. Each and every posedge clock(clk) the comparator checks or we can say compare the count value and register value. If count value equal to register value then comparator generate high signal which is 1. If count value not equal to register value then comparator generate low signal which is 0. If comparator generate high signal then count become 0. If comparator generate low signal then count get incremented by one in each and every posedge clock(clk).

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3.1.9: Baud rate generator for transmitter

No over sampling involved, the frequency of the mode count is 16 times slower the UART receiver. Transmitter baud rate generator use 16 times deviser in receiver baud rate generator output(baud) and generate the Tx_baud_rate.

3.1.10: FSM of baud rate generator for Transmitter:

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3.1.11: Functional Description of FSM in each state:

State S0 : here count is input for state S0. When count >= 0 and count <= 7 then baud set to be Low. When count > 7 then it goes to next state S1.

State S1: here also count is input for state S1. When count > 7 and count <= 15 then baud set to be high. When count > 15 then it goes to next state S0.

Initial value of count set to be 0. Each and every posedge clock(baud_clk) the comparator checks or we can say compare the count value and register value. If count value equal to register value then comparator generate high signal which is 1. If count value not equal to register value then comparator generate low signal which is 0. If comparator generate high signal then count become 0. If comparator genrate low signal then count get incremented by one in each and every posedge clock(baud_clk).

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3.1.12.3: Functional Description of FSM in each state:

State S0 : here Rx(one bit) is input for state S0. When Rx = high, then count1, byte_done1 and byte_done set to be Low. When Rx = low, then it goes to next state S1. State S1: here count1 is input for state S1. When count1 >= 0 and count1 < 7, then count2 set to be 0 and count1 get incremented by one with each posedge clk. When count1 > 7, then it goes to next state S2.

State S2: here count2 is input for state S2. When count2 >= 0 and count2 < 15, then count2 get incremented by one with each posedge clk. when count2 = 15, then it goes to next state S3.

State S3: here Num is input for state S3.Num signal used to indicate position of data bit. When num >= 0 and num < 8, then it goes to next state S2. Corsponding to num value the data bit shifted in the 8 bit register. When num = 8, then it goes to next state S4. State S4: here count3 is input for state S4. When count3 >= 0 and count < 15,then num set to be 0 and count3 get incremented by one with each posedge clk. When count3 = 15, then it goes to next state S5. State S5: here byte_done1 is input for state S5. When byte _done = low, then byte_done set to be high and 8 bit data bus Assign to data_out. When byte_done = high, then it goes to next state S0.

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3.1.14: asynchronous FIFO Interface circuit

The receivers interface circuit has two functions. a) It provides a mechanism to signal the availability of a new word and to prevent the received word from being retrieved multiple time. b) It can provide buffer space between the receiver and the main system. There are tree commonly used schemes : a) A flag FF b) A flag FF and one word buffer c) A FIFO buffer The old word will be over written, an error known as data overrun. FIFO is used in the project to prevent the overrun problem.

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3.1.14.1: FSM of write in FIFO:

3.1.14.2: Functional Description of FSM in each state:

State S0 : here data_in_enable is input for state S0. When data_in_enable = low, then wr_done set to be low. When data_in_enable = high, then it goes to next state S1. State S1 : here wr_done is input for state S1. When wr_done = low, then wr_address get incremented by one with respect to each and every posedge clk and corresponding to wr_address the incoming data stored in the FIFO memory. When wr_done = high, then it goes to next state S0.

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3.2.2: Horizontal Synchronization:

A detailed timing diagram of one horizontal scan. A period of the hsync signal contains 800 pixels and can be divided into four regions.

3.2.2.1:Display: Region where the pixels are actually display on the screen. The length
of this region is 640 pixels.

3.2.2.2: Retrace: Region in which the electron beams return to the left edge. The video
signal should be disabled (i. e. , black), and the length of this region is 96 pixels.

3.2.2.3: Right border: Region that forms the right border of the display region. It is
also known as the front porch (i. e. , porch before retrace). The video signal should be disabled and the length of the region is 16 pixels.

3.2.2.4: Left border: Region that forms the left border of the display region. It is also
know as the back porch (i. e. , porch after retrace). The video signal should be disabled and the length of this region is 48 pixels. The hsync signal can be obtained by a special mod 800 counter and a decoding circuit. Start the counting from the beginning of the display region. This allows us to use the counter. This allows us to use the counter output as the horizontal (X- axis) coordinate. This output constitutes the pixel x signal. The hsync signal goes low when the counters output is between 656 and 751. CRT monitor should be block in the right and left borders and during retrace. We use the h_video_on signal to indicate whether the current horizontal coordinate is in the displayable region. It is asserted only when the pixel count is smaller than 640.

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3.2.2.5: FSM of Horizontal Synchronization:

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3.2.2.6: Vertical Synchronization:

During the vertical scan, the electron beams move grodully from top to bottom and then return to the top. This corresponds to the time required to refresh the entire screen. The time unit of the movement is represented in terms of horizontal scan lines. A period of the Vsync signal is 525 lines can be divided into four regions.

3.2.2.6.1: Display: Region where the horizontal lines are actually displayed on the
screen. The of this region is 480 lines.

3.2.2.6.2: Retrace: Region that the electron beams to the top of the screen. The vido
signal should be disabled and the length of this region is 2 lines.

3.2.2.6.3: Bottom Border: Region that forms the bottom border of the display region. It
is also known as the front porch (i. e. , porch before retrace). The video signal should be disabled and the length of this region is 10 lines.

3.2.2.6.4: Top Border: Region that forms the top border of the display region. It video
signal should be disabled and the length of this region is 33 lines.

3.2.3.1: FSM of Clock for vertical synchronization:

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3.2.3.2: FSM of Vertical synchronization:

3.2.4: Timing Calculation of VGA synchronization signals:

Pixel rate is determined by three parameters: P The number of pixels in a horizontal scan line. For 640 by 480 resolution, it is P = 800 pixels/Line. L The number of lines in a screen () for 640 by 480 resolution, it L = 525 lines/ screen.
S The number of screens per second. For flicking free operation, we can set to S screens/ Second. 60

The S parameter specifies how fast the screen should be refreshed. For a human eye, the refresh rate must be at least 30 screens per second to make to monitor usually has a much higher rate, such as the 60 screens per second specification above. The pixel rate can be calculated by the three parameters : Pixel Rate = P * L * S = 25 M Pixels/Second.

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3.2.5: Overview Of the pixel Generation circuit:

The Pixel generation circuit generates the 3 bit RGB signal for the VGA port. The external control and data signals specifify the content of the screen and the screen and the pixel_x and pixel_y signals from the VGA _sync circuit provide the current coordinates off the pixel. We divided this circuit into three broad categories:

3.2.5.1: Bit Mapped Scheme:

A video memory is used to store the data to be display on the screen. Each pixel of the screen is mapped directly to a memory word and the pixel_x and Pixel_y signals from the address. A graphics processing circuit continuously updates the screen and writes relevant data to the video memory. A retrieval circuit continuously reads the video memory and routes the data to the data to the RGB signal. This is the scheme used in todays high performance video controller. For 640 by 480 resolution, there are about 310K (i. e. , 640 * 480) pixels on a screen. This translates to 310 K memory bits for a monochrome display and 930 K memory bits (i. e. , 3 bits per pixel) for a 3 bit color display.

3.2.5.2: Tile Mapped Scheme: It is used as a alternative to reduce the memory

requirement. We group a collection of bits to form a tile and each treat each tile as a display unit. We can define an 8 by 8 square of pixels as a title. The 640 by 480 pixel oriented screen becomes an 80 by 60 till oriented screen. Only 4800 words are need for the title memory. The number of bits in a word depends on the number of tile patterns. If there are 32 tile patterns, each word should contain 5 bits and the size of the tile memory is about 24 K bits. The till-mapped scheme usually requires a ROM to store the tile patterns it is called as pattern memory. Each 8 by 8 tile pattern requires 64 bits and the entire 32 patterns need 2K bits. The overall memory requirement is about 26K bits, which is much smaller than the 310 K bits of the bit mapped scheme.

3.2.5.3: Object Mapped Scheme: The video display can be very simple and
contains only a few objects. Instead of wasting memory to store a mostly blank screen we can generate these objects using simple object generation circuit. Which is called as object mapped scheme. The three schemes can be mixed together to generate a full screen. Bit mapped scheme to generate the background. Object mapped schemed scheme to produce the main objects. We can also use a bit mapped scheme for one portion of a screen and tile mapped text for another part of the screen.

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3.2.5.4: Graphic Generation With An Object Mapped Scheme:

An object generation circuit performs the following tasks: a) It keep the coordinates of the current object and compares them with the current scan location provided by the pixel_x and Pixel_y signal. b) If the current scan location falls with the region, it asserts the obj-i-on signal to indicate that the current scan location is within the region of the ith object and the object should be turned on. c) It specifies the desired color in the obj-i-rgb signal. The rgb mux circuit performs multiplexing according to an internal prioritize scheme. It examines various obj-i-on signal and determines which object obj-1-rgb signal is to be routed to the rgb output. The prioritizing scheme prioritizes the order of the displays when multiple obj-i-on signal are asserted at the same time. It corres - propounds to selecting an object for the foreground.

3.2.5.5: FSM Of video ON/OFF Signal:

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3.3: Conclusion and scope for future work.

In this project we had design of UART in VHDL language and VGA in verilog language and simulation done in Xilinx ISE Design Suite 12.2 and then we got the proper simulated behavioral result and RTL schematic view and then implemented design and generated programming file which is diffused in side the Spartan 3 FPGA board. Tested the UART VHDL code and VGA Verilog code by using terminal. During this project we got know about UART and VGA functionality.

3.4: Bibliography:
1. Hand book of FPGA Prototyping by VHDL Examples, by Pong P. chu. 2. Hand book of VHDL Programming by Example (Fourth edition), by Dougles L. Perry. 3. PPT of VHDL by Avent Spees Way Design Workshop. 4. www.applied VHDL.com

5. ISE Quick start tutorial www.xilinx.com.

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3.5: Appendices

3.5.1: VHDL CODE OF UART:

3.5.1.1: Top Module:

---------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 14:14:55 11/21/2011 -- Design Name: -- Module Name: topcode - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

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component Rxcode is Port ( Rx : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0); baud_clk : in STD_LOGIC ; byte_done : out std_logic); end component; component Txbaud is Port ( baud_clk : in STD_LOGIC; baud : out STD_LOGIC); end component; component Txcodefull is Port ( data_in_enable : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR (7 downto 0); Tx : out STD_LOGIC; baud_clk : in STD_LOGIC); end component; component loopcode is Port ( Tx_baud_clk : in STD_LOGIC; Rx_baud_clk : in std_logic; data_in : in STD_LOGIC_VECTOR (7 downto 0); data_out : out STD_LOGIC_vector(7 downto 0); data_in_enable : in STD_LOGIC; data_out_enable : out STD_LOGIC); end component; begin Rx_baud_program : Rxbaud Port map( clk => clk, baud => xr); Rx_program : Rxcode port map(Rx => Rx, data_out => D, baud_clk => xr, byte_done => z); Tx_baud_program : Txbaud port map(baud_clk => xr, baud => xt); Tx_program : Txcodefull port map(data_in_enable => T, data_in => din, Tx => Tx, baud_clk => xt); Loopprogram : loopcode port map(Tx_baud_clk => xt, Rx_baud_clk => xr, data_in => D, data_out => din, data_in_enable => z, data_out_enable => T ); LED_OUT <= din; end Behavioral;

3.5.1.2: Receiver baud generator code

----------------------------------------------------------------------------

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------- Company: -- Engineer: --- Create Date: 03:29:41 11/18/2011 -- Design Name: -- Module Name: RXbaud - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity RXbaud is Port ( clk : in STD_LOGIC; baud : out STD_LOGIC); end RXbaud; architecture Behavioral of RXbaud is type shukla1 is(s0,s1,s2); signal Nx_state,Pr_state : shukla1; signal count :integer range 0 to 163 := 0; begin process(Pr_state,count) begin case Pr_state is when s0 => if((count >= 0) and (count <= 81))then Nx_state <= s0; else Nx_state <= s1; end if; when s1 => if((count >81) and (count < 163))then Nx_state <= s1; else Nx_state <= s0; end if; when others => Nx_state <= s0; end case;

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end process; process(clk) begin if(clk' event and clk ='1')then Pr_state <= Nx_state; case Nx_state is when s0 => baud <= '1'; when s1 => baud <= '0'; when others => baud <= '1'; end case; end if; end process; process(clk,count) begin if(clk' event and clk = '1')then count <= count + 1; else count <= count; end if; if(count = 163 )then count <= 0; end if; end process; end Behavioral;

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num <= 0; count3 <= count3 + 1; when s5 => byte_done1 <= '1'; byte_done <= '1'; data_out <= data; when others => byte_done <= '0'; end case; end if; end process; end Behavioral;

3.5.1.4: Transmitter baud generator code:

---------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 03:21:38 11/18/2011 -- Design Name: -- Module Name: Txbaud - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL;

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process(Pr_state,count) begin case Pr_state is when s0 => if((count >= 0) and (count <= 7))then Nx_state <= s0; else Nx_state <= s1; end if; when s1 => if((count >= 7)and (count <= 15))then Nx_state <= s1; else Nx_state <= s0; end if; when others => Nx_state <= s0; end case; end process; process(baud_clk) begin if(baud_clk' event and baud_clk ='1')then Pr_state <= Nx_state; case Nx_state is when s0 => baud <= '1'; when s1 => baud <= '0'; when others => baud <= '1'; end case; end if; end process; process(baud_clk,count) begin if(baud_clk' event and baud_clk = '1')then count <= count + 1; else count <= count; end if; if(count = 16 )then count <= 0; end if; end process; end Behavioral;

Saurabh Shukla

count = count + 1; end end S1: begin if((count >= 640) && (count <= 655)) begin H_video_on = 0; H_synch = 1; Pixel_x = count; count = count + 1; end end S2: begin if((count >= 656) && (count <= 751)) begin H_video_on = 0; H_synch = 0; Pixel_x = count; count = count + 1; end end S3: begin if((count >= 752) && (count <= 799)) begin H_video_on = 0; H_synch = 1; Pixel_x = count; count = count + 1; end if(count > 799) begin count = 0; end end default: begin count = 0; end endcase end end endmodule

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input [9:0]Pixel_x; input [9:0]Pixel_y; reg object1; reg object2; reg object3; reg [1:0]Nx_state; reg [1:0]Pr_state; always@(Pr_state or Pixel_x or Pixel_y or video_on) begin Nx_state = S0; object1 = 1; object2 = 0; object3 = 0; case(Pr_state) S0: begin if((Pixel_x >= 32) && (Pixel_x <= 35) && (video_on)) begin object1 = 1; object2 = 0; object3 = 0; Nx_state = S0; end else begin object1 = 0; object2 = 0; object3 = 0; Nx_state = S1; end end S1: begin if((Pixel_x >= 200) && (Pixel_x <= 205) && (Pixel_y >= 104) && (Pixel_y <= 175) && (video_on)) begin object1 = 0; object2 = 1; object3 = 0; Nx_state = S1; end else begin object1 = 0; object2 = 0; object3 = 0; Nx_state = S2; end end S2: begin if((Pixel_x >= 300) && (Pixel_x <= 350) && (Pixel_y >= 190) && (Pixel_y <= 210) && (video_on)) begin object1 = 0; object2 = 0; object3 = 1;

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Nx_state = S2; end else begin object1 = 0; object2 = 0; object3 = 0; Nx_state = S0; end end default: begin object1 = 0; object2 = 0; object3 = 0; Nx_state = S0; end endcase end always@(posedge clk or posedge Rst) begin if(Rst) begin Pr_state = S0; end else begin Pr_state = Nx_state; end end endmodule

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3.6: RESULT 3.6.1: RTL Schematic View

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3.6.2.3: Receiver Simulated behavioral result

3.6.2.4: Transmitter baud generator Simulated behavioral result

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3.6.3.2: Result of WALL object:

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3.7: ACRONYMS:
1: CLK = 2: baud = 3: Tx = CLOCK mode count

Transmitter

4: Rx = Receiver 5: LED_OUT = FPGA LED 6: baud_clk = mode count CLOCK 7: Tx_baud_clk = Transmitter mode count CLOCK(Transmitter baud CLOCK) 8: Rx_baud_clk = Receiver mode count CLOCK(Receiver baud CLOCK) 9: rd_addrs = read address used in FIFO memory 10: wr_addrs = write address used in FIFO memory

MCIS, Manipal University

Page 131

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