ADSP-214xx SHARC Processor Hardware Reference

Includes ADSP-2146x, ADSP-2147x, ADSP-2148x

Revision 1.0, February 2012 Part Number 82-000469-01

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Copyright Information
2012 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA.

Disclaimer
Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

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CONTENTS

CONTENTS PREFACE
Purpose of This Manual .................................................................lxxi Intended Audience .........................................................................lxxi Manual Contents ......................................................................... lxxii Whats New in This Manual ......................................................... lxxv Technical or Customer Support ................................................... lxxvi Registration for MyAnalog.com ............................................ lxxvii EngineerZone ....................................................................... lxxvii Supported Processors ................................................................. lxxviii Product Information ................................................................. lxxviii Analog Devices Web Site ..................................................... lxxviii VisualDSP++ Online Documentation .................................... lxxix Technical Library CD ............................................................ lxxix Notation Conventions .................................................................. lxxx

INTRODUCTION
Design Advantages ........................................................................ 1-1 SHARC Family Product Offerings ........................................... 1-2

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Contents

Processor Architectural Overview .................................................. 1-2 Processor Core ........................................................................ 1-2 I/O Peripherals ....................................................................... 1-2 I/O Processor ..................................................................... 1-3 Digital Audio Interface (DAI) ............................................. 1-3 DAI System Interrupt Controller ........................................ 1-3 Signal Routing Unit ............................................................ 1-4 Digital Peripheral Interface (DPI) ....................................... 1-4 DPI System Interrupt Controller ......................................... 1-4 Signal Routing Unit 2 ......................................................... 1-4 Differences from Previous Processors ............................................. 1-4 I/O Architecture Enhancements .............................................. 1-5 Development Tools ....................................................................... 1-6

INTERRUPT CONTROL
Features ........................................................................................ 2-1 Clocking ...................................................................................... 2-2 Register Overview ......................................................................... 2-2 Functional Description ................................................................. 2-3 Programmable Interrupt Priority Control ................................ 2-3 Peripheral Interrupt ............................................................ 2-5 Software Interrupt .............................................................. 2-5 Peripherals with Multiple Interrupt Request Signals ............. 2-5 System Interrupt Controller .................................................... 2-6 DAI/DPI Interrupt Sources ................................................. 2-7

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DAI Interrupt Latch Priority Option ................................... 2-8 DPI Interrupt Latch ............................................................ 2-9 DAI/DPI Interrupt Mask for Waveforms ............................. 2-9 DAI/DPI Interrupt Mask for Events .................................. 2-10 DAI/DPI Interrupt Service ................................................ 2-10 Interrupt Service ................................................................... 2-11 Core Buffer Service Request (I/O mode) ............................ 2-12 DMA Access ..................................................................... 2-12 Interrupt Latency .................................................................. 2-12 DMA Completion Types ................................................... 2-14 Debug Features ........................................................................... 2-15 Shadow Interrupt Register ..................................................... 2-15

I/O PROCESSOR
Features ........................................................................................ 3-2 Register Overview ......................................................................... 3-3 DMA Channel Registers .......................................................... 3-4 DMA Channel Allocation ................................................... 3-4 Standard DMA Parameter Registers ..................................... 3-4 Extended DMA Parameter Registers .................................... 3-8 Data Buffers ..................................................................... 3-10 Chain Pointer Registers ..................................................... 3-12 TCB Storage ............................................................................... 3-15 Serial Port TCB ..................................................................... 3-15 SPI TCB ............................................................................... 3-15

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UART TCB .......................................................................... 3-16 Link Port TCB ...................................................................... 3-16 FIR Accelerator TCB ............................................................ 3-17 IIR Accelerator TCB ............................................................. 3-18 FFT Accelerator TCB ............................................................ 3-19 External Port TCB ................................................................ 3-20 Clocking .................................................................................... 3-22 Functional Description ............................................................... 3-23 Automated Data Transfer ...................................................... 3-23 DMA Transfer Types ............................................................. 3-23 DMA Direction .................................................................... 3-25 Internal to External Memory ............................................. 3-25 Peripheral to Internal Memory .......................................... 3-25 Peripheral to External Memory (SPORTs) ......................... 3-26 Internal Memory to Internal Memory ............................... 3-26 DMA Controller Addressing .................................................. 3-26 Internal Index Register Addressing .................................... 3-27 External Index Register Addressing .................................... 3-29 DMA Channel Status ............................................................ 3-29 DMA Bus Architecture .......................................................... 3-30 Standard DMA Start and Stop Conditions ............................. 3-31 Operating Modes ........................................................................ 3-31 Chained DMA ...................................................................... 3-31 TCB Memory Storage ....................................................... 3-32

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Chain Assignment ............................................................. 3-33 Starting Chain Loading ..................................................... 3-34 Buffered Chain Loading Register ....................................... 3-35 TCB Chain Loading Priority ............................................. 3-35 Chain Insert Mode (SPORTs Only) ................................... 3-36 Peripheral DMA Arbitration .................................................. 3-36 Peripheral Group Stage 1 Arbitration ................................. 3-36 Peripheral DMA Bus Stage 2 Arbitration ........................... 3-38 External Port DMA Arbitration ......................................... 3-38 External Port Group Stage 1 Arbitration ............................ 3-41 SPORT/External Port Group Stage 2 Arbitration ............... 3-42 External Port DMA Bus Stage 3 Arbitration ....................... 3-42 Fixed Versus Rotating Priority ........................................... 3-44 Peripheral and External Port DMA Block Conflicts ............ 3-44 Interrupts ................................................................................... 3-44 Sources .................................................................................. 3-45 DMA Complete ................................................................ 3-45 Internal Transfer Completion ........................................ 3-45 Access Completion ........................................................ 3-46 Chained DMA Interrupts .................................................. 3-46 Masking ................................................................................ 3-47 Service .................................................................................. 3-47 Interrupt Versus Channel Priorities ........................................ 3-47 Effect Latency ............................................................................. 3-48

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Write Effect Latency ............................................................. 3-48 IOP Effect Latency ............................................................... 3-49 IOP Throughput .................................................................. 3-49 Programming Model ................................................................... 3-50 General Procedure for Configuring DMA .............................. 3-50 Debug Features ........................................................................... 3-50 Emulation Considerations ..................................................... 3-51

EXTERNAL PORT
Features ........................................................................................ 4-2 Pin Descriptions ........................................................................... 4-3 Pin Multiplexing ..................................................................... 4-3 Register Overview ......................................................................... 4-4 External Port ........................................................................... 4-4 Asynchronous Memory Interface ............................................. 4-4 SDRAM Controller ................................................................. 4-4 DDR2 Controller ................................................................... 4-5 Shared DDR2 Memory ........................................................... 4-6 Clocking AMI/SDRAM (ADSP-2147x/ ADSP-2148x Models) ...... 4-6 Clocking AMI/DDR2 (ADSP-2146x Models) ............................... 4-7 External Port Arbiter .................................................................... 4-8 Functional Description ........................................................... 4-8 Operating Mode ................................................................... 4-10 Arbitration Modes ............................................................ 4-10 Arbitration Freezing .......................................................... 4-11

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Asynchronous Memory Interface ................................................. 4-12 Features ................................................................................. 4-12 Functional Description .......................................................... 4-12 Parameter Timing ............................................................. 4-13 Asynchronous Reads ...................................................... 4-14 Asynchronous Writes ..................................................... 4-15 Idle Cycles .................................................................... 4-15 Wait States .................................................................... 4-16 Hold Cycles .................................................................. 4-16 Data Storage and Packing .............................................. 4-16 External Instruction Fetch ..................................................... 4-17 Interrupt Vector Table (IVT) ............................................. 4-17 Instruction Packing ........................................................... 4-18 External Instruction Fetch from AMI Boot Space ............... 4-18 8-Bit Instruction Storage and Packing ................................ 4-19 16-Bit Instruction Storage and Packing .............................. 4-20 Mixing Instructions and Data in External Bank 0 .............. 4-21 Cache for External Instruction Fetch ............................. 4-22 Operating Modes ................................................................... 4-25 Data Packing .................................................................... 4-25 External Access Extension .................................................. 4-25 Predictive Reads ................................................................ 4-26 SDRAM Controller (ADSP-2147x/ADSP-2148x) .................................................... 4-27 Features ................................................................................. 4-27 ADSP-214xx SHARC Processor Hardware Reference ix

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Pin Descriptions ................................................................... 4-28 Functional Description ......................................................... 4-28 SDRAM Commands ........................................................ 4-29 Load Mode Register ...................................................... 4-30 Bank Activation ............................................................ 4-31 Single Precharge ........................................................... 4-31 Precharge All ................................................................ 4-31 Read/Write ................................................................... 4-32 Auto-Refresh ................................................................ 4-34 No Operation/Command Inhibit .................................. 4-34 Command Truth Table ................................................. 4-34 Refresh Rate Control ........................................................ 4-35 Internal SDRAM Bank Access ........................................... 4-37 Single Bank Access ........................................................ 4-37 Multi-Bank Access ........................................................ 4-37 Multi-Bank Operation with Data Packing ..................... 4-39 Timing Parameters ............................................................ 4-40 Fixed Timing Parameters ............................................... 4-40 Data Mask ........................................................................ 4-40 Resetting the Controller .................................................... 4-41 16-Bit Data Storage and Packing ....................................... 4-41 External Instruction Fetch ................................................ 4-42 Interrupt Vector Table (IVT) ........................................ 4-42 Fetching ISA Instructions From External Memory ......... 4-42

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Instruction Packing ....................................................... 4-43 16-Bit Instruction Storage and Packing .......................... 4-43 Fetching VISA Instructions From External Memory ....... 4-44 Mixing Instructions and Data in External Bank 0 ........... 4-46 Cache for External Instruction Fetch ............................. 4-47 Address Versus SDRAM Types ....................................... 4-50 Operating Modes ................................................................... 4-50 Address Mapping .............................................................. 4-50 Address Translation Options .......................................... 4-51 Address Width Settings ................................................. 4-52 16-Bit Address Mapping .................................................... 4-53 Parallel Connection of SDRAMs ....................................... 4-56 Buffering Controller for Multiple SDRAMs ................... 4-57 SDRAM Read Optimization ............................................. 4-57 Core Accesses ................................................................ 4-59 DMA Access ................................................................. 4-60 Notes on Read Optimization ......................................... 4-61 Self-Refresh Mode ............................................................. 4-61 Forcing SDRAM Commands ............................................. 4-62 Force Precharge All ....................................................... 4-63 Force Load Mode Register ............................................. 4-63 Force Auto-Refresh ........................................................ 4-63 DDR2 DRAM Controller (ADSP-2146x) .................................... 4-63 Features ................................................................................. 4-64

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Pin Descriptions ................................................................... 4-64 Functional Description ......................................................... 4-65 DDR2 Controller ............................................................. 4-66 DDR2 Arbiter .................................................................. 4-66 DDR2 PHY ..................................................................... 4-67 DDR2 Memory DLL ........................................................ 4-68 Self Calibration Logic ....................................................... 4-69 Mode Registers ................................................................. 4-69 Load Mode Register ...................................................... 4-70 Load Extended Mode Register ....................................... 4-70 Load Extended Mode Register 2 .................................... 4-70 Load Extended Mode Register 3 .................................... 4-71 DDR2 Commands ........................................................... 4-71 Bank Activation ............................................................ 4-71 Precharge ...................................................................... 4-71 Precharge All ................................................................ 4-72 Burst Read .................................................................... 4-72 Burst Write ................................................................... 4-73 Auto-Refresh ................................................................ 4-74 Self-Refresh Entry ......................................................... 4-74 Self-Refresh Exit ........................................................... 4-75 Precharge Power-Down Entry ....................................... 4-76 Precharge Power-down Exit ........................................... 4-77 No Operation/Command Inhibit .................................. 4-77

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Refresh Rate Control ......................................................... 4-78 Data Mask ........................................................................ 4-80 Resetting the Controller .................................................... 4-80 Automated Initialization Sequence ..................................... 4-80 Initialization Time ........................................................ 4-82 Internal DDR2 Bank Access .......................................... 4-82 16-Bit Data Storage and Packing ................................... 4-87 External Instruction Fetch ............................................. 4-87 Operating Modes ................................................................... 4-88 Address Mapping .............................................................. 4-88 Address Translation Options .......................................... 4-88 Page Interleaving Map ................................................... 4-89 Bank Interleaving Map .................................................. 4-89 Address Width Settings ................................................. 4-90 16-Bit Address Mapping ................................................ 4-91 Address Map Tables ....................................................... 4-91 Parallel Connection of DDR2s .......................................... 4-95 Buffering Controller for Multiple DDR2s ...................... 4-95 Read Optimization ............................................................ 4-95 Read Optimization Modifier ......................................... 4-96 Self-Refresh Mode ............................................................. 4-99 Single-Ended Data Strobe ............................................... 4-101 On Die Termination (ODT) ........................................... 4-101 Additive Latency ............................................................. 4-102

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Forcing DDR2 Commands ............................................. 4-102 Force Precharge All ..................................................... 4-102 Force Load Mode Register ........................................... 4-103 Force Auto-Refresh ..................................................... 4-103 Force Extended Mode Register 13 ............................. 4-103 Force DLL External Bank Calibration ......................... 4-103 Shared Memory Interface (ADSP-2146x) .................................. 4-104 Features .............................................................................. 4-104 Pin Descriptions ................................................................. 4-104 Functional Description ....................................................... 4-105 Bus Transition Cycle ....................................................... 4-106 DDR2 Bus Mastership Transfer ...................................... 4-109 Bus Synchronization After Reset ..................................... 4-110 Operating Modes ................................................................ 4-112 Bus Mastership Time-Out ............................................... 4-112 Bus Lock ........................................................................ 4-113 Data Transfer ........................................................................... 4-115 Data Buffers ....................................................................... 4-115 Receive Buffer Unpacking ............................................... 4-115 Transmit Buffer Unpacking ............................................. 4-115 External Port DMA Buffer .............................................. 4-116 Buffer Status ............................................................... 4-116 Flush Buffer ............................................................... 4-116 Core Access ......................................................................... 4-116

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External Port Dual Data Fetch ......................................... 4-117 Conditional Instructions ................................................. 4-117 SIMD Access ....................................................................... 4-117 SDRAM ......................................................................... 4-118 DDR2 ............................................................................ 4-118 External Port DMA ................................................................... 4-120 Features ............................................................................... 4-120 DMA Parameter Registers .................................................... 4-120 Functional Description ........................................................ 4-122 DMA Addressing ............................................................ 4-122 Operating Modes ................................................................. 4-122 Standard DMA ............................................................... 4-124 Circular Buffered DMA .................................................. 4-124 Chained DMA Mode ...................................................... 4-126 Data Direction on the Fly ........................................... 4-126 Write Back Circular Index Pointer ................................... 4-127 Scatter/Gather DMA ....................................................... 4-128 Pre Modified Read/Write Index ................................... 4-129 Delay Line DMA ............................................................ 4-133 Pre-Modified Read Index ............................................. 4-136 External Port DMA Group Priority ................................. 4-137 Interrupts ................................................................................. 4-138 Sources ................................................................................ 4-138 Delay Line DMA ............................................................ 4-138

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Scatter Gather DMA ...................................................... 4-138 Internal Transfer Completion .......................................... 4-138 Access Completion ......................................................... 4-139 Chained DMA ............................................................... 4-139 Masking .............................................................................. 4-140 Service ................................................................................ 4-140 Interrupt Dependency on DMA Mode ................................ 4-140 External Port Throughput ......................................................... 4-141 Data Throughput ................................................................ 4-141 DMA Throughput .......................................................... 4-142 Core Throughput ........................................................... 4-143 DDR2 Read Optimization .............................................. 4-144 Throughput Conditional Instructions ............................. 4-148 External Instruction Fetch Throughput ............................... 4-148 SDRAM Throughput ..................................................... 4-148 DDR2 Throughput ........................................................ 4-149 AMI Throughput ........................................................... 4-149 Effect Latency .......................................................................... 4-149 Programming Models ............................................................... 4-150 AMI Initialization ............................................................... 4-150 AMI Instruction Fetch .................................................... 4-151 SDRAM Controller ............................................................. 4-151 Power-Up Sequence ........................................................ 4-151 Changing the SDRAM Clock on the Fly ......................... 4-152

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SDRAM Instruction Fetch .............................................. 4-153 Output Clock Generator Programming Model ................. 4-153 Self-Refresh Mode ........................................................... 4-154 Changing the VCO Clock During Runtime ..................... 4-154 DDR2 Controller ................................................................ 4-156 Power-Up Sequence ........................................................ 4-156 Changing the DDR2 Clock on the Fly ............................ 4-158 Changing the Clock Frequency During Precharge Power Down Mode ............................................................. 4-158 Changing the Clock Frequency During Self-Refresh Mode ....................................................................... 4-159 External Port DMA ............................................................. 4-160 Standard DMA .............................................................. 4-160 Chained DMA ................................................................ 4-161 Delay Line DMA ............................................................ 4-162 Disabling and Re-enabling DMA ..................................... 4-162 Additional Information ................................................... 4-163 External Instruction Fetch ................................................... 4-164 AMI Configuration ......................................................... 4-164 SDRAM Configuration ................................................... 4-164 DDR2 Instruction Fetch ................................................. 4-165 External Memory Access Restrictions ................................... 4-165 Debug Features ......................................................................... 4-166 Core FIFO Write ................................................................. 4-166

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LINK PORTS ADSP-2146X

Features ........................................................................................ 5-2 Pin Descriptions ........................................................................... 5-3 Register Overview ......................................................................... 5-3 Clocking ...................................................................................... 5-4 Functional Description ................................................................. 5-4 Architecture ............................................................................ 5-4 Protocol .................................................................................. 5-5 Intercommunication ............................................................... 5-7 Self-Synchronization ............................................................... 5-9 Multi-Master Conflicts ............................................................ 5-9 Operating Modes ........................................................................ 5-10 Receive Link Service Request Mode ....................................... 5-10 Transmit Link Service Request Mode ..................................... 5-10 Example Token Passing ......................................................... 5-10 Data Transfer ............................................................................. 5-13 Packing Registers .................................................................. 5-13 Output Register ................................................................ 5-13 Input Register .................................................................. 5-13 Buffers .................................................................................. 5-14 Transmit Buffer ................................................................ 5-14 Receive Buffer .................................................................. 5-14 Buffer Status ..................................................................... 5-15 Buffer Reception Error ..................................................... 5-15

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Flushing Buffers ................................................................ 5-15 Buffer Hand Disable ......................................................... 5-15 Core Transfers ....................................................................... 5-15 DMA Transfers ...................................................................... 5-16 Link Port DMA Group Priority ............................................. 5-16 Interrupts ................................................................................... 5-17 Sources .................................................................................. 5-17 Core Buffer Service Request .............................................. 5-18 DMA Complete ................................................................ 5-18 Internal Transfer Complete ................................................ 5-18 Access Complete ............................................................... 5-18 Link Service Request ......................................................... 5-18 Chained DMA .................................................................. 5-19 Protocol Error ................................................................... 5-19 Masking ................................................................................ 5-19 Service .................................................................................. 5-19 Effect Latency ............................................................................. 5-20 Write Effect Latency .............................................................. 5-20 Link Port Effect Latency ........................................................ 5-20 Programming Model ................................................................... 5-20 Changing the Link Port Clock ............................................... 5-20 Receive DMA ........................................................................ 5-21 Transmit DMA ...................................................................... 5-22 Debug Features ........................................................................... 5-22

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Shadow Register .................................................................... 5-23 Buffer Hang Disable (BHD) .................................................. 5-23

MEMORY-TO-MEMORY PORT DMA

Features ........................................................................................ 6-2 Register Overview ......................................................................... 6-2 Clocking ...................................................................................... 6-2 Functional Description ................................................................. 6-3 Data Transfer Types ...................................................................... 6-3 Buffer ..................................................................................... 6-3 Buffer Status ....................................................................... 6-4 Flushing the Buffer ............................................................. 6-4 DMA Transfer ........................................................................ 6-4 Interrupts ..................................................................................... 6-4 Sources ................................................................................... 6-5 DMA Complete ................................................................. 6-5 Masking .................................................................................. 6-5 Service .................................................................................... 6-6 MTM Throughput ....................................................................... 6-6 Effect Latency .............................................................................. 6-6 Write Effect Latency ............................................................... 6-6 MTM Effect Latency .............................................................. 6-6 Programming Model ..................................................................... 6-7

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FFT/FIR/IIR HARDWARE MODULES

FFT Accelerator ............................................................................ 7-3 Features ................................................................................... 7-4 Register Descriptions ............................................................... 7-4 Clocking ................................................................................. 7-5 Functional Description ............................................................ 7-5 Compute Block ................................................................... 7-5 Data Memory ..................................................................... 7-6 Coefficient Memory ............................................................ 7-6 Accelerator States ................................................................ 7-6 Reset State ...................................................................... 7-6 Idle State ........................................................................ 7-7 Read State ....................................................................... 7-7 Processing State ............................................................... 7-7 Write State ...................................................................... 7-7 Internal Memory Storage ..................................................... 7-8 Small FFT N<=256 ........................................................ 7-8 Large FFT N>256 ........................................................... 7-9 Operating Modes ................................................................... 7-10 Small FFT Computation (<= 256 Points) ........................... 7-10 Large FFT Computation (> 256 Points) ............................. 7-11 Example for FFT Size N=512 ............................................ 7-11 Vertical FFT ................................................................. 7-11 Special ProductNumber of Iterations is N/128 = 4 ..... 7-12

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Horizontal FFT ............................................................ 7-13 No Repeat Mode .............................................................. 7-13 Repeat Mode .................................................................... 7-13 Unpacked Data Mode ....................................................... 7-14 Inverse FFT ...................................................................... 7-14 Data Transfer ........................................................................ 7-14 FFT Buffers ...................................................................... 7-15 Buffer Status ................................................................. 7-15 Flushing the Buffer ....................................................... 7-15 DMA Transfers ................................................................. 7-15 DMA Channels and TCB Structure .............................. 7-15 Chained DMA .............................................................. 7-16 Interrupts ............................................................................. 7-17 Sources ............................................................................. 7-18 DMA Complete ............................................................ 7-18 MAC Status ................................................................. 7-18 Chained DMA ............................................................. 7-18 Masking ........................................................................... 7-18 Service ............................................................................. 7-19 FFT Performance .................................................................. 7-19 Small FFT (N is <= 256) ................................................... 7-19 Large FFT (N >= 256) ...................................................... 7-20 Vertical FFT Cycles .............................................................. 7-20 Special Prod Cycles ............................................................... 7-20

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Horizontal FFT Cycles .......................................................... 7-20 Effect Latency ....................................................................... 7-20 Write Effect Latency ......................................................... 7-21 FFT Accelerator Effect Latency ......................................... 7-21 Programming Model .............................................................. 7-21 N <= 256, No Repeat ........................................................ 7-21 N <= 256, Repeat .............................................................. 7-22 N >= 512, No Repeat ........................................................ 7-24 Configure the FFT Control Register .............................. 7-24 Vertical FFT Configuration ........................................... 7-24 Special Buffer Configuration ......................................... 7-25 Horizontal FFT Configuration ...................................... 7-25 N >= 512, Repeat ............................................................. 7-26 Using Debug Mode ........................................................... 7-27 Write to Local Memory ................................................. 7-27 Read from Local Memory .............................................. 7-27 Debug Features ..................................................................... 7-28 Local Memory Access ........................................................ 7-28 Shadow Register ................................................................ 7-28 FIR Accelerator ........................................................................... 7-28 Features ................................................................................. 7-29 Register Overview ................................................................. 7-29 Clocking ............................................................................... 7-30 Functional Description .......................................................... 7-30

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Compute Block ................................................................ 7-32 Partial Sum Register .......................................................... 7-32 Delay Line Memory .......................................................... 7-32 Coefficient Memory ......................................................... 7-33 Pre Fetch Data Buffer ....................................................... 7-33 Processing Output ............................................................ 7-34 Internal Memory Storage .................................................. 7-36 Coefficients and Input Buffer Storage ............................ 7-36 Operating Modes .................................................................. 7-37 Single Rate Processing ...................................................... 7-37 Single Iteration ............................................................. 7-38 Multi Iteration .............................................................. 7-38 Window Processing ......................................................... 7-38 Multi Rate Processing ...................................................... 7-39 Decimation ...................................................................... 7-39 Interpolation .................................................................... 7-40 Channel Processing ........................................................... 7-41 Floating-Point Data Format .............................................. 7-41 Fixed-Point Data Format .................................................. 7-43 Data Transfer ........................................................................ 7-43 DMA Access ..................................................................... 7-43 Chain Pointer DMA ..................................................... 7-43 Interrupts ............................................................................. 7-45 Sources ............................................................................ 7-45

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Window Complete ........................................................ 7-46 All Channels Complete ................................................. 7-46 Chained DMA ............................................................. 7-46 MAC Status ................................................................. 7-46 Masking ............................................................................ 7-47 Service .............................................................................. 7-47 Effect Latency ....................................................................... 7-48 Write Effect Latency ......................................................... 7-48 FIR Accelerator Effect Latency .......................................... 7-48 FIR Throughput .................................................................... 7-49 Programming Model .............................................................. 7-49 Single Channel Processing ................................................. 7-50 Multichannel Processing .................................................... 7-51 Dynamic Coefficient Processing Notes ............................... 7-52 Debug Mode ..................................................................... 7-53 Write to Local Memory ................................................. 7-53 Read from Local Memory .............................................. 7-53 Single Step Mode .............................................................. 7-54 FIR Programming Example ............................................... 7-54 Computing FIR Output, Tap Length > Than 4096 ............ 7-56 Debug Features ..................................................................... 7-58 Local Memory Access ........................................................ 7-58 Single Step Mode .............................................................. 7-59 Emulation Considerations ................................................. 7-59

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IIR Accelerator ........................................................................... 7-59 Features ................................................................................ 7-59 Register Overview ................................................................. 7-60 Clocking ............................................................................... 7-60 Functional Description ......................................................... 7-61 Multiply and Accumulate (MAC) Unit .............................. 7-63 Input Data and Biquad State ............................................. 7-64 Coefficient Memory ......................................................... 7-64 Internal Memory Storage .................................................. 7-64 Coefficient Memory Storage ......................................... 7-64 Operating Modes .................................................................. 7-65 Window Processing .......................................................... 7-65 40-Bit Floating-Point Mode .............................................. 7-65 Save Biquad State Mode .................................................... 7-66 Data Transfers ....................................................................... 7-66 DMA Access ..................................................................... 7-67 Chain Pointer DMA ..................................................... 7-67 Interrupts ............................................................................. 7-68 Sources ............................................................................ 7-69 Window Complete ....................................................... 7-69 All Channels Complete ................................................. 7-69 Chained DMA ............................................................. 7-69 MAC Status ................................................................. 7-69 Masking ........................................................................... 7-70

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Service .............................................................................. 7-70 Effect Latency ....................................................................... 7-71 Write Effect Latency ......................................................... 7-71 IIR Accelerator Effect Latency ........................................... 7-71 IIR Throughput .................................................................... 7-72 Programming Model .............................................................. 7-72 Dynamic Coefficient Processing Notes ............................... 7-74 Writing to Local Memory .................................................. 7-74 Reading from Local Memory ............................................. 7-75 Single Step Mode .............................................................. 7-76 Save Biquad State of the IIR .............................................. 7-76 Programming Example ...................................................... 7-77 Throughput Comparison Accelerator Versus Core ............... 7-78 FFT .................................................................................. 7-79 FIR ................................................................................... 7-79 IIR ................................................................................... 7-81 Debug Features ..................................................................... 7-83 Local Memory Access ........................................................ 7-83 Single Step Mode .............................................................. 7-84 Emulation Considerations ................................................. 7-84 Application Guidelines for Effective Use of the FIR/IIR/FFT Accelerators .............................................................................. 7-85 Sample Versus Block Processing Operation ............................. 7-85 Adding Pipeline Stages ........................................................... 7-86 Splitting Tasks ....................................................................... 7-86 ADSP-214xx SHARC Processor Hardware Reference xxvii

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PULSE WIDTH MODULATION

Features ........................................................................................ 8-2 Pin Descriptions ........................................................................... 8-4 Multiplexing Scheme .............................................................. 8-4 SRU Programming ....................................................................... 8-5 Register Overview ......................................................................... 8-5 Clocking ...................................................................................... 8-6 Functional Description ................................................................. 8-6 Two-Phase PWM Generator .................................................... 8-6 Switching Frequencies ......................................................... 8-6 Duty Cycles ........................................................................ 8-7 Dead Time ....................................................................... 8-12 Output Control Unit ............................................................ 8-13 Output Enable ................................................................. 8-13 Output Polarity ................................................................ 8-13 Complementary Outputs .................................................. 8-14 Crossover ......................................................................... 8-14 Emergency Dead Time for Over Modulation ......................... 8-15 Output Control Feature Precedence .................................. 8-16 Operation Modes ....................................................................... 8-17 Waveform Modes .................................................................. 8-17 Edge-Aligned Mode .......................................................... 8-18 Center-Aligned Mode ....................................................... 8-19 PWM Timer Edge Aligned Update ........................................ 8-21

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Single Update Mode .......................................................... 8-22 Double Update Mode ....................................................... 8-22 Effective Accuracy ................................................................. 8-23 Synchronization of PWM Groups ........................................... 8-24 Interrupts ................................................................................... 8-24 Sources .................................................................................. 8-25 PWM Period ..................................................................... 8-25 Masking ................................................................................ 8-25 Service .................................................................................. 8-25 Effect Latency ............................................................................. 8-27 Write Effect Latency .............................................................. 8-27 PWM Effect Latency ............................................................. 8-27 Debug Features ........................................................................... 8-27 Status Debug Register ............................................................ 8-27 Emulation Considerations ..................................................... 8-27

MEDIA LOCAL BUS

Features ........................................................................................ 9-3 Pin Descriptions ........................................................................... 9-4 Register Overview ......................................................................... 9-4 Device Configuration and Status Registers ............................... 9-4 Channel Registers .................................................................... 9-5 Clocking ....................................................................................... 9-5 Functional Description ................................................................. 9-6 Media LB Protocol .................................................................. 9-7

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Operating Modes .......................................................................... 9-8 Logical Channel Control ......................................................... 9-8 Synchronous Channels ............................................................ 9-9 Asynchronous Channels ........................................................ 9-10 Control Channels ................................................................. 9-10 Data Transfer ............................................................................. 9-11 Core Access ........................................................................... 9-11 Threshold Depth .............................................................. 9-11 Status ........................................................................... 9-13 Flushing the Buffer ....................................................... 9-13 DMA .................................................................................... 9-13 MLB DMA Group Priority ................................................... 9-14 Ping-Pong DMA ............................................................... 9-15 Circular Buffer DMA ....................................................... 9-16 Interrupts ................................................................................... 9-18 Sources ................................................................................. 9-18 Core Buffer Service Request .............................................. 9-18 Threshold Transmit Request ............................................. 9-19 Threshold Receive Request ............................................... 9-19 DMA Complete ............................................................... 9-19 Receive Channel Errors ..................................................... 9-19 Masking ................................................................................ 9-19 Service .................................................................................. 9-20 Programming Model ................................................................... 9-20

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I/O Interrupt Mode ............................................................... 9-20 DMA Modes ......................................................................... 9-21 Debug Features ........................................................................... 9-23 Loop-Back Test Mode ............................................................ 9-23

DIGITAL APPLICATION/ DIGITAL PERIPHERAL INTERFACES

SRU Features .............................................................................. 10-2 Register Overview ....................................................................... 10-3 Clocking ..................................................................................... 10-4 Functional Description ............................................................... 10-5 DAI/DPI Signal Naming Conventions ................................... 10-8 I/O Pin Buffers ..................................................................... 10-9 Pin Buffer Signals ............................................................. 10-9 Pin Buffer Input Signal ................................................. 10-9 Pin Buffer Enable Signal .............................................. 10-10 Pin Buffer Functions ....................................................... 10-10 Pin Buffers as Signal Input .......................................... 10-11 Pin Buffers As Signal Output ....................................... 10-11 Pin Buffers as Open Drain ........................................... 10-13 DAI/DPI Pin Buffer Status .......................................... 10-13 DAI/DPI Peripherals ........................................................... 10-14 Output Signals With Pin Buffer Enable Control .............. 10-14 Output Signals Without Pin Buffer Enable Control ......... 10-15 Signal Routing Units (SRUs) ............................................... 10-15

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Signal Routing Matrix by Groups .................................... 10-16 DAI/DPI Group Routing ................................................ 10-17 Rules for SRU Connections ............................................ 10-19 Miscellaneous Buffers and Functions ................................... 10-19 DAI/DPI Routing Capabilities ............................................ 10-22 DAI Routing Capabilities ................................................ 10-22 DPI Routing Capabilities ................................................ 10-24 DAI Default Routing .......................................................... 10-24 DPI Default Routing .......................................................... 10-27 Unused DAI/DPI Connections ............................................ 10-28 Operating Modes ...................................................................... 10-28 DAI Pin Buffer Polarity ....................................................... 10-29 DAI Miscellaneous Buffer Polarity ....................................... 10-29 Interrupts ................................................................................. 10-30 DAI/DPI Miscellaneous Interrupts ....................................... 10-30 Sources ........................................................................... 10-31 Edge Detection ........................................................... 10-31 Masking ......................................................................... 10-31 Service ........................................................................... 10-32 Effect Latency .......................................................................... 10-32 Write Effect Latency ........................................................... 10-32 Signal Routing Unit Effect Latency ...................................... 10-32 Programming Model ................................................................. 10-32 Making SRU Connections ................................................... 10-34

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DAI Example System ........................................................... 10-38 Debug Features ......................................................................... 10-39 Shadow Interrupt Registers .................................................. 10-39 Loopback Routing ............................................................... 10-39

SERIAL PORTS (SPORTS)

Features ...................................................................................... 11-2 Serial Port Versus Input Data Port Features ............................ 11-4 Pin Descriptions ......................................................................... 11-5 SRU Programming ...................................................................... 11-6 SRU SPORT Receive Master ................................................. 11-7 SRU SPORT Signal Integrity ................................................. 11-7 Register Overview ....................................................................... 11-8 Clocking ..................................................................................... 11-9 Master Clock ....................................................................... 11-10 Master Frame Sync .............................................................. 11-10 General-Purpose Pulse Generator ......................................... 11-11 Slave Mode .......................................................................... 11-11 Mixed Mode ........................................................................ 11-12 Maximum Clock Rate Restrictions ....................................... 11-12 Clock Power Savings ............................................................ 11-12 Functional Description ............................................................. 11-13 Architecture ........................................................................ 11-13 Companding ................................................................... 11-14 Frame Sync and Data Sampling ........................................... 11-16

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Continuous Framed Data Transfers ................................. 11-17 SPORT Protocols ................................................................ 11-17 Standard Serial Protocol .................................................. 11-17 Protocol Configuration Options .................................. 11-17 Left-Justified Protocol ..................................................... 11-18 Protocol Configuration Options .................................. 11-18 I2S Protocol .................................................................... 11-19 Protocol Configuration Options .................................. 11-19 I2S Compatibility ....................................................... 11-19 Channel Order First .................................................... 11-20 Multichannel Protocol .................................................... 11-20 Protocol Configuration Options .................................. 11-21 Multiple Channels ...................................................... 11-21 Multichannel Frame Sync Delay .................................. 11-22 Number of Channels (NCH) ...................................... 11-23 Active Channel Selection Registers .............................. 11-23 Active Channel Companding Selection Registers ......... 11-24 Companding Limitations (ADSP-2146x) .................... 11-25 Transmit Data Valid Output Enable ............................ 11-25 Multichannel Protocol Backward Compatibility ........... 11-26 Packed Protocol .............................................................. 11-26 Protocol Configuration Options .................................. 11-27 Packed Words ............................................................. 11-27 Operating Modes ...................................................................... 11-28

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Mode Selection .................................................................... 11-32 Data Direction ................................................................ 11-32 Serial Word Length ......................................................... 11-32 Data Types Format .......................................................... 11-33 Sampling Edge ................................................................ 11-33 Frame Sync Modes .............................................................. 11-34 Framed Versus Unframed Frame Syncs ............................. 11-34 Early Versus Late Frame Syncs ......................................... 11-35 Internal Versus External Frame Syncs................................ 11-36 Polarity Frame Sync Level ................................................ 11-37 Frame Sync Generation ................................................... 11-37 Data-Independent Frame Sync ..................................... 11-37 Channel Dependency .................................................. 11-38 Frame Sync Error Detection ............................................ 11-39 Internal Frame Sync Errors .......................................... 11-39 External Frame Sync Errors ......................................... 11-39 Data Transfers ........................................................................... 11-40 Serial Shift Registers ............................................................ 11-41 Output Shift Register ...................................................... 11-41 Input Shift Register ......................................................... 11-41 Buffers ................................................................................ 11-41 Transmit Buffers ............................................................. 11-42 Receive Buffers ............................................................... 11-42 Buffer Packing ................................................................ 11-43

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Companding .............................................................. 11-43 Buffer Status .................................................................. 11-44 Buffer Errors .................................................................. 11-44 Reception Error .......................................................... 11-45 Transmission Error ..................................................... 11-45 Flushing Buffers ............................................................. 11-45 Core Transfers ..................................................................... 11-45 DMA Transfers ................................................................... 11-46 SPORT DMA Group Priority ......................................... 11-47 Standard DMA ............................................................... 11-48 DMA Chaining .............................................................. 11-49 DMA Chain Insertion Mode ........................................... 11-50 SPORT DMA to External Memory ................................. 11-50 SPORT SPEP Bus Priority .......................................... 11-51 Interrupts ................................................................................. 11-51 Sources ............................................................................... 11-52 Core Buffer Service Request ............................................ 11-52 Data Buffer Packing ........................................................ 11-52 DMA Complete ............................................................. 11-52 Internal Transfer Complete ............................................. 11-53 Access Complete ............................................................. 11-53 Chained DMA ............................................................... 11-53 Buffer Over/Underflow .................................................. 11-54 Unexpected Frame Sync Errors ........................................ 11-54

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Masking .............................................................................. 11-54 Service ................................................................................ 11-55 Throughput .............................................................................. 11-56 Effect Latency ..................................................................... 11-56 Write Effect Latency ....................................................... 11-57 SPORT Effect Latency .................................................... 11-57 Programming Model ................................................................. 11-57 Setting Up and Starting DMA Master Mode ........................ 11-57 Setting Up and Starting Chained DMA ................................ 11-58 Enter DMA Chain Insertion Mode ...................................... 11-58 Setting Up and Starting Multichannel Mode ........................ 11-59 Multichannel Mode Backward Compatibility ................... 11-60 Programming Packed Mode ................................................. 11-61 External Frame Sync Operation ........................................... 11-62 Companding As a Function ................................................. 11-62 Debug Features ......................................................................... 11-63 SPORT Loopback ............................................................... 11-64 LoopBack Routing .......................................................... 11-64 Buffer Hang Disable (BHD) ................................................ 11-64

INPUT DATA PORT (SIP, PDAP)

Features ...................................................................................... 12-2 Pin Descriptions ......................................................................... 12-3 SRU Programming ...................................................................... 12-4 Register Overview ....................................................................... 12-5

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Clocking .................................................................................... 12-5 Functional Description ............................................................... 12-6 Operating Modes ........................................................................ 12-7 PDAP Port Selection ............................................................. 12-8 Data Hold ............................................................................ 12-9 PDAP Data Masking ........................................................... 12-10 PDAP Data Packing ............................................................ 12-10 No Packing ..................................................................... 12-10 Packing by 2 ................................................................... 12-11 Packing by 3 ................................................................... 12-12 Packing by 4 ................................................................... 12-13 Data Transfer ........................................................................... 12-14 Buffers ................................................................................ 12-14 Buffer Threshold Depth .................................................. 12-14 Buffer Status ................................................................... 12-15 Buffer Error Status .......................................................... 12-15 Flushing the Buffer ......................................................... 12-15 Buffer Hang Disable ....................................................... 12-15 Core Transfers ..................................................................... 12-16 SIP Data Buffer Format .................................................. 12-16 PDAP Data Buffer Format .............................................. 12-19 DMA Transfers ................................................................... 12-19 Data Buffer Format for DMA ......................................... 12-20 IDP DMA Group Priority ............................................... 12-20

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Standard DMA ............................................................... 12-20 Ping-Pong DMA ............................................................. 12-21 Multichannel DMA Operation ........................................ 12-22 Multichannel FIFO Status ............................................... 12-23 Interrupts ................................................................................. 12-24 Sources ................................................................................ 12-24 Core Buffer Service Request ............................................ 12-24 Interrupt Acknowledge .................................................... 12-24 Buffer Threshold ............................................................. 12-25 DMA Complete .............................................................. 12-25 Buffer Overflow .............................................................. 12-25 Masking .............................................................................. 12-26 Service ................................................................................ 12-26 Effect Latency ........................................................................... 12-26 Write Effect Latency ............................................................ 12-27 IDP Effect Latency .............................................................. 12-27 Programming Model ................................................................. 12-27 Setting Miscellaneous Bits ................................................... 12-27 Starting Core Interrupt-Driven Transfer ............................... 12-28 Additional Notes ............................................................. 12-29 Starting A Standard DMA Transfer ...................................... 12-30 Starting a Ping-Pong DMA Transfer ..................................... 12-31 Servicing Interrupts for DMA .............................................. 12-31 Debug Features ......................................................................... 12-33

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Status Register Debug ......................................................... 12-33 Buffer Hang Disable ........................................................... 12-33 Shadow Interrupt Registers .................................................. 12-34 Core FIFO Write ................................................................ 12-34

ASYNCHRONOUS SAMPLE RATE CONVERTER

Features ...................................................................................... 13-2 Pin Descriptions ......................................................................... 13-3 SRU Programming ..................................................................... 13-4 Register Overview ....................................................................... 13-4 Clocking .................................................................................... 13-5 Functional Description ............................................................... 13-5 I/O Ports .............................................................................. 13-5 De-Emphasis Filter ............................................................... 13-6 Mute Control ....................................................................... 13-7 SRC Core ............................................................................. 13-7 RAM FIFO ...................................................................... 13-8 Digital Servo Loop ........................................................... 13-8 FIR Filter ......................................................................... 13-9 Sample Rate Sensing ......................................................... 13-9 Digital Filter Group Delay .............................................. 13-10 Data Format ....................................................................... 13-10 Operating Modes ...................................................................... 13-11 TDM Input Mode .............................................................. 13-11 TDM Output Mode ........................................................... 13-12

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Matched-Phase Mode (ADSP-21488) .................................. 13-13 Bypass Mode ....................................................................... 13-14 De-Emphasis Mode ............................................................. 13-15 Dithering Mode .................................................................. 13-15 Muting Modes ..................................................................... 13-15 Soft Mute ....................................................................... 13-16 Hard Mute ...................................................................... 13-16 Auto Mute ...................................................................... 13-16 Interrupts ................................................................................. 13-17 Sources ................................................................................ 13-17 SRC Mute Out ............................................................... 13-17 Masking .............................................................................. 13-17 Service ................................................................................ 13-18 Effect Latency ........................................................................... 13-18 Write Effect Latency ............................................................ 13-18 ASRC Effect Latency ........................................................... 13-18 Programming Model ................................................................. 13-19 Debug Features ......................................................................... 13-19 Shadow Interrupt Registers .................................................. 13-19

SONY/PHILIPS DIGITAL INTERFACE

Features ...................................................................................... 14-2 Pin Descriptions ......................................................................... 14-3 SRU Programming ...................................................................... 14-4 Register Overview ....................................................................... 14-6

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Clocking .................................................................................... 14-6 S/PDIF Transmitter .................................................................... 14-7 Functional Description ......................................................... 14-7 Input Data Formats .......................................................... 14-9 Operating Modes ................................................................ 14-11 Full Serial Mode ............................................................. 14-11 Standalone Mode ............................................................ 14-11 Data Output Mode ......................................................... 14-12 S/PDIF Receiver ....................................................................... 14-13 Functional Description ....................................................... 14-13 Clock Recovery .............................................................. 14-15 Output Data Format ...................................................... 14-15 Channel Status ............................................................... 14-16 Operating Modes ................................................................ 14-16 Compressed or Non-linear Audio Data ............................ 14-16 Emphasized Audio Data .............................................. 14-17 Single-Channel Double-Frequency Mode .................... 14-18 Clock Recovery Modes ................................................... 14-18 Digital On-Chip PLL ................................................. 14-18 Interrupts ................................................................................. 14-19 Sources ............................................................................... 14-19 Transmit Block Start ....................................................... 14-19 Receiver Status ............................................................... 14-20 Receiver Error ................................................................ 14-20

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Masking .............................................................................. 14-20 Service ................................................................................ 14-21 Effect Latency ........................................................................... 14-21 Write Effect Latency ............................................................ 14-21 Programming Model ................................................................. 14-21 Programming the Transmitter .............................................. 14-22 Programming the Receiver ................................................... 14-22 Interrupted Data Streams on the Receiver ............................ 14-23 Debug Features ......................................................................... 14-25 Loopback Routing ............................................................... 14-25 Shadow Interrupt Registers .................................................. 14-25

PRECISION CLOCK GENERATOR

Features ...................................................................................... 15-2 Pin Descriptions ......................................................................... 15-3 SRU Programming ...................................................................... 15-4 Register Overview ....................................................................... 15-5 Clocking ..................................................................................... 15-5 Functional Description ............................................................... 15-6 Serial Clock ........................................................................... 15-6 Frame Sync ........................................................................... 15-7 Frame Sync Output ........................................................... 15-7 Divider Mode Selection ..................................................... 15-8 Phase Shift ........................................................................ 15-8 Pulse Width .................................................................... 15-10

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Default Pulse Width ....................................................... 15-11 Input Clock Source Considerations ................................. 15-11 Timing Example for I2S Mode ........................................ 15-11 Operating Modes ...................................................................... 15-12 Normal Mode ..................................................................... 15-12 Bypass Mode ....................................................................... 15-13 One-Shot Mode .................................................................. 15-14 External Event Trigger ......................................................... 15-15 External Event Trigger Delay .......................................... 15-15 Audio System Example ........................................................ 15-16 Clock Configuration Examples ............................................ 15-18 Effect Latency .......................................................................... 15-19 Write Effect Latency ........................................................... 15-19 PCG Effect Latency ............................................................ 15-19 Programming Model ................................................................. 15-20 Frame Sync Phase Setting .................................................... 15-21 External Event Trigger ......................................................... 15-21 Debug Features ......................................................................... 15-22

SERIAL PERIPHERAL INTERFACE PORTS

Features ...................................................................................... 16-2 Pin Descriptions ......................................................................... 16-3 SRU Programming ..................................................................... 16-4 Register Overview ....................................................................... 16-5 Clocking .................................................................................... 16-6 xliv ADSP-214xx SHARC Processor Hardware Reference

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Choosing the Pin Enable for the SPI Clock ............................. 16-7 Functional Description ............................................................... 16-8 SPI Transaction ..................................................................... 16-9 Single Master Systems .......................................................... 16-10 Multi Master Systems .......................................................... 16-11 Operating Modes ...................................................................... 16-12 Transfer Initiate Mode ......................................................... 16-13 SPI Modes ........................................................................... 16-14 Slave Select Outputs ............................................................ 16-15 Variable Frame Delay for Slave ............................................. 16-17 Data Transfers ........................................................................... 16-18 Serial Shift Register ............................................................. 16-18 Output Shift Register ...................................................... 16-18 Input Shift Register ......................................................... 16-19 Buffers ................................................................................ 16-19 Transmit Buffer ............................................................... 16-19 Receive Buffer ................................................................. 16-20 Buffer Packing ............................................................ 16-20 Buffer Errors ................................................................... 16-21 Transmission Error ...................................................... 16-21 Reception Error .......................................................... 16-21 Transmit Collision Error ............................................. 16-21 Flush Buffer ................................................................ 16-22 Core Buffer Status ........................................................... 16-22

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DMA Buffer Status ......................................................... 16-23 Core Transfers ..................................................................... 16-24 Backward Compatibility ................................................. 16-24 DMA Transfers .................................................................... 16-24 DMA Chaining .............................................................. 16-27 DMA Transfer Count ..................................................... 16-27 Full Duplex Operation .................................................... 16-28 Interrupts ................................................................................. 16-28 Sources ............................................................................... 16-29 Core Buffer Service Request ............................................ 16-29 Data Buffer Packing ........................................................ 16-29 DMA Complete ............................................................. 16-29 Internal Transfer Complete ............................................. 16-29 Access Complete ............................................................. 16-30 Chained DMA ............................................................... 16-30 DMA Buffer Over/Underflow ..................................... 16-30 Multimaster Error ....................................................... 16-30 Masking .............................................................................. 16-30 Service ................................................................................ 16-31 Effect Latency .......................................................................... 16-32 Write Effect Latency ........................................................... 16-32 SPI Effect Latency ............................................................... 16-32 Programming Model ................................................................. 16-32 SPI Routing ........................................................................ 16-33

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Master Mode Transfers ........................................................ 16-33 Core Master Transfers ..................................................... 16-33 DMA Master Transfers .................................................... 16-34 Slave Mode Transfers ........................................................... 16-34 Core Slave Transfers ........................................................ 16-35 DMA Slave Transfers ....................................................... 16-35 Chained DMA Transfers ...................................................... 16-36 Stopping SPI Transfers ......................................................... 16-36 Changing SPI Timing Configuration ................................... 16-37 Switching From Transmit DMA to a New DMA .................. 16-37 Switching From Receive to a New DMA .............................. 16-39 Switching from Receive DMA to Receive DMA Without Disabling the SPI and DMA ............................... 16-41 DMA Error Interrupts ......................................................... 16-41 Multi-Master Transfers .................................................... 16-43 Debug Features ......................................................................... 16-43 Shadow Receive Buffers ....................................................... 16-43 Internal Loopback Mode ..................................................... 16-44 Loopback Routing .......................................................... 16-44

PERIPHERAL TIMERS
Features ...................................................................................... 17-2 Pin Descriptions ......................................................................... 17-3 SRU Programming ...................................................................... 17-3 Register Overview ....................................................................... 17-4

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Read-Modify-Write ............................................................... 17-5 Clocking .................................................................................... 17-5 Functional Description ............................................................... 17-5 Operating Modes ........................................................................ 17-7 Pulse Width Modulation Mode (PWM_OUT) ...................... 17-8 PWM Waveform Generation .......................................... 17-10 Single-Pulse Generation .................................................. 17-11 Pulse Mode .................................................................... 17-12 Pulse Width Count and Capture Mode (WDTH_CAP) ....... 17-12 External Event Watchdog Mode (EXT_CLK) ...................... 17-15 Interrupts ................................................................................. 17-17 Sources ............................................................................... 17-17 PWM_OUT Mode ......................................................... 17-18 WDTH_CAP Mode ....................................................... 17-18 EXT_CLK Mode ............................................................ 17-18 PWM_OUT Mode ......................................................... 17-18 WDTH_CAP Mode ....................................................... 17-18 Masking .............................................................................. 17-18 Service ................................................................................ 17-19 Effect Latency .......................................................................... 17-20 Write Effect Latency ........................................................... 17-20 Timers Effect Latency ......................................................... 17-20 Programming Model ................................................................. 17-21 PWM Out Mode ................................................................ 17-22

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WDTH_CAP Mode ............................................................ 17-23 EXT_CLK Mode ................................................................. 17-24 Debug Features ......................................................................... 17-25 Loopback Routing ............................................................... 17-25

SHIFT REGISTER ADSP-2147X

Features ...................................................................................... 18-2 Pin Descriptions ......................................................................... 18-3 SRU Programming ...................................................................... 18-3 Register Overview ....................................................................... 18-4 Clocking ..................................................................................... 18-4 Functional Description ............................................................... 18-4 Operating Modes ........................................................................ 18-6 Serial Data Output ................................................................ 18-6 Parallel Data Output ............................................................. 18-7 Effect Latency ............................................................................. 18-7 Write Effect Latency .............................................................. 18-7 Shift Register Effect Latency .................................................. 18-7 Programming Model ................................................................... 18-7

REAL-TIME CLOCK ADSP-2147X/ADSP-2148X

Features ................................................................................. 19-2 Pin Descriptions ......................................................................... 19-3 Clocking ..................................................................................... 19-3 Register Overview ....................................................................... 19-3

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Functional Description ............................................................... 19-4 Interrupts ................................................................................. 19-13

WATCHDOG TIMER ADSP-2147X, ADSP-2148X

Features ...................................................................................... 20-2 Pin Descriptions ......................................................................... 20-3 Register Overview ....................................................................... 20-3 Clocking .................................................................................... 20-4 Functional Description ............................................................... 20-5 Operating Mode ......................................................................... 20-6 Trip Count ........................................................................... 20-6 Effect Latency ............................................................................ 20-7 Write Effect Latency ............................................................. 20-7 Watchdog Timers Effect Latency ........................................... 20-7 Programming Model ................................................................... 20-7 Debug Features ........................................................................... 20-9 Emulation Considerations ..................................................... 20-9

UART PORT CONTROLLER

Features ...................................................................................... 21-2 SRU Programming ..................................................................... 21-3 Register Overview ....................................................................... 21-3 Clocking .................................................................................... 21-4 Functional Description ............................................................... 21-5 Serial Communication .......................................................... 21-7

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Operating Modes ........................................................................ 21-8 Data Packing/Unpacking ....................................................... 21-8 Data Transfer Types .................................................................... 21-8 Serial Shift Registers .............................................................. 21-9 Output Shift Register ........................................................ 21-9 Input Shift Register ........................................................... 21-9 Buffers .................................................................................. 21-9 Transmit Buffer ................................................................. 21-9 Receive Buffer ................................................................. 21-10 Buffer Status ....................................................................... 21-10 Buffer Packing ..................................................................... 21-10 9-Bit Transmission Mode ..................................................... 21-11 Flushing the Buffer .............................................................. 21-13 Core Transfers ..................................................................... 21-13 DMA Transfers .................................................................... 21-14 UART DMA Group Priority ........................................... 21-15 DMA Chaining ............................................................... 21-15 Interrupts ................................................................................. 21-16 Sources ................................................................................ 21-16 Core Buffer Service Request ............................................ 21-17 Address Detection ........................................................... 21-17 DMA Complete .............................................................. 21-17 Chained DMA ................................................................ 21-17 Line Status Error ............................................................. 21-18

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Masking .............................................................................. 21-18 Service ................................................................................ 21-19 Core Buffer Service Request ............................................ 21-19 Errors ............................................................................. 21-20 Effect Latency .......................................................................... 21-20 Write Effect Latency ........................................................... 21-20 UART Effect Latency .......................................................... 21-20 Programming Model ................................................................. 21-21 Autobaud Detection ............................................................ 21-21 DMA Transfers ................................................................... 21-22 Setting Up and Starting Chained DMA ........................... 21-22 Notes on Using UART DMA .......................................... 21-23 Core Transfers ..................................................................... 21-23 9-Bit Transmission and Packing Transfers ........................ 21-24 Debug Features ......................................................................... 21-24 Shadow Registers ................................................................ 21-24 Shadow Buffer .................................................................... 21-25 Shadow Interrupt Registers .................................................. 21-25 Loopback Routing .............................................................. 21-25

TWO WIRE INTERFACE CONTROLLER

Features ...................................................................................... 22-2 Pin Descriptions ......................................................................... 22-3 SRU Programming ..................................................................... 22-4 Clocking .................................................................................... 22-4

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Register Overview ....................................................................... 22-5 Functional Description ............................................................... 22-6 Bus Arbitration ..................................................................... 22-9 Start and Stop Conditions ................................................... 22-10 Operating Modes ...................................................................... 22-11 General Call Addressing ...................................................... 22-11 Slave Mode Addressing ........................................................ 22-12 Master Mode Addressing ..................................................... 22-12 Fast Mode ........................................................................... 22-12 Data Transfer ............................................................................ 22-12 Serial Shift Register ............................................................. 22-13 Output Shift Register ...................................................... 22-13 Input Shift Register ......................................................... 22-13 Buffers ................................................................................ 22-13 8-Bit Transmit Buffer ...................................................... 22-13 16-Bit Transmit Buffer .................................................... 22-14 8-Bit Receive Buffer ........................................................ 22-15 16-Bit Receive Buffer ...................................................... 22-15 Buffer Status ....................................................................... 22-16 Buffer Error .................................................................... 22-16 Flushing the Buffer ......................................................... 22-16 Buffer Hang Disable ....................................................... 22-16 Interrupts ................................................................................. 22-17 Sources ................................................................................ 22-17

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Slave Status .................................................................... 22-17 Master Status .................................................................. 22-17 Error .............................................................................. 22-17 Masking .............................................................................. 22-18 Service ................................................................................ 22-18 Effect Latency .......................................................................... 22-19 Write Effect Latency ........................................................... 22-19 TWI Effect Latency ............................................................ 22-19 Programming Model ................................................................. 22-19 General Setup ..................................................................... 22-20 SRU Programming Mode .................................................... 22-20 Slave Mode ......................................................................... 22-21 Master Mode Clock Setup ................................................... 22-22 Master Mode Transmit ........................................................ 22-22 Master Mode Receive .......................................................... 22-24 Repeated Start Condition .................................................... 22-25 Transmit/Receive Repeated Start Sequence ...................... 22-25 Receive/Transmit Repeated Start Sequence ...................... 22-26 Electrical Specifications ............................................................ 22-27 Debug Features ......................................................................... 22-27 Buffer Hang Disable ........................................................... 22-27 Shadow Interrupt Registers .................................................. 22-28 Loopback Routing .............................................................. 22-28

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POWER MANAGEMENT
Features ...................................................................................... 23-1 Register Overview ....................................................................... 23-1 Phase-Locked Loop (PLL) ........................................................... 23-2 Functional Description .......................................................... 23-2 PLL Input Clock .................................................................. 23-3 Pre-Divider Input .................................................................. 23-3 PLL Multiplier ...................................................................... 23-4 PLLM Hardware Control .................................................. 23-4 PLLM Software Control .................................................... 23-4 PLL VCO ............................................................................. 23-5 Output Clock Generator ....................................................... 23-5 Core Clock (CCLK) .......................................................... 23-6 IOP Clock (PCLK) ........................................................... 23-6 Peripheral Clocks (SDRAM/DDR2/Link Port) .................. 23-6 Default PLL Hardware Settings .............................................. 23-6 Operating Modes ........................................................................ 23-7 Bypass Mode ......................................................................... 23-7 Normal Mode ........................................................................ 23-8 Clocking Golden Rules .......................................................... 23-8 Power-Up Sequence .................................................................... 23-8 PLL Start-Up ........................................................................ 23-9 Peripherals Enabled by Default ............................................ 23-10 SDRAM Controller ......................................................... 23-10

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DDR2 Controller ........................................................... 23-10 S/PDIF RX Controller .................................................... 23-11 Real-Time Clock Controller ............................................ 23-11 Disabling Peripheral Clocks ................................................. 23-11 Routing Units ..................................................................... 23-11 Packages Without an External Port .................................. 23-12 Example for Clock Management .......................................... 23-12 General Notes on Power Savings .......................................... 23-12 Programming Models ............................................................... 23-13 Post Divider ........................................................................ 23-13 Multiplier and Post Divider Programming Model.................. 23-14 Back to Back Bypass ............................................................ 23-17

SYSTEM DESIGN
Features ...................................................................................... 24-1 Thermal Diode ..................................................................... 24-2 Pin Descriptions ......................................................................... 24-2 Register Overview ....................................................................... 24-2 Processor Reset .......................................................................... 24-3 Hardware Reset ..................................................................... 24-3 Software Reset ...................................................................... 24-4 Running Reset ..................................................................... 24-4 System Considerations ...................................................... 24-5 External Host ............................................................... 24-7 Processor Booting ....................................................................... 24-7

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Boot Mechanisms .................................................................. 24-8 External Port Booting ............................................................ 24-8 SPI Port Booting ................................................................. 24-12 Master Boot Mode .......................................................... 24-12 Master Read Command ................................................... 24-14 Slave Boot Mode ............................................................. 24-15 SPI Boot Packing ............................................................ 24-16 32-Bit SPI Packing ...................................................... 24-18 16-Bit SPI Packing ...................................................... 24-19 8-Bit SPI Packing ........................................................ 24-20 Link Port Booting ............................................................... 24-21 Kernel Boot Time ................................................................ 24-23 ROM Booting ..................................................................... 24-24 Programming Model ................................................................. 24-24 Running Reset ..................................................................... 24-24 Running The Boot Kernel ................................................... 24-25 Loading the Boot Kernel Using DMA .............................. 24-25 Executing the Boot Kernel ............................................... 24-25 Loading the Application .................................................. 24-26 Loading the Applications Interrupt Vector Table .............. 24-26 Starting Program Execution ............................................. 24-27 Memory Aliasing in Internal Memory .................................. 24-27 Pin Multiplexing ....................................................................... 24-28 Core FLAG Pins Multiplexing .............................................. 24-28

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Backward Compatibility ................................................. 24-29 External Port Pin Multiplexing ............................................ 24-29 Backward Compatibility ................................................. 24-30 Multiplexed External Port Pins ........................................ 24-30 Parallel Connection of Flag Pins via External Port and DPI Pins ............................................... 24-31 Processor Identification Register ................................................ 24-34 High Frequency Design ............................................................ 24-34 Circuit Board Design .......................................................... 24-35 Clock Input Specifications and Jitter ............................... 24-35 RESETOUT .................................................................. 24-35 Input Pin Hysteresis ....................................................... 24-35 Clock and Control Signal Transitions .............................. 24-36 Pull-Up/Pull-Down Resistors .......................................... 24-36 Memory Select Pins ........................................................ 24-37 Edge-Triggered I/O ......................................................... 24-37 Asynchronous Inputs ...................................................... 24-37 Decoupling and Grounding ................................................. 24-38 Circuit Board Layout .......................................................... 24-38 ESD/EOS Protection Circuits ............................................. 24-39 Other Recommendations and Suggestions ............................ 24-39 EZ-KIT Lite Schematics ...................................................... 24-41 Oscilloscope Probes ............................................................. 24-41 Recommended Reading ....................................................... 24-42 System Components ................................................................. 24-43 lviii ADSP-214xx SHARC Processor Hardware Reference

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Power Management Circuits ................................................ 24-43 Supervisory Circuits ............................................................ 24-43 Definition of Terms .................................................................. 24-46

REGISTER REFERENCE
Overview ..................................................................................... A-2 Register Diagram Conventions ................................................ A-2 Bit Types and Settings ............................................................ A-3 System and Power Management Registers ..................................... A-5 System Control Register (SYSCTL) ......................................... A-5 Power Management Registers (PMCTL, PMCTL1) ................. A-7 Running Reset Control Register (RUNRSTCTL) .................. A-13 Programmable Interrupt Priority Control Registers ..................... A-14 Source Signals ...................................................................... A-14 Destination Signal Control Registers (PICRx) ....................... A-16 DAI/DPI Interrupt Control Registers .................................... A-18 External Port Registers ............................................................... A-20 External Port Control Register (EPCTL) ............................... A-20 External Port DMA Control Registers (DMACx) .................. A-23 Asynchronous Memory Interface Registers (AMI) .................. A-27 AMI Control Registers (AMICTLx) ................................. A-27 AMI Status Register (AMISTAT) ...................................... A-30 SDRAM Registers ................................................................ A-31 Control Register (SDCTL) ............................................... A-31 Refresh Rate Control Register (SDRRC) ........................... A-36

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Control Status Register 0 (SDSTAT0) ............................... A-37 Controller Status Register 1 (SDSTAT1) ............................ A-38 DDR2 Registers .................................................................... A-40 DDR2 Control Register 0 (DDR2CTL0) .......................... A-40 DDR2 Timing Control Register 1 (DDR2CTL1)............... A-45 DDR2 Control Register 2 (DDR2CTL2) .......................... A-47 DDR2 Control Register 3 (DDR2CTL3) .......................... A-49 DDR2 Control Register 4 (DDR2CTL4) .......................... A-51 DDR2 Control Register 5 (DDR2CTL5)........................... A-52 Refresh Rate Control Register (DDR2RRC) ...................... A-53 Controller Status Register 0 (DDR2STAT0) ...................... A-54 Controller Status Register 1 (DDR2STAT1) ...................... A-56 DLL0 Control Register 1 (DLL0CTL1) ............................ A-58 DLL1 Control Register 1 (DLL1CTL1) ............................ A-59 DLL Status Registers (DLL0STAT0, DLL1STAT0) ............ A-60 DDR2 Pad Control Register 0 (DDR2PADCTL0) ............ A-60 DDR2 Pad Control Register 1 (DDR2PADCTL1) ............ A-61 Peripheral Registers ..................................................................... A-62 Link Port Registers ................................................................ A-62 Control Register (LCTLx) ................................................ A-62 Status Registers (LSTATx) ................................................. A-65 Memory-to-Memory DMA Register ...................................... A-66 DMA Control (MTMCTL Register) ................................. A-66 Pulse Width Modulation Registers ......................................... A-67

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Global Control Register (PWMGCTL) ............................ A-67 Global Status Register (PWMGSTAT) .............................. A-69 Control Register (PWMCTLx) ......................................... A-69 Status Registers (PWMSTATx) ......................................... A-71 Output Disable Registers (PWMSEGx) ............................ A-71 Polarity Select Registers (PWMPOLx) .............................. A-72 Period Registers (PWMPERIODx) ................................... A-73 Duty Cycle High Side Registers (PWMAx, PWMBx) ........ A-74 Duty Cycle Low Side Registers (PWMALx, PWMBLx) ..... A-74 Dead Time Registers (PWMDTx) .................................... A-74 Debug Status Registers (PWMDBGx) .............................. A-74 FFT Accelerator Registers ..................................................... A-75 General Control Register (FFTCTL1) .............................. A-75 Control Register (FFTCTL2) ........................................... A-76 Multiplier Status Register (FFTMACSTAT) ...................... A-78 DMA Status Register ........................................................ A-78 Debug Registers (FFTDADDR, FFTDDATA) .................. A-79 FIR Accelerator Registers ...................................................... A-79 Global Control Register (FIRCTL1) ................................. A-79 Channel Control Register (FIRCTL2) .............................. A-81 FIR MAC Status Register (FIRMACSTAT) ...................... A-83 FIR DMA Status Register (FIRDMASTAT) ...................... A-85 FIR Debug Registers (FIRDEBUGCTL, FIRDBGADDR) ........................................................... A-86 IIR Accelerator Registers ....................................................... A-87 ADSP-214xx SHARC Processor Hardware Reference lxi

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IIR Global Control Register (IIRCTL1) ............................ A-87 IIR Channel Control Register (IIRCTL2) ......................... A-89 IIR MAC Status Register (IIRMACSTAT) ........................ A-90 IIR DMA Status Register (IIRDMASTAT) ........................ A-91 IIR Debug Registers (IIRDEBUGCTL, IIRDEBUGADDR) ....................................................... A-92 Media Local Bus Registers ..................................................... A-93 MLB System Registers ...................................................... A-93 Device Control Configuration Register (MLB_DCCR) .......................................................... A-94 System Status Register (MLB_SSCR) ............................ A-96 System Data Configuration Register (MLB_SDCR) ...... A-97 System Mask Configuration Register (MLB_SMCR) ..... A-98 Channel Interrupt Status Register (MLB_CICR) ........... A-99 DMA Base Address Registers ......................................... A-99 Logical Channel Registers ............................................... A-101 Channel Control Registers (MLB_CECRx) ................. A-101 Channel Status Configuration Registers (MLB_CSCRx) ........................................................ A-106 Channel x Current Buffer Configuration Registers (MLB_CCBCRx) .................................................. A-109 Channel x Next Buffer Configuration Registers (MLB_CNBCRx) .................................................... A-109 Local Buffer Configuration Registers (MLB_LCBCRx) ..................................................... A-110 Watchdog Timer Registers ................................................... A-111

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Control (WDTCTL) ...................................................... A-111 Status (WDTSTATUS) .................................................. A-112 Current Count (WDTCURCNT) .................................. A-113 Trip Counter (WDTTRIP) ............................................ A-113 Clock Select (WDTCLKSEL) ......................................... A-114 Period (WDTCNT) ....................................................... A-114 Unlock (WDTUNLOCK) .............................................. A-115 Real-Time Clock Registers .................................................. A-115 Control Register (RTC_CTL) ........................................ A-115 Status Register (RTC_STAT) .......................................... A-117 Stopwatch Count Register (RTC_STPWTCH) ............... A-118 Clock Register (RTC_CLOCK) ...................................... A-119 Alarm Register (RTC_ALARM) ..................................... A-120 Initialization Register (RTC_INIT) ................................ A-120 Initialization Status Register (RTC_INITSTAT) ............. A-122 DAI Signal Routing Unit Registers ........................................... A-123 Group A Clock Routing ................................................... A-123 Source Signals ................................................................ A-123 Destination Signal Control Registers (SRU_CLKx) ......... A-125 Group B Serial Data Routing ........................................... A-128 Source Signals ................................................................ A-128 Destination Signal Control Registers (SRU_DATx) ......... A-130 Group C Frame Sync Routing .......................................... A-133 Source Signals ................................................................ A-134

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Destination Signal Control Registers (SRU_FSx) ............. A-135 Group D Pin Buffer Signal Assignments ........................... A-137 Source Signals ................................................................ A-137 Destination Signal Control Registers (SRU_PINx) .......... A-141 Group E Miscellaneous Signals ......................................... A-143 Source Signals ................................................................ A-143 Destination Signal Control Registers (SRU_MISCx) ....... A-145 Group F DAI Pin Buffer Enable ....................................... A-146 Source Signals ................................................................ A-146 Destination Signal Control Registers (SRU_PBENx) ....... A-148 Group H Shift Register Clock Routing (ADSP-2147x) ...... A-150 Source Signals ................................................................ A-150 Destination Control Signal Register (SR_CLK_SHREG) ..................................................... A-151 Group I Shift Register Serial Data Routing Register (ADSP-2147x) ................................................................. A-152 Source Signals ................................................................ A-152 Destination Control Signal Register (SR_DAT_SHREG) A-153 DAI Pin Buffer Registers (DAI_PIN_STAT) ........................ A-153 Peripherals Routed Through the DAI ........................................ A-154 Serial Port Registers ............................................................. A-154 SPORT Divisor Registers (DIVx) .................................... A-154 Serial Control Registers (SPCTLx) .................................. A-155 SPORT Control 2 Registers (SPCTLNx) ......................... A-164 SPORT Multichannel Control Registers (SPMCTLx) ...... A-166

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SPORT Active Channel Select Registers (SPxCSy) .......... A-169 SPORT Compand Registers (SPxCCSy) ......................... A-169 Error Control Register (SPERRCTLx) ............................ A-170 SPORT Error Status Register (SPERRSTAT) .................. A-171 Input Data Port Registers ................................................... A-172 Input Data Port Control Register 0 (IDP_CTL0) ........... A-172 Input Data Port Control Register 1 (IDP_CTL1) ........... A-174 Input Data Port Control Register 2 (IDP_CTL2) ........... A-176 Parallel Data Acquisition Port Control Register (IDP_PP_CTL) .......................................................... A-176 IDP Status Register (DAI_STAT0) ................................. A-178 IDP Status Register 1 (DAI_STAT1) .............................. A-180 Asynchronous Sample Rate Converter Registers ................... A-181 Control Registers (SRCCTLx) ........................................ A-181 Mute Register (SRCMUTE) ........................................... A-185 Ratio Registers (SRCRATx) ............................................ A-186 Precision Clock Generator Registers .................................... A-187 Control Registers (PCG_CTLxy) ................................... A-187 Clock Inputs .................................................................. A-189 Pulse Width Registers (PCG_PWx) ................................ A-190 PCG Frame Synchronization Registers (PCG_SYNCx) ... A-192 Sony/Philips Digital Interface Registers ............................... A-195 Transmitter Registers ...................................................... A-195 Transmit Control Register (DITCTL) ......................... A-195

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Transmit Status Bit Registers for Subframe A/B (DITCHANAx/Bx) .................................................. A-198 Transmit User Bits Buffer Registers for Subframe A/B Registers (DITUSRBITAx/Bx) ................................. A-199 User Bit Update Register (DITUSRUPD) ................... A-200 Receiver Registers ........................................................... A-200 Receive Control Register (DIRCTL) ........................... A-200 Receive Status Register (DIRSTAT) ............................. A-202 Receive Status Registers for Subframe A (DIRCHANA) ......................................................... A-205 Receive Status Registers for Subframe B (DIRCHANB) ......................................................... A-205 Shift Register Control Register ............................................ A-206 Control Register (SR_CTL) ............................................ A-206 DPI Signal Routing Unit Registers ............................................ A-207 Group A Miscellaneous Signals ......................................... A-207 Source Signals ................................................................ A-207 Destination Control Signal Registers (SRU2_INPUTx) ... A-208 Group B Pin Assignment Signal ........................................ A-211 Source Signals ................................................................ A-211 Destination Signal Control Registers (SRU2_PINx) ........ A-214 Group C Pin Enable ......................................................... A-215 Source Signals ................................................................ A-216 Destination Control Signal Registers (SRU2_PBENx) ..... A-218 DPI Pin Buffer Status Register (DPI_PIN_STAT) ................ A-219

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Peripherals Routed Through the DPI ........................................ A-219 Serial Peripheral Interface Registers ..................................... A-219 Control Registers (SPICTL, SPICTLB) .......................... A-219 DMA Configuration Registers (SPIDMAC, SPIDMACB) .............................................................. A-225 Baud Rate Registers (SPIBAUD, SPIBAUDB) ................. A-228 Status (SPISTAT, SPISTATB) Registers ........................... A-229 SPI Port Flags Registers (SPIFLG, SPIFLGB) .................. A-231 UART Control and Status Registers .................................... A-232 Global Control Registers (UART0TXCTL, UART0RXCTL) ......................................................... A-232 Divisor Latch Registers (UART0DLL, UART0DLH) ...... A-234 Mode Register (UART0MODE) ..................................... A-234 Line Control Register (UART0LCR) .............................. A-236 Line Status Register (UART0LSR) .................................. A-238 Interrupt Enable Register (UART0IER) .......................... A-239 Interrupt Identification Registers (UART0IIR, UART0IIRSH) ........................................................... A-241 Scratch Register (UART0SCR) ....................................... A-242 DMA Status Registers (UART0TXSTAT, UART0RXSTAT) ........................................................ A-242 Two Wire Interface Registers .............................................. A-243 Master Internal Time Register (TWIMITR) ................... A-243 Clock Divider Register (TWIDIV) ................................. A-244 Master Control Register (TWIMCTL) ........................... A-245

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Master Address Register (TWIMADDR) ......................... A-247 Master Status Register (TWIMSTAT) ............................. A-248 Slave Mode Control Register (TWISCTL) ...................... A-250 Slave Address Register (TWISADDR) ............................. A-251 Slave Status Register (TWISSTAT) .................................. A-252 FIFO Control Register (TWIFIFOCTL) ......................... A-253 FIFO Status Register (TWIFIFOSTAT) .......................... A-254 Interrupt Latch Register (TWIIRPTL) ............................ A-256 Interrupt Enable Register (TWIIMASK) ......................... A-258 Peripheral Timer Registers ................................................... A-260 Read-Modify-Write Timer Control Register .................... A-260 Timer Control Registers (TMxCTL) ............................... A-261 Timer Status Register (TMSTAT) ................................... A-262

REGISTER LISTING
Power Management and Miscellaneous Registers ................. B-1 External Port Registers ........................................................ B-1 Serial Port Registers ............................................................ B-4 Serial Peripheral Interface Registers ................................... B-12 Peripheral Timer Registers ................................................ B-13 DAI/DPI Signal Routing Control Registers ....................... B-13 DAI/DPI Interrupt Control Registers ................................ B-16 Programmable Interrupt Priority Control Registers ............ B-16 DAI/DPI Pin Buffer Status Registers ................................. B-17 Input Data Port Registers .................................................. B-17

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Precision Clock Generator Registers ................................. B-19 Pulse Width Modulation Registers .................................... B-20 Memory-to-Memory DMA Registers ................................ B-21 Hardware Accelerator Registers (FFT/FIR/IIR) ................. B-22 S/PDIF Interface Registers ............................................... B-24 Sample Rate Converter Registers ...................................... B-26 UART Registers ............................................................... B-26 Two Wire Interface Registers ............................................ B-27 Link Port Registers ........................................................... B-28 Shift Register Register ...................................................... B-29 Watchdog Timer Registers ................................................ B-29 Real-Time Clock Registers ............................................... B-30 Media Local Bus Registers ................................................ B-30

AUDIO FRAME FORMATS

Overview ..................................................................................... C-2 Standard Serial Mode ................................................................... C-2 I2S Mode ..................................................................................... C-3 Left-Justified Mode ...................................................................... C-5 Right-Justified Mode .................................................................... C-5 TDM Mode ................................................................................. C-6 Packed I2S Mode .................................................................... C-7 MOST Mode ......................................................................... C-7 AES/EBU/SPDIF Formats ........................................................... C-8

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Subframe Format .................................................................. C-11 Channel Coding ................................................................... C-13 Preambles ............................................................................. C-14

INDEX

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PREFACE

Thank you for purchasing and developing systems using SHARC processors from Analog Devices.

Purpose of This Manual

The ADSP-214xx SHARC Processor Hardware Reference contains information about the peripherals associated with these processors. These are 32-bit, fixed- and floating-point digital signal processors from Analog Devices for use in computing, communications, and consumer applications.

Intended Audience
The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts (such as the appropriate hardware reference manuals and data sheets) that describe your target architecture.

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Manual Contents

Manual Contents
This manual provides detailed information about the ADSP-214xx processor peripherals in the following chapters: Chapter 1, Introduction Provides an architectural overview of the SHARC processors. Chapter2 Interrupt Control Provides a functional description of the system interrupt controller including a complete listing of the registers that are used to configure and control interrupts. Chapter 3, I/O Processor Describes input/output processor architecture, and provides direct memory access (DMA) procedures for the processor peripherals. Chapter 4, External Port Describes how the processors connect to external memories. These include DDR2 (ADSP-2146x) and SDRAM (ADSP-2147x, ADSP-2148x). Chapter 5, Link Ports ADSP-2146x Describes the two bidirectional 8-bit wide link ports, which can connect to other processor or peripheral link ports. Chapter 6, Memory-to-Memory Port DMA Describes on-chip memory-to-memory DMA. Chapter 7 FFT/FIR/IIR Hardware Modules Describes the dedicated hardware accelerators used to reduce the instruction load on the core, freeing it up for other tasks, effectively adding more bandwidth.

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Chapter 8, Pulse Width Modulation Describes the implementation and use of the pulse width modulation module which provides a technique for controlling analog circuits with the microprocessors digital outputs. Chapter 9, Media Local Bus Details the Media Local Bus port (MLB), an on-PCB or inter-chip communication bus, which allows an application to access MOST network data via an INIC (intelligent network interface controller). Chapter 10, Digital Application/ Digital Peripheral Interfaces Provides information about the digital audio/digital peripheral interface (DAI/DPI) which allows you to attach an arbitrary number and variety of peripherals to the SHARC processor while retaining high levels of compatibility. Chapter 11, Serial Ports (SPORTs) Describes the data line serial ports. Each SPORT contains a clock, a frame sync, and two data lines that can be configured as either a receiver or transmitter pair. Chapter 12, Input Data Port (SIP, PDAP) Discusses the function of the input data port (IDP) which provides a low overhead method of routing signal routing unit (SRU) signals back to the cores memory. Chapter 13, Asynchronous Sample Rate Converter Provides information on the sample rate converter (SRC) module. This module performs synchronous or asynchronous sample rate conversion across independent stereo channels, without using any internal processor resources.

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Chapter 14, Sony/Philips Digital Interface Provides information on the use of the Sony/Philips Digital Interface which is a standard audio file transfer format that allows the transfer of digital audio signals from one device to another without having to be converted to an analog signal. Chapter 15, Precision Clock Generator Details the precision clock generators (PCG), each of which generates a pair of signals derived from a low jitter based off-chip clock input signal. Chapter 16, Serial Peripheral Interface Ports Describes the operation of the serial peripheral interface (SPI) port. SPI devices communicate using a master-slave relationship and can achieve high data transfer rate because they can operate in full-duplex mode. Chapter 17, Peripheral Timers Describes the 32-bit timers that can be used to interface with external devices. Chapter 18, Shift Register ADSP-2147x Describes the 18 stage serial in, serial/parallel out shift register. Chapter 19, Real-Time Clock ADSP-2147x/ADSP-2148x Describes the real time clock which operates independent of the processor clocks. Chapter 20, WatchDog Timer ADSP-2147x, ADSP-2148x Describes software watchdog function which can improve system reliability by forcing the processor to a known state. Chapter 21, UART Port Controller Describes the operation of the Universal Asynchronous Receiver/Transmitter (UART) which is a full-duplex peripheral compatible with PC-style industry-standard UART.

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Chapter 22, Two Wire Interface Controller The two wire interface is fully compatible with the widely used I2C bus standard. It is designed with a high level of functionality and is compatible with multi-master, multi-slave bus configurations. Chapter 23, System Design Describes system design features of the ADSP-214xx processors. These include power, reset, clock, JTAG, and booting, as well as pin multiplexing schemes and other system-level information. Chapter 24, Power Management Describes system design features as they relate to power management. Appendix A, Register Reference Provides a graphical presentation of all registers and describes the bit usage in each register. Appendix B, Register Listing Provides the register mnemonic, address, brief description, and state at reset of all registers. Appendix C Audio Frame Formats Provides descriptions on the standard audio formats used by many of the peripherals. is a companion This hardware referenceReference. document to the SHARC Processor Programming

Whats New in This Manual

This is the first general release of the final edition (Revision 1.0) of the this manual and corresponds to the production release of all products described in this manual. Changes from the preliminary edition include the following.

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Technical or Customer Support

Corrected and clarified functional descriptions, operating modes and programming models across all chapters. Added support for shared memory systems using the ADSP-21469 processor. See Shared Memory Interface (ADSP-2146x) on page 4-104 for complete information. Revised and retitled the Peripheral Interrupt Control appendix by moving more general system interrupt information here. As such this chapter contains most of the basic interrupt information and therefore was moved to the beginning of the manual. Removed the Register Listing section of the Register Reference and created a separate appendix with bookmarks.

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following ways: Visit the Embedded Processing and DSP products Web site at
http://www.analog.com/processors/technical_support

E-mail tools questions to

[email protected]

E-mail processor questions to

[email protected] (World wide support) [email protected] (China support)

Phone questions to 1-800-ANALOGD

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Contact your Analog Devices, Inc. local sales office or authorized distributor Send questions by mail to: Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA

Registration for MyAnalog.com

is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information about products you are interested in. Click Register to use this site. Registration takes about five minutes and serves as a means to select the information you want to receive.
MyAnalog.com

If you are already a registered user, just log on. Your user name is your e-mail address.

EngineerZone
EngineerZone is a technical support forum from Analog Devices. It allows you direct access to ADI technical support engineers. You can search FAQs and technical information to get quick answers to your embedded processing and DSP design questions. Use EngineerZone to connect with other DSP developers who face similar design challenges. You can also use this open forum to share knowledge and collaborate with the ADI support team and your peers. Visit http://ez.analog.com to sign up.

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Supported Processors

Supported Processors
The name SHARC refers to a family of high-performance, 32-bit, floating-point processors that can be used in speech, sound, graphics, and imaging applications. VisualDSP++ currently supports the following SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x and ADSP-2148x.

Product Information
Product information can be obtained from the Analog Devices Web site, VisualDSP++ online Help system, and a technical library CD.

Analog Devices Web Site

The Analog Devices Web site, www.analog.com, provides information about a broad range of productsanalog integrated circuits, amplifiers, converters, and digital signal processors. To access a complete technical library for each processor family, go to http://www.analog.com/processors/technical_library. The manuals selection opens a list of current manuals related to the product as well as a link to the previous revisions of the manuals. When locating your manual title, note a possible errata check mark next to the title that leads to the current correction report against the manual. Also note, MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests, including documentation errata against all manuals.

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provides access to books, application notes, data sheets, code examples, and more.
MyAnalog.com

Visit www.myanalog.com to sign up. If you are already a registered user, just log on. Your user name is your e-mail address.

VisualDSP++ Online Documentation

Online documentation comprises the VisualDSP++ Help system, software tools manuals, hardware tools manuals, processor manuals, Dinkum Abridged C++ library, and FLEXnet License Tools software documentation. You can search easily across the entire VisualDSP++ documentation set for any topic of interest. For easy printing, supplementary Portable Documentation Format (.pdf) files for all manuals are provided on the VisualDSP++ installation CD. Each documentation file type is described as follows.
File
.chm .htm or .html

Description Help system files and manuals in Microsoft help format Dinkum Abridged C++ library and FLEXnet License Tools software documentation. Viewing and printing the .html files requires a browser, such as Internet Explorer 6.0 (or higher). VisualDSP++ and processor manuals in PDF format. Viewing and printing the .pdf files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).

.pdf

Technical Library CD
The technical library CD contains seminar materials, product highlights, a selection guide, and documentation files of processor manuals, VisualDSP++ software manuals, and hardware tools manuals for the following processor families: Blackfin, SHARC, TigerSHARC, ADSP-218x, and ADSP-219x.

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Notation Conventions

To order the technical library CD, go to http://www.analog.com/processors/manuals, navigate to the manuals page for your processor, click the request CD check mark, and fill out the order form. Data sheets, which can be downloaded from the Analog Devices Web site, change rapidly, and therefore are not included on the technical library CD. Technical manuals change periodically. Check the Web site for the latest manual revisions and associated documentation errata.

Notation Conventions
Text conventions used in this manual are identified and described as follows. Note that additional conventions, which apply only to specific chapters, may appear throughout this document.
Example Close command (File menu)
{this | that}

Description Titles in reference sections indicate the location of an item within the VisualDSP++ environments menu system (for example, the Close command appears on the File menu). Alternative items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required. Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that. Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this. Commands, directives, keywords, and feature names are in text with letter gothic font. Non-keyword placeholders appear in text with italic style format.

[this | that]

[this,]

.SECTION
filename

SWRST Software Reset Register names appear in UPPERCASE and a special typeface. The descriptive names of registers are in mixed case and regular typeface. register
TMR0E, RESET

Pin names appear in UPPERCASE and a special typeface. Active low signals appear with an OVERBAR.

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Preface

Example
DRx, I[3:0] SMS[3:0]

Description Register, bit, and pin names in the text may refer to groups of registers or pins: A lowercase x in a register name (DRx) indicates a set of registers (for example, DR2, DR1, and DR0). A colon between numbers within brackets indicates a range of registers or pins (for example, I[3:0] indicates I3, I2, I1, and I0; SMS[3:0] indicates SMS3, SMS2, SMS1, and SMS0). A 0x prefix indicates hexadecimal; a b# prefix indicates binary. Note: For correct operation, ... A Note: provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol. Caution: Incorrect device operation may result if ... Caution: Device damage may result if ... A Caution: identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol. Warning: Injury to device users may result if ... A Warning: identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for devices users. In the online version of this book, the word Warning appears instead of this symbol.

0xabcd, b#1111

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lxxxi

Notation Conventions

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1 INTRODUCTION

The ADSP-214xx SHARC processors are high performance 32-bit processors used for high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. By adding on-chip SRAM, integrated I/O peripherals, and an additional processing element for single-instruction multiple-data (SIMD) support, this processor builds on the ADSP-21xxx family DSP core to form a complete system-on-a-chip.

Design Advantages
A digital signal processors data format determines its ability to handle signals of differing precision, dynamic range, and signal-to-noise ratios. Because floating-point DSP math reduces the need for scaling and the probability of overflow, using a floating-point processor can simplify algorithm and software development. The extent to which this is true depends on the floating-point processors architecture. Consistency with IEEE workstation simulations and the elimination of scaling are clearly two ease-of-use advantages. High level language programmability, large address spaces, and wide dynamic range allow system development time to be spent on algorithms and signal processing concerns, rather than assembly language coding, code paging, and error handling. The SHARC processors described in this manual are highly integrated, 32-bit/40-bit floating-point processors which provide all of these design advantages.

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Processor Architectural Overview

SHARC Family Product Offerings

The products described in this manual offer a variety of features and performance. A complete list of features and specifications can be found in the product specific data sheet. Some models of these products are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Contact your local ADI account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Processor Architectural Overview

The ADSP-214xx processors form a complete system-on-a-chip, integrating a large, high speed SRAM and I/O peripherals supported by a dedicated I/O bus. The following sections summarize the features of each functional block in the SHARC architecture.

Processor Core
The processor core consists of two processing elements (each with three computation units and data register file), a program sequencer, two data address generators, a timer, and an instruction cache. Digital signal processing occurs primarily in the processor core.

I/O Peripherals
These peripherals are coupled with the external port and therefore independent from the routing units. Asynchronous Memory Interface (AMI) SDRAM controller (ADSP-2147x, ADSP-2148x)

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Introduction

DDR2 controller (ADSP-2146x) 4 PWM modules The FFT, FIR, and IIR accelerators each contain dedicated signal processing units to off load core processing for these units. Link ports for inter-chip communication I/O Processor The input/output processor (IOP) manages the off-chip data I/O to free the core from this burden. Up to 67 peripheral DMA channels are multi-stage arbitrated into internal or external memory. For model specific information, see the product specific data sheet. Digital Audio Interface (DAI) The digital audio interface (DAI) unit consists of an interrupt controller, a signal routing unit, and many peripherals: 8 serial ports (SPORT) Input Data Port (IDP) 4 precision clock generators (PCG) Some family members have an S/PDIF receiver/transmitter 4 asynchronous sample rate converters (ASRC) DTCP encryption DAI System Interrupt Controller The DAI contains its own interrupt controller that indicates to the core when DAI audio events have occurred. This interrupt controller offers 32 independently configurable channels.

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1-3

Differences from Previous Processors

Signal Routing Unit Conceptually similar to a patch-bay or multiplexer, the SRU provides a group of registers that define the interconnection of the DAI peripherals to the DAI pins or to other DAI peripherals. Digital Peripheral Interface (DPI) The digital peripheral interface (DPI) unit consists of an interrupt controller, a signal routing unit, and many peripherals: 2 serial peripheral interface ports (SPI) 2 peripheral timers 1 UART 1 TWI controller (I2C compatible) DPI System Interrupt Controller The DPI contains its own interrupt controller that indicates to the core when DPI audio events have occurred. This interrupt controller offers 12 independently configurable channels. Signal Routing Unit 2 Conceptually similar to a patch-bay or multiplexer, the SRU2 provides a group of registers that define the interconnection of the DPI peripherals to the DPI pins or to other DPI peripherals.

Differences from Previous Processors

This section identifies differences between the ADSP-214xx processors and previous SHARC processors: ADSP-21161, ADSP-21160, ADSP-21060, ADSP-21061, ADSP-21062, and ADSP-21065L. Like the

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Introduction

ADSP-2116x family, the ADSP-214xx SHARC processor family is based on the original ADSP-2106x SHARC family. The ADSP-214xx processors preserve much of the ADSP-2106x architecture and is code compatible to the ADSP-21160, while extending performance and functionality. For background information on previous generations of SHARC processors and the ADSP-2106x family DSPs, see the ADSP-2106x SHARC Users Manual or the ADSP-21065L SHARC DSP Technical Reference.

I/O Architecture Enhancements

The I/O processor provides much greater throughput than the ADSP-2116x processors. This architecture incorporates two independent DMA buses versus the previous SHARC DMA controllers: one peripheral DMA bus (IOD0) one external port DMA bus (IOD1) This allows operation of all external port DMA accesses independently from the peripheral buses since up to four internal memory blocks are addressable without bus conflicts. The SPORT modules can perform DMA accesses directly into the SDRAM/DDR2 memory space without the need to split the memory space into I/O-to- internal memory and internal-to-external memory. The core access bus to the external port has been increased in I/O size from 48 bits (previous SHARC processors) to 64 bits. This enhancement allows external memory access in SIMD mode operation by accessing data directly between external memory and the PEY unit. Moreover, external instruction fetch has also been enhanced. The application decides (depending on the address space) for normal word to fetch traditional ISA instructions or in the short word space to fetch VISA instructions.

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Development Tools

Development Tools
The processors are supported by CrossCore Embedded Studio (CCSE), an easy to use Integrated Development Environment (IDE) for Analog Devices processor-based applications. The CCSE IDE is built upon Eclipse, a multi-language, open-source software development environment, and provides complete graphical control of the edit, build, and debug processes. You can move easily between editing, building, and debugging activities within a single interface.

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2 INTERRUPT CONTROL

This chapter provides information about controlling interrupts as well as a complete listing of the registers that are used to configure and control programmable interrupts. For information on the IRPTL, LIRPTL, and IMASK registers, see the SHARC Processor Programming Reference. Table 2-1. Link Port Specifications
Feature Total Channels Peripheral Channels Miscellaneous Channels Local Priorities Rising Falling Edge Interrupt to Core Clock Operation DAI 32 22 10 Yes (high, low) Yes 2 fPCLK/4 DPI 12 3 9 No Yes 1 fPCLK/4

Features
Two system interrupt controllers (DAI SIC, DPI SIC) are connected to the core interrupt controller. The DAI SIC allows high or low interrupt priority configuration options. The DAI interrupt controller offers up to 32 independently configurable channels.

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Clocking

The DPI interrupt controller offers up to 12 independently configurable channels. Both controllers allow latching on rising or/and falling edges of waveform events. Same interrupt latency as core latched interrupts.

Clocking
The fundamental timing clock of the system interrupt controllers is peripheral clock/4. (fPCLK/4). All interrupt requests are acknowledged and responded to with up to fPCLK/4 speed.

Register Overview
Programmable Interrupt Control Registers (PICR30). Nineteen peripherals can be routed to the programmable interrupt inputs with the purpose to assign individual priorities to each peripheral channel. DAI Interrupt Mask Registers (DAI_IMASK_RE/FE). Masks interrupt for rising and/or falling edge waveform events. DAI Interrupt Mask Priority Register (DAI_IMASK_PRI). Masks interrupt for DAI high or DAI low interrupt priority. DAI Interrupt Latch Registers (DAI_IRPTL_L/H). Latches interrupt for the DAI high or DAI low interrupt. DPI Interrupt Mask Registers (DPI_IMASK_RE/FE). Masks interrupts for rising and/or falling edge waveform events. DPI Interrupt Latch Registers (DPI_IRPTL). Latches interrupt for DPI interrupt.

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Interrupt Control

Functional Description
The following sections provide information on function of the interrupt controller.

Programmable Interrupt Priority Control

The processor core supports 19 programmable prioritized interrupts, which are shown in an example routing in Figure 2-1. The highest priority interrupt is P0I while the lowest priority is P18I. Any peripheral interrupt output may be connected to any programmable priority interrupt input. All peripheral interrupt output signals are considered as source signals. The 19 prioritized peripheral interrupts (P0IP18I) of the core are considered destination interrupts. The PICR register controls the connectivity between the source and destination. The interrupt output of every peripheral can be programmed to connect to any one of the 19 peripheral interrupts. Moreover, the peripherals are grouped in two broad categoriesDAI or DPI, each having its own interrupt controller. These interrupt controllers program the polarity, priority and the destination of each peripheral interrupt output. Therefore, all peripheral interrupts can also be connected to the core as DAI or DPI interrupts.

The PICR controls all peripherals interrupts including DAI or DPI unit.

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Functional Description

SOURCE (PERIPHERAL IRQ) DAIHI SPIHI GPTMR0I SP1I SP3I SP5I SP0I SP2I SP4I EPDMA0I GPTMR1I SP7I DAILI EPDMA1I DPII MTMI SP6I SPILI UART0RXI UART0TXI TWII PWMI LP0I/RTCI LP1I ACC0I ACC1I MLBI SOFTWARE

DESTINATION (PICR CONTROL) P5I-P0I P11I-P6I P17I-P12I

PICR MUX

PICR MUX
5 4 1 3 1 2 0 1 1 0 1 4 0 PICR0 Select Field

3 0

PICR1 Select Field

Figure 2-1. Programmable Prioritized Interrupts

PICR MUX
5 2 1 1 1 0 1 4 0

5 3 0 2 0 1 1 0 0

PICR2 Select Field

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Interrupt Control

Peripheral Interrupt All input field encodings from Table A-6 on page A-14 assign a peripheral to trigger an interrupt as shown in the example below.
ustat1=dm(PICR2); bit set ustat1 P17I4|P17I3; bit clr ustat1 P17I2|P17I1|P17I0; dm(PICR2)=ustat1; /* write 11000 to route ACC1I to P17I

*/

Software Interrupt Using the selection code 11111 (High) in Table A-6 on page A-14 allows programs to use software based interrupts (see example below). Unlike the core (four software interrupts) these software interrupts can be changed in priority.
ustat1=dm(PICR0); bit set ustat1 P2I4|P2I3|P2I2|P2I1|P2I0; dm(PICR0)=ustat1; /* write 11111 to route SWI to P2I */ ...... P2I_ISR: ustat1=dm(PICR0); bit clr ustat1 P2I4|P2I3|P2I2|P2I1|P2I0; dm(PICR0)=ustat1; /* clear 00000 for P2I acknowledge */ rti;

Peripherals with Multiple Interrupt Request Signals The TWI and the UART have separate interrupt outputs. Both peripherals are already connected via the P14I (DPI) by default. However both peripherals allow separate connectivity into the PICR that are not routed by default. This provides more flexibility for priority change across the DAI/DPI interrupts.

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Functional Description

System Interrupt Controller

The DAI and DPI modules each incorporate a system interrupt controller (SIC) which is connected to the core interrupt controller as seen in Figure 2-2.
32 DAI Interrupt Channels 12 DPI Interrupt channels DAI SIC
CLR

INTERRUPT CONTROL 31-0

DAI_IMASK_PRI DPI SIC DAI_IMASK_RE DAI_IMASK_FE DPI_IRPTL

CLR

INTERRUPT CONTROL DPI_IMASK_RE 11-0 DPI_IMASK_FE OR

DAI_IRPTL_L DAI_IRPTL_H

high

low

OR OR

PERIPHERAL CORE BUS High Priority Interrupt Low Priority Interrupt Programmable Interrupts (Core Interrupt Controller) Programmable Interrupts (P18I - P0I) Misc. Core Interrupts DPI Interrupt Misc. Peripheral Interrupts

Core Interrupt Control

Interrupt Vector Table

Figure 2-2. DAI/DPI System Interrupt Controllers (SIC) The DAI/DPI contain their own system interrupt controllers that indicate to the core when DAI/DPI audio peripheral-related events have occurred. Since audio events generally occur infrequently relative to the SHARC core, the DAI/DPI interrupt controller reduces all of its interrupts onto three interrupt signals within the cores primary interrupt systemsone mapped with DAI low priority, one mapped with DAI high priority and the third mapped into the DPI interrupt. This allows programs to broadly indicate priority. In this way the DAI SIC provides 32 and the DPI SIC 2-6 ADSP-214xx SHARC Processor Hardware Reference

Interrupt Control

12 independently configurable sources/channels. The output bus interrupt signals are logically ORed into one interrupt line and fed to the cores interrupt controller logic.

The DAI/DPI interrupt controllers6have theofsame interrupt latency as the core interrupt controller, or cycles latency to respond to
asynchronous interrupts. Three registers are used to configure the DAI interrupt controller. Each of the 32 interrupt sources can be independently configured to trigger on an incoming signals rising edge, falling edge, both edges, or neither edge. Two registers are used to configure the DPI interrupt controller. Each of the 12 interrupt sources can be independently configured to trigger on an incoming signals rising edge, falling edge, both edges, or neither edge. Note that all DAI/DPI interrupt control registers are memory mapped registers and are accessed via the peripheral bus while the core interrupt registers are system registers. For more information on core interrupts, see the processor programming reference manual. DAI/DPI Interrupt Sources The DAIs five peripheral sources are multiplexed into 32 interrupt sources and are labeled DAI_INT310. The DPIs three peripheral sources are multiplexed into 12 interrupt sources and are labeled DPI_INT130 (Table 2-2). conventions. There are two naming labeled The DAI/DPI interrupt con/ troller register bits are
DAI_31-0_INT DPI_13-0_INT

(def214xx.h file). Their corresponding SRU routing signals are labeled DAI_INT_31-0_I/DPI_INT_13-0_I (sru214xx.h file).

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Functional Description

Table 2-2. Overview of DAI/DPI Interrupt Sources

Interrupt Source DAI_INT70 DAI_INT98 DAI_INT1710 DAI_INT70 DAI_INT2118 DAI_INT3122 DPI_INT2, 0 DPI_INT4 DPI_INT135 Description S/PDIF RX, 8 channels IDP Buffer, 2 channels IDP DMA, 8 channels S/PDIF RX, 8 channels ASRC, 4 channels Miscellaneous, S/PDIF TX, 10 channels UARTRX/TX, 2 DMA channels TWI, 1 channel Miscellaneous, 9 channels Waveform Event Waveform Signal Response Event

DAI Interrupt Latch Priority Option The DAI system interrupt controller register pair (DAI_IRPTL_H and DAI_IRPTL_L) replace functions normally performed by the core interrupt controllers IRPTL register. A single register (DAI_IRPTL_PRI) specifies to which latch these interrupts are mapped. When a DAI interrupt is configured as low priority (DAI_IMASK_PRI bit cleared, default setting), it is latched in the DAI_IRPTL_L register. The low priority DAI interrupt, DAILI, is connected to the P12I core interrupt by default. The PICR register can alter this connection. Whenever a DAI low priority interrupt is set, the programmed DAILI bit in LIRPTL register sets, and the core services that low priority interrupt. When a DAI interrupt is configured as high priority (DAI_IMASK_PRI bit set), it is latched in the DAI_IRPTL_H register. The high priority DAI interrupt, DAIHI, is connected to the P0I core interrupt by default. The PICR register can alter this connection. Whenever a DAI high priority interrupt is set, the programmed DAIHI bit in LIRPTL register sets, and the core services that interrupt with high priority.

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Interrupt Control

interrupts the one each or The DAI triggers twoany interruptinfromIVT,DAI needsfor lowserhigh priority. When the to be viced, one of the two core ISRs must interrogate the DAIs interrupt controller to determine the source(s). DPI Interrupt Latch The DPI SIC register (DPI_IRPTL) replaces functions normally performed by the core interrupt controllers IRPTL register. When a DPI interrupt is configured, it is latched in the DPI_IRPTL register. The DPI interrupt is connected to the P14I core interrupt by default. The PICR register can alter this connection. Whenever a DPI interrupt is set, the programmed DPI bit in LIRPTL register sets and the core services that interrupt with the programmed priority. DAI/DPI Interrupt Mask for Waveforms Two registers (DAI_IMASK_RE and DAI_MASK_FE) replace the core interrupt controllers version of the IMASK register. As with the IMASK register, these DAI registers provide a way to specify which interrupts to acknowledge and handle, and which interrupts to ignore. These dual registers function as IMASK does, but with a higher degree of granularity. Use of the DAI_IMASK_RE/DAI_IMASK_FE registers or the DPI_IMASK_RE/ registers allows programs to acknowledge and respond to rising edges, falling edges, both rising and falling edges, or neither rising nor falling edges so they can be masked separately.
DPI_IMASK_FE

Signals from the SRU can be used to generate interrupts. For example, when the DAI_30_INT bit of DAI_IMASK_FE register is set to one, any falling edge signals from the external channel generate an interrupt in the core and the interrupt latch is set. A read of the MASK register does not clear the IRPTL register.

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Functional Description

DAI/DPI Interrupt Mask for Events The system interrupt controller needs information about a peripherals interrupt sources that correspond to event signals (refer to Table 2-2 on page 2-8). As a result, the rising edge is used as an interrupt source only. For DAI/DPI peripherals marked as events, programs may unmask an interrupt source on the rising edge only. DAI/DPI Interrupt Service The interrupt acknowledge operates differently when multiple channels are multiplexed into one interrupt output signal. When an interrupt from the DAI/DPI must be serviced, any of the three interrupt service routines (DAILI, DAIHI and DPII) must query the RIC to determine the source(s). Sources can be any one or more of the DAI channels (DAI_INT31-0) or DPI channels (DPI_INT13-0). When DAI_IRPTL_H is read, the high priority latched interrupts are cleared. When DAI_IRPTL_L is read, the low priority latched interrupts are cleared. When
DPI_IRPTL

is read, the latched interrupts are cleared.

The IDP_FIFO_GTN_INT interrupt is not cleared when the DAI_IRPTL_H/L registers are read. This interrupt is cleared automatically when the situation that caused the interrupt goes away. A shadow register, DPI_IRPTL_SH, is provided for the primary register DPI_IRPTL. Reads of this register returns the data in the DPI_IRPTL register without clearing the contents of the register. If an interrupt occurs in the same cycle as a latch register is cleared, the clear mechanism has lower priority and the new interrupt is registered.

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Interrupt Control

UARTRXI interrupts do The TWII andoccurs in these peripheralsnot follow this rule. Acknowledge latch register. latch registers ( / ) Reading the interrupt(read-only-to-clear bit type). Therefore, the clears the interrupts
DAI_IRPTL_x DPI_IRPTL

ISR must service all of the interrupt sources it discovers. That is, if multiple interrupts are latched in multiple mask registers, all of them must be serviced before executing an RTI instruction. Otherwise the condition is not cleared. For more information, see Programmable Interrupt Priority Control Registers on page A-14.

Interrupt Service
This section describes how the interrupt service routines operate to clear interrupt requests correctly. Interrupt driven I/O is advantageous because the core does not need to poll input signal. (For more information, see the Interrupts section in each peripheral chapter.) When an interrupt is triggered, the sequencer typically finishes the current instruction and jumps to the IVT (interrupt vector table). From the IVT the address then typically vectors to the ISR routine. The sequencer jumps into this routine, performs program execution and then exits the routine by executing the RTI (return from interrupt) instruction. However this rule does not apply for all cases and is discussed below. There are three interrupt acknowledge mechanisms used in an ISR routine and they depend on the peripheral: RTI instruction Read-only to-clear (ROC) status bit + RTI instruction Write-1-to clear (W1C) status bit + RTI instruction

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Functional Description

The DAI/DPI interrupt controllers are designed such that in order to terminate correctly, the latch register must be read to identify the source. Note that this read automatically acknowledges the request before exiting an interrupt routine. For the W1C mechanism, programs must write into the specific bit of the latch register in order to terminate the interrupt properly. not If the acknowledge mechanism rules areoccur.followed correctly, unwanted and sporadic interrupts will Core Buffer Service Request (I/O mode) If the data stream peripherals access its data buffer of the respective DMA FIFO through the core, the buffer status plays a significant role in acknowledging the interrupt. If, for example, a receive buffer is full, an interrupt is generated and the buffer is read in the ISR, automatically clearing the request (ROC + RTI). Similarly, if a transmit buffer is empty, an interrupt is generated and the write clears the request (WOC + RTI). DMA Access If the peripherals access the buffer by DMA, the logic operates differently. In DMA, the buffer status has no effect on interrupts. Rather, the DMA count register generates an interrupt whenever it reaches zero. The acknowledge mechanisms may vary by the peripheral used.

Interrupt Latency
Good programming requires that an interrupt service acknowledge an interrupt request back to the peripheral as early as possible. This response allows the peripheral to sense additional events as quickly as possible. The service routine must ensure that the requests are released before the RTI instruction executes. Otherwise, the service routine is invoked immediately after the execution of the RTI instruction. Some interrupt requests

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Interrupt Control

are cleared by write-one-to-clear (W1C) operations. This write command does not stall the core, rather it is automatically latched in a write buffer and synchronized with the peripheral clock domain (PCLK) before it is sent to the peripheral bus. This process may require multiple CCLK cycles before the W1C operation arrives at the peripheral. If the W1C operation executes at the end of a service routine, a dummy read should be executed over the peripheral bus before the RTI instruction to ensure that the peripheral releases the request before the RTI executes. The following describe cases for interrupt latency. For peripherals with W1C acknowledge mechanisms a write into the peripherals status register to clear the interrupt causes a certain amount of latency (because of register write effect latency). Interrupt-driven data transfers (core or DMA) from any peripheral that generates interrupts and which uses an ISR routine, a write into a peripheral data buffer (to clear the interrupt) or a control register causes a certain amount of latency (due to the existence of register write effect latency and buffer clock domains). In both cases, if for example the program comes out of the interrupt service routine (RTI instruction) during that period of latency (maximum of 10 CCLK cycles), the interrupt is generated again. To avoid interrupt regeneration, use one of the following solutions.

The interrupt regeneration restriction does not apply to any SPORT in DMA operation mode.
1. Read an IOP register from the same peripheral block before the return from interrupt (RTI). The read forces the write to occur as shown in the example below.

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Functional Description

ISR_SPI_Routine: R0 = dm(i0,m0); dm(TXSPI) = R0; R0 = dm(SPICTL); rti; ISR_PWM_Routine: r1=PWM_STAT3; dm(PWMGSTAT)=r1; r0=dm(PWMGSTAT); rti;

/* write to SPI data buffer */ /* this dummy read forces the previous write to complete */

/* W1C to PWM status reg */ /* this dummy read forces the previous write to complete */

2. Add sufficient NOP instructions after a write. In the worst case, programs need to add ten NOP instructions after a write, as shown in the example code below.
ISR_Routine: R0 = 0x0; dm(SPICTL) = R0; /* or disable SPI control */ nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; rti;

DMA Completion Types On SHARC processors, interrupts are generated after internal transfer completion (when the DMA count register has expired). However, in some cases the transfer may not have completed (due to different channel priorities) and valid data still resides in the peripherals buffer, waiting to be transmitted. To overcome this problem, the interrupt access completion mode is introduced. In this mode the interrupt is generated when the last data has left the buffer. This option is available for the SPORT, SPI, link port and external port DMA. For details, refer to the specific peripherals chapter.

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Interrupt Control

Debug Features
This section describes the shadow registers used with the IDP, S/PDIF, ASRC, UART, TWI and DAI/DPI

Shadow Interrupt Register

The DAI/DPI interrupt controller has shadow registers to simplify debug activities since these registers do not manipulate status control. Any read of the DAI_IRPTL_x_SH or DPI_IRPTL_SH shadow registers provides the same data as a read of the DAI_IRPTL_x or DPI_IRPTL registers. However reads of the DAI/DPI shadow registers dont change the interrupt acknowledge status to the core interrupt controller.

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Debug Features

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3 I/O PROCESSOR

In applications that use extensive off-chip data I/O, programs may find it beneficial to use a processor resource other than the processor core to perform data transfers. The ADSP-214xx processors contain an I/O processor (IOP) that supports a variety of DMA (direct memory access) operations. Each DMA operation transfers an entire block of data. These operations include the transfer types shown in Table 3-1 and the list that follows. Table 3-1. I/O Processor Specifications
Feature Total DMA channels Rotating DMA channel priority Media Local Bus (MLB) SPORT DMA channels IDP DMA channels UART DMA channels FIR/FFT/IIR DMA channels SPI DMA channels MTM/DTCP DMA channels External Port DMA channels PDAP DMA channel DMA channel interrupts Clock Operation Availability See product specific data sheet Yes 31 16 8 2 2 2 2 2 1 16 fPCLK

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Features

Features
The I/O processor features are briefly described in the following list. Two independent DMA buses (peripheral and external port DMA bus) Both buses have high priority over the core for internal memory access DMA transfer types for standard, chained and ping-pong (IDP) DMA channel interrupt priority programmable (PICR registers) Channel arbitration fixed or rotated SPORT DMA support chain insertion mode (Changing TCB list during runtime) External port DMA supports direction on the fly DMA transaction can be paused by clearing the DMA enable bit DMA can be halt during single step for debug The I/O processor supports the following DMA transaction types. Internal memory IDP (DAI) unidirectional Internal memory SPORT (DAI) External memory SPORT (DAI) Internal memory SPI Internal memory Link port Internal memory MLB Internal memory UART

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I/O Processor

Internal memory Accelerator Internal memory External memory (External port) Internal memory Internal memory (MTM, External port) By managing DMA, the I/O processor frees the processor core, allowing it to perform other operations while off-chip data I/O occurs as a background task. The multi-bank architecture of the ADSP-214xx internal memory allows the core and IOP to simultaneously access the internal memory if the accesses are to different memory banks. This means that DMA transfers to internal memory do not impact core performance. The processor core continues to perform computations without penalty. To further increase off-chip I/O, multiple DMAs can occur at the same time. The IOP accomplishes this by managing multiple DMAs of processor memory through the different peripherals. Each DMA is referred to as a channel and each channel is configured independently.

Register Overview
Two global IOP registers control the DMA arbitration over the I/O busesthe first for the peripheral bus and the second for the external port bus. This section provides brief descriptions of the major IOP registers. For complete information, see Register Listing on page B-1. System Control Register (SYSCTL). Controls the peripheral DMA operation for fixed or rotating DMA channel arbitration. External Port Control Register (EPCTL). Controls the external port bus arbitration between SPORT, EPDMA and core access.

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Register Overview

DMA Channel Registers

The following sections provide information on the registers that control all DMA operations for each peripheral. Additional information on DMA operations can be found in specific peripheral chapters. DMA Channel Allocation Each channel has a set of parameter registers which are used to set up DMA transfers. Table 3-29 on page 3-39 shows the DMA channel allocation and parameter register assignments for the ADSP-214xx processors. vary by model. For a DMA channelsparticularprocessorsee the productbreakdown of DMA channels for a model, specific data sheet. Also note that each DMA channel has a specific peripheral assigned to it. Standard DMA Parameter Registers The parameter registers described below control the source and destination of the data, the size of the data buffer, and the step size used. changed from The length of DMA registers for thetoserial ports have data transfers earlier SHARC processors in order accommodate to/from external memory. Index registers. These registers, shown in Table 3-2, provide an internal memory address that acts as a pointer to the next internal memory DMA read or write location. All internal index registers have 18-bit address width. However all index registers are based on an internal memory offset of 0x80000 (bit 19 set) so the total width results to 19 bits. This internal memory offset is not applicable for the index registers that correspond to SPORT DMAs as these registers are 28 bits.

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I/O Processor

Table 3-2. Index Registers

Register Name IISP07A IISP07B IISPI IISPIB IDP_DMA_I07 IDP_DMA_I07A IDP_DMA_I07B IIUART0RX IIUART0TX IILB01 IIFIR CIFIR OIFIR IIIIR CIIIR OIIIR IIFFT OIFFT IIMTMW IIMTMR IIEP01 EIEP01 Width (Bits) Description 28 28 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 28 SPORTxA (supports external addresses) SPORTxB (supports external addresses) SPI SPIB IDPx IDPx index A (ping-pong) IDPx index B (ping-pong) UART0 Receiver UART0 Transmitter Link Port01 Accelerator FIR data input Accelerator FIR coeff input Accelerator FIR output Accelerator IIR data input Accelerator IIR coeff input Accelerator IIR output Accelerator FFT input Accelerator FFT output MTM Write MTM Read External Port External Port (external)

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Register Overview

Modify registers. These registers, shown in Table 3-3, provide the signed increment by which the DMA controller post-modifies the corresponding memory index register after the DMA read or write. Table 3-3. Modify Registers
Register Name IMSP07A IMSP07B IMSPI IMSPIB IDP_DMA_M07 IDP_DMA_M07A IDP_DMA_M07B IMLB01 IMUART0RX IMUART0TX IMFIR CMFIR OMFIR IMIIR CMIIR OMIIR IMFFT OMFFT IMMTMW IMMTMR IMEP01 EMEP01 Width (Bits) Description 16 16 16 16 6 6 6 16 16 16 16 16 16 16 16 16 16 16 16 16 16 27 SPORTA SPORTB SPI SPIB IDP IDP modify A (ping-pong) IDP modify B (ping-pong) Link Port UART0 Receiver UART0 Transmitter Accelerator FIR data input Accelerator FIR coeff input Accelerator FIR output Accelerator IIR data input Accelerator IIR coeff input Accelerator IIR output Accelerator FFT input Accelerator FFT output MTM Write MTM Read External Port External Port (external)

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Count registers. These registers, shown in Table 3-4, indicate the number of words remaining to be transferred to or from memory on the corresponding DMA channel. Table 3-4. Count Registers
Register Name CSP07A CSP07B ICSPI ICSPIB IDP_DMA_C07 ICLB01 CUART0RX CUART0TX ICFIR CCFIR OCFIR ICIIR CCIIR OCIIR ICFFT OCFFT ICMTMW ICMTMR ICEP01 ECEP01 Width (Bits) Description 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 SPORTA SPORTB SPI SPIB IDP Link Port UART0 Receiver UART0 Transmitter Accelerator FIR data input Accelerator FIR coeff input Accelerator FIR output Accelerator IIR data input Accelerator IIR coeff input Accelerator IIR output Accelerator FFT input Accelerator FFT output MTM Write MTM Read External Port External Port (external)

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Register Overview

Chain pointer registers. These registers, shown in Table 3-5, hold the starting address of the transfer control block (TCB parameter register values) for the next DMA operation on the corresponding channel. These registers also control whether the I/O processor generates an interrupt when the current DMA process ends. on transfer For information 3-31. control blocks (TCBs), see Chained DMA on page Table 3-5. Chain Pointer Registers
Register Name CPSP07A CPSP07B CPSPI CPSPIB CPLB01 CPUART0RX CPUART0TX CPFIR CPIIR CPIFFT CPOFFT CPEP01 Width (Bits) Description 28 28 20 20 20 20 20 20 20 21 20 21 SPORTA SPORTB SPI SPIB Link Port UART0 Receiver UART0 Transmitter Accelerator FIR Accelerator IIR Accelerator FFT input Accelerator FFT output External Port

Extended DMA Parameter Registers This section describes the enhanced parameter registers used for the accelerators and the external port. Base registers. These registers, shown in Table 3-6, indicate the start address of the circular buffer to be transferred to/from memory on the corresponding DMA channel. All internal base registers have 18-bit address

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width. However all index registers are based on an internal memory offset of 0x80000 (bit 19 set) so the total width is 19 bits. Table 3-6. Base Registers
Register Name IBFIR OBFIR IBIIR OBIIR IBFFT OBFFT EBEP01 Width (Bits) 19 19 19 19 19 19 28 Description Accelerator FIR input Accelerator FIR output Accelerator IIR input Accelerator IIR output Accelerator FFT input Accelerator FFT output External Port (external)

Length registers. These registers, shown in Table 3-7, define the length of the circular buffer to be transferred to/from memory on the corresponding DMA channel. Table 3-7. Length Registers
Register Name ILFIR OLFIR ILIIR OLIIR ILFFT OLFFT ELEP01 Width (Bits) 19 19 19 19 19 19 26 Description Accelerator FIR input Accelerator FIR output Accelerator IIR input Accelerator IIR output Accelerator FFT input Accelerator FFT output External Port (external)

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Register Overview

Miscellaneous External Port Parameter registers. These registers, shown in Table 3-8, are used for the delay line and scatter/gather DMA. They read from tap list buffers, store counters and index pointers. Table 3-8. Miscellaneous External Port Parameter Registers
Register Name RCEP1 RIEP1 RMEP1 TCEP TPEP 1 Width (Bits) 16 19 27 16 19 Description Delay line DMA read block size Delay line DMA read internal index Delay line DMA read external modifier Delay line/tap list DMA tap list count Delay line/tap list DMA tap list pointer

These registers are only accessible through the TCB loading.

MLB Parameter registers. The MLB interface does not have modify and count parameter registers like the other peripherals. Instead it has base and end address registers which implicitly define the DMA length. For more information, see Chapter 9, Media Local Bus. Data Buffers The data buffers or FIFOs (shown in Table 3-9) are used by each DMA channel to store data during the priority arbitration time period. The buffers (depending on the peripheral) are accessed by both DMA and the core. Table 3-9. Data Buffers
Buffer Name TXSP07A TXSP07B RXSP07A Total FIFO Depth 1+1 1+1 1+1 Description SPORTA Transmit (RW) + Shift Register SPORTB Transmit (RW) + Shift Register SPORTA Receive (RW) + Shift Register

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Table 3-9. Data Buffers (Contd)

Buffer Name RXSP07B TXSPI TXSPIB RXSPI RXSPIB RXSPI_SHADOW RXSPIB_SHADOW SPI DMA SPIB DMA IDP_FIFO TXLB01 TXLB01_IN_SHADOW Total FIFO Depth 1+1 1+1 1+1 1+1 1+1 1 1 4 4 8 2+1 1 Description SPORTB Receive (RW) + Shift Register SPI Transmit (RW) + Shift Register SPIB Transmit (RW) + Shift Register SPI Receive (RO) + Shift Register SPIB Receive (RO) + Shift Register SPI Receive Shadow (RO) SPIB Receive Shadow (RO) DMA only DMA only IDP FIFO Receive (RW) Link Port Transmit Buffer (RW) Link Port Transmit Shadow Pack Register (RO) Link Port Transmit Shadow Pack Register (RO) Link Port Receive Buffer (RW) Link Port Receive Shadow Pack Register (RO) Link Port Receive Shadow Pack Register (RO) UART0 Receiver (RO) + Shift Register UART0 Transmitter (WO) + Shift Register Buffer for FFT only Buffer for FFT only Internal DMA only External Port DMA only AMI Receive Packer AMI Transmit Packer TWI Transmit (WO) + Shift Register

TXLB01_OUT_SHADOW 1 RXLB01 RXLB01_IN_SHADOW 2+1 1

RXLB01_OUT_SHADOW 1 UARTRBR0 UARTTHR0 Accelerator FFT input Accelerator FFT output MTM read/write DFEP01 AMIRX AMITX TXTWI8 1+1 1+1 8 8 2 6 1 1 1+1

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Register Overview

Table 3-9. Data Buffers (Contd)

Buffer Name TXTWI16 RXTWI8 RXTWI16 MLB_CCBCR MLB_CNBCR Total FIFO Depth 2+1 1+1 2+1 124 x 36 124 x 36 Description TWI Transmit (WO) + Shift Register TWI Receive (RO) + Shift Register TWI Receiver (RO) + Shift Register RX Buffer (RW) (I/O mode) TX Buffer (RW) (I/O mode)

Some data buffers provide debug support to enable the buffer hang disable (BHD) bit. This feature can be enabled in the dedicated peripheral control register for the IDP, SPORT, link port, UART0 and the TWI. Chain Pointer Registers The chain pointer registers, described inTable 3-10, Table 3-11 (generic), Table 3-12 (SPORTs), Table 3-13 (external port) and Table 3-14 (FFT) are 20 bits wide. The lower 19 bits are the memory address field. Like other I/O processor address registers, the chain pointer registers value is offset to match the starting address of the processors internal memory before it is used by the I/O processor. On the SHARC processor, this offset value is 0x80000. Table 3-10. Chain Pointer Registers
Register CPEP01 CPSP07A CPSP07B CPSPI CPSPIB CPUART0RX Width 21 29 29 20 20 20 Description External Port SPORT A Channels SPORT B Channels SPI SPIB UART Receive

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Table 3-10. Chain Pointer Registers (Contd)

Register CPUART0TX CPLB0-1 CPFIR CPIIR CPIFFT CPOFFT Width 20 20 19 19 21 20 Description UART Transmit Link Port FIR IIR Input FFT Output FFT

Table 3-11. Chain Pointer Register Bit Descriptions (CPx)

Bit 180 19 Name IIx address PCI Description Next chain pointer address Program controlled interrupt 0 = no interrupt after current TCB 1 = interrupt after current TCB

SPORT when For the newinvolve theexternal memory functionality,addresswriting tests which bit, the external memory should
PCI

be split before writing to the chain pointer register. Table 3-12. SPORT Chain Pointer Register Bit Descriptions (CPSPx)
Bit 180 19 Name IIx address PCI Description Next chain pointer address (bits 180 of the chain pointer) Program controlled interrupt 0 = no interrupt after current TCB 1 = interrupt after current TCB Next chain pointer (external address, bits 2719 of the chain pointer)

2820

IIx address

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Register Overview

Note that the serial ports have the ability to fetch TCBs from external memory. Table 3-13. External Port Chain Pointer Register Bit Descriptions (CPEPx)
Bit 180 19 Name IIx address PCI Description Next chain pointer address Program controlled interrupt 0 = no interrupt after current TCB 1 = interrupt after current TCB DMA direction for next TCB 0 = write to internal memory 1 = read from internal memory

20

CPDR

Table 3-14. FFT Input Chain Pointer Register Bit Descriptions (CPIFFT)
Bit 180 19 Name IIx address PCI Description Next chain pointer address Program controlled interrupt 0 = no interrupt after current TCB 1 = interrupt after current TCB Coefficient select for next TCB 0 = next TCB is data TCB 1 = next TCB is coeff TCB

20

COEFFSEL

Bit 19 of the chain pointer register is the program controlled interrupt (PCI) bit. This bit controls whether an interrupt is latched after every DMA in the chain (when set = 1), or whether the interrupt is latched after the entire DMA sequence completes (if cleared = 0). If a program contains a single chained DMA then the PCI interrupt is generated coincident with the start of next TCB loading.

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However, if running multiple DMA channels this coincidence is no longer true since there are different DMA channel priorities versus interrupt priorities. bit only effects have The interrupt requests DMA channels thatbit arechaining enabled. Also, enabled by the maskable with
PCI PCI

the IMASK register.

TCB Storage
This section lists all the different TCB memory allocations used for DMA chaining on the peripherals. Note that all TCBs must be located in internal memory except SPORTs, where TCBs can exist in external memory.

Serial Port TCB

The serial ports support single and chained DMA. Table 3-15 shows the required TCBs for chained DMA Table 3-15. SPORT TCBs
Address CP[27:0] CP[27:0] + 0x1 CP[27:0] + 0x2 CP[27:0] + 0x3 Register CPSPx Chain Pointer ICSPx Internal Count IMSPx Internal Modifier IISPx Internal/External Index

SPI TCB
The serial peripheral interfaces supports both single and chained DMA. However, unlike the serial ports, programs cannot insert a TCB in an active chain. Table 3-16 shows the required TCBs for chained DMA.

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TCB Storage

Table 3-16. SPI/SPIB TCBs

Address CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 Register CPSPI/B Chain Pointer ICSPI/B Internal Count IMSPI/B Internal Modifier IISPI/B Internal Index

UART TCB
The UART interface supports both single and chained DMA. However, unlike the serial ports, programs cannot insert a TCB in an active chain. Table 3-17 shows the required TCBs for chained DMA. Table 3-17. UART0 TCBs
Address CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 Register RXCP_UAC0/TXCP_UAC0 Chain Pointer RXC_UAC0/TXC_UAC0 Internal Count RXM_UAC0/TXM_UAC0 Internal Modifier RXI_UAC0/TXI_UAC0 Internal Index

Link Port TCB

The link port interface supports both single and chained DMA. Table 3-18 shows the required TCBs for chained DMA. Table 3-18. Link Port TCBs
Address CP[18:0] CP[18:0] + 0x1 Register CPLPx Chain Pointer CLBx Internal Count

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Table 3-18. Link Port TCBs (Contd)

Address CP[18:0] + 0x2 CP[18:0] + 0x3 Register IMLBx Internal Modifier IILBx Internal Index

FIR Accelerator TCB

The FIR accelerator DMA supports circular buffer chained DMA. Table 3-19 shows the required TCBs for chained DMA. The FIR accelerator does not support circular buffering for the coefficient buffer. Table 3-19. FIR TCBs
Address CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 CP[18:0] + 0x4 CP[18:0] + 0x5 CP[18:0] + 0x6 CP[18:0] + 0x7 CP[18:0] + 0x8 CP[18:0] + 0x9 CP[18:0] + 0xA CP[18:0] + 0xB CP[18:0] + 0xC Register CPFIR CCFIR CMFIR CIFIR OBFIR OCFIR OMFIR OIFIR IBFIR ICFIR IMFIR IIFIR FIRCTL2

register loaded with the values in the TCB field The is decrementedisfrom that value onwards. However, coefficient and
CCFIR CCFIR

loading continues until the number of coefficients, equal to the tap ADSP-214xx SHARC Processor Hardware Reference 3-17

TCB Storage

length, are read. This is true even if the CCFIR register reaches zero as in the case of a tap length = 10, and the CCFIR field in the TCB is initialized to 0. The value in the CCFIR register is 10 after all coefficients are loaded.

IIR Accelerator TCB

The IIR accelerator supports circular buffer chained DMA. Table 3-20 shows the required TCBs for chained DMA. two different TCB loading sequences In the IIR accelerator DMA, five parameters for the coefficients are available: one TCB loads (IIRCTL2, CIIIR, CMIIR, CCIIR and CPIIR). The second loads 10 parameters for the data (IIRCTL2, IIIR, IMIIR, ICIIR, IBIIR, OIIIR, OMIIR, OCIIR, OBIIR and CPIIR). Table 3-20. IIR TCBs
Address CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 CP[18:0] + 0x4 CP[18:0] + 0x5 CP[18:0] + 0x6 CP[18:0] + 0x7 CP[18:0] + 0x8 CP[18:0] + 0x9 CP[18:0] + 0xA CP[18:0] + 0xB CP[18:0] + 0xC Register CPIIR CCIIR CMIIR CIIIR OBIIR OCIIR OMIIR OIIIR IBIIR ICIIR IMIIR IIIIR IIRCTL2

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FFT Accelerator TCB

The FFT accelerator supports circular buffer chained DMA. Table 3-21 and Table 3-22 shows the required TCBs for chained DMA. Table 3-21. FFT Input TCBs
Address CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 CP[18:0] + 0x4 CP[18:0] + 0x5 Register CPIFFT IBFFT ILFFT ICFFT IMFFT IIFFT

both data and coefficients. 20 The input)TCB controlschain pointer register ( Bit indicates of the input ), (
COEFFSEL CPIFFT

whether the TCB is for loading data or coefficients. For coefficient TCBs (COEFFSEL=1), circular buffering and the input length (ILFFT) and base length (IBFFT) TCB fields are ignored. Table 3-22. FFT Output TCBs
Address CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 CP[18:0] + 0x4 CP[18:0] + 0x5 Register CPOFFT OBFFT OLFFT OCFFT OMFFT OIFFT

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TCB Storage

External Port TCB

The external port interface supports many different types of DMA, resulting in different lengths of TCBs. The TCB size varies from six locations (chained DMA) to 13 locations (delay line DMA). Table 3-23 shows the required TCBs for chained DMA. Table 3-23. External Port TCBs
Address CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 CP[18:0] + 0x4 CP[18:0] + 0x5 Register CPEP EMEP EIEP ICEP IMEP IIEP

The order the descriptors are fetched with circular buffering enabled is shown in Table 3-24. Table 3-24. External Port TCBs for Circular DMA
Address CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 CP[18:0] + 0x4 CP[18:0] + 0x5 CP[18:0] + 0x6 CP[18:0] + 0x7 Register CPEP ELEP EBEP EMEP EIEP ICEP IMEP IIEP

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For delay line DMA, TCB loading is split into two sequences to improve overall priority. The first TCB loads the write parameters (IIEPELEP) and the second loads the read parameters (RIEPCPEP). This two stage loading is transparent to the application. The order the descriptors are fetched with circular buffering enabled is shown in Table 3-25. Table 3-25. External Port TCBs for Delay Line DMA
Address Delay Line Read CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 CP[18:0] + 0x4 CP[18:0] + 0x5 Delay Line Write CP[18:0] + 0x6 CP[18:0] + 0x7 CP[18:0] + 0x8 CP[18:0] + 0x9 CP[18:0] + 0xA CP[18:0] + 0xB CP[18:0] + 0xC ELEP EBEP EMEP EIEP ICEP IMEP IIEP CPEP TPEP TCEP RMEP RCEP RIEP Register

The order the descriptors are fetched for scatter/gather DMA with circular buffering enabled is shown in Table 3-26 and Table 3-27.

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Clocking

Table 3-26. External Port TCBs for Scatter/Gather DMA

Address CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 CP[18:0] + 0x4 CP[18:0] + 0x5 CP[18:0] + 0x6 CP[18:0] + 0x7 Register CPEP TPEP TCEP EMEP EIEP ICEP IMEP IIEP

Table 3-27. External Port TCBs for Circular Scatter/Gather DMA

Address CP[18:0] CP[18:0] + 0x1 CP[18:0] + 0x2 CP[18:0] + 0x3 CP[18:0] + 0x4 CP[18:0] + 0x5 CP[18:0] + 0x6 CP[18:0] + 0x7 CP[18:0] + 0x8 CP[18:0] + 0x9 Register CPEP ELEP EBEP TPEP TCEP EMEP EIEP ICEP IMEP IIEP

Clocking
The fundamental timing clock of the IOP is peripheral clock (PCLK). All DMA data transfers over the IO0 or IO1 buses are clocked at PCLK speed.

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Functional Description
The following several sections provide detail on the function of the I/O processor.

Automated Data Transfer

Because the IOP registers are memory-mapped, the processors have access to program DMA operations. A program sets up a DMA channel by writing the transfers parameters to the DMA parameter registers. After the index, modify, and count registers (among others) are loaded with a starting source or destination address, an address modifier, and a word count, the processor is ready to start the DMA. The peripherals each have a DMA enable bit in their channel control registers. Setting this bit for a DMA channel with configured DMA parameters starts the DMA on that channel. If the parameters configure the channel to receive, the I/O processor transfers data words received at the buffer to the destination in internal memory. If the parameters configure the channel to transmit, the I/O processor transfers a word automatically from the source memory to the channels buffer register. These transfers continue until the I/O processor transfers the selected number of words as determined by the count parameter. DMA through the IDP ports occurs in receive mode (into internal memory) only.

DMA Transfer Types

Standard DMA. A standard DMA (once it is configured) transfers data from location A to location B. An interrupt can be used to indicate the end of the transfer. To start a new DMA sequence after the current one is finished, a program must first clear the DMA enable bit (control register), write new parameters to the index, modify, and count registers (parameter registers), then set the DMA enable bit to re-enable DMA (control register).

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Functional Description

An instance where standard DMA can be used is to copy data from a peripheral to internal memory for processor booting. With the help of the loader tool, the tag (header information) of the boot stream is decoded to get the storage information which includes the index, modify, and count of a specific array to start another standard DMA. Chained DMA. Chained DMA sequences are a set of multiple DMA operations, each autoinitializing the next in line. To start a new DMA sequence after the current one is finished, the IOP automatically loads new index, modify, and count values from an internal memory location (or external memory location for DMA to external ports) pointed to by that channels chain pointer register. Using chaining, programs can set up consecutive DMA operations and each operation can have different attributes. Chained DMA with direction on the fly (External Port). The external port DMA controller supports chained DMA sequences with an additional feature that allows the port to change the data direction for each individual TCB. An additional bit in the TCB differentiates between a read or write operation. IDP The DMAport doesInnot support DMA chaining. have two Ping-pong (IDP). ping-pong DMA, the parameters memory index values (index A and index B), one count value and one modifier value. The DMA starts the transfer with the memory indexed by A. When the transfer is completed as per the value in the count register, the DMA restarts with the memory location indexed by B. The DMA restarts with index A after the transfer to memory with index B is completed as per the count value. This repeats until the DMA is stopped by resetting the DMA enable bit. Circular Buffering DMA (FFT, FIR, IIR, External Port). This mode resembles the chained DMA mode, however two additional registers (base and length) are used. This mode performs DMA within the circular

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buffer, which is useful for filter implementation since core interaction is limited, conserving bandwidth.

DMA Direction
The IOP supports DMA in four directions. These are described in the following sections. Internal to External Memory DMA transfers between internal memory and external memory devices use the processors external port. For these types of transfers, the application code provides the DMA controller with the internal memory buffer size, address, and address modifier, as well as the external memory buffer size, address, address modifier, and the direction of transfer. After setup, the DMA transfers begin when the program enables the channel and continues until the I/O processor transfers the entire buffer to processor memory. Table 3-29 on page 3-39 shows the parameter registers for each DMA channel. Peripheral to Internal Memory Similarly, DMA transfers between internal memory and serial, IDP, or SPI ports have DMA parameters. When the I/O processor performs DMA between internal memory and one of these ports, the program sets up the parameters, and the I/O uses the port instead of the external bus. The direction (receive or transmit) of the peripheral determines the direction of data transfer. When the port receives data, the I/O processor automatically transfers the data to internal memory. When the port needs to transmit a word, the I/O processor automatically fetches the data from internal memory. Figure 3-1 on page 3-27 shows more detail on DMA channel data paths.

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Functional Description

Peripheral to External Memory (SPORTs) The SPORTs allow direct DMA transfers between the SPORT and external memory space. Programs do not need to first copy data into internal memory and then run an external port DMA to external memory space. Internal Memory to Internal Memory The SHARC processors can use memory-to-memory DMA to transfer 64-bit blocks of data between internal memory locations.

DMA Controller Addressing

Figure 3-1 shows a block diagram of the I/O processors address generator (DMA controller). Standard DMA Parameter Registers on page 3-4 lists the parameter registers for each DMA channel. The parameter registers are uninitialized following a processor reset. The I/O processor generates addresses for DMA channels much the same way that the Data Address Generators (DAGs) generate addresses for data memory accesses. Each channel has a set of parameter registers, including an index register and modify register that the I/O processor uses to address a data buffer in internal memory. The index register must be initialized with a starting address for the data buffer. As part of the DMA operation, the I/O processor outputs the address in the index register onto the processors I/O address bus and applies the address to internal memory during each DMA cyclea clock cycle in which a DMA transfer is taking place.

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DMA ADDRESS GENERATOR (INTERNAL ADDRESSES)

PERIPHERAL CORE BUS

INTERNAL MEMORY ADDRESS

INDEX (ADDRESS)

MODIFIER

+/POST-MODIFY

DMA WORD COUNTER

PERIPHERAL CORE BUS

COUNT

CHAIN POINTER BUFFER

+
ZERO COUNT DETECTION CHAIN POINTER

MUX

DMA ADDRESS GENERATOR (EXTERNAL ADDRESSES)

EXTERNAL PORT CORE BUS

EXTERNAL MEMORY ADDRESS

EXTERNAL INDEX (ADDRESS)

EXTERNAL MODIFIER

EXTERNAL COUNT (IC ALIAS)

1 +
POST-MODIFY

Figure 3-1. DMA Address Generator Internal Index Register Addressing All addresses in the index registers are offset by a value matching the processors first internal normal word addressed RAM location, before the

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Functional Description

I/O processor uses the addresses. For the ADSP-214xx processors, this offset value is 0x0008 0000. This internal memory offset is not applicable for the index registers that correspond to SPORT DMAs as these registers are 28 bits. The following rules for data transfers must be followed. The DMA controller requires data transfers with an I/O of 32 bits. Therefore index addresses must always be normal word space. If the peripheral receives smaller I/O sizes, the peripheral packs data into a 32-bit data format (the peripherals include the SPORT, SPI, UART, AMI, and link port) with the help of shift registers. After transferring each data word to or from internal memory, the I/O processor adds the modify value to the index register to generate the address for the next DMA transfer and writes the modified index value to the index register. The modify value in the modify register is a signed integer, which allows both increment and decrement modifies. The modify value can have any positive or negative integer value. Note that: If the I/O processor modifies the internal index register past the maximum 19-bit value to indicate an address out of internal memory, the index wraps around to zero. With the offset for the SHARC processor, the wraparound address is 0x80000. If a DMA channel is disabled, the I/O processor does not service requests for that channel, whether or not the channel has data to transfer. with zero, If a program loads the count registerthat channel.the I/O processor does not disable DMA transfers on The I/O proces-

sor interprets the zero as a request for 216 transfers. This count occurs because the I/O processor starts the first transfer before testing the count value. To quickly disable a DMA channel, clear its channel DMA enable bit or write a 1 to the DMA word count register.

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External Index Register Addressing The external port DMA channels each contain additional parameter registers: the external index registers (EIEPx), external modify registers (EMEPx), and external count registers (ECEPx). The DMA controller generates 28-bit external memory addresses over the IOD1 bus using the EIEPx register during DMA transfers between internal memory and external memory. all SPORT DMA channels can Unlike previous SHARCs,the external memory space. This transfer data from the SPORTs to transfer uses the 28-bit IIxSPx register.

DMA Channel Status

There are two methods the processor uses to monitor the progress of DMA operations; interrupts, which are the primary method, and status polling. The same program can use either method for each DMA channel. The following sections describe both methods in detail. Programs can check the appropriate DMA status bits (for example the status bits in the SPMCTL register for the serial ports) to determine which channels are performing a DMA or chained DMA. All DMA channels can be active or inactive. If a channel is active, a DMA is in progress on that channel. The I/O processor indicates the active status by setting the channels bit in the status register. is cycle latency DMA Note that thereand1the status update inbetween a change inregister. channel status the corresponding
PCLK

The peripherals DMA controller tracks status information of the channels in each of the peripheral registers (for example SPMCTLx, SPIDMACx, DAI_STAT, DMACx, and MTMCTL). DMA channel status (status bit is set until the DMA terminates) TCB chain loading status (status bit is set until TCB loading completes)

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Functional Description

If polling the status of a chained DMA, the DMA status bit is first set when the TCB has terminated, then it is cleared. The TCB status loading bit is set until the load is finished and cleared on load completion. This procedure is repeated for all subsequent DMA blocks. Note that polling the DMA status registers (especially chained DMA) reduces I/O bandwidth.

DMA Bus Architecture

This section provides information on IOP bus architecture. The SHARC processor contains two independent 32-bit DMA buses (Figure 3-3 on page 3-37). The IOD0 bus is used for the peripherals to the internal memory and the IOD1 bus is used for external-to-internal memory transfers. The IOD0 bus is the path that the IOP uses to transfer data between internal memory and the peripherals. When there are two or more peripherals with active DMAs in progress, they may all require data to be moved to or from memory in the same cycle. For example, the SPI port may fill its buffer just as a SPORT shifts a word into its buffer. To determine which word is transferred first, the DMA channels for each of the processors I/O ports negotiate channel priority with the I/O processor using an internal DMA request/grant handshake. and buses operate independently. However, in The IOD0 thereIOD1be address conflicts if both buses access the some cases may same internal memory block. In this case, the IOD0 bus has first priority. Each I/O port has one or more DMA channels, and each channel has a single request and a single grant. When a particular channel needs to read or write data to internal memory, the channel asserts an internal DMA request. The I/O processor prioritizes the request with all other valid DMA requests. When a channel becomes the highest priority requester,

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I/O Processor

the I/O processor asserts the channels internal DMA grant. In the next clock cycle, the DMA transfer starts.

Standard DMA Start and Stop Conditions

A standard DMA sequence starts when chaining is disabled, and the DMA enable bit transitions from low to high. Once a program starts a DMA process, the process is influenced by DMA channel priority. A DMA sequence ends when one of the following occurs. The count register decrements to zero. Chaining is disabled and the channels DMA enable bit transitions from high to low. To abort a standard DMA, write a 1 directly to the DMA count register.

Operating Modes
The following sections provide information on the different operating modes supported through DMA.

Chained DMA
DMA data transfers can be set up as continuous or periodic. Furthermore, these DMA transfers can be configured to run automatically using chained DMA. With chained DMA, the attributes of a specific DMA are stored in internal memory and are referred to as a Transfer Control Block or TCB. The DMA controller loads these attributes in chains for execution. This allows for multiple chains that are an finite or infinite. a DMA channel, When chaining is enabled on status only becausepolling should not be used to determine channel the DMA appears inactive if it is sampled while the next TCB is loading. In such

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Operating Modes

cases where chaining is enabled, along with the polling of DMA status bit, polling of chaining status bit should also occur to so that the correct status of the DMA is known. For example, with an external port DMA with chaining enabled, the CHS bit should be polled as well as the DMAS and EXTS bits. TCB Memory Storage The location of the DMA parameters for the next sequence comes from the chain pointer register that points to the next set of DMA parameters stored in the processors internal memory. In chained DMA operations, the processor automatically initializes and then begins another DMA transfer when the current DMA transfer is complete. Each new set of parameters is stored in a user-initialized memory buffer or TCB for a chosen peripheral. Table 3-28 provides a brief description of the TCBs. The size of a varies and is the peripheral to the SPORTs,TCBports and SPIbased onfour locations, the be used: link require external port requires six to 13 locations, the accelerator five to 13 locations. Allowing different TCB sizes reduces the memory load since only the required TCBs are allocated in internal memory. Table 3-28. Principal TCB Allocation for a Serial Peripheral
Address CPx CPx + 0x1 (ICx) CPx + 0x2 (IMx) CPx + 0x3 (IIx) Register Chain pointer register Internal count register Internal modify register Internal index register Description Chain pointer for DMA chaining Length of internal buffer Stride for internal buffer Internal memory buffer

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Chain Assignment The structure of a TCB is conceptually the same as that of a traditional linked-list. Each TCB has several data values and a pointer to the next TCB. Further, the chain pointer of a TCB may point to itself to continuously re run the same DMA. The I/O processor reads each word of the TCB and loads it into the corresponding register. Programs must assign the TCB in memory in the order shown in Figure 3-2 and Listing 3-1, placing the index parameter at the address pointed to by the chain pointer register of the previous DMA operation of the chain. The end of the chain (no further TCBs are loaded) is indicated by a TCB with a chain pointer register value of zero. The address field of the chain pointer registers is only 19 bits wide. If a program writes a symbolic address to bit 19 of the chain pointer there may be a conflict with the PCI bit. Programs should clear the upper bits of the address then AND the PCI bit separately, if needed, as shown below.
T CB 1 CPx ICx IMx IIx T CB 2 CPx ICx IMx IIx If pointing to zero, chain operation ends

Figure 3-2. Chaining in the SPI and Serial Ports

Clear the chain pointer register before chaining is enabled.

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Operating Modes

Listing 3-1. Chain Assignment

R0=0; dm(CPx)=R0; /* clear CPx register */

/* init DMA control registers */ R2=(TCB1+3) & 0x7FFFF; R2=bset R2 by 19; dm(TCB2)=R2; R2=(TCB2+3) & 0x7FFFF; R2=bclr R2 by 19; dm(TCB1)=R2; dm(CPx)=R2; /* load IIx address of next TCB and mask address */ /* set PCI bit */ /* write address to CPx location of current TCB */ /* load IIx address of next TCB and mask address*/ /* clear PCI bit */ /* write address to CPx location of current TCB */ /* write IIx address of TCB1 to CPx register to start chaining*/

DMA operations occur within Chained processor does notmay only cross-channelthe same channel. The support chaining. Starting Chain Loading A DMA sequence is defined as the sum of the DMA transfers for a single channel, from when the parameter registers initialize to when the count register decrements to zero. Each DMA channel has a chaining enable bit (CHEN) in the corresponding control register. To start the chain, write the internal index address of the first TCB to the chain pointer register. When chaining is enabled, DMA transfers are initiated by writing a memory address to the chain pointer register. This is also an easy way to start a single DMA sequence, with no subsequent chained DMAs.

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During TCB chain loading, the I/O processor loads the DMA channel parameter registers with values retrieved from internal memory. starting chain loading, note that is When above. To execute the first DMAthe SPI portfor an exception to the in a chain this peripheral, the DMA parameter registers also need to be explicitly programmed. For more information, see DMA Transfers on page 16-24. The address in the chain pointer register points to the highest address of the TCB (containing the index parameter). This means that if a program declares an array to hold the TCB, the chain pointer register should point to the last location of the array and not to the first TCB location. Buffered Chain Loading Register The chain pointer register is buffered (see Figure 3-1 on page 3-27). Before the chain loading starts the buffer is copied into the chain pointer register and is decremented after each register is loaded. The chain pointer register can be loaded with a new address at any time during the DMA sequence (CHEN bit =1). This allows a DMA channel to have chaining status deactivated (chain pointer register = 0x0) until some event occurs that loads the chain pointer register with a non zero value. Writing all zeros to the address field of the chain pointer register also deactivates chaining for the next TCB. TCB Chain Loading Priority A TCB chain load request is prioritized like all DMA channels. Therefore, the TCB chain loading request has the same priority level as the DMA channel itself. The I/O processor latches a TCB loading request and holds it until the load request has the highest priority. If multiple chaining requests are present, the I/O processor services the TCB block for the highest priority DMA channel first.

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Operating Modes

that is in A channel any other the process of chain loading cannot be interrupted by request (TCB, DMA channel). The chain loading sequence is atomic and the I/O bus is locked until all the DMA parameter registers are loaded. For a list of DMA channels in priority order, see Table 3-29. Chain Insert Mode (SPORTs Only) It is possible to insert a single SPORT DMA operation or another DMA chain within an active SPORT DMA chain. Programs may need to perform insertion when a high priority DMA requires service and cannot wait for the current chain to finish. This is supported only for SPORT DMA channels. For more information, see Chapter 11, Serial Ports (SPORTs).

Peripheral DMA Arbitration

DMA bus arbitration is required to delegate a peripherals data stream over a common bus. DMA bus arbitration is a multistage process; peripheral needs to win multiple stages to finally get ownership of the DMA bus. Peripheral Group Stage 1 Arbitration The first arbitration stage (peripheral group arbitration) arbitrates between the peripherals themselves (SPORTs, IDP, MLB, UART, link port and external port DMA). The winning channel moves into the DMA bus arbitration (stage 2, Table 3-29 on page 3-39). group arbitration fixed or rotating (not The peripheralthe peripheral (withis one exception externaloptional) depending on port DMA channels) Figure 3-3 shows the arbitration schemes for the peripheral and external port DMA bus.

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INTERNAL MEMORY BLOCK INTERNAL MEMORY BLOCK

BLOCK ARBITER (FIXED)

BLOCK ARBITER (FIXED)

32-BIT PERIPHERAL DMA BUS ARBITER (FIXED/ROTATING DCPR BIT)

IOD0 BUS
BLOCK CONFLICT ACC IN

32-BIT EXTERNAL PORT DMA ARBITER (FIXED/ROTATE DMAPR BIT)

IOD1 BUS

IDP ARBITER (FIXED)

MLB ARBITER (ROTATE)

LP1/0 ARBITER (ROTATE)

UART0 ARBITER (FIXED)

SPORT1/0 ARBITER (FIXED)

SPORT5/4 ARBITER (FIXED) SPEP DMA ARBITER (FIXED/ROTATE DCPR BIT) EPDMA CH0 EPDMA CH1

SPI

SPIB

MTM RD

MTM WR

ACC OUT

SPORT3/2 ARBITER (FIXED)

SPORT7/6 ARBITER (FIXED)

EXTERNAL PORT ARBITER

(FIXED/ROTATE EPBR BIT)

Figure 3-3. Peripheral Arbitration Schemes

CORE 64-BIT AMI SDRAM DDR2

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EXTERNAL MEMORY BANKS

I/O Processor

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Operating Modes

Peripheral DMA Bus Stage 2 Arbitration When more than one of these peripheral groups requests access to the IOD0 bus in a clock cycle, the bus arbiter, which is attached to the IOD0 bus, determines which master should have access to the bus and grants the bus to that master. Peripheral DMA bus arbitration can be set to use either a fixed or rotating algorithm by setting or clearing DCPR bit in the SYSCTL register as follows. fixed arbitration (default) rotating arbitration In the fixed priority scheme (DCPR = 0), the lower indexed peripheral group has the highest priority as shown in Table 3-29. External Port DMA Arbitration Two peripheral groups and the core arbitrate for the external port bus: SPEP (SPORT/external port) DMA bus 32-bit External port DMA bus 32-bit Core bus 64-bit

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Table 3-29. Peripheral DMA Channel Priorities for SHARC Processors

Peripheral DMA Bus Arbiter Optional (Stage 2) A (highest) Peripheral Group Arbiter (Stage 1) Peripheral Control Registers Parameter Registers

0 (highest) 1 2 3 (lowest)

SPORT1A SPORT1B SPORT0A SPORT0B SPORT3A SPORT3B SPORT2A SPORT2B SPORT5A SPORT5B SPORT4A SPORT4B IDP0 IDP1 IDP2 IDP3 IDP4 IDP5 IDP6 IDP7 SPI

SPCTL5-0, SPMCTL5-0

IISP5-0A, IMSP5-0A, CSP5-0A, CPSP5-0A, IISP5-0B, IMSP5-0B, CSP5-0B, CPSP5-0B

0 (highest) 1 2 3 (lowest)

0 (highest) 1 2 3 (lowest)

0 (highest) 1 2 3 4 5 6 7 (lowest)

IDP_CTL2-0, IDP_PP_CTL

IDP_DMA_I7-0, IDP_DMA_M7-0, IDP_DMA_C7-0, IDP_DMA_I7-0A, IDP_DMA_I7-0B, IDP_DMA_PC7-0

SPICTL, SPIDMAC,

IISPI, IMSPI, CSPI, CPSPI

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Operating Modes

Table 3-29. Peripheral DMA Channel Priorities for SHARC Processors (Contd)
Peripheral DMA Bus Arbiter Optional (Stage 2) F Peripheral Group Arbiter (Stage 1) Peripheral Control Registers Parameter Registers

0-30 channels (rotating)

Media LB

MLB_CECR300

MLB_SBCR, MLB_ABCR, MLB_CBCR, MLB_CCBCR30-0, MLB_CNBCR30-0 IISPIB, IMSPIB, CSPIB, CPSPIB IIMTMW, IMMTMW, CMTMW IIMTMR, IMMTMR, CMTMR IIUART0RX, IMUART0RX, CUART0RX, CPUART0RX, IIUART0TX, IMUART0TX, CUART0TX, CPUART0TX, IILB1-0, IMLB1-0, ICLB1-0, CPLB1-0 IISP7-6A, IMSP7-6A, CSP7-6A, CPSP7-6A, IISP7-6B, IMSP7-6B, CSP7-6B, CPSP7-6B

G H I J 0 (highest) 1 (lowest) K 0 1 channel (rotating) 0 (highest) 1 2 3 (lowest)

SPIB MTMWR MTMRD UART0RX UART0TX LP0 LP1 SPORT7A SPORT7B SPORT6A SPORT6B

SPICTLB, SPIDMACB MTMCTL (or DTCP) MTMCTL (or DTCP) UART0RXCTL UART0TXCTL LCTL10

SPCTL7-6, SPMCTL7-6

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Table 3-29. Peripheral DMA Channel Priorities for SHARC Processors (Contd)
Peripheral DMA Bus Arbiter Optional (Stage 2) M Peripheral Group Arbiter (Stage 1) Peripheral Control Registers Parameter Registers

ACC IN

PMCTL1, FIRCTL1, FIRCTL2, IIRCTL1, IIRCTL2, FFTCTL1, FFTCTL2

IIFIR, IMFIR, ICFIR, IBFIR,CIFIR, CMFIR, CLFIR, CPFIR IIIIR, IMIIR, ICIIR, IBIIR,CIIIR, CMIIR, CLIIR, CPIIR IIFFT, IMFFT, ICFFT, IBFFT, CIFFT, CMFFT, CLFFT, CPIFFT

ACC OUT

OIFIR, OMFIR,OCFIR, OBFIR, COFIR, CMFIR,CLFIR, CPFIR OIIIR, OMIIR, OCIIR, OBIIR, COIIR, CMIIR, CLIIR, CPIIR OIFFT, OMFFT, OCFFT, OBFFT, COFFT, CMFFT, CLFFT, CPOFFT

External Port Group Stage 1 Arbitration External port DMA channels transfer data between internal memories or between internal and external memory over the IOD1 bus. When both external port channels request access to the IOD1 bus in a clock cycle, the external port bus arbiter, which is attached to the IOD1 bus, determines which master should have access to the bus and grants the bus to that master.

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Operating Modes

The external port channel arbitration can be set to use either a fixed or rotating algorithm by setting or clearing the DMAPR bits in the EPCTL register as follows. fixed arbitration channel 0 high rotating arbitration (default) SPORT/External Port Group Stage 2 Arbitration The data connection between the SPORT and the external port is performed over the SPEP (SPORT/external port) DMA bus. After the first arbitration stage in the SPORT group, the winning channels arbitrate for the external port bus. By default the SPORT0/1 group has highest priority and SPORT7/6 lowest priority. The arbitration of the SPEP bus can be set to use either a fixed or rotating mode by setting the DCPR bit in the SYSCTL register as follows. fixed arbitration (default) rotating arbitration

The

DCPR

bit controls arbitration on the peripheral and SPEP bus.

External Port DMA Bus Stage 3 Arbitration In the last stage the SPORT group, DMA group and the core arbitrate for the DMA bus. The arbitration can be set to use either a fixed or rotating algorithm by setting the EPBR bits in the EPCTL register as follows. Priority order from highest to lowest is SPORT, external port DMA, core. Priority order from highest to lowest is external port DMA, SPORT, core.

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Highest priority is core. SPORT and external port DMA are in rotating priority. Rotating priority (default). Table 3-30 shows the priority from highest to lowest SPORT, external port DMA and core (EPBR = 00). Table 3-30. External Port Bus Priorities for SHARC Processors (EPBR = 00)
External Port Bus Arbiter optional (Stage 3) A (highest) SPEP Group Arbiter optional (Stage 2) 0 (highest/ rotating) Peripheral Group Arbiter (Stage 1) 0 (highest) 1 2 3 (lowest 1 0 (highest) 1 2 3 (lowest 2 0 (highest) 1 2 3 (lowest D 3 0 (highest) 1 2 3 (lowest) Peripheral Control Registers Parameter Registers

SPORT1A SPORT1B SPORT0A SPORT0B SPORT3A SPORT3B SPORT2A SPORT2B SPORT5A SPORT5B SPORT4A SPORT4B SPORT7A SPORT7B SPORT6A SPORT6B

SPCTL7-0, SPMCTL7-0

IISP7-0A, IMSP7-0A, CSP7-0A, CPSP7-0A, IISP7-0B, IMSP7-0B, CSP7-0B, CPSP7-0B

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Interrupts

Table 3-30. External Port Bus Priorities for SHARC Processors (EPBR = 00) (Contd)
External Port Bus Arbiter optional (Stage 3) E SPEP Group Arbiter optional (Stage 2) Peripheral Group Arbiter (Stage 1) 0 (highest/ rotating) 1 (lowest) Peripheral Control Registers Parameter Registers

EPDMA0 EPDMA1

DMAC10

IIEP1-0, IMEP0, ICEP0, EIEP0, EMEP0, ELEP0, EBEP0, RIEP0, RCEP0, RMEP0, TCEP0, TPEP0, CPEP0

64-Bit Core

Fixed Versus Rotating Priority Programs can change DMA arbitration modes between fixed and rotate on the fly which incurs an effect latency of 2 PCLK cycles. Peripheral and External Port DMA Block Conflicts Note that if both DMA buses arbitrate for the same internal memory block (Figure 3-3 on page 3-37) the peripheral DMA always has a higher priority over the external port DMA bus. For more information refer to Memory chapter of ADSP-2136x Programming Reference Manual.

Interrupts
This section provides information on using interrupts. This information includes interrupt sources, masking and servicing.

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Sources
The information in this section is generic and provides a basic understanding of interrupt sources. For more information, see the Interrupts section of the specific peripheral. DMA Complete When a standard (single block) DMA process reaches completion (the DMA count decrements to zero) on any DMA channel, the interrupt controller latches that DMA channels interrupt. The next two sections describe the two types of interrupts that are used to signal interrupt completion. These are based on the type of peripheral used.
Internal Transfer Completion

This mode of interrupt generation resembles the traditional SHARC DMA interrupt generation. The interrupt is generated once the DMA internal transfers are complete, independent of whether the DMA is a transmit or receive. Therefore, when the completion interrupt is generated for external transmit DMAs, there may still be an external access pending at the external DMA interface. I/O processor when Thechannels countonly generates a DMAtocompletea interruptactual the register decrements zero as result of DMA transfers. Writing zero to a count register does not generate the interrupt. To stop a DMA preemptively, write a one to the count register. This causes one additional word to be transferred or received, and an interrupt is then generated.

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Interrupts

Access Completion

A DMA complete interrupt is generated when accesses are finished. For an external write DMA, the DMA complete interrupt is generated only after the external writes on the DMA external interface are complete. For an external read DMA, the interrupt is generated when the internal DMA writes are complete. In this mode the DMA interface can be disabled as soon as the interrupt is received. The access completion option is supported by the SPORTs, SPI, link ports and external port. Chained DMA Interrupts For chained DMA, the channel generates interrupts in one of two ways: 1. If PCI = 1, (bit 19 of the chain pointer register is the program controlled interrupts, or PCI bit) an interrupt occurs for each DMA in the chain. 2. If PCI = 0, an interrupt occurs at the end of a completed chain. For more information on DMA chaining, see Functional Description on page 3-23. Figure 3-4 shows the PCI timing during TCB loading. After the DMA count for the last word of frame N becomes zero, the PCI interrupt is latched. At the same time the DMA reloads the TCB for that specific channel (assuming no higher priority DMA requests). Finally the DMA channel resumes operation for frame N1. bit during By clearing a channels interrupt forchained DMA, programsa mask the DMA complete a DMA process within
PCI

chained DMA sequence.

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PCI INTERRUPT LATCHED FOR FRAME N

FRAME N

FRAME N-1

IOD BUS

DMA Count=1

DMA Count=0

DMA Channel TCB Loading

DMA Count=N

DMA Count=N-1

Figure 3-4. DMA Chaining

Masking
For information on interrupt masking, see the Masking section of the specific peripheral.

Service
For information on interrupt masking, see the Service section of the specific peripheral.

Interrupt Versus Channel Priorities

At their default setting shown in Table 3-31, the DMA interrupt priorities do not match the DMA channel priorities. However, if both priorities schemes should match, the DMA interrupt priorities can be re-assigned by dedicated settings of the PICRx registers. default for the external are two program At theirinterruptssettingand P13I) whichport thereagainst two mable (P9I arbitrate external port DMA channels.

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Effect Latency

Table 3-31. Default Channel vs. Interrupt Priorities (Peripheral DMA Bus)
Programmable Interrupt P0I P1I P3I P4I P5I P6I P7I P8I P11I P12I P14I P15I P16I P17I P18I Default Interrupt Priorities Priority DAIHI SPII SP1I SP3I SP5I SP0I SP2I SP4I SP7I DAILI DPII MTMI SP6I No default SPIBI Lowest SPORT76, 4 channels Accelerator (I/O), 2 channels UART0 2 channels MTM 2 channels SPI B 1 channel MLB 31 channels SPI 1 channel IDP70, 8 channels Highest Default DMA Channel Priority SPORT50, 12 channels

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference. 3-48 ADSP-214xx SHARC Processor Hardware Reference

I/O Processor

IOP Effect Latency

Table 3-32 lists the time required to load a specific TCB from the internal memory into the DMA controller. During this time, both buses (for a peripheral DMA, the IOD0 bus and for external port DMA the IOD1 bus) are locked and cannot be interrupted.

IOP Throughput
Since the I/O processor controls two I/O buses (peripheral and external port) the maximum bandwidth per IOD bus is gained for: Internal memory writes with fPCLK 32-bit Internal memory isolated reads with fPCLK/3 32-bit Internal memory back to back reads with fPCLK/2 32-bit Table 3-32. I/O Processor TCB Chain Loading Access
Chained TCB Type SPI DMA, SPORT DMA1, Link port DMA IIR Accelerator DMA coefficient2 IIR Accelerator DMA data2 External Port standard DMA, FFT Accelerator DMA, Delay Line DMA read External Port Circular Buffer DMA, Delay Line DMA write External Port Scatter/Gather DMA External Port Circular Buffer Scatter/Gather DMA FIR Accelerator DMA2 1 TCB Size Number of Core Cycles 4 5 10 6 7 8 10 13 26 22 40 34 40 42 50 94

If the TCB for a SPORT is located in external memory, additional access cycles are required for External Port arbitration and AMI or DDR2 cycles. 2 For throughput performance add 6 core cycles.

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Programming Model

Programming Model
This section provides a general procedure for configuring DMAs. There is more specific information on DMA in each peripheral chapter.

General Procedure for Configuring DMA

To configure the processors to use DMA, use the following general procedure. Note this is a generic model. For specific information refer to the individual programming model section in the peripheral specific chapter. 1. Clear all relevant registers (DMA/peripheral control, chain pointer). 2. Determine interaction method (enable IRQEN/IMASK setting or status polling). 3. Define the DMA channels interrupt priority (PICR registers). 4. Determine the DMA channel priority (fixed or rotating). 5. Determine the DMA address region for source and destination (index, modifier, count). 6. Determine the DMA transfer type (standard, chained, circular). 7. Set the DMA enabled bit/write index address of first TCB to the chain pointer register.

Debug Features
The JTAG interface provides some user debug features for DMA in that it allows programs to place breakpoints on the IOD buses. Programmers can then insert DMA related breakpoints. For more information, see the VisualDSP tools documentation and the SHARC Processor Programming Reference. 3-50 ADSP-214xx SHARC Processor Hardware Reference

I/O Processor

Emulation Considerations
An emulation halt will optionally stop the DMA engine. The JTAG interface provides some user debug features for DMA. Placing breakpoints on the IOD address buses allows DMA related breakpoints. For more information, see the VisualDSP tools documentation and the SHARC Processor Programming Reference.

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Debug Features

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The external memory interface provides a glueless interface to external memories. The asynchronous memory interface and the SDRAM/DDR2 memory that interfaces to the external port is clocked by the SDRAM or DDR2 clock. The interface specifications are shown in Table 4-1. Table 4-1. External Port Specifications
Feature AMI SDRAM Interface (ADSP-2147x and ADSP-2148x Processors) DDR2 Interface (ADSP-2146x Processor)

Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half-Duplex Transmission Full-Duplex Yes No Yes Yes No Yes No Yes Yes No Yes No Yes Yes No Yes (External Port) No N/A No N/A Yes Yes (External Port) No N/A No N/A Yes No No N/A No N/A Yes

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Features

Table 4-1. External Port Specifications (Contd)

Feature AMI SDRAM Interface (ADSP-2147x and ADSP-2148x Processors) DDR2 Interface (ADSP-2146x Processor)

Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Miscellaneous Clock Power Management Boot Capable Local Memory Max Clock Operation Yes Yes No SDCLK or DDR2CLK Yes No No SDCLK Yes No No DDR2CLK Yes Yes Yes 2 Yes Yes Yes Yes 2 Yes Yes Yes Yes 2 Yes

Features
The external port has the following features. Supports access to the external memory by core and DMA accesses. The external memory address space is divided into four banks. Any bank can be programmed as either asynchronous or synchronous memory. An asynchronous memory interface which communicates with SRAM, FLASH, and other devices that meet the standard asynchronous SRAM access protocol.

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External Port

A SDRAM controller (ADSP-2147x and ADSP-2148x processors) that supports a glue-less interface with any of the standard SDRAMs. A DDR2 controller (ADSP-21469 processor) that supports a glue-less interface with any of the standard DDR2. A 2-channel external port DMA which supports standard, circular, chained, scatter/gather and delay line operating modes for internal to external or internal to internal transfers and optional direction change on the fly. Arbitration logic to coordinate between SPORT, AMI, SDRAM/DDR2 transfers (core versus DMA) between internal and external memory over the external port. External port supports various ratios of core to external port clock determined by programming bits in the power management control registers (PMCTL). For more information, see Power Management Registers (PMCTL, PMCTL1) on page A-7.

Pin Descriptions
For the external port pin descriptions of the AMI and SDRAM/DDR2 interfaces, see the appropriate processor-specific data sheet.

Pin Multiplexing
The address data and memory select pins are multiplexed for the AMI and SDRAM controller of ADSP-2147x and ADSP-2148x processors. The ADSP-2146x processors have dedicated pins for the AMI and the DDR2 controller and therefor are not multiplexed.For more information on multiplexing schemes refer to Pin Multiplexing on page 24-28.

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Register Overview

Register Overview
This section provides brief descriptions of the major registers. For complete register information, see Appendix A, Register Reference.

External Port
External Port Control (EPCTL). This register enables the external banks for the SDRAM or the AMI. Moreover controls accesses between the processor core and DMA, and between different DMA channels. External Port DMA (DMAC10). DMA transfers between the internal and external memory space are controlled with these registers. For the corresponding DMA modes/parameter register information, see External Port DMA on page 4-120. Power Management Control (PMCTL). Controls the SDCLK to core clock ratio or DDR2CLK to core clock ratio related to the external port timing.

Asynchronous Memory Interface

AMI Control (AMICTLx). These registers control the mode of operations for the four banks of external memory. Note for all AMI timing bit settings, all defined cycles are derived from the SDRAM/DDR2 clock. AMI Status (AMISTAT). This 32-bit register provides status information for the AMI interface and can be read at any time.

SDRAM Controller
SDRAM Control (SDCTL). Configures various aspects of SDRAM operation. These are control clock operation, bank configuration, and

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External Port

SDRAM commands. Programmable parameters associated with the SDRAM access timing. SDRAM Control Status (SDSTATx). Provides information on the state of the controller. This information can be used to determine when it is safe to alter SDRAM control parameters or as a debug aid. SDRAM Refresh Rate Control (SDRRC). Provides a flexible mechanism for specifying auto-refresh timing.

DDR2 Controller
DDR2 Control 0 (DDR2CTL0). Contains the bits that control the DDR2 size, enables mode register and allows forcing of specific DDR2 commands. DDR2 Control 1 (DDR2CTL1). Includes the timing programmable parameters associated with the DDR2 access timing. All the values for this register are defined in terms of number of clock cycles from the DDR2 data sheet. DDR2 Control 2 (DDR2CTL2). Includes the programmable parameters associated to the burst type, burst length and CAS latency. DDR2 Control 35 (DDR2CTLx). Include the programmable parameters associated with the DDR2 extended mode registers 1 through 3. DDR2 Status (DDR2STAT10). Provide information on the state of the DDR controller. This information can be used to determine when it is safe to alter DDR control parameters or as a debug aid. DDR2 Refresh Control (DDR2RRC). Provides a programmable refresh counter which has a period based value which coordinates the supplied clock rate with the DDR2 device's required refresh rate. DDR2 DLL Control (DLL10CTL1). A built-in DLL in the DDR2 controller provides a 90 phase shifted clock to manage the data (DDR2_DATA)

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Clocking AMI/SDRAM (ADSP-2147x/ ADSP-2148x Models)

to data strobe (DDR2_DQS) timing relationships. For each data byte a control register is responsible. The bits are used to reset the DLL logic and to start a new DLL initialization. DDR2 DLL Status (DLL10STAT0). After the built-in DLL has started the bits return the status if the DLL has locked. A control register is responsible for each data byte. DDR2 Pad Control (DDR2PADCTL10). If the DDR2 interface is not used, these registers should be used to power-down the receiver pads for further power savings.

Shared DDR2 Memory

System Control (SYSCTL). Contains control bits for shared memory as Force synchronization and enable bus lock. System Status (SYSTAT). Returns the status of synchronized system and the current bus master. Bus Time-out Maximum, Bus Count (BMAX, BCOUNT). Contains counters which forces the current bus master to relinquish the bus if expired to guarantee a fair bus sharing.

Clocking AMI/SDRAM (ADSP-2147x/ ADSP-2148x Models)

The fundamental timing clock of the external port is SDRAM clock (SDCLK). The AMI/SDRAM controller is capable of running at up to 166 MHz for ADSP-2148x processors and 133 MHz for ADSP-2147x processors. The various possible AMI/SDRAM clock to core clock frequency ratios are shown in Table 4-2.

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SDRAM The clock ( clock ratio settings are independent from the peripheral ).
PCLK

Table 4-2. External Port Clock Frequencies

CCLK:SDCLK Clock Ratio 1:2.0 1:2.5 1:3.0 1:3.5 1:4.0 CCLK = 400 MHz N/A 160 133 114 100 CCLK = 333 MHz 166 133 111 95 83 CCLK = 266 MHz 133 106 88 76 66 CCLK = 200 MHz 100 80 67 57 50

For information on processor instruction rates, see the appropriate processor data sheets. certain higher To obtain to be reduced. SDRAM frequencies, the core frequency may need The external port and SDRAM clocks may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

Clocking AMI/DDR2 (ADSP-2146x Models)

The fundamental timing clock of the external port is DDR2 clock (DDR2_CLK). The AMI/DDR2 controller is capable of running up to core clock/2 speed (CCLK/2) and can run at various frequencies, depending on the programmed DDR2 clock (DDR2_CLK) to core clock (CCLK) ratios. For

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External Port Arbiter

information processor instruction rates, see the appropriate processor data sheet. DDR2 The clock ( clock ratio settings are independent from the peripheral ).
PCLK

The external port and DDR2 clocks may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

External Port Arbiter

The external port arbiter is a key component of the module. The arbiter performs the following functions. Controls the speed for the AMI SDRAM/DDR2 Controls the external banks individually Performs access arbitration for the processor core, AMI, SDRAM/DDR2 and SPORT access Allows channel freezing between core and DMA access to improve fairness of bus ownership

Functional Description
The external port has four ports for communication: Peripheral core bus for control of external port IOP registers External port core 64-bit bus for core access to external memory banks.

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External port DMA bus for transfers between the external port and internal memory. SPORT EP DMA bus for transfers between the external port and the SPORTs. Figure 4-1 shows a diagram of the external port for the ADSP-2147x and ADSP-2148x processors (containing a SDRAM interface).
EP CORE BUS 64 32 AMI CONTROLLER PERIPHERAL CORE BUS EXTERNAL PORT IOP REGISTER RD WR ACK

SPEP (SPORT) BUS

EXTERNAL PORT ARBITER DMA 0 SDRAM CONTROLLER DMA 1

ADDR DATA/MSx

IOD1 (EP) DMA BUS 32 DMA ARBITER

RAS CAS WE CKE CLK SDA10, DQM

Figure 4-1. Functional Block Diagram (ADSP-2147x and ADSP-2148x Processors) Figure 4-2 shows a diagram of the external port for the ADSP-2146x processor (containing a DDR2 interface). As shown in the figures, the external port is a fundamental block since every access in the external memory space is handled by this port. The AMI or the SDRAM/DDR2 controller modules act as peripherals to the external world and as such they are responsible for filling the buffers with data based on the protocol used. The external port also keeps track of the two DMA channels which can serve as data streams via the external and internal memory.

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External Port Arbiter

ACK
AMI PADS

EP CORE BUS 64 SPEP (SPORT) BUS 32 AMI ARBITER

AMI_MS AMI_WR AMI_RD AMI_ADDR AMI_DATA

AMI

PERIPHERAL CORE BUS

EXTERNAL PORT IOP REGISTER

DDR2_CLK0 DDR2_CLK0 DDR2_CLK1 DDR2_CLK1

DLL1

IOD1 (EP) DMA BUS 32 DMA ARBITER

DMA 0
DDR2 PADS

DDR2_CAS DDR2_RAS DDR2_WE DDR2_CKE 4 2 19 DDR2_ODT DDR2_CS DDR2_DM 2 2 16 DDR2_ADDR DDR2_DQS DDR2 _DQS DDR2_DATA BR ID

DDR2 ARBITER DMA 1

DDR2 CONTROLLER

SHARED MEMORY LOGIC

Figure 4-2. Functional Block Diagram (ADSP-2146x Processor)

Operating Mode
The following operation mode applies to the external port arbiter. Arbitration Modes Arbitration can be changed to be fixed or rotating (default). The SPORT/external port 32-bit DMA bus (SPEP) arbiter and the external port arbiter allow priority rule changes. For more information, see SPORT/External Port Group Stage 2 Arbitration on page 3-42. The external port uses a three stage arbitration process whereby all DMA requests need to pass through the first stage until one request wins. When

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DLL0

External Port

this occurs, the winning DMA channel needs to arbitrate with a SPORT DMA group (for example group A has four DMA channels SP1A/B, SP0A/B). The winning DMA channel then has a last arbitration process with the core where the following occurs. 1. External port DMA channels 0/1 rotating priority or high/low priorities. 2. Winning DMA channel arbitrating with SPORT DMA groups. 3. Winning DMA channel arbitrating with core access. In the EPCTL register, the EBPR and DMAPR bits define the priorities. All the bits of EPCTL register can be changed only when the external port is idle (when all DMA engines are idle and no core or SPORT access to external memory are pending). Arbitration Freezing Arbitration length freezing can be used to improve the throughput of read accesses by programming the various freeze bits of the EPCTL register. When multiple DMA channels are reading data from SDRAM/DDR2 memory, channel freezing can improve the data throughput. By setting the freeze bits (FRZDMA, FRZCR, and FRZSP), each channel request is frozen for programmed accesses. For example, if the processor core is frozen for 32 accesses, and if the core requests 32 accesses to SDRAM/DDR2 sequentially, data throughput improves. Freezing is based on the fact that sequential accesses to the SDRAM/DDR2 provide better throughput than non-sequential accesses. The arbiter also allows core or DMA access freeze which helps to balance out system performance.

Channel freezing has no effect on write accesses.

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Asynchronous Memory Interface

Asynchronous Memory Interface

The asynchronous memory interface (AMI) is described in the following sections.

Features
The AMI has the following features and capabilities. User defined combinations of programmable wait states. External hardware acknowledge signals. Data packing support for 8 and 16 bits (ADSP-2147x and ADSP-2148x). External instruction fetch from 8 and 16 bits (16 bits for ADSP-2147x and ADSP-2148x). Both the processor core and the I/O processor have access to external memory using the AMI. Support a glueless interface with any of the standard SRAMs. Bank 0 can accommodate up to 6M words, and banks 1, 2, and 3 can accommodate up to 8M words each (ADSP-2147x and ADSP-2148x). Bank 0 can accommodate up to 2M words, and banks 1, 2, and 3 can accommodate up to 4M words each (ADSP-2146x).

Functional Description
The following sections provide a functional overview of the asynchronous memory interface.

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The AMI communicates with SRAM, FLASH and any other memory device that conforms to its protocol. It provides a DMA interface between internal memory and external memory, performs instruction (48-bit) fetch from external memory, and directs core access to external memory locations. The AMI on the ADSP-2147x and ADSP-2148x supports 8- and 16-bit data access to external memory. The external interface follows standard asynchronous SRAM access protocol. The programmable wait states, hold cycle and idle cycles are provided to interface memories of different access times. To extend access the ACK signal can be pulled low by the external device as an alternative to using wait states. AMI memory space with the For ADSP-2146x products, writing0,tothe write is postponed until bit in the register =
AMIEN AMICTLx

the AMI controller is enabled (AMIEN bit = 1). However, once this occurs, the AMI address pins and the WR strobe start to toggle uncontrollably, causing the AMI to fail. Therefore, programs must enable the AMI (AMIEN bit = 1) prior to allowing any writes. Parameter Timing This section describes the programmable timing parameters for the AMI which include wait states for idle or hold cycles. Programmable timing allows the interface to be flexible and efficient regardless of whether the data transfers are being run from the core or from DMA or regardless of the sequence of transactions (read followed by read, read followed by write, and so on). The bits used to set programmable timing for the AMI are located in AMI Control Registers (AMICTLx) on page A-27.

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Asynchronous Memory Interface

Asynchronous Reads

Figure 4-3 shows an asynchronous read bus cycle. Asynchronous read bus cycles proceed as follows. 1. At the start of the setup period, MSx and AMI_RD assert. The address bus becomes valid. 2. At the beginning of the read access period and after the 3rd cycles, AMI_RD deasserts. 3. At the beginning of the hold period, read data is sampled on the rising edge of the SDCLK clock. 4. At the end of the hold period, some IDLE cycles happened in the case the read is followed by a write. Also, MSx deasserts unless the next cycle is to the same memory bank.
READ STROBE SETUP 1 CYCLE AMI_ADDR AMI_MSx READ WAIT STATES (WS) READ HOLD WAIT STATES (HC)

AMI_RD

AMI_DATA STROBE SETUP FOR ACK

AMI_ACK

ADDRESS SETUP FOR ACK

Figure 4-3. AMI Asynchronous Reads

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Asynchronous Writes

Figure 4-4 shows an asynchronous write bus cycle. Asynchronous write bus cycles proceed as follows. 1. At the start of the setup period, MSx, the address bus, data buses, become valid. 2. At the beginning of the write access period, WR asserts. 3. At the beginning of the hold period, WR deasserts. 4. One hold cycle is introduced before next access can happen. Also, MSx deasserts unless the next cycle is to the same memory bank.
STROBE SETUP 1 CYCLE AMI_ADDR AMI_MSx WRITE WAIT STATES (WS) WRITE HOLD CYCLES (H)

AMI_WR

AMI_DATA STROBE SETUP ACK ADDRESS SETUP ACK AMI_ACK

Figure 4-4. AMI Asynchronous Writes

Idle Cycles

An idle cycle is inserted by default for an AMI read followed by write or a read followed by a read from a different bank or a read followed by an external access by another device in order to avoid data bus driver conflicts.

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Asynchronous Memory Interface

If an idle cycle is programmed for a particular bank, then a minimum of 1 idle cycle is inserted for reads even if they are from the same bank. In order to achieve better read throughput, an idle cycle should be set to 0. For more information refer to the product specific data sheet.
Wait States

Wait states and acknowledge signals are used to allow the processors to connect to memory-mapped peripherals and slower memories. Wait states are programmable from 1 to 31.
Hold Cycles

A bus hold cycle is an inactive bus cycle that the processor automatically generates at the end of a write to allow a longer hold time for address and data. Programs may disable holds, or hold off processing for one or more external port processor cycles. Note the address, data (if a write), and bank select (if in banked external memory) remain unchanged and are driven for one or more cycles after the read or write strobes are deasserted.
Data Storage and Packing

The processors have the ability to use logical addressing when an external memory smaller than 32 bits is used. When logical addresses are used, multiple external addresses seen by the memory correspond to a single internal address, depending on the width of the memory being accessed, and the packing mode setting of the AMI controller. The external physical address map is shown in Table 4-3. For an external bus width of 8 bits with packing enabled (PKDIS = 0), the external physical address ADDR230 generation is ADDR232 = bits 210 in the address being supplied to the external port by the core or DMA controller. Here, ADDR10 corresponds to the 1st/2nd/3rd/4th 8-bit word.

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Table 4-3. AMI Address Memory Map

Bus Width External Memory Bank Internal Logical Address (supported memory map) External Physical Address (on ADDR230)

ADSP-2146x/ADSP-2147x/ADSP-2148x 8-bit (and PKDIS = 0) 8-bit (and PKDIS = 0) 0 1, 2, 3 0x0020_0000 0x003F_FFFF 0x0400_0000 0x043F_FFFF 0x0800_0000 0x083F_FFFF 0x0C00_0000 0x0C3F_FFFF 0x80_0000 0xFF_FFFF 0x00_0000 0xFF_FFFF

ADSP-2147x/ADSP-2148x 16-bit (and PKDIS = 0) 16-bit (and PKDIS = 0) 0 1, 2, 3 0x0020_0000 0x007F_FFFF 0x0400_0000 0x047F_FFFF 0x0800_0000 0x087F_FFFF 0x0C00_0000 0x0C7F_FFFF 0x40_0000 0xFF_FFFF 0x00_0000 0xFF_FFFF

External Instruction Fetch

The processors support direct fetch of ISA instructions from external memory, using the 8/16-bit external port. Fetching is supported from external memory space bank 0 which is selected by MS0. This external memory can either be asynchronous memory, such as SRAM or flash. Interrupt Vector Table (IVT) The interrupt vector table can be located in the internal ROM (0x80 000, IIVT bit = 0) or internal RAM (0x8C 000, IIVT bit = 1) based on the selected boot mode. However for all boot modes except the reserved boot mode, the default IIVT bit setting is 1 (SYSCTL). Therefore, if instruction fetch from external memory is desired at reset, the program needs to set up the appropriate interrupt vector tables in internal memory as part of the boot-up code before beginning to fetch these instructions. ADSP-214xx SHARC Processor Hardware Reference 4-17

Asynchronous Memory Interface

When an unmasked interrupt occurs and is serviced, program execution automatically jumps to the location of the corresponding interrupt vector table in internal memory. Upon returning from the interrupt, the sequencer resumes fetching instructions from external memory because locating the IVT in external memory is not supported. Instruction Packing Any address produced by the sequencer which falls in external memory is first translated into the physical address in external memory based on the actual data bus width of external memory as shown in Figure 4-5. The controller completes the required number of accesses from consecutive locations for returning a 48-bit word instructions.

Only bank0 can be populated for external instruction fetch.

EXTERNAL PORT
MS0 CS

Logical ADDR ISA Sequencer Instructions 48-bit

Address Translator

Physical ADDR [23:0]

External Memory

Instruction Packing 16/48 8/48

SRAM Packed Instructions (8/16-bit)

Figure 4-5. Logical Versus Physical Addresses External Instruction Fetch from AMI Boot Space External instruction fetch (ISA) from boot prom is useful if functions are only executed once (runtime environment, routing for example) and performance is not a primary concern. This type of instruction fetch helps to reduce the internal memory load.

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For systems that boot and fetch instructions from a boot PROM, additional external logic is required. For AMI boot the processor asserts the MS1 memory chip select only, and for external instruction fetch it asserts the MS0 memory chip select only. Therefore both memory selects need to be combined to assert the memory select for both cases. 8-Bit Instruction Storage and Packing For packed 8-bit instructions the controller performs six required accesses from consecutive locations for returning a 48-bit word instruction. In Table 4-4, the logical to physical translation is a multiplication by a factor of 6 and N = 0xAAAA9. Therefore, the 8-bit wide AMI supports 0.7 million instructions. Table 4-4. Logical Versus Physical Address Mapping, 8-Bit AMI
Logical ISA Normal Word Physical Address, External Bus Address, Program Sequencer 0x20 0000 0xC0 0000 0xC0 0001 0xC0 0002 0xC0 0003 0xC0 0004 0xC0 0005 0x20 0001 0xC0 0006 0xC0 0007 0xC0 0008 0xC0 0009 0xC0 000A 0xC0 000B ... ... Data 70 Instr0[7:0] Instr0[15:8] Instr0[23:16] Instr0[31:24] Instr0[39:32] Instr0[47:40] Instr1[7:0] Instr1[15:8] Instr1[23:16] Instr1[31:24] Instr1[39:32] Instr1[47:40]

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Asynchronous Memory Interface

Table 4-4. Logical Versus Physical Address Mapping, 8-Bit AMI (Contd)
Logical ISA Normal Word Physical Address, External Bus Address, Program Sequencer 0x2A AAA9 0xFF FFFA 0xFF FFFB 0xFF FFFC 0xFF FFFD 0xFF FFFE 0xFF FFFF Data 70 InstrN[7:0] InstrN[15:8] InstrN[23:16] InstrN[31:24] InstrN[39:32] InstrN[47:40]

16-Bit Instruction Storage and Packing For packed 16-bit instructions the controller performs three required accesses from consecutive locations for returning a 48-bit word instruction. In Table 4-5 the logical to physical translation is a multiplication by a factor of 3 and N = 0x355554. Therefore, the 16-bit wide AMI memory supports 3.3 million instructions. Table 4-5. Logical Versus Physical Address Mapping, 16-Bit AMI
Logical ISA Normal Word Physical Address, External Bus Address, Program Sequencer 0x20 0000 0x60 0000 0x60 0001 0x60 0002 0x20 0001 0x60 0003 0x60 0004 0x60 0005 Data 150 Instr0[15:0] Instr0[31:16] Instr0[47:32] Instr1[15:0] Instr1[31:16] Instr1[47:32]

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Table 4-5. Logical Versus Physical Address Mapping, 16-Bit AMI (Contd)
Logical ISA Normal Word Physical Address, External Bus Address, Program Sequencer 0x20 0002 0x60 0006 0x60 0007 0x60 0008 ... 0x55 5554 ... 0xFF FFFD 0xFF FFFE 0xFF FFFF InstrN[15:0] InstrN[31:16] InstrN[47:32] Data 150 Instr2[15:0] Instr2[31:16] Instr2[47:32]

Mixing Instructions and Data in External Bank 0 It is possible to store both 48-bit instructions as well as 16-bit data in external memory bank 0. However, care must be taken while specifying the proper starting addresses if 48-bit instructions are stored or interleaved with 16-bit data in the same memory bank. In 16-bit wide external SRAM memory, one instruction is packed into three 16-bit memory locations, while 32-bit data occupies two memory locations. For example, if 2k instructions are placed in 16-bit wide SRAM memory starting at the bank 0 (logical address 0x0020 0000 corresponding to physical address 0x0060 0000) and ending at logical address 0x002007FF (corresponding to physical address 0x0060 17FF), then data buffers can be placed starting at an address that is offset by 3k 16-bit words (for example, starting at 0x0060 1800).

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Asynchronous Memory Interface

Cache for External Instruction Fetch

To circumvent the relative difference in clock domains between the core and external memory interface (1:2 in the best case) and enable faster execution throughput, the functionality of the traditional conflict cache on the SHARC has been enhanced to serve as an instruction cache in external instruction fetch operations. In previous generations of SHARC processors, the function of the conflict cache had been to cache only those instructions whose fetching conflicted with access of a data operand from memory over the PM bus. The enhancements to the cache architecture mean that the functionality of the cache remains intact for execution from internal memory whereas it behaves as instruction cache for external memory execution. is Every instruction thatalsofetched from external memory into the program sequencer is simultaneously loaded into the cache. The next time that this instruction needs to be fetched from external memory, it is first searched for in the cache. The instruction is stored using the entire 24-bit address. Figure 4-6 shows the format for storing an instruction. In other words, the 32-entry 2-way set-associative cache in the SHARC has been modified to act as an instruction cache when the program sequencer executes instructions from external memory, while continuing to work as the traditional conflict cache when the sequencer executes instructions located in internal memory. This context switching from conflict cache to instruction cache and vice-versa happens automatically without the need for any user intervention. The first time that an instruction from a particular address is fetched from external memory, there is a cache miss when the sequencer looks for this instruction within the cache. Consequently, the instruction has to be fetched from external memory and a copy of instruction is stored in cache. Upon subsequent executions of this instruction, the sequencer search results in a cache hit, resulting in the instruction being fetched from cache 4-22 ADSP-214xx SHARC Processor Hardware Reference

External Port

LRU VALID BIT BIT SET 0 SET 1 SET 2 ENTRY 0 ENTRY 1 ENTRY 0 ENTRY 1 ENTRY 0 ENTRY 1

INSTRUCTIONS

ADDRESSES BITS (23-4)

ADDRESSES BITS (3-0) 0000

0001

0010

SET 13 SET 14 SET 15

ENTRY 0 ENTRY 1 ENTRY 0 ENTRY 1 ENTRY 0 ENTRY 1

1101

1110

1111

Figure 4-6. Instruction Cache Architecture instead of external memory. This allows for an instruction throughput that is equivalent to internal memory execution. This context-dependent caching preserves the cache performance of the traditional SHARC conflict cache as well as significantly improving program instruction throughput for repetitive instructions such as those inside loops when executing from external memory. Analyses of typical application code examples have shown that this 32-entry instruction cache improves execution throughput by 50-80% over not having this cache. In general, cache hits occur for all instructions which are fetched and executed multiple times (for example loops, subroutine calls, negative branches, and so on). Typical applications, such as signal processing algorithms, are ideal candidates for significant performance improvements as a result of the cache. An important and significant result of the instruction being fetched from the cache is that it frees up the external port as well as the internal PM and ADSP-214xx SHARC Processor Hardware Reference 4-23

Asynchronous Memory Interface

DM buses for other operations such as data transfers, operand fetches, or DMA transfers. The following example shows the innermost loop of a FIR filter.
lcntr=FILTER_TAPS-1, do macloop until lce; macloop: f12=f0*f4, f8=f8+f12, f0=dm(i0,m1), f4=pm(i9,m9);

In this example, if the code is stored and executed from external memory, the first time through this loop the program sequencer places the appropriate 24-bit address on the external address bus, and fetches the instruction in line 2 from external memory. While this instruction is being fetched and processed by the sequencer, it is also simultaneously stored in the internal instruction cache. For every subsequent iteration of this loop, the instruction is fetched from the internal cache, thereby occurring in a single cycle, while freeing up the internal memory buses to fetch the data operands required for the instruction. Previously, in the absence of the internal instruction cache, the number of cycles taken by the loop for a case of FILTER_TAPS = 16 would have been a minimum of 96 cycles over an 8-bit wide external bus (excluding any conflicts for data operand fetches). However, with the presence of the instruction cache, and assuming that the execution is from external AMI, the number of cycles is reduced to 17 core clock cycles over an 8-bit wide external bus. expected, it important As might bedoes not play is significant to remember that the instruction cache a role in improving the efficiency of strictly linearly executed code from external memory.

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Operating Modes
The AMI operating modes are described in the following sections. Data Packing The combination of the (PKDIS) and (MSWF) bits allow combinations of packing for 8/16 to 32 bits. These modes are summarized in Table 4-6. Table 4-6. Data Packing Bit Settings (PKDIS)
Packing Mode Enabled PKDIS Bit MSWF Bit Description Setting Setting 0 0 8- or 16-bit received data is packed to 32-bit data and transmitted 32-bit data is unpacked to 2 16-bit data or 4 8-bit data. First 8- or 16-bit word read/written occupies the least significant position in the 32-bit packed word. 8- or 16-bit received data is packed to 32-bit data and 32-bit data to be transmitted is unpacked to 2 16-bit data or 4 8-bit data. First 8- or 16-bit word read/written occupies the most significant position in the 32-bit packed word. 8- or 16-bit data received is zero filled. For transmitted data only 16-bit or the 8-bit LSB part of the 32-bit data word is written to external memory.

Enabled

Disabled

N/A

External Access Extension The AMI controller has an ACK Pin which can be used for external access extension. When ACK is enabled, the wait state value should be set to indicate when the processor can sample ACK after the AMI_RD/AMI_WR edge goes low (refer to Figure 4-3 and Figure 4-4). If ACK is not enabled, the minimum value for WS is 2 (a wait state value of 0 corresponds to 32 wait cycles). If ACK is enabled, the minimum allowed value for WS is 1. When ACK is enabled (ACKEN = 1), the processor samples the ACK signal after two wait states plus the expiration of the wait state count

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Asynchronous Memory Interface

programmed in the AMICTLx register. It is imperative that the WS value is initialized when the acknowledge enable bit (ACKEN) is set. Predictive Reads The AMI controller allows two types of read access: predictive reads (default) non predictive reads Predictive read (PREDIS bit = 0) reduces the time delay between two reads. The predictive address is generated and compared with the actual address. If they do not match, then that read data is ignored. Every last read access is therefore a duplication of the 2nd to last read with the same address. Note that this redundant read does not update the memory location. In contrast, when no predictive read (PREDIS bit = 1) is used, the delay between two reads increases. Note that both DMA and the processor core have predictive read capability. Further note that the PREDIS bit should not be changed when the AMI is performing an access. Disabling predictive reads reduces peripheral performance. If an access to an external FIFO is required at maximum speed, programs can also clear PREDIS (=0). The last access before a non AMI access should be a dummy AMI write access. This ensures that the last predictive read is omitted.

The

PREDIS

AMICTLx

bit (bit 21) is a global bit that when set in any of the registers provides access to all memory banks.

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SDRAM Controller (ADSP-2147x/ADSP-2148x)

The SHARC processors support a glueless interface with any of the standard SDRAMs.

Features
The SDRAM controller can support up to 254M words of SDRAM in four banks. Bank 0 can accommodate up to 62M words, and banks 1, 2, and 3 can accommodate up to 64M words each. The interface has the following additional features. I/O width 16-bits Types of 32, 64, 128, 256, and 512M bit with I/O of x4, x8, and x16 Page sizes of 128, 256, 512, 1k, 2k words Variable memory address map (bank or page interleaving) Supports up to 254M words of SDRAM memory No-burst mode (BL = 1) with sequential burst type Open page policyany open page is closed only if a new access in another page of the same bank occurs Supports multibank operation within the SDRAM Uses a programmable refresh counter to coordinate between varying clock frequencies and the SDRAMs required refresh rate Provides multiple timing options to support additional buffers between the processor and SDRAM

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SDRAM Controller (ADSP-2147x/ADSP-2148x)

Allows independent auto-refresh while the asynchronous memory interface (AMI) has control of the external port Supports self-refresh mode for power savings Predictive data accesses for higher read data throughput (read optimization) Supports external instruction fetch in bank 0 for ISA and VISA operation Supports 64-bit SIMD mode by the core Supports dual data instruction type 1

Pin Descriptions
The pins used by the external memory interface are described in the ADSP-2147x SHARC Processor Data Sheet and the ADSP-2148x SHARC Processor Data Sheet. Additional information on pin multiplexing can be found in Pin Descriptions on page 24-2.

Functional Description
The SDRAM control signals (MSx, SDCKE, SDRAS, SDCAS, SDWE, SDA10) define various operation modes to the SDRAM. Table 4-7 provides a reference to these commands and the pin state for each one. The configuration is programmed in the SDCTL register. The SDRAM controller can hold off the processor core or DMA controller with an internally connected acknowledge signal, as controlled by refresh, or page miss latency overhead. A programmable refresh counter is provided which generates background auto-refresh cycles at the required refresh rate based on the clock frequency used. The refresh counter period is specified with the RDIV field in the SDRAM refresh rate control register (Refresh Rate Control Register 4-28 ADSP-214xx SHARC Processor Hardware Reference

External Port

(SDRRC) on page A-36). The internal 32-bit non-multiplexed address is multiplexed into: SDRAM column address SDRAM row address Internal SDRAM bank address Based on the addressing mapping bit (ADDRMODE = 0) the lowest bits are mapped into the column address, next bits are mapped into the row address, and the final two bits are mapped into the internal bank address. If ADDRMODE = 1 the lowest bits are mapped into the column address, next bits are mapped into the internal bank address and the final bits are mapped into the row address. This mapping is based on the SDCAW and SDRAW values programmed into the SDRAM control register. The controller uses no burst mode (BL = 1) for read and write operations. This requires the controller to post every read or write address on the bus as for non-sequential reads or writes, but does not cause any performance degradation. For read commands, there is a latency from the start of the read command to the availability of data from the SDRAM, equal to the CAS latency. This latency is always present for any single read transfer. Subsequent reads with optimization enabled do not have any latency. SDRAM Commands This section provides a description of each of the commands that the controller uses to manage the SDRAM interface. These commands are handled automatically by the controller. A summary of the various commands used by the on-chip controller for the SDRAM interface follows and is shown in Table 4-7 on page 4-35.

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Load mode registerinitializes the SDRAM operation parameters during the power-up sequence. Single prechargecloses a specific internal bank depending on user code. Precharge allcloses all internal banks, preceding any auto-refresh command. Activateactivates a page in the required internal SDRAM bank Read/write Auto-refreshcauses the SDRAM to execute an internal CAS before RAS refresh. Self-refresh entryplaces the SDRAM in self-refresh mode, in which the SDRAM powers down and controls its refresh operations internally. Self-refresh exitexits from self-refresh mode by expecting auto-refresh commands from controller. NOP/command inhibitno operation used to insert wait states for activate and precharge cycles
Load Mode Register

This command initializes SDRAM operation parameters. It is a part of the SDRAM power-up sequence. Load mode register uses the address bus of the SDRAM as data input. The power-up sequence is enabled by writing 1 to the SDPSS bit in the SDCTL register, subsequent SDRAM accesses initiate the power-up sequence. The exact order of the power-up sequence is determined by the SDPM bit of the SDCTL register.

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The load mode register command initializes the following parameters. Burst length = 1, bits 20, always zero Wrap type = sequential, bit 3, always zero Ltmode = latency mode (CAS latency), bits 64, programmable in the SDCTL register Bits 147, always zero While executing the load mode register command, the unused address pins are set to zero. During the first SDCLK cycle following load mode register, the controller issues only NOP commands to satisfy the tMRD specification.
Bank Activation

The bank activation command is required for first access to any internal bank in SDRAM. This command open a row in the particular bank for the subsequent access. The value on the ADDR1817 pins selects the bank. And the address provided on the ADDR150 pins selects the row. This row remains open for access until a single precharge command is issued to that bank. The single precharge command must be issued before opening a different row in the same bank.
Single Precharge

For a page miss during reads or writes in any specific internal SDRAM bank, the controller uses the single precharge command to close that bank. All other internal banks are untouched.
Precharge All

The precharge all command is given to precharge all internal banks at the same time before executing an auto-refresh. All open banks are automatically closed. This is possible since the controller uses a separate SDA10 pin

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which is asserted high during this command. This command precedes the auto-refresh command.
Read/Write

This command is executed if the next read/write access is in the present active page. During the read command, the SDRAM latches the column address. The delay between activate and read commands is determined by the tRCD parameter. Data is available from the SDRAM after the CAS latency has been met. In the write command, the SDRAM latches the column address. The write data is also valid in the same cycle. The delay between activate and write commands is determined by the tRCD parameter. The controller does not use the auto-precharge function of SDRAMs, which is enabled by asserting SDA10 high during a read or write command. Figure 4-7 and Figure 4-8 show the SDRAM write and read timing of the processors.

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SDCLK

COMMAND

ACT

NOP

WR

WR

WR

WR

NOP

PRE

NOP

ACT

ADDR

ROW

COL

COL

COL

COL

ROW

BA[1:0]

DATA tRCD

tWR tRAS tRC tRP

Figure 4-7. Write Timing Diagram

SDCLK

COMMAND

ACT

NOP

RD

RD

NOP

NOP

NOP

PRE

NOP

ACT

ADDR

ROW

COL

COL

ROW

BA[1:0]

DATA tRCD tRAS tRC CL

tRP

Figure 4-8. Read Timing Diagram

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Auto-Refresh

The SDRAM internally increments the refresh address counter and causes a CAS before RAS (CBR) refresh to occur internally for that address when the auto-refresh command is given. The controller generates an auto-refresh command after the controller refresh counter times out. The RDIV value in the SDRAM refresh rate control register (SDRRC) must be set so that all addresses are refreshed within the tREF period specified in the SDRAM timing specifications. Before executing the auto-refresh command, the controller executes a precharge all command to all external banks. The next activate command is not given until the tRFC specification (tRFC = tRAS + tRP) is met. Auto-refresh commands are also issued by the controller as part of the power-up sequence and after exiting self-refresh mode.
No Operation/Command Inhibit

The no operation (NOP) command to the SDRAM has no effect on operations currently in progress. The command inhibit command is the same as a NOP command; however, the SDRAM is not chip-selected. When the controller is actively accessing the SDRAM, but needs to insert additional commands with no effect, the NOP command is given. When the controller is not accessing any SDRAM external banks, the command inhibit command is given.
Command Truth Table

Table 4-7 provides the bit states of the SDRAM for specific SDRAM commands. Note that an X means do not care.

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Table 4-7. SDRAM Pin States During SDRAM Commands

Command Mode register set Activate Read Single Precharge Precharge all Write Auto-refresh Self-refresh entry Self-refresh Self-refresh exit Nop Inhibit SDCKE (n1) 1 1 1 1 1 1 1 1 0 0 1 1 SDCKE (n) 1 1 1 1 1 1 1 0 0 1 1 1 MS30 0 0 0 0 0 0 0 0 X 1 0 1 SDRAS 0 0 1 0 0 1 0 0 X X 1 X SDCAS 0 1 0 1 1 0 0 0 X X 1 X SDWE 0 1 1 0 0 0 1 1 X X 1 X SDA10 Opcode Valid 0 0 1 0 X X X X X X Addresses Opcode Valid Valid Valid X Valid X X X X X X

Refresh Rate Control The SDRAM refresh rate control register provides a flexible mechanism for specifying auto-refresh timing. The controller provides a programmable refresh counter which has a period based on the value programmed into the lower 12 bits of this register. This coordinates the supplied clock rate with the SDRAM devices required refresh rate. The delay (in number of SDCLK cycles) between consecutive refresh counter time-outs must be written to the RDIV field. A refresh counter time-out triggers an auto-refresh command to the external SDRAM bank. Programs should write the RDIV value to the SDRRC register before the SDRAM

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SDRAM Controller (ADSP-2147x/ADSP-2148x)

power-up sequence is triggered. Change this value only when the controller is idle as indicated in the SDSTAT register. To calculate the value to write to the SDRRC register, use the following equation. RDIV = (SDCLK tREFI) (tRAS + tRP) where: Where: SDCLK = SDRAM system clock frequency tREFI = SDRAM maximum average auto refresh period (in s). (Note tREFI = tREF/Number of row addresses) tRAS = Active to precharge time ( SDRAS bit in the SDCTL register) in number of clock cycles tRP = RAS to precharge time (SDRP bit in the SDCTL register) in number of clock cycles This equation calculates the number of clock cycles between required refreshes and subtracts the required delay between bank activate commands to the same bank (tRC = tRAS + tRP). The tRC value is subtracted, so that in the case where a refresh time-out occurs while an SDRAM cycle is active, the SDRAM refresh rate specification is guaranteed to be met. The result from the equation is always rounded down to an integer. Below is an example of the calculation of RDIV for a typical SDRAM in a system with a 133 MHz SDRAM clock. 6 3 133 ( 10 ) 64 ( 10 ) RDIV = ------------------------------------------------------------------- ( 6 + 3 ) = 1030 8192 fSDCLK = 133 MHz tREF = 64 ms NRA = 8192 row addresses 4-36 ADSP-214xx SHARC Processor Hardware Reference

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tRAS = 6 tRP = 3 This means RDIV is 0x406 (hex) and the SDRAM refresh rate control register is written with 0x406. The RDIV value must be programmed to a nonzero value if the SDRAM controller is enabled. When RDIV = 0, operation of the SDRAM controller is not supported and can produce undesirable behavior. SDRAM separate Someactive time vendors userow refreshtiming(tspecifications for the time ). The controller row (t ) and ignores the tRFC spec. For auto-refresh, it uses the equation tRC = tRAS + tRP. However since both timing specifications must meet (especially for extended temperature range) the modification of the tRAS specification resolves the timing equation without performance degradation (tRFC = tRAS + tRP). Internal SDRAM Bank Access The following sections describe the different scenarios for SDRAM bank access.
Single Bank Access
RC RFC

The controller keeps only one page open at a time if all subsequent accesses are to the same row or another row in the same bank.
Multi-Bank Access

The processors are capable of supporting multi-bank operation, thus taking advantage of the SDRAM architecture. depends only Operation using single versus multi-bankisaccessesan operation on the address to be posted to the device, it NOT mode.

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Any first access to SDRAM bank (A) forces an activate command before a read or write command. However, if any new access falls into the address space of the other banks (B, C, or D) the controller leaves bank (A) open and activates any of the other banks (B, C, or D). Bank (A) to bank (B) active time is controlled by tRRD = tRCD + 1. This scenario is repeated until all four banks (AD) are opened and results in an effective page size of up to four pages. This is because the absence of latency allows switching between these open pages (as compared to one page in only one bank at a time). Any access to any closed page in any opened bank (AD) forces a precharge command only to that bank. If, for example, two external port DMA channels are pointing to the same internal SDRAM bank, this always forces precharge and activation cycles to switch between the different pages. However, if the two external port DMA channels are pointing to different internal SDRAM banks, there is no additional overhead. See Figure 4-9.
Access to page x Bank A Access to page y Bank B Access to page x Bank C Access to page y Bank D Bank D Bank C Access to page y Bank B Access to page x Bank A

Single bank access

Multibank access

Figure 4-9. Single Versus Multibank Access Furthermore the controller supports four external memory selects containing each SDRAM. All external banks (MS3-0) provide multi-bank support, so the maximum number of open pages is 4 4 = 16 pages.

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reduces precharge and Multi-bank accessamong different internalactivation cycles by mapping opcode/data SDRAM banks driven by the A1817 pins and external memory selects (MSx).
Multi-Bank Operation with Data Packing

A logical address corresponds to 2 physical addresses when X16DE = 1. Consequently a physical address (for example of 512 x 16 page size) translates into a logical address of 256 16 words to satisfy the packing. Accordingly, all row addresses are shifted by 2. A populated SDRAM of 2M 16 4 with a 512 word page size, connected to external bank 0 and using bank interleaving (SDADDRMODE bit = 0) has the following logical map.
0x200000 logical start address int bankA 0x2000FF logical end address int bankA 0x300000 logical start address int bankB 0x3000FF logical end address int bankB 0x400000 logical start address int bankC 0x4000FF logical end address int bankC 0x500000 logical start address int bankD 0x5000FF logical end address int bankD

The same SDRAM with page interleaving (SDADDRMODE bit = 1) has the following address map:
0x200000 logical start address int bankA 0x2000FF logical end address int bankA 0x200100 logical start address int bankB 0x2001FF logical end address int bankB 0x200200 logical start address int bankC 0x2002FF logical end address int bankC 0x200300 logical start address int bankD 0x2003FF logical end address int bankD

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Timing Parameters The controller requires many timing settings in order to correctly access the SDRAM devices. Those that are user configurable can be found in SDRAM Registers on page A-31.
Fixed Timing Parameters

The timing specifications below are fixed by the controller. tMRD (mode register delay). Required delay time to complete the mode register write. This parameter is fixed to 2 cycles. tRRD (row active A to row active B delay). Required delay between two different SDRAM banks. This parameter is fixed to tRCD +1 cycle. tRC (row access cycle). Required delay time to open and close a single row. This parameter is fixed to tRC =tRAS + tRP cycles. tRFC (row refresh cycle). Required delay time to refresh a single row. This parameter is fixed to tRFC =tRC cycles. tXSR (exit self-refresh mode). Required delay to exit the self-refresh mode. This parameter is fixed to tXSR = tRC cycles. Data Mask The SDRAM controller provides one DQM pin (SDDQM), all SDRAM DQM pins could be connected to SDDQM pin. The SDDQM pin is driven high from reset deassertion until SDRAM initialization completes, after that its driven low irrespective of whether any accesses occur. Note that some manufacturers require keeping DQM high during the power-up initialization sequence.

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Resetting the Controller Like any other peripheral, the SDRAM controller can be reset by a hard or a soft reset. A hard reset puts the PLL in bypass mode where the SDRAM clock runs at a lower frequency. A hard or soft reset also causes data loss, and programs need to re-initialize SDRAM before it can be used again. reset ( Running controller. SDRAM
RESETOUT

pin as an input) does not reset the

16-Bit Data Storage and Packing The processors use logical addressing when an external memory smaller than 32 bits is used. Logical addresses require multiple external addresses seen by the memory correspond to a single internal address, depending on the width of the memory being accessed. The external physical address map is shown in Table 4-3. Table 4-8. SDRAM Address Memory Map
Bus Width External Memory Bank 0 1, 2, 3 Internal Logical Address (supported memory map) 0x0020_0000 0x007F_FFFF 0x0400_0000 0x047F_FFFF 0x0800_0000 0x087F_FFFF 0x0C00_0000 0x0C7F_FFFF External Physical Address (on ADDR230) 0x40_0000 0xFF_FFFF 0x00_0000 0xFF_FFFF

16-bit 16-bit

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External Instruction Fetch The processors support direct fetch of ISA instructions from external memory, using the 8/16-bit external port. Fetching is supported from external memory space bank 0 which is selected by MS0.
Interrupt Vector Table (IVT)

The interrupt vector table can be located in the internal ROM (0x80 000, IIVT bit = 0) or internal RAM (0x8C 000, IIVT bit = 1) based on the selected boot mode. However for all boot modes except the reserved boot mode, the default IIVT bit setting is 1 (SYSCTL). Therefore, if instruction fetch from external memory is desired at reset, the program needs to set up the appropriate interrupt vector tables in internal memory as part of the boot-up code before beginning to fetch these instructions. When an unmasked interrupt occurs and is serviced, program execution automatically jumps to the location of the corresponding interrupt vector table in internal memory. Upon returning from the interrupt, the sequencer resumes fetching instructions from external memory because locating the IVT in external memory is not supported.
Fetching ISA Instructions From External Memory

The SDRAM controller along with the processor core incorporates appropriate enhancements so that instruction code can be fetched from the SDRAM at the maximum possible throughput. Throughput is limited only by the SDRAM when the code is non sequential. The address map for code is same as for data. Each address refers to a 32-bit word. Any address produced by the sequencer is checked to deter-mine if it falls in the external memory and if so, the SDRAM controllers initiate access to the SDRAM. Because the sequencer address bus is limited to 24 bits, only part of the external memory address area can be used to store code. As explained in the following section, the address

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generated by the sequencer undergoes translation to produce a physical address, since the SDRAM data bus width is less than 48 bits. ISA or Whether fetching normal VISA instructions, the IVT needs to be placed in the ISA word space (NW).
Instruction Packing

Any address produced by the sequencer which falls in external memory is first translated into the physical address in external memory based on the actual data bus width of external memory as shown in Figure 4-8. The controller completes the required number of accesses from consecutive locations for returning a 48-bit word instructions. For a 16-bit SDRAM bus, it performs three accesses.

Only bank0 can be populated for external instruction fetch.

EXTERNAL PORT Logical ADDR ISA VISA Sequencer Instructions 48/32/16-bit
MS Address Translator CS

Physical ADDR [23:0]

External Memory

Instruction Packing 16/48

SDRAM Packed Instructions (16-bit)

Figure 4-10. Logical Versus Physical Addresses

16-Bit Instruction Storage and Packing

In Table 4-9 P = 0xE00000. Therefore, the total number of external memory instructions for a 16-bit wide SDRAM memory is 14 million.

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Table 4-9. Logical Versus Physical Address Mapping, 16-Bit SDRAM

Logical ISA Normal Word Physical Address, External Bus Address, Program Sequencer 0x20 0000 0x60 0000 0x60 0001 0x60 0002 0x20 0001 0x60 0003 0x60 0004 0x60 0005 0x20 0002 0x60 0006 0x60 0007 0x60 0008 ... 0x5F FFFF ... 0x11F FFFD 0x11F FFFE 0x11F FFFF InstrN[15:0] InstrN[31:16] InstrN[47:32] Data 150 Instr0[15:0] Instr0[31:16] Instr0[47:32] Instr1[15:0] Instr1[31:16] Instr1[47:32] Instr2[15:0] Instr2[31:16] Instr2[47:32]

Fetching VISA Instructions From External Memory

The SHARC processors support fetching instructions from external SDRAM or DDR2 memory. These instructions may be stored either as traditional 48-bit SHARC ISA instructions, or as VISA instructions. There is an overhead incurred when fetching data in general directly from external memory owing to inherent latencies and overheads associated with accessing SDRAM/DDR2 memory. Additionally, there are latencies involved with accessing non-sequential VISA instructions from external memory because of the width of the external SDRAM/DDR2 data bus (instructions have to be fetched as 16-bit units).

VISA mode execution is not supported through the asynchronous memory interface (AMI).
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In VISA operation, the sequencer fetches 3 x 16-bit of data which decodes in one, two or three instructions. For more information on VISA operation refer to the SHARC Processor Programming Reference. Just as the same physical internal memory on the processors can be accessed and addressed in many different ways, the external memory space can also be viewed either as logical or physical addresses. To support VISA in external memory, the external memory address range has been divided into two ranges: Normal word 0x20 0000 to 0x5F FFFF (ISA) Short word 0x60 0000 to 0xFF FFFF (VISA) When the processor accesses any instruction from the external normal word space, the instruction is deemed to have the traditional SHARC instruction encoding. When the processor accesses any instruction from external short word space, the instruction is deemed to have the new VISA instruction encoding. For a x16 memory, the external port interface effectively translates the addresses in range 0x20 0000 0x5F FFFF to 0x60 0000 0x11F FFFF, when accessing 48-bit instructions in legacy (ISA) encoding from external memory. The external port performs three accesses to form one 48-bit word before forwarding it to the IAB. Note that the external port interface passes the addresses in the range 0x60 0000 0xFF FFFF as is to external memory. As in the previous case, the external port accesses three short words to return a 48-bit word to the IAB for each access requested by the sequencer. The short words for a VISA section of code are packed in such a way that lowest of the addresses pertaining to a given instruction has the most significant short word of that instruction and the highest address has the least significant short word (see Figure 4-11). This packed instruction, when fetched in VISA space, is internally rotated before it reaches the instruction alignment buffer and cache. However, if

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SDRAM Controller (ADSP-2147x/ADSP-2148x)

this instruction is fetched in ISA space, this rotation does not occur and the instruction is cached without rotation. Eventually, if the cache gives out the instruction to the processor, it is a corrupted instruction. To avoid this, code should not be placed in either of the following ranges: 0x5F FFFD 0x5F FFFF and 0x60 0000 0x60 0008.
PHYSICAL ADDRESS (TRANSLATED BY INTERFACE FOR X16 DEVICE)

0x40 0000 LOGICAL ADDRESS (GENERATED BY SEQUENCER) 0x60 0000 0x80 0000 0x20 0000 ISA (NW) OPERATION 0x5F FFFF 0x60 0000

0xFF FFFF VISA (SW) OPERATION

0xFF FFFF

0x11F FFFF

Figure 4-11. Translation of Logical to Physical External Memory Addressing

Mixing Instructions and Data in External Bank 0

It is possible to store both 48-bit instructions as well as 16-bit data in external memory bank 0. However, care must be taken while specifying the proper starting addresses if 48-bit instructions are stored or interleaved with 16-bit data in the same memory bank.

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In 16-bit wide external SDRAM/DDR2 memory, one instruction is packed into three 16-bit memory locations, while 32-bit data occupies two memory locations. For example, if 2k instructions are placed in 16-bit wide SDRAM/DDR2 memory starting at the bank 0 (logical address 0x0020 0000 corresponding to physical address 0x0060 0000) and ending at logical address 0x002007FF (corresponding to physical address 0x0060 17FF), then data buffers can be placed starting at an address that is offset by 3k 16-bit words (for example, starting at 0x0060 1800).
Cache for External Instruction Fetch

To circumvent the relative difference in clock domains between the core and external memory interface (1:2 in the best case) and enable faster execution throughput, the functionality of the traditional conflict cache on the SHARC has been enhanced to serve as an instruction cache in external instruction fetch operations. In previous generations of SHARC processors, the function of the conflict cache had been to cache only those instructions whose fetching conflicted with access of a data operand from memory over the PM bus. The enhancements to the cache architecture mean that the functionality of the cache remains intact for execution from internal memory whereas it behaves as instruction cache for external memory execution. is Every instruction thatalsofetched from external memory into the program sequencer is simultaneously loaded into the cache. The next time that this instruction needs to be fetched from external memory, it is first searched for in the cache. The instruction is stored using the entire 24-bit address. Figure 4-6 shows the format for storing an instruction. In other words, the 32-entry 2-way set-associative cache in the SHARC has been modified to act as an instruction cache when the program sequencer executes instructions from external memory, while continuing

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to work as the traditional conflict cache when the sequencer executes instructions located in internal memory. This context switching from conflict cache to instruction cache and vice-versa happens automatically without the need for any user intervention.
LRU VALID BIT BIT SET 0 SET 1 SET 2 ENTRY 0 ENTRY 1 ENTRY 0 ENTRY 1 ENTRY 0 ENTRY 1 0010 0001 INSTRUCTIONS ADDRESSES BITS (23-4) ADDRESSES BITS (3-0) 0000

SET 13 SET 14 SET 15

ENTRY 0 ENTRY 1 ENTRY 0 ENTRY 1 ENTRY 0 ENTRY 1

1101

1110

1111

Figure 4-12. Instruction Cache Architecture The first time that an instruction from a particular address is fetched from external memory, there is a cache miss when the sequencer looks for this instruction within the cache. Consequently, the instruction has to be fetched from external memory and a copy of instruction is stored in cache. Upon subsequent executions of this instruction, the sequencer search results in a cache hit, resulting in the instruction being fetched from cache instead of external memory. This allows for an instruction throughput that is equivalent to internal memory execution. This context-dependent caching preserves the cache performance of the traditional SHARC conflict cache as well as significantly improving program instruction throughput for repetitive instructions such as those

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inside loops when executing from external memory. Analyses of typical application code examples have shown that this 32-entry instruction cache improves execution throughput by 50-80% over not having this cache. In general, cache hits occur for all instructions which are fetched and executed multiple times (for example loops, subroutine calls, negative branches, and so on). Typical applications, such as signal processing algorithms, are ideal candidates for significant performance improvements as a result of the cache. An important and significant result of the instruction being fetched from the cache is that it frees up the external port as well as the internal PM and DM buses for other operations such as data transfers, operand fetches, or DMA transfers. The following example shows the innermost loop of a FIR filter.
lcntr=FILTER_TAPS-1, do macloop until lce; macloop: f12=f0*f4, f8=f8+f12, f0=dm(i0,m1), f4=pm(i9,m9);

In this example, if the code is stored and executed from external memory, the first time through this loop the program sequencer places the appropriate 24-bit address on the external address bus, and fetches the instruction in line 2 from external memory. While this instruction is being fetched and processed by the sequencer, it is also simultaneously stored in the internal instruction cache. For every subsequent iteration of this loop, the instruction is fetched from the internal cache, thereby occurring in a single cycle, while freeing up the internal memory buses to fetch the data operands required for the instruction. Previously, in the absence of the internal instruction cache, the number of cycles taken by the loop for a case of FILTER_TAPS = 16 would have been a minimum of 96 SDRAM cycles over a 8-bit wide external bus (excluding any conflicts for data operand fetches). However, with the presence of the instruction cache, and assuming that the execution is from external AMI,

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the number of cycles is reduced to 17 core clock cycles over a 8-bit wide external bus. expected, it important As might bedoes not play is significant to remember that the instruction cache a role in improving the efficiency of strictly linearly executed code from external memory.
Address Versus SDRAM Types

Table 4-10 provides addressing for various sizes of SDRAM memory. Table 4-10. Translation of Logical to Physical Addressing for SDRAM
DDR2 Device 32 Mb (x16) 64 Mb (x16) 128 Mb (x16) 256 Mb (x16) Physical Address Range Mapped to Memory Device 0x60 0000 0x7F FFFF 0x60 0000 0x9F FFFF 0x60 0000 0xDF FFFF 0x60 0000 0x15F FFFF Mapping Between External Port Address Range and Memory Device 0x00 0000 0x1F FFFF 0x020 0000 0x3F FFFF 0x000 0000 0x1F FFFF 0x020 0000 0x7F FFFF 0x000 0000 0x1F FFFF 0x020 0000 0xFF FFFF 0x000 0000 0x1F FFFF

Operating Modes
The following sections provide on the operating modes of the SDRAM interface. Address Mapping To access SDRAM, the controller multiplexes the internal 32-bit non-multiplexed address into three portions: Row address bits

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Column address bits Bank address bits The non multiplexed address that is seen from the core/DMA is referred to as IA310 in the following sections.
Address Translation Options

To provide flexible addressing, the SDADDRMODE bit (bit 31) in the SDCTL0 register is used to select the address mapping schemepage interleaving or bank interleaving (default). Page Interleaving Map Programming the SDADDRMODE bit to 1 selects the page interleaving scheme. In this scheme consecutive pages fall in consecutive banks. The bank address bits follow the most significant column address bits. This is shown in Figure 4-13. One advantage of the page interleaving is that the effective page size is up to four pages (assuming four banks activated) and all the addresses are sequential. If using delay line DMA mode, the addresses for a long delay line are all sequential, simplifying the addressing. Moreover, SDRAM sequential addressing provides maximum performance. Page interleaving Interleaving Map is not supported with 2 bank devices. Bank Programming the SDADDRMODE bit to 0 selects the bank interleaving scheme. In this scheme consecutive pages sit in the same bank. The bank address bits follow the most significant row address bits. This is shown in Figure 4-13.

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CORE ADDRESS MAPPING, TO ROW, COLUMN ADDRESSES (Page Interleaving, SDADDRMODE=1)

31
Unused Row Address Bank Address Column Address

CORE ADDRESS MAPPING, TO ROW, COLUMN ADDRESSES (Bank Interleaving, SDADDRMODE=0)

31
Unused Bank Address Row Address Column Address

Figure 4-13. Core Address MappingPage and Bank Interleaving One advantage of bank interleaving is that the effective page size is also up to four pages (assuming that four banks are activated) but the addresses of the four pages are not sequential. If using two external port DMAs pointing to the SDRAM space, this scheme has the advantage where every bank uses single DMA buffer addressing.

For two-banked SDRAMs, connect2 BA with A17. Note that page interleaving is not supported with bank devices. row address width The mapping of the addresses depends),on thethe address mode bit ), column address width ( and (
SDRAW SDCAW

(SDADDRMODE) setting.
Address Width Settings

Address width settings can be configured as shown in Table 4-17. Table 4-11. External Memory Address Bank Decoding
IA[27] 0 0 IA[26] 0 1 External Bank Bank 0 Bank 1

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Table 4-11. External Memory Address Bank Decoding (Contd)

IA[27] 1 1 IA[26] 0 1 External Bank Bank 2 Bank 3

Number of Internal Banks. The controller assumes the SDRAM is comprised of four bank devices. However, SDRAM can use two bank devices by not connecting the ADDR18 pin. Row Address Width (SDRAW). These bits in the SDCTL register determine the row width of the SDRAM. The SDRAW bits can be programmed for row widths of 8 to 15. Column Address Width (SDCAW). The SDRAM memory control register also includes external bank specific programmable parameters. The external bank can be configured for a different SDRAM size. The SDRAM controller determines the internal SDRAM page size from the PGSZ128 and SDCAW parameters. Page sizes of 128, 256, 512, 1K, 2K words are supported. 16-Bit Address Mapping Even if the external data width is 16 bits, the processor supports only 32-bit data accesses. If X16DE is enabled (=1) the controller performs two 16-bit accesses to get and place 32-bit data. The controller takes the IA address and appends one extra bit to the LSB to generate the address externally. In the following sections and in Table 4-12 and Table 4-13, the mapping of internal addresses to the external addresses is discussed. The mapping of the addresses depends on the address mode (SDADDRMODE bit) on row address width (SDRAW), and on column address width (SDCAW).

The

X16DE

bit must always be set.

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For example, if the processor core requests address 0x2000000 for a 32-bit access, the controller performs two 16-bit accesses at 0x4000000 and 0x4000001, using MS0 to get one 32-bit data word. The column and row addresses seen by 16-bit SDRAMs is shown in Table 4-12 where SDADDRMODE = 1, X16DE = 1, SDRAW20 = 101 (13 bits), and SDCAW10 = 10 (10 bits). Table 4-12. Page Interleaving Map (1K Page Size)
Pin A[18] A[17] A[13] A[12] A[11] SDA10 A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] 1b0 IA[8] IA[7] IA[6] IA[5] IA[4] IA[3] IA[2] IA[1] IA[0] 1/0 IA[23] IA[22] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] IA[11] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] Column Address Row Address Bank Address IA[10] IA[9] Pins of SDRAM BA[1] BA[0]

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Table 4-13 where SDADDRMODE = 0, X16DE = 1, SDRAW20 = 100 (12 bits), and SDCAW10 = 11 (11 bits). Table 4-13. Bank Interleaving Map (2K Page Size)
Pin A[18] A[17] A[13] A[12] A[11] SDA10 A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] IA[9] 1b0 IA[8] IA[7] IA[6] IA[5] IA[4] IA[3] IA[2] IA[1] IA[0] 1/0 IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] IA[11] IA[10] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] Column Address Row Address Bank Address IA[23] IA[22] Pins of SDRAM BA[1] BA[0]

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Parallel Connection of SDRAMs To specify a SDRAM system, multiple possibilities are given based on the different memory sizes. For a 16-bit I/O capability, the following can configured. 1 x 16-bit/page 512 words 2 x 8-bit/page 1k words 4 x 4-bit/page 2k words The SDRAMs page size is used to determine the system you select. All three systems have the same external bank size, but different page sizes. Note that larger page sizes, allow higher performance but larger page sizes require more complex hardware layouts. connecting Even ifthe cluster as SDRAMs in parallel, the controller always considers one external SDRAM bank because all address and control lines feed the parallel parts as shown in Figure 4-15.
ADSP-2147x
C O N T R O L A D D R E S S RAS CAS SDWE SDCKE MS3 A[14-11] A[9-0] SDA10 A17 A18 SDCLK DATA[15-0] SDDQM BA0 BA1 CLK DATA[15-0] DQM A[14-0] SDRAM 8M x 16 x 4 RAS CAS WE CKE CS

Figure 4-14. Single Processor System With SDRAM

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Buffering Controller for Multiple SDRAMs

If using multiples SDRAMs or modules, the capacitive load will exceed the controllers output drive strength. In order to bypass this problem an external latch can be used for decoupling by setting the SDBUF (bit 23). This adds a cycle of data buffering to read and write accesses. An example single processor system is shown in Figure 4-15. SDRAM Read Optimization To achieve better performance, read addresses can be provided in a predictive manner to the SDRAM memory. This is done by setting (=1) SDROPT (bit 16) and correctly configuring the SDMODIFY bits (2017) in the SDRRC register according to the cores DAG modifier or the DMAs modify parameter register. The predictive address given to the memory depends on the SDMODIFY bit values. For example, if the DAG modifier = 2, the SDMODIFY value should also be 2, in which case the address + 2 is the predictive value provided to the SDRAM address pins. Programs may choose to determine whether read optimization is used or not. If read optimization is disabled, then each read takes 7 cycles for a CAS latency of 3, even for sequential reads. With read optimization enabled, 32 sequential reads, with offsets ranging from 0 to 15, take only 37 SDCLK cycles. Read optimization should not be enabled while reading at the external bank boundaries. For example, if SDMODIFY = 1, then 32 locations in the boundary of the external banks should not be used. These locations can be used without optimization enabled. If SDMODIFY = 2, then 64 locations cannot be used at the boundaries of the external bank (if it is fully populated). Use read optimization for core and DMA, with a constant modifier to achieve better performance. With multiple channels running with ping-pong accesses, use arbitration freezing to get better throughput.

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ADDR [15] CTRL [6]

21 D Q
SDRAM BANK 1 ADDR & CTRL

21 D Q
SDRAM BANK 2 ADDR & CTRL

S
C O N T R O L

REGISTERED BUFFERS RAS CAS SDWE SDCKE MS3 A[12-11] A[9-0] SDA10 A17 A18 DATA [7-4] IXA[12-0] DATA [3-0] CLK I0 I1 I2 I4 I5 O0A O1A O2A O3A O4A RAS CAS WE CKE CS

SDRAM #1 32M x 4 x 4

DQM

DQM

A D D R E S S

OXA[12-0]

A[14-0] DQM

DATA [3-0] DATA[3:0]

SDRAM #2 32M x 4 x 4

DQM

DATA [11-8]

DATA[3:0]
SDRAM #3 32M x 4 x 4

SDCLK DATA [15-0] SDDQM

DATA [15-12]

DATA[3:0]
SDRAM #4 32M x 4 x 4

Figure 4-15. Uniprocessor System With Multiple Buffered SDRAM Devices enabled ( = 1) a By default, the( read optimization is optimization assumes with the modifier of 1 = 1). Read that
SDROPT SDMODIFY

SDRAM pointer has a constant modifier. For non-sequential accesses, turning off optimization provides better results.

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Core Accesses

Any break of sequential reads of full page accesses can cause a throughput loss due to a maximum of four extra reads (eight 16-bit reads). Listing 4-1 shows how to achieve maximum core access throughput. Any cycle between consecutive reads to an SDRAM address results in non-sequential reads. Listing 4-1. Maximum Throughput Using Sequential Reads
ustat1=dm(SDCTL); bit set ustat1 SDROPT|SDMODIFY1; dm(SDCTL)=ustat1; nop; I0 = sdram_addr; M0 = 1; Lcntr = 512, do(PC,1) until lce; R0 = R0 + R1, R0 = dm (I0, M0);

The example shows read optimization can be used efficiently using core accesses. All reads are on the same page and it takes 1184 cycles to perform 512 reads. Without read optimization, 512 reads use 6144 processor cycles if all of the reads are on the same page. With read optimization (Listing 4-2), 512 reads take 7168 cycles, due to the breaking of sequential reads.

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Listing 4-2. Interrupted Reads With Read Optimization

ustat1=dm(SDCTL); bit set ustat1 SDROPT|SDMODIFY2; dm(SDCTL)=ustat1; nop; I0 = sdram_addr; M0 = 2; Lcntr = 512, do(PC,2) until lce; R0 = R0 + R1, R0 = dm (I0, M0); NOP;

DMA Access

Listing 4-3 shows an example of external port DMA using read optimization. Listing 4-3. EPDMA With Read Optimization
ustat1=dm(SDCTL); bit set ustat1 SDROPT|SDMODIFY2; dm(SDCTL)=ustat1; nop; r0=DFLSH; dm(DMAC1)=r0; r0=intmem; r0=2; r0=N; r0=2; r0=extmem; r0=DEN; dm(DMAC1)=r0; dm(IIEP1)=r0; dm(IMEP1)=r0; dm(ICEP1)=r0; dm(EMEP1)=r0; dm(EIEP1)=r0;

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Notes on Read Optimization

The core and the DMA engine take advantage of the major improvements during reads using read optimization. However, in situations where both the core and DMA need to read from different internal memory banks with different modifiers at the same time, programs need to choose whether or not to use optimization. Note that from a throughput prospective, external port arbitration also is a factor. A good rule is that the requester with the higher priority should have the same modifier as SDMODIFY. In other words, if DMA has a higher priority over the core, then the DMA modifier should match the SDMODIFY setting. Self-Refresh Mode This mode causes refresh operations to be performed internally by the SDRAM, without any external control. This means that the controller does not generate any auto-refresh cycles while the SDRAM is in self-refresh mode. Self-refresh entrySelf-refresh mode is enabled by writing a 1 to the SDSRF bit of the SDRAM memory control register (SDCTL). This deasserts the SDCKE pin and puts the SDRAM in self-refresh mode if no access is currently underway. The SDRAM remains in self-refresh mode for at least tRAS and until an internal access (read/write) to SDRAM space occurs. Self-refresh exitWhen any SDRAM access occurs, the controller asserts SDCKE high which causes the SDRAM to exit from self-refresh mode. The controller waits to meet the tXSR specification (tXSR = tRAS + tRP) and then issues an auto-refresh command. After the auto-refresh command, the controller waits for the tRFC specification (tRFC = tRAS + tRP) to be met before executing the activate command for the transfer that caused the SDRAM to exit self-refresh mode. Therefore, the latency from when a transfer is received by the controller while in self-refresh mode, until the activate command occurs for that transfer, is 2 (tRC + tRP) cycles.

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System clock during self-refresh mode. Note that the SDCLK is not disabled by the controller during self-refresh mode. However, software may disable the clocks by clearing the DSDCTL bit in the SDCTL register. Programs should ensure that all applicable clock timing specifications are met before the transfer to SDRAM address space (which causes the controller to exit the self-refresh mode). If a transfer occurs to SDRAM address space when the DSDCTL bit is cleared, an internal bus error is generated, and the access does not occur externally, leaving the SDRAM in self-refresh mode. The following steps are required when using self-refresh mode. 1. Set the SDSRF bit to enter self-refresh mode 2. Poll the SDSRA bit in the SDRAM status register (SDSTAT) to determine if the SDRAM has already entered self-refresh mode. 3. Optionally: set the DSDCTL bit to freeze SDCLK 4. Optionally: clear the DSDCTL bit to re-enable SDCLK 5. SDRAM controller executes a self refresh exit sequence on receiving a SDRAM access request. minimum The command istime between a subsequent self-refresh entry and cycle. If a self-refresh request is issued exit the t during any external port DMA, the controller grants the request with the tRAS cycle and continues DMA operation afterwards. Forcing SDRAM Commands The controller has bits which can be specifically used to aid in debug and in specific system solutions. By setting the SDPSS bit after reset, all mode registers are automatically updated. The SDPSS bit should be cleared when using forced commands.
RAS

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Force Precharge All

Whenever an auto-refresh or a mode register set command is issued, the internal banks are required to be in idle state. Setting bit 21 (=1) forces a precharge all command to accomplish this. If the precharge all command is not issued, the auto-refresh and mode register set commands can be illegal depending on the current state. Note that it is a good practice always to perform a force precharge all command before a forced refresh/mode register command.
Force Load Mode Register

Programs can use the Force LMR command by setting bit 22 (=1) in the SDCTL register. This command is preceded by a precharge all (if banks not idle) followed by a mode register write. The Force LMR bit allows changes to the MODE register based settings during runtime. These settings include the CL (CAS latency) timing specification which needs to be changed to adapt to a new frequency operation.
Force Auto-Refresh

Bit 20 (=1) forces the auto refresh to be immediately executed (not waiting until the refresh counter has expired). This is useful for test purposes but also to synchronize the refresh time base with a system relevant time base.

DDR2 DRAM Controller (ADSP-2146x)

The DDR2 DRAM controller (the controller) on ADSP-2146x processors enable a transfer of data to and from synchronous DDR2 DRAM. It supports a glueless interface with four external banks, controlled by the memory chip select pins (DDR2_CS30), of standard DDR2 DRAMs of 256 Mbit to 2 Gbit with configurations x8 and x16.

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Features
The features of the DDR2 DRAM controller are listed below. Supports up to 8G bit (254M x 32-bit) of DDR2 memory Supports DDR2-400 of 256M bit, 512M bit, 1G bit and 2G bit with x8 and x16 Supports 4 and 8 bank DDR2 devices with page sizes of 512, 1K, 2K, and 4K words Variable memory address map (bank or page interleaving) Burst mode of 4 (BL = 4) with sequential burst type Supports multibank operation with open page policy Supports self-refresh mode and precharge power-down to reduce power consumption Supports read optimization (predictive solution) DDR2 PHY does provide the physical interface to JEDEC standard DDR2 Memories Supports programmable ODT (on-die termination) Supports 64-bit data SIMD and external instruction fetch in bank 0 for ISA/VISA instructions Independent transfers between DDR2 and AMI modules

Pin Descriptions
The pins used by the external memory interface are described in the ADSP-2146x SHARC Processor Data Sheet. Additional information on pin multiplexing can be found in Pin Descriptions on page 24-2.

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Functional Description
On SDRAM systems all timing is referenced to the rising edge of the clock as per the JEDEC specification. However, since the clock speed has increased, this approach becomes limited based on setup and hold times. DDR2 is no longer system synchronous (as SDRAM), it is source synchronous which means the data source provides a reference signal (called the data strobe signal or DQS) which is sampled by the receiver and used to latch the data accordingly. Two main modules shown in Figure 4-16 control the high speed throughputs/constraints. One block is the DDR2 controller which also interfaces to the arbiter (core vs. DMA) containing the state machine to generate the supported commands to the DDR2 memory. The other main module is the DDR2 PHY which owns DLL circuits and I/O logic (Data and Data strobes).
ADSP-2146x
DDR2 MEMORY CONTROLLER CLOCK/CLOCK ENABLE ADDRESS/COMMAND
DQ7-0 DQS0/DQS0 DM0

DDR2 DRAM MEMORY

DQ7-0 LDQS/LDQS LDM

DLL0

I/O0

DDR2 PHY

Figure 4-16. DDR2 Controller

ADSP-214xx SHARC Processor Hardware Reference

DLL1

I/O1

DQ15-8 DQS1/DQS1 DM1

DQ15-8 UDQS/UDQS UDM

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DDR2 Controller The controller uses burst length 4 (BL = 4) for read and write operations. This requires the controller to post only the first read or write address on the bus, all subsequent sequential address are posted by the DDR2 internal burst counter. For read commands, there is a latency from the start of the read command to the availability of data from the DDR2, equal to the CAS latency. This latency is always present for any single read transfer. Subsequent reads do not have latency. Note that writes also have latency which = read latency 1. For more information on commands used by the DDR2 controller, see SDRAM Commands below. The configuration is programmed in the DDR2CTL5-0 registers. The DDR2 controller can hold off the processor core or DMA controller with an internally connected acknowledge signal, as controlled by refresh, or page miss latency overhead. A programmable refresh counter is provided which generates background auto-refresh cycles at the required refresh rate based on the clock frequency used. The refresh counter period is specified using the RDIV field in the DDR2 refresh rate control register (Refresh Rate Control Register (DDR2RRC) on page A-53). memory the JEDEC DDR2 The burstaccesses are burst oriented perand therefore specification. accesses are NOT divisible every DDR2 access needs to satisfy the burst length of 4 words (4x16) even if not required for an application. This makes single read/write accesses inefficient and the controller needs to ignore (read) or mask (write) unwanted data. DDR2 Arbiter For read accesses, the DDR2 memory drives 16 bit data at both the edges of DDR2 clock which is sampled by the DDR2 controller data path, synchronized with internal clock and transferred to DDR2 arbiter as a single 64 bit data. The DDR2 arbiter in turns transfers the 64-bit data to

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corresponding queue for which the read request command was accepted. The queue in turn transfers the same on to DMA or core bus and unpacks the 64 bit data word in to 2 single words (32-bit) before transferring them on to external port DMA bus. DDR2 PHY The DDR2 PHY supplies the complete physical interface to JEDEC standard DDR2 SDRAM Memories. Figure 4-16 shows a representation of part a system of the DDR2 PHY with the controller and the external memory. There are two DLL circuits (DLL10) for each data byte lane (upper and lower byte) DLL0 controls DDR2_DATA7-0, DDR2_DQS0 and DDR2_DM0 pins. DLL1 controls DDR2_DATA15-8, DDR2_DQS1 and DDR2_DM1 pins. As per JEDEC specifications, the data (DQ) are center-aligned with the DQS signal during a write to the memory and edge-aligned with the DQS signal during a read from the memory. The DDR2 controllers command enables either the write or read path in the memory I/O. During a DRAM write, the DDR2 controller performs the multiplexing of positive and negative edge data. This in turn is driven onto DQ as write data when the write path in the memory I/O buffers is activated. The corresponding write DDR2_DQS is also driven through the memory I/O, but after a phase shift of 90 degrees (controlled by the controller DLL). During a memory read, the data from the DDR2 memory (SSTL-18 level) is converted to the core voltage logic level inside the DDR2 memory I/O pads. This is captured by the DDR2 DLL using precise delays on the data strobe (DDR2_DQS) line provided to the controller. Read data is sent by the DDR2 DRAM on both the rising and falling edges of the DDR2_DQS signal. The read data is captured by the on-chip

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DLL using a delayed DQS that is phase shifted by approximately 90 degrees for the positive edge data and by approximately 90 degrees for the negative edge data. These delays are precisely generated by the internal on-chip DLL circuit. The captured data is sent out, corresponding to the data launched by the DRAM with the positive edge and negative edge of DDR2_DQS respectively. con For correct DDR2 operation it is important to connectgroup only trol/data signals ( , and ) to their byte lane
DQx DMx DQSx

(high or low byte DLL). Only data signals ( DQx) within a byte lane are allowed to be mixed, for example DQ7-0 can be connected to DQ0-7 of DDR2 device to match trace lengths in layout design. It should be noted that the DDR2 PHY does not directly control the address and command lines. (DDR2_ADDR, DDR2_RAS, DDR2_CAS, DDR2_WE). DDR2 Memory DLL Although read data is captured at the controller using data strobes (DQS), this represents only a portion of the read timing (data capture timing). The complete DDR2 controller timing including the controller generating a read command, capturing the data, and transferring the data to its internal data path begins and ends in the controller clock domain. For this reason, it is necessary to specify a relationship between the DDR2 memory output data, data strobes and the input clock. Uncompensated timing variations (process, voltage and temperature) that occur in SDRAMs are not acceptable at the targeted clock frequencies. For this reason, a delay locked loop (DLL) is included in DDR2 memories to compensate for process, temperature and voltage variations. Note the variation updates occur during the auto-refresh command. systems DLLs DDR2 memorythe DLL isrequire that the controller/memoryJEDEC are enabled (if disabled the operation mode not compliant). It is achieved by clearing the SH_DLL_DIS bit (controller, DDR2CTL0) and the DDR2DLLDIS bit (memory, DDR2CTL3).

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Self Calibration Logic Both data byte lanes are internally re timed such that they can be captured directly by the controller on the positive edge of DDR2_CLK, irrespective of the arbitrary phase relation that may exist between DDR2_CLK and the DDR2_DQS. During initial operation (external bank calibration), the on-chip DLL determines the phase difference between the DDR2_CLK and DDR2_DQS and re times the data captured accordingly. In the last stage of the DDR2 init sequence, the controller starts an automated external memory bank calibration by sending dummy read commands which drive the memorys DQS strobes (via the memory DLL) back to the controllers DQS pins. The delay (phase relation between the internal DDR2 clocks and the DQS signals) is sensed and stored in a DLL register. This coarse delay represents PCB flight delay. The initial goal is to shift the DQS strobes into the center of what becomes the Read Data capture window. To compensate for process, voltage and temperature related shifting of the DQS strobes, a continuous calibration runs during normal operation. The calibration logic monitors the delay taps of the DQS input paths. If a shift is detected, the delay count on the DQS strobe input paths can be fine adjusted to keep them centered in the Read Data capture window. The update is done during DDR2 memory auto-refresh command since the data path is idle avoid impacting normal data operations and controller efficiency. Mode Registers DDR2 functionality is programmed through the (extended) Mode registers (per JEDEC definition). These registers need to be programmed prior to using the interface. During the mode register command the address bus (DDR2_ADDR15-0) is used to program the various options while the DDR2 bank select pins (DDR2_BA1-0) are used to select one of the 4 mode registers.

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All bit settings in the mode registers must be programmed. This can be done using the DDR2PSS bit in the DDR2 memory control register (DDR2CTL0) which automatically programs all mode registers bits appropriately. Note that options that are not supported are programmed to zero. Note that programs can change the optional bits for forced mode registers (DDR2CTL0 register) individually afterwards. For more information refer to automated initialization sequence.
Load Mode Register

The MR command initializes DDR2 operation parameters. The controller supports CAS latency. For more information, see DDR2 Control Register 2 (DDR2CTL2) on page A-47.
Load Extended Mode Register

The EMR command initializes enhanced DDR2 operation parameters. The following options are supported. DDR2 DLL disable Output drive strength reduced Additive latency On die termination Differential DQS signal disable Output buffer disable For more information, see DDR2 Control Register 3 (DDR2CTL3) on page A-49.
Load Extended Mode Register 2

The EMR2 command initializes enhanced 2 DDR2 operation parameters. The controller does not support any of these options. For more informa-

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tion, see DDR2 Control Register 4 (DDR2CTL4) on page A-51.

Load Extended Mode Register 3

The EMR3 command initializes enhanced 3 DDR2 operation parameters. The controller does not support any of these options. For more information, see DDR2 Control Register 5 (DDR2CTL5) on page A-52. DDR2 Commands This section provides a description of each of the commands that the DDR2 controller uses to manage the DDR2 interface. These commands are handled automatically by the DDR2 controller. A summary of the various commands, including the truth tables used by the on-chip controller for the DDR2 interface can be found in the JEDEC specification (JESD792x).
Bank Activation

This command is required if the next data access is on a different page in the same internal bank or in a different internal bank that is in an idle state. The controller executes the pre-charge command, followed by a bank activate command, to activate the page in the desired DDR2 internal bank. The controller is able to open up to eight pages at the same time in different internal banks. For 8 banked devices, the controller follows the tFAW specification.
Precharge

This command is executed by the controller if the address to be accessed falls in a different page in the same external bank and the same internal bank. A precharge is not done if the address to be accessed falls in an open page in another internal or external bank.

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For page miss reads or writes, only the external and internal banks to be accessed by the read or write is pre-charged. For auto-refresh and self-refresh, all external DDR2 banks are pre-charged at one time.
Precharge All

This command is given to precharge all internal banks. Just before an auto refresh or self refresh, or during the power up sequence, the controller always issues the precharge command to all internal DDR2 banks. For eight bank devices, the tFAW period must be satisfied while performing the precharge all command.
Burst Read

The burst read command is initiated by having DDR2_CS and DDR2_CAS low while holding DDR2_RAS and DDR2_WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DDR2_DQS) is driven low one clock cycle before valid data (DDR2_DATA) is driven onto the data bus (Figure 4-17). The first bit of the burst is synchronized with the rising edge of the data strobe (DDR2_DQS). Each subsequent data-out appears on the DDR2_DATA The first bit of the burst is synchronized with the rising edge of the data strobe (DDR2_DQS). Each subsequent data-out appears on the DDR2_DATA pin in phase with the DDR2_DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the mode register (MR), similar to the existing SDRAM. The AL is defined by the EMR1 register.

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T0 DDR2_CLKx/ DDR2_CLKx

T1

T2

T3

T4

T5

T6

T7

T8

CMD

ACTIVE N

READ N

NOP

NOP

NOP

NOP

NOP

NOP

tRCD (MIN) DDR2_DQS/ DDR2_DQS

Dout n Dout n+1 Dout n+2 Dout n+3

DQ CAS Latency (CL) = 3 Additive Latence (AL) = 2 READ latency = RL - AL + CL - 5 tAC, tDQSCK, tDQSQ = NOMINAL

AL - 2 RL - 5

CL - 3

Figure 4-17. Burst Read

Burst Write

The burst write command, shown in Figure 4-18, is initiated by having DDR2_CS, DDR2_CAS and DDR2_WE pins low while holding DDR2_RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL 1) and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first DDR2_DQS strobe.
T0 DDR2_CLKx/ DDR2_CLKx T1 T2 T3 T4 T5 T6 T7

CMD

ACTIVE N

WRITE N

NOP

NOP

NOP

NOP

NOP

NOP

tRCD (min) DDR2_DQS/ DDR2_DQS AL = 2 CL - 1 = 2

Din n Din n+1 Din n+2 Din n+3

DQS WL = AL + CL - 1 = 4 CAS Latency (CL) = 3 Additive Latence (AL) = 2 WRITE latency = AL + CL - 1 = 4

Figure 4-18. Burst Write

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A data strobe signal (DDR2_DQS) should be driven low (preamble) nominally a 1/2 clock prior to the WL. The first data bit of the burst cycle must be applied to the DDR2_DATA pins at the first rising edge of DDR2_DQS following the preamble. The subsequent burst bit data are issued on successive edges of DDR2_DQS until the burst length is completed. When the burst has finished, any additional data supplied to the DDR2_DATA pins is ignored. The DDR2_DATA signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (WR).
Auto-Refresh

The DDR2 internally increments the refresh address counter and causes a CAS before RAS (CBR) refresh to occur internally for that address when the auto-refresh command is given. The controller generates an auto-refresh command after the refresh counter times out. The RDIV value in the DDR2RRC register must be set so that all addresses are refreshed within the tREF period specified in the DDR2 timing specifications. Before executing the auto-refresh command, the DDR controller executes a pre-charge all command to all external banks. The next activate command is not given until the tRFC specification is met. Auto-refresh commands are also issued by the controller as part of the power-up sequence and after exiting self-refresh mode.
Self-Refresh Entry

Self-refresh mode causes refresh operations to be performed internally by the DDR2 controller, without any external control. This means that the controller does not generate any auto refresh cycles while it is in self-refresh mode. The self-refresh entry command is performed by writing a 1 to the DDR2SRF bit of the memory control register (DDR2CTL0). This deasserts the DDR2_CKE pin to put the device into self-refresh mode. In this

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mode, the DDR2 memory DLL is put into reset in order to reduce power consumption. If any of the two DDR2 clocks is not required in a system during self-refresh, they can be stopped by setting the DIS_DDR2CTL and DIS_DDR2CLK1 bit in the DDR2CTL0 control register. This reduces the power consumption in a system and is shown in the following code example.
ustat1 = dm(DDR2CTL0); bit set ustat1 DDR2SRF; dm(DDR2CTL0) = ustat1; nop; ustat2 = dm(DDR2STAT0); bit tst ustat2 DDR2SRA; if not TF jump (pc,2); /* enter self-refresh */

/* test self-refresh entry */

ustat1 = dm(DDR2CTL0); bit set ustat1 DIS_DDR2CTL|DIS_DDR2CLK1; dm(DDR2CTL0) = ustat1; nop;

/* freeze DDR2 clock */

careful This requiresruntime.software control because the if this bit isbit is set during Systems may become unstable set
DIS_DDR2CTL

too early because the system can lose control of the DDR2 memory device.
Self-Refresh Exit

The DDR2 remains in self-refresh mode for at least tRAS period and until an access to DDR2 space occurs or SREF_EXIT bit in DDR2CTL0 is set. When exiting from self-refresh mode programs need to consider if this occurs during a read or write. If exiting during a read, additional latency occurs because the DDR2 memory DLL needs to be locked again. When an access to DDR2 space occurs or when the SREF_EXIT bit is set in the DDR2CTL0 register, the controller: 1. Exits DDR2 from self-refresh mode by asserting DDR2CKE pin high

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2. Waits to meet the tXSNR specification (tXSNR = tRAS + tRP) 3. Issues an auto-refresh command After the auto-refresh command, the controller waits for the tRFC specification to be met before executing the activate command for the transfer that caused the DDR2 to exit self-refresh mode. 4. For reads, the tXSRD time must be satisfied. When exiting self refresh, ODT must remain low until tXSRD is satisfied. For example:
ustat1 = dm(DDR2CTL0); bit clr ustat1 DIS_DDR2CTL|DIS_DDR2CLK1; dm(DDR2CTL0) = ustat1; /* release clock */ nop; ustat2 = dm(DDR2STAT0); bit tst ustat2 DDR2SRA; if not TF jump (pc,2); dm(DDR2_ADDR) = r0;

/* test self-refresh */ /* exit self-refresh */

Precharge Power-Down Entry

The DDR2 controller supports DDR2 precharge power down mode. In this mode, the DDR2 memory DLL is disabled (like Self-refresh mode) to maximize power consumption. When the DIS_DDR2CKE bit is set to 1 and the DDR2 controller enters an idle state, it issues a pre-charge command (if necessary) and then, after meeting the required timing specifications, pulls down the DDR2CKE signal. If an internal access is pending, the controller delays entering the power-down mode until it completes the pending DDR2 access and any subsequent pending access requests.
DIS_DDR2CKE DIS_DDR2CKE

= 0 No effect. = 1 Enter precharge power down.

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Once the DDR device enters into power-down mode, the DDR controller asserts the DDR2PD bit in the DDR control status register (DDR2STAT0). entry mode does Unlike self-refresh mode, precharge power-downsoftware control is not refresh the DDR2 device. Therefore, careful required so as not to violate refresh conditions which leads to data corruption. The typical refresh interval of tREFI can be extended up to 8 tREFI. Consult the DDR2 data sheet for complete information. This mode is useful if the DDR2 operation is idling only for a short period of time. This time is limited by the JEDEC spec and is typically 9 tREFI. If for example tREFI = 7.8 s the maximum power-down time is 9 7.8 s = 70 s. According to the JEDEC standard eight burst refresh cycles are required before entering precharge power down mode. When DDR2 memory pauses for a short period of time, systems should evaluate on a case by case basis whether or not self-refresh or precharge power-down should be used. This consideration will take into account that precharge power-down is limited to a timing window of approximately 70 s (9 tREFI), and that self-refresh release requires 200 DDR2 cycles for the DLL to lock again.
Precharge Power-down Exit

The DDR2 device exits power-down mode only when the DIS_DDRCKE bit in the control register is cleared. The controller takes care of the power-down exit timing specifications tXP, tXARD, tXARDS and tCKE min.
No Operation/Command Inhibit

The no operation (NOP) command to the DDR2 has no effect on operations currently in progress. When the controller is actively accessing the DDR2 but needs to insert additional commands with no effect, the NOP command is given.

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The command inhibit command is the same as a NOP command, except that the DDR2 is not chip-selected. When the controller is not accessing any DDR2 external banks, the command inhibit command is given. Refresh Rate Control The DDR2 refresh rate control register (DDR2RRC) provides a flexible mechanism for specifying the auto-refresh timing. The DDR2 controller provides a programmable refresh counter which has a period based on the value programmed into the RDIV field of this register, which coordinates the supplied clock rate with the DDR2 devices required refresh rate. The delay (in number of DDR2_CLK cycles) desired between consecutive refresh counter time-outs must be written to the RDIV field. A refresh counter time-out triggers an auto-refresh command to the external DDR2 bank. Write the RDIV value to the DDR2RRC register before the DDR2 power-up sequence is triggered. Change this value only when the DDR2 controller is idle. To calculate the value that should be written to the DDR2RRC register, use the following equation: RDIV = (DDR2_CLK t REFI) (tRAS + tRP) where: DDR2 Clock = DDR2 system clock frequency tREFI = DDR2 maximum average auto refresh period (in us). (Note tREFI = tREF/Number of row addresses) tRAS = Active to precharge time (DDR2_RAS bit in the DDR2CTL1 register) in number of clock cycles tRP = RAS to precharge time (in the DDR2CTL1 register) in number of clock cycles This equation calculates the number of clock cycles between the required distributed refreshes, and subtracts the required delay between bank activate commands to the same bank (tRC = tRAS + tRP). The tRC value is

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subtracted, so that in the case where a refresh time-out occurs while a DDR2 cycle is active, the refresh rate specification is guaranteed to be met. The result from the equation should always be rounded down to an integer. The tRFC field in (DDR2RRC) provides the row refresh cycle time. (Required time after receiving the refresh command and until row refresh done). Below is an example of the calculation of RDIV for a typical DDR2 memory in a system with a 200 MHz clock. = 200 MHz tREFI = 7.8 s tRAS = 9 cycles tRP = 3 cycles
DDR2_CLKx

The equation for RDIV yields: 6 6 RDIV = (200 10 7.8 10 ) (9 + 3) = 1548 clock cycles. This means RDIV is 0x614 and the DDR2RRC register bits 130 should be written with 0x60C. Note that the RDIV bit must be programmed to a non-zero value if the DDR2 controller is enabled. When RDIV = 0, operation of the controller is not supported and can produce undesirable behavior. Values for RDIV can range from 0x001 to 0x3FFF. refresh interval The consumer parts t(t For
REFI) may change with the application used. REFI =7.8 s while for industrial and automo-

tive parts tREFI =3.9 s.

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Data Mask The DDR2 controller provides two DDR2_DM1-0 pins. Both pins (for each byte) should be connected to the DDR2 DM pins. The meaning of this pin is significant, based on the fact that the minimum burst length is 4 and a burst is not divisible. The DDR2_DM1-0 pins are used to mask the data on both edges of the DQS signal during writes in cases less than 4 sequential writes, for example a single write need to mask the data for the next sequential 3 writes. useful monitoring during The commands.pins are assertedfor performancethat the controller is write When they indicate
DDR2_DM1-0

masking unwanted data writes that cause performance penalties. For reads, the controller does not latch the data from the burst. Resetting the Controller Like any other peripheral, the DDR2 controller can be reset by hard- or a soft reset. Both reset modes pull the DDR2_CKE pin asynchronously low. Since DDR2_CKE drops asynchronously and the PLL goes into bypass mode (hardware reset) immediately after reset, timing parameter cannot be met, causing data loss. The DDR2 device must be re-initialized and the DDR2 DLL must be re locked to use the DDR2 again. Running controller.reset (
RESETOUT

pin as an input) does not reset the DDR2

Automated Initialization Sequence DDR2 SDRAM must be powered up and initialized in a predefined manner. After the DDR2PSS bit is set in the DDR2CTL0 register, the DDR2 controller starts the power-up initialization sequence which occurs in the following order. Note that this procedure is performed by the DDR2 controller and user intervention is not required.

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Table 4-14. DDR2 Initialization Sequence

Step 1 2 3 4 5 6 7 Action DDR2CKE high, drive a NOP command. Wait a minimum of 400 ns (with NOP or DESELECT commands). Issue a precharge all command. tRP period DDR2CTL4 DDR2CTL5 Hard coded bit mask Hard coded bit mask Wait (Timing Specification) Register Read

Issue a load EMR(2) command to initialize operat- tMRD period ing parameters. Issue a load EMR(3) command to initialize operat- tMRD period ing parameters. Issue a load EMR command. Enable memory DLL tMRD period (clear bit 0), all other operating parameters cleared. Issue a load EMR command. Reset memory DLL tMRD period (set bit 8), all other operating parameters cleared. Trigger a 200 cycle counter for memory DLL lock. Issue a precharge all command. Issue four auto refresh commands. Issue a load EMR command without resetting the memory DLL (bit 8), to initialize operating parameters. Wait for the 200 cycle counter (step 7) to be expired Issue a load EMR command OCD default operation by setting bits A97. All other operating parameters are cleared. Issue a load EMR command OCD exit operation by clearing bits A97 and initialize operating parameters. Start the DLL external bank calibration DDR2 ready for user access tMRD period tRP period 4 tRFC period tMRD period

8 9 10

DDR2CTL2

11 12

Hard coded bit mask DDR2CTL3

13

tMRD period

15 16

EPCTL (ext bank select)

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Initialization Time

After setting the power-up start bit, the controller starts internal and external calibration routines which are described below. The actual cycles may vary due to different timing specifications. Best case (one external DDR2 bank assigned). The entire power up requires 680 DDR2 initialization + 660 external bank calibration = around 1340 DDR2 cycles. Worst case (all external DDR2 banks assigned). Entire power up requires 680 DDR2 initialization + (4 x 660 external bank calibration) = around 3320 DDR2 cycles.
Internal DDR2 Bank Access

The following sections describe the different scenarios for DDR2 bank access.
Single Bank Access

The DDR2 controller keeps only one page open at a time if all subsequent accesses are to the same row or another row in the same bank.
Multibank Access

The processors are capable of supporting multibank operation, thus taking advantage of the DDR2 architecture. accesses depends only Operation using single versus multibank is NOT an operation on the address to be posted to the device, it mode. Any first access to DDR2 bank (A) forces an activate command before a read or write command. However, if any new access falls into the address space of the other banks (B, C, D, E, F, or H) the controller leaves bank (A) open and activates any of the other banks (B, C, D, E, F, or H). Bank (A) to bank (B) active time is controlled by tRRD. This scenario is repeated

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until all eight banks (AH) are opened and results in an effective page size of up to eight pages. This is because the absence of latency allows switching between these open pages (as compared to one page in only one bank at a time). Any access to any closed page in any opened bank (AH) forces a precharge command only to that bank. If, for example, two external port DMA channels are pointing to the same internal DDR2 bank, this always forces precharge and activation cycles to switch between the different pages. However, if the two external port DMA channels are pointing to different internal DDR2 banks, there is no additional overhead. See Figure 4-19.
Access to page x Bank A Access to page y Bank B Access to page x Bank C Access to page y Bank D Bank D Bank C Access to page y Bank B Access to page x Bank A

Single bank access

Multibank access

Figure 4-19. Single Versus Multibank Access

Force Activation Window

Traditionally, SDRAM has operated with a maximum of 4 internal banks. However, with DDR2 some higher-density devices will support 8 individual banks. For this reason, JEDEC has limited the number of banks that may be activated within a set period.

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DDR2 devices support a new timing parameter called four active banks window (tFAW). This is the minimum amount of time that must pass before more than four ACTIVE (ACT) commands may occur. It is acceptable to have more than 4 banks open simultaneously, but the additional ACT command(s) must be spaced out past the tFAW(min) window. As shown in Figure 4-20, tRCD for the fourth opened bank is complete at T8. To satisfy tFAW(min), the fifth ACT command cannot occur until T11. Furthermore the controller supports four external memory selects containing each DDR2. All external banks (DDR2_CSx) provide multibank support, so the maximum number of open pages is 8 x 4 = 32 pages.
T0 DDR2_CLKx DDR2_CLKx/ T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

COMMAND

ACT

READ

ACT

READ

ACT

READ

ACT

READ

NOP

NOP

NOP

ACT

BA0, BA1, BA2

Bank A

Bank A tRDD(min)

Bank B

Bank B tRDD(min)

Bank C

Bank C tRDD(min)

Bank D

Bank D tRDD(min)

Bank E

tFAW(min)

Figure 4-20. Bank Activation for a 8 Banked Device precharge and activation cycles by map Multibank access reduces different internal DDR2 banks driven by ping opcode/data among the (DDR2_BA2-0) pins and external memory selects (DDR2_CS3-0).
Multi-Bank Operation with Data Packing

A logical address corresponds to 2 physical addresses. Consequently a physical address for example of 1024 x 16 page size translates into a logical address of 512 x 16 words to satisfy the packing. According to this all row addresses are shifted by 2.

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A populated DDR2 of 8M x 16 x 8 with 1K words page size connected to external bank 0 has a logical mapping as follows. Page Interleaving (DDR2ADDRMODE bit = 0):
0x200000 0x2001FF 0x200200 0x2003FF 0x200400 0x2005FF 0x200600 0x2007FF 0x200800 0x2009FF 0x200A00 0x200BFF 0x200C00 0x200DFF 0x200E00 0x201000 logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical start address int bankA end address int bankA start address int bankB end address int bankB start address int bankC end address int bankC start address int bankD end address int bankD start address int bankE end address int bankE start address int bankF end address int bankF start address int bankG end address int bankG start address int bankH end address int bankH

Bank Interleaving (DDR2ADDRMODE bit = 1):

0x200000 0x2001FF 0x600000 0x6001FF 0xA00000 0xA001FF 0xE00000 0xE001FF 0x1200000 0x12001FF 0x1600000 0x16001FF 0x1A00000 0x1A001FF 0x1E00000 0x1E001FF logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical start address int bankA end address int bankA start address int bankB end address int bankB start address int bankC end address int bankC start address int bankD end address int bankD start address int bankE end address int bankE start address int bankF end address int bankF start address int bankG end address int bankG start address int bankH end address int bankH

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Fixed Timing Parameters

The timing specifications below are fixed by the controller. tMRD (mode register delay). Required delay time to complete the mode register write. This parameter is fixed to 2 cycles. tRC (row access cycle). Required delay time to open and close a single row. This parameter is fixed to tRC =tRAS + tRP cycles. tCCD (column to column delay). Required delay between two column accesses (read/write). This parameter is fixed to 2 cycles. tXSNR (exit self-refresh with non-read). Required delay to exit the self-refresh mode with a non read command. This parameter is fixed to tXSNR = tRFC + 4 cycles. tXSRD (exit self-refresh with read). Required delay to exit the self-refresh mode with a read command. This parameter is fixed to tXSRD = 200 cycles. The DDR2 controller controls the following ODT related timing parameters, no user programming is required. tANPD (ODT to power-down entry latency) tAXPD (ODT to power down exit latency) tAOND (ODT turn on delay) tAOFD (ODT turn off delay) tAON (ODT turn on time) tAOF (ODT turn off time)

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16-Bit Data Storage and Packing

The processors use logical addressing when an external memory smaller than 32 bits is used. Logical addresses require multiple external addresses seen by the memory correspond to a single internal address, depending on the width of the memory being accessed. The external physical address map is shown in Table 4-15. Table 4-15. DDR2 Address Memory Map
Bus Width External Memory Bank 0 1, 2, 3 Internal Logical Address (supported memory map) 0x0020_0000 0x007F_FFFF 0x0400_0000 0x047F_FFFF 0x0800_0000 0x087F_FFFF 0x0C00_0000 0x0C7F_FFFF External Physical Address (on ADDR230) 0x40_0000 0xFF_FFFF 0x00_0000 0xFF_FFFF

16-bit 16-bit

External Instruction Fetch

For more information, see External Instruction Fetch on page 4-42.

Address For DDR2 Types

Table 4-16 provides addressing for various sizes of DDR2 DRAM memory. Table 4-16. Translation of Logical to Physical Addressing for DDR2
DDR2 Device 256 Mb (x16) Physical Address Range Mapped to Memory Device 0x60 0000 0x15F FFFF Mapping Between External Port Address Range and Memory Device 0x20 0000 0xFF FFFF 0x00 0000 0x1F FFFF

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Table 4-16. Translation of Logical to Physical Addressing for DDR2

DDR2 Device 512 Mb (x16) 1 Gb (x16) Physical Address Range Mapped to Memory Device 0x60 0000 0x25F FFFF 0x60 0000 0x45F FFFF Mapping Between External Port Address Range and Memory Device 0x020 0000 0x1FF FFFF 0x000 0000 0x01F FFFF 0x020 0000 0x3FF FFFF 0x000 0000 0x01F FFFF

Operating Modes
The following sections provide on the operating modes of the DDR2 interface. Address Mapping To access DDR2, the DDR2 controller multiplexes the internal 32-bit non-multiplexed address into three portions: Row address bits Column address bits Bank address bits The non multiplexed address that is seen from the core/DMA is referred to as IA310 in the following sections.
Address Translation Options

To provide flexible addressing, DDR2ADDRMODE (bit 14 in the DDR2CTL0 register) is used to select the address mapping schemepage interleaving (default) or bank interleaving.

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Page Interleaving Map

Programming the DDR2ADDRMODE bit to 0 selects the page interleaving scheme. In this scheme consecutive pages fall in consecutive banks. The bank address bits follow the most significant column address bits. This is shown in Figure 4-21.
31
Unused Row Address Bank Address Column Address

Figure 4-21. Core Address Mapping to Row, Column Addresses (Page) One advantage of the page interleaving is that the effective page size is up to four pages (assuming four banks activated) and all the addresses are sequential. If using delay line DMA mode, the addresses for a long delay line are all sequential, simplifying the addressing. Moreover, DDR2 sequential addressing provides maximum performance.
Bank Interleaving Map

Programming the DDR2ADDRMODE bit to 1 selects the bank interleaving scheme. In this scheme consecutive pages sit in the same bank. The bank address bits follow most significant row address bits. This is shown in Figure 4-22.
31
Unused Bank Address Row Address Column Address

Figure 4-22. Core Address Mapping to Row, Column Addresses (Bank) One advantage of bank interleaving is that the effective page size is also up to four pages (assuming four banks activated) but the addresses of the four pages are not sequential. If the program uses two external port DMAs pointing to the DDR2 space, this scheme has advantages since every bank has its one DMA buffer addressing.

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Address Width Settings

Number Internal Banks (DDR2BC). The controller assumes the DDR2 is comprised of eight bank devices. However, DDR2 can use four bank devices by not connecting the DDR2_BA2 pin and programming the DDR2BC bits in the DDR2CTL0 register. The external bank addresses are decoded as shown in Table 4-17. Table 4-17. External Memory Address Bank Decoding
IA[27] 0 0 1 1 IA[26] 0 1 0 1 External Bank Bank 0 Bank 1 Bank 2 Bank 3

Row Address Width (DDR2RAW). These bits in the DDRCTL0 register determine the row width of the DDR. The DDR2RAW bits can be programmed for row widths of 8 to 15. Column Address Width (DDR2CAW). The DDR2 memory control register also includes external bank specific programmable parameters. The external bank can be configured for a different DDR2 size. The DDR controller determines the internal DDR2 page size from the X16DE and DDR2CAW parameters. Page sizes of 256, 512, 1K, 2K and 4K words are supported. addresses depends the row address width The mapping of theaddress width ( on ), and the address mode ( ), column
DDR2RAW DDR2CAW

bit (DDR2ADDRMODE) setting.

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16-Bit Address Mapping

Even if the external data width is 16 bits, the processor supports only 32-bit data accesses. The DDR2 controller performs two 16-bit accesses to get and place 32-bit data. The controller takes the IA address and appends one extra bit to the LSB to generate the address externally. For example, if the processor core requests address 0x20 0000 for a 32-bit access, the controller performs two 16-bit accesses at 0x40 0000 and 0x40 0001, using MS0 to get one 32-bit data word.

The

X16DE

bit must always be set.

Address Map Tables

The row address and column address mappings for 16-bit addresses are shown in Table 4-18 through Table 4-21. The row, bank and column addresses are multiplexed to the A14A0 and BA2BA0 pins of the processor. Table 4-18 through Table 4-21 also show the mapping of the internal address [IA] to the external address. The mapping of the address depends on row address width, column address width, the number of internal banks, and the external I/O width. Table 4-18 shows DDR2ADDRMODE = 0, DDR2RAW = 100 (12), DDR2CAW = 10 (10), DDR2BC = 10. Table 4-18. 16-bit Address Mapping (8 Banks, Page Interleaving)
SHARC Pin DDR2_BA2 DDR2_BA1 DDR2_BA0 DDR2_ADDR[12] DDR2_ADDR[11] IA[23] Column Address Row Address Bank Address IA[11] IA[10] IA[9] DDR2 Pin BA[2] BA[1] BA[0] A[12] A[11]

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Table 4-18. 16-bit Address Mapping (8 Banks, Page Interleaving) (Contd)

SHARC Pin DDR2_ADDR[10] DDR2_ADDR[9] DDR2_ADDR[8] DDR2_ADDR[7] DDR2_ADDR[6] DDR2_ADDR[5] DDR2_ADDR[4] DDR2_ADDR[3] DDR2_ADDR[2] DDR2_ADDR[1] DDR2_ADDR[0] IA[8] IA[7] IA[6] IA[5] IA[4] IA[3] IA[2] IA[1] IA[0] 1/0 Column Address Row Address IA[22] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] Bank Address DDR2 Pin A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]

Table 4-17 shows DDR2ADDRMODE = 0, DDR2RAW = 100 (12), DDR2CAW = 11 (11), DDR2BC = 01(four banks). Table 4-19. 16-bit Address Mapping (4 Banks, Page Interleaving)
SHARC Pin DDR2_BA1 DDR2_BA0 DDR2_ADDR[13] DDR2_ADDR[12] DDR2_ADDR[11] IA[9] DDR2_ADDR[10] DDR2_ADDR[9] DDR2_ADDR[8] DDR2_ADDR[7] IA[8] IA[7] IA[6] IA[23] IA[22] IA[21] IA[20] IA[19] A[12] A[11] A[10] A[9] A[8] A[7] Column Address Row Address Bank Address IA[11] IA[10] DDR2 Pin BA[1] BA[0]

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Table 4-19. 16-bit Address Mapping (4 Banks, Page Interleaving) (Contd)

SHARC Pin DDR2_ADDR[6] DDR2_ADDR[5] DDR2_ADDR[4] DDR2_ADDR[3] DDR2_ADDR[2] DDR2_ADDR[1] DDR2_ADDR[0] Column Address IA[5] IA[4] IA[3] IA[2] IA[1] IA[0] 1/0 Row Address IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] Bank Address DDR2 Pin A[6] A[5] A[4] A[3] A[2] A[1] A[0]

Table 4-20 shows DDR2ADDRMODE = 1, DDR2RAW = 100 (12), DDR2CAW = 10 (10), DDR2BC = 10 (eight banks). Table 4-20. 16-bit Address Mapping (8 Banks, Bank Interleaving)
SHARC Pin DDR2_BA2 DDR2_BA1 DDR2_BA0 DDR2_ADDR[12] DDR2_ADDR[11] DDR2_ADDR[10] DDR2_ADDR[9] DDR2_ADDR[8] DDR2_ADDR[7] DDR2_ADDR[6] DDR2_ADDR[5] DDR2_ADDR[4] DDR2_ADDR[3] IA[8] IA[7] IA[6] IA[5] IA[4] IA[3] IA[2] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] Column Address Row Address Bank Address IA[23] IA[22] IA[21] DDR2 Pin BA[2] BA[1] BA[0] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3]

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Table 4-20. 16-bit Address Mapping (8 Banks, Bank Interleaving) (Contd)

SHARC Pin DDR2_ADDR[2] DDR2_ADDR[1] DDR2_ADDR[0] Column Address IA[1] IA[0] 1/0 Row Address IA[11] IA[10] IA[9] Bank Address DDR2 Pin A[2] A[1] A[0]

Table 4-21 shows DDR2ADDRMODE = 1, DDR2RAW = 100 (12), DDR2CAW = 11 (11), DDR2BC = 01(four banks). Table 4-21. 16-bit Address Mapping (4 Banks, Bank Interleaving)
SHARC Pin DDR2_BA1 DDR2_BA0 DDR2_ADDR[13] DDR2_ADDR[12] DDR2_ADDR[11] DDR2_ADDR[10] DDR2_ADDR[9] DDR2_ADDR[8] DDR2_ADDR[7] DDR2_ADDR[6] DDR2_ADDR[5] DDR2_ADDR[4] DDR2_ADDR[3] DDR2_ADDR[2] DDR2_ADDR[1] DDR2_ADDR[0] IA[8] IA[7] IA[6] IA[5] IA[4] IA[3] IA[2] IA[1] IA[0] 1/0 IA[9] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] IA[11] IA[10] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] Column Address Row Address Bank Address IA[23] IA[22] DDR2 Pin BA[1] BA[0]

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Parallel Connection of DDR2s To specify a DDR2 system, multiple possibilities are given based on the different memory sizes. For a 16-bit I/O capability, the following memory sizes can configured. 1 x 16-bit/page 512 words 2 x 8-bit/page 1k words 4 x 4-bit/page 2k words The DDR2s page size is used to determine the system you select. All three systems have the same external bank size, but different page sizes. Note that larger page sizes, allow higher performance but larger page sizes require more complex hardware layouts. connecting Even ifthe cluster as DDR2s in parallel, the controller always considers one external DDR2 bank because all address and control lines feed the parallel parts.
Buffering Controller for Multiple DDR2s

If using multiples DDR2s or modules, the capacitive load will exceed the controllers output drive strength. In order to bypass this problem an external register (SSTL18 class) can be used for decoupling by setting bit 24 in DDR2CTL0 register. This adds a cycle of data buffering to read and write accesses. Read Optimization The best throughput numbers for reads are achievable only when the DDR2OPT bit in the DDR2CTL0 register is set. To achieve better performance for reads, predictive addresses need to be given to the DDR memory. The predictive address given to the memory depends on the DDR2MODIFY bit setting. If the DDR2MODIFY value is 2 then the address + 2 is given

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predictively on the DDR address pins. Programs have the option whether to use read optimization or not. It is advisable to use read optimization for core and DMA transfers, with a constant modifier to achieve better performance. With multiple channels running with ping-pong accesses, use arbitration freezing to get better throughput. if optimization is enabled and modifier FortoSIMD accesses, modifier is changed, it remainsthe 2). The is set 2 (even if the at throughput is at maximum if optimization is enabled for sequential accesses. But in the case of non sequential accesses, throughput is affected by enabling optimization.
Read Optimization Modifier

The predictive address given to the memory depends on the DDR2MODIFY bit values. For example, if the DAG modifier = 2, the DDR2MODIFY value should also be 2, in which case the address + 2 is the predictive value provided to the DDR2 address pins. Programs may choose to determine whether read optimization is used or not. If read optimization is disabled, then each read takes 11 DDR2CLK cycles for a CAS latency of 3, even for sequential reads. With read optimization enabled, 32 sequential reads, with offsets ranging from 0 to 15, take only 42 DDR2CLK cycles. Read optimization should not be enabled while reading at the external bank boundaries. For example, if DDR2MODIFY = 1, then 32 locations in the boundary of the external banks should not be used. These locations can be used without optimization enabled. If DDR2MODIFY = 2, then 64 locations cannot be used at the boundaries of the external bank (if it is fully populated). It should be noted that read optimization always improves the read performance (if the access modifiers are deterministic and accesses are not interrupted) by a factor of approximately 45.

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Optimization extracts the data from the incoming burst as described below. For modifier = 1 the controller does not need to extract the correct data from the burst of 4 and has the best data throughput. For modifier = 2 the controller extracts every second data from the burst of 4 and has the second best data throughput. By default, is enabled ( = 1) with a modifier of the( read optimizationRead optimization assumes that 1 = 1).
SDROPT DDR2MODIFY

the DDR2 pointer has a constant modifier. For non-sequential accesses, turning off optimization provides better results.
Core Accesses

Any break of sequential reads of full page accesses can cause a throughput loss due to a maximum of eight extra reads. Listing 4-4 shows how to achieve maximum throughput using core accesses. Any cycle between consecutive reads to an DDR2 address results in non-sequential reads. Listing 4-4. Maximum Throughput Using Sequential Reads
ustat1=dm(DDR2CTL0); bit set ustat1 DDR2OPT|DDR2MODIFY1; dm(DDR2CTL0)=ustat1; nop; I0 = DDR2_addr; M0 = 1; Lcntr = 1024, do(PC,1) until lce; R0 = R0 + R1, R0 = dm (I0, M0);

The example shows read optimization can be used efficiently using core accesses. All reads are on the same page and it takes 2088 core cycles (core to DDR2 clock ratio 2:1) to perform 1024 reads.

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Without read optimization, 1024 reads use 5125 core cycles if all of the reads are on the same page, non-sequential reads takes 9220 core cycles. With read optimization (Listing 4-5), 1024 reads take 10262 core cycles, due to the breaking of sequential reads. Listing 4-5. Interrupted Reads With Read Optimization
ustat1=dm(DDR2CTL0); bit set ustat1 DDR2OPT|DDR2MODIFY2; dm(DDR2CTL0)=ustat1; nop; I0 = DDR2_addr; M0 = 2; Lcntr = 1024, do(PC,2) until lce; R0 = R0 + R1, R0 = dm (I0, M0); NOP;

Note the above mentioned cycles may vary based on different latency and timing parameters programmed.
DMA Access

Listing 4-6 shows an example of external port DMA using read optimization. Listing 4-6. EPDMA With Read Optimization
ustat1=dm(DDR2CTL0); bit set ustat1 DDROPT|DDRMODIFY2; dm(DDR2CTL0)=ustat1; nop; r0=DFLSH; dm(DMAC1)=r0; r0=intmem; r0=2; dm(IIEP1)=r0; dm(IMEP1)=r0;

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r0=N; r0=2; r0=extmem; r0=DEN; dm(DMAC1)=r0;

dm(ICEP1)=r0; dm(EMEP1)=r0; dm(EIEP1)=r0;

Notes on Read Optimization

The core and the DMA engine take advantage of the major improvements during reads using read optimization. However, in situations where both the core and DMA need to read from different internal memory banks with different modifiers at the same time, programs need to choose whether or not to use optimization. Note that from a throughput prospective, external port arbitration also is a factor. A good rule is that the requester with the higher priority should have the same modifier as DDR2MODIFY. In other words, if DMA has a higher priority over the core, then the DMA modifier should match the DDR2MODIFY setting.

Read optimization is only effective if the accesses are uninterrupted.

Self-Refresh Mode This mode causes refresh operations to be performed internally by the DDR2, without any external control. This means that the controller does not generate any auto-refresh cycles while the DDR2 is in self-refresh mode. Self-refresh entrySelf-refresh mode is enabled by writing a 1 to the DDR2SRF bit of the DDR2 memory control register (DDR2CTL0). This deasserts the DDR2CKE pin and puts the DDR2 in self-refresh mode if no access is currently underway. The DDR2 remains in self-refresh mode for at least tRAS and until an internal access (read/write) to DDR2 space occurs or the SREF_EXIT bit in the DDR2CTL0 register is set.

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entry command automatically disables the The self-refreshTherefore its release command (exit) requiresDDR2 memory DLL. additional stall cycles until the DLL has re-locked. Self-refresh exit. When any DDR2 access occurs, the controller asserts DDR2CKE high which causes the DDR2 to exit from self-refresh mode. The controller waits to meet the tXSNR specification (exit with no read command) or the tXSRD specification (exit with read command). Here is a significant difference; releasing with a read command requires 200 DDR2 cycles (since the memory DLL needs to re read memory). System clock during self-refresh mode. Note that the DDR2CLK is not disabled by the controller during self-refresh mode. However, software may disable the clocks by setting the DIS_DDR2CTL bit in the DDR2CTL0 register. Programs should ensure that all applicable clock timing specifications are met before the transfer to DDR2 address space (which causes the controller to exit the self-refresh mode). If a transfer occurs to DDR2 address space when the DIS_DDR2CTL bit is cleared, an internal bus error is generated, and the access does not occur externally. The following steps are required when using self-refresh mode. 1. Set the DDR2SRF bit to enter self-refresh mode. 2. Poll the DDR2SRA bit in the DDR2 status register (DDR2STAT) to determine if the DDR2 has already entered self-refresh mode. 3. Optionally: set the DIS_DDR2CTL bit to freeze DDR2_CLK. 4. Optionally: clear the DIS_DDR2CTL bit to re-enable DDR2_CLK. DDR2 access occurs and the DDR2 exits from self-refresh mode.

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minimum The command istime between a subsequent self-refresh entry and exit the t cycle. If a self-refresh request is issued during any external port DMA, the DDR2 controller grants the request with the tRAS cycle and continues DMA operation afterwards. Single-Ended Data Strobe DDR2 data strobe mode is specified for either single ended or differential mode, depending on the setting of the EMR register enable DDR2_DQS mode bit. The timing advantages of differential mode are realized in system design. The method by which the DDR2 pin timing is measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DDR2_DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DDR2_DQSS and its complement, DDR2_DQS. This distinction in timing methods is guaranteed by design and characterization. When differential data strobe mode is disabled via the EMR register, the complementary pin, DDR2_DQS, must be tied externally to VSS through a 20 to 10 k resistor to insure proper operation. On Die Termination (ODT) The DDR2 controller contains a separate pin (DDR2_ODT) that controls on-die termination. By default this pin is deasserted. If during power-up, the ODT register field in the DDR2CTL3 register is programmed with any Rtt value, the ODT pin is asserted after the power-up sequence has finished. The level can be changed by forcing another power-up sequence which disables Rtt resistance in the ODT field. After completion, the ODT pin is deasserted. Note that the ODT pin control is independent on the DDR2 data access directions (read or write).
RAS

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Additive Latency Posted CAS operation helps maintain efficient and sustainable bandwidths in DDR2 SDRAM on the command and data bus. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD, period). The command is held for the time of the additive latency (AL) before it is issued inside the device. The read latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a program wants to issue a read/write command before the tRCDmin, then AL (greater than 0) must be written into the EMR(1) register. The write latency (WL) is always defined as RL 1 (read latency 1) where read latency is defined as the sum of additive latency plus CAS latency (RL = AL + CL). Read or write operations using AL allow seamless bursts (refer to seamless operation timing diagram examples in read burst and write burst section). Note that while the controller supports this feature, performance has nothing to do with the AL settings written to EMR1. Forcing DDR2 Commands The controller has some specific bits which can be used to aid in debug and in specific system solutions. If for example the part enters precharge power-down mode, explicit auto refresh commands need to be triggered (JEDEC standard). Or if during runtime the mode register settings and clock speed are changed. By setting the SDPSS bit after reset, all mode registers are automatically updated. The SDPSS bit should be cleared when using forced commands.
Force Precharge All

Whenever an auto-refresh or a mode register set command is issued, the internal banks are required to be in idle state. Setting bit 21 (=1) forces a precharge all command to accomplish this. If the precharge all command

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is not issued, the auto-refresh and mode register set commands can be illegal depending on the current state. Note that it is a good practice always to perform a force precharge all command before a forced refresh/mode register command.
Force Load Mode Register

Programs can use the Force LMR command by setting bit 22 (=1) in the DDR2CTL0 register. The Force LMR bit allows changes to the MODE register based settings during runtime. These settings include bit 22 (=1) for MR command (settings DDR2CTL2 register).
Force Auto-Refresh

Bit 20 (=1) in the DDR2CTL0 register forces the auto refresh to be immediately executed (not waiting until the refresh counter has expired). This is useful for test purposes but also to synchronize the refresh time base with a system relevant time base.
Force Extended Mode Register 13

Programs use the Force extended mode register 13 commands (DDR2CTL0 register) by setting: bit 23 (=1) for EMR1 command (settings DDR2CTL3 register) bit 12 (=1) for EMR2 command (settings DDR2CTL4 register) bit 17 (=1) for EMR3 command (settings DDR2CTL5 register) This allows programs to initialize or change the content of the EMR register.
Force DLL External Bank Calibration

The last step during power up is the post calibration of the external DDR2 banks. This command is enabled by setting bit 13 (=1) in the DDR2CTL0 register. If enabled the DDR2 controller posts 300 dummy reads for calibration between the internal DDR2 clock and the DDR2_DQS1-0

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pins which are driven during the read. Note the calibration is done separately for each assigned external bank.

Shared Memory Interface (ADSP-2146x)

The ADSP-2146x processor supports connections to a common shared external memory of up to two other ADSP-2146x processors. These connections create shared external bus processor systems.

Features
Shared memory space for all four external DDR2 banks Supports shared data or instruction fetch Distributed, on-chip arbitration for the shared DDR2 bus Bus lock feature support for semaphore implementation Bus master time-out for arbitration fairness Figure 4-23 illustrates a basic shared memory system. In a system with several processors sharing the external bus, any of the processors can become the bus master. The bus master has control of the bus, which consists of the DDR2 control and address/data signals and associated control lines. the ADSP-2146x owns two separate and independent Note thatport buses, one for the AMI and the other for the DDR2. external

Pin Descriptions
The pins used by the shared external memory interface are described in the ADSP-21467/ADSP-21469 Processor Data Sheet.

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ADSP-2146x #2

CLKIN
RESET ID1-0

ADDR DATA OL CONTROL

ADSP-2146x #1

CLOCK RESET

CLKIN RESET

ADDR[18:0] DATA[15:0] CS3-0 BR2-1 CS DATA

CONTROL

ID1-0 DDR2_RAS DDR2_CAS DDR2_WE DDR2CLK[1:0] DDR2_CKE DQS[1:0] DM[1:0]

ADDRESS

DDR2 MEMORY

RAS CAS WE CLK CKE DQS DM DATA ADDR

Figure 4-23. Shared DDR2 Memory System

Functional Description
Multiple processors can share the external bus with no additional arbitration logic as shown in Figure 4-23. Arbitration logic is included on chip to allow the connection of up to two ADSP-2146x processors. The processor accomplishes bus arbitration through the BR2-1 signals which arbitrate between the two processors. The ID2-1 pins provide a unique identity for each processor in a multiprocessing system. The first processor should be assigned ID = 1, the second should be assigned ID = 2. One of the processors must be assigned ID = 1 in order for the bus synchronization scheme to function properly.

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CONTROL

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processor with = 1 holds the The(pull-up enabled) during reset. external bus control lines stable
ID

A processor in a shared memory system can determine which processor is the current bus master by reading the CRBM bits of the SYSTAT register. These bits provide the values of the ID2-1 inputs of the current bus master. 1:4 are multiple Only system. ratios of 1:2 andnot worksupportedofinunaligned processor Other ratios do because
DDR2CKR

clocks. The PCLK and CLKIN clocks are used in the arbitration logic for the shared external bus. The multiprocessor logic requires that these clocks need to be rising edge aligned to function properly. Therefore, not all core to DDR2 clock ratios are allowed in multiple processor system. The PLL bit settings PLLM/PLLD in PMCTL register need to be programmed such that the PLLM/PLLD ratio is integer (for example 15/2=7.5 fractional, is not allowed). Bus Transition Cycle The bus request (BR1-0) pins are connected between each processor in a shared memory system, where the number of BRx lines used is equal to the number of processors in the system. Each processor drives the BRx pin that corresponds to its ID2-1 inputs and monitors all others. When the slave processor needs to perform an access to the shared memory space, it needs to become bus master, it automatically initiates the bus arbitration process by asserting its BRx line at the beginning of the cycle. Later in the same cycle, the processor samples the value of the other BRx lines. The cycle in which mastership of the bus is passed from one processor to another is called a bus transition cycle (BTC). A BTC occurs when the current bus masters BRx pin is deasserted and the slaves BRx pin is asserted. The bus master can retain bus mastership by keeping its BRx pin asserted.

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By observing all of the BRx lines, each processor can detect when a bus transition cycle occurs and which processor has become the new bus master. A bus transition cycle is the only time that bus mastership is transferred. The actual transfer of bus mastership, shown in Figure 4-24, is accomplished by the current bus master three-stating the DDR2 bus signalsat the end of the bus transition cycle and the new bus master driving these signals at the beginning of the next cycle.
Bus Mastership Transfer (SREF entry + BTC + SREF exit) CLKIN

BR1

ID1

CONTROL DDR2

SREF ENTRY

SREF MODE

BR2

ID2

SREF MODE

SREF EXIT

CONTROL DDR2

DDR2 DATA

ID1 DATA

THREE-STATE

ID2 DATA

Figure 4-24. DDR2 Bus Mastership Transfer During bus transition cycle delays, execution of external accesses are delayed. When one of the slave processors needs to perform a read or write to the shared memory space, it automatically initiates the bus arbitration process by asserting its BRx line. This read or write is delayed until the processor receives bus mastership. If the read or write was generated by the processors core (not the DMA controller), program execution stops on that processor until the instruction is completed.

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requester cant interrupt a current Any slavethe shared of an ADSP-2146xwait until the DMA has DMA to memory, it has to completed. The following steps occur as a slave acquires bus mastership and performs an external read or write over the DDR2 bus. 1. The slave determines that it is executing an instruction which requires an off-chip access. It asserts its BRx line at the beginning of the cycle. Extra cycles are generated by the core processor (or DMA controller) until the slave acquires bus mastership. 2. To acquire bus mastership, the slave waits for a bus transition cycle in which the current bus master deasserts its BRx line. The slave becomes bus master in the next cycle. 3. At the end of the BTC, the current bus master releases the bus and the new bus master starts driving. During the CLKIN cycle in which the bus master deasserts its BRx output, it three-states its outputs in case another bus master wins arbitration and enables its drivers in the next CLKIN cycle. If the current bus master retains control of the bus in the next cycle, it enables its bus drivers, even if it has no bus operation to run. clock for the The fundamental members mustbus arbitration is the Therefore all bus share the same input. oscillator. Note the higher CLKIN the higher the bus arbitration speed.
CLKIN CLKIN

When the bus master stops using the bus, its BRx line is deasserted, allowing other processors to arbitrate for mastership if they need it. If no other processor is asserting its BRx line when the master deasserts its BRx, the master retains control of the bus and continues to drive the memory control signals until: 1. it needs to use the bus again 2. another processor asserts its BRx line 4-108 ADSP-214xx SHARC Processor Hardware Reference

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DDR2 Bus Mastership Transfer The DDR2 memory is shared among two ADSP-2146x processors. Both processors must have the same configured DDR2 frequency, and the same core to DDR2 clock ratio. This implies that both processors must use the same controller settings in their respective control (DDR2CTL5-0) and refresh rate (DDR2RRC) registers. The bus master ownership is switched between the processors by using additional self-refresh entry and exit commands to perform the bus transition cycle. The DDR2 memory is automatically entered in self-refresh mode before releasing the bus and its clock is three-stated for one DDR2CLK cycle. The new bus master executes a self-refresh exit command immediately after acquiring mastership. Since the DDR2 memory is in self-refresh mode during the BTC cycle the command bus state is undefined preventing it from latching invalid commands due to glitches on clock. The slave processor does not track DDR2 commands on the bus. After getting bus mastership the processor clears the current refresh counter value (DDR2RRC) for auto-refresh and issues an auto-refresh command. This simplifies the design and avoids maintaining the refresh counters in sync on both processors. The bus master transfer is executed in the five phases listed below. 1. Memory access of current bus master, slave asserts its BR signal 2. Current bus master enters SREF mode and de-asserts BR signal 3. BTC cycle 4. New bus master releases SREF mode 5. Memory access of new bus master The time for the entire bus mastership transfer is: SREF Entry (bus release) + BTC + SREF Exit (bus request) cycles

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Where: SREF Entry = 1 CLKIN + tRP cycles SREF Exit = 1 CLKIN + 8 DDR2CLK + 2x tXSNR (for non read command after self refresh exit) SREF Exit = 1 CLKIN + 4 DDR2CLK + tXSRD (for read command after self refresh exit) Bus Synchronization After Reset When a shared memory system comes out of reset (after RESET is de-asserted), the bus arbitration logic on each processor must synchronize, ensuring that only one processor drives the external bus. One processor must become the bus master, and all other processors must recognize it before actively arbitrating for the bus. The bus synchronization scheme also lets the system safely bring individual processors into and out of reset. One of the processors in the system must be assigned ID = 1 in order for the bus synchronization scheme to function properly. This processor also holds the external bus control lines stable during reset.

Busa arbitration and synchronization are disabled if the processor is in single processor system ( = 0).
ID

To synchronize their bus arbitration logic and define the bus master after a system reset, the multiple processors obey the following rules: The processor with ID = 2 de-assert its BRx line during reset. It keeps its BRx deasserted for at least two cycles after reset and until their bus arbitration logic is synchronized. After reset, a processor considers itself synchronized when it detects a cycle in which only one BRx line is asserted. The processor identifies the bus master by recognizing which BRx is asserted and updates its internal record to indicate the current master.

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The processor with ID = 1 asserts its BRx during reset and for at least two cycles after reset. If the other BRx line is asserted during these cycles, the processor with ID = 1 drives the memory control signals to prevent glitches. Although the processor with ID = 1 is asserting its BRx and driving the memory control signals during these cycles, this processor does not perform reads or writes over the bus. While in reset, the processor with ID = 1 attempts to gain control of the bus by asserting BR1. While in reset, the processor with ID = 1 drives the DDR2 signals only if it determines that it has control of the bus. For the processor to decide it has control of the bus: 1) its BR1 signal must be asserted and 2) in the previous cycle, no other processors BRx signals were asserted. The processor with ID = 1 continues to drive the DDR2 signals for two cycles after reset, as long as other BRx lines are asserted. If the processor with ID = 1 is synchronized by the end of the two cycles following reset, it becomes the bus master. If it is not synchronized at this time, it deasserts its BRx signal and stops driving the memory control signals and does not arbitrate for the bus until it becomes synchronized. When a processor has synchronized itself, it sets the BSYN bit in the SYSTAT register. Note that the BSYN bit is set after de-assertion of the RESETOUT pin for a minimum delay of 1 CLKIN cycle or more. If one processor comes out of reset after the other has synchronized and started program execution, that processor may not be able to synchronize immediately (for example, if it detects more than one BRx line asserted). If the non-synchronized processor tries to execute an instruction with an off-chip read or write, it cannot assert its BRx line to request the bus and execution is delayed until it can synchronize and correctly arbitrate for the bus.

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The FSYNC bit in SYSCTL register is provided to force synchronizing the cluster system. When set this bit enables synchronization and when cleared disables synchronization of the system. master regular operation should not be The current busreset), asduringwould result in system synchronizareset (hardware this tion problems.

Operating Modes
The following sections describe the operating modes that can be used with shared memory. Bus Mastership Time-Out Systems may need to limit how long a bus master can retain the bus. This is accomplished by forcing the bus master to deassert its BRx line after a specified number of CLKIN cycles and giving the other processors a chance to acquire bus mastership. To set up a bus master time-out, a program must load the bus time-out maximum (BMAX register, 16-bit) with the maximum number of CLKIN cycles (minus 2) that allows the processor to retain bus mastership. This equation is shown below.
BMAX

= (maximum number of bus mastership CLKIN cycles) 2

The minimum value for BMAX is 2, which lets the processor retain bus mastership for four CLKIN cycles. Setting BMAX=1 is not allowed. To disable the bus master time-out function, set BMAX=0. Each time a processor acquires bus mastership, its bus time-out counter (BCNT register, 16-bit) is loaded with the value in BMAX. The BCNT is then decremented in every CLKIN cycle in which the master performs a read or write over the bus and any other (slave) processors are requesting the bus. Any time the bus master deasserts its BRx line, BCNT is reloaded from BMAX.

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When BCNT decrements to zero, the bus master first completes its off-chip read/write and then deasserts its own BRx (any new off-chip accesses are delayed), which allows transfer of bus mastership. If BCNT reaches zero while bus lock is active, the bus master does not deassert its BRx line until bus lock is removed. Bus lock is enabled by BUSLK (bit 29 of SYSCTL register). For more information, see Bus Transition Cycle on page 4-106. access master During anythe bus (core/external port DMA), the newreleases the requesting must wait until the present master bus. The new master can not interrupt current bus master transfers. If the current master doesnt have an external transfer, it releases the bus (even before BCNT = 0). If BCNT reaches zero while bus lock bit is set, the bus master does not de-assert its BRx line until bus lock bit is cleared. Bus Lock With the use of its bus lock feature, the processor has the ability to read and modify a semaphore in a single indivisible operation a key requirement of multiple processor systems. Semaphores can be used in multiple processor systems to allow the processors to share resources such as memory. A semaphore is a flag that can be read and written by any of the processors sharing the resource. The value of the semaphore tells the processor when it can access the resource. Semaphores are also useful for synchronizing the tasks being performed by different processors in a system. on semaphores Read-modify-write operationssimple rules. can be performed if all of the processors obey two

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A processor must not write to a semaphore unless it is the bus master. When attempting a read-modify-write operation on a semaphore, the processor must have bus mastership for the duration of the operation. Both of these rules apply when a processor uses its bus lock feature, which retains its mastership of the bus and prevents the other processors from simultaneously accessing the semaphore. Bus lock is requested by setting the BUSLK bit in the SYSCTL register. When this happens, the processor initiates the bus arbitration process by asserting its BRx line. When it becomes bus master, it locks the bus by keeping its BRx line asserted even when it is not performing an external read or write. When the BUSLK bit is cleared, the processor gives up the bus by de-asserting its BRx line. While the BUSLK bit is set, the processor can determine if it has acquired bus mastership by executing a conditional instruction with the Bus Master (BM) or Not Bus Master (Not BM) condition codes, (refer to the SHARC Processor Programming Reference manual). For example:
IF NOT BM JUMP(PC,0); /* Wait for bus mastership */

If it has become the bus master, the processor can proceed with the external read or write. If not, it can clear its BUSLK bit and tries again later. A read-modify-write operation is accomplished with the following steps. 1. Request bus lock by setting the BUSLK bit. 2. Wait for bus mastership to be acquired. 3. Read the semaphore, test it, then write to it. Note that locking the bus prevents the other processor from writing to the semaphore while the read-modify-write is occurring.

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Data Transfer
The external port has two buffers, the AMI which requires two buffer for packing/unpacking 8/16-bit to 32-bit data. The DMA has a data buffer for each of the DMA channels.The AMI can access data from both the core and through DMA. The following sections describe these options.

Data Buffers
The asynchronous memory interface has two 1 deep data buffers, one each for the transmit and receive operations. These buffers pack data or instruction during external port boot. Receive Buffer Unpacking Reads from external memory are done through the 1 deep receive packing buffer (AMIRX). When an external address that is mapped to the AMI in the EPCTL register is accessed, it receives 8/16-bit data and packs the data based on the packing and control modes in the AMI control register (AMICTLx). Once a full packed word is received, the internal status signal is deasserted and new reads are allowed. The AMI provides the interface to the external data pins as well as to the processor core or to the internal DMA controller. When the AMI receives data, it is passed by internal hardware to the DMA controller or to the external port control bus, depending on which entity requested the data. Transmit Buffer Unpacking Writes to external memory are done through the 1 deep transmit packing buffer (AMITX). When an external address that is mapped to the AMI in the EPCTL register is accessed, it receives data from internal memory using the DMA controller or through direct core writes.

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Once a full word is transferred out of the AMI, the internal status signal is deasserted and new writes are allowed. No more external transfers can start while the AMI module is not empty. Whenever the AMITX buffer is empty, the DMA controller or a direct access from the processor core can write new data into the AMI. If the register is full, further writes from the core (or DMA controller) are stalled. access, data is For core and DMAsetting ofthe receivedbit. The also unpacked, depending on the the order of unpacking
PKDIS

is dependent on the MSWF bit in AMICTLx registers. External Port DMA Buffer The external port supports two DMA channels, each populated with a data buffer (DFEP10). Each data buffer is 6 locations deep and its status can be read in the DMACx register. Note the DMA channels are valid for AMI, SDRAM or DDR2 transfers. For more information, see External Port DMA on page 4-120.
Buffer Status

The entire path form a 6-stage buffer. Six writes/reads can occur to the transmit/receive buffer by the DMA before it signals a full/empty condition. Full/empty status for the DMA buffer is read by the DFS bits in the DMACx register.
Flush Buffer

The AMI and the external port DMA buffers are flushed when the FLSH bit (AMI) and DFLSH bit (external port) are set.

Core Access
For core-driven external port transfers, the instruction needs to read or write from a valid external port address.

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External Port Dual Data Fetch The dual data fetch instruction (Type 1) allows the processor to access external data from both DAGs. In such an instruction, the accesses are executed sequentially (not simultaneously as in internal memory). For example:
r4=r2+r3, r2=dm(i6,m6), r3=pm(i10,m10);

The DAG1 access (operand r2) is executed first followed by the second DAG2 access (operand r3). Conditional Instructions On the SHARC processors, almost all instruction types can be conditional. Access to external data based on a conditional instructions are allowed. For example:
r10=pass r9; If EQ r4=r2+r3, r2=dm(i6,m6);

The instruction is only executed if the condition is true.

SIMD Access
The SHARC processor supports SIMD data access from external memory for SDRAM and DDR2 memory space in normal space only. In SIMD mode, the core expects 64-bit data on a single read request and drives 64-bit data for write requests. The controller decodes the access request and if it is a SIMD read from a location N, the controller fetches data from N and N+1, irrespective of whether N is an odd or an even address.

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The memory controller then packs the data into 64 bits and sends it back along the core buses. For a SIMD write, the controller unpacks the 64-bit data given by the core and writes it to N and N+1 memory locations. The behavior of SIMD access to/from external memory is similar to the internal processor memory. The only difference is that it is supported in normal word (32-bit) address space only. Unlike internal memory access, SIMD access from external memory may have a different latency, the explicit transfer terminate first followed by the implicit transfer. SDRAM SIMD mode transfers are performed within 2 core accesses. The first access performs an explicit 32-bit access (which results in the physical space in 2x16-bit words) while the 2nd 32-bit access performs the implicit transfer. In total there are four read or write commands as shown in Table 4-22. Table 4-22. SDRAM SIMD Access
Access Explicit Implicit Logical x32 0x20 0000 0x20 0001 Physical x16 0x40 0000 = LS word 0x40 0001 = MS word 0x40 0002 = LS word 0x40 0003 = MS word Comment No Masking No Masking

SIMD mode access is not supported in the asynchronous memory interface (AMI).
DDR2 For a SIMD transfer, the controller can burst the 64-bit data given by the core and writes it to N and N+1 memory locations. Since the burst length is 4, SIMD mode transfers can be performed within one burst access.

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The first access performs the explicit 32-bit access (which results in the physical space in 2x16-bit words) while the 2nd 32-bit access performs the implicit transfer. In total there is one read or write command per burst of 4x16-bit data as shown in Table 4-23. Table 4-23. DDR2 SIMD Burst Access
Access Explicit Implicit Logical x32 0x20 0000 0x20 0001 Physical x16 0x40 0000 = LS word 0x40 0001 = MS word 0x40 0002 = LS word 0x40 0003 = MS word Comment No masking No masking

divisible. During reads, all DDR2 received Bursts are notmasked by the DDR2 controller. Fordata arewrite and on-chip single access in SISD mode, the 3rd and 4th data needs to be masked. The data masking (DDR2_DM1-0 signal) is only performed during write operations as shown in Table 4-24. Table 4-24. DDR2 SISD Access
Access Explicit only Logical x32 DM(0x200000) = R0; Physical x16 0x40 0000 = LSW 0x40 0001 = MSW 0x40 0002 = LSW 0x40 0003 = MSW Comment No masking Masking required (burst)

memory should SIMD write access to the DDR2the throughput is be even address aligned. If odd address aligned, reduced by a factor of 2. This does not apply to SIMD reads or any SISD mode. For more information on SIMD access, see the SHARC Processor Programming Reference.

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External Port DMA

The external port has two DMA channels that can use either the SDRAM/DDR2 controller or the asynchronous memory interface (AMI). The AMI controller supports DMA with an external data width of 8 or 16 bits. The SDRAM/DDR2 controllers support DMA with an external data width of 16-bits.

Features
The external port has the following features and capabilities. Two DMA channels Standard mode Chained Mode with direction on the fly Tap List Mode (Scatter/Gather) Delay Line Mode (Write to Read) All these modes can operate in circular fashion In circular operation some modes allow write back of index pointer for correct addressing of next transfer control block (TCB) Addressing from internal to external or internal to internal

DMA Parameter Registers

These registers are used to set up and control DMA through the processors external port. For information on these registers and on how to set up DMA transfers, see General Procedure for Configuring DMA on page 3-50. The registers that control external port DMA are described Table 4-25.

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Table 4-25. DMA Parameter Registers

Register IIEPx Description Internal Index Comment Internal Start Address. For delay line DMA, it serves as the delay line write index; for example, the start address of the internal memory buffer for the external write data. Internal address modifier. For delay line DMA, it serves as count for delay line writes, write block size. External start address. In delay line DMA this address is written back to internal memory once the writes completes (ICEP=0) External address modifier. External memory count, read only (alias of ICEPx) Contains address of the next descriptor in internal memory.

IMEPx ICEPx EIEPx

Internal Modifier Internal Count External Index

EMEPx ECEPx CPEPx

External Modifier External Count Chain Pointer

Table 4-26. Enhanced DMA Parameter Registers

Register ELEPx EBEPx RIEPx1 Description Circular Buffer Length External Base Read Internal Index Comment Hold circular buffer length for circular, delay line DMA, scatter/gather DMA. Hold circular start address for circular, delay line DMA, scatter/gather DMA. Contains start address of internal memory buffer to which the data read from external memory during delay line DMA reads are to be written into (alias of IIEPx during delay line read DMA). Contains number of reads from each tap list, read block size (alias of ICEPx during delay line read DMA).

RCEPx1 RMEPx1

Read Internal Count

Read External Modifier Contains external modifier to be used for delay line reads (alias of EMEPx during delay line read DMA).

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Table 4-26. Enhanced DMA Parameter Registers (Contd)

Register TCEPx TPEPx Description Tap Count Tap List Pointer Comment Holds the length of the tap list, number of taps. Applies to delay line DMA, scatter/gather DMA. Holds address of an array in internal memory which holds offsets to be used when accessing delay line DMA in external memory. The offset represents the first address of each read block. Applies to delay line DMA, scatter/gather DMA

These registers are only accessible through the TCB loading.

Functional Description
The external port DMA supports two different DMA channels with different addressing types and DMA modes described below. DMA Addressing Besides the traditional internal to external addressing type, the DMA module also supports internal to internal transfers. This is accomplished by indexing all external parameter registers with internal addresses. The DMA controller recognizes the transfer by addresses and not by an additional control bit setting. the Note thatindex DMA channel priority changes if using internal vs. external addresses. The SHARC supports another internal to internal DMA module (MTM) which has higher default priority but only supports standard DMA mode. For more information, see Chapter 6, Memory-to-Memory Port DMA.

Operating Modes
This section and Table 4-27 highlight the different DMA modes which can be used with the external port. The complete register bit descriptions

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are in External Port DMA Control Registers (DMACx) on page A-23. Table 4-27. DMACx Register Bit to Operating Modes
Bit (Name) Control Bits 0 (DEN,) 1 (TRAN) 2 (CHEN) 3 (DLEN) 4 (CBEN) 5 (DFLSH) 6 7 (WRBEN) 8 (OFCEN) 9 (TLEN) 1110 12 (INTIRT) 1513 Status Bits 1716 (DFS) 1918 20 (DMAS) 21 (CHS) 22 (TLS) 23 (WBS) 24 (EXTS) 25 (DIRS) 3126 Reserved Reserved Reserved Used Used Reserved Used Used Reserved Used Reserved Used Used Reserved Used Reserved Reserved Used Reserved Reserved Used Used Used Reserved Used Used Reserved Reserved (=0) Reserved (=1) Reserved Reserved Used Used Used Used Reserved Standard Chained Scatter/Gather Delay Line

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field indicate The additional bit-field information for the reservedreserved bits how the hardware operates internally. Reading these however does not generate a meaningful result. Standard DMA This DMA type resembles the traditional DMA type to initialize the different internal and external parameters (index, modify and count) registers and configuration of the DMA control registers. Note that the ECEP parameter register (read only) is a copy of the ICEP register. If ICEP is written, the ECEP register is updated automatically (Figure 4-25). Circular Buffered DMA Circular buffered DMA (Figure 4-26, Figure 4-27) resembles the traditional core DAG circular buffered mode by using registers for circular buffering. In this mode the DMA needs two additional registers (base and length) to support reads and writes to a circular buffer.

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SOURCE BUFFER 20 19 18 17 DESTINATION BASE ADDRESS (EBEP) DESTINATION INDEX (EIEP)

DESTINATION BUFFER 19 20 1 2

BUFFER LENGTH (ELEP) 3 2 1 SOURCE INDEX (IIEP) 16 17 18

Figure 4-26. Circular Buffering Write DMA

DESTINATION BUFFER
20 19 18

SOURCE BUFFER SOURCE INDEX (EIEP) SOURCE BASE ADDRESS (EBEP) 19 20 1 2

17

BUFFER LENGTH (ELEP) 3 2 1 16 17 18

DESTINATION INDEX (IIEP)

Figure 4-27. Circular Buffering Read DMA

SOURCE BUFFER DESTINATION BUFFER 1 2 3 4

20 19 18
17

DESTINATION INDEX

3 2 1

SOURCE INDEX

18 19 20

Figure 4-25. Standard Write

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Note circular operation is available for all operating modes (standard, Chained, tap list and delay line DMA). Chained DMA Mode Chained DMA is used to support automated access by a linked list (repetitive reads and writes to a defined location defined by the individual TCBs). Setting the CHEN bit, the corresponding TCB storage must be selected (for non-circular or circular mode). See TCB Memory Storage on page 3-32. Note that for the delay line DMA the CHEN bit must be set (not optional).
Data Direction on the Fly

The SHARC processors allow a change of external port data direction for each individual TCB in a chain sequence. As shown in Listing 4-7, the CPDR bit of the external port chain pointer register (CPEPx) changes the data flow direction. If CPDR is cleared (=0) writes to internal memory are performed, if CPDR is set (=1), internal memory reads are performed. This works similar to the PCI bit. The OFCEN and CHEN bits in the DMACx register must be set (=1) to enable this functionality. Listing 4-7. Changing DMA Direction
.section/pm seg_dmda; /* EP TCB storage order CP-EM-EI-C-IM-II */ .var TCB1[6] = 0 , M , extbuffer , N , M , buffer; .var TCB2[6] = 0 , M , extbuffer , N , M , buffer; .section/pm seg_pmco; R0=0; dm(CPEP0)=R0; r0 = DEN|CHEN|OFCEN; /* clear CPx register */ /* enable DMA channel */

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dm(DMAC0)=r0; R2=(TCB1+5) & 0x7FFFF; R2=bset R2 by 19; dm(TCB2)=R2; R2=(TCB2+5) & 0x7FFFF; /* load IIx address of next TCB and mask address */ /* set PCI bit */ /* write address to CPx location of current TCB */ /* load IIx address of next TCB and mask address*/ R2=bset R2 by 19; R2=bset R2 by 20; dm(TCB1)=R2; dm(CPEP0)=R2; /* clear PCI bit */ /* set CPDR bit */ /* write address to CPx location of current TCB */ /* write IIx address of TCB1 to CPx register to start chaining*/

is the If chainingandenabled withdeterminedbit set then the in thebit has bit no effect, direction is by the
OFCEN TRAN CPDR CPEP

register. Write Back Circular Index Pointer Operating the DMA in circular mode requires some special considerations. The index pointer of start address within the buffer may wrap around for the case if IC IM > EL or does not finish if IC IM < EL. In both cases the TCB start address is no longer valid. Setting the WRBEN bit writes (at the end of current TCB block) the current index address + 1 into the TCB memory which is the start address for the next TCB. This bit is only selectable for chained DMA mode, for tap list and delay line modes this bit is hardwired to 0 or 1.

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Scatter/Gather DMA The purpose of scatter/gather DMA (Table 4-28, and Figure 4-28 through Figure 4-31 on page 4-133) is the transfer of data from/to non contiguous memory blocks. The scatter/gather DMA type is a fixed block size scatter/gather DMA that relies on tap list entries in internal memory to calculate the external address to scatter/gather the DMA. If the DMA direction is external write (TRAN = 1) then it is a scatter DMA. If TRAN = 0 then it is a gather DMA. This mode also supports chained and circular buffer chained DMAs. Table 4-28. Read/Write Index Pre-Modify (Scatter/Gather DMA)
Pre-Modify Address Equation EIEP + TPEP[TCEP] + (EMEPx ICEP) EIEP + TPEP[0] + EMEPx1 EIEP + TPEP[0] + EMEPx2 EIEP + TPEP[0] + EMEPx3 EIEP + TPEP[0] + EMEPxN EIEP + TPEP[1] + EMEPx1 EIEP + TPEP[1] + EMEPx2 EIEP + TPEP[1] + EMEPx3 EIEP + TPEP[1] + EMEPxN EIEP + TPEP[M] + EMEPx1 EIEP + TPEP[M] + EMEPx2 EIEP + TPEP[M] + EMEPx3 EIEP + TPEP[M] + EMEPxN N M N 1 Blocksize N Result Tap 0

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Pre Modified Read/Write Index

For scatter/gather DMA, the tap list modifiers are employed and the number of taps is determined by the tap list count register (TCEPx). The number of sequential reads (block size) from every tap is determined by the internal count register (ICEPx), and is the same for every tap. The read/write pointer in external index register (EIEPx) serves as the index address for these read/writes. TL[N] is the first tap list entry in the internal memory as pointed by the TPEP, the tap list pointer. The tap list entries are 27-bit signed integers. Therefore, for each read/write block, the DMA state machine fetches the offset from the tap list. The offset is added to the EIEP value to get the start address of the next block. The external addresses are circular buffered if circular buffering is enabled (Figure 4-30, Figure 4-31). Once the ICEP register for the final tap decrements to zero (both TCEP and are zero), then the tap list DMA access is complete and the DMA completion interrupt is generated (if chaining is enabled the interrupt depends on the PCI bit setting).
ICEP

The write back mode (WRBEN bit) is hardwired to zero for tap list based DMA (as the addressing is pre-modify, and therefore the EIEP value coincides with the TCB value even at the end of the DMA).

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TAP LIST BUFFER TAP LIST POINTER (TPEP) OFFSET1 OFFSET2 OFFSET3 DESTINATION INDEX (EIEP) SOURCE INDEX (IIEP) 1 2 3 4 5 6 7 8 9 10 11 12 SOURCE BUFFER --1 2 3 4 EIEP + OFFSET1

Parameter Settings: IIEP = Source IMEP = 1 ICEP = 4 EIEP = Dest. EMEP = 1 ICEP = 4 TPEP = TL Buffer TCEP = 3 Control Settings: DEN|TRAN|LEN

5 6 7 8

EIEP + OFFSET2

9 10 11 12

EIEP + OFFSET3

DESTINATION BUFFER

Figure 4-28. Scatter DMA (Writes)

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TAP LIST BUFFER TAP LIST POINTER (TPEP) OFFSET1 OFFSET2 OFFSET3 SOURCE INDEX (EIEP) DESTINATION INDEX (IIEP) 1 2 3 4 5 6 7 8 Parameter Settings: IIEP = Source IMEP = 1 ICEP = 4 EIEP = Dest. EMEP = 1 ICEP = 4 TPEP = TL Buffer TCEP = 3 Control Settings: DEN|TLEN 9 10 11 12 DESTINATION BUFFER 9 10 11 12 SOURCE BUFFER --1 2 3 4 EIEP + OFFSET1

5 6 7 8

EIEP + OFFSET2

EIEP + OFFSET3

Figure 4-29. Gather DMA (Reads)

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TAP LIST BUFFER TAP LIST POINTER (TPEP) 4 12 20 28 36 SOURCE INDEX (IIEP) 1 2 3 4 5 6 7 8 9 10 11 Parameter Settings: IIEP = Source IMEP = 1 ICEP = 4 EIEP = Dest. EMEP = 1 EBEP = Dest. ELEP = 20 ICEP = 4 TPEP = TL Buffer TCEP = 5 Control Settings: DEN|TRAN|TLEN|CBEN 12 13 14 15 16 17 18 19 20 SOURCE BUFFER SOURCE BASE (EBEP) DESTINATION INDEX (EIEP) 9 10 11 12 1 2 3 4 13 14 15 16 5 6 7 8 17 18 19 20 DESTINATION BUFFER EIEP + 12 EIEP + 28 EIEP + 20

EIEP + 4

EIEP + 36

Figure 4-30. Circular Buffering Scatter DMA (Writes)

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TAP LIST BUFFER TAP LIST POINTER (TPEP) 4 12 20 28 36 DESTINATION INDEX (IIEP)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

SOURCE INDEX (EIEP) 9 10 11 12 1 2 3 4 13 14 15 16 5 6 7 8 17 18 19 20 SOURCE BUFFER

EIEP + 20

SOURCE BASE (EBEP)

EIEP + 4

EIEP + 28

Parameter Settings: IIEP = Dest IMEP = 1 ICEP = 4 EIEP = Source EMEP = 1 EBEP = Dest. ELEP = 20 ICEP = 4 TPEP = TL Buffer TCEP = 5 Control Settings: DEN|TLEN|CBEN

EIEP + 12

EIEP + 36

DESTINATION BUFFER

Figure 4-31. Circular Gather DMA (Reads) Delay Line DMA Delay line DMA is used to support reads and writes to external delay line buffers with limited core interaction. In this sense, delay line DMA is basically a quantity of integrated writes followed by reads from external memory-called a delay line DMA access. Delay line DMA is described in the following sections. line DMA can operate DMA mode Delay bit set). In orderonlyuse delayby using chained single DMA ( to line DMA for a
CHEN

sequence, initialize the CPEP register to zero in the TCB.

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Delay Line DMA operates using the following five steps: 1. Load first half TCB for write (7 parameters). 2. DMA writes to the delay line buffer until IC = 0. 3. Update EI index pointer if circular mode is enabled. 4. Load second half TCB for read (6 parameters). 5. DMA tap based read from delay line buffer until RC = 0. Jump to step 1. Writes to delay line, Figure 4-32. The number of writes is determined by the ICEP register. The data is fetched from the IIEP register and the IMEP register is used as the internal modifier. The EIEP register serves as the external index and is incremented by the EMEP register after each write. These writes are circular buffered if circular buffering is enabled.
SOURCE BUFFER 20 15 16 17 DESTINATION BASE ADDRESS (EBEP) DESTINATION INDEX (EIEP) DELAY LINE BUFFER 19 20 1 2

3 2 1

SOURCE INDEX (IIEP)

16 17 18

BUFFER LENGTH (ELEP)

Figure 4-32. Write to Delay Line Buffer When the writes are complete, (ICEP = 0) the EIEP register, which serves as the write pointer of the delay line, is written back (WRBEN is hardwired to 1) to the internal memory TCB location from where it was fetched. Reads from the delay line, Figure 4-33. For reads, the tap list (TL) modifiers are used and the number of reads is determined by the RCEP register.

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The write pointer in the RIEP register serves as the index address for these reads (reads start from where writes end). The RIEP register, along with tap list modifiers, are used in a pre-modify addressing mode to create the external address for the reads. Therefore, for each read, the DMA controller fetches the external modifier (TCEP register) from the tap list and the reads are circular buffered (if enabled). Therefore, for each read, the DMA controller fetches the external modifier from the tap list and the reads are circular buffered (if enabled).
TAP LIST BUFFER TAP LIST POINTER (TPEP) 4 12 20 28 36 DESTINATION INDEX (RIEP)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SOURCE BUFFER

SOURCE INDEX (EIEP) 9 10 11 12 1 2 3 4 13 14 15 16 5 6 7 8 17 18 19 20 DELAY LINE BUFFER

EIEP + 20

SOURCE BASE (EBEP)

EIEP + 4

EIEP + 28

EIEP + 12

EIEP + 36

Figure 4-33. Read From Delay Line Buffer

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Pre-Modified Read Index

Note that TL[N] is the first tap list entry in internal memory pointed to by the tap list pointer register (TPEP). Tap list entries are 27-bit signed integers. Therefore, for each read-block, the DMA state machine fetches the offset external modifier from the tap list. The reads are circular buffered if circular buffering is enabled. pre-modify addressing for The external address generation followsthe register values are reads in delay line DMA and therefore
EIEP

not updated. Also the EMEP register does not have any effect during these delay line reads. Once the read count completes, the ICEP register decrements to zero (both ICEP and TCEP are zero) for the final tap. Finally, the delay line DMA access completes and the DMA completion interrupt is generated. If chaining is enabled, the interrupt is dependent on the PCI bit setting. The delay line DMA can only be initialized using the TCB. In order to use the delay line DMA for a single DMA sequence, initialize the CPEP register to zero in the TCB. For each 32-bit tap read, the external read index is shown in Table 4-29. Note that one tap list entry starts multiple reads. Table 4-29. Read/Write Index Pre-Modify (Scatter/Gather DMA)
Pre-Modify Address Equation RIEP + TPEP[TCEP] + (RMEPxRCEP) RIEP + TPEP[0] + RMEPx1 RIEP + TPEP[0] + RMEPx2 RIEP + TPEP[0] + RMEPx3 RIEP + TPEP[0] + RMEPxN Result Blocksize N Tap 0

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Table 4-29. Read/Write Index Pre-Modify (Scatter/Gather DMA) (Contd)

Pre-Modify Address Equation RIEP + TPEP[TCEP] + (RMEPxRCEP) RIEP + TPEP[1] + RMEPx1 RIEP + TPEP[1] + RMEPx2 RIEP + TPEP[1] + RMEPx3 RIEP + TPEP[1] + RMEPxN RIEP + TPEP[M] + RMEPx1 RIEP + TPEP[M] + RMEPx2 RIEP + TPEP[M] + RMEPx3 RIEP + TPEP[M] + RMEPxN N M Result Blocksize N Tap 1

External Port DMA Group Priority The external port has two DMA channels. When the channels have data ready, the channel arbitrates by a fixed or rotating method (which is the first arbitration stage). The winning channel requests the DMA bus arbiter to get control of the external port DMA bus (2nd stage of arbitration). In fixed priority, channel 0 has highest priority. For fixed priority, if channel 0 performs internal to internal memory transfers, then channel 1 has the higher priority. For the I/O processor, the two DMA channels are considered as a group with one arbitration request. For more information, see External Port DMA Arbitration on page 3-38.

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Interrupts
There are two external port DMA channels. The following sections describe the two ways of triggering interrupts. Table 4-30 provides an overview of external port interrupts. Table 4-30. External Port Interrupt Overview
Default Programmable Interrupt EPDMA0I = P9I EPDMA1I = P13I Sources DMA complete Internal transfer completion Access completion Masking N/A Service RTI instruction

Sources
Each external port DMA module generates one interrupt signal. The external port DMA can generate interrupts under the conditions described in the following sections. Delay Line DMA For the delay line DMA, the DMA complete interrupt is generated when the delay line reads are completed (after the write access). Scatter Gather DMA With scatter/gather DMA, the DMA complete interrupt is generated only after all tap list reads/writes are complete. Internal Transfer Completion This mode of interrupt generation is enabled when the INTIRT bit is set in the DMA control register and resembles traditional SHARC DMA interrupt generation. This mode is provided for backward compatibility. This

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interrupt is generated once the DMA internal transfers (transmit or receive) are completed. For external transmit DMA, there may be still external access pending at the external DMA interface when the completion interrupt is generated. Therefore, the DMA may be disabled on the DMA complete interrupt only if the external interface is idle (for example, EXTS = 0). Access Completion This is the default mode of interrupt generation where the DMA complete interrupt is generated when accesses are completed. For external write DMA, the DMA complete interrupt is generated only after external writes on the DMA external interface are done. For external read DMA, the DMA complete interrupt is generated when the internal DMA writes complete. In this mode, the DMA interface can be disabled as soon as the interrupt is received, (there is no need to check the EXTS bit before disabling the DMA interface). interface can be disabled based on a DMA complete The DMAHowever, the external device interfacesAMI/SDRAM/ interrupt. DDR2 may still be performing writes of the DMA data. Prior to disabling any of these devices, programs should check their respective status bits.

If DMA is disabled in the middle of data transfers, the DMA interrupts should not be used.
Chained DMA For chained DMA, if the PCI bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the PCI bit is set (= 1), then a DMA interrupt is generated for each TCB. ADSP-214xx SHARC Processor Hardware Reference 4-139

Interrupts

In a chained delay line DMA, the PCI bit determines if each delay line TCB generates an interrupt or not. For scatter/gather DMA, the PCI bit setting determines if each tap list TCB generates an interrupt in a chained access.

Masking
The EPDMA0I and EPDMA1I signals are routed by default to programmable interrupts as follows. To service the EPDMA0I, unmask (set = 1) the P9IMSK bit in the LIRPTL register. To service the secondary EPDMA1, unmask (set = 1) the P13IMSK bit in the LIRPTL register. For example:
bit set LIRPTL P9IMSK; bit set LIRPTL P13IMSK; /* unmasks P9I interrupt */ /* unmasks P13I interrupt */

Service
Interrupts are serviced with a RTI (return from interrupt) instruction.

Interrupt Dependency on DMA Mode

Interrupt generation varies, depending on the DMA mode used. The INTIRT bit determines whether the interrupt is generated on internal completion or access completion. The following also effect interrupt generation. For standard chained DMA, if the PCI bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the PCI bit is set (= 1), then a DMA interrupt is generated for each TCB.

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For the delay line DMA, the DMA complete interrupt is generated when both the write access and the delay line reads are completed. In a chained delay line DMA, the PCI bit determines if each delay line TCB generates an interrupt or not. With scatter/gather DMA, the DMA complete interrupt is generated only after all tap list reads/writes are complete. As in the delay line DMA, the PCI bit setting determines if each tap list TCB generates an interrupt in a chained access.

If DMA is disabled in the middle of data transfers, the DMA interrupts should not be used.
External Port Throughput
The following sections provide information on the throughput of the external port interfaces (AMI, SDRAM).

Data Throughput
Table 4-31 provides information needed to configure the SDRAM interface for the desired throughput. Table 4-31. SDRAM 16-bit SISD Data Throughput
Access Sequential uninterrupted reads Any writes Non sequential uninterrupted reads 1 Page Same Same Same Throughput per SDCLK (16-Bit Data) One word per two cycles1 One word per two cycles One word per seven cycles (CL=2) One word per eight cycles (CL=3)

Read Optimization enabled, first data of a sequential read takes 7 cycles for CL =2 and 8 cycles for CL = 3, thereafter it is one word per two cycles.

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Table 4-32 provides information needed to configure the DDR2 interface for the desired throughput. Table 4-32. DDR2 16-bit SISD Data Throughput
Access Sequential uninterrupted reads Any writes Non sequential uninterrupted reads Non sequential interrupted writes Page Same Same Same Same Throughput per DDR2CLK (16-Bit Data) One word per two cycles1 One word per cycle One word per 10 cycles (CL=3) One word per two cycles

1 Read Optimization enabled, first data of a sequential read takes 10 cycles for CL = 3, thereafter it is one word per cycle.

The AMI data throughput is shown in Table 4-33. Table 4-33. AMI Read/Write Throughput
Access1 Write Read 1 8-Bit I/O 32-bit word per 12 cycles 32-bit word per 12 cycles 16-Bit I/O 32-bit word per 6 cycles 32-bit word per 6 cycles

Throughput for minimum wait states of 2 with no idle and hold cycles.

DMA Throughput Table 4-34 provides approximate throughput information with the processor core running at 400 MHz for DMA-driven reads and writes of external DDR2 memory. The throughput numbers shown are measured by running chained DMA with four TCBs (with 256 32-bit words per transfer block).

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For the analysis, 16 bit DDR2 is used (tFAW=10, tRRD=2, tRTP=2, tRCD=3, tWTR=1, tRP=3, tRAS=8, CL=4, AL=4, tWR=4). Throughput is calculated by measuring time between the instant when DMA is enabled and instant when DMA completion ISR is entered. Table 4-34. DMA Throughput, 400 MHz Core Clock
Operation DMA Reads 133 MHz 200 MHz DMA Writes 133 MHz 200 MHz 1:3 1:2 481M bytes/sec. 732M bytes/sec. 1:3 1:2 473M bytes/sec. 700M bytes/sec. DDR2 Clock Clock Ratio Throughput

Core Throughput Table 4-35 provides approximate throughput information with the processor core running at 400 MHz for core-driven reads and writes of external DDR2 memory. The throughput numbers shown are measured by running a loop of 1024 read/writes (512 in case of SIMD reads/writes). For the analysis, 16-bit DDR2 is used (tFAW=10, tRRD=2, tRTP=2, tRCD=3, tWTR=1, tRP=3, tRAS=8, CL=4, AL=4, tWR=4). Throughput is calculated from start of the first iteration of the loop to the end of the last iteration of the loop. Table 4-35. Core Throughput, 400 MHz Core Clock
Operation DDR2 Clock Clock Ratio Throughput Core Reads (SISD/SIMD) 133 MHz 1:3 495M bytes/sec.

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Table 4-35. Core Throughput, 400 MHz Core Clock (Contd)

Operation DDR2 Clock 200 MHz Core Writes (SISD) 133 MHz 200 MHz Core Writes (SIMD) 133 MHz 200 MHz 1:3 1:2 531M bytes/sec. 796M bytes/sec. 1:3 1:2 529M bytes/sec. 793M bytes/sec. Clock Ratio 1:2 Throughput 742M bytes/sec.

DDR2 Read Optimization Listing 4-8 through Listing 4-13 on page 4-147 provide different scenarios of core read accesses. The timing settings for these examples are: (CL = 4, AL = 0, tRRD = 3, tRTP= 2, tRCD = 4, tRP = 4, tRAS = 9) Listing 4-8 shows how read optimization can be used efficiently using core accesses. All reads are on the same page and it takes 1070 DDR2CLK cycles to perform 1024 reads which is close to 1 DDR2CLK cycle per access. Listing 4-8. Consecutive Locations Accessed Sequentially With Read Optimization Enabled
ustat1=dm(DDR2CTL0); bit set ustat1 DDR2OPT|DDR2MODIFY1; dm(DDR2CTL0)=ustat1; nop; I8 = intmem_addr; M8 = 1; I0 = sdram_addr; M0 = 1; lcntr = 1024, do(PC,1) until lce; R0 = dm(I0,M0),pm(I8,M8) = R0;

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In Listing 4-9 the access are made non-sequential by inserting a NOP instruction in between reads. All reads are on the same page and it takes approximately 11794 DDR2CLK cycles to perform 1024 reads. That is approximately 11 DDR2CLK cycles per read. Even though optimization is enabled it has no effect because of the non-sequential behavior of the read accesses. Listing 4-9. Consecutive Locations Accessed Non-sequentially With Read Optimization Enabled
ustat1=dm(DDR2CTL0); bit set ustat1 DDR2OPT|DDR2MODIFY1; dm(DDR2CTL0)=ustat1; nop; I8 = intmem_addr; M8 = 1; I0 = sdram_addr; M0 = 1; lcntr = 1024, do(PC,2) until lce; R0 = dm(I0,M0),pm(I8,M8) = R0; Nop;

In Listing 4-10 the access are made from non-consecutive locations. All reads are on the same page and it takes approximately 11269 DDR2CLK cycles to perform 1024 reads which is approximately 11 DDR2 cycles per read. Even though optimization is enabled it has no effect because the locations accessed are non-consecutive. Set the DDR2MODIFY bit to match the DAG Modifier (2 in this case) to get better performance. Listing 4-10. Non-Consecutive Locations Accessed Sequentially With Read Optimization Enabled
ustat1=dm(DDR2CTL0); bit set ustat1 DDR2OPT|DDR2MODIFY1;

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dm(DDR2CTL0)=ustat1; nop; I8 = intmem_addr; M8 = 1; I0 = sdram_addr; M0 = 2; lcntr = 1024, do(PC,1) until lce; R0 = dm(I0,M0),pm(I8,M8) = R0;

In Listing 4-11, all reads are on the same page and it takes 5655 DDR2CLK cycles to perform 1024 reads. Listing 4-11. Consecutive Locations Accessed Sequentially With Read Optimization Disabled
ustat1=dm(DDR2CTL0); bit clr ustat1 DDR2OPT|DDR2MODIFY1; dm(DDR2CTL0)=ustat1; nop; I8 = intmem_addr; M8 = 1; I0 = sdram_addr; M0 = 1; lcntr = 1024, do(PC,1) until lce; R0 = dm(I0,M0),pm(I8,M8) = R0;

In Listing 4-12 the access are made non-sequential by inserting a NOP in between accesses. All reads are on the same page and it takes around 11272 DDR2CLK cycles to perform 1024 reads which is approximately 11 DDR2CLK cycles per read.

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Listing 4-12. Consecutive Locations Accessed Non-sequentially With Read Optimization Disabled
ustat1=dm(DDR2CTL0); bit clr ustat1 DDR2OPT|DDR2MODIFY1; dm(DDR2CTL0)=ustat1; nop; I8 = intmem_addr; M8 = 1; I0 = sdram_addr; M0 = 1; lcntr = 1024, do(PC,2) until lce; R0 = dm(I0,M0),pm(I8,M8) = R0; Nop;

In Listing 4-13 the access are made from non-consecutive locations. All reads are on the same page and it takes around 10249 DDR2CLK cycles to perform 1024 reads. That is approximately 10 DDR2CLK cycles per read. Please note that compared to read optimization enabled case throughput is better by 1 DDR2CLK cycle per access here. Listing 4-13. Non-Consecutive Locations Accessed Sequentially With Read Optimization Disabled
ustat1=dm(DDR2CTL0); bit clr ustat1 DDR2OPT|DDR2MODIFY1; dm(DDR2CTL0)=ustat1; nop; I8 = intmem_addr; M8 = 1; I0 = sdram_addr; M0 = 2; lcntr = 1024, do(PC,1) until lce; R0 = dm(I0,M0),pm(I8,M8) = R0;

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In summary, for SISD mode the modifier of 1 allows programs to take advantage of sequential addressing. One burst reads two words until a new burst has started resulting in 1 cycle/word with optimization enabled. For SIMD mode the modifier of 2 fills one entire burst (explicit 2 words + implicit 2 words) also performing at 1 cycle/word if optimization is enabled. Throughput Conditional Instructions A conditional read/write may take 1 PCLK cycle (access made and access aborted, respectively). For more information, see External Memory Access Restrictions on page 4-165.

External Instruction Fetch Throughput

Read optimization logic does not apply to external instruction fetch.

SDRAM Throughput Table 4-36 illustrates the performance of code execution depending on different access types for SDRAM. Table 4-36. SDRAM 16-bit Instruction Fetch Throughput
Access Sequential uninterrupted reads Non sequential uninterrupted reads Page Same Same Throughput per SDCLK 2 instructions per 6 cycles (CL=3) 1 instruction per 9 cycles (CL=2) 1 instruction per 10 cycles (CL=3)

The SDC has to fetch 3 instruction data for each ISA instruction. First 48-bit instruction of a sequential read will take 8 cycles for CL = 2 and 9 cycles for CL = 3, thereafter it is two instructions per 6 cycles. The instruction available cycles will look like - 8, 10, 14, 16, 20, 22, 26, 28 (CL = 2)

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DDR2 Throughput Table 4-37 illustrates the performance of code execution depending on different access types for DDR2. Table 4-37. DDR2 16-bit Instruction Fetch Throughput
Access Sequential uninterrupted reads Non sequential uninterrupted reads Page Same Same Throughput per DDR2CLK (CL = 3) 2 instructions per 3 cycles 1 instructions per 11 cycles

The DDR2C has to fetch 3 instruction data for each ISA instruction. First 48-bit instruction of a sequential read will take 11 cycles for CL = 3, thereafter it is two instructions per 3 cycles. The instruction available cycles will look like - 11, 12, 14, 15, 17, 18, 20, 21 (CL = 3)

AMI Throughput When executing from external asynchronous memory, instruction throughput depends on the settings of asynchronous memory such as the number of wait states, the ratio of core to peripheral clock and other settings. For details, please refer to the external port global control register (EPCTL), the AMICTLx register, and the SDCTL0 register in External Port Registers on page A-20.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific). After the AMI/SDRAM/DDR2 registers are configured the write effect latency is 1.5 PCLK cycles minimum and 2 PCLK cycles maximum. After the external port register is configured the effect latency is 4 PCLK cycles. This is the valid for the worst case of core to SDRAM/DDR2 clock ratio of 1:4

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Programming Models
The following sections provide information on the various programming models that are used through the external port interface. For all external port programming models two cases of latency are involved. 1. The latency for an external port clock ratio change is 8 PCLK cycles. After any external port clock ratio change (PMCTL register) no external port registers (external port, AMI, SDC, DDR2, external port DMA registers) should be changed during these 8 PCLK cycles. Also no external memory accesses (AMI, SDRAM or DDR2) are allowed during this period. 2. The access latency for external port registers is 4 PCLK cycles. After any external port register change (external port, AMI, SDC, DDR2, external port DMA registers) external memory accesses are not allowed during this period.

AMI Initialization
After reset, the SDCLK/DDR2CLK is running with the default PLL settings. However, the AMI must be configured and initialized. In order to set up the AMI, use the following procedure. Note that the registers must be programmed in order. 1. Chose a valid CCLK to SDCLK/DDR2CLK clock ratio in the PMCTL register. 2. Wait at least 15 CCLK cycles (effect latency). 3. Assign external banks to the AMI using the EPCTL register (default).

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4. Enable the global AMIEN bit and program the AMI control (AMICTLx) registers. (Define control settings for AMI based on SDCLK speed and asynchronous memory specifications. The AMIMS and AMIS bits 10 of the AMI status register (AMISTAT) can be checked to determine the current state of the AMI. 5. Wait 8 core cycles before first data access (effect latency). AMI Instruction Fetch For ISA instruction fetch, these steps are required (besides power-up). 1. Assign external bank 0 to AMI in the EPCTL register. 2. Enable the global AMIEN bit and clear (=0) the PKDIS bit. 3. For ISA instruction the first fetch starts at logical address 0x20 0000.

SDRAM Controller
This section describes software programming steps required for the successful operation of the SDRAM controller. Power-Up Sequence After reset, the SDCLK is running with the default PLL settings. However, the controller must be configured and initialized. In order to set up the controller and start the SDRAM power-up sequence for the SDRAMs, use the following procedure. Note that the registers must be programmed in order. 1. Chose a valid CCLK to SDCLK clock ratio in the PMCTL register. 2. Wait at least 15 core clock cycles until the new SDCLK frequency has been settled up correctly.

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3. Assign external banks to controller in the EPCTL register. 4. Wait at least 8 core clock cycles (effect latency). 5. Program the refresh counter in the SDRRC register. 6. Define global control for controller and SDRAM based on speed and SDRAM specifications in the SDCTL register. 7. Wait at least 8 core clock cycles (effect latency). 8. Once the SDPSS bit in the SDCTL register is set to 1, a dummy access is required to start the power-up sequence. The SDRAM is ready for access. The SDRS bit of the SDRAM control status register can be checked to determine the current state of the controller. If this bit is set, the SDRAM power-up sequence has not been initiated. Changing the SDRAM Clock on the Fly Self-refresh mode is an option, this mode can take infinite time. Use the following steps. 1. Ensure that the SDRAM controller is idle by checking the SDCI bit (bit 0) in the SDSTAT0 register. 2. Set the self refresh mode bit (SDSRF bit) and wait until the SREF status bit is set. 3. Shut off the clock to the external port using the EPOFF bit in the PMCTL1 register. 4. Change the clock ratio/frequency and wait 15 CCLK cycles.

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5. Enable the clock to the external port. 6. Exit from by SDRAM dummy access, and wait until the SREF status bit is cleared. The SDRAM controller is now ready for operation with the new clock frequency. If timing parameters require a change due to the frequency change that can be done after step 6. If any mode register parameter requires a change a force mode register write must be performed with the new values. SDRAM Instruction Fetch Use the following steps to perform an ISA/VISA instruction fetch (exclusive of power up). 1. Assign external bank 0 to DDR2 using the EPCTL register. 2. Configure the power-up sequence. For ISA instruction the first fetch starts at logical address 0x20 0000 and for VISA instruction fetch at address 0x60 0000. Output Clock Generator Programming Model The following non VCO programming sequence may be used to change the output generator clock and the core-to-peripheral clock ratio (for example the SDRAM clock). Note that if your program is only changing the PLL output divider, programs do not need to wait 4096 CLKIN cycles (required only if the PLL multiplier or the INDIV bit is modified). 1. Disable the peripheral (SDRAM). Note that the peripherals cannot be enabled when changing clock ratio. 2. Select the PLL divider by setting the PLLDx bits (bits 67 in the PMCTL register).

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3. Select the clock divider (CCLK to SDRAM ratio) by setting the ratio bits (PMCTL register). 4. Wait 15 CCLK cycles. During this time, programs must not execute any valid instructions. 5. Enable the peripheral (SDRAM). The new divisor ratios are picked up on the fly and the clocks smoothly transition to their new values after a maximum of 15 core clock CCLK cycles. Self-Refresh Mode The following steps are required when entering and releasing self-refresh mode. 1. Set the SDSRF bit to enter self-refresh mode. 2. Poll the SDSRA bit in the SDRAM status register (SDSTAT) to determine if the SDRAM has already entered self-refresh mode. 3. Set the DSDCTL bit to freeze SDCLK (optional). 4. Self refresh mode-no activities on all SDRAM signals (clock optional). 5. Clear the DSDCTL bit to re-enable SDCLK (optional). 6. SDRAM access releases controller from self-refresh mode. Changing the VCO Clock During Runtime In previous SHARC models, only a hardware reset initiated another SDRAM power-up sequence. This is no longer the case since the PLL allows programs to change the output clocks during runtime.

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All SDRAM timing specifications are normalized to the SDRAM clock. Since most of these are minimum specifications, (except tREF, which is a maximum specification), a variation of the system clock violates a specific specification and causes a performance degradation for the other specifications. The reduction of the system clock violates the minimum specifications, while increasing the system clock violates the maximum tREF specification. Therefore, careful software control is required to adapt these changes. Therefore, the release from self-refresh mode should be a dummy read operation since it happens with the old frequency settings. most sequence For of theapplications, the SDRAM power-uponce. Onceand writing mode register needs to occur only the power-up sequence has completed, the SDPSS bit should not be set again unless a change to the mode register is desired. The recommended procedure for changing the system frequency SDCLK is as follows. 1. Set the SDRAM to self-refresh mode by writing a 1 to the SDSRF bit of the SDCTL register. 2. Poll the SDSRA bit of SDSTAT register for self-refresh grant. 3. Execute the desired PLL programming sequence. (For more information, see PLL Start-Up on page 23-9.) 4. Wait 4096 CLKIN cycles (RESETOUT asserted) which indicates the PLL has settled to the new frequency. 5. Reprogram the SDRAM registers (SDRRC, SDCTL) with values appropriate to the new SDCLK frequency and assure that the SDPSS bit is set.

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6. Bring the SDRAM out of self-refresh mode by performing a dummy read SDRAM access. 7. The controller now issues the commands PREA, 8xREF and MRS to initialize the controller and the SDRAM to the new frequency. The SDRAM device is now ready to be accessed.

DDR2 Controller
The following sections are specific to DDR2 SDRAM memory on the ADSP-2146x processor. Note these general rules. If a program changes only the timing parameters (tRRD, tRP for example) without changing the clock ratios, then no initialization sequence is required. However, if any of the mode registers are changed (MR, EMR1, EMR2), then the program needs to perform a force load of the corresponding mode register using the force bits in the DDR2CTL0 register. Note the CAS latency (CL) is a timing parameter which is also transferred to the memory via the mode register command. However if a program changes the clock frequencies, then the program also needs to reset the DLL. Both the ADSP-2146x and DDR2 memory DLL will have to be reset. In such a case, an entire initialization sequence is required. With the worst case timing parameter, it takes 410 cycles for one external DDR2 bank to calibrate. Power-Up Sequence The following steps are used to power-up the DDR2 device.

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1. Program the core to DDR2 clock ratio using the PMCTL register. For PLL changes wait at least 4096 core cycles, for output divider changes at least 15 core clock cycles for effect latency. Ensure the minimum DDR2 clock frequency is stable and at least 125 MHz (according to datasheet). 2. Wait at least 200 s with a stable clock provided to the DDR2 memory (JEDEC standard). 3. If a new DDR2 frequency is desired, put the on-chip DLL into reset using DLL1-0CTL1 registers. 4. Wait at least 9 core cycles. 5. DLL in reset starts new locking event. Wait for the DLL to lock to the new frequency. Note that the DLL locking time depends on the CCLK to DDR2_CLK ratio and is: 1:2 3000 CCLK cycles 1:3 7500 CCLK cycles 1:4 10000 CCLK cycles 6. Assign the required external DDR2 banks in the EPCTL register. 7. Wait 8 core cycles for effect latency. 8. Program the refresh rate control register (DDR2RRC). 9. Program the timing parameters in the DDR2CTL1 register. 10.Program all MR and EMR31 settings in the DDR2CTL5-3 registers. 11.Ensure that the DDR2_DLL_DIS bit (DDR2CTL3) and the SH_DLL_DIS (DDR2CTL0) bits are cleared. 12.Enable DDR size (row, column, bank) and other parameters in the DDR2CTL0 register.

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13.Wait 8 core cycles for effect latency. 14.Start the power-up sequence with the DDR2PSS bit. Wait for DLL external bank calibration. The device now ready for any access. Changing the DDR2 Clock on the Fly Two different modes allow programs to change the DDR2 clock during run time. Precharge power-down mode requires careful software control since the DRAM is no longer refreshed and therefore a maximum window must be guaranteed. This interval is typically tRASmax = 8 tREFI or 9 tREFI). On die termination must be turned off. Self-refresh mode is the 2nd option, and this mode can take infinite time.
Changing the Clock Frequency During Precharge Power Down Mode

Use the following procedure to change the clock frequency during precharge power down mode. 1. Ensure that the DDR2 controller is idle by checking the DDR2CI bit (bit 0) in the DDR2STAT0 register. 2. Perform a Force precharge all banks command (FPC bit) and force 8 refresh commands (FARF bit) 3. Set the precharge power down mode (DIS_DDR2CKE bit) and wait until the power-down status bit is set. 4. Shut off the clock to the external port in the PMCTL1 register. 5. Change clock ratio/frequency and wait 15 CCLK cycles. 6. Enable the clock to the external port.

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7. Wait for the DLL to lock to the new frequency. 8. Exit from power-down mode by clearing the DIS_DDR2CKE bit, and wait until the DDR2PD status bit is cleared. 9. Perform an on chip DLL calibration again by setting the Force DLL calibration bit. The DDR2 controller is now ready for operation with the new clock frequency. If timing parameters require a change due to the frequency change that can be done after step 7. If any mode register parameter requires a change a force mode register write must be performed with the new values. Note that the maximum precharge power down time is 9 tREFI.
Changing the Clock Frequency During Self-Refresh Mode

Use the following procedure to change the clock frequency during self-refresh mode. 1. Ensure that the DDR2 controller is idle by checking the DDR2CI bit (bit 0) in the DDR2STAT0 register. 2. Set the self refresh mode bit (DDR2SRF) and wait until the SREF status bit is set. 3. Shut off the clock to the external port using the EPOFF bit in the PMCTL1 register. 4. Change the clock ratio/frequency and wait 15 CCLK cycles. 5. Enable the clock to the external port. 6. Wait for the DLLs to lock to the new frequency.

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7. Exit from self-refresh mode by clearing the DDR2SRF bit, and wait until the SREF status bit is cleared. 8. Perform an on chip DLL calibration again by setting the Force DLL calibration bit.

External Port DMA

The following sections describe the programming steps for different types of DMA transfers. Before using the external port DMA it is assumed that the AMI/SDRAM or DDR2 controllers are programmed accordingly. Standard DMA Use the following procedure to set up and run a standard DMA on the external port. 1. Configure the AMICTLx registers to enable the AMI and to set the desired wait states, data bus width, and so on. Configure the SDCTL registers to enable SDRAM/DDR2, and to set the desired clock and timing settings, the data bus width, and other parameters. 2. Initialize the IIEP, IMEP, ICEP, EIEP, and EMEP registers. 3. If circular buffering is desired, use the corresponding TCB storage. 4. If scatter/gather DMA is desired, program additional writes to the TCEP and TPEP registers. 5. Enable DMA using the DMAEN bit, and set the transfer direction using the TRAN bit in the DMACx registers. If scatter/gather DMA is desired, set the TLEN bit. It is advised that the DMA FIFOs are flushed using the DFLSH bit when DMA is enabled. Once the DMA control register is initialized, the DMA engine fetches the DMA descriptors from the address pointed to by CPEP. Once the DMA descriptors are fetched then the DMA (or the tap list DMA) process starts.

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Once the DMA (or tap list DMA) is complete, the new DMA descriptors are loaded and the process is repeated until CPEP = 0x0. A DMA completion interrupt is generated at the end of each DMA block or at the end of entire chained DMA, depending on the PCI bit setting. Chained DMA Use the following procedure to set up and run a chained DMA on the external port. 1. Clear the chain pointer register. 2. Configure the AMICTLx registers to enable the AMI, set the desired wait states, the data bus width, and so on. Configure the SDCTL register to enable the SDRAM/DDR2, configure the desired clock and timing settings, data bus width, and other parameters. 3. Initialize the CPEP register and set the PCI bit if interrupts are required after the end of each DMA block. Set the CPDR bit if different DMA direction is required in conjunction with the OFCEN bit in the DMACx register. 4. If circular buffering is needed, use the corresponding TCB storage. 5. Enable DMA using the DMAEN, bit, set chaining using the CHEN bit. If circular buffering is required, set the CBEN bit in the DMACx registers. It is advised that programs flush the DMA FIFOs using the DFLSH bit when DMA is enabled. Once the DMA control register is initialized, the DMA controller fetches the DMA descriptors from the address pointed to by the external port chain pointer register (CPEP). Once the DMA descriptors are fetched, the normal DMA process starts. Upon completion, new DMA descriptors are loaded and the process is repeated until CPEP = 0x0. A DMA completion interrupt is generated at

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the end of each DMA block or at the end of an entire chained DMA, depending on the PCI bit setting. Delay Line DMA 1. Configure the AMICTLx register with the desired wait states, enable AMI, data bus width and other parameters. 2. Initialize the CPEP register and set the PCI bit if interrupts are required after the end of each delay line DMA block. 3. Enable DMA (DMAEN), delay line DMA (DLEN), chaining (CHEN) if required in the DMACx register. Programs should flush the DMA FIFO (DFLSH) along with enabling the DMA. If circular buffering is required (which is normally the case) enable it by setting the CBEN bit. Once the DMA control register is initialized the DMA engine fetches the DMA descriptors from the address pointed to by the CPEP register. Once the delay line DMA access is complete, the new DMA descriptors are loaded and the process is repeated until CPEP = 0x0. A DMA completion interrupt is generated at the end of each delay line DMA block or at the end of entire chained DMA, depending on the PCI bit setting. delay enabled When blocksline DMA isdelay line with chaining, all the chainednot DMA follow the DMA access procedure. It is possible to mix normal DMA with delay line DMA in chained DMA. Disabling and Re-enabling DMA Use the following programming model to disable the external port DMA during transfers. 1. Clear the DMAEN bit on the DMACx register. 2. Wait until the EXTS bit is 0.

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3. Write 0x0 to the ICEP and DMACx registers. In cases where DMA is used without chaining, writing to ICEP is not required. 4. Re-initialize the required DMA registers, and enable the DMACx register while flushing the data buffer. The external port DMA buffers are flushed by setting the respective DFLSH bits. Additional Information 1. If DMA is disabled in the middle of a data transfer, then DMA interrupts cannot be relied on. 2. A standard DMA (no chaining) can be stopped midway by clearing the DMAEN bit in the DMACx register and then restarted from the point where it was stopped by re-enabling the DMAEN bit. This mode of inhibiting the DMA only works with standard DMA. If a chained/delay line DMA is disabled by clearing DMAEN bit then the DMA should be reprogrammed again following the above programming model. 3. For a chained DMA, new TCB loading can be inhibited by clearing the CHEN bit while keeping all other control bits the same. The new TCB is loaded once CHEN bit is re-enabled. The TCB load which was happening when CHEN was cleared will complete. 4. Before initializing a chained DMA (including delay line) make sure that the ICEP and ECEP registers are zero. 5. The DMA parameter registers (except DMACx) should not be written to while chaining is occurring (the CHS bit is set), but any register can be read during chaining. 6. A zero count for the ICEP, RCEP and TCEP registers is forbidden. If a chain pointer with such a descriptor is programmed then the DMA might hang. So a read count zero or a write count zero for a delay line DMA is also forbidden.

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External Instruction Fetch

The section describes the software programming steps needed for the successful operation of external instruction fetch through the external port. Note only the additional steps for code execution are illustrated. For timing related settings refer to Functional Description on page 4-8. AMI Configuration For instruction fetch, the original (logical) address is multiplied by 3/2 and this address is translated depending on the bus width and PKDIS bit setting. 1. Assign external bank0 to AMI in the EPCTL register (default). 2. Wait at least 8 CCLK cycles (effect latency). 3. Enable the global AMIEN bit and clear (=0) the PKDIS bit. SDRAM Configuration For instruction fetch, the original (logical) address is multiplied by 3/2 and this address is translated depending on the bus width setting (X16DE bit). 1. Assign external bank 0 to SDRAM in the EPCTL register (default). 2. Wait at least 8 CCLK cycles (effect latency). 3. Configure the SDCTL and SDRRC registers accordingly.

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External Port

DDR2 Instruction Fetch Use the following steps to perform an ISA/VISA instruction fetch (exclusive of power up). 1. Assign external bank 0 to DDR2 using the EPCTL register. 2. Configure the power-up sequence. For ISA instruction the first fetch starts at logical address 0x20 0000 and for VISA instruction fetch at address 0x60 0000.

External Memory Access Restrictions

The following external memory restrictions should be noted when writing programs. 1. The LW mnemonic is not applicable to external memory. 2. Conditional accesses to external memory should not be based on any of the FLAG pin status. 3. There is one cycle latency between a multiplier status change and an arithmetic loop abort. This extra cycle is a machine cycle and not the instruction cycle. Therefore, if there is a pipeline stall (due to external memory access etc.) then the latency does not apply. 4. A one cycle stall is generated whenever an instruction that contains a conditional external memory access is in the decode stage, where the evaluation of the condition is dependent on the outcome of the previous instruction in address stage. It applies to all kinds of conditions except for conditions based on FLAG status. The following is an example:
f12 = f11+f10; if eq dm(ext) = r0;

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Debug Features

5. The FLUSH CACHE instruction has an effect latency of one instruction when executing program instructions from internal memory, and two instructions when executing from external memory. 6. When a new external memory instruction fetch occurs on the processor due to a jump from internal to external memory, or after a cache hit while executing instructions from external memory, there is one stall cycle present in the fetch1 stage. This stall avoids resource conflicts at the cache interface. 7. Any sequence of external memory access (read or write) followed by an IOP access, causes the IOP access to fail. To workaround this restriction, separate the external memory access and IOP access by adding a NOP instruction or any other instruction which is not either an IOP read/write, or an external memory access. Example:
R12 = dm(Ext_mem); NOP; /* fixes restriction */ R0 = dm(SPCTL2);

Debug Features
The following section describes the features available to aid in debugging the external port DMA module.

Core FIFO Write

The core may also write to the 6 deep data FIFO. When it does, the data word is pushed into the input side of the FIFO (as if it had come from the DMA on the channel). This can be useful for verifying the operation of the FIFO, the DMA channels, and the status portions of the external port DMA. The DMACx register returns the current state of the FIFO. Note that if both the DMA and core try to write to the FIFO, the core has higher priority.

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5 LINK PORTS ADSP-2146x

The ADSP-2146x processors have two 8-bit wide link ports, which can connect to another processor or peripheral link ports. The link ports allow a variety of interconnection schemes to I/O peripheral devices as well as co-processing and multiprocessing schemes. The port specifications are shown in Table 5-1. Table 5-1. Link Port Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Yes Yes Yes Yes Yes No No No N/A No N/A Yes Link Port10

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Features

Table 5-1. Link Port Specifications (Contd)

Feature Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Max Clock Operation Link Port10 Yes Yes 2 Yes Yes (Link Port 0) No LCLK

Features
These bidirectional ports have eight data lines, an acknowledge line, and a clock line. The maximum frequency of operation of the link ports is 166 MHz. The link port clock to core clock ratio programming is applicable only if the link port is configured as transmitter. The receiver link port can operate at any asynchronous clock frequency up to 166 MHz (or peripheral clock frequency (PCLK = CCLK/2) which ever is lower) independent of the programmed ratio. The link ports contain the features shown in the following list. Operate independently and simultaneously. Pack data into 32-bit words; this data can be directly read by the processor or DMA-transferred to or from on-chip memory. Have double-buffered transmit and receive data registers. Include programmable clock and acknowledge controls for link port transfers. Each link port has its own dedicated DMA channel.

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Provide high-speed, point-to-point data transfers to other processors, allowing differing types of interconnections between multiple DSPs.

Pin Descriptions
The pins associated with each link port are described in the ADSP-2146x data sheet.
TRANSMITTER
LDATx7-0 LCLKx LACKx 8

RECEIVER
LDATx7-0 LCLKx LACKx

Figure 5-1. Link Port Pin Connections

Register Overview
Each link port has its own control and status register. These are described in the following sections and in Link Port Registers on page A-62. For information on the link port DMA registers, see Standard DMA Parameter Registers on page 3-4. For information on the link port buffer registers, see Data Buffers on page 3-10. Control Registers (LCTLx). The control registers are used to enable the port, to set up DMA parameters, and to configure interrupts. Status Registers (LSTATx). Programs can see several aspects of link port operation using the status registers. These include bus status, buffer status, receive and transmit status, and errors.

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Clocking

Clocking
The link port clock is derived from the clock out generator based on the link port to core clock ratio. For more information, see Output Clock Generator on page 23-5. The link port to core clock ratios (1:2, 1:2.5, 1:3, 1:4) can be programmed in the PMCTL register. This programming is applicable only for the transmitter. The receiver can operate at any asynchronous frequency up to the maximum frequency, independent of the ratio programmed.

Functional Description
Each link port, shown in Figure 5-2, consists of eight data lines (LDATx70, x = 0, 1), a link port clock line (LCLKx), and a link port acknowledge line (LACKx). The LCLKx and LACKx pins of each link port allow handshaking for asynchronous data communication between DSPs. Other devices that follow the same protocol may also communicate with these link ports. The link port operates in half-duplex mode, only receive or transmit operation can happen per link port by using core or DMA. If full-duplex operation is required both link ports must be used. In receive operations, the data are received by the external receive buffer packed into 32-bit format and shifted to the internal receive buffer. The core or DMA read the data from the internal buffer. In transmit operations, the data are written to the internal transmit buffer and moved to the external transmit buffer to shift the data off-chip.The following sections provide details on this interface.

Architecture
Figure 5-2 shows the architecture of the link ports.

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Link Ports ADSP-2146x

LDATx7 -0

LACKx

LCLKx

LTRAN

TRANSMIT SHIFT BUFFER

CONTROL STATUS

RECEIVE SHIFT REGISTER

TRANSMIT BUFFER (2 DEEP)

RECEIVE BUFFER (2 DEEP)

DMA

PERIPHERAL CORE BUS IOD0 BUS

Figure 5-2. Link Port Block Diagram

Protocol
A link port transmitted word consists of 4 bytes (for a 32-bit word). The transmitter asserts the clock (LCLKx) high with each new byte of data. The falling edge of LCLKx is used by the receiver to latch the byte. The receiver asserts LACKx when it is ready to accept another word in the receive buffer, RXLBx. The transmitter samples LACKx driven by the receiver at the beginning of each word transmission (that is, after every 4 bytes with a positive level latch). If LACKx is deasserted at that time, the transmitter does not transmit the new word. The transmitter leaves LCLKx high and continues to drive the first byte if LACKx is deasserted. When LACKx is eventually asserted again, the transmitter drives LCLKx low and begins transmission of the next word. If the transmit buffer is empty, LCLKx remains low until the buffer is refilled, regardless of the state of LACKx.

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Functional Description

The following list describes the stages during a link port handshake. 1. The LCLK signal stays high at byte 0 if LACK is sampled low on the previous LCLK rising edge. LCLK high indicates a stall. 2. The LxACK signal may deassert after byte 0. 3. The LACK signal reasserts as soon as the link buffer is not full. 4. The transmitter samples LACK to determine whether to transmit the next word. 5. The receiver accepts the remaining word even if LACK is deasserted. The transmitter does not send the following word. 6. Transmit data for next word is held until LACK is asserted. The receive buffer may fill if a higher priority DMA, core I/O processor register access, or chain loading operation is occurring. The LACKx signal may deassert when it anticipates the buffer may fill. The LACKx signal is reasserted by the receiver as soon as the internal DMA grant signal has occurred, freeing a buffer location or the core reads the receive buffer RXLBx thereby freeing a buffer location. The LACKx signal inhibits transmission of the next word and not of the current byte. is latched in the edge of . Datareceive operation receive buffer on the falling can occur at any The is purely asynchronous and
LCLKx

frequency up to 166 MHz or peripheral clock frequency (whichever is less). When a link port is not enabled, LDAT7-0, LCLKx and LACKx are three-stated. When a link port is enabled to transmit, the data pins are driven with whatever data is in the output buffer, LCLKx is driven high and LACKx is three-stated. When a port is enabled to receive, the data pins and LCLKx are three-stated and LACKx is driven high.

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Intercommunication
The transmitter and the receiver may be enabled at different times. The LACKx and LCLKx signals should be held low with the external pull-down resistors. If the transmitter is enabled before the receiver, the LACKx signal (of the receiver) is held low and transmission is held off. If the receiver is enabled before the transmitter, the LCLKx signal (of the transmitter) is held low by the pull-down and the receiver is held off. that have link Unlike older SHARC processorshave an internalports, the resisADSP-2146x processors do not pull-down tor. Because of this there is no PDRDE bit available to disable the internal pull-down and an external pull-down (20K Ohms) is required on the LACKx and LCLKx signals. Figure 5-3, Figure 5-4 and Figure 5-5 show various timings for the link port.

LCLKx driven by transmitter

LCLKx held high until LACKx goes high

LACKx driven by receiver

LACKx may deassert after BYTE 0

LDAT7-0 driven by transmitter

BYTE 0 Transmit data held until LACKx is asserted

BYTE 1

BYTE 2

Figure 5-3. Enable Transmitter and Receiver at Different Times

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Functional Description

LCLKx DRIVEN BY TRANSMITTER LCLKx STAYS HIGH IF LA SAMPLED LOW ON PREV LCLKx FALLING EDGE

LACKx DRIVEN BY RECEIVER

LACKx MAY DEASSERT AFTER BYTE 0 TRANSMITTER SAMPLES LACKx HERE TO DECIDE WHETHER TO TRANSMIT NEXT WORD

LDAT7-0 DRIVEN BY TRANSMITTER

BYTE 1

BYTE 2

BYTE 3 (MSB)

BYTE 0 (LSB)

TRANSMIT DATA FOR NEXT WORD HELD UNTIL LACKx IS ASSERTED

Figure 5-4. Relationship Between LACK and LCLK

INTERNAL LINKCLK IN TRANSMITTER

LCLKx DRIVEN BY TRANSMITTER START OF FIRST BYTE TRANSMISSION

LCLKx HELD HIGH UNTIL LACKx GOES HIGH

LACKx DRIVEN BY RECEIVER LACKx MAY DEASSERT AFTER BYTE 0

Figure 5-5. Relationship Between Internal LCLK and LCLK at Pads

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Self-Synchronization
The link ports are designed to allow long distance connections to be made between the driver and the receiver. This is possible because the links are self-synchronizingthe clock and data are transmitted together. Only relative delay, not absolute delay between clock and data is relevant. In addition, the LACKx signal inhibits transmission of the next word, not of the current nibble or byte. Since the processor operates on 4 bytes of data words and the link ports are 1 byte wide, each transaction has a length of 4. The receiver pulls LACK low after the first byte of the word being received causing the buffer to fill. This ensures that 3 LCLK cycles are available for deassertion propagation to the transmitter.

Multi-Master Conflicts
Multi-master conflicts can be resolved using token passing. In token passing, the token is a software flag that passes between processors. This is described in more detail in the following section Example Token Passing. The example shown in Figure 5-6 is a typical case where the link port is used as fast I/O link. A FPGA bridge is required to communicate between two different protocols. If using both link ports, full duplex operation is possible without core intervention.
PCI BUS NETWORK CONTROLLER LINK PORT BUS ADSP-2146x

FPGA BRIDGE

Figure 5-6. Fast I/O Link

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Operating Modes

Operating Modes
The following sections describe the operating modes of the link ports.

Receive Link Service Request Mode

A Link Service Request interrupt can be generated when an external source accesses the link port when the link port is disabled. For transmitter it requires that the LTRQ interrupt is unmasked by setting LTRQ_MSK bit in the LCTLx register. When the transmitter is disabled, and the enabled receiver wants to initiate a transfer, it can drive LACKx high. When LACKx of the disabled link port is asserted, then a link service transmit request interrupt is generated and the receiver can initiate the transfer.

Transmit Link Service Request Mode

For the receiver, a Link Service Request requires that the LRRQ interrupt is unmasked by setting LRRQ_MSK bit in the LCTLx register. When the receiver is disabled, and the enabled transmitter wants to initiate transfer, it can drive LCLKx high. When LCLKx of the disabled link port is asserted, then a Link service receive request interrupt is generated and the transmitter can initiate the transfer.

Example Token Passing

When two ADSP-2146x processors communicate using a link port, only one can be the transmitter or receiver. Token passing is a protocol that assists the DSPs alternate control. Figure 5-7 on page 5-11 shows a flow chart of the token passing process.

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ORIGINAL MASTER
DMA TRANSFER COMPLETE LTRQ INTERRUPT ENABLED

ORIGINAL SLAVE
DMA TRANSFER COMPLETE LINK PORT CORE Rx ENABLED

LACK ASSERTION CAUSES LTRQ INTERRUPT LINK PORT Tx NON DMA ENABLED SEND TRW 4 TIMES TO FILL LINK PORT FIFOS ON BOTH SIDES CHECK LSTAT FOR SLAVE READ OF TRW BEFORE ACCEPTANCE TEST READ RECEIVE BUFFER TEST FOR TRW

CHECK LSTAT TO SEE IF SLAVE ACCEPTED TOKEN BY EMPTYING FIFOS IN ALLOTTED TIME PERIOD

ACCEPT TOKEN BY EMPTYING LINK PORT FIFOS THROUGH 3 MORE READS WITHIN THE ALLOTTED TIME PERIOD

SET UP LINK PORT FOR CORE Rx TO ACCEPT DMA SIZE SET UP LINK PORT FOR Rx DMA AND DMA COMPLETE IRQ

DISABLE LINK PORT AND LTRQ INTERRUPT POLL LSRQ STATUS FOR LINK PORT TRANSMIT REQUEST TO ENSURE THAT THE ORIGINAL MASTER IS NOW A SLAVE

LACK ASSERTION ASSURES THAT IT IS SAFE TO BEGIN TRANSMITTING SET UP LINK PORT FOR CORE Tx TO SEND DMA SIZE SET UP LINK PORT FOR Tx DMA AND DMA COMPLETE INTERRUPT

DMA TRANSFER COMPLETE DMA TRANSFER COMPLETE SET UP LINK PORT FOR CORE Rx SET UP LBUF FOR CORE Tx

Figure 5-7. Token Passing Flow Chart In token passing, the token is a software flag that passes between the processors. At reset, the token (flag) is set to reside in the link port of one device, making it the master and the transmitter. When a receiver link ADSP-214xx SHARC Processor Hardware Reference 5-11

Operating Modes

port (slave) wants to become the master, it may assert its LACKx line (request data) to get the masters attention. The master knows, through software protocol, whether it is supposed to respond with actual data or whether it is being asked for the token. The token release word can be any user-defined value. Since both the transmitter and receiver are expecting a code word, this does not need to be exclusive of normal data transmission. If the master wishes to give up the token, it may send back a user-defined token release word and thereafter clear its token flag. Simultaneously, the slave examines the data sent back and if it is the token release word, the slave sets its token, and can thereafter transmit. If the received data is not the token release word, then the slave must assume the master was beginning a new transmission. Through software protocol, the master can also request data by sending the token release word (TRW) without the LACKx (data request) going low first. The following is a list of the areas of concern when a program implements a software protocol scheme for token passing. The program must make sure that both link ports are not enabled to transmit at the same time. In the event that this occurs, data may be transmitted and lost due to the fact that neither link port is driving LACKx. In the example, the TLRQ status bit is polled to ensure that the master becomes the slave before the slave becomes the master, avoiding the two transmitter conflict. The program must make sure that the link interrupt selection matches the application. If a status detection scheme using the status bits is to be used, it is important to note the following: If a link port that is configured to receive is disabled while LACKx is asserted, there is an RC delay before the external pulldown resistor on LACKx (if enabled) can pull the value below logic threshold. If the LTRQ

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Link Ports ADSP-2146x

status bit is unmasked (in this instance), then an LSR is latched and the LSRQ interrupt may be serviced, even though unintended, if enabled. The program must make sure that synchronization is not disrupted by unrelated influences at critical sections where timing control loops are used to synchronize parallel code execution. Disabling of nested interrupts is one technique to control this.

Data Transfer
The link ports are able to transfer data using DMA and core.

Packing Registers
The transmit shift and receive shift registers work with the FIFO buffers as described below. Output Register The transmit shift register receives byte wide FIFO data or register data (address) and serially shifts its data out externally off chip. The output can be controlled for generation of acknowledgements or can be manually over written. The transmit pack register is clocked with the rising edge. Input Register The receive shift register receives its data serially from off chip. Internally the receive shift register is byte wide and data received can either be transferred to the FIFO buffer or used in an address comparison. The receive pack register is clocked with the falling edge.

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Data Transfer

Note that the transmit/receive pack registers are not memory mapped.
TRANSMIT 8-BIT BYTE 3 BIT 31 8-BIT BYTE 2 8-BIT BYTE 1 8-BIT BYTE 0 BIT 0 RECEIVE

Figure 5-8. Link Port Output Packing Transmit/Receive Registers

Buffers
The transmit buffer registers (TXLBx) and receive buffer registers (RXLBx) buffer the data flow through the link port. The transmit and receive buffers consist of a 2 deep buffer and a shift register. The registers read from or write to internal memory under DMA or processor core control. Transmit Buffer In the transmit path, the TXLBx buffer is used to accept core data or DMA data from internal memory. Data is transferred to the shift register to send unpacked bytes to the ports. The least significant byte is transmitted first. As each word is unpacked and transmitted, the next location in the FIFO becomes available and a new DMA request is made if DMA is enabled. If the shift register becomes empty, the LCLKx signal is deasserted. Receive Buffer In the RXLBx receive buffer, data is transferred to the core or DMA from the buffer whereas the shift register performs the packing, least significant byte first (the least significant byte is placed in bits 70). The LACKx signal is deasserted by the receiver as soon as it receives the first byte from transmitter if the buffer already has a word (the receive buffer RXLBx is already half full). The packing is done as shown in Figure 5-8.

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Link Ports ADSP-2146x

ADSP-2146x processor, the least significant byte is trans For thefirst. This is different to legacy processors (ADSP-2116x) mitted where the most significant byte is transmitted first. Buffer Status The entire receive and transmit path form a 3-stage FIFO. Two writes/reads can occur to the transmit/receive buffer by the core or DMA before it signals a full/empty condition. Full/empty status for the link buffer is shown by the FFST bits in the LSTATx register. If the link port is configured as a transmitter, then the FFST bits in the LSTATx register reflect the status of the TXLBx register. If the link port is configured as a receiver, then the FFST bits in LSTATx register reflect the status of RXLBx. Buffer Reception Error The LERR bit (LSTATx register) reports the byte packing complete status (complete/incomplete). Flushing Buffers Disabling the link port flushes the transmit and receive buffers. Buffer Hand Disable For more information, see Buffer Hang Disable (BHD) on page 5-23.

Core Transfers
In applications where the latency of link port DMA transfers to and from internal memory is too long, or where a process is continuous and has no block boundaries, the processor core may read or write link buffers directly using the full or empty status bit of the link buffer to automatically pace the operation. The full or empty status of a particular link

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Data Transfer

buffer can be determined by reading the LSTATx bits in the LCTL register.

DMA should be disabled if reading or writing to the link port buffers.

If a read is attempted from an empty receive buffer, the core stalls (hangs) until the link port completes reception of a word. If a write is attempted to a full transmit buffer, the core stalls until the external device accepts the complete word. Up to four words (2 in the receiver and 2 in the transmitter) may be sent without a stall before the receiver core or DMA must read a link buffer register. To support debugging buffer transfers, the processor has a buffer hang disable (LP_BHD) bit. When set (=1), this bit prevents the processor core from detecting a buffer-related stall condition, permitting debugging of this type of stall condition.

DMA Transfers
Each link port supports a DMA channel. link ports do not The previous SHARCssupport internal to internal memory transfers like (no link assignment register). If internal to internal memory transfers are required, refer to Chapter 6, Memory-to-Memory Port DMA. In standard DMA operations, the software needs to set up the DMA parameter registers before the link port control register is configured. After setting the DMA enable bit the transfer starts until the word count reaches zero, the DMA has finished.

Link Port DMA Group Priority

The link port 0 and 1 modules each have a DMA channel which are grouped together. When both channels have data ready, the channel arbi-

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Link Ports ADSP-2146x

trates by rotating using a round robin method (which is the first arbitration stage). The winning channel requests the DMA bus arbiter to get control of the peripheral DMA bus (2nd stage of arbitration). The I/O processor considers the two DMA channels as a single group and therefore one arbitration request. For more information, see Peripheral DMA Arbitration on page 3-36.

Interrupts
The following sections and Table 5-2 provide details on using link port interrupts. Table 5-2. Link Port Interrupt Overview
Default Programmable Interrupt LP0I/LP1I not connected by default Sources Masking Service

- DMA complete - DMA chain TCB complete - core buffer access - internal transfer completion - access completion - link service request - invalid transmit attempt

N/A

ROC from LSTATx + RTI instruction

Sources
The link port interrupt is not connected by default to the IVT. Operating with status interrupts the corresponding LP0I or LP1I must be routed to a programmable IVT by using the PICR registers. The link ports generate interrupts under the conditions described in the following sections.

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Interrupts

Core Buffer Service Request When DMA is disabled the processor core may read from the RXLBx buffer or write to the TXLBx buffer. An interrupt is generated when the receive buffer is not empty or the transmit buffer is not full. DMA Complete A DMA channel interrupt is generated when a DMA block transfer through the link port with DMA enabled completes. Internal Transfer Complete The transmitter generates an internal transfer completion interrupt (DMACH_ IRPT_MSK = 1 and EXTTXFR_DONE_MSK = 0). Once the DMA count is zero, this interrupt is generated regardless of the state of the transmitter FIFO (traditional mode). Access Complete The transmitter generates an access completion interrupt (DMACH_IRPT_MSK = 0 and EXTTXFR_DONE_MSK = 1) once the external transfer is completed. When DMA is not enabled, this interrupt is generated when the transmitter FIFO is empty and the last byte has been transmitted. If using DMA, the transmitter checks if the DMA is complete. Link Service Request A link service request interrupt is generated when an external source accesses the link port when the link port is disabled. For example, if the enabled receiver wants to initiate a data transfer with the disabled transmitter, it can make LACKx high. When LACKx of the disabled link port goes high, then a link service request interrupt is generated. Now the receiver can initiate the transfer.

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Chained DMA For chained DMA, if the PCI bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the PCI bit is set (= 1), then a DMA interrupt is generated for each TCB. Protocol Error A link port invalid transmit (LPIT) is generated if the transmitter is driving LCLKx high because the receiver has not asserted LACKx and LCLKx goes low due to a processor reset (or some other reason, even though the receiver has not yet asserted LACKx). In this case, the receiving link port generates an interrupt.

Masking
The LP0I and LP1I signals are not routed by default to programmable interrupts. To service the LPxI, unmask (set = 1) any programmable interrupt bit in the IMASK/LIRPTL register.

Service
Status interrupts are latched and stored in the corresponding status register. In the ISR, programs should read the corresponding status register (LSTATx) which clears the interrupt bits. Reading the status register when an interrupt occurs causes the core to hang until the interrupt bits are set in the status register. Otherwise, a simultaneous read and update of the status register results in a loss of information. This hang cannot be overridden with the BHD bit LPCTLx register. Error interrupts are latched and stored in the corresponding status register.

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Effect Latency

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

Link Port Effect Latency

After the link port registers are configured the effect latency is 2 PCLK cycles.

Programming Model
The following sections provide information on programming receive and transmit DMA and changing the link port clock.

Changing the Link Port Clock

The following programming sequence may be used to change the core-to-link port clock ratio only. Note that this procedure changes only the PLL output divider. Therefore programs do not need to wait 4096 CLKIN cycles (required only if the PLL multiplier or the INDIV bit is modified). 1. Disable the link ports. Note that the peripherals cannot be enabled when changing clock ratio. 2. Select the PLL divider by setting the PLLDx bits (bits 67 in the PMCTL register).

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Link Ports ADSP-2146x

3. Select the link port clock divider (CCLK to LPCLK ratio) by setting the LPCKRx bits (bits 21 and 22 in the PMCTL register). 4. Enable the new divisors by setting the DIVEN bit (bit 9 in the PMCTL register). 5. Wait 15 CCLK cycles. During this time, programs must not execute any valid instructions. The LPCLK change does not happen on-the-fly. This means that when a clock ratio change is registered, the current clock cycle may get truncated before the change and the new clock cycle ratio start. 6. Enable link ports. For more information on link port clocking and programming the PLL, see Phase-Locked Loop (PLL) on page 23-2.

Receive DMA
The following is the sequence that occurs when an external device transfers a block of data into the processors internal memory using a link port. that the link ports not support internal internal mem Notetransfers like previousdoSHARCs. If internal totointernal memory ory transfers are required, refer to External Port DMA on page 4-120. 1. The processor writes the DMA channels parameter registers (index register IILBx, modify register IMLBx and count register CLBx) and initializes the link port for receive (LTRAN = 0). 2. The processor enables the link port by setting the LEN bit. DMA is enabled by setting the LDEN bit in the LCTLx register. 3. The external device begins writing data to the RXLBx buffer through the link port.

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Debug Features

4. The RXLBx buffer detects that data is present and sends a internal DMA request. 5. After the request is granted, the DMA transfer is performed thereby emptying the RXLBx buffer FIFO.

Transmit DMA
The following is the sequence that occurs when the processor transfers a block of data from its internal memory to an external device using link port. 1. The processor writes the DMA channels parameter registers (index register IILBx, modify register IMLBx and count register CLBx) and initializes the link port for transmit (LTRAN = 1). 2. The processor enables the link port by setting the LEN bit and enables the link port DMA by setting the LDEN bit in the LCTLx register. Because this is a transmit, setting LDEN automatically asserts an internal DMA request. 3. After the request is granted the internal DMA transfer is performed filling the TXLBx buffers FIFO. 4. The external device begins reading data from the TXLBx buffer through the link port. 5. The TXLBx buffer detects that there is room in the buffer (partially empty) and asserts another DMA request continuing the process.

Debug Features
The following sections provide information on features that help in debugging link port software.

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Shadow Register
For ease of debug all registers are available as shadow registers. For the transmit path, the TXLB1-0_IN_SHADOW register is the data buffer while the TXLB1-0_OUT_SHADOW register is the pack register which is connected to the link port data. For the receive path, the RXLB1-0_IN_SHADOW register is the data buffer while the RXLB1-0_OUT_SHADOW register is the pack register which is connected to the link port data. Reading these registers does not change link port status. Moreover, the LSTAT1-0_SHADOW registers allows programs to read the status and clear the interrupt bits.

Buffer Hang Disable (BHD)

A buffer hang disable (BHD) bit has been provided in the control register (LPCTLx). Setting this bit to 1 prevents the core from hanging when a read from an empty receive buffer or a write to a full transmit buffer is attempted. If the BHD bit is set and a read is performed from an empty receive buffer, then the previous data is returned. Writing to a full transmit buffer with the BHD bit set overwrites the existing data.

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Debug Features

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6 MEMORY-TO-MEMORY PORT DMA

Table 6-1 shows the memory-to-memory DMA port specifications. Table 6-1. MTM Port Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Yes No Yes 2 No Yes No Yes No No No No N/A No N/A Yes Availability

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Features

Table 6-1. MTM Port Specifications (Contd)

Feature Boot Capable Local Memory Clock Operation Availability No No fPCLK

Features
The memory-to-memory port incorporates: 2 DMA channels (read and write) Internal to internal transfers Data engine for DTCP applications (only for special part numbers) Note that the SHARC supports another internal to internal DMA module (external port) which supports multiples DMA modes.

Register Overview
MTM Control Register (MTMCTL). Enables the read and write DMA channels across the internal memory and returns status about the read or write DMA channel.

Clocking
The fundamental timing clock of the MTM is peripheral clock (PCLK). The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

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Memory-to-Memory Port DMA

Functional Description
The MTM module owns two DMA channels one for read and one for write including a data buffer which stores up to 2x32-bit data. After the DMA is configured, the read DMA channel fills the buffer with 64-bit data. After this transfer, the write DMA channel becomes active and empties the buffer according to its destination. This procedure is repeated until the DMA count is zero. The memory-to-memory DMA controller is capable of transferring 64-bit bursts of data between internal memories. in normal word The MTM controller supports dataDMA transfers areaddress space only (32-bit). External to external not supported.

Data Transfer Types

The memory-to-memory DMA controller is capable of transferring 64-bit bursts of data between internal memories.

Buffer
For memory-to-memory transfers the two stage buffer is the interface between the write and read channels. The write channel fills up the buffer first which triggers the read channel. After two reads the buffer becomes empty which re-triggers the write channel. MTM performance is therefore dependent on the buffer depth.

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Interrupts

Buffer Status The buffer status cant be directly read from the control register. However both DMA channels (read and write) return the status if the channels are pending or active MTMDMAxACT bits Flushing the Buffer The MTMFLUSH bit in the MTMCTL register can be set to flush the FIFO and reset the read/write pointers. Setting and resetting the MTMDEN bit only starts and stops the DMA transfer, so it is always better to flush the FIFO along with MTMDEN reset. Note that the MTMFLUSH bit should not be set along with the MTMDEN bit set. Otherwise the FIFO is continuously flushed leading to DMA data corruption.

DMA Transfer
Two DMA channels are used for memory-to-memory DMA transfers. The write DMA channel has higher priority over the read channel. The transfer is started by a write DMA to fill up the MTM buffer with a 2 x 32-bit word. Next, the buffer is read back over the same IOD bus to the new destination. With a two position deep buffer and alternate write and read access over the same bus, throughput is limited. The memory-to-memory DMA control register (MTMCTL) allows programs to transfer blocks of 64-bit data from one internal memory location to another. This register also allows verification of current DMA status during writes and reads.

Interrupts
There are two DMA channels; one write channel and one read channel. When the transmission of a complete data block is performed, each channel generates an interrupt to signal that the entire block of data has been

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Memory-to-Memory Port DMA

processed. Note that the write and read interrupts (P15I, if the MTMI bit in the IMASK register is enabled) are very close to each other, so only one interrupt is triggered. Table 6-2 provides an overview of MTM interrupts. Table 6-2. MTM Interrupt Overview
Default Programmable Interrupt MTM = P15I Sources DMA write complete DMA read complete Masking N/A Service RTI instruction

Sources
There are two interrupt signalsone for the write and one for read channel. The MTM port can generate interrupts under the conditions described in the section below. DMA Complete When the transmission of a complete data block is performed, each DMA channel (write/read) generates an interrupt to signal that the entire block of data has been processed. If both channels are enabled interrupts occur very close to each other, and the read interrupt is aborted. This is because the read interrupt is dependent on write interrupt .

Masking
The MTMI signal is routed by default to programmable interrupt. To service the MTMI, unmask (set = 1) the P15I bit in the IMASK register. For example:
bit set IMASK P15I; /* unmasks P15I interrupt */

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MTM Throughput

Service
Interrupts are serviced with a RTI (return from interrupt) instruction.

MTM Throughput
Data throughput for internal to internal transfers is 12 PCLK cycles for 64-bit data.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

MTM Effect Latency

After the MTM register is configured the effect latency is 1.5 PCLK cycles minimum and 2 PCLK cycles maximum.

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Programming Model
This data transfer can be set up using the following procedure. 1. Program the DMA registers for both channels. 2. Set (=1) the MTMFLUSH bit (bit 1) in the MTMCTL register to flush the FIFO and reset the read/write pointers. 3. Set (=1) the MTMEN bit in the MTMCTL register. A two-deep, 32-bit FIFO regulates the data transfer through the DMA channels.

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Programming Model

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7 FFT/FIR/IIR HARDWARE MODULES

Finite Impulse Response (FIR) filters are frequently used in DSP applications. With its high performance floating-point processing capabilities the SHARC processors are uniquely designed for FIR filtering. The SIMD SHARC core has two MAC units which provide 800 MIPS of processing speed when the processor is running at 400 MHz. However, for high performance applications, with their ever increasing complexity (such as room equalization or surround sound), even more processing power is needed.

Each of the accelerator modules (FFT/FIR/IIR) have access to the internal memory only.
To meet this need, the ADSP-214xx SHARC processors off load some of the most frequently used and intensive processing into hardware accelerators. An accelerator dedicated for filter processing can reduce the instruction processing load on the core, freeing it up for other tasks. The FIR/IIR/FFT accelerator units are capable of performing the filters and FFT without core intervention. This gives software developers enormous freedom to use core processing cycles to implement complex algorithms, effectively adding more instructions per second to the processor. local memory The accelerator modules (FFT/FIR/IIR) each haveoperation mode. which is not accessible by the core during regular The interface specifications are shown in Table 7-1.

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Table 7-1. Accelerator Specifications

Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation Yes No Yes 2 Yes N/A Yes (RAM) fPCLK N/A N/A N/A N/A N/A No No N/A No N/A Yes FFT/FIR/IIR

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FFT Accelerator
The FFT accelerator (shown in Figure 7-1) implements radix-2 complex floating-point FFT. The accelerators data and twiddle coefficient interface is designed to connect to the processors DMA engine (acting like a peripheral) and implements a synchronous pipeline read/write protocol with a pipeline depth of 1.
PERIPHERAL BUS IOD0 BUS

FFT CONTROL REGISTERS

FFT CONTROLLER

DMA CONTROLLER

INPUT BUFFER

OUTPUT BUFFER

256x2

256x4

C O E F F I C I E N T S

COEFF ACCESS CONTROL

FFT COMPUTE UNIT (Complex Butterfly)

DATA ACCESS CONTROL

D A T A

Figure 7-1. FFT Block Diagram

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FFT Accelerator

Features
The following list describes the features available through the FFT accelerator. Supports FFT sizes from 16 8k2 points all handled by DMA with no core intervention. Computes a radix 2 decimation in time algorithm with automated bit reversal. Contains a 1024 32-bit word data memory unit. Contains a 512 32-bit word twiddle coefficients memory unit. Contains a compute block unit with four floating-point multipliers and six floating-point adders. Has a control unit with configuration registers, responsible for all memory addresses and strobe generation. Contains a 8 32 deep input/output FIFO unit.

Register Descriptions
The accelerator has two control and two status registers that are used to program and check operation of the module. The module also contains DMA registers which are described inI/O Processor in Chapter 3, I/O Processor. Power Management Control Register (PMCTL1). Used for FFT accelerator selection. Controls the clock power down to the module if not required. Global Control Register (FFTCTL1). Used to enable, start, and reset the FFT module. It is also used to enable DMA and debug operation.

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Control Register (FFTCTL2). Used to configure individual FFT parameters (such as length) and how the module process the FFT, such as data packing. MAC Status Register (FFTMACSTAT). Reports errors and status on the multiply/accumulator. DMA Status, Shadow DMA Status Registers (FFTDMASTAT, FFTSHDMASTAT). Provide information on DMA operations such as DMA progress and chain pointer loading.

Clocking
The FFT accelerator runs at the maximum speed of the peripheral clock (PCLK). The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

Functional Description
The FFT accelerator is comprised of a compute block, data memory and coefficient memory. The design allows programs to off-load an FFT calculation by initializing few TCBs and control registers. In this way, the FFT accelerator can perform the FFT calculation in the background while the core is busy doing some other useful task. It can interrupt the core once the processing is complete. The following sections provide functional details of the FFT accelerator. Compute Block The compute block contains one complex butterfly stage (based on four IEEE floating-point multipliers and six IEEE floating-point adders) whose operation is pipelined and simultaneous.

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FFT Accelerator

Data Memory The accelerator has a 1024 location deep, 32-bit wide data memory, organized into four independent blocks. Blocks are grouped in sets of two that are used to fetch or store real and imaginary parts of data simultaneously. Fetches and stores are accomplished by ping-ponging the read and write buffers. Coefficient Memory The accelerator has a 512 location deep, 32-bit wide twiddle memory, organized into two independent blocks (256x2). It allows fetching real and imaginary twiddles simultaneously. Accelerator States The FFT accelerator has five different states: 1. Reset 2. Idle 3. Reading 4. Processing 5. Writing These states are described in detail in the following sections.
Reset State

Reset mode is activated either by setting the FFT_RST bit in the FFTCTL1 register or by applying logic low to the RESET input pin. If reset is activated by setting the FFT_RST bit, this bit must be cleared to bring the accelerator out of reset.

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Resetting via a logic low to the RESET pin resets all registers, thereby clearing the FFT_RST bit. Once the processor is brought out of reset by applying a logic high to the RESET pin, the FFT module goes into the idle state in the next clock cycle.
Idle State

This mode is used to program the accelerators control registers. Setting the FFT_EN and FFT_START bits in the FFTCTL1 register moves the state from idle to reading.
Read State

In this state the module reads data and coefficients, but counts the number of read data only. This is because for successive FFT calculations the coefficient need not be read againonly the next set of data has to be read. When a specified number of data words are read, the state automatically moves to processing.
Processing State

In this mode the module computes FFT ping-pong stages in memory. Once this is done, the state automatically moves to the write state.
Write State

In this mode all the computed data is written out to internal memory. The state then automatically changes to either idle or read, depending on the way the block is configured using the repeat function (FFT_RPT bit in the FFTCTL2 register). If the FFT_RPT bit is set, the block moves to the read state, if cleared, the block moves to the idle state. The FFT_RPT bit is useful when programs need to continuously perform an FFT on input data without core intervention.

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Internal Memory Storage This section describes the required software buffers in internal memory and the required storage model for data and coefficients using the FFT accelerator.
Small FFT N<=256

To run a small FFT three buffers are required: Input Buffer [2 N] packed or unpacked data Output Buffer [2 N] packed or unpacked data Coefficient Buffer [2 N]
Unpacked Data

If unpacked data is selected this is the required input format or output format. Programs can optionally select the input or output data streams to be unpacked. In this mode, the first samples are all real followed by the imaginary samples.
RE[0], RE[1], ...RE[N-1], IM[0], IM[2], ... IM[N-1]

This can be independent for the input or output data streams.

Packed Data

The default format for packed data is as follows.

RE[0], IM[0], RE[1], IM[1], .... RE[N-1], IM[N-1]

Twiddles

The default format for coefficient buffer (twiddles) is as follows.

Re(CF[0]), Im(CF[0]), -Im(CF[0]), Re(CF[0]), Re(CF[1]), Im(CF[1]), -Im(CF[1]), Re(CF[1]),.......... Re(CF[N/2-1]), Im(CF[N/2-1]), -Im(CF[N/2-1]), Re(CF[N/2-1]) (4xN/2 = 2N words)]

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Large FFT N>256

To run a large FFT, 6 buffers are required: Input Buffer [2 N] (packed data) Special Buffer [2 N] (intermediate buffer used in step 1 for vertical FFT and in step 2 for special product = Product of vertical buffer with special twiddles) Output Buffer [2 N] (packed data) Vertical complex Coeff Buffer [2 V] Horizontal complex Coeff Buffer [2 H] Special complex Coeff Buffer [4 N]
Twiddles

For N>256, the FFT accelerator follows the Divide and Conquer approach. Therefore, three types of coefficient buffers are required: Complex Coefficient buffer for V point FFT
Re(CF[0]), Im(CF[0]), -Im(CF[0]), Re(CF[0]), Re(CF[1]), Im(CF[1]), -Im(CF[1]), Re(CF[1]), .......... Re(CF[V/2-1]), Im(CF[V/2-1]), -Im(CF[V/2-1]), Re(CF[V/2-1]) (4xV/2 = 2V words)

Complex Coefficient buffer for H point FFT

Re(CF[0]), Im(CF[0]), -Im(CF[0]), Re(CF[0]), Re(CF[1]), Im(CF[1]), -Im(CF[1]), Re(CF[1]), .......... Re(CF[H/2-1]), Im(CF[H/2-1]), -Im(CF[H/2-1]), Re(CF[H/2-1]) (4xH/2 = 2H words)

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Special complex coefficient buffer

Re(SP_CF[0]), Im(SP_CF[0]), -Im(SP_CF[0]), Re(SP_CF[0]), Re(SP_CF[1]), Im(SP_CF[1]), -Im(SP_CF[1]), Re(SP_CF[1]), .......... Re(SP_CF[N-1]), Im(SP_CF[N-1]), -Im(SP_CF[N-1]), Re(SP_CF[N-1]) (4N words).

Where,
Re(CF[x]) Im(CF[x])

= Real part of the complex coefficient CF[x], = Imaginary part of the complex coefficient CF[x], = Real part of special complex coefficient SP_CF[x], = Imaginary part of special complex coefficient SP_CF[x]

Re(SP_CF[x]) Im(SP_CF[x])

SP_CF[n]=WN^vxh where n = vxH + h, h = 0, 1,. H1, v = 0, 1,. V1. For more information see EE-322, Expert Code Generator for SHARC Processors. This EE note can be fount on the analog Devices web site.

Operating Modes
The following sections describe FFT processing types and methods. Small FFT Computation (<= 256 Points) A small FFT (NOVER256 = zero) can be handled completely in one step since the twiddles and input data stream fit in the local memories for twiddles and data. In this way two input TCBs (twiddles and data) are fed into the accelerator. After performing the FFT the output TCB writes the results back into the internal memory and the next FFT can start.

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Large FFT Computation (> 256 Points) For large FFTs (NOVER256 = non zero) the model looks different since the twiddle/data do not fit completely into the local memories. The FFT computation is matrix based on rows (horizontal) and columns (vertical) and performed in three steps:
x(0) x(1) x(2) . . . . x(H - 1) x(H) x(H + 1) x (H + 2) . . . x(2H - 1) x(2H) x(2H + 1) x(2H + 2) . . . . x(3H - 1) | | | . . | x((V - 1)H) x((V - 1)H + 1) x((V - 1)H + 2) . . . . x(VH - 1)

1. The vertical (column) V Point FFTs are performed on the matrix. 2. The output of step 1 is multiplied by special twiddles (special coefficients). 3. Horizontal (row) H Point FFTs are performed on the output matrix of Step 2. This produces the final FFT on vertical columns (column wise). The final FFT result is obtained in internal memory, not local memory. Example for FFT Size N=512 This example shows a large FFT matrix of V H = 32 16.
Vertical FFT

1. Input coeff DMA from vertical coeff buffer[64] 2. Input data DMA from input buffer[1024] (modifier = 2H, circbuf = 2N) 3. FFT computation 4. Output DMA to special buffer[1024]

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Special ProductNumber of Iterations is N/128 = 4

1. First iteration: a. Input coeff DMA from special coeff buffer[512] b. Input DMA from special buffer[256] c. FFT computation d. Output DMA to Special buffer[256] 2. Second iteration: a. Input coeff DMA from special coeff buffer[512] (offset = 512) b. Input DMA from special buffer[256] (offset = 256) c. FFT computation d. Output DMA to special buffer[256] (offset = 256) 3. Third iteration: a. Input coeff DMA from special coeff buffer[512] (offset = 1024) b. Input DMA from special buffer[256] (offset = 512) c. FFT computation d. Output DMA to special buffer[256] (offset = 512) 4. Fourth iteration: a. Input coeff DMA from special coeff buffer[512] (offset = 1536) b. Input DMA from special buffer[256] (offset = 768)

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c. FFT computation d. Output DMA to special buffer[256] (offset = 768)

Horizontal FFT

1. Input coeff DMA from horizontal coeff buffer[32] 2. Input data DMA from special buffer[1024] (modifier = 2V, circbuf = 2N) 3. FFT computation 4. Output DMA to Output Buffer[1024] (modifier = 2V, circbuf = 2N) This FFT generates a total of six partial FFT computations. Each computation has an input and output DMA which results in 12 interrupts. No Repeat Mode If the FFT_RPT bit = 0, after FFT_START = 1 the accelerator moves from the idle state into the read state (input DMA). After the read completes, the accelerator moves into the processing state then the write state to read the results back into internal memory. The accelerator ends in the idle state. For large FFTs (based on the VDIM, HDIM and NOVER256 bits) the accelerator knows when the entire FFT processing has finished. Repeat Mode If the FFT_RPT bit = 1, after FFT_START = 1 the accelerator moves from the idle state into the read state (input DMA). After the read completes, the accelerator moves into the processing state then the write state to read the results back into internal memory. The accelerator then moves automatically back into the read state for the next FFT frame. In this state multiple linked TCBs which were executed during the first iteration are re-used.

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FFT Accelerator

For large FFTs (based on the configuration of the VDIM, HDIM and NOVER256 bits) the accelerator knows when the entire frame processing has finished in order to re-load the new FFT frame parameters at the right time. Unpacked Data Mode For small FFTs (FFT<=256), the unpacked data mode can be selected independently for the input or output streams through the use of the FFT_CPACKIN or FFT_CPACKOUT bits (FFTCTL2 register).

The points. The/ input is alwayssettings aretonot applicable forreal < 512 expected be in alternate
FFT_CPACKIN FFT_CPACKOUT

and imaginary format and the output is always generated in the same format. Inverse FFT The inverse FFT uses the same algorithm as the forward FFT. The accelerator takes advantage of this fact when processing IFFTs by setting up a coefficient TCB with change of sign for the sine twiddles (FFT uses twiddles cosine, sine, -sine, cosine, the IFFT uses cosine, -sine, sine, cosine). When TCB loading completes, the accelerator processes the inverse FFT and returns the data into the local data memory. Finally, in write mode, data is returned to internal memory. In order to get the correct amplitude for the inverse FFT, the output buffer needs to be scaled by 1/N.

Data Transfer
The FFT accelerator works exclusively through DMA and therefore does not require core intervention. This allows the core to perform other system tasks. The core is used to configure the DMA parameter registers and the accelerator control registers and to start accelerator operation.

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FFT/FIR/IIR Hardware Modules

FFT Buffers As shown in Figure 7-1 on page 7-3, the input and output DMA stream each pass an 8 deep buffer. These I/O buffers ensure that the FFT stream of the accelerator is not stalled during high DMA bus loads. Note that the buffer status cannot be read.
Buffer Status

Buffer status cannot be read.

Flushing the Buffer

The FFT does not have any control bit for flushing the buffers. The buffers are flushed by entering into reset mode. DMA Transfers The FFT accelerator supports circular buffer chained DMA. Two TCB structures are associated with input and output DMA. The input TCB structure is used for transferring either data or coefficients to the accelerator block and the output TCB is used for receiving data from the FFT block to the internal memory of the SHARC processor. For TCB structure details see FFT Accelerator TCB on page 3-19.
DMA Channels and TCB Structure

The accelerator has two DMA channels that connect to internal memory. The channels fetch the data and coefficients from internal memory and store the results to internal memory. The DMA controller supports circular buffer chain pointer DMA. Separate TCBs must be created for both input and output DMA. Note that bit 20 of the input chain pointer register (FFTICP) indicates whether the TCB is for loading data or coefficients. If the TCB is a coefficient TCB, then circular buffering is not supported and the input length and base registers are ignored.

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FFT Accelerator

Table 3-21 on page 3-19 and Table 3-22 on page 3-19 show the input and output TCB structures.
Chained DMA

The DMA controller supports circular buffer chain pointer DMA. The input TCB structure consists of index, modify, count and chain-pointer register values for input data. The input TCB also consists of length and base pointer register values to support circular buffering. Similar to the input TCB structure, the output TCB also consists of index, modify, count, chain pointer, length and base pointer register values to support circular buffered chained DMA for output data. Once the accelerator is enabled, it loads the TCB values pointed to by the chain pointer register value into its internal registers. The FFT accelerator uses the input TCB values to fetch coefficients and data. It then computes the FFT on the fetched data without any core intervention. Once the computing is complete, the results are stored into the internal memory of the processor using the TCB values of the output TCB registers. If the repeat bit (FFT_RPT) is set, the accelerator goes continues on a new FFT frame once the current FFT frame is processed. One or more Transfer Control Blocks (TCB) chained to each other may need to be configured for both input and output DMA channels. Each of these TCBs may contain any of the following. DMA parameter register values for input data. DMA parameter register values for twiddles load. DMA parameter register values for output data. Intermediate results for large FFT are stored in the internal memory. DMA parameter register values for intermediate input/output data (required only for large FFT).

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DMA parameter register values for special twiddles (required only for small FFT) access The circular matrix.type is used for large FFTs to process the entire FFT (VxH)
20 19

. . . 5 Buffer Length Register 4 3 2 1 Base Register Index Register

Figure 7-2. Circular Buffer Addressing

Interrupts
Table 7-2 provides an overview of FFT interrupts. Table 7-2. FFT Interrupt Overview
Default Programmable Interrupt Sources Masking N/A Service ROC from FFTDMASTAT + RTI instruction ROC from FFTMACSTAT + RTI instruction

ACC0I/ACC1I not con- Input DMA complete nected by default Output DMA complete

MAC IEEE floating point N/A exceptions

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Sources The FFT module drives two interrupt signals, ACC0I for the DMA status and ACC1I for the MAC status. The FFT module generates interrupts as described in the following sections.
DMA Complete

The DMA interrupt is shared by the input and output DMA. They are generated at the end of every chain or at the end of an entire DMA sequence, depending on the PCI value in the respective chain pointer registers. The interrupt follows the access completion rule, where the interrupt is generated when all data are written back to internal memory.
MAC Status

A MAC status interrupt is generated under these conditions MAC underflow Set if MAC result to small MAC overflow Set if MAC result overflows MAC not a number Set if number is not IEEE compliant MAC denormal Set if number is not IEEE compliant
Chained DMA

For chained DMA, if the PCI bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the PCI bit is set (= 1), then a DMA interrupt is generated for each TCB. Masking The ACC0I and ACC1I signals are not routed by default to programmable interrupts. To service the ACCxI, unmask (set = 1) any programmable interrupt bit in the IMASK/LIRPTL register.

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Service When a DMA interrupt occurs, programs can find whether the input DMA interrupt occurred or the output DMA interrupt occurred by reading the DMA status register (FFT_DMASTAT). The DMA interrupt status bits are sticky and are cleared by a read. When a MAC status interrupt occurs, programs can find whether the MAC interrupt occurred by reading the MAC status register (FFT_MACSTAT). The MAC interrupt status bits are sticky and are cleared by a read.

FFT Performance
In this section: V = Number of rows H = Number of columns N=VH Reads from internal memory take 2 cycles/word. Writes to internal memory take 1 cycle/word. It takes 2 PCLK cycles to compute a single complex butterfly by the FFT computation. For performance consideration each FFT computation is accompanied with a preceding Read DMA and a post write DMA. Small FFT (N is <= 256) Data reads: 2N 2 Butterfly computes: N log2N cycles (A radix2 takes N/2 log2N 2 PCLK cycles) Data write: 2N 1

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Large FFT (N >= 256) Total number of performance cycles = (Vertical FFT + Special Prod + Horizontal FFT) cycles.

Vertical FFT Cycles

Data and coefficient reads: 2N 2 + 2V 2 Butterfly computes: (Vlog2V) H Data writes: 2N 1

Special Prod Cycles

Data and coefficient reads: 2N 2 + 4N 2 Product compute: 2 4N/4 Data writes: 2N 1

Horizontal FFT Cycles

Data and coefficient reads: 2N 2 + 2H 2 Butterfly compute: (Hlog2H) V Data writes: 2N 1 For the large FFT mode the entire expression is 28N + Nlog2N + 4 (V+H) PCLK cycles. Only the term dependent on H and V is 4. In order to improve performance V and H should be selected in such a way that H + V is minimum. For N=512, (H,V) should be (16,32) or (32,16). For N=1024, (H,V) should be (32,32) and so on.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

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Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. FFT Accelerator Effect Latency After the FFT registers are configured the effect latency is 1.5 PCLK cycles minimum and 2 PCLK cycles maximum. Writes to the PMCTL1 register have an effect latency of two PCLK cycles. Wait for at least four CCLK cycles after selecting an accelerator before accessing any of its registers.

Programming Model
There are two separate programming models, one for a FFT that fits in the accelerators internal memory (N = 256 points or less) and one for a FFT that is larger than the accelerators internal memory (N = 512 points or more). In both models, is assumed that the accelerator starts in idle mode. N <= 256, No Repeat For details on the storage format of the coefficients see Internal Memory Storage on page 7-8. 1. Configure the ACCSEL bits in the PMCTL1 register to select the FFT accelerator. 2. Program the FFTCTL2 register with: VDIM = N/16 LOG2VDIM = Log2(N) HDIM = 0 LOG2HDIM = 0 FFT_RPT = 0 FFT_CPACKIN/FFT_CPACKOUT = 0 or 1 depending on whether input/output data is packed into complex words or sent/received data is real or imaginary.

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3. Set (=1) the FFT_RST bit in the FFTCTL1 register and wait for a minimum of 4 CCLK cycles. 4. Program control register FFTCTL1 with: FFT_RST = 0 FFT_EN = 1 FFT_START = 1 FFT_DMAEN = 1 FFT_DEBUG = 0 5. Configure a coefficient DMA to read N complex twiddle factors from the coefficient buffer into the accelerator (total of 2N 32- bit words) and wait until the DMA is complete (or chain DMA in Step 4). This step is not needed if twiddles are already in the coefficient memory of the accelerator. 6. Configure a data DMA to read N complex data points from the input buffer into the accelerator (total of 2N 32-bit words). 7. Configure a data DMA to write N complex data points from the accelerator into the output buffer (total of 2N 32-bit words). There is no need to wait until the DMA in Step 6 completes. 8. Wait until the DMA in Step 7 completes (by interrupt or polling). The computed FFT is now in the cores internal memory and the accelerator is in idle mode. N <= 256, Repeat For details on the storage format of the coefficients see Internal Memory Storage on page 7-8 . 1. Configure the ACCSEL bits in the PMCTL1 register to select the FFT accelerator.

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2. Program the FFTCTL2 register with: VDIM = N/16 LOG2VDIM = Log2(N) HDIM = 0 LOG2HDIM = 0 FFT_RPT = 1 FFT_CPACKIN/FFT_CPACKOUT = 0 or 1 depending on whether input/output data is packed into complex words or sent/received data is real or imaginary. 3. Set (=1) the FFT_RST bit in the FFTCTL1 register and wait for a minimum of 4 CCLK cycles. 4. Program the FFTCTL1 register with: FFT_RST = 0 FFT_EN = 1 FFT_START = 1 FFT_DMAEN = 1 FFT_DEBUG = 0 5. Configure a coefficient DMA to read N complex twiddle factors from the coefficient buffer into the accelerator (total of 2N 32- bit words) and wait until the DMA is complete (or chain DMA in Step 4). This step is not needed if twiddles are already in the coefficient memory of the accelerator. 6. Configure a data DMA to read N complex data points from the input buffer into the accelerator (total of 2N 32-bit words). 7. Configure a data DMA to write N complex data points from the accelerator into the output buffer (total of 2N 32-bit words). There is no need to wait until the DMA in Step 6 completes. 8. Wait until the DMA in Step 7 completes (by interrupt or polling). The computed FFTs is now in the cores internal memory and the accelerator is in reading mode, waiting for next batch of FFTs.

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N >= 512, No Repeat For details on the storage format of the coefficients see Internal Memory Storage on page 7-8.
Configure the FFT Control Register

1. Configure the ACCSEL bits in the PMCTL1 register to select the FFT accelerator. 2. Factor N = VH, where 16 V and 16 H. 3. Set (=1) the FFT_RST bit in the FFTCTL1 register and wait for a minimum of 4 CCLK cycles. 4. Program the FFTCTL2 register with VDIM = V/16 LOG2VDIM = Log2(V) HDIM = H/16 LOG2HDIM = Log2(H) NOVER256 = VH/256 FFT_RPT = 0 5. Program the FFTCTL1 register with FFT_RST = 0 FFT_EN = 1 FFT_START = 1 FFT_DMAEN = 1 FFT_DEBUG = 0
Vertical FFT Configuration

6. Configure a coefficient DMA to read 2V twiddle factors from the vertical coeff buffer into the accelerator (total of 2V 32-bit words) and wait until the DMA is complete (or chain DMA in Step 7). This step is not needed if twiddles are already in the coefficient memory of the accelerator.

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7. Configure a data transmit DMA to load 2N 1 data points from the input buffer into the accelerator with a modify value of 2H, and a circular buffer length of 2N 1. Chain a data transmit DMA of count = 1 that loads the last imaginary point. / settings are applicable for The 512 points. The input is always expectednot be in alternate real N to
FFT_CPACKIN FFT_CPACKOUT

and imaginary format and the output is always generated in the same format. 8. Configure a data receive DMA to read 2N data points from the accelerator into the special buffer with a modify of 1. There is no need to wait until the DMA in Step 6 completes.
Special Buffer Configuration

9. Configure a DMA to load special coefficients from the special coefficients buffer into the accelerator, with a count = 512. 10.Once the DMA in Step 9 completes, configure a data DMA (chained or via interrupt) to read 256 data points (count = 256) from the special buffer into the accelerator with a modify value = 1. 11.Configure a data DMA to write 256 data points (count = 256) from the accelerator into the special buffer with modify value = 1. There is no need to wait until the DMA in Step 9 completes. 12.Repeat step 9 N/128 times (offset processing the entire 2N buffer of data).
Horizontal FFT Configuration

13.Once the last DMA in Step 10 completes, configure a coefficient DMA to read 2H twiddle factors from the horizontal coeff buffer into the accelerator.

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14.Once the DMA in Step 12 completes, configure a data DMA (chained or via interrupt) to read 2N 1 data points from special buffer into the accelerator with a modify value = 2V and a circular buffer length of 2N 1. Chain a data DMA of count = 1 that reads the last imaginary point. 15.Configure a data DMA to write 2N1 data points from the accelerator into the output buffer with a modify value = 2V and a circular buffer length of 2N 1. There is no need to wait until the DMA in Step 9 completes. Chain a data DMA of count = 1 that reads the last imaginary point. 16.Wait until the DMA in step 14 completes (by interrupt or polling). The computed FFT is now in the output buffer and the accelerator is in idle mode. N >= 512, Repeat For details on the storage format of the coefficients see Internal Memory Storage on page 7-8.

Transmit DMAs take place using input TCBs; receive DMAs take place using output TCBs.
1. Configure the ACCSEL bits in the PMCTL1 register to select the FFT accelerator. 2. Factor N = VH, where 16 V and 16 H. 3. Set (=1) the FFT_RST bit in the FFTCTL1 register and wait for a minimum of 4 CCLK cycles. 4. Program the FFTCTL2 register with: VDIM = V/16 LOG2VDIM = Log2(V) HDIM = H/16

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= Log2(H) NOVER256 = VH/256 FFT_RPT = 1.

LOG2HDIM

5. Program the FFTCTL1 register with: FFT_EN = 1 FFT_START = 1 FFT_DMAEN = 1 FFT_DEBUG = 0

FFT_RST

=0

For steps 615, see N >= 512, No Repeat above. Using Debug Mode The next sections show the steps required for reading and writing local memory in debug mode.
Write to Local Memory

1. Enable the FFT module using the PMCTL1 register. 2. Wait at least 4 CCLK cycles. 3. Clear the FFT_DMAEN bit in the FFTCTL1 register. 4. Set the FFT_DBG bit in the FFTCTL1 register. 5. Write first data to the FFTDDATA register. 6. Write address to the FFTDADDR register. Note the MSB Address bits determines which memory to write. 7. Wait at least 12 CCLK cycles before writing again FFTDDATA register.
Read from Local Memory

1. Enable FFT module using the PMCTL1 register. 2. Wait at least 4 CCLK cycles.

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3. Clear the FFT_DMAEN bit in the FFTCTL1 register. 4. Set the FFT_DBG bit in the FFTCTL1 register. 5. Write address to the FFTDADDR register. The MSB address bits determine which memory to read. 6. Wait at least 20 CCLK cycles before writing data to FFTDDATA register.

Debug Features
The following sections describe the debugging features available on the accelerator. Local Memory Access Setting the FFT_DBG bit in the FFTCTL1 register puts the accelerator into debug mode and allows all memory locations (coefficient and data memory) to be read and written indirectly, using FFTDADDR and FFTDDATA registers. The MSB bits of the FFTDADDR register determines if the access is for the data or the coefficient memory. Shadow Register A shadow DMA status register, FFTSHDMASTAT, can read the DMA status register without modifying the status values.

FIR Accelerator
Finite Impulse Response (FIR) filters are used in a wide array of applications, and can be used in multi-rate processing in conjunction with an interpolator or decimator.

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Features
This hardware module is capable of performing FIR filters without core intervention. This gives programs freedom to use the core to implement complex algorithms, effectively adding more bandwidth to the processor. FIR supports fixed point and IEEE floating point format Has four MAC units which operate in parallel Various rounding modes supported Single rate or multi-rate window processing Change the rates with decimation or interpolation mode Up to 32 filter channels available in TDM

Register Overview
The FIR accelerator registers are described below. Power Management Control Register (PMCTL1). Used for FIR accelerator selection. Controls the clock power down to the module if not required. Global Control Register (FIRCTL1). Configures the global parameters for the accelerator. These include number of channels, channel auto iterate, DMA enable, and accelerator enable. Channel Control Register (FIRCTL2).The FIRCTL2 register is used to configure the channel specific parameters such as filter TAP length, window size, sample rate conversion, up/down sampling and ratio. DMA Status Register (FIRDMASTAT). Provides the status of the FIR accelerator operation. This information includes chain pointer loading, coefficient DMA, data preload DMA, processing in progress, window processing complete, and all channels processing complete.

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MAC Status Register (FIRMACSTAT). Provides the status of MAC operation for all four multiply accumulators. In fixed-point mode, only the ARIx (adder result infinity) is used, all other bits are reserved. Debug Control Register (FIRDEBUGCTL). Controls the debug mode operation of the accelerator.

Clocking
The FIR accelerator runs at the maximum speed of the peripheral clock frequency (fPCLK).

Functional Description
Figure 7-3 shows the block diagram of the 1024-TAP FIR hardware accelerator. The accelerator consists of a 1024 word coefficient memory, a 1024 deep delay line for data, and four MAC units. The accelerator runs at the peripheral clock frequency (PCLK). The FIR accelerator has following logical sub blocks. 1. A data path unit that consists of: a. A 1024 deep coefficient memory b. A 1024 deep delay line for the data c. Four 32-bit floating-point and fixed-point multiplier and adder units d. One 32-bit prefetch buffer to operate in a pipelined fashion e. One 32-bit buffer to hold previous partial sum f. One 32-bit buffer to hold the output

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PERIPHERAL CORE BUS

IOD0 BUS

FIR CONTROL REGISTERS

FIR CONTROLLER

DMA CONTROLLER

OUTPUT REGISTER

PREFETCH BUFFER

C O E F F I C I E N T S

. . .
1024 x 32

COEFF ACCESS CONTROL

FIR COMPUTE UNIT (4 MACs)

DATA ACCESS CONTROL

. . .
1024 x 32

D E L A Y L I N E

PARTIAL SUM REGISTER

Figure 7-3. FIR Block Diagram 2. Configuration registers for the number of TAPs, number of channels, filter enable, interrupt control, DMA enable, up sample/down sample control, and ratios. 3. Core access interface for writing the DMA/filter configuration registers and reading the status register. 4. DMA bus interface for transferring data and/or coefficients to and from the accelerator. 5. DMA configuration registers including chain pointer, input, output, and coefficient registers.

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Compute Block The MAC unit, shown in Figure 7-4, has four multiply accumulators. They operate simultaneously on a single filter as described below. The MAC unit operates on the data and coefficient fetched from the data and coefficient RAMs. Each MAC can perform 32-bit floating-point or 32-bit fixed-point MAC operations. Floating-point format is IEEE compliant. Multiply and accumulation operation (addition) are pipelined. 32-bit floating-point MAC operation generates 32-bit multiply results. 32-bit fixed-point operation generates 80-bit results (64-bit result + 16 guard bits). Partial Sum Register The partial sum register is useful for floating-point multi-iteration mode. For a particular channel, the intermediate MAC result is written to the internal memorys output buffer. If the same channel is requested again, the partial result register is updated with the intermediate MAC result via DMA from the internal memorys output buffer and added to the current MAC result after each iteration. This process is repeated until all iterations are done (the entire soft filter length is processed). Delay Line Memory The accelerator has a 1024 TAP delay line to hold the data locally. The DMA controller fetches the data from internal memory and loads it into the delay line. Four read accesses can be made to the delay line simultaneously.

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DATA REGISTER

COEFFICIENT REGISTER

MULT

PARTIAL SUM REGISTER

MULT RESULT REGISTER

MUX

ADDER

MAC RESULT REGISTER

Figure 7-4. FIR MAC Unit Coefficient Memory The accelerator has a 1024 deep coefficient memory to store the coefficients. The DMA controller loads the coefficients from internal memory into coefficient memory. Four coefficients can be fetched from the coefficient memory simultaneously. If the soft filter length is more than 1024, processing is done in multi-iteration mode. Pre Fetch Data Buffer This buffer enables pipeline operation. 1 data sample is pre-fetch when the compute unit is operating on the delay-line corresponding to the current sample. The data pre-fetched in this buffer is later used to update the delay line for the next sample. This happens in parallel again, when the compute unit is not accessing the delay line in other words when it is adding the output from the four MACs and the partial sum register.

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Table 7-3. Pipeline Operation for Window Size = 1

Cycles Output DMA Compute Input DMA N N 1 2 3 N N1 4 N1 N2 5 N2 N3 6 N3

prefetch N1 prefetch N2 prefetch N3

Processing Output The accelerator uses all four MACs simultaneously to calculate one output sample as shown in Figure 7-5 and the following procedure. 1. The accelerator fetches four input data from the delay line and four corresponding coefficients from the coefficient memory and feeds them to the MAC units for multiply/accumulation. 2. The accelerator repeats the procedure with the next four input data and coefficients until all the TAPs complete. For an N TAP filter for example, this procedure is done N/4 times. 3. When all the TAPs complete, the accelerator adds the four MAC outputs together to the previous partial sum (if any) to calculate the final result. 4. Finally, that output sample is stored back in internal memory.

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Load chain pointer and control registers and enable accelerator

Load coefficients for the iteration

Pre fill delay line

Load next data

Perform all MACS and calculate result DMA partial sum from output buffer OR load 0 if first iteration

Add partial sum to the result

DMA Computed result to output

Is this the last data for this iteration?

NO

YES

Is this the last iteration?

NO

YES Raise channel complete interrupt END

Figure 7-5. Multi-Iteration Filtering Flow

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Internal Memory Storage The following sections describe the storage format for the accelerator.
Coefficients and Input Buffer Storage

For any N TAP filter with coefficients:

C[i] i = 0,1, N 1

the coefficients should be stored in internal memory buffer in the order:

C[N 1], C[N 2] C[1],C[0]

and the CI should point to C(N Single Rate Input Filtering

1)

The total size of the input buffer should at least be equal to N 1 + W. If the input buffer that needs to be processed is:
x[n],x[n+1],x[n+2] .... x[n+W-1]

it should be stored in the memory as

x[n-(N-1)], x[n-(N-2)] .... x[n-1], x[n], x[n+1] .... x[n+W-1]

and IIFIR should point to x[n

(N 1)]

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Decimation Assuming M = decimation ratio, the total size of the input buffer should at least be equal to N1+WxM. If the input buffer that needs to be processed is x[n],x[n+1],x[n+2]....x[n+WxM-1], it should be stored in the memory as
x[n-(N-1)], x[n-(N-2)]....x[n-1], x[n], x[n+1]....x[n+WxM-1]

and IIFIR should point to x[n-(N-1)]. Interpolation Assuming L= interpolation ratio, the total size of the input buffer should at least be equal to Ceil ((N1)/L)+W/L. If the input buffer that needs to be processed is
x[n], x[n+1], x[n+2]....x[n+W/L-1], and K= Ceil((N-1)/L)

it should be stored in the memory as:

x[n-k], x[n-(K-1)], x[n-(K-2)]....x[n-1], x[n], x[n+1].... x[n+W/L-1]

and the IIFIR should point to x[n-K].

Operating Modes
The FIR core performs a sum-of-products operation to compute the convolution sum. It supports single-rate, decimation, and interpolation functions. Single Rate Processing In a single-rate filter, the output result rate is equal to the input sample rate. The filter output Y(n) is computed according to following equation

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where N is the number of filter coefficients: c(i) i = 0,..., N 1 are the filter coefficients and x(n) represents the input time-series.
N1

Y(n) =

c(k) x(n k)
k=0

Single Iteration

Results are computed in single iteration when the soft filter length is less than or equal to 1024.
Multi Iteration

Results are computed in multiple iterations when the soft filter length is greater than 1024 (for example, 2048 TAPs on a 1024 hard filter length). In this mode, the controller implements two iterations of 1024 TAPs. Note that if the soft filter length is not a multiple of the hard filter length the controller iterates until the soft filter length is satisfied. Example: 550 taps on a 256 tap filter. In this example, the FIR controller implements two iterations of 256 taps and one iteration of 38 taps.

Multi-iteration mode is not supported in fixed-point format.

Window Processing Sample based processing mode is selected by configuring window size to 1. In this mode, one sample from a particular channel is processed through all the biquads of that channel and the final output sample is calculated. In window based mode, multiple output samples (up to 1024) equal to the window size of that channel are calculated. After these calculations are complete, the accelerator begins processing the next channel. A

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configurable window size parameter is provided to specify the length of the window. Multi Rate Processing Multi rate filters change the sampling rate of a signalthey convert the input samples of a signal to a different set of data that represents the same signal sampled at a different rate. Decimation A decimation filter provides a single output result for every M input samples, where M is the decimation ratio. Note that the output rate is 1/Mth of the input rate. The filter implementation exploits the low output sample rate by not starting a computation until a new set of M input samples is available. In this mode, after low pass filtering (for anti aliasing), FIR logic discards the ratio 1 samples of output data. For performance optimization, FIR logic skips the computation of output samples, which are discarded. The input buffer size for decimation filters is N 1 + (W M) where: N is the number of taps W is the window size M is the decimation ratio The window size (WINDOW bits) in the FIRCTL2 register must be programmed with the number of output samples. To start this mode, programs set the FIR_RATIO and FIR_UPSAMP bits in the FIRCTL2 register (along with normal filter setting). Also the TAPLEN bits setting should be greater than or equal to FIR_RATIO bits setting for decimation filter.

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Interpolation An interpolator filter provides L output results for each new input sample, where L is the interpolation ratio. Note that the output rate is L times the input rate. In this mode, according to the ratio specified in configuration register, FIR logic inserts L 1 zeros between any two input samples (up-sampling) and then performs the interpolation (through the FIR filter). Both up-sampling and down-sampling do not support multi iteration mode. Therefore, the filtering operation can only be done on up to 1024 TAPs and the ratio of up/down sampling can only be an integer value. In an interpolation filter FIR logic inserts L 1 zeros between each sample and the program has to make sure that these zeroes are fully shifted out of the delay line before moving on to the next channel. This puts a restriction on window size in terms of L the sample ratio as shown below. WINDOWSIZE = n SAMPLERATIO where n is the number of input samples. The input buffer size is smallest integer greater than or equal to (N 1 + W)/L for interpolation filters where: N is the number of taps W is the window size L is the interpolation ratio To start the mode, programs configure the FIR_RATIO and FIR_UPSAMP bits (along with filter settings) in the FIRCTL2 register.

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Channel Processing Figure 7-6 on page 7-42 shows the flow diagram for processing a single channel. Channels are processed in TDM format by setting the FIR_CH bits greater one. In the time slot corresponding to a particular channel, the corresponding TCB is loaded from internal memory. 1. The FIRCTL2 value is fetched from internal memory and is used to configure the filter parameters for that channel. 2. The accelerator fetches the coefficients using the CIFIR register as the pointer and loads them into coefficient memory. 3. The delay line is pre-filled using the IIFIR register as the pointer. 4. The accelerator calculates the first output and stores the result back into the output buffer using the OIFIR register as the pointer. 5. While calculating the output the accelerator fetches the next data in parallel. After one window of data is processed, the index registers in the internal memory TCB ares updated so that in the next time slot of the same channel, processing can be continued from where it stopped. 6. Processing moves to the next channel and repeats the procedure. If the soft filter length is more than the hard filter length, multiple iterations are done to process the window. Floating-Point Data Format The FIR accelerator treats data and coefficients in 32-bit floating-point format as the default functional mode.

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Load I, M, B, L registers for coefficient and data I/O

Load coefficients into coefficient memory

Preload delay line from internal memory

Compute result and store in internal memory Fetch next data

Window over?

NO

YES

NO

Last iteration?

YES

Update index register values of TCB in internal memory

To next channel processing

Figure 7-6. Single Channel Filtering Flow

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Fixed-Point Data Format In fixed-point mode, the 32-bit input data/coefficient is treated as fixed-point. A 32-bit fixed-point MAC operation generates an 80-bit result. Fixed-point data/coefficients can be unsigned integer, unsigned fractional and signed integer. entire result register always writ In fixed point mode, 3the 32 bits.80-bitfirst word is theis LSW, the ten back in bursts of The 2nd the MSW and the third word is a 16-bit overflow, the remaining 16-bits are padded with zeros. Therefore for fixed-point WINDOWSIZE = WINDOWSIZE 3. If signed fractional format is used, the output needs to be scaled by 2 since the MAC does not the right shift to remove the redundant sign bit. A final routine needs to decimate the output buffer to the desired samples. Multi iteration mode is not supported in this format. Therefore, the maximum TAP length is 1024.

Data Transfer
The FIR filter works exclusively through DMA. DMA Access The FIR accelerator has two DMA channels (accelerator input and output) to connect to the internal memory. The DMA controller fetches the data and coefficients from memory and stores the result.
Chain Pointer DMA

The DMA controller supports circular buffer chain pointer DMA. One transfer control block (TCB) needs to be configured for each channel. The TCB contains:

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A control register value to configure the filter parameters (such as filter tap length, window size, sample rate conversion settings) for each channel DMA parameter register values for the input data (delay line) DMA parameter register values for coefficient load DMA parameter register values for output data Intermediate results in multi-iteration mode are saved in the output buffer As shown in FIR Accelerator TCB on page 3-17 and Figure 7-7, the accelerator loads the TCB into its internal registers and uses these values to fetch coefficients and data and to store results. After processing a window of data for any channel, the accelerator writes back the appropriate values to the IIFIR and OIFIR fields of the TCB in memory, so that data processing can begin from where it left off during the next time slot of that channel. The write back value for input buffer is: IIFIR + W for single rate filtering. IIFIR + W M for decimation (M = decimation ratio). IIFIR + W/L for interpolation (L = interpolation ratio). The write back values for output buffer in floating point mode is: OIFIR + W. The write back values for output buffer in fixed point mode is: OIFIR + 3 W. register is part of the This allows program The individual FIR channels withFIR TCB.control attributes. ming different
FIRCTL2

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20 19

. . . 5 Buffer Length Register 4 3 2 1 Base Register Index Register

Figure 7-7. Circular Buffer Addressing

Interrupts
Table 7-4 provides an overview of FIR interrupts. Table 7-4. FIR Interrupt Overview
Default Programmable Interrupt Sources Masking N/A Service ROC from FIRDMASTAT + RTI instruction

ACC0I/ACC1I not con- Input DMA complete nected by default Output DMA complete Window complete All channels complete MAC IEEE floating-point exceptions MAC fixed-point Overflow

ROC from FIRMACSTAT + RTI instruction

Sources The FIR module drives two interrupt signals, ACC0I for the DMA status and ACC1I for the MAC status. The FIR module generates interrupts as described in the following sections.

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Window Complete

This interrupt is generated at the end of each channel when all the output samples are calculated corresponding to a window and updated index values are written back.
All Channels Complete

This interrupt is generated when all the channels are complete or when one iteration of time slots completes. Note that the interrupt follows the access completion rule, where the interrupt is generated when all data are written back to internal memory.
Chained DMA

For chained DMA, if the PCI bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the PCI bit is set (= 1), then a DMA interrupt is generated for each TCB.
MAC Status

A MAC status interrupt is generated under these conditions Multiplier result zero Set if Multiplier result is zero Multiplier Result Infinity Set if Multiplier result is Infinity Multiply Invalid Set if Multiply operation is Invalid Adder result zero Set if Adder result is zero Adder result infinity Set if Adder result is infinity Adder invalid Set if Addition is invalid Adder overflow for fixed-point operation

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Masking The ACC0I and ACC1I signals are not routed by default to programmable interrupts. To service the ACCxI, unmask (set = 1) any programmable interrupt bit in the IMASK/LIRPTL register Service When a DMA interrupt occurs, programs can find whether the input or output DMA interrupt occurred by reading the DMA status register (FIRDMASTAT). The DMA interrupt status bits are sticky and are cleared when the DMA status register is read. When a MAC status interrupt occurs, programs can find this by reading the MAC status register (FIRMACSTAT). The MAC interrupt status bits are sticky and are cleared by a read. The status interrupt sources are derived from the FIRMACSTAT register. If the status interrupt occurs as a result of the last set of MAC operations of a processing iteration corresponding to a particular channel, the interrupt is generated continuously and cannot be stopped, even after disabling the accelerator. The interrupt can only be stopped by another processing iteration that results in a non-zero or valid multiply/add result. However, in this situation it is difficult to isolate whether the interrupt corresponds to the previous processing iteration or that of the current one. This makes the use of status interrupts impractical. An alternate way is to poll status bits of the FIRMACSTAT register inside the DMA interrupt service routine. However, the behavior of the status bits, as described below, should be kept in mind. The status bits in the FIRMACSTAT registers are sticky. Once a status bit is set, it gets cleared only when the FIRMACSTAT register is read and the previous set of MAC operations resulted in a non-zero/valid output. Therefore, if the last set of MAC operations of a particular processing iteration results in a zero/non-valid output, the corresponding status bit wont be cleared, even after reading the FIRMACSTAT register. To avoid a false indication in the next processing

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iteration, it is necessary to ensure that all the status bits are cleared after the current iteration finishes. The solution is to read the FIRMACSTAT register twice inside the DMA interrupt service routine. The first read is used to identify which status bits are set. The second read is used to discover if the status bit was set because of the last set of MAC operations. If the status bit was not set because of the last set of MAC operations, it provides a zero result. Otherwise, the bit was set because of the last set of MAC operations. In that case, the status bit must be cleared by performing a simple dummy FIR processing iteration (tap length = 4 and window size = 1) by choosing the appropriate coefficients and input buffer and reading the FIRMACSTAT register after the processing is complete. For more information, see FIR MAC Status Register (FIRMACSTAT) on page A-83.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific). Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. FIR Accelerator Effect Latency After the FIR registers are configured the effect latency is 1.5 PCLK cycles minimum and 2 PCLK cycles maximum. Writes to the PMCTL1 register have an effect latency of two PCLK cycles. Wait for at least four CCLK cycles after selecting an accelerator before accessing any of its registers.

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FIR Throughput
Accelerator input and output channels are used to connect to internal memory. Data throughput is one 32-bit data word per peripheral clock cycle for writes to memory, provided there are no conflicts. Read throughput from memory, throughput is one 32-bit data word per two peripheral clock cycles. The following information describes the performance of the FIR accelerator in processor cycles. Total number of PCLK cycles for single rate filtering N<=1024 is: (TCB load + 4 N +W(N/4 + 2)) C and the total number of PCLK cycles for decimation is: (TCB load + 4 N + W(N/4 + 2) + (W 1) (M 1) 7) C where: N Number of taps W Window size C Number of channels TCB load = 49 PCLK cycles 4 N Number of cycles for loading coefficients an data considering two cycles for read N/4 + 2 FIR compute cycles considering four pipelined MACs M Decimation ratio

Programming Model
The following steps should be used when programming the accelerator. Enable the FIR accelerator by setting accelerator select bits ( ACCSEL in the PMCTL1 register) to 00. ADSP-214xx SHARC Processor Hardware Reference 7-49

FIR Accelerator

Single Channel Processing 1. Create input, coefficient, and output buffers in internal memory. For input and coefficient buffer storage format see Coefficients and Input Buffer Storage on page 7-36. 2. Create the TCBs in internal memory. Each TCB corresponds to a particular channel. TCBs hold the FIRCTL2 register which allows programming the window size and tap size along with up or down sample enable, sample rate conversion enable, and the conversion ratio for decimation and interpolation filters. 3. Configure the index, modifier, length entries in the TCBs to point to the corresponding channels data buffer, coefficient buffer, and output data buffer. The output index register should always point to the start of the output buffer. However, the input index registers value should be initialized based on the explanation provided in Coefficients and Input Buffer Storage on page 7-36. 4. The core configures the FIRCTL1 register with the number of channels (one channel), fixed- or floating-point format. 5. Set the enable bit to start accelerator operation in the modes configured (in FIRCTL1 and FIRCTL2 registers) by loading the first channels TCB. Once the first channel window is calculated, the input and output index registers are written back to internal memory corresponding to the first channel. Once the write back is complete the accelerator moves into idle.

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Multichannel Processing Figure 7-8 on page 7-52 shows the diagram for multichannel filtering. Multiple channels are processed in a time division multiplexed (TDM) format. After completing all the channels, the accelerator can either repeat the slots or wait for core intervention. For multichannel filtering, use the following steps. 1. Program the number of channels in the FIRCTL1 register using the FIR_NCH bits (51). 2. Configure the TCBs in internal memory with one channels TCB pointing to the next channels TCB. 3. Write the first TCB value into the CPFIR register and enable the accelerator. The accelerator fetches the first channels TCB and, using it as pointer, pre-fills the delay line and coefficient memory and loads the FIRCTL2 register to configure the filter parameters corresponding to that channel. The accelerator then calculates output samples corresponding to one Window and stores the data back in internal memory. At the end of the Window the accelerator updates the IIFIR and OIFIR registers in the TCB of internal memory and moves to the next channel. When all the channels are finished and the auto channel iterate (CAI, bit 9) is set, the accelerator processes the first channel again and iterates through the channels. If the CAI bit is cleared, the accelerator waits for core intervention.

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Core sets up control register and initiates RUN command

Load TCB for current channel

Process one window of current channel

All channels done?

NO

YES

YES

Auto channel iterate?

NO Wait for core intervention

Figure 7-8. Wait for Core Intervention => Idle (if CAI bit = 0) Dynamic Coefficient Processing Notes 1. The dynamic update of the coefficients may be useful for the FIR accelerator. The reason is that the FIR accelerator re-loads the coefficients for each iteration (if the CAI bit is set) before the start of processing of each channel. 2. The dynamic coefficient update should be possible for single iteration mode (tap length <=1024) by making sure that the new coefficients are updated after the accelerator loads the coefficients for current processing and before the next processing starts. The

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expression for the maximum time available for the coefficient memory update should be equal to 2 N + W(ceil(N/4) + 2) PCLK cycles. 3. For multi-iteration mode dynamic updates are not supported. Programs must finish current processing, disable the accelerator, update the coefficients, and re-enable the accelerator. Debug Mode The next sections show the steps required for reading and writing local memory in debug mode.
Write to Local Memory

1. Enable the FIR module using the PMCTL1 register. 2. Wait at least 4 CCLK cycles. 3. Clear the FIR_DMAEN bit in the FIRCTL1 register. 4. Set FIR_DBGMODE, FIR_DBGMEM and FIR_HLD bits in FIRDEBUGCTL register. 5. Set the FIR_ADRINC bit in FIRDEBUGCTL register for address auto increment. 6. Write start address to the FIRDBGADDR register. Note if bit 11 is set, coefficient memory is selected. 7. Wait at least 4 CCLK cycles. 8. Write data to the FIRDBGWRDATA register.
Read from Local Memory

1. Enable FIR module using the PMCTL1 register. 2. Wait at least 4 CCLK cycles.

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3. Clear the FIR_DMAEN bit in the FIRCTL1 register. 4. Set FIR_DBGMODE, FIR_DBGMEM and FIR_HLD bits in FIRDEBUGCTL register. 5. Set the FIR_ADRINC bit in FIRDEBUGCTL register for address auto increment. 6. Write start address to the FIRDBGADDR register. Note if bit 11 is set, coefficient memory is selected. 7. Wait at least 4 CCLK cycles. 8. Read data from the FIRDBGRDDATA register. Single Step Mode Single step mode can be used for debug purposes. An additional debug register is used in this mode. 1. Enable stop DMA during breakpoint hit in the emulator settings. 2. Clear the FIR_HLD bit and enable FIR_DBGMODE and FIR_RUN bits in FIRDEBUGCTL register. 3. Program FIR module according to the application. 4. In single step each iteration is updated in the emulator session. FIR Programming Example An application needs FIR filtering of six channels of data. The first four channels require 256 TAP filtering and the last two channels require 1024 TAP filtering. The window size for all the channels is 128. 1. Create a circular data buffer in internal memory for each channel.

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The buffer should be large enough to avoid overwriting data before being processed by the accelerator. Ideally, the input buffer size for a channel is tap length + window size 1 for that channel. The 256 coefficients of each of the first four channels and the 1024 coefficients each of the last two channels are also configured in internal memory buffers. The output buffer size is equal to the window size. 2. Create six TCBs in internal memory with each channels chain pointer (CP) entry pointing to the next channels and the sixth channels CP entry pointing back to the firsts in a circular fashion. 3. Configure the FIRCTL2 register for the first four channels TCBs to 256 TAPs and a window size of 128, and the next two channels for 1024 TAPs and a window size of 128, respectively. 4. Configure the index, modifier, length entries in the TCBs to point to the corresponding channels data buffer, coefficient buffer, and output data buffer. The location of the first channels TCB is written to the CPFIR register. The FIRCTL1 register is then programmed with an FIR_CH value that corresponds to six channels. a. The accelerator iterates through six channels once and then waits for core intervention, (the FIR_CAI bit is not set, the DMA is enabled, and the FIR_EN bit is set). b. The accelerator then loads the first channels TCB then loads the coefficient and data and processes one window. c. After saving the index values to memory the accelerator moves to the next channel. d. After all six channels are complete the accelerator halts and waits for core intervention.

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Computing FIR Output, Tap Length > Than 4096 With little core intervention, the FIR accelerator can as well be used to calculate output for tap length greater than 4096 taps. The section shows how it can be done with an example of 8192 taps. Transfer function of an 8192 FIR filter can be divided into two 4096 FIR filters as shown below. H(Z) = b0 + b1Z1 + b2Z2 + ...........b4095Z4095 + b4096Z4096b4097 Z4097 +........b8191Z8191 = b0 + b1Z1 + b2Z2+ ...........b4095Z4095 + Z4096(b4096 + b4097+ ........b8191Z4096) Filter coefficients of an 8192 tap filter therefore need to be divided among two 4096 tap FIR filters Filter 1 Coefficients = b0, b1, b2,, b4095 Input data = x[n], x [n-1],.x[n-4095] Filter 2 Coefficients=b4096, b4097,..,b8191 Input data = x[n-4096], x[n-4097],x[n-8191] The accelerator can be used in two channel mode where channel 1 operates on x[n]x[n-4095] input data with the filter coefficients of filter 1 and channel 2 operates on x[n-4096]x[n-8191] with the filter coefficients of filter 2. Once both the channels are processed, the partial sum output of both the channels can to be added together to get the final output. The following

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programming steps are needed to implement this approach (tap length = TAPS = 8192, window size = WINDOW). 1. Create a circular input data buffer in internal memory (IBUF). The buffer should be large enough to avoid overwriting data before being processed by the accelerator. Ideally, the input buffer size for a channel is TAPS + WINDOW1. 2. Create a coefficient buffer of size TAPS (8192) (CBUF). 3. Create one output buffer of size WINDOW (OBUF) and another temporary output buffer (OBUF1) to store the partial sum. 4. Create two TCBs in internal memory with first TCB chained to the second and second one chained to the first in circular manner. a. The CIFIR field of the first TCB should point to the start address of the coefficient buffer (CBUF) and that of the second TCB should point to 4096 offset from the start of the coefficient buffer (CBUF + 4096). b. The OBFIR and OIFIR field of the first TCB should point to the start address of OBUF and that of the second TCB should point to the start address of OBUF1. c. The IIFIR field of the first TCB should point to the start address of IBUF and that of the second TCB should point to 4096 offset from the start address of IBUF. d. The FIRCTL2 field of both the TCB should be configured for tap length = TAP/2 = 4096 and window size = WINDOW. 5. Initialize the CPFIR register pointing to the first TCB.

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6. Program the FIRCTL1 register to initiate the accelerator processing now by setting the FIR_EN, FIR_DMAEN bits and no of channels configured as 2 7. Wait for the FIR all channel done interrupt to occur and inside the ISR, add the partial sum results using core from both the output buffers (OBUF and OBUF1) to get the final output. To save memory, the contents of the buffer OBUF can as well be replaced by the final output result.

Debug Features
The following sections provide information of debugging the FIR accelerator. Local Memory Access The contents of FIR delay line and coefficient memories are made observable for debug by setting the FIR_DBGMODE/FIR_DBGMEM and FIR_HLD bits in the FIRDEBUGCTL control register. The debug address register (FIR_DBGADDR) and two data registers are provided for debug operations. Bit 11 of the DBGADDR register selects coefficient memory if set (=1) and selects delay line memory in cleared (=0). In the debug mode, the read data register (DBGMEMRDDAT) returns the contents of the memory location pointed to by the address register. Data can be written into any memory location using DBGMEMWRDAT register writes. If the address auto increment bit (FIR_ADRINC) is set, the address register auto increments on DBGMEMWRDAT writes and DBGMEMRDDAT reads. During auto increment, the FIR_DBGADDR register cannot cross the data memory/ coefficient memory boundary.

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Single Step Mode Programs can single step through the MAC operations and observe the memory contents after each step. The FIR_DBGMODE/FIR_HLD and FIR_RUN bits control the FIR MAC units. Emulation Considerations In FIR debug mode, the DMA operations are not observable.

IIR Accelerator
The ADSP-214xx processors have an IIR filter accelerator implemented in hardware, that reduces the processing load on the core, freeing it up for other tasks.

Features
The accelerator supports a maximum of 24 channels. There is support for up to 12 cascaded bi-quads per channel. This means that the accelerator locally stores all the biquad coefficients of 24 channels. Window size can be configured from 1 (sample based) to 1024. IIR supports IEEE floating point format 32/40-bit Various rounding modes supported Sample based or window based processing Up to 12 cascaded biquads per channel Up to 24 filter channels available in TDM Allows Biquad save state storage

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Register Overview
The following sections provide information on the IIR accelerator control and status registers. Power Management Control Register (PMCTL1). Used for IIR accelerator selection. Controls the clock power down to the module if not required. Global Control (IIRCTL1). Configures the global parameters for the accelerator. These include number of channels, channel auto iterate, DMA enable, and accelerator enable. Channel Control (IIRCTL2). The IIRCTL2 register is used to configure the channel specific parameters. These include number of biquads and window size. DMA Status (IIRDMASTAT). Provides the status of accelerator operation including chain pointer loading, coefficient DMA, processing progress, window complete and all channels complete. MAC Status (IIRMACSTAT). Provides the status of the MAC operations. Debug Mode Control (IIRDEBUGCTL). Controls the debug mode operation of the accelerator.

Clocking
The IIR accelerator runs at the maximum speed of the peripheral clock (fPCLK).

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Functional Description
Figure 7-9 shows the block diagram of the IIR hardware accelerator. The accelerator has a coefficient memory size of 1440 40 bits (12 biquads 12 channels 5 coeffs), a data memory size of 576 40 bits (12 biquads 12 channels 2 states) and one MAC unit with an input data buffer to supply data to the MAC.
PERIPHERAL CORE BUS IOD0 BUS

IIR CONTROL REGISTERS

IIR CONTROLLER

DMA CONTROLLER

BIQUAD BIQUAD C O E F F I C I E N T S CHANNEL 0 BIQUAD 0 Ak, Bk CHANNEL 0 BIQUAD M Ak, Bk . . . CHANNEL 0 BIQUAD 11 Ak, Bk

RESULT REGISTER

BIQUAD BIQUAD

I N P CHANNEL 0 U BIQUAD 0 T Xk, Dk D CHANNEL 0 A BIQUAD M T A Xk, Dk . . . &

COEFF ACCESS CONTROL

BIQUAD COMPUTE UNIT (1 MAC)

DATA AND STATE ACCESS CONTROL

S T A CHANNEL 0 BIQUAD 11 T E Xk, Dk

Figure 7-9. IIR Accelerator Block Diagram The IIR accelerator is implemented using Transposed Direct Form II biquad which has less coefficient sensitivity. Figure 7-10 shows the signal flow graph for the biquad structure.

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ak0 xk

+
dk2
-1 Z

yk

ak1

bk1

+
dk1
-1 Z

ak2

bk2

Figure 7-10. Transposed Direct Form II Biquad The accelerator has the following logical sub blocks. A data path unit with the following elements: 32/40-bit coefficient memory (Ak, Bk) for storing biquad coefficients 32/40-bit input data (Xk) and state (Dk) One 40/32-bit floating-point multiplier and adder (MAC) unit An input data buffer to efficiently supply data to MAC One 40-bit result register to hold result of biquad Configuration registers for controlling various parameters such as the number of biquads, the number of channels, interrupt control, and DMA control A core access interface for writing the DMA/filter configuration registers and for reading the status registers

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A DMA bus interface for transferring data to and from the accelerator. This interface is also used to preload the coefficients (Ak, Bk) and state (Dk) at start up. DMA configuration registers for the transfer of input data, output data and coefficients Multiply and Accumulate (MAC) Unit The MAC unit shown in Figure 7-11 has a pipelined multiplier and accumulator unit that operates on the data and coefficient fetched from the data and coefficient memory. The MAC can perform either 32-bit floating-point or 40-bit floating-point MAC operations. 32-bit floating-point operations generate 32-bit results and 40-bit floating-point operations generate 40-bit results.
DATA REGISTER COEFFICIENT REGISTER

dk1 REGISTER MULT

dk2 REGISTER

MULT RESULT REGISTER

MUX

ADDER

MAC RESULT REGISTER

Figure 7-11. IIR MAC Unit

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Input Data and Biquad State The size of data memory is 576 40 bits and is used to hold the dk1 and dk2 state of all the biquads locally. The DMA controller fetches the sample data from internal memory and calculates the output as well as the dk1 and dk2 values for each biquad and stores them in local data memory. Coefficient Memory The size of coefficient memory is 1440 40 bits and is used to store all the coefficients of all the biquads. At start-up, DMA loads the coefficients from internal memory into local coefficient memory. Internal Memory Storage This section describes the required storage model for the IIR accelerator.
Coefficient Memory Storage

Coefficients and Dk values for a particular biquad BQD[k] should be stored in internal memory in the order Ak0, Ak1, Bk1, Ak2, Bk2, Dk2, Dk1. convention the filter here is dif The namingthe one used for MATLAB.coefficients used conversion ferent from in The following should be used when using MATLAB generated coefficients: (Akx = bx and Bkx = ax). In other words, the coefficients for each biquad should be stored in the order:
b0, b1, a1, b2, a2, dk2, dk1

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For N biquad stages, the order of coefficients should be as follows:

b01, b11, a11, b21, a21, dk21, dk11, b02, b12, a12, b22, a22, dk22, dk12 ,...... b0N, b1N, a1N, b2N, a2N, dk2N, dk1N.

where bxN and axN are the coefficients ([b, a]) for the Nth biquad stage.

Operating Modes
The accelerator can be operated in the following modes. Window Processing Sample based processing mode is selected by configuring window size to 1. In this mode, one sample from a particular channel is processed through all the biquads of that channel and the final output sample is calculated. In window based mode, multiple output samples (up to 1024) equal to the window size of that channel are calculated. After these calculations are complete, the accelerator begins processing the next channel. A configurable window size parameter is provided to specify the length of the window. 40-Bit Floating-Point Mode In 40-bit floating-point mode, the input data/coefficient is treated as a 40-bit floating-point number. 40-bit floating-point MAC operations generate 40-bit results. This mode can be selected by setting bit 12 of the IIRCTL1 register. Since the DMA bus width is 32 bits, in 40-bit mode the IIR accelerator performs two packed 32-bit accesses to the memory to fetch one 40-bit input or coefficient data, or to store one 40-bit output word. The first

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32-bit word provides the lower 32 bits and the 8 LSBs of the second 32-bit word provides rest of the upper 8 bits of the a complete 40-bit word. Figure 7-12 shows the 32-40 bit packing used by accelerator. to pack the input Overheads might be required accelerator and for40-bit data into the format acceptable by the IIR unpacking the output of accelerator to the format acceptable by the rest of the application.
X DATA1 [390] X+1 X+2 DATA2 [390] X+3 3 COLUMN INTERNAL MEMORY (40-BIT) DATA2 [3931] IOD0 DMA BUS (32-BIT) IIR ACCELERA TOR (40-BIT) MEMORY DATA1 [3931] DATA2 [310] DATA2 [390] DATA1 [310] DATA1 [390]

Figure 7-12. 32-Bit To 40-Bit Packing Save Biquad State Mode The IIR_SS bit (IIRCTL1 register) completely stores the current biquad states in local memory (writes all the DK1 and DK2 states back into the internal memory states). This is useful in applications that require fast switching to another high priority accelerator taska required IIR to FIR processing transition for example. After resuming these states can be reloaded and IIR processing can be continued. Note that the DMA status is automatically stored after each iteration.

Data Transfers
The IIR filter works exclusively through DMA.

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DMA Access The IIR accelerator has two DMA channels (accelerator input and output) to connect to the internal memory. The DMA controller fetches the data and coefficients from memory and stores the result.
Chain Pointer DMA

The DMA controller supports circular buffer chain pointer DMA. One transfer control block (TCB) needs to be configured for each channel. The TCB contains: A control register value to configure the filter parameters (such as number of biquads, window size) for each channel DMA parameter register values for the input data DMA parameter register values for coefficient load DMA parameter register values for output data ( the last should The chain pointerchannels) field ofThis is sochannels TCBIIR accelpoint to the first TCB. that when the
CPIIR

erator is enabled, 1) it first loads the coefficients (Ak, Bk) and state variables (Dk) for all the channels in to it's local coefficient memory and 2) it loops back to first channel again to start fetching the input data for processing. As shown in IIR Accelerator TCB on page 3-18 and Figure 7-13, the accelerator loads the TCB into its internal registers and uses these values to fetch coefficients and data and to store results. After processing a window of data for any channel, the accelerator writes back the IIRII (input index register) and IIROI (output index register) values to the TCB in memory, so that data processing can begin from where it left off during the next time slot of that channel. For 32-bit mode, the write back values for the index registers is equal to IIRII + W and IIROI + W.

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For 40-bit mode, the write back values are: IIRII + 2 W and IIR0I + 2 W. Accelerator input and output channels connect to internal memory. register is part the IIR TCB. The individual IIR channelsofhaving differentThis allows to program control attributes.
IIRCTL2
20 19

. . . 5 Buffer Length Register 4 3 2 1 Base Register Index Register

Figure 7-13. Circular Buffer Addressing

Interrupts
Table 7-5 provides an overview of IIR interrupts. Table 7-5. IIR Interrupt Overview
Default Programmable Interrupt ACC0I/ACC1I not connected by default Sources Input DMA complete Output DMA complete MAC IEEE floating point exceptions Masking N/A Service ROC from IIRDMASTAT + RTI instruction ROC from IIRMACSTAT + RTI instruction

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Sources The IIR module drives two interrupt signals, ACC0I for the DMA status and ACC1I for the MAC status. The IIR module generates interrupts as described in the following sections.
Window Complete

This interrupt is generated at the end of each channel when all the output samples are calculated corresponding to a window and updated index values are written back.
All Channels Complete

This interrupt is generated when all the channels are complete or when one iteration of time slots completes. The interrupt follows the access completion rule, where the interrupt is generated when all data are written back to internal memory.
Chained DMA

For chained DMA, if the PCI bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the PCI bit is set (= 1), then a DMA interrupt is generated for each TCB.
MAC Status

A MAC status interrupt is generated under these conditions Multiplier result zero Set if Multiplier result is zero Multiplier Result Infinity Set if Multiplier result is Infinity Multiply Invalid Set if Multiply operation is Invalid Adder result zero Set if Adder result is zero

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Adder result infinity Set if Adder result is infinity Adder invalid Set if Addition is invalid Masking The ACC0I and ACC1I signals are not routed by default to programmable interrupts. To service the ACCxI, unmask (set = 1) any programmable interrupt bit in the IMASK/LIRPTL register Service When a DMA interrupt occurs, programs can find whether the input or output DMA interrupt occurred by reading the DMA status register (IIRDMASTAT). The DMA interrupt status bits are sticky and are cleared when the DMA status register is read. When a MAC status interrupt occurs, programs can find this by reading the MAC status register (IIRMACSTAT). The MAC interrupt status bits are sticky and are cleared by a read. The status interrupt sources are derived from the IIRMACSTAT register. If the status interrupt occurs as a result of the last set of MAC operations of a processing iteration corresponding to a particular channel, the interrupt is generated continuously and cannot be stopped, even after disabling the accelerator. The interrupt can only be stopped by another processing iteration that results in a non-zero or valid multiply/add result. However, in this situation it is difficult to isolate whether the interrupt corresponds to the previous processing iteration or that of the current one. This makes the use of status interrupts impractical. An alternate way is to poll status bits of the IIRMACSTAT register inside the DMA interrupt service routine. However, the behavior of the status bits, as described below, should be kept in mind. The status bits in the IIRMACSTAT registers are sticky. Once a status bit is set, it gets cleared only when the IIRMACSTAT register is read and the previous set of MAC operations resulted in a non-zero/valid output. Therefore, if the last set of MAC

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operations of a particular processing iteration results in a zero/non-valid output, the corresponding status bit wont be cleared, even after reading the IIRMACSTAT register. To avoid a false indication in the next processing iteration, it is necessary to ensure that all the status bits are cleared after the current iteration finishes. The solution is to read the IIRMACSTAT register twice inside the DMA interrupt service routine. The first read is used to identify which status bits are set. The second read is used to discover if the status bit was set because of the last set of MAC operations. If the status bit was not set because of the last set of MAC operations, it provides a zero result. Otherwise, the bit was set because of the last set of MAC operations. In that case, the status bit must be cleared by performing a simple dummy IIR processing iteration (biquads = 1 and window size = 1) by choosing the appropriate coefficients and input buffer and reading the IIRMACSTAT register after the processing is complete. For more information, see IIR MAC Status Register (IIRMACSTAT) on page A-90.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific). Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. IIR Accelerator Effect Latency After the IIR registers are configured the effect latency is 1.5 PCLK cycles minimum and 2 PCLK cycles maximum. Writes to the PMCTL1 register have an effect latency of two PCLK cycles. Wait for at least four CCLK cycles after selecting another accelerator before accessing any of its registers.

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IIR Throughput
Data throughput is one 32-bit data word per peripheral clock cycle for writes to memory, provided there are no conflicts. Read throughput from memory, throughput is one 32-bit data word per two peripheral clock cycles. IIR throughput is calculated as follows: Total number of peripheral clock cycles = (TCB load + 5 B W) C where: B = number of bi-quads W = Window size C = number of channels TCB load = 36 PCLK cycles 5 B Number of cycles to calculate B biquads (Note: This does not include the coefficient loading cycles as coefficients need to be loaded only once.)

Programming Model
The IIR supports up to 24 channels which are time division multiplexed (TDM). Each channel can have a maximum of 12 cascaded biquads. The window size for each channel is configurable using control registers. A window size of 1 corresponds to sample based operation and the maximum window size is 64. The coefficients are initially stored in internal memory and one TCB per channel is created in internal memory with each channels TCB pointing

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to the next channels. The TCB also contains channel specific control registers, input data buffer parameters and output data buffer parameters.

The TCB of the last channel should point to the TCB of first channel.
The total number of channels is configured using the IIRCTL1 register and DMA is enabled. The procedure that the accelerator uses to process biquads is shown in Figure 7-14 and described in the following procedure.
Core sets up control register and initiates run

Preload all the coefficients and initialize intermediate results

Load TCB for current channel

Process one window of current channel

Move to next channel

All channels done?

NO

YES

Wait for core intervention

Figure 7-14. Biquad Processing Program Flow

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1. The controller loads all coefficients of all the channels into local storage. 2. Once all the coefficients are loaded, the controller goes to the first biquad of the first channel and calculates the output of the first biquad and updates the intermediate results for that biquad. 3. Then, the accelerator moves to the next biquad of that channel and repeats the process until all the biquads for that channel are completed and the results are stored to memory. 4. This process is repeated with next sample until one window of the corresponding channel is processed. 5. After one window of the channel accelerator is processed, the accelerator moves to the next channel and computes the results. Dynamic Coefficient Processing Notes The IIR accelerator loads the coefficients for all the channels only once when the IIR accelerator is enabled. In order to re-load the new coefficients, the accelerator has to be disabled and re-enabled. Writing to Local Memory 1. Enable IIR module in PMCTL1 register. 2. Wait at least 4 CCLK cycles. 3. Clear the IIR_DMAEN bit in the IIRCTL1 register. 4. Set the IIR_DBGMODE, IIR_DBGMEM and IIR_HLD bits in the IIRDEBUGCTL register. 5. Set the IIR_ADRINC bit in IIRDEBUGCTL register for address auto increment.

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FFT/FIR/IIR Hardware Modules

6. Write start address to the IIRDBGADDR register. If bit 11 is set, coefficient memory is selected. 7. Wait at least 4 CCLK cycles. 8. Write data to the IIRDBGWRDATA_L register. 9. Write data to the IIRDBGWRDATA_H register. Reading from Local Memory 1. Enable IIR module in PMCTL1 register. 2. Wait at least 4 CCLK cycles. 3. Clear the IIR_DMAEN bit in the IIRCTL1 register. 4. Set the IIR_DBGMODE, IIR_DBGMEM and IIR_HLD bits in the IIRDEBUGCTL register. 5. Set the IIR_ADRINC bit in the IIRDEBUGCTL register for address auto increment. 6. Write start address to the IIRDBGADDR register. If bit 11 is set, coefficient memory is selected. 7. Wait at least 4 CCLK cycles. 8. Read data from the IIRDBGRDDATA_L register. 9. Read data from the IIRDBGRDDATA_H register.

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IIR Accelerator

Single Step Mode Single step mode can be used for debug purposes. An additional debug register is used in this mode. 1. Enable stop DMA during breakpoint hit in the emulator settings. 2. Clear the IIR_HLD bit and enable IIR_DBGMODE and IIR_RUN bits in IIRDEBUGCTL register. 3. Program FIR module according to the application. 4. In single step each iteration is updated in the emulator session. Save Biquad State of the IIR The following steps are required to resume IIR processing after being interrupted by another accelerator module. 1. When starting the accelerator for the first time, set the IIR_EN, IIR_DMAEN and IIR_SS bits. 2. The core waits for the first set of IIR processing to conclude or performs some other task. 3. The accelerator writes back the updated DMA index registers and the updated Dk values after the processing completes. 4. Disable the accelerator by clearing the IIR_EN bit. Optionally, clear the IIR_DMAEN bit. 5. The core and accelerator wait for the next set of data to be ready. (The FIR/FFT accelerator can be used for a completely different purpose during this time.)

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FFT/FIR/IIR Hardware Modules

6. Once the next block is ready for processing, enable the IIR accelerator again by setting the IIR_EN and IIR_DMAEN bits. The coefficients and the Dk values will be re-loaded back into the local memory. 7. The core waits for the current set of IIR processing to conclude or performs some other task. Programming Example In this example, an application needs IIR filtering for two channels of data; channel 1 has six biquads and channel 2 has eight biquads. The window size for all channels is 32. 1. Create a circular buffer in internal memory for each channels data. The buffer should be large enough to avoid overwriting data before it is processed by the accelerator. 2. Configure internal memory buffers containing the 6 5 coefficients and the 6 2 Dk values for the channel 1 biquads, and the 8 5 coefficients and 8 2 Dk values of the channel 2 biquads. 3. Configure two TCBs in internal memory with each channels chain pointer entry pointing to the next channels and the last channels chain pointer entry pointing to the first in a circular fashion. 4. Program the IIRCTL2 register to use channel 1 TCB for 6 biquads and a window size of 32, and channel 2 for 8 biquads and a window size of 32. 5. Configure the index, modifier, and length entries in the TCBs to point to the corresponding channels data buffer, coefficient buffer and output data buffer. The location of the first channels TCB is written to the chain pointer register in the accelerator.

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IIR Accelerator

6. Program the global control register IIR_NCH bit for 2 channels. a. The accelerator starts and loads the first channels TCB, loads coefficients and Dk values of all the 6 biquads into local storage, then loads the TCB of the second channel, and finally loads coefficients and Dk values of all the 8 biquads. b. Once all the coefficients and Dk values are loaded, the controller loads the TCB of first channel and fetches the input sample. It then starts calculating the first biquad of the first channel. c. The accelerator calculates the output of the first biquad and then updates the intermediate results for that biquad. Then it moves to the next biquad of that channel and repeats the biquad processing until all the biquads for that channel are done and the final result is stored to memory. d. The accelerator repeats this process with next sample until one window of the corresponding channel is processed. Once the window is done, the accelerator saves the index values to memory and moves to the next channel. After both channels are done, the accelerator waits for core intervention.

Throughput Comparison Accelerator Versus Core

The following sections provide throughput comparisons between the FIR/IIR/FFT hardware module and the core. The cycles for the accelerators were calculated using the throughput expressions provided in earlier sections while that for the core were calculated with the help of the optimized C library functions. In each case, the solid line is used for the core and the dashed line for the accelerator.

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FFT Figure 7-15 shows a graphical comparison between the number of CCLK cycles consumed by the core and the FFT accelerator to perform the FFT operation for different numbers of points (N).
80 70 CCLK Cycles (in thousands) 60 50 40 30 20

10 0 0 200 400 600 Number of Points (N) 800 1000 1200

Figure 7-15. FFT Accelerator Comparison to Core In most of the cases, the core takes fewer cycles than the FFT accelerator. However, the difference in number of cycles is comparatively less for N<=256 (small FFT) and becomes much more significant for N>256 (large FFTs). FIR Figure 7-16 through Figure 7-18 show a graphical comparison between the number of CCLK cycles consumed by the core and the FIR accelerator

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IIR Accelerator

to perform the FIR operation for different window (block) size (W) and tap length (N) values.
200

CCLK Cycles (in thousands)

150

100

50

0 0 10 20 30 40 Window Size (W) 50 60 70

Figure 7-16. FIR Core/Accelerator Comparison, N = 256

200

CCLK Cycles (in thousands)

150

100

50

0 0 10 20 30 40 Window Size (W) 50 60 70

Figure 7-17. FIR Core/Accelerator Comparison, N = 2048

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FFT/FIR/IIR Hardware Modules

200

CCLK Cycles (in thousands)

150

100

50

0 0 10 20 30 40 Window Size (W) 50 60 70

Figure 7-18. FIR Core/Accelerator Comparison, N = 4096 The cycles for the accelerator were calculated using the throughput expression provided in one of the previous sections while those for the core were calculated with the help of one of the C FIR library functions. The figures show that for a fixed tap length, the larger the window size, the better performance is achieved using the FIR accelerator. As the window size increases, initially the accelerator consumes more cycles than the core. However, after a threshold, the accelerator performs better than the core. The reason of such behavior is the trade-off between the four MACs (each running simultaneously at the PCLK rate) and the overhead for initial pre-loading of the delay line and the coefficient memory. The cycles required by the pre-loading become less significant as the window size increases while the performance achieved using the four MACs in parallel become more significant. IIR Figure 7-19 through Figure 7-21 show a graphical comparison between the number of CCLK cycles consumed by the core and the IIR accelerator to

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IIR Accelerator

perform the IIR operation for different block size (W) and filter order (N) or number of biquads (B = N/2).
10

CCLK Cycles (in thousands)

0 0 10 20 30 40 Window Size (W) 50 60 70

Figure 7-19. IIR Core/Accelerator Comparison, N = 4, B = 2

10

CCLK Cycles (in thousands)

0 0 10 20 30 40 Window Size (W) 50 60 70

Figure 7-20. IIR Core/Accelerator Comparison, N = 12, B = 6

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FFT/FIR/IIR Hardware Modules

10

CCLK Cycles (in thousands)

0 0 10 20 30 40 Window Size (W) 50 60 70

Figure 7-21. IIR Core/Accelerator Comparison, N = 24, B = 12 In most of these cases the core takes fewer cycles than the IIR accelerator. The difference between the cycles taken by the core and the accelerator is almost negligible for lower order IIR operations but becomes more significant for higher order IIR operations. This difference increases as the window size is increases.

Debug Features
The following sections describe the debugging features available on the accelerator. Local Memory Access The contents of IIR delay line and coefficient memories are made observable for debug by setting the IIR_DBGMODE/IIR_DBGMEM and IIR_HLD bits in the IIRDEBUGCTL control register. The debug address register (IIRDBGADDR) and four data registers are provided for debug operations. Bit 11 of the this register selects coefficient memory if set (=1) and selects delay line memory in cleared (=0).

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IIR Accelerator

The 40-bit wide debug mode read data register is organized as: The IIRDBGRDDATA_L register holds the lower 32 bits The IIRDBGRDDATA_H register holds the upper 8 bits The 40-bit wide debug mode write data register is organized as: The IIRDBGWRDATA_L register holds the lower 32 bits and The IIRDBGWRDATA_H register holds the upper 8 bits A read from the IIRDBGRDDATA_L register followed by a read from the IIRDBGRDDATA_H register returns the content of the 40-bit memory location pointed to by the address register. Data can be written into any memory location using the IIRDBGWRDATA_L register followed by the IIRDBGWRDATA_H register. If the address auto increment bit (IIR_ADRINC) is set, the address register auto increments on IIRDBGWRDATA_H/L writes and IIRDBGRDDATA_H/L reads. During auto increment, the IIR_DBGADDR register cannot cross the data memory/coefficient memory boundary. The address boundary for data memory is 1024 locations and for coefficient memory 2048 locations Single Step Mode Programs can single step through the MAC operations and observe the memory contents after each step. The IIR_DBGMODE/IIR_HLD and IIR_RUN bits control the IIR MAC units. Emulation Considerations In IIR debug mode, the DMA operations are not observable.

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Application Guidelines for Effective Use of the FIR/IIR/FFT Accelerators

From the throughput numbers mentioned in the earlier sections of this chapter, one might find that the FIR/IIR/FFT accelerators/off-load engines may not finish the same processing task faster than using the core. This implies that using the accelerators in the conventional sequential approach and making the core wait until the accelerator finishes processing may not be advantageous from the performance point of view. The only way to get the most out of the accelerators is to make sure that the core is busy doing something useful when the accelerator is performing a processing task. Thus, in order to use these accelerators effectively, special care must be taken while designing the application framework. The following sections describe two approaches to consider.

Sample Versus Block Processing Operation

It may be difficult to achieve the required performance by using sample based processing (Window size = 1). Increasing the window size provides more computation time and the ability to perform the real time processing. It is a common practice to use block based processing (Window size greater 1). In the following example, the core is running at 450 MHz with a single channel tap length of 512. Sampling frequency = 96 kHz and the maximum processing time is 10 s. The computation of the filter requires: TCB load + 4 N + W(N/4 + 2)) C. For window size = 1 49 + 4 512 + 1 (512/4 + 2) = 2227 PCLK = 9.8 s. For window size = 10

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Application Guidelines for Effective Use of the FIR/IIR/FFT Accelerators

49 + 4 512 + 10 (512/4 + 2) = 3397 PCLK = 15 s. Therefore, 10 samples at 96 kHz = 10 10 = 100 us of available processing time: Actual time used is 15 s.

Adding Pipeline Stages

The first approach is to pipeline the input and output data buffers wherever filter/FFT engines are to be used. This can be done by adding a ping-pong buffer mechanism where the core and the filter engines operate on two different blocks of the data. The data blocks move from/to the core and to/from the off-load engine in a pipelined fashion. This ensures that the core and filter engine operate totally independently and without the need to wait for each other. The disadvantage of this approach is that it adds more latency in the final output. This latency increases with the increase in the pipeline stages.

Splitting Tasks
The second approach is to off-load the cores tasks to the accelerators (relevant for applications where multichannel data is involved). This is accomplished by splitting the processing task between core and the accelerator. This doesnt require much change in the existing application framework as no data pipe-lining is used. When processing multichannel data, a few channels can be off-loaded to the filter/FFT engine and the rest to the processor core. With proper partitioning, the application ensures that the core isnt in an idle state after processing its channels.

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8 PULSE WIDTH MODULATION

Pulse width modulation (PWM) is a technique for controlling analog circuits with a microprocessors digital outputs. PWM is employed in a wide variety of applications, ranging from measurement to communications to power control and conversion. The interface specifications are shown in Table 8-1. Table 8-1. PWM Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access No N/A N/A Yes N/A N/A N/A N/A Yes, (External port) No N/A Yes Availability

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Features

Table 8-1. PWM Specifications (Contd)

Feature DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation Availability N/A N/A N/A No fPCLK

Features
The following is a brief summary of the features of this interface. Four independent PWM units 2-phase output timing unit Center or edge aligned PWM Single or double update PWM timer period Output logic allows redirection of 2-phase output timing PWM units can operate synchronized to each other Complementary outputs allows bridge based applications A block diagram of the module is shown in Figure 8-1. The generation of the four output PWM signals on pins AH to BL is controlled by four primary blocks. The two-phase PWM timing unit, which is the core of the PWM controller, generates two pairs of complemented center based PWM signals.

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Pulse Width Modulation

The emergency dead time insertion is implemented after the ideal PWM output pair, including crossover, is generated. The output control unit allows the redirection of the outputs of the two-phase timing unit for each channel to either the high-side or the low-side output. In addition, the output control unit allows individual enabling/disabling of each of the four PWM output signals. The PWM interrupt controller generates an interrupt at the start of the PWM period which is shared for all modules.

PERIPHERAL CORE BUS

PWM STATUS

PWM CONTROL PWM PERIOD

PWM DUTY CYCLE CONTROL

PWM DEAD TIME

PWM OUTPUT CONTROL

AH PWM INTERRUPT
TWO-PHASE PWM GENERATOR UNIT

PCLK

DEAD TIME CONTROL UNIT

AL OUTPUT CONTROL UNIT BH BL

Figure 8-1. PWM Module Block Diagram

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Pin Descriptions

Pin Descriptions
The PWM module has four groups of four PWM outputs each, for a total of 16 PWM outputs. These outputs are described in Table 8-2. Table 8-2. PWM Pin Descriptions
Multiplexed Pin Name PWM_AH30 PWM_AL30 PWM_BH30 PWM_BL30 Direction O O O O Description PWM output of pair A produce high side drive signals. PWM output of pair A produce low side drive signals. Note in paired mode, this pin is the complement of AH3-0. PWM output of pair B produce high side drive signals. PWM output of pair B produce low side drive signals. Note in paired mode, this pin is the complement of BH3-0.

Multiplexing Scheme
By default the PWM output pins are disabled. To enable the PWM units refer to Table 24-15 on page 24-30. Table 8-3 shows the connection to the PWM outputs on the external port pins. For more information, see Pin Multiplexing on page 24-28. Table 8-3. PWM Connections
PWM Unit PWM0 Pin Multiplexing1 ADDR8 = AL0 ADDR9 = AH0 ADDR10 = BL0 ADDR11 = BH0 ADDR12 = AL1 ADDR13 = AH1 ADDR14 = BL1 ADDR15 = BH1

PWM1

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Pulse Width Modulation

Table 8-3. PWM Connections (Contd)

PWM Unit PWM2 Pin Multiplexing1 ADDR16 = AL2 ADDR17 = AH2 ADDR18 = BL2 ADDR19 = BH2 ADDR20 = AL3 ADDR21 = AH3 ADDR22 = BL3 ADDR23 = BH3

PWM3

For ADSP-2146x products the pins are AMI_ADDRx.

SRU Programming
The ADSP-2147x and ADSP-2148x can output the PWM31 units over the DPI pins. The PWMONDPIEN bit (bit 30 in the SYSCTL register) enables the routing output logic for the DPI group B register.

Register Overview
This section provides brief descriptions of the major registers. For complete register information, see Appendix A, Register Reference. PWM Global Control Register (PWMGCTL). Enables or disables the four PWM groups simultaneously in any combination for synchronization between the PWM groups. PWM Global Status Register (PWMGSTAT). Provides the status of each PWM group. PWM Control Registers (PWMCTLx). Used to set the operating modes of each PWM block. This register also allows programs to disable interrupts from individual groups.

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Clocking

PWM Status Registers (PWMSTATx). Report the phase and mode status for each PWM group. a The traditional read-modify-write operation to enable/disablesee peripheral is different for the PWMs. For more information, Global Control Register (PWMGCTL) on page A-67.

Clocking
The fundamental timing clock of the PWM controllers is peripheral clock (PCLK). The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

Functional Description
The individual elements shown in Figure 8-1 are described in detail in the following sections.

Two-Phase PWM Generator

Each PWM group is able to generate complementary signals on two outputs in paired mode or each group can provide independent outputs in non-paired mode. Switching Frequencies The 16-bit read/write PWM period registers, PWMPERIOD30, control the PWM switching frequency.

The PWM generator does not support external synchronization mode.

The fundamental timing unit of the PWM controller is PCLK. Therefore, for a 200 MHz peripheral clock, the fundamental time increment is 5 ns. 8-6 ADSP-214xx SHARC Processor Hardware Reference

Pulse Width Modulation

The value written to the PWMPERIODx register is effectively the number of PCLK clock increments in a PWM period (edge aligned mode) or in a half PWM period (center aligned mode) in half a PWM period. Therefore, the PWM switching period, Ts, can be written as: Ts = 2 PWMPERIOD tPCLK (edge aligned) Ts = PWMPERIOD tPCLK (center aligned) For example, for a 200 MHz PCLK and a desired PWM center aligned switching frequency of 10 kHz (Ts = 100 s), the correct value to load into the PWMPERIODx register is: 200 10 PWMPERIOD = ------------------------------ = 10000
2 10 10 3 6

The largest value that can be written to the 16-bit PWMPERIODx register is 0xFFFF = 65,535 which corresponds to a minimum PWM switching frequency of: 200 10 f ( PWM ) ,min = ------------------------- = 1523 Hz
2 65535 6

values of 0 and are not defined and should when the PWM outputs or1 PWM sync is enabled. not be used
PWMPERIOD

Duty Cycles The two 16-bit read/write duty cycle registers, PWMA and PWMB, control the duty cycles of the four PWM output signals on the PWM pins. The twos-complement integer value in the PWMA register controls the duty cycle of the signals on the PWM_AH and PWM_AL. The twos-complement integer value in the PWMB register controls the duty cycle of the signals on PWM_BH and PWM_BL pins. The duty cycle registers are programmed in twos-complement integer counts of the fundamental time unit, PCLK, and

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Functional Description

define the desired on-time of the high-side PWM signal produced by the two-phase timing unit over half the PWM period. The duty cycle register range is from: (PWPERIOD 2 PWMDT) to (+PWPERIOD 2 + PWMDT) which, by definition, is scaled such that a value of 0 represents a 50% PWM duty, cycle. The switching signals produced by the two-phase timing unit are also adjusted to incorporate the programmed dead time value in the PWMDT register. The two-phase timing unit produces active low signals so that a low level corresponds to a command to turn on the associated power device. A typical pair of PWM outputs (in this case for PWM_AH and PWM_AL) from the timing unit are shown in Figure 8-2 for operation in single update mode. All illustrated time values indicate the integer value in the associated register and can be converted to time by simply multiplying by the fundamental time increment, (PCLK) and comparing this to the twos-complement counter. Note that the switching patterns are perfectly symmetrical about the midpoint of the switching period in single update mode since the same values of the PWMAx, PWMPERIODx, and PWMDTx registers are used to define the signals in both half cycles of the period. Further, the programmed duty cycles are adjusted to incorporate the desired dead time into the resulting pair of PWM signals. As shown in Figure 8-2, the dead time is incorporated by moving the switching instants of both PWM signals (PWM_AH and PWM_AL) away from the instant set by the PWMAx registers. Both switching edges are moved by an equal amount (PWMDT PCLK) to preserve the symmetrical output patterns. Also shown is the PWM_PHASE bit of the PWMSTAT register that indicates whether operation is in the first or second half cycle of the PWM period.

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Pulse Width Modulation

count

PWMPERIOD + 2

PWMPERIOD 0
PWMCHA

0
PWMCHA

PWMPERIOD + 2

PWM_AH

......................

......................

PWM_AL

.....

.....

2xPWMDT
PWMPHASE

2xPWMDT

PWMPERIOD

PWMPERIOD

PWM INTERRUPT LATCH BIT

Figure 8-2. Center-Aligned Paired PWM in Single Update Mode, Low Polarity The resulting on-times (active low) of the PWM signals over the full PWM period (two half periods) produced by the PWM timing unit and illustrated in Figure 8-2 may be written as: The range of TAH is: [ 0 2 PWMPERIOD t PCLK ] and the corresponding duty cycles are: T AH = ( PWMPERIOD 2 ( PWMCHA + PWMDT ) ) t PCLK

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Functional Description

The range of TAL is: [ 0 2 PWMPERIOD t PCLK ] and the corresponding duty cycles are: t AH 1 PWMCHA PWMDT d AH = ------- = -- + ------------------------------------------------------------------TS PWMPERIOD 2 t AL 1 PWMCHA PWMDT d AL = ------ = -- + ------------------------------------------------------------------TS PWMPERIOD 2 The minimum permissible value of TAH and TAL is zero, which corresponds to a 0% duty cycle, and the maximum value is TS, the PWM switching period, which corresponds to a 100% duty cycle. Negative values are not permitted. The output signals from the timing unit for operation in double update mode are shown in Figure 8-3. This illustrates a general case where the switching frequency, dead time, and duty cycle are all changed in the second half of the PWM period. The same value for any or all of these quantities can be used in both halves of the PWM cycle. However, there is no guarantee that a symmetrical PWM signal will be produced by the timing unit in this double update mode. Additionally, Figure 8-3 shows that the dead time is inserted into the PWM signals in the same way as in single update mode. In general, the on-times (active low) of the PWM signals over the full PWM period in double update mode can be defined as: T S = ( PWMPERIOD 1 + PWMPERIOD 2 ) t PCLK
T PWMPERIOD PWMPERIOD 1 2 = ----------------------------------------- + ----------------------------------------- PWMCHA PWMCHA PWMDT PWMDT t PCLK 1 2 1 2 AL 2 2

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Pulse Width Modulation

PWMPERIOD PWMPERIOD 1 2 = ----------------------------------------- + ----------------------------------------- + PWMCHA + PWMCHA PWMDT PWMDT t PCLK AH 1 2 1 2 2 2

PWMPERIOD1

+ count

PWMPERIOD1

2 0

PWMPERIOD2

+ 0

PWMPERIOD2

PWMCHA1

PWMCHA2

pwm_ah

......................

......................

pwm_al

.....

.....

2xPWMDT1

2xPWMDT2

PWM PHASE BIT

PWM INTERRUPT LATCH BIT

PWMPERIOD1

PWMPERIOD2

Figure 8-3. Center-Aligned Paired PWM in Double Update Mode, Low Polarity where subscript 1 refers to the value of that register during the first half cycle and subscript 2 refers to the value during the second half cycle. The corresponding duty cycles are:
T AL ) 1 ( PWMCHA 1 + PWMCHA 2 + PWMDT 1 + PWMDT 2 d AL = ---------- = -- -----------------------------------------------------------------------------------------------------------------------------------------TS 2 ( PWMPERIOD 1 + PWMPERIOD 2 )

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Functional Description

T AH 1 ( PWMCHA 1 + PWMCHA 2 PWMDT 1 PWMDT 2 ) = ----------- = -- + ----------------------------------------------------------------------------------------------------------------------------------------AH T 2 ( PWMPERIOD + PWMPERIOD ) H 1 2

since for the general case in double- update mode, the switching period is given by: T S = ( PWMPERIOD 1 + PWMPERIOD 2 ) t PCLK Again, the values of TAH and TAL are constrained to lie between zero and TS. Similar PWM signals to those illustrated in Figure 8-2 and Figure 8-3 can be produced on the BH and BL outputs by programming the PWMBx registers in a manner identical to that described for the PWMAx registers. Dead Time The second important parameter that must be set up in the initial configuration of the PWM block is the switching dead time. This is a short delay time introduced between turning off one PWM signal (say AH) and turning on the complementary signal, AL. This short time delay is introduced to permit the power switch being turned off (AH in this case) to completely recover its blocking capability before the complementary switch is turned on. This time delay prevents a potentially destructive short-circuit condition from developing across the DC link capacitor of a typical voltage source inverter. The 10-bit, read/write PWMDT30 registers control the dead time. The dead time, Td, is related to the value in the PWMDTx registers by: T d = PWMDT 2 t PCLK Therefore, a PWMDT value of 0x00A (= 10), introduces a 200 ns delay between when the PWM signal (for example AH) is turned off and its complementary signal (AL) is turned on. The amount of the dead time can

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Pulse Width Modulation

therefore be programmed in increments of 2 PCLK (or 10 ns for a 200 MHz peripheral clock). The PWMDTx registers are 10-bit registers, and the maximum value they can contain is 0x3FF (= 1023) which corresponds to a maximum programmed dead time of: T d ,max = 1023 2 t PCLK = 1023 2 5 10 9 = 10.2s

This equates to an PCLK rate of 200 MHz. Note that dead time can be programmed to zero by writing 0 to the PWMDTx registers (see Pulse Width Modulation Registers on page A-67).

Output Control Unit

The PWMSEG register contains four bits (0 to 3) that can be used to individually enable or disable each of the 4 PWM outputs. Output Enable If the associated bit of the PWMSEG register is set (=1), then the corresponding PWM output is disabled, regardless of the value of the corresponding duty cycle register. This PWM output signal remains disabled as long as the corresponding enable/disable bit of the PWMSEGx register is set. In single update mode, changes to this register only become effective at the start of each PWM cycle. In double update mode, the PWMSEG register can also be updated at the mid-point of the PWM cycle. reset, all four enable bits of Afterall PWM outputs are enabledthe default.register are cleared so that by
PWMSEG

Output Polarity The polarity of the generated PWM signals is programmed using the PWMPOLARITY30 registers, so that either active high or active low PWM patterns can be produced. The polarity values can be changed on the fly if

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Functional Description

required, provided the change is done a few cycles before the next period change. Complementary Outputs The PWM controller can be operated in paired or non paired mode (PWMCTLx register). In non paired mode (default) both outputs (high and low side) are driven independently. Since paired mode drives the output logic of the PWM in a complementary fashion (low side = /high side), this feature may be useful in PWM bridge applications. Crossover The PWMSEG30 registers contain two bits (AHAL_XOVR and BHBL_XOVR), one for each PWM output. If crossover mode is enabled for any pair of PWM signals, the high-side PWM signal from the timing unit (for example, AH) is diverted to the associated low side output of the output control unit so that the signal ultimately appears at the AL pin. The corresponding low side output of the timing unit is also diverted to the complementary high side output of the output control unit so that the signal appears at the AH pin. Following a reset, the two crossover bits are cleared so that the crossover mode is disabled on both pairs of PWM signals. Even though crossover is considered an output control feature, dead time insertion occurs after crossover transitions to eliminate shoot-through safety issues. Note that crossover mode does not work if: 1. One signal of PWM_ALPWM_AH or PWM_BLPWM_BH is disabled. 2.
PWM_AL and PWM_AH or PWM_BL and PWM_BH have different polarity settings from PWMPOLx registers.

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Pulse Width Modulation

In other words, both PWM_AL and PWM_AH or PWM_BL and PWM_BH should be enabled and both should have same polarity for proper operation of cross-over mode.

Emergency Dead Time for Over Modulation

The PWM timing unit is capable of producing PWM signals with variable duty cycle values at the PWM output pins. At the extreme side of the modulation process, settings of 0% and 100% modulation are possible. These two modes are termed full off and full on respectively. over-modulation is entered by Full off and full oncycle values in conjunction with virtue of thein commanded duty the setting the PWMDTx registers. Settings that fall between the extremes are considered normal modulation. These settings are explained in more detail below. Full On. The PWM for any pair of PWM signals operates in full on when the desired high side output of the two-phase timing unit is in the on state (low) between successive PWM interrupts. Full Off. The PWM for any pair of PWM signals operates in full off when the desired high side output of the two-phase timing unit is in the off state (high) between successive PWMSYNC pulses. Normal Modulation. The PWM for any pair of PWM signals operates in normal modulation when the desired output duty cycle is other than 0% or 100% between successive PWMSYNC pulses. There are certain situations, when transitioning either into or out of either full on or full off, where it is necessary to insert additional emergency dead time delays to prevent potential shoot-through conditions in the inverter. These transitions are detected automatically and, if appropriate, the emergency dead time is inserted to prevent the shoot through conditions.

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Functional Description

Inserting additional emergency dead time into one of the PWM signals of a given pair during these transitions is only needed if both PWM signals would otherwise be required to toggle within a dead time of each other. The additional emergency dead time delay is inserted into the PWM signal that is toggling into the on state. In effect, the turn on (if turning on during this dead time region), of this signal is delayed by an amount of 2 PWMDT PCLK from the rising edge of the opposite output. After this delay, the PWM signal is allowed to turn on, provided the desired output is still scheduled to be in the on state after the emergency dead time delay. Figure 8-4 illustrates two examples of such transitions. In (a), when transitioning from normal modulation to full on at the half cycle boundary in double update mode, no special action is needed. However in (b), when transitioning into full off at the same boundary, an additional emergency dead time is necessary. This inserted dead time is a little different from the normal dead time as it is impossible to move one of the switching events back in time because this would move the event into the previous modulation cycle. Therefore, the entire emergency dead time is inserted by delaying the turn on of the appropriate signal by the full amount. Output Control Feature Precedence The order in which output control features are applied to the PWM signal is significant and important. The following lists the order in which the signal features are applied to the PWM output signal. 1. Duty Cycle Generation 2. Crossover 3. Output Enable 4. Emergency Dead Time Insertion 5. Output Polarity

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PWMPERIOD1

0
PWMCHA1

PWMPERIOD1

PWMPERIOD2

FULL ON

............................................

PWM_AH

............................................

2xPWMDT PWM_AL

(a)

FULL OFF

PWM_AH

(b)
2xPWMDT

PWM_AL

EMERGENCY DEAD TIME INSERTED BY PWM CONTROLLER PWMPERIOD PWMPERIOD

(a) TRANSITION FROM NORMAL MODULATION TO FULL-ON, AT HALF-CYCLE BOUNDARY IN DOUBLE UPDATE MODE, WHERE NO ADDITIONAL DEAD TIME IS NEEDED. (b) TRANSITION FROM NORMAL MODULATION TO FULL-OFF, AT HALF-CYCLE BOUNDARY IN DOUBLE UPDATE MODE, WHERE ADDITIONAL DEAD TIME IS INSERTED BY THE PWM CONTROLLER

Figure 8-4. Normal Modulation to Full ON to Full OFF Transition

Operation Modes
The following sections provide information on the operating modes of the PWM module.

Waveform Modes
The PWM module can operate in both edge- and center-aligned modes. These modes are described in the following sections.

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Operation Modes

Edge-Aligned Mode In edge-aligned mode, shown in Figure 8-5, the PWM waveform is left-justified in the period window. A duty value of zero, programmed through the PWMAx registers, produces a PWM waveform with 50% duty cycle. For even values of period, the PWM pulse width is exactly period/2, whereas for odd values of period, it is equal to period/2 (rounded up). Therefore for a duty value programmed in twos-complement, the PWM pulse width is given by: To generate constant logic high on PWM output, program the duty register with the value + period/2. To generate constant logic low on PWM output, program the duty register with the value period/2. For example, using an odd period of p = 2n + 1, the counter within the PWM generator counts as (n...0...+n). If the period is even (p = 2n) then the counter counts as (n+1...0...n). The PWM switching period time for edge aligned mode is: Ts = tPCLK PWMPERIOD. For more information seePulse Width Modulation Registers on page A-67.

PERIOD/2

DUTY

PERIOD

Figure 8-5. Edge Aligned PWM Wave with High Polarity

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Center-Aligned Mode Most of the following description applies to paired mode, but can also be applied to non-paired mode, the difference being that each of the four outputs from a PWM group is independent. Within center aligned mode, shown in Figure 8-6 there are several options to choose from. Center-Aligned Single Update Mode. Duty cycle values are programmable only once per PWM period, so that the resultant PWM patterns are symmetrical about the mid-point of the PWM period. Center-Aligned Double Update Mode. Duty cycle values are programmable only twice per PWM period. This second updating of the PWM registers is implemented at the mid-point of the PWM period, producing asymmetrical PWM patterns that produce lower harmonic distortion in two-phase PWM inverters. Center-Aligned Paired Mode. Generates complementary signals on two outputs. Center-Aligned Non-Paired Mode. Generates independent signals on two outputs. In paired mode, the twos-complement integer values in the 16-bit read/write duty cycle registers, PWMAx and PWMBx, control the duty cycles of the four PWM output signals on the PWM_AL, PWM_AH, PWM_BL and PWM_BH pins respectively. The duty cycle registers are programmed in twos-complement integer counts of the fundamental time unit, PCLK and define the desired on time of the high side PWM signal over one-half the PWM period. The duty cycle register range is from (PWMPERIOD/2 PWMDT) to (+PWMPERIOD/2 + PWMDT), which, by definition, is scaled such that a value of 0 represents a 50% PWM duty cycle.

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Operation Modes

PWM TIME DECREMENTS FROM PWMPERIOD/2 TO -PWMPERIOD/2 PWMPERIOD/2

PWM TIME DECREMENTS FROM -PWMPERIOD/2 TO PWMPERIOD/2

-PWMPERIOD/2

PCLK

PWMPHASE BIT

PWM INTERRUPT LATCH (SINGLE UPDATE MODE) PWM INTERRUPT LATCH (DOUBLE UPDATE MODE)

Figure 8-6. Operation of Internal PWM Timer (Center Aligned) Each group in the PWM module (03) has its own set of registers which control the operation of that group. The operating mode of the PWM block (single or double update mode) is selected by the PWM_UPDATE bit (bit 2) in the PWM control (PWMCTRL30) registers. Status information about each individual PWM group is available to the program in the PWM status (PWMSTAT30) registers. Apart from the local control and status registers for each PWM group, there is a single PWM global control register (PWMGCTL) and a single PWM global status register ( PWMGSTAT). The global control register allows programs to enable or disable the four groups in any combination, which provides synchronization across the four PWM groups. The global status register shows the period completion status of each group. On period completion, the corresponding bit in the PWMGSTAT

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Pulse Width Modulation

register is set and remains sticky. The program first reads the global status register and clears all the intended bits by explicitly writing 1.

PWM Timer Edge Aligned Update

The internal operation of the PWM generation unit is controlled by the PWM timer which is clocked at the peripheral clock rate, PCLK. The operation of the PWM timer over one full PWM period is illustrated in Figure 8-7. It can be seen that during the first half cycle, the PWM timer decrements from PWMPERIOD/2 to 0 using a twos-complement count. At this point, the count direction changes and the timer continues to increment from 0 to the PWMPERIOD/2 value. Also shown in Figure 8-7 are the PWM interrupt pulses for operation in edge aligned mode. An PWM interrupt is latched at the beginning of every PWM cycle. Note that the PWMPHASE bit (PWMSTAT register) has no meaning in this mode and is always set.

PWM TIME DECREMENTS FROM PWMPERIOD/2 TO -PWMPERIOD/2 PWMPERIOD/2

PWM TIME DECREMENTS FROM -PWMPERIOD/2 TO PWMPERIOD/2

-PWMPERIOD/2

PCLK

PWM INTERRUPT LATCH

Figure 8-7. Operation of Internal PWM Timer (Edge Aligned)

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Operation Modes

Single Update Mode In single update mode, a single PWM interrupt is produced in each PWM period. The rising edge of this signal marks the start of a new PWM cycle and is used to latch new values from the PWM configuration registers (PWPERIOD and PWMDT) and the PWM duty cycle registers (PWMCHx) into the two-phase timing unit. In addition, the PWMSEG register is also latched into the output control unit on the rising edge of the PWM interrupt latch pulse. In effect, this means that the characteristics and resultant duty cycles of the PWM signals can be updated only once per PWM period at the start of each cycle. The result is that PWM patterns that are symmetrical about the mid-point of the switching period are produced. Double Update Mode In double update mode, there is an additional PWM interrupt latch pulse produced at the mid-point of each PWM period. The rising edge of this new PWM pulse is again used to latch new values of the PWM configuration registers, duty cycle registers and the PWMSEG register. As a result, it is possible to alter both the characteristics (switching frequency and dead time) as well as the output duty cycles at the mid-point of each PWM cycle. Consequently, it is possible to produce PWM switching patterns that are no longer symmetrical about the mid-point of the period (asymmetrical PWM patterns). In double update mode, it may be necessary to know whether operation at any point in time is in either the first half or the second half of the PWM cycle. This information is provided by the PWMPHASE bit of the PWMSTAT register which is cleared during operation in the first half of each PWM period (between the rising edge of the original PWM interrupt latch pulse and the rising edge of the new PWM interrupt pulse introduced in double update mode). The PWMPHASE bit of the PWMSTAT register is set during operation in the second half of each PWM period. This status bit allows programs to make a determination of the particular half-cycle during implementation of the PWM interrupt service routine, if required.

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The advantage of the double update mode is that the PWM process can produce lower harmonic voltages and faster control bandwidths are possible. However, for a given PWM switching frequency, the interrupts occur at twice the rate as in double update mode. Since new duty cycle values must be computed in each PWM interrupt service routine, there is a larger computational burden on the processor in the double update mode. Alternatively, the same PWM update rate may be maintained at half the switching frequency to give lower switching losses.

Effective Accuracy
The PWM has 16-bit resolution but accuracy is dependent on the PWM period. In single update mode, the same values of PWMA and PWMB are used to define the on times in both half cycles of the PWM period. As a result, the effective accuracy of the PWM generation process is 2 x PCLK (or 10 ns for a 200 MHz clock). Incrementing one of the duty cycle registers by one changes the resultant on time of the associated PWM signals by PCLK in each half period (or 2 x PCLK for the full period). In double update mode, improved accuracy is possible since different values of the duty cycles registers are used to define the on times in both the first and second halves of the PWM period. As a result, it is possible to adjust the on-time over the whole period in increments of PCLK. This corresponds to an effective PWM accuracy of PCLK in double update mode (or 10 ns for a 200 MHz clock). The achievable PWM switching frequency at a given PWM accuracy is tabulated in Table 8-4. In Table 8-4, PCLK = 200 MHz. Table 8-4. PWM Accuracy in Single- and Double Update Modes
Resolution (bits) 8 9 10 11 Single Update Mode PWM Frequency (kHz) 200 MHz 2 28 = 390.63 195.3 97.7 48.8 Double Update Mode PWM Frequency (kHz) 200 MHz 28= 781.25 390.6 195.3 97.7

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Interrupts

Table 8-4. PWM Accuracy in Single- and Double Update Modes (Contd)
Resolution (bits) 12 13 14 Single Update Mode PWM Frequency (kHz) 24.4 12.2 6.1 Double Update Mode PWM Frequency (kHz) 48.8 24.4 12.2

Synchronization of PWM Groups

The PWMGCTL register enables or disables the four PWM groups in any combination. This provides synchronization across the four PWM groups. The PWM_SYNCENx bits in this register can be used to start the counter without enabling the outputs through PWM_EN. So when PWM_ENx is asserted, the 4 PWM outputs are automatically synced to the initially programmed period. In most cases, all SYNC bits can be initialized to zero, enabling the PWM_ENx bits of the four PWM groups at the same time synchronizes the four groups. The PWM sync enable feature allows programs to enable the PWM_SYNCENx bits to independently start the main counter without enabling the corresponding PWM module using the PWM_ENx bits. To synchronize different groups, enable the corresponding groups PWM_ENx bit at the same time. In order to stop the counter both the PWM_DISx and PWM_SYNCDISx bits should be set in this register.

Interrupts
Table 8-5 provides an overview of PWM interrupts.

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Table 8-5. Overview of PWM Interrupts

Default Programmable Sources Interrupt PWMI not connected by default PWM period start Masking Service

PWM_IRQEN bit RW1C to PWMGSTAT (PWMCTLx) + RTI instruction

Sources
The PWM module drives one interrupt signal, PWMI. All four PWM unit interrupts are logically ORed into the interrupt signal. The PWM ports can generate interrupts under these conditions. PWM Period Whenever a period starts, the PWM interrupt is generated. The interrupt latch bit is set 1 PCLK cycle after the PWM counter resumes.

Masking
The PWMI signal is not routed by default to programmable interrupts. To service the PWM port, unmask (set = 1) any programmable interrupt bit in the IMASK/LIRPTL register. For interrupt execution, the specific PWM_IRQEN bit in the PWMCTLx register must be set.

Service
Since all four PWM units share the same interrupt vector, the interrupt service routine should read the PWMGSTAT register in order to determine the source of the interrupt. Next, the ISR needs to clear the status bits of the PWMGSTAT register by explicitly writing 1 into the status bit (RW1C operation) as shown in Listing 8-1.

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Interrupts

Listing 8-1. Writing 1 Into the Status Bit

GPWM_ISR: ustat2=dm(PWMGSTAT); bit tst ustat2 PWM_STAT2; if tf jump PWM2_ISR; instruction; instruction; PWM2_ISR: r1=PWM_STAT2; dm(PWMGSTAT)=r1; r10=dm(PWMCTL2); instruction; rti; /* W1C to clear PWM2 interrupt */ /* dummy read for write latency */ /* read global status reg */ /* test PWM2 status */ /* jump to PWM2 routine */

Typically the PWM interrupt is used to periodically execute an interrupt service routine (ISR) to update the two PWM channel duty registers according to a control algorithm based on expected system operation. The PWM interrupt can trigger the ADC to sample data for use during the ISR. During processor boot the PWM is initialized and program flow enters a wait loop. When a PWM interrupt occurs, the ADC samples data, the data is algorithmically interpreted, and new PWM channel duty cycles are calculated and written to the PWM. More sophisticated implementations include different startup, runtime, and shutdown algorithms to determine PWM channel duty cycles based on expected behavior and further features. During initialization, the PWMPERIOD register is written to define the PWM period and the PWMCHx registers are written to define the initial channel pulse widths. The PWMSEG and PWMCHx registers are also written, depending on the system configuration and modes. During the PWM interrupt driven control loop, only the PWMCHx duty values are typically updated. The PWMSEG register may also be updated for other system implementations requiring output crossover.

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Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

PWM Effect Latency

After the PWM registers are configured the effect latency is 1 PCLK cycle minimum and 2 PCLK cycles maximum.

Debug Features
The module contains four debug status registers (PWMDBG30), which can be used for debug aid. Each register is available per unit. The registers return current status information about the AH, AL, BH, BL output pins.

Status Debug Register

The module contains four debug status registers (PWMDBG30), which can be used for debug aid. Each register is available per unit. The registers return current status information about the AH, AL, BH, BL output pins.

Emulation Considerations
An emulation halt does not stop the PWM period counter.

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Debug Features

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9 MEDIA LOCAL BUS

Media Local Bus (MediaLB) is an on-PCB or inter-chip communication bus, which allows an application to access the MOST network data. Media Local Bus supports all the MOST network data transport methods including synchronous stream data, asynchronous packet data, control message data and isochronous data. The media local bus topology supports communication among the MLB controller and MLB devices, where the MLB controller is the interface between the MLB devices and the MOST network. More information on the MediaLB protocol can be found in the MediaLB Device Specification at www.smsc-ais.com. Table 9-1 shows the interface specifications. Table 9-1. MLB Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control No No N/A No N/A Yes Availability

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Table 9-1. MLB Specifications (Contd)

Feature Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation Yes Yes Yes 31 No No Yes 50 MHz No Yes Yes Yes No Availability

The MLB module in the ADSP-214xx serves as an interface between the MediaLB and ADSP-214xx, implementing the requirements of the physical layer and the link layer outlined in the MediaLB specification. It supports up to 31 logical channels with up to 124 bytes of data per MediaLB frame. Transmit and receive data can be transferred between MediaLB and on-chip memory with single word core-driven transfers or with DMA block transfers. interface supports MOST25 and MOST50 streaming The MLBrates. Isochronous modes of transfer are not supported. port data

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Features
The MLB device has the following features. Support for both 3-pin and 5-pin MediaLB interfaces Selectable MediaLB clock rate: 256Fs, 512Fs and 1024Fs Support for control, streaming and packet data Support for 31 channels, configured for any channel type (synchronous, asynchronous, control) and direction (transmit and receive) DMA and core-driven data transport methods Memory for channel data buffering System channel command handling Hardware loop-back test mode support Support for transmit command and data transmission Support for data reception and receive status response transmission Programmable threshold and depth for all buffers Support for Big-Endian and Little-Endian data formats Support for streaming channel frame synchronization

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Pin Descriptions

Pin Descriptions
The MediaLB pin descriptions can be found in the product specific data sheet. the MLB module is programmed as a 3-pin interface. By defaultinformation, see Device Control Configuration Register For more (MLB_DCCR) on page A-94.

Register Overview
The following sections provide brief descriptions of the registers used by the MediaLB interface. For complete bit descriptions, see Media Local Bus Registers on page A-93.

Device Configuration and Status Registers

These registers are used to set up the basic features of the interface and to report status of the MLB network. They include the following registers. Device Control Configuration Register (MLB_DCCR). Controls the device pin connectivity, enable/disable, clock rate, lock status and addressing of the MLB. System Status Register (MLB_SSCR), System Data Configuration Register (MLB_SDCR), System Mask Configuration Register (MLB_SMCR). Controls system features of the MediaLB interface and system interrupt handling. Synchronous Base Register (MLB_SBCR), Asynchronous Base Register (MLB_ABCR). Defines the base address for control Rx/Tx system memory buffers.

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Channel Registers
These registers are used to configure and monitor individual MLB channels. They include the following registers. Channel Control Registers (MLB_CECRx). Defines basic attributes about a given logical channel, such as the channel enable, channel type, channel direction, and channel address. The definition of the bit fields in this register vary depending on the selected channel type. Channel Interrupt Status Register (MLB_CICR). Reflects the channel interrupt status of the individual logical channels. These bits are set by hardware when a channel interrupt is generated. The channel interrupt bits are sticky and can only be reset by software. Channel Status Configuration Registers (MLB_CSCRx). Reflects the status of the current buffer and previous buffer for a given logical channel. The definition of the bit fields in this register vary dependant on the selected channel type. Channel Current Buffer Configuration Registers (MLB_CCBCRx), Channel Next Buffer Configuration Registers (MLB_CNBCRx), Local Buffer Configuration Registers (MLB_LCBCRx). These registers allow programs to control and monitor the buffers used in the MLB network.

Clocking
The MLB controller provides an external clock pinthe media local bus clock. This clock is generated by the MLB controller that is synchronized to the MOST network and provides the timing for the entire MLB interface at 49.152 MHz at FS = 48 kHz. The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

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Functional Description

Functional Description
Figure 9-1 illustrates the MLB high level architecture. The MLB core serves as an interface between the MediaLB and the ADSP-214xx, implementing the requirements of the physical layer and the link layer outlined in the MediaLB specification. The MLB core has the following responsibilities. Transmit commands/data operating as transmit device associated with a Channel Address. Receive data and transmit RxStatus responses when functioning as the receiving device associated with a Channel Address. MLB lock detection. System channel command handling. The MLB local channel buffer is a single ported RAM which implements the local channel buffering for the MLB device. It is 36 bits wide and 124 words long.

IOD0 BUS

SRAM LOCAL CHANNEL BUFFER 36 x 124 BITS

ADDR[6:0] DMA ARBITER HBI I/O PINS BUFFER LINK CORE

PERIPHERAL CORE BUS

MLB IRQ CONFIGURATION PBI

Media LB

Figure 9-1. Media LB Block Diagram

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Media LB Protocol
Once per MOST network frame, the MLB controller generates a unique frame sync pattern on the MLBSIG line. The end of the frame sync pattern defines the byte boundary and the channel boundary for the MLBSIG and MLBDAT lines of all MLB devices. The MLB controller manages the arbitration for all the channels on the MLB and grants bandwidth for all the MLB devices. A MLB physical channel is defined as four bytes wide, or a quadlet. Physical channels can be grouped into multiple quadlets (which do not have to be consecutive) to form a MLB logical channel, which is defined by a unique channel address. As shown in Figure 9-2, the MLB controller initiates communication by sending out a channel address on the MLBSIG line for each physical channel. The channel address indicates which MLB device is transmitting and which MLB devices are receiving in the following physical channel. Therefore, four bytes after the controller outputs the channel address on the MLBSIG line, the transmitting device outputs a command byte command on the MLBSIG line and outputs the respective data on the MLBDAT line, concurrently. The MLB command byte contains the type of data currently being transmitted (for example synchronous, asynchronous or control). The MLB device receiving the channel data outputs a status byte, RxStatus, on the MLBSIG line immediately after the transmitting device outputs the command byte. The status response can indicate that the receiving device is busy and cannot receive the data at present, or the device is ready to receive the data. Since synchronous stream data is sent in a broadcast fashion, receiving devices cannot return a busy status and should not drive RxStatus onto the MLBSIG line.

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Operating Modes

CONTROLLER GRANTS THE TRANSMITTING DEVICE ACCESS TO THE LOGICAL CHANNEL ASSOCIATED WITH THE CHANNELADDRESS

TRANSMITTING DEVICE SENDS ITS COMMAND AND ASSOCIATED DATA ON THE LOGICAL CHANNEL ASSOCIATED WITH THE CHANNELADDRESS RECEIVING DEVICE ACCEPTS OR REJECTS THE DATA USING THE RXSTATUS FIELD

MLBSIG

CHANNEL ADDRESS

RX TXCMD STATUS

MLBDAT

DATA

4-BYTE DELAY 1 QUADLET = 1 PHYSICAL CHANNEL 1 QUADLET = 1 PHYSICAL CHANNEL

Figure 9-2. MLB Data Structure

Operating Modes
The following sections describe the operating modes of the MLB interface. The channel type selection enables the logical channels to operate in synchronous, asynchronous or control channels described here.

The logical channels can be any combination of channel type (for example synchronous, asynchronous, or control) and direction
(transmit or receive).

Logical Channel Control

Table 9-2 provides an overview of the control register settings for the logical channels (MLB_CECR30-0). The CTYPE bits (bits 28 and 29) are used to configure whether the channel is synchronous, asynchronous, or control.

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Table 9-2. MLB_CECRx Register Bit Settings

Bit 70 12-8 1413 15 16 17 18 19 20 21 22 2324 2625 27 2928 30 31 FSCD (frame sync channel disable) Reserved Reserved Synchronous Channel Asynchronous/Control Channel CA (channel address) FSPC (frame sync physical channel count) PCTH (packet count threshold, I/O mode only) Reserved Reserved IMASK0 (protocol error) IMASK1 (break detect)

IMASK2 (IO RX service request/DMA buffer done) IMASK3 (IO TX service request/DMA buffer start) IMASK4 (buffer error) Reserved IMASK6 (lost frame sync) Reserved MDS (channel mode select) FSE (frame sync enable) CTYPE = synchronous PCE (packet count enable, I/O mode only) CTYPE = asynchronous/control

CTRAN (channel data direction) CE (channel enable)

Synchronous Channels
Synchronous channels are enabled if the channel type select CTYPE bits in the MLB_CECRx register are configured accordingly (default). streaming Synchronous channel is used for real timenetwork. data which are continuously synchronous to the MOST Certain types of streaming applications require data to be synchronous with the MediaLB frame, including: stereo, 5.1 audio, and generic syn-

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Operating Modes

chronous packet format (GSPF) DTCP. This feature is provided as an optional programmable synchronous logical channel by setting the FSE bit in the MLB_CECRx register. When enabled, the synchronous logical channel begins transmitting data only at a MediaLB frame boundary. A maskable interrupt is generated when the loss of frame synchronization occurs. In order to use this option, system software must program the FSPC bits in the MLB_CECRx register with the expected number of physical channels per frame for the logical channel, and unmask the STS interrupt bit (bit 6) in the MLB_CSCRx register by setting the MASK bit in MLB_CECRx register. An interrupt is generated when the actual number of physical channels detected during a MLB frame does not match the expected value. Software can also set the FSCD bit in MLB_CSCRx register, which causes hardware to automatically disable a logical channel (clear the channel enable bit in the MLB_CECRx register) when synchronization is lost.

Asynchronous Channels
Asynchronous channels are enabled if the channel type select CTYPE bits in the MLB_CECRx register are configured accordingly. Asynchronous channels are used for packed data which is packetized and is transferred in bursts, as foe example with internet, GPS map and e-mail. Frame synchronization is not supported for asynchronous channels.

Control Channels
Control channels are enabled if the channel type select CTYPE bits in the MLB_CECRx register are configured accordingly. Control channels are used for data containing control/diagnostic and status information of devices on the MOST network. Frame synchronization is not supported for control channels.

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Data Transfer
Two modes of operation are supported for transferring channel data between the MLB and internal memory. DMA allows the multi-channel DMA engine to manage data transfers without core intervention. Core driven mode (I/O mode) allows software to manage the transfer of data between MLB and internal memory. channels data transfer method. All hardware operationmust use the samechannels operate in both Mixed mode where hardware I/O mode and DMA mode is not supported.

Core Access
Core driven mode is an interrupt driven data transfer method between hardware channels and internal memory. Core mode and data direction are configured by the channel mode select (MDS) bits and the CTRAN bit in the MLB_CECRx register. Transmit and receive service request interrupts are generated when data is to be transferred from/to internal memory to/from MLB local channel buffer.

In IO mode the and the

Threshold Depth

register is used as the receive buffer MLB_CNBCRx register as the transmit buffer.
MLB_CCBCRx

A single ported SRAM implements the local channel buffer for the Media LB device. Its capacity is 36-bits x 124 quadlets (words). The local channel buffer configuration register (MLB_LCBCRx) allows software to optimize use of the local channel buffer memory. The buffer depth, buffer threshold and buffer start address for each channel is programmed using the respective register.

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Data Transfer

As shown in Figure 9-3, once a quadlet is received on the MLB bus, it is transferred to the corresponding local channel buffer. The data transfer takes place from this local channel buffer to internal memory. After reset each channel has four quadlets each.
BUFFER DEPTH BUFFER THRESHOLD TX DATA INPUT TX DATA OUTPUT

VALID DATA

FREE QUADLETS

TRANSMIT SERVICE REQUEST GENERATED (NUMBER OF VALID DATA QUADLETS <= BUFFER THRESHOLD)

BUFFER DEPTH BUFFER THRESHOLD RX DATA OUTPUT VALID DATA FREE QUADLETS RX DATA INPUT

RECEIVE SERVICE REQUEST GENERATED (NUMBER OF FREE DATA QUADLETS <= BUFFER THRESHOLD)

Figure 9-3. Local Channel Buffer Threshold Mechanism The byte order in which data is transferred between local channel buffers and internal memory is determined by enabling either Big-Endian or Little-Endian mode. Both data transfer methods, DMA and IO mode support Big-Endian and Little-Endian system memory data formats. The buffer depth, buffer threshold and buffer start address for each channel is programmed using the respective MLB_LCBCRx register. used by hardware channels in I/O The local buffer threshold isthe local channel buffer threshold to mode only. Hardware uses determine when to issue an I/O service request to system software.

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Media Local Bus

Hardware uses the local channel buffer threshold to determine when to issue an I/O service request to system software. I/O service requests are generated when: The number of valid quadlets in the local channel buffer falls below the threshold for transmit channels or: valid quadlets <= MLB_LCBCRx (programmed using TH bits) The number of free quadlets in the local channel buffer falls below the threshold for receive channels or: free quadlets <= MLB_LCBCRx (programmed using TH bits) A receive channel detects a broken packet (ReceiverBreak, AsyncBreak, ControlBreak or ReceiverProtocolError). Configuring local channel buffer memory is accomplished using the MLB_LCBCRx register. For more information, see Programming Model on page 9-20.
Status

The local channel buffer is available by reading the buffer MLB_CSCRn register. The full/empty local buffer threshold status is depending on the MLB_LCBCRx register settings.
Flushing the Buffer

The MLB local buffer is only flushed by a system hard (RESET) or software reset (SYSCTL).

DMA
There are two modes of DMAPing-pong buffering and circular buffering. There are 31 DMA channels for the 31 logical channels. Each channel can address up to 16k words.

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Data Transfer

The DMA address is comprised of: A 5-bit base configured in the MLB base register set (MLB_SBCR, MLB_ABCR, MLB_CBCR or MLB_CBCR for the corresponding channel data type). The 5-bit base is the same for all the channels of the same type (for example for all synchronous RX channels MLB_SBCR3116 act as the base). A 14-bit offset configured using the BCA bits in the MLB_CCBCRx register. The register holds the lower 14 bits (bits 3118 for start address and 152 for end address). Bits 1716 and bits 10 are reserved and must always be written with zero. For example, if the internal address is 0xC0100, then 19 bits of the address translates to address 0x40100 because the internal memory offset for the ADSP-214xx is 0x0008 0000. The lower 14 bits (00 0001 0000 0000) and the 2 reserved bits 00 are written in the MLB_CNBCRx register (write 0000 0100 0000 0000 = 0x0400 to bits 3116 in the MLB_CNBCRx register for the start address or bits 150 for the end address). The remaining higher 5 bits (1 0000) are written in one of the base address registers, depending on the transfer mode. For example, if using synchronous mode, write bits 3116 = 0x0010 for receive and bits 150 for transmit in the MLB_SBCR register.

MLB DMA Group Priority

The MLB module has up to 31 DMA channels. When multiple channels have data ready, the channel arbitrates using a rotating round robin method (first arbitration stage). The winning channel requests the DMA bus arbiter to get control of the peripheral DMA bus (second arbitration stage). For the I/O processor, the 31 DMA channels are considered as a group and one arbitration request. For more information, see Peripheral DMA Arbitration on page 3-36.

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Media Local Bus

Ping-Pong DMA Logical channels operate in core mode when the channel mode select MDS bits in the MLB_CECRx register are configured accordingly (default). When MLB is configured in ping-pong mode, the MLB_CCBCRx and MLB_CNBCRx registers are used to configure and monitor the system memory current buffer (ping) and next buffer (pong) respectively. Ping-pong DMA is available for all data types. When receiving and transmitting asynchronous and control packet data, the current buffer and next buffer are independent internal memory buffers. This allows hardware to support the ping-pong buffering. Each buffer is addressed using two 16-bit address fields in the MLB_CNBCRx and MLB_CCBCRx registers as described below. Current buffer address (BCA bits, CCBCRx register) start of current buffer in internal memory. Current buffer final address (BFA bits, CCBCRx register) end of current buffer in internal memory. Next buffer start address (BSA bits, CNBCRx register) start of next buffer in internal memory. Next buffer end address (BEA bits, CNBCRx register) end of next buffer in internal memory. For ping-pong DMA mode, transmit and receive for all data types are handled in the following manner. At the start of buffer processing, the beginning of the next buffer becomes the beginning of the current buffer, as the BSA bits from the MLB_CNBCRx register are loaded into the BCA bit field of the MLB_CCBCRx register. Additionally, the end of the next buffer

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Data Transfer

becomes the end of the current buffer, as the BEA bit field from the MLB_CNBCRx register is loaded into the BFA bit field of the MLB_CCBCRx register. A current buffer start interrupt is generated (STS bit in the MLB_CSCRx register), which informs the software that hardware has updated the MLB_CCBCRn register, cleared the local channel RDY bit, and is available to accept the next buffer. Software may then prepare the next buffer by writing: BSA, BEA, and RDY bits. During the processing of the current buffer, BCA bits continue to mark which quadlet of data or packet is currently being processed. A current buffer done interrupt is generated when the last quadlet in the current buffer has been successfully transmitted/received. The current buffer and the next buffer can be configured for either multi-packet or single-packet buffering, when receiving and transmitting asynchronous and control packet data. Multi-packet buffering allows the system to reduce the interrupt load at the expense of larger DMA buffers. Single-packet buffering allows DMA buffer size to be reduced at the expense of increasing the interrupt rate. For more information, see Programming Model on page 9-20. Circular Buffer DMA Logical channels operate in circular buffer DMA mode when the channel mode select bits in the MLB_CECRx register are configured accordingly. In contrast to ping-pong buffering, circular buffering uses a single, circular memory buffer to process channel data.

Circular buffer DMA is available for synchronous channels only.

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Media Local Bus

For circular buffer mode, synchronous data is handled in the following manner: Before buffer processing can begin, the BSA bits in the MLB_CNBCRx register and the BEA bits in the MLB_CNBCRx register should be programmed with the beginning and the ending address of the circular buffer. Set the RDY bit in the MLB_CSCRx register to initiate buffer processing. At the start of buffer processing, the beginning address of the circular buffer (BSA) is loaded into BCA field of the MLB_CCBCRx register. Additionally, the ending address of the circular buffer (BEA bits) is loaded into the BFA bit field of the MLB_CCBCRx register. During the processing of the circular buffer, the BCA bits are updated to indicate which quadlet of the synchronous data is currently being processed. Once the end of the buffer is reached and BCA = BFA, the BCA field is reloaded to point to the beginning address of the circular buffer (BSA). Unlike in ping-pong DMA, the RDY bit remains set during the processing of the circular buffer DMA. Software must clear this bit to halt buffer processing. For more information, see Programming Model on page 9-20.

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Interrupts

Interrupts
Table 9-3 provides an overview of MLB interrupts. Table 9-3. Overview of MLB Interrupts
Default Programmable Sources Interrupt MLBI not connected by default MLB Lock/Unlock Network Lock/Unlock Sub command Reset Core buffer service DMA start DMA complete Break detect Lost frame sync Buffer error RX protocol error Masking Unmask MLB_SMCR Service RW1C to MLB_SSCR + RTI instruction

Unmask MLB_CECRx

RW1C to MLB_CSCRx + RTI instruction

Sources
The MLB module generates a total of 38 local interrupts which are grouped into seven system status and 31 logical channel status interrupts. All 38 signals are logically ORed into 1 MLB interrupt signal which must be routed into a programmable interrupt. The MLB interface generates interrupts as described in the following sections. Core Buffer Service Request When I/O mode is enabled and the processor core reads from the receive buffer (MLB_CCBCRx register) or writes to the transmit buffer (MLB_CNBCRx register) an interrupt is generated when the local channel buffer is not empty or not full respectively.

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Threshold Transmit Request In I/O mode the logical channel interrupt requests are generated when the number of valid quadlets in the local channel buffer falls below the threshold for transmit channels or: valid quadlets MLB_LCBCRX (programmed using the TH bits). Threshold Receive Request For I/O mode the logical channel interrupt requests are generated when the number of free quadlets in the local channel buffer falls below the threshold for receive channels or: free quadlets MLB_LCBCRx (programmed using the TH bits). DMA Complete When ping-pong or circular mode is enabled the DMA complete is generated after the count is zero. Receive Channel Errors A receive channel detects errors such as: Receiver Break, Asynchronous Break, Control Break Receiver Protocol Error

Masking
The MLBI signal is not routed by default to programmable interrupts. To service the MLBI, unmask (set = 1) any programmable interrupt bit in the IMASK/ LIRPTL register.

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Programming Model

The system status interrupts are unmasked by setting the corresponding bits in the MLB_SMCR register. The logical channel status interrupts are unmasked by setting the corresponding bits in the MLB_CECR30-0 register. To enable core buffer service request the MDS bit must be configured for I/O mode. To enable DMA interrupts the MDS bit must be configured for ping-pong or circular buffering mode.

Service
For system status interrupts RW1C to the corresponding bit in the MLB_SSCR register (except for the SSRE bit which is cleared by hardware). The global interrupt channel status register (MLB_CICR) reflects the global status of 31 logic channels together. Reading identifies the logical channel. RW1C the corresponding status bit in the local channel register (MLB_CSCRx) which also clear its MLB_CICR bits.

Programming Model
The following sections provide procedures that are helpful when programming media local bus interface.

I/O Interrupt Mode

To configure the MLB interface for I/O mode using interrupts, use the following procedure. 1. Reset the MLB device. 2. Program the appropriate bits in the PICRx register to generate MLB interrupt.

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Media Local Bus

3. Unmask the appropriate bits in the MLB_SSCR register in order to monitor the MLB network. 4. Configure the MLB control register (MLB_DCCR) with the appropriate settings and enable the MediaLB device. 5. Check for MLB lock using the status bit in the MLB_SSCR register using polling or interrupt. 6. Configure the MLB_LCBCRx register for channel buffer threshold, depth and start address. 7. Configure the logical channel using the MLB_CECRx register for I/O mode, transfer direction, channel type, channel address and interrupt generation. For a transmit, a transmit service request, (STS bit 1 in the MLB_CSCRx register) an interrupt is generated when the local channel buffer can accept data. Within the ISR, check if this status bit is set. If set, write the data into transmit data buffer (MLB_CNBCRx). For a receive, a receive service request, (STS bit 2 in the MLB_CSCRx register) an interrupt is generated when the local channel buffer has data to be read. Within the ISR, check if this status bit is set. If set, read the data from the receive data buffer (MLB_CCBCRx). 8. Clear all interrupts by writing 0x0000FFFF to the MLB_CSCRx register.

DMA Modes
MLB channels can be configured for circular buffer DMA mode by programming the channel mode select bits (MLB_CECRx register, bits 2526 = 01) for synchronous channels only. In contrast to DMA mode with ping-pong buffering, circular buffering uses a single, circular memory buffer to process channel data.

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Programming Model

To configure a ping-pong or circular buffered DMA, use the following procedure. 1. Reset the MLB device. 2. Program the appropriate bits in the PICRx register to generate MLB interrupt. 3. Unmask the appropriate bits in the MLB_SSCR register in order to monitor the MLB network. 4. Configure the MLB control register (MLB_DCCR) with the appropriate settings and enable the MediaLB device. 5. Configure the base address register (MLB_SBCR, MLB_ABCR or MLB_CBCR) based on the data type configured for the logical channel. 6. Check for MLB lock using the status bit in the MLB_SSCR register using polling or interrupt. 7. Configure the MLB_LCBCRx register for channel buffer threshold, depth and start address. 8. Configure the logical channel using the MLB_CECRx register for ping-pong or circular buffer DMA mode, transfer direction, channel type, channel address and also to generate appropriate interrupts. 9. Configure the MLB_CNBCRx register with the buffer start and end address. 10.Set the RDY bit in the MLB_CSCRx register to start the DMA. Hardware automatically the clears the RDY bit ping-pong DMA but not for circular buffer DMA. Therefore, for circular buffer DMA, this bit should be cleared manually by the software to stop buffer processing.

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11.An interrupt is generated depending on the bit unmasked in the MLB_CECRx register. Within the ISR check that the appropriate status bit (in the MLB_CSCRx register) is set. 12.Clear all interrupts by writing 0x0000FFFF to the MLB_CSCRx register.

Debug Features
The following sections provide information to assist in MediaLB debug.

Loop-Back Test Mode

Loop-back test mode is used for debug operations and is enabled by setting the LBM bit in the MLB_DCCR register. This mode provides basic testing capabilities for the MediaLB pads, physical layer, link layer, channel protocol and the local channel buffer by enabling a single receive channel and a single transmit channel. When loop-back test mode is enabled, a data path is enabled which allows receive data from even channel N to be sent out as transmit data on channel N + 1, where N = {0, 2, 4 30}.

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Debug Features

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10 DIGITAL APPLICATION/ DIGITAL PERIPHERAL INTERFACES

The digital application interface (DAI) and the digital peripheral interface (DPI) are comprised of a groups of peripherals and their respective signal routing units (SRU and SRU2). The inputs and outputs of the peripherals are not directly connected to external pins. Rather, the SRUs connect the peripherals to a set of pins and to each other, based on a set of configuration registers. This allows the peripherals to be interconnected to suit a wide variety of systems. It also allows the SHARC processors to include an arbitrary number and variety of peripherals while retaining high levels of compatibility without increasing pin count. The routing unit specifications are listed in Table 10-1. Table 10-1. Routing Unit Specifications
Feature Pin Buffers Number Input Output Open-drain Polarity Change High Impedance Programmable Pull-up I/O Level Status Register 20 Yes Yes Yes Yes Yes No Yes 14 Yes Yes Yes No Yes No Yes DAI DPI

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SRU Features

Table 10-1. Routing Unit Specifications (Contd)

Feature Local Memory Max Clock Operation DAI No fPCLK/4 DPI No fPCLK/4

SRU Features
In a typical processor, static (multiplexed) pins are assigned to specific peripherals. When certain peripherals are not required for an application, these pins are unnecessary and expensive because they may need to be defined as high/low to prevent any illegal conditions. The signal routing unit on the SHARC processors addresses this by controlling a number of general-purpose pins which can be assigned flexibly (a virtual connectivity between peripherals) depending on system requirements. This virtual connectivity includes pin buffers and routing logic (multiplexer) and offers the following advantages. Flexibility connections can be made via software and during runtime, no hard-wiring is required. Control is provided via memory-mapped control registers organized in groups. This is useful for interconnects (for example clocks, frame sync, data). At reset a default routing scheme is already programmed including boot enabled peripherals. Connectivity can be internally between peripherals, externally between pin buffers, or a mix of both. Status of the pin buffers can be programmed for conditional execution or interrupts. Some pin buffers allow control of signal polarity changes.

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For shared bus systems such as SPI or TWI, open drain configuration possible. No fan-out limitation, a peripheral/pin buffer output can be routed to multiple peripheral/pin buffer inputs. Two independent routing systems are available the DAI and the DPI. Signals cant be interconnected between both routings units with exception of the precision clock generator (PCG). are Analog Devices offers macros that codeincluded with thethe SRU. VisualDSP++ tools, greatly easing development in

Register Overview
The SRU for the DAI contains six register sets that are associated with the DAI groups. Clock Routing Registers (SRU_CLKx). Associated with Group A, routes clock signals. Serial Data Routing Registers (SRU_DATx). Associated with group B, routes data. Frame Sync Routing Control Registers (SRU_FSx). Associated with group C, routes frame syncs or word clocks to the serial ports, the SRC, the S/PDIF, and the IDP. Pin Signal Assignment Registers (SRU_PINx). Associated with group D, routes physical pins (connected to a bonded pad). Miscellaneous Signal Routing Registers (SRU_MISCx). Associated with group E, allows programs to route to the DAI interrupt latch, PBEN input routing, or input signal inversion. DAI Pin Buffer Enable Registers (SRU_PBENx). Associated with group F, Activate the drive buffer for each of the 20 DAI pins.

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Clocking

DAI Shift Registers Clock (SRU_CLK_SHREG). Associated with group H, routes all shift register clock signals (ADSP-2147x). DAI Shift Registers Data (SRU_DAT_SHREG). Associated with group I, routes all shift register serial data signals (ADSP-2147x). The SRU2 for DPI contains three register sets associated with the DPI groups. Miscellaneous Signal Routing Registers (SRU2_INPUTx). Associated with group A, used to route the 14 external pin signals to the inputs of the other peripherals. Pin Assignment Signal Routing (SRU2_PINx). Associated with group B routes pin output signals to the DPI pins. Pin Enable Signal Routing (SRU2_PBENx). Associated with group C used to specify whether each DPI pin is used as an output or an input by setting the source for the pin buffer enable. The DAI/DPI registers are unique in that they work as groups to control other peripheral functions. The register groups and routings are described in detail in DAI/DPI Group Routing on page 10-17, DAI Signal Routing Unit Registers on page A-123 and DPI Signal Routing Unit Registers on page A-207.

Clocking
The fundamental timing clock of the DAI/DPI modules is peripheral clock/4 (PCLK/4). The clock to the DAI may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

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Digital Application/ Digital Peripheral Interfaces

Functional Description
Figure 10-1 and Figure 10-2 shows how the DAI/DPI pin buffers are connected via the SRU/SRU2. This allows for very flexible signal routing. The DAI/DPI are comprised of four primary blocks: Peripherals (A/B/C) associated with DAI/DPI Signal Routing Units (SRU, SRU2) DAI/DPI I/O pin buffers Miscellaneous buffers The peripherals shown in Figure 10-1 and Figure 10-2 can have up to three connections (if master or slave capable); one acts as a signal input, one as a signal output and the 3rd as an output enable. The SRUs are based on a group of multiplexers which are controlled by registers to establish the desired interconnects. The DAI/DPI pin buffers have three signals which are used for input/output to/from off-chip and the 3rd for output enable. The miscellaneous buffers have an input and an output and are used for group interconnection.

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Functional Description

PERIPHERAL CORE BUS

Input DAI PERIPHERAL A

SRU
Output

Output Enable Input Invert (optional) Enable DAI PIN BUFFER Input

OFF CHIP

DAI PERIPHERAL B

Output DAI INTERRUPT LATCH

Input

Input Invert (optional)

DAI PERIPHERAL C

Output Output Enable MISCELLANEOUS DAI BUFFER

Figure 10-1. DAI Functional Block Diagram

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Digital Application/ Digital Peripheral Interfaces

PERIPHERAL CORE BUS

Input DPI PERIPHERAL A

SRU2
Output Input

Output Enable

OFF CHIP

Enable DPI PIN BUFFER Input DPI PERIPHERAL B

Output

DPI INTERRUPT LATCH

Input

Input

DPI PERIPHERAL C

Output Output Enable MISCELLANEOUS DPI BUFFER

Figure 10-2. DPI Functional Block Diagram Note that the figures are simplified representation of a DAI and DPI system. In a real representation, the SRU and DAI would show several types of data being routed from several sources including the following. Serial ports (SPORT) Precision clock generators (PCG) Input data port (IDP)

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Functional Description

Asynchronous sample rate converters (SRC) S/PDIF transmitter S/PDIF receiver Shift register DAI interrupts (miscellaneous) Similarly, the DPI pin buffers are connected via the SRU2. The DPI makes use of several types of data from a large variety of sources, including: Peripheral timers Serial Peripheral Interfaces (SPI) Precision clock generators (PCG)

Universal asynchronous Rx/Tx ports (UART) Two wire interface (TWI)

GPIO flags (external port) DPI interrupts (miscellaneous) clock Note thattothe precisionand/orgenerator (units C/D) can be assigned access DAI DPI pins.

DAI/DPI Signal Naming Conventions

The peripherals associated with the DAI/DPI do not have any dedicated I/O pins for off-chip communication. Instead, the I/O pin is only accessible in the chip internally and is known as an internal node. Every internal node of a DAI peripheral (input or output) is given a unique mnemonic. The convention is to begin the name with an identifier for the peripheral that the signal is coming to/from followed by the signals function. A

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Digital Application/ Digital Peripheral Interfaces

number is included if the DAI contains more than one peripheral type (for example, serial ports), or if the peripheral has more than one signal that performs this function (for example, IDP channels). The mnemonic always ends with _I if the signal is an input, or with _O if the signal is an output (Figure 10-3).
SIGNAL FUNCTION BUFFER NUMBER

SPORT0_CLK_O
PERIPHERAL DIRECTION RELATIVE TO SIGNALS PERIPHERAL

DAI_PB11_I
DAI BUFFER DIRECTION RELATIVE TO SIGNALS BUFFER

Figure 10-3. Example SRU Mnemonics

I/O Pin Buffers

Within the context of the SRU, physical connections to the DAI pins are replaced by a logical interface known as a pin buffer. This is a three terminal active device capable of sourcing/sinking output current when its driver is enabled, and passing external input signals when disabled. Each pin has an input, an output, and an enable as shown in Figure 10-4. The inputs and the outputs are defined with respect to the pin, similar to a peripheral device. This is consistent with the SRU naming convention. Pin Buffer Signals The pin buffer is based on three signals shown in Figure 10-4 described in the following sections.
Pin Buffer Input Signal

A pin buffer input (DAI_PBxx_I, DPI_PBxx_I) is driven as an output from the processor when the pin buffer enable is set (=1). Each physical pin (connected to a bonded pad) may be connected via the SRU to any of the outputs of the DAI/DPI peripherals, based on the bit field values. The ADSP-214xx SHARC Processor Hardware Reference 10-9

Functional Description

DAI_PBxx_O

INTERFACE TO SRU

DAI_PBxx_I

IN

PIN BUFFER
ENABLE

OUT

EXTERNAL DAI PIN BUFFER

PBENxx_I

Figure 10-4. Pin Buffer Example SRU also may be used to route signals that control the pins in other ways. Many signals may be configured for use as control signals.
Pin Buffer Enable Signal

When a pin buffer enable (PBENxx_I) is set (=1), the signal present at the corresponding pin buffer input (PBxx_I) is driven off-chip as an output. When a pin buffer enable is cleared (=0), the signal present at the corresponding pin buffer input is ignored. The pin enable control registers activate the drive buffer for each of the DAI/DPI pins. When the pins are not enabled (driven), they can be used as inputs. There are two options to control the pin buffer enable signal; setting the level high for a static solution, or connecting the dedicated peripherals pin buffer output enable signal to its pin buffer, which automatically enables the pin buffer. Pin Buffer Functions Pin buffers may be configured as inputs, outputs or as open drain as described in the following sections.

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Pin Buffers as Signal Input

When the DAI pin is to be used only as an input, connect the corresponding pin buffer enable to logic low as shown in Figure 10-5. This disables the buffer amplifier and allows an off-chip source to drive the value present on the DAI pin and at the pin buffer output. When the pin buffer enable (PBENxx_I) is cleared (= 0), the pin buffer output (PBxx_O) is the signal driven onto the DAI pin by an external source, and the pin buffer input (PBxx_I) is not used.
PIN BUFFER OUTPUT

DAI_PBxx_O

INTERFACE TO SRU

PIN BUFFER INPUT (NOT USED)

DAI_PBxx_I

IN

PIN BUFFER
PIN ENABLE

EXTERNAL DAI PIN BUFFER OUT

PIN BUFFER ENABLE (= LOW)

PBENxx_I

Figure 10-5. Pin Buffer as Input DAI/DPI Whether programmed as inputtoor output, ainternally. buffer input always routes the same signal an output
Pin Buffers As Signal Output

In a typical embedded system, most pins are designated as either inputs or outputs when the circuit is designed, even though they may have the ability to be used in either direction. Each of the DAI pins can be used as either an output or an input. Although the direction of a DAI pin is set

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Functional Description

simply by writing to a memory-mapped register, most often the pins direction is dictated by the designated use of that pin. For example, if the DAI pin were to be hard wired to only the input of another interconnected circuit, it would not make sense for the corresponding pin buffer to be configured as an input. Input pins are commonly tied to logic high or logic low to set the input to a fixed value. Similarly, setting the direction of a DAI pin at system startup by tying the pin buffer enable to a fixed value (either logic high or logic low) is often the simplest and cleanest way to configure the SRU. When the DAI pin is to be used only as an output, connect the corresponding pin buffer enable to logic high as shown in Figure 10-6. This enables the buffer amplifier to operate as a current source and to drive the value present at the pin buffer input onto the DAI pin and off-chip. When the pin buffer enable (PBENxx_I) is set (=1), the pin buffer output (PBxx_O) is the same signal as the pin buffer input (PBxx_I), and this signal is driven as an output.
PIN BUFFER OUTPUT DAI_PBxx_O

INTERFACE TO SRU

PIN BUFFER INPUT

DAI_PBxx_I
IN

PIN BUFFER
PIN ENABLE

EXTERNAL DAI PIN BUFFER

OUT

VDDEXT

PBENxx_I PIN BUFFER ENABLE (= HIGH)

Figure 10-6. Pin Buffer as Output

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Digital Application/ Digital Peripheral Interfaces

Pin Buffers as Open Drain

Certain peripherals (for example the TWI or SPI) may be required to run in multiprocessing environments. These peripherals will need their pin drivers to work in open drain mode for transmit and receive operation as shown in Figure 10-7. The signal input of the assigned pin buffer is tied low. The peripherals data output signal is connected to the PBEN signal. In open drain mode, if PBEN = low, the level on the pin depends on the bus activities. If PBEN = high, the driver is conducting (input always low level) and ties the bus level low. Note that for the SPI the ODP bit in the SPICTL register must be enabled.
PIN BUFFER OUTPUT DAI_PBxx_O

INTERFACE TO SRU

PIN BUFFER INPUT (TIED LOW)

DAI_PBxx_I

IN

PIN BUFFER
PIN ENABLE

EXTERNAL DAI PIN BUFFER OUT

PIN BUFFER ENABLE TWI_DATA_PBEN_O

PBENxx_I

Figure 10-7. Pin Buffer as Open Drain

DAI/DPI Pin Buffer Status

The signal levels on the DAI/DPI pins can be read with the DAI/DPI_PIN_STAT registers. This allows conditions like for example:
ustat2=dm(DAI_PIN_STAT); bit tst ustat2 DAI_PB10; if TF jump DAI_PB10_high;

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Functional Description

DAI/DPI Peripherals
There are two categories of peripherals associated with the DAI and DPI. These are described in the following sections.
SPORT0_CLK_I SPORT0_CLK_O SPORT0_CLK_PBEN_O TIMER0_I TIMER0_O TIMER0_PBEN_O SPORT0_FS_I SPORT0_FS_O SPORT0_FS_PBEN_O SPORT0_DA_I SPORT0_DA_O SPORT0_DA_PBEN_O SPORT0_DB_I SPORT0_DB_O SPORT0_DB_PBEN_O

Interface to SRU

Figure 10-8. SRU Connections for Timer and SPORT0 Output Signals With Pin Buffer Enable Control Many peripherals within the DAI/DPI that have bidirectional pins generate a corresponding pin enable signal. Typically, the settings within a peripherals control registers determine if a bidirectional pin is an input or an output, and is then driven accordingly. Though most peripherals are capable of operating bi-directionally, it is not required that all of a peripherals _I and _O signals should be connected to the pin buffer. If the system design only uses a signal in one direction, it is simpler just to connect the pin buffer accordingly.

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Digital Application/ Digital Peripheral Interfaces

enables must be routed to their pin All available pin buffer outputcases where data streaming connecbuffer input enable signals in tions are used. This will guarantee timing requirements (for example a gated clock for the SPI). Output Signals Without Pin Buffer Enable Control Some peripherals have signal outputs without automated pin buffer control enable as shown in Figure 10-9 (PDAP_STRB_O, MISCx_O, BLK_START_O). The operation of these peripherals is simplified as the routing to a DAI/DPI pin buffer enable input requires a static high from the SRU. In order to disable the pin buffer output, software must clear the pin buffer enable input accordingly.

SRC0_CLK_IP_I SRC0_FS_IP_I SRC0_DAT_IP_I SRC0_TDM_IP_O

Interface to SRU
SRC0_CLK_OP_I SRC0_FS_OP_I SRC0_TDM_OP_I SRC0_DAT_IP_O

Figure 10-9. SRU Connections (no PBEN Signals)

Signal Routing Units (SRUs)

The following sections provide more detail specific to the SRUs.

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Functional Description

Signal Routing Matrix by Groups The SRU can be likened to a set of patch bays, which contains a bank of inputs and a bank of outputs. For each input (destination), there is a set of permissible output (source) options. Outputs can feed to any number of inputs in parallel, but every input must be patched to exactly one valid output source. Together, the set of inputs and outputs are called a group. The signals inputs and outputs that comprise each group all serve similar purposes. They are compatible such that almost any output-to-input patch makes functional sense. With the grouping, the multiplexing scheme becomes highly efficient since it wouldnt make sense (for example) to route a frame sync signal to a data signal. The SRU for the DAI contains seven groups that are named sequentially A through F. Each group routes a unique set of signals with a specific purpose as shown below. Group A routes clock signals Group B routes serial data signals Group C routes frame sync signals Group D routes pin signals Group E routes miscellaneous signals Group F routes pin output enable signals Group H routes all shift register clock signals (ADSP-2147x only) Group I routes all shift register data signals (ADSP-2147x only) Together, the SRUs seven groups include all of the inputs and outputs of the DAI peripherals, a number of additional signals from the core, and all of the connections to the DAI pins. The SRU2 for DPI contains three groups that are named sequentially A through C. Each group routes various signals with a specific purpose:

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Digital Application/ Digital Peripheral Interfaces

Group A routes miscellaneous signals Group B routes pin output signals Group C routes pin output enable signals the DAI module, all types of functionality, Unlike the SRU inare merged into the same group in the DPI such as clock and data, SRU2. Note that it is not possible to connect a signal in one group directly to signal in a different group (analogous to wiring from one patch bay to another). However, group D (DAI) or group B (DPI) is largely devoted to routing in this vein. DAI/DPI Group Routing Each group has a unique encoding for its associated output signals and a set of configuration registers. For example, DAI group A is used to route clock signals. The memory-mapped registers, SRU_CLKx, contain bit fields corresponding to the clock inputs of various peripherals. The values written to these bit fields specify a signal source that is an output from another peripheral. All of the possible encodings represent sources that are clock signals (or at least could be clock signals in some systems). Figure 10-10 diagrams the input signals that are controlled by the group A register, SRU_CLKx. All bit fields in the SRU configuration registers correspond to inputs. The value written to the bit field specifies the signal source. This value is also an output from some other component within the SRU. The SRU is similar to a set of patch bays. Each bay routes a distinct set of outputs to compatible inputs. These connections are implemented as a set of memory-mapped registers with a bit field for each input. The outputs are implemented as a set of bit encodings. Conceptually, a patch cord is used to connect an output to an input. In the SRU, a bit pattern that is associated with a signal output (shown in Figure 10-10) is written to a bit field corresponding to a signal input.

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Functional Description

The same encoding can be written to any number of bit fields in the same group. It is not possible to run out of patch points for an output signal.
SOURCE SIGNALS SPORT5_CLK_I DAI_PB01_O DAI_PB02_O DAI_PB03_O DAI_PB04_O DAI_PB05_O DAI_PB06_O DAI_PB07_O DAI_PB08_O DAI_PB09_O DAI_PB10_O DAI_PB12_O DAI_PB13_O DAI_PB14_O DAI_PB15_O DAI_PB16_O DAI_PB17_O DAI_PB18_O DAI_PB19_O DAI_PB20_O SPORT0_CLK_O SPORT1_CLK_O SPORT2_CLK_O SPORT3_CLK_O SPORT4_CLK_O SPORT5_CLK_O DESTINATION SIGNALS SPORT4_CLK_I SPORT3_CLK_I

SRU_CLK MUX

SRU_CLK MUX

SRU_CLK MUX

LOGIC LOW (0) LOGIC HIGH (1) 4 0 29 3 0 28 2 0 27

5 1 0 26 0 0 25 4 0 24 3 0 23 2 0 22

5 1 0 21 0 0 20 4 1 3 1 2 0

5 1 0 16 0 0 15

19 18

17

SPORT5_CLK_I Select Field

SPORT4_CLK_I Select Field

SPORT3_CLK_I Select Field

Figure 10-10. Example DAI SRU Group A Multiplexing (SRU_CLKx)

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Just as group A routes clock signals, each of the other groups route a collection of compatible signals. Group B routes serial data streams while group C routes frame sync signals. Note that all of the groups have an encoding that allows a signal to flow from a pin output to the input being specified by the bit field. Group D routes signals to pins so that they may be driven off-chip (required to route a signal to the pin input). Group F routes signals to the pin enables, and the value of these signals determines if a DAI pin is used as an output or an input. One pins input can be patched to another pins output, allowing board-level routing under software control. Rules for SRU Connections There are two rules which apply to all routing: 1. One source (output node) can drive different destinations (input nodes). 2. One destination (input node) can only be assigned to one source (output node). As an example from Figure 10-10:
DAI_PB01_O DAI_PB01_O

is routed to SPORT5_CLK_I is routed to SPORT4_CLK_I is routed to SPORT3_CLK_I

SPORT4_CLK_O

Inputs may only be connected to outputs.

Miscellaneous Buffers and Functions
The SRU group E provides miscellaneous buffers used for group interconnect which is explained below.

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Functional Description

DAI group E or DPI group C connections are slightly different from the others in that the inputs and outputs being routed vary considerably in function. This group routes control signals and provides a means of connecting signals between groups. For the DAI (Figure 10-11, Table 10-2), the MISCAx_I signals appear as inputs in group E (also connected to the DAI interrupt logic), but do not directly feed any peripheral. Rather, the MISCAx_O signals reappear as outputs in group F. Table 10-2. DAI MISCAx SRU Signal Connections
MISCA Source DAI Connection Group E MISCA50_O Group F MISCA Destination MISCA50_I

SOURCE SIGNALS DAI_PB04_O

DESTINATION SIGNALS MISCA3_I

SOURCE SIGNALS MISCA3_O

DESTINATION SIGNALS DAI_PBENxx_I

32:1 MUX

MISCA3

64:1 MUX

DAI_INT_31

Group E MISCA3_I 5-Bit Select Field

Group F DAI_PBENxx_I 6-Bit Select Field

Figure 10-11. Miscellaneous DAI Connections For the DPI (Figure 10-12, Table 10-3), the MISCBx_I signals appear as inputs in group A (also connected to DPI interrupt logic), but do not directly feed any peripheral. Rather, the MISCBx_O signals reappear as outputs in group C.

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Additional connections among groups provide a great amount of utility. Since the output groups F (DAI) and C (DPI) dictate pin direction, these few signal paths enable a number of possible uses and connections for the DAI/DPI pins. Other examples include: A pin input can be patched to another pins enable, allowing an off-chip signal to gate an output from the processor. Any of the DAI pins can be used as interrupt sources or generalpurpose I/O (GPIO) signals. Table 10-3. DPI MISCBx SRU2 Signal Connections
MISCB Source DAI Connection Group A MISCB80_O Group C MISCB Destination MISCB80_I

SOURCE SIGNALS DPI_PB04_O

DESTINATION SIGNALS MISCB2_I

SOURCE SIGNALS MISCB2_O

DESTINATION SIGNALS DPI_PBENxx_I

32:1 MUX

MISCB2

64:1 MUX

DPI_INT_07

Group A MISCB2_I 5-Bit Select Field

Group C DPI_PBENxx_I 6-Bit Select Field

Figure 10-12. Miscellaneous DPI Connections In summary the SRU enables many possible functional changes, both within the processor as well as externally. Used creatively, it allows system

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Functional Description

designers to radically change functionality at runtime, and to potentially reuse circuit boards across many products.

DAI/DPI Routing Capabilities

This section describes the routing options to aid in designing a system using the DAI/DPI. In Table 10-4 and Table 10-5 the left column represents the source signals, the right column the destination signals, and the central column the group to which the signal belongs. A valid connection is built by connecting a source to destination signal within a group. For example in the DAI group A the source signal SPORT2_CLK_O needs to be connected to the sample rate converter0 destination signal SRC0_CLK_I. In practice a macro is provided and forms the style SRU(source_O, destination_I) so the example appears as: SRU(SPORT2_CLK_O, SRC0_CLK_I). The routing registers are described in DAI Signal Routing Unit Registers on page A-123 and DPI Signal Routing Unit Registers on page A-207. DAI Routing Capabilities Table 10-4 provides an overview of the different routing capabilities for the DAI unit. For information on an individual peripherals routing, see the SRU Programming section of that peripherals chapter.

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Table 10-4. DAI Routing Capabilities

Source Signals Output (xxxx_O) SPORT50 PCG A, B S/PDIF Rx (clock, TDM clock) DAI Group Destination Signals Input (xxxx_I) SPORT70 SRC30 IDP70 PCG AD (Ext. clock, Ext. FS) S/PDIF-Tx (clock, HF Clock) SPORT70 A, B SRC30 (data, TDM data) IDP70 S/PDIF Tx/Rx SPORT70 SRC30 IDP70 DAI Pin Buffer 201 Options: DAI Pin Buffer 2019 Polarity Change

DAI Pin Buffer201 AClocks Logic level high Logic level low

SPORT70 A, B SRC30 (data, TDM data) S/PDIF Tx/Rx SPORT50 PCG A, B S/PDIF Rx SPORT70 (clock, FS, TDV, data) S/PDIF Rx (clock, TDM clock, FS, data) S/PDIF Tx (data, block start) PDAP (strobe) PCG C, D (clock, FS) (also in DPI) SPORT50 (FS) PCG A (clock) PCG B (clock, FS) S/PDIF Tx (block start) SPORT70 (clock, FS, data, TDV) MISCA50 ADSP-2147x Only SR_SCLK, SR_LAT (dedicated pins) SPORT70A, B (clock, FS) PCGAB (clock, FS) SR_SDI (dedicated pin) Logic level high Logic level low

BData

CFrame Sync

DPin Buffer Inputs

EMiscellaneous DAI Interrupt 3122 Signals MISCA50 Options: MISCA54 Polarity Change FPin Buffer Enable DAI Pin Buffer Enable 20-1

DAI Pin Buffer 81 HSR Clocks Logic level high Logic level low ISR Data

SR_SCLK SR_LAT SR_SDI

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Functional Description

DPI Routing Capabilities Table 10-5 provides an overview about the different routing capabilities for the DPI unit. For information on an individual peripherals routing, see the SRU Programming section of that peripherals chapter. Table 10-5. DPI Routing Capabilities
Source Signals Output (xxxx_O) TIMER10 UART0 Tx Data DPI Pin Buffer 141 Logic level high Logic level low DPI Group AMiscellaneous Signals Destination Signals Input (xxxx_I) TIMER10 UART0 Rx data SPIB (data, clock, control) FLAG154 TWI (clock, FS) MISCB80 DPI Interrupt 135

TIMER10 UART0 Tx data SPI (data, clock, control) FLAG/PWM154 PCG (C, D) (clock, FS) (Also DAI) TIMER10 UART0 Tx data SPIB (data, clock, control) FLAG154 TWI (clock, FS) MISCB80 Logic level high Logic level low

BPin Buffer Input DPI Pin Buffer141

CPin Buffer Enable

DPI Pin Buffer Enable141

DAI Default Routing

When the processor comes out of reset, the SPORT junctions are bi-directional to the DAI pin buffers (Figure 10-13, Figure 10-14). This allows systems to use the SPORTs as either master or slave (without changing the routing scheme). Therefore, programs only need to use the SPORT control register settings to configure master or slave operation. Note that all DAI inputs which are not routed by default are tied to signal low.

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IDP7-0_DAT_I

DIR_I DIT_DAT_I

SRC_3-0_DAT_IP_I SRC_3-0_TDM_OP_I

SPORT0_DA_I SPORT0_DA_O SPORT0_PBEN_O SPORT0_DB_I SPORT0_DB_O SPORT0_PBEN_O SPORT0_CLK_I SPORT0_CLK_O SPORT0_PBEN_O SPORT0_FS_I SPORT0_FS_O SPORT0_PBEN_O DAI Pin04 DAI Pin03 DAI Pin02 DAI Pin01

SPORT1_DA_I SPORT1_DA_O SPORT1_PBEN_O SPORT1_DB_I SPORT1_DB_O SPORT1_PBEN_O SPORT1_CLK_I SPORT1_CLK_O SPORT1_PBEN_O SPORT1_FS_I SPORT1_FS_O SPORT1_PBEN_O DAI Pin08 DAI Pin07 DAI Pin06 DAI Pin05

Figure 10-13. DAI Default Routing

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Functional Description

SPORT2_DA_I SPORT2_DA_O SPORT2_PBEN_O SPORT2_DB_I SPORT2_DB_O SPORT2_PBEN_O SPORT2_CLK_I SPORT2_CLK_O SPORT2_PBEN_O SPORT2_FS_I SPORT2_FS_O SPORT2_PBEN_O DAI Pin10 DAI Pin09

SPORT4_DA_I SPORT4_DA_O SPORT4_PBEN_O SPORT4_DB_I SPORT4_DB_O SPORT4_PBEN_O SPORT4_CLK_I SPORT4_CLK_O SPORT4_PBEN_O SPORT4_FS_I SPORT4_FS_O SPORT4_PBEN_O DAI Pin16 DAI Pin15

SPORT3_CLK_I SPORT3_CLK_O SPORT3_PBEN_O SPORT3_FS_I SPORT3_FS_O SPORT3_PBEN_O SPORT3_DA_I SPORT3_DA_O SPORT3_PBEN_O SPORT3_DB_I SPORT3_DB_O SPORT3_PBEN_O DAI Pin12 DAI Pin11 DAI Pin14 DAI Pin13

SPORT5_CLK_I SPORT5_CLK_O SPORT5_PBEN_O SPORT5_FS_I SPORT5_FS_O SPORT5_PBEN_O SPORT5_DA_I SPORT5_DA_O SPORT5_PBEN_O SPORT5_DB_I SPORT5_DB_O SPORT5_PBEN_O DAI Pin18 DAI Pin17 DAI Pin20 DAI Pin19

Figure 10-14. DAI Default Routing (Cont) input buffers which are default are All DAI all DAI pin buffer enablenot routed bydriven low. driven low and signals are

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DPI Default Routing

When the processor comes out of reset, some default routing is established (Figure 10-15). This scheme allows systems to use the SPI as either master or slave (without changing the routing scheme). Programs only need to use the SPI control register settings to configure master or slave operation.
SPI_MOSI_I SPI_MOSI_O PBEN_O SPI_MISO_I SPI_MISO_O PBEN_O low SPI_CLK_I SPI_CLK_O PBEN_O SPIDS_I DPI Pin04 low low PBEN_O TWI_CLK_I low SPI_FLG0_O PBEN_O TIMER0_O PBEN_O DPI Pin13 DPI Pin05 PBEN_O DPI Pin12 DPI Pin03 TWI_DATA_I DPI Pin11 DPI Pin02 DPI Pin01 UART0TX_O PBEN_O UART0RX_I low DPI Pin10 DPI Pin09

low

SPI_FLG1_O PBEN_O

DPI Pin06

SPI_FLG2_O PBEN_O

DPI Pin07

TIMER1_O PBEN_O

DPI Pin14

SPI_FLG3_O PBEN_O

DPI Pin08

Figure 10-15. DPI Default Routing

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Operating Modes

which are default are driven All DPI input buffersbuffer enablenot routed bydriven low. For SPI low and all DPI pin signals are boot, the DPI pin buffer enable signals 1 and 2 change depending on master or slave boot configuration.

Unused DAI/DPI Connections

As shown in previous sections, the SRUs have a default general-purpose routing scheme which may be modified to suit any number of different system designs. Regardless of the system design, it is good practice to tie all unused inputs to a high or low level to reduce dynamic power consumption. An example is shown in Listing 10-1. Listing 10-1. Tieing Unused Pins Low
/* SPORT5 operates as transmitter only */ SRU(SPORT5_DA_O, DAI_PB03_I); SRU(SPORT5_DB_O, DAI_PB04_I); SRU(LOW, SPORT5_DA_I); SRU(LOW, SPORT5_DB_I); /* DAI pin 03 Data A output */ /* DAI pin 04 Data B output */ /* Data A input tied low */ /* Data B input tied low */

/* DAI Pin buffer 12 operates as input only */ SRU(LOW, DAI_PB12_I); SRU(SPORT5_PBEN_O, DAI_PBEN12_I); /* Input tied low */ /* Output Enable pin tied high */

Operating Modes
Some buffers allow polarity changes which are described below.

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DAI Pin Buffer Polarity

As shown in Figure 10-16, the DAI pin buffer 2019 can change the polarity of the input signal if the corresponding control bits INV_PB[20-19] in the SRU_PIN4 register are set. These bits can be set during runtime and the buffer should not loopback to itself.
DESTINATION SIGNALS DAI_PB01_I SOURCE SIGNALS DAI_PB01_O DAI_PB19_I DAI_PB20_I

...

DAI_PB20_O SPORT0_CLK_O

EX OR

EX OR

...

SPORT5_CLK_O

128:1 MUX

128:1 MUX

BIT 28

128:1 MUX

BIT 29

LOGIC LOW (0) LOGIC HIGH (1)

DAI_PB01_I 7-Bit Select Field

DAI_PB19_I 7-Bit Select Field

DAI_PB20_I 7-Bit Select Field

Figure 10-16. Pin Buffer Polarity

DAI Miscellaneous Buffer Polarity

As shown in Figure 10-16 the A54 miscellaneous buffers can change the polarity of the input signal if the corresponding control bits INV_MISCA[5-4] in the SRU_EXT_MISCA register are set. Both buffers are not connected to the DAI interrupt latch register. Note these bits can be set during runtime.

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Interrupts

DESTINATION SIGNALS MISCA0_I SOURCE SIGNALS DAI_PB01_O MISCA4_I MISCA5_I

...
DAI_PB20_O SPORT0_CLK_O

EX OR

EX OR

...

SPORT5_CLK_O

32:1 MUX

32:1 MUX

BIT 30

32:1 MUX

BIT 31

LOGIC LOW (0) LOGIC HIGH (1)

DAI_INT_22

MISCA0_I 5-Bit Select Field

MISCA4_I 5-Bit Select Field

MISCA5_I 5 -Bit Select Field

Figure 10-17. Miscellaneous Buffer Polarity

Interrupts
The following sections provide information on interrupt capabilities that are DAI/DPI specific. For information on DAI/DPI system interrupts, see Chapter 2, Interrupt Control.

DAI/DPI Miscellaneous Interrupts

Table 10-6 provides an overview of DAI/DPI miscellaneous interrupts. Table 10-6. DPI Miscellaneous Interrupt Overview
Default Sources Programmable Interrupt DAIHI = P0I DAILI = P12I DPII = P14I Rising edge detect Falling edge detect Rising and falling edge detect Masking Service

DAI_IMASK_RE DAI_IMASK_FE DPI_IMASK_RE DPI_IMASK_FE

ROC from DAI_IRPTL_x + RTI instruction ROC from DPI_IRPTL + RTI instruction

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Sources The DAI module generates 10 local miscellaneous interrupts and the DPI nine local miscellaneous interrupts. All the miscellaneous signals are connected into the DAI_IRPTL_x or DPI_IRPTL latch registers. The MISC port can generate interrupts under these conditions. For some applications for instance, SIC needs information about interrupt sources that correspond to waveforms (not event signals). As a result, the falling edge of the waveform may be used as an interrupt source as well.
Edge Detection

Programs may select any of these three conditions: Latch on the rising edge Latch on the falling edge Latch on both the rising and falling edge Masking The DAIHI and DAILI signals are routed by default to programmable interrupt. To service the DAIHI, unmask (set = 1) the P0I bit in the IMASK register. To service the secondary DAILI, unmask (set = 1) the P12IMSK bit in the LIRPTL register. For DAI system interrupt controller the DAI_IMASK_RE or DAI_IMASK_FE register must be unmasked. The DPI signal is routed by default to programmable interrupt. To service the DPI, unmask (set = 1) the P14I bit in the IMASK register. For DPI system interrupt controller the DPI_IMASK_RE or DPI_IMASK_FE register must be unmasked. For example:
bit set IMASK P0I; bit set LIRPTL P12IMSK; bit set IMASK P14I; /* unmasks P0I interrupt */ /* unmasks P12I interrupt */ /* unmasks P14I interrupt */

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Effect Latency

Service To clear the interrupt request, the interrupt service routine needs to read from the DAI_IRPTL_x or DPI_IRPTL register.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

Signal Routing Unit Effect Latency

After the DAI/DPI registers are configured the effect latency is 2 PCLK cycles minimum and 3 PCLK cycles maximum.

Programming Model
As discussed in the previous sections, the signal routing unit is controlled by writing values that correspond to signal sources into bit fields that further correspond to signal inputs. The SRU is arranged into functional groups such that the registers that are made up of these bit fields accept a common set of source signal values. In order to ease the coding process, the header file SRU.H is included with the VisualDSP++ tools. This file implements a macro that abstracts away most of the work of signal assignments and functions. The macro has identical syntax in C/C++ and assembly, and makes a single connection from an output to an input as shown below.

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SRU(Output Signal, Input Signal);

The names passed to the macro are the names given DAI Signal Routing Unit Registers on page A-123. The code in Listing 10-2 shows how the macro is used. Listing 10-2. DAI Macro Code
#include <sru.h>; /* The following lines illustrate how the macro is used: */ /* Route SPORT 1 clock output to pin buffer 5 input */ SRU(SPORT1_CLK_O,DAI_PB05_I); /* Route pin buffer 14 out to IDP3 frame sync input */ SRU(DAI_PB14_O,IDP3_FS_I); /* Connect pin buffer enable 19 to logic low */ SRU(LOW,PBEN19_I);

Additional example code is available on the Analog Devices Web site. macro that has been created to peripherals used There is aconfiguration. This code can be connect both assembly in a DAI used in and C code. See the INCLUDE file SRU.H. There is also a software plug-in called the Expert DAI that greatly simplifies the task of connecting the signals described in this chapter. This plug-in is described in Engineer-to-Engineer Note EE-243, Using the Expert DAI for ADSP-2126x and ADSP-2136x SHARC Processors. This EE note is also found on the Analog Devices Web site.

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Programming Model

Making SRU Connections

In this section, three types of SRU routing are demonstrated. 1. Listing 10-3 and Figure 10-18 show the SRU connection between the DAI and pin buffers. 2. Listing 10-4 on page 10-36 and Figure 10-19 on page 10-36 show the SRU connection between the DAI pin buffers and SPORTs. 3. Listing 10-5 on page 10-37 and Figure 10-20 on page 10-37 show SRU connection from the SPORT/PCG to the MISC/DAI pin buffers. examples use a macro by the These Also see Programmingwhich is provided 10-32. VisualDSP tools. Model on page Listing 10-3. SRU Connection Between DAI Pin Buffers
SRU(HIGH, PBEN03_I); // DAI pin 3 output nop; SRU(LOW, PBEN14_I); // DAI pin 14 input nop; SRU(LOW, DAI_PB14_I); // DAI pin 14 input level low nop; SRU(DAI_PB14_O, DAI_PB03_I); // connect DAI pin 14 to DAI pin 3 nop; SRU(DAI_PB14_O, DAI_INT_22_I); // connect DAI pin 14 to DAI interrupt 22

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SRU
DAI_PB03_I PERIPHERAL PBEN03_I

DAI_PB03

DAI_PB14_O PERIPHERAL

PBEN14_I

DAI_PB14

PERIPHERAL

DAI_INT_22_I

DAI_INT_22 LATCH DAI_INT_22

Figure 10-18. SRU Connection Between DAI Pin Buffers

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Programming Model

Listing 10-4. SRU Connection Between DAI Pin Buffers and SPORTs
SRU(SPORT0_CLK_PBEN_O, PBEN03_I); nop; SRU(SPORT0_CLK_O, DAI_PB03_I); nop; SRU(SPORT0_CLK_O, SPORT1_CLK_I); nop; SRU(SPORT0_CLK_O, SPORT2_CLK_I); // DAI pin 3 as output // connect to DAI pin 3 // connect to SPORT1 // connect to SPORT2

SRU
SPORT0_CLK_O SPORT0 CLK_PBEN_O DAI_PB03_I PBEN03_I

DAI_PB03

SPORT1_CLK_I SPORT1

DAI_PBxx SPORT2_CLK_I SPORT2

DAI_INT_xx LATCH MISCAx

Figure 10-19. SRU Connection Between DAI Pin Buffers and SPORTs

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Digital Application/ Digital Peripheral Interfaces

Listing 10-5. SRU Connection SPORT/PCG to MISC/DAI Pin Buffers

SRU(HIGH, PBEN03_I); nop; SRU(DAI_PB14_O, DAI_PB03_I); nop; SRU(PCG_CLKB_O, DAI_PB14_I); nop; SRU(SPORT2_FS_O, MISCA4_I); nop; SRU(MISCA4_O, PBEN14_I); nop; SRU(HIGH, INV_MISCA4_I); // DAI pin 3 output // connect pin 3 and 14 // connect PCG and pin 14 // connect SPORT to MISCA // connect MISCA to PBEN14 // invert MISCA4 input

SRU

DAI_PB03_O DAI_PB03_I

PERIPHERAL

PBEN03_I

DAI_PB03

DAI_PB14_O PCG_CLKB_O PCG B PBEN14_I DAI_PB14 DAI_PB14_I

MISCA4_O SPORT2_FS_O SPORT2 MISCA4_I INVERT MISCA4

Figure 10-20. SRU Connection SPORT/PCG to MISC/DAI Pin Buffers

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Programming Model

DAI Example System

A complete system using the DAI peripherals (SPORTs, PCG, S/PDIF) is shown in Figure 10-21.

SOURCE FROM DVD PLAYER S/PDIF serial protocal containing multichannel audio sampled at 48 KHz and compressed in AC3

CLOCK

PIN_1

S/PDIF STREAM

S/PDIF RECEIVER

FRAME SYNC SERIAL DATA

IDP CHANNEL0

SHARC CORE

MULTICHANNEL CLOCK

CONNECT TO S/PDIF RX

TRANSLATE PROTOCOL On-chip DPLL used to recover clock and frame sync

I2S DATA INTO SHARC CORE AC3 (Dolby Digital) decompression algorithm is executed in software

BRING DATA INTO SHARC CORE Three synchronized (but separate) stereo streams sampled at 44.1 KHz are brought back to the core for IDP reverb, CHANNEL_1 EQ and CHANNEL_2 other effects CHANNEL_3

SAMPLE RATE CONVERSION Convert using chaining mode multichannel channels are extracted and the rate conversion ratio is phase locked channel to channel. SRC2 I2S DATA (3 STEREO PAIRS)
44.1 KHz MULTICHANNEL RATE

SPORT0 5.1 channel surround sound sampled at 48 KHz SRC0

SRC1

SHARC CORE

SAMPLE CLOCK OUTPUT The output of the PCG is routed to a pin and the 44.1 KHz output sample rate clock is also routed to the same pin. PCG

STEREO MIX SPORT1 If the system has only 2 speakers, this stereo DAC can be used instead of the 5.1 The SHARC runs a spaitial effects algorithm for virtual rear speakers.

SPORT2
SERIAL DATA FRAME SYNC

SPORT3
SERIAL DATA

SPORT4
SERIAL DATA

SPORT5
SERIAL DATA FRAME SYNC

Low Jitter DAC Clock (44.1 KHz) for both SRCs and external DACs

PIN_9

PIN_8

PIN_7

PIN_6

PIN_5

PIN_4

PIN_3

PIN_2

PIN_12

PIN_11

PIN_10 MIX_FS MIX_DAT FL_FR_DAT CTR_LFE_DAT RL_RR_DAT FS SCLK MCLK

CLK

FS

DATA

External 8-bit macro for scanning for button presses, knobs, etc.

Figure 10-21. DAI Example

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Digital Application/ Digital Peripheral Interfaces

Debug Features
The following sections describe features that can be used to help in debugging the DAI.

Shadow Interrupt Registers

For more information, see Debug Features on page 2-15.

Loopback Routing
The serial peripherals (SPORT and SPI) support an internal loopback mode. If the loopback bit for each peripheral is enabled, it connects the transmitter with the receiver block internally (does not signal off-chip). The SRU can be used for this purpose. Table 10-7 describes the different possible routings based on the peripheral. mode The peripherals loopback units. for debug is independent from both of the signal routing Table 10-7. Loopback Routing
Peripheral DAI IDP SPORT N/A Yes N/A SPORTx_xx_O SPORTx_xx_I DIT_O DIR_I SRCx_DAT_OP_O SRCx_DAT_IP_I N/A SPORTx_xx_O DAI_PBxx_I DIT_O DAI_PBxx_I DAI_PBxx_O DIR_I SRCx_DAT_OP_O DAI_PBxx_I DAI_PBxx_O SPORTx_xx_I Loopback Mode SRU/SRU2 Internal Routing SRU/SRU2 External Routing for for Loopback Loopback

S/PDIF Tx/Rx SRC

No

No

DAI_PBxx_O SRCx_DAT_IP_I

DPI

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Debug Features

Table 10-7. Loopback Routing (Contd)

Peripheral Timer Loopback Mode No SRU/SRU2 Internal Routing SRU/SRU2 External Routing for for Loopback Loopback TIMERx_O TIMERx_I No UART0_TX_O UART0_RX_I No DPI_PBxx_O TIMERx_I DPI_PBxx_O SPIx_xx_I UART0 No SPIx_xx_O DPI_PBxx_I UART0_TX_O DPI_PBxx_I DPI_PBxx_O UART0_RX_I DPI_PBxx_O TWI_xx_I TWI_xx_O DPI_PBxx_I TIMERx_O DPI_PBxx_I

SPI

Yes

TWI

No

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11 SERIAL PORTS (SPORTS)

The processors have eight independent, synchronous serial ports (SPORTs) that provide an I/O interface to a wide variety of peripheral devices and are optimized for multichannel audio applications. They are called SPORT0 to SPORT7. Each SPORT has its own set of control registers and data buffers. With a range of clock and frame synchronization options, the SPORTs allow a variety of serial communication protocols and provide a glueless hardware interface to many industry-standard data converters and CODECs. The interface specifications are shown in Table 11-1. Table 11-1. Serial Port Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Yes Yes Yes Yes No Yes Yes No N/A Yes SPORT70[AB]

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Features

Table 11-1. Serial Port Specifications (Contd)

Feature Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Miscellaneous Clock Power Management Boot Capable Local Memory Clock Operation Yes No No fPCLK/4 (fPCLK/8 if SPORT is slave transmitter or master receiver) Yes Yes Yes 2 per SPORT Yes SPORT70[AB] No

Features
Serial ports offer the following features and capabilities: A variety of protocols are supported (see Operating Modes on page 11-28): 1. Standard serial 2. Left-justified 3. I2S 4. Packed 5. Multichannel

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Serial Ports (SPORTs)

Two bidirectional channels (A and B) per serial port, configurable as either transmitters or receivers. Each serial port can also be configured as two receivers or two transmitters, permitting two unidirectional streams into or out of the same serial port. This bidirectional functionality provides greater flexibility for serial communications. Further, two SPORTs can be combined to enable full-duplex, dual-stream communications. Serial ports can operate at a maximum of one-fourth the peripheral clock rate of the processor. If channels A and B are active, each SPORT has a maximum throughput of 2 x PCLK/4 rate. Chained DMA operations for multiple data blocks, see Chained DMA on page 3-31. SPORT DMA channels are assigned highest priority for fixed DMA arbitration mode. DMA Chain insertion mode allows the SPORTs to change DMA flow during chaining. See Enter DMA Chain Insertion Mode on page 11-58. Data words between 3 and 32 bits in length, either most significant bit (MSB) first or least significant bit (LSB) first. For multichannel/packed protocol, a SPORT pair can be combined together for full-duplex, dual-stream communications. 128-channel multichannel is supported in multichannel mode operation, useful for audio CODEC connections or H.100/H.110 and other telephony interfaces described in Multichannel Protocol on page 11-20. In multichannel mode active channel selection logic allows programs to enable/disable individual channels.

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Features

-law and A-law companding hardware on transmitted (compression) and received (expansion) words when the SPORT operates in multichannel mode. Supports error event detection for unexpected Frame Syncs and not meeting real time requirements (data buffer under/overflow).

Receive comparison and 2-dimensional DMA are not supported.

Serial Port Versus Input Data Port Features
If the input stream requires I2S, left-justified or right-justified protocols the IDP may be an appropriate interface to use. It supports up to 8 DMA channels and frees up SPORT resources. Table 11-2 shows an overview. For more information, see Chapter 12, Input Data Port (SIP, PDAP). Table 11-2. Support Versus IDP Features
Feature Data inputs Data direction Data companding Protocol Bus Serial clock DMA modes DMA channels SPORT Serial 32-bit Input/Output Yes Standard serial, I2S, left-justified, packed, multichannel Master/slave Any Standard/chained 16 (8 2) IDP Serial 32-bit Parallel 20-bit Input No I2S, left justified, right-justified Slave 64 FS Standard/Ping-pong 8

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Serial Ports (SPORTs)

Pin Descriptions
Table 11-3 describes pin function. Table 11-3. SPORT Pin Descriptions
Internal Node SPORT70_DA_I SPORT70_DA_O Direction I O Description Data receive channel A. Bidirectional data pin. If TRAN = 0, input to receive serial data. Data transmit channel A. Bidirectional data pin. If TRAN = 1, output to transmit serial data. The transmit data pin is always driven (and continues to drive last level of serial word) if the serial port is enabled and TRAN=1 unless it is in multichannel/packed mode and an inactive channel slot occurs. Data receive channel B. Bidirectional data pin. If TRAN = 0, input to receive serial data. Data transmit channel B. Bidirectional data pin. If TRAN = 1, output to transmit serial data. The transmit data pin is always driven (and continues to drive last level of serial word) if the serial port is enabled and TRAN=1 unless it is in multichannel/packed mode and an inactive channel slot occurs. Transmit/Receive Serial Clock. This signal can be either internally or externally generated. Transmit/Receive Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. It can be active high or low or an early or a late frame sync, in reference to the shifting of serial data. Multichannel Transmit Data Valid. This output only active in SPORT transmit multichannel/ packed protocol mode. The signal is asserted during active transmit channel slots based on the active channel selection registers.

SPORT7-0_DB_I SPORT70_DB_O

I I/O

SPORT70_CLK_I/O SPORT70_FS_I/O

I/O I/O

SPORT70_TDV_O

ADSP-214xx SHARC Processor Hardware Reference

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SRU Programming

Table 11-3. SPORT Pin Descriptions (Contd)

Internal Node SPORT70_DA_PBEN_O SPORT70_DB_PBEN_O SPORT70_CLK_PBEN_O SPORT70_FS_PBEN_O SPORT70_TDV_PBEN_O Direction O O O O O Description Pin Buffer Enable Pins. For correct SPORT operation the PBEN output signals should be routed to its pin buffer input signal. Note that the SCLK and FS outputs are only driven if programmed as master.

SRU Programming
Any of the serial ports signals can be mapped to digital applications interface (DAI_Px) pins through the signal routing unit (SRU) as shown in Table 11-4. For more information, see Chapter 10, Digital Application/ Digital Peripheral Interfaces. their SPORTs 6 and 7 receiveclocks clocks from other routed sources but cannot route their own to other SPORTs or other peripherals internally through the SRU. If SPORTs 6 and 7 are needed externally, route them through the DAI pins. Table 11-4. SPORT DAI/SRU Signal Connections
Serial Port Source Inputs SPORT50_CLK_O SPORT70_DA_O SPORT70_DB_O SPORT50_FS_O Group A Group B Group C SPORT70_CLK_I SPORT70_DA_I SPORT70_FS_I DAI Connection Serial Port Destination

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Serial Ports (SPORTs)

Table 11-4. SPORT DAI/SRU Signal Connections (Contd)

Serial Port Source SPORT70_CLK_O SPORT70_DA_O SPORT70_DB_O SPORT70_FS_O SPORT70_TDV_O SPORT50_FS_O SPORT70_CLK_PBEN_O SPORT70_DA_PBEN_O SPORT70_DB_PBEN_O SPORT70_FS_PBEN_O SPORT70_TDV_PBEN_O DAI Connection Group D Serial Port Destination

Group E Group F

SRU SPORT Receive Master

If the SPORT is operating as receive master, it must feed its master output clock back to its input clock. This is required to trigger the SPORTs state machine. Using SPORT 4 as an example receive master, programs should route SPORT4_CLK_O to SPORT4_CLK_I. This is not required if the SPORT is operating as a transmitter in master mode.

SRU SPORT Signal Integrity

There is some sensitivity to noise on the clock (SPORTx_CLK) and frame sync (SPORTx_FS) signals when the SPORT is configured as a master receiver. By correctly programming the signal routing unit (SRU) clock and frame sync registers, the reflection sensitivity in these signals can be avoided. Figure 10-10 on page 10-18 shows the default routing of the serial port where the SRU maps to: The signal from the DAI pin (DAI_PBxx_O) back to the SPORT clock input (SPORTx_CLK_I)

ADSP-214xx SHARC Processor Hardware Reference

11-7

Register Overview

The SPORT clock output (SPORTx_CLK_O) to the pin buffer input (DAI_PBxx_I) By redirecting the signals as shown in Figure 11-1 where the clock and frame sync outputs are routed directly back to their respective inputs, the signal sensitivity issue can be avoided.
SPORT0_CLK_I

DAI_PB01_O

SPORT0_CLK_O DAI_PB01_I

IN

PIN ENABLE

DAI_PB01_O OUT

EXTERNAL PACKAGE CONNECTION

SPORT0_CLK_PBEN_O

PBEN01_I

SPORT0_FS_I

DAI_PB02_O

SPORT0_FS_O DAI_PB02_I

IN

PIN ENABLE

DAI_PB02_O OUT

EXTERNAL PACKAGE CONNECTION

SPORT0_FS_PBEN_O PBEN02_I

Figure 11-1. SRU Configuration when SPORT is Master Receiver.

Register Overview
This section provides brief descriptions of the major registers. For complete information, seeSerial Port Registers on page A-154. Master Clock Divider (DIVx). Contain divisor values that determine frequencies for internally-generated clocks and frame syncs. If your system

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Serial Ports (SPORTs)

requires more precision and less noise and jitter, refer to Chapter 15, Precision Clock Generator. Serial Port Control/Status (SPCTLx). Control serial port modes and are part of the SPCTLx (transmit and receive) control registers. Other bits in these registers set up DMA related serial port features. For information about configuring a specific operation mode, refer to Table 11-8 on page 11-29 and Operating Modes on page 11-28. Multichannel Control/Status (SPMCTLx). There is one global control and status register for each SPORT (SPORT70) for multichannel operation. These registers define the number of channels, provide the status of the current channel, enable multichannel operation, and set the multichannel frame delay. Serial Port Control N (SPCTLNx). Control enhanced serial port modes and also allow compatibility mode switches between legacy SPORT modules. See SPORT Control 2 Registers (SPCTLNx) on page A-164. Serial Port Error (SPERRxx). Two error registers (SPERRCTLx/SPERRSTAT) are used to observe and control error handling during transfers. Detected errors can be frame sync violation or buffer over/underflow conditions. For more information, see Sources on page 11-52.

Clocking
The fundamental timing clock of the SPORT modules is peripheral clock/4 (PCLK/4). Each serial port has a clock signal (SPORTx_CLK) for transmitting and receiving data on the two associated data signals. The clock and frame sync signals are configured by the ICLK/IFS and CLKDIV/ FSDIV bits of the SPCTLx/DIVx control registers. One clock signal clocks both A and B data signals (either configured as inputs or outputs) to receive or transmit data at the same rate. The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

ADSP-214xx SHARC Processor Hardware Reference

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Clocking

Master Clock
The CLKDIV bit field specifies how many times the processors internal clock (PCLK) is divided to generate the transmit and receive clocks. The frame sync (SPORTx_FS) is considered a receive frame sync if the data signals are configured as receivers. Likewise, the frame sync SPORTx_FS is considered a transmit frame sync if the data signals are configured as transmitters. The divisor is a 15-bit value, (bit 0 in divisor register is reserved) allowing a wide range of serial clock rates. Use the following equation to calculate the serial clock frequency: TX master: SCLK = PCLK (4 (CLKDIV + 1)) for CLKDIV[132767] RX master: SCLK = PCLK (4 (CLKDIV + 1)) for CLKDIV[232767] The maximum serial clock frequency is equal to one-fourth (0.25) the processors internal peripheral clock (PCLK) frequency, which occurs when CLKDIV is set to a minimum of 1. Use the following equation to determine the value of CLKDIV, given the PCLK frequency and desired serial clock frequency: CLKDIV = (PCLK 4 SCLK) 1

Master Frame Sync

The bit field FSDIV specifies how many transmit or receive clock cycles are counted before a frame sync pulse is generated. In this way, a frame sync can initiate periodic transfers. The counting of serial clock cycles applies to internally- or externally-generated serial clocks. The formula for the number of cycles between frame sync pulses is: Number of serial clocks between frame syncs = FSDIV + 1 Use the following equation to determine the value of FSDIV, given the serial clock frequency and desired frame sync frequency: FSDIV = (SCLK FSCLK) 1

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Serial Ports (SPORTs)

The frame sync is continuously active when FSDIV = 0. The value of FSDIV should not be less than the serial word length (the value of the SLEN field in the serial port control register), as this may cause an external device to abort the current operation or cause other unpredictable results. Programming SLEN > FSDIV1 field causes a FS error exception if error logic is enabled. For more information, see Interrupts on page 11-51. should sync on the Programsto drive not use the master clock/frameaudio systems since SPORTs ADCs/DACs in high fidelity jitter may be introduced from the on-chip PLL. To alleviate this problem use the precision clock generator (PCGx) routed by low jitter external master clocks (CLKIN or DAI pin inputs). For more information, see Chapter 15, Precision Clock Generator.

General-Purpose Pulse Generator

If the serial port is not being used, the FSDIV divisor can be used as a counter for dividing an external clock or for generating a periodic pulse or periodic interrupt. The serial port must be enabled for this mode of operation to work properly. If the SPORT serial clock (SCLK) is required as general-purpose clock in a system, only the ICLK/MSTR bit and the serial clock divider register DIVx must be programmed. If the frame sync of SPORT (FS) is required as general-purpose clock in a system, the ICLK/MSTR bit and the serial clock divider register DIVx must be programmed. Additionally the SPEN_x/SPTRAN/DIFS bits must be set.

Slave Mode
Exercise caution when operating with externally-generated transmit clocks near the frequency of PCLK/4 of the processors internal clock. There is a delay between when the clock arrives at the SPORTx_CLK node and when

ADSP-214xx SHARC Processor Hardware Reference

11-11

Clocking

data is output. This delay may limit the receivers speed of operation. Refer to the appropriate product data sheet for exact timing specifications. Externally-generated late transmit frame syncs also experience a delay from when they arrive to when data is output. This can also limit the maximum serial clock speed. Refer to the appropriate product data sheet for exact timing specifications.

Mixed Mode
This mode allows combinations of serial clock as master and frame sync as slave or vice versa. This mode is only supported by the standard serial and multichannel or packed protocol modes.

Maximum Clock Rate Restrictions

Caution should be exercised when operating with externally generated transmit clocks near the maximum operating frequency (PCLK/4). There is a delay between when the clock arrives at the DAI pin and when data is output which may limit the receivers operating speed. For reliable operation, it is recommended that full-speed serial clocks only be used when receiving with an externally generated clock and externally generated frame sync (ICLK = 0, IFS = 0). Externally-generated late transmit frame syncs (LAFS = 1) also experience a delay from when they arrive to when data is output which can also limit the maximum serial clock speed. Refer to the product specific data sheet for exact timing specifications.

Clock Power Savings

For information on managing power when the SPORT is paused or not used, see Chapter 23, Power Management.

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ADSP-214xx SHARC Processor Hardware Reference

Serial Ports (SPORTs)

Functional Description
The following sections provides general information on the function of the SPORTs. Architecture below Data Types Format on page 11-33 Frame Sync Modes on page 11-34

Architecture
A serial port receives serial data on one of its bidirectional serial data signals configured as inputs, or transmits serial data on the bidirectional serial data signals configured as outputs. It can receive or transmit on both channels simultaneously and unidirectionally, where the pair of data signals can both be configured as either transmitters or receivers. The SPORTx_DA and SPORTx_DB channel data signals on each SPORT cannot transmit and receive data simultaneously for full-duplex operation. Two SPORTs must be combined to achieve full-duplex operation. The SPTRAN bit in the SPCTLx register controls the direction for both the A and B channel signals. direction channel The datamust be theofsame. A and channel B on a particular SPORT Serial communications are synchronized to a clock signal. Every data bit must be accompanied by a clock pulse. Each serial port can generate or receive its own clock signal (SPORTx_CLK). Internally-generated serial clock frequencies are configured in the DIVx registers. The A and B channel data signals shift data based on the rate of SPORTx_CLK. Note that if the SPORT is enabled in master mode, the serial clock starts running unless the SPORT is disabled.

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Functional Description

In addition to the serial clock signal, data may be signaled by a frame synchronization signal. The framing signal can occur at the beginning of an individual word or at the beginning of a block of words. The configuration of frame sync signals depends upon the type of serial device connected to the processor. Each serial port can generate or receive its own frame sync signal (SPORTx_FS) for transmitting or receiving data. Internally-generated frame sync frequencies are configured in the DIVx registers. Both the A and B channel data signals shift data based on their corresponding SPORTx_FS signal. Figure 11-2 shows a block diagram of a serial port. Setting the SPTRAN bit enables the data buffer path, which, once activated, responds by shifting data in response to a frame sync at the rate of SPORTx_CLK. An application program must use the correct serial port data buffers, according to the value of the SPTRAN bit. The SPTRAN bit enables either the transmit data buffers for the transmission of A and B channel data, or it enables the receive data buffers for the reception of A and B channel data. Inactive data buffers are not used. Companding Companding (compressing/expanding) is the process of logarithmically encoding and decoding data to minimize the number of bits that must be sent. The processors serial ports support the two most widely used companding algorithms, A-law and -law, performed according to the CCITT G.711 specification. Note that companding is not supported for I2S and left-justified protocols. The type of companding can be selected independently for each SPORT. Companding is selected by the DTYPE field of the SPCTLx control register. supported channel only. Companding ischannels areon the Aof compression,SPORT0, 2, 4 and 6 primary capable while SPORTs 1, 3, 5 and 7 primary channels are capable of expansion.

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ADSP-214xx SHARC Processor Hardware Reference

Serial Ports (SPORTs)

IOD1 BUS IOD0 BUS PERIPHERAL CORE BUS

32 32 32 32
TXSPxB TRANSMIT DATA BUFFER

32

32
RXSPxB RECEIVE DATA BUFFER

TXSPxA TRANSMIT DATA BUFFER 32 HARDWARE COMPANDING (COMPRESSION) SPORTS 0, 2, 4, 6 ONLY 32 TRANSMIT SHIFT REGISTER

RXSPxA RECEIVE DATA BUFFER 32

HARDWARE COMPANDING (EXPANSION) SPORTS 1, 3, 5, 7 ONLY 32

32

32

RECEIVE SHIFT REGISTER

TRANSMIT SHIFT REGISTER SPTRAN=1 Tx ENABLE

RECEIVE SHIFT REGISTER SPTRAN=0 Rx ENABLE

SPTRAN=1 Tx ENABLE

SPTRAN=0 Rx ENABLE

SPORTx_CLK SPORTx_FS

SPTRAN CNTL

SPORTx_DA_OUT

SPORTx_DA_IN
SERIAL PORT CONTROL

SPORTx_DB_OUT

SPORTx_DB_IN

SPORTx_DA SPORTx_FS

SPORTx_DB

SPORTx_CLK

Figure 11-2. Serial Port Block Diagram The processors SPORTs are not UARTs and cannot communicate with an RS-232 device or any other asynchronous communications protocol. One way to implement RS-232 compatible communication with the processor is to use two of the FLAG pins as asynchronous data receive and transmit signals.

ADSP-214xx SHARC Processor Hardware Reference

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Functional Description

Frame Sync and Data Sampling

The information contained in this section is generic to the SPORTs in any operating mode. Additional information about frame syncs and data sampling that applies to a specific operating mode can be found in Operating Modes on page 11-28. As shown in Figure 11-3 the SPORT uses two control signals to sample data. 1. Serial clock (SCLK) applies the bit clock for each serial data. 2. Frame sync (FS) divides the incoming data stream into frames. Frames define the required data length (after the serial to parallel conversion) necessary to store the data in memory for further processing as shown in Figure 11-3. For example, the transmitter drives the master clock and frame sync while the receiver slave is sampling the data.
DRIVE SCLK DRIVE FS SDRIVE DATA

D7

D6

D5

D4

D3

D2

D1

D0

SAMPLED FS SLEN COUNTER

SAMPLED DATA

D7

D6

D5

D4

D3

D2

D1

D0

Figure 11-3. Frame Sync and Data Driven on Rising Edge After the slave has sampled the FS the SLEN word counter is reloaded to its maximum setting. Each SCLK period decrements the SLEN counter until the

11-16

ADSP-214xx SHARC Processor Hardware Reference

Serial Ports (SPORTs)

full frame is received. If the transmitter drives the frame sync and data on the rising edge, the falling edge is used to sample the frame sync and data, and vice versa. Continuous Framed Data Transfers If data transmission is continuous in framing mode (for example, the last bit of each word is immediately followed by the first bit of the next word), the following settings should be used. For non-multichannel protocol mode, load the FSDIV register with SLEN1. For example, for 8-bit data words set SLEN = 0x7 and FSDIV = 0x7. For multichannel/packed mode the FS period = serial word length number of channels. In multichannel mode if NCH = 0x7 channels, set SLEN = 0x7 and FSDIV = 0x3F.

SPORT Protocols
The following sections provide brief descriptions of the serial port supported protocols. For more information, see Appendix C, Audio Frame Formats. Standard Serial Protocol The standard serial mode lets the serial ports interface to a variety of serial devices such as serial data converters and audio codecs. In order to connect to these devices, a variety of clocking, framing, and data formatting options are available.
Protocol Configuration Options

Data (direction, linear or companding) Little or big endian

ADSP-214xx SHARC Processor Hardware Reference

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Functional Description

Serial word length (3-32 bits) Data buffer (16 or 32-bit packing) Serial clock (internal or external edge select) Frame sync (polarity, required vs continuous, internal or external, early or late, data or channel de-pendent) DMA (standard or chained) Debug (loopback test) Left-Justified Protocol The left-justified protocol transmits and or receives two samples of data in each frame sync cycleone sample on the high segment (left channel) of the frame sync, the other on the low segment (right channel) of the frame sync.
Protocol Configuration Options

Data (direction) Serial word length (8-32 bits) Data buffer (16 or 32-bit packing) Serial clock and FS (Internal or External) Frame sync (polarity, data dependent, channel first) DMA (standard or chained) Debug (loopback test)

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Serial Ports (SPORTs)

I 2 S Protocol The I2S protocol transmits and or receives two samples of data in each frame sync cycleone sample on the high segment (right channel) of the frame sync, the other on the low segment (left channel) of the frame sync. Note that in I2S mode, the data is delayed by one SCLK cycle.
Protocol Configuration Options

Data (direction) Serial word length (8-32 bits) Data buffer (16 or 32-bit packing) Serial clock and FS (Internal or External) Frame sync (polarity, data dependent, channel first) DMA (standard or chained) Debug (loopback test)
I2S Compatibility

In previous generations of SHARC processors, the serial ports did not generate a FS edge (word select signal) after the transmission of the last word in the DMA channel. This differed from standard I2S receivers which look for the edge to latch and read data. Therefore, I2S slave receivers connected to the SHARC SPORTs were unable to latch the last word of a transmit DMA. The ADSP-214xx SHARC processors are able to generate the last FS edge (WS) if configured as an I2S master (valid only for DMA), if the extra frame edge (I2SEFE bit) in the SPCTLNx register is set. If this bit is cleared, legacy behavior is provided.

ADSP-214xx SHARC Processor Hardware Reference

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Functional Description

(extra) frame edge Setting the bit generates the compatible programmed in only for continuous data streams ( =
I2SEFE FSDIV SLEN DIVx

register). In the cases where FSDIV > SLEN value programmed, the extra last edge is not generated.

Channel Order First

The LFS bit (renamed to L_FIRST) is used for the I2S/left-justified or the packed protocol to determine which frame transmits or receives first. The left and right channels are time-duplex data channels. Table 11-5. Channel Order First
OPMODE Left-Justified I2S/Packed L_FIRST = 0 Left channel first Right channel first L_FIRST = 1 Right channel first Left channel first

In I2S/left justified or packed protocols the SPORT starts to drive the FS signal high (=1) for the first valid frame. Multichannel Protocol The processors serial ports offer a multichannel mode of operation (Figure 11-4), which allows the SPORT to communicate in a time division multiplexed (TDM) serial system. In multichannel communications, each data word of the serial bit stream occupies a separate channel and each word belongs to the next consecutive channel. For example, a 24-word block of data contains one word for each of the 24 channels.

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Serial Ports (SPORTs)

Frame N FS

Frame N + 1

CLK

DATA

WORD0

WORD1

WORD0

WORD1

Figure 11-4. TDM and Multichannel Protocol

Protocol Configuration Options

Data (direction, linear or companding) Little or big endian Serial word length (3-32 bits) Data buffer (16 or 32-bit packing) Serial clock (internal or external, edge select) Frame sync (polarity, internal or external, delay) DMA (standard or chained) TDM channel (number, activation)
Multiple Channels

The serial port can automatically select some words for particular channels while ignoring others. Up to 128 channels are available for transmitting or receiving or both. Each SPORT can receive or transmit data selectively from any of the 128 channels. To operate in full-duplex operation, the SPORT can be optionally routed in pairs together, each SPORT configured as transmitter/ receiver. All receiving and transmitting devices in a multichannel system must have the same timing reference.

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Functional Description

Data companding and DMA transfers can also be used in multichannel mode on channel A. Channel B can also be used in multichannel mode, but companding is not available on this channel. Although the eight SPORTs are programmable for data direction in the standard mode of operation, their programmability is restricted for multichannel operations. The following points summarize the following limitations. The primary A channels of SPORT1, 3, 5, and 7 are capable of expansion only, and the primary A channels of SPORT0, 2, 4, and 6 are capable of compression only. Receive comparison is not supported.
Multichannel Frame Sync Delay

The 4-bit MFD field (bits 41) in the multichannel control registers (SPMCTLx) specifies a delay between the frame sync pulse and the first data bit in multichannel mode. The value of MFD is the number of serial clock cycles of the delay. Multichannel frame delay allows the processor to work with different types of telephony interface devices. A value of zero for MFD causes the frame sync to be concurrent with the first data bit. The maximum value allowed for MFD is 15. A new frame sync may occur before data from the last frame has been received, because blocks of data occur back to back. Figure 11-5 shows an example of timing for a multichannel transfer with SPORT pairing using SPORT0 and 1. The transfer has the following characteristics. SPORT10 have the same SCLK and frame sync as input. Multichannel is configured as 8 channels. SPORT0A drives data to DAC1 during slot 10 which asserts TDV for two slots.

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Serial Ports (SPORTs)

SPORT1A drives data to DAC2 during slot 32 which asserts TDV for two slots. SPORT1B receives data from ADC during slot 30.
SPORT1-0_CLK_I

SPORT1-0_FS_I

SPORT0_TDV_O

SPORT0_DA_O

THREE-STATE

SLOT0

SLOT1

THREE-STATE

SPORT1_TDV_O

SPORT1_DA_O

THREE-STATE

SLOT2

SLOT3

THREE-STATE

SPORT1_DB_I

SLOT0

SLOT1

SLOT2

SLOT3

Figure 11-5. Multichannel Operation

Number of Channels (NCH)

Select the number of channels used in multichannel operation by using the 7-bit NCH field in the multichannel control register. Set NCH to the actual number of channels minus one (NCH = Number of channels 1). The 7-bit CHNL field in the multichannel control registers indicates the channel that is currently selected during multichannel operation. This field is a read-only status indicator. The CHNL(6:0) bits increment modulo NCH(6:0) as each channel is serviced.
Active Channel Selection Registers

Specific channels can be individually enabled or disabled to select the words that are received and transmitted during multichannel communications. Data words from the enabled channels are received or transmitted,

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Functional Description

while disabled channel words are ignored. Up to 128 channels are available for transmitting and receiving. The multichannel selection registers enable and disable individual channels. The registers for each serial port are shown inSerial Port Registers on page A-154. Each of the four multichannel enable and compand select registers are 32 bits in length. These registers provide channel selection for 128 (32 bits 4 channels = 128) channels. Setting a bit enables that channel so that the serial port selects its word from the multiple-word block of data (for either receive or transmit). For example, setting bit 0 in the SP0CS0 register (SPORT0) or SP7CS0 register (SPORT7) selects channel 0, setting bit 12 selects channel 12, and so on. Setting bit 0 in SP0CS1 register (SPORT0) or SP7CS1 register (SPORT7) selects channel 32, setting bit 12 selects channel 44, and so on.
Active Channel Companding Selection Registers

Companding may be selected on a per-channel basis as shown in Table 11-6. Setting a bit to 1 in any of the multichannel registers (SPxCCSy specifies that the data be companded for that channel. A-law or -law companding can be selected using the DTYPE bit in the SPCTLx control registers. SPORTA1, 3, 5 and 7 expand selected incoming time slot data, while SPORTA0, 2, 4 and 6 can compress the data. registers must be enabled according Active channel selection core or DMA hang can occur. to the application, otherwise a Table 11-6. Active Channel Selection Register Settings
Active Channel Selection Registers SP70CS0 SP70CS1 Active Channel Companding Selection Registers SP70CCS0 SP70CCS1 Activated Channel Slots 031 3263

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Table 11-6. Active Channel Selection Register Settings

Active Channel Selection Registers SP70CS2 SP70CS3 Active Channel Companding Selection Registers SP70CCS2 SP70CCS3 Activated Channel Slots 6495 96127

Companding Limitations (ADSP-2146x)

In multichannel mode, there is an option to enable companding for any active channel. If the first active channel is NOT channel 0 and companding is enabled for the first active channel (for example, channel 2), then from the second frame onward companding for channel 2 does not occur. In Table 11-7 channel 0 and 1 are not active and channel 2 is active and companding is enabled. For the ADSP-2146x processors, in the first frame companding occurs for the first active channel (for example, channel 2) but the second frame onward companding for channel 2 does not occur. However, for other channels, companding occurs correctly. In Table 11-7, 1 = Active, 0 = Not Active, x = Dont care. Table 11-7. Companding
Channel Number Active Channel Number Companding Enable 0 0 0 1 0 0 2 1 1 3 x x 4 x x 5 x x

For the ADSP-2147x and ADSP-2148x processors, setting the COMPANDEN bit in the SPCTLNx register overcomes this limitation.
Transmit Data Valid Output Enable

Each SPORT has its own transmit data valid signal (SPORTx_TDV_O) which is active during the transmission of an enabled word. Because the serial ports receiver signals are three-stated when the time slot is not active, the

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Functional Description

SPORTx_TDV_0

signal specifies if the SPORT data is being driven by the

processor. For polarity change of the SPORTx_TDV_O output signal use any of the DAI_PB20-19_I inputs of the routing unit. For more information, see DAI Pin Buffer Polarity on page 10-29.
Multichannel Protocol Backward Compatibility

In previous ADSP-2136x SHARC processors, multichannel protocol mode required a selected SPORT pair (SPORT01, 23 or 45), even if only half-duplex operation was required. This pair needs to route the SCLK and FS (regardless of master/slave) to the odd SPORT (receive) and the TDV output enable signal is multiplexed with the FS output of even SPORT (transmit). The pair itself interconnects the SCLK and FS signals internally. With the ADSP-21367/8/9 processors and later, multichannel mode operates completely independently and no pair is required for half-duplex operation. Each SPORT uses its own SCLK, FS and TDV signal programmed using the SRU. The FS signal synchronizes the channels and restarts each multichannel sequence. The SPORTx_FS signal initiates the start of the first channel data word. The frame sync can be configured in master or slave mode based on the setting of the IFS bit and the FS polarity can be changed using the LFS bit. Packed Protocol A packed mode is available in the SPORT and can be used for audio codec communications using multiples channels. This mode allows applications to send more than the standard 32 bits per channel available through standard I2S mode. Packed mode is implemented using standard multichannel mode (and is therefore programmed similarly to multichannel mode). Packed mode also supports the maximum of 128 channels as does multichannel mode as well as the maximum of (128 x 32) bits per left or right channel.

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Protocol Configuration Options

Data (direction, linear or companding) Little or big endian Serial word length (3-32 bits) Data buffer (16 or 32-bit packing) Serial clock (internal or external, edge select) Frame sync (internal or external, channel order, delay) DMA (standard or chained) TDM channel (number, activation)
Packed Words

As shown in Figure 11-6, packed waveforms are the same as the wave forms used in multichannel mode, except that the frame sync is toggled for every frame, and therefore emulates I2S mode. So it is a hybrid between multichannel and I2S mode. Note that every polarity change of FS restarts a new TDM frame, therefore the frame sync frequency is one-half of that in the TDM protocol.

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Operating Modes

TDM MULTICHANNEL PROTOCOL

FS

CLK

DATA

WORD0

WORD1

WORD0

WORD1

PACKED I2S PROTOCOL

FS

CLK

DATA

WORD0

WORD1

WORD0

WORD1

Figure 11-6. Packed I2S Versus TDM Multichannel Protocols

Operating Modes
The serial port protocol modes are selected via bits in the SPCTLx and the SPMCTLx registers as shown in Table 11-8 and the following list. 1. Bits 0/24 (SPEN_A/SPEN_B) of SPCTLx register enables I2S, left-justified, and standard serial protocols for channel A/B. 2. Bit 11 (OPMODE) of the SPCTLx register selects between I2S, left-justified, and standard serial/multichannel protocols for channel A/B. 3. Bit 17 (LAFS) of the SPCTLx register selects between I2S and left-justified protocol only if bit 11(OPMODE) set.

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4. Bits 0/23 (MCEA/MCEB) of SPMCTLx register enable multichannel and packed protocols for channel A/B. 5. Bit 11 (OPMODE) of the SPCTLx register selects between the multichannel and packed protocol for channel A/B only if bits 0/24 (SPEN_A/SPEN_B) are cleared. Table 11-8. SPORT Protocol Enable Bit Settings
SPCTLx Bits OPERATING MODES (x = A or B or A and B SPORT Channels) Standard Serial Mode Left-justified Mode I2S Mode Packed Mode Multichannel Mode OPMODE (Bit 11) OPMODE (Bit 17) SPEN_x (Bit 0/24) SPMCTLx Bits MCEx

0 1 1 1 0

Valid 1 0 0 0

1 1 1 0 0

0 0 0 1 1

When changing protocol mode, clear the serial port control registers before the new protocol mode is written to the register. The SPORTs operate in five protocols which are listed in the next tables. In each protocol a bit can have the same meaning or a different meaning or is reserved. All modes depending on protocol are described in this section. The SPCTLx and SPMCTL control registers are unique in that the name and function of their bits change depending on the protocol selected. In the following sections, the bit names associated with the protocol are described. Table 11-8 provides values for each of the bits in the SPORT serial control registers that must be set in order to configure each specific protocol. The shaded regions indicated bits responsible for protocol mode setting.

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Operating Modes

The main control register for each serial port is the serial port control register, SPCTLx. These registers are described inSerial Port Registers on page A-154. the serial When changing operatingismodes, clearthe register.port control register before the new mode written to The SPCTLx registers control the operating modes of the serial ports. Table 11-9 lists all the bits in the SPCTLx register. Table 11-9. SPCTLx Control Bit Comparison
[Bit] Name Standard Serial Mode Multichannel Mode Packed I2S Mode I2S and Left-justified Mode

Control [0] SPEN_A [12] DTYPE [3] LSBF [48] SLEN [9] PACK [10] [11] OPMODE [12] CKRE [13] FSR [14] [15] DIFS [16] LFS [17] LAFS [18] SDEN_A [19] SCHEN_A [20] SDEN_B Used Used Used Reserved Used Used Used Used Used Reserved (=1) Used Reserved (=1) Reserved Used Used (L_FIRST) Used (OPMODE) Used Used Reserved (=1) Used Used Used Used Used Used (MSTR) Reserved Used Reserved Reserved (=1)

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Table 11-9. SPCTLx Control Bit Comparison (Contd)

[Bit] Name Standard Serial Mode Multichannel Mode Packed I2S Mode I2S and Left-justified Mode

[21] SCHEN_B [22] FS_BOTH [23] BHD [24] SPEN_B [25] SPTRAN Status [26] DERR_B [2728] DXS_B [29] DERR_A [3031] DXS_A Used Used

Used Reserved (=0) Used Reserved Used Used Reserved (=1) if both channels

Used Used Used Used

Table 11-10. SPMCTLx Control Bit Comparison

[Bit] Name Standard Serial Mode I2S and Left-justified Mode Multichannel Mode Packed I2S Mode

Control [0] MCEA [41] MFD [115] NCH [12] SPL [2216] CHNL [23] MCEB Status [24] DMASxA Standard DMA Channel A Status Reserved Reserved Reserved Used Reserved Reserved Used Used Used Reserved Used Used

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Operating Modes

Table 11-10. SPMCTLx Control Bit Comparison (Contd)

[Bit] Name Standard Serial Mode I2S and Left-justified Mode Multichannel Mode Packed I2S Mode

[25] DMASxB [2627] [28] DMACHSxA [29] DMACHSxB [3031]

Standard DMA Channel B Status Compatible to legacy programming model Chain Loading DMA Channel A Status Chain Loading DMA Channel B Status Compatible to legacy programming model

Mode Selection
The following sections provide detailed information on operating modes available in some or all protocols. Data Direction The SPTRAN bit enables the channel A or B as a transmitter or receiver. Since one SPORT operates in half-duplex mode, both channels must be either transmit or receive. Otherwise one other SPORT is required for full-duplex mode (see Packed Protocol on page 11-26). The SPORT output data signal is always driven if the serial port is enabled as transmitter (SPTRAN = 1 and SPEN_x= 1) unless it is in multichannel/packed mode and an inactive channel slot occurs. Serial Word Length The serial word length is not unique and is based on the operation mode. Moreover the companding feature limits the word length settings.

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Words smaller than 32 bits are right-justified in the receive and transmit buffers, residing in the least significant bit (LSB) positions (Table 11-11). Table 11-11. Serial Word Length Versus Modes
Mode Standard Serial Mode Multichannel Packed Left justified I 2S Word Length (SLEN) Bits 332 332 332 832 832

Data Types Format Linear transfers occur in the A channel if the A channel is active and companding is disabled (bit 1 of DTYPE) for that A channel. Companded transfers occur if the A channel is active and companding is enabled for that A channel. The multichannel compand select registers (SPxCCSy) specify the transmit and receive channels that are companded when multichannel mode is enabled. Companding is not supported for the B channel. For A and B channels transmit or receive sign extension is selected by bit 0 of DTYPE in the SPCTLx register and is common to all transmit or receive channels. If bit 0 of DTYPE is set, sign extension occurs on selected A channels that do not have companding selected. If this bit is not set, the word contains zeros in the MSB positions. requires a word The compression =for7)transmissionfunction. Ifminimumthe expanlength of 8 ( for proper <7
SLEN SLEN

sion may not work correctly. Sampling Edge Data and frame syncs can be sampled on the rising or falling edges of the serial port clock signals. The CKRE bit of the SPCTLx control registers selects ADSP-214xx SHARC Processor Hardware Reference 11-33

Operating Modes

the sampling edge. For sampling receive data and frame syncs, setting CKRE to 1 in the SPCTLx register selects the rising edge of SPORTx_CLK. When CKRE is cleared (=0), the processor selects the falling edge of SPORTx_CLK for sampling receive data and frame syncs. Note that transmit data and frame sync signals change their state on the clock edge that is not selected. For example, the transmit and receive functions of any two serial ports connected together should always select the same value for CKRE so internally-generated signals are driven on one edge and received signals are sampled on the opposite edge.

Frame Sync Modes

This section describes the different operating modes for the frame sync signal. Framed Versus Unframed Frame Syncs The use of frame sync signals is optional in serial port communications. The FSR (transmit frame sync required) bit determines whether frame sync signals are required. Active low or active high frame syncs are selected using the LFS bit. This bit is located in the SPCTLx control registers. When FSR is set (=1), a frame sync signal is required for every data word. To allow continuous transmission from the processor, each new data word must be loaded into the transmit buffer before the previous word is shifted out and transmitted. When FSR is cleared (=0), the corresponding frame sync signal is not required. A single frame sync is required to initiate communications but it is ignored after the first bit is transferred. Data words are then transferred continuously in what is referred to as an unframed mode. Figure 11-7 illustrates framed serial transfers.

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SPORTx_CLK

FRAMED DATA
B 3 B 2 B 1 B 0 B 3 B 2 B 1 B 0

UNFRAMED DATA

B 3

B 2

B 1

B 0

B 3

B 2

B 1

B 0

B 3

B 2

B 1

B 0

Figure 11-7. Framed Versus Unframed Data Early Versus Late Frame Syncs Frame sync signals can be early or late. Frame sync signals can occur during the first bit of each data word or during the serial clock cycle immediately preceding the first bit. The LAFS bit of the SPCTLx control register configures this option. When LAFS is cleared (=0), early frame syncs are configured. This is the default mode of operation. In this mode, the first bit of the transmit data word is available (and the first bit of the receive data word is latched) in the serial clock cycle after the frame sync is asserted. The frame sync is not checked again until the entire word has been transmitted (or received). In multichannel operation, this is the case when the frame delay is one. If data transmission is continuous in early framing mode (for example, the last bit of each word is immediately followed by the first bit of the next word), the frame sync signal occurs during the last bit of each word. Internally-generated frame syncs are asserted for one clock cycle in early framing mode. When LAFS is set (=1), late frame syncs are configured. In this mode, the first bit of the transmit data word is available (and the first bit of the

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Operating Modes

receive data word is latched) in the same serial clock cycle that the frame sync is asserted. In multichannel operation, this is the case when frame delay is zero. Receive data bits are latched by serial clock edges, but the frame sync signal is checked only during the first bit of each word. Internally-generated frame syncs remain asserted for the entire length of the data word in late framing mode. Externally-generated frame syncs are only checked during the first bit. They do not need to be asserted after that time period. Figure 11-8 illustrates the two modes of frame signal timing.
SPORTX_CLK

LATE FRAME SYNC EARLY FRAME SYNC

DATA

B3

B2

B1

B0

...

Figure 11-8. Normal Versus Alternate Framing Internal Versus External Frame Syncs Both transmit and receive frame syncs can be generated internally or input from an external source. The IFS bit of the SPCTLx control register determines the frame sync source. When IFS is set (=1), the corresponding frame sync signal is generated internally by the processor, and the SPORTx_FS signal is an output. The frequency of the frame sync signal is determined by the value of the frame sync divisor (FSDIV) in the DIVx register.

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When IFS is cleared (=0), the corresponding frame sync signal is accepted as an input on the SPORTx_FS signals, and the frame sync divisors in the DIVx registers are ignored. All frame sync options are available whether the signal is generated internally or externally. Note that for I2S, left-justified, and packed protocols, the MSTR bit selects the clock and frame sync to be together configured as master or slave. Polarity Frame Sync Level Frame sync signals may be active high or active low (for example, inverted). The LFS/LMFS bit in the SPCTLx registers selects the logic level of the frame sync signals as active low (inverted) if set (=1) or active high if cleared (=0). Active high (=0) is the default. Frame Sync Generation A frame sync pulse marks the beginning of the data word. There are some conditions related to this signal which are discussed in the following sections.
Data-Independent Frame Sync

When DIFS = 0 and SPTRAN = 1, the internally-generated transmit frame sync is only output when a new data word has been loaded into the SPORT channels transmit buffer. Once data is loaded into the transmit buffer, it is not transmitted until the next frame sync is generated. This mode of operation allows data to be transmitted only at specific times. When DIFS = 0 and SPTRAN = 0, a receive SPORTx_FS signal is generated only when receive data buffer status is not full. If the internally-generated frame sync is used with DIFS = 0, any core write to the transmit buffer starts the FS and data transfer.

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Operating Modes

The data-independent frame sync mode allows the continuous generation of the SPORTx_FS signal, with or without new data in the buffers. The DIFS bit of the SPCTLx control register configures this option. When DIFS = 1 and SPTRAN = 1, a transmit SPORTx_FS signal is generated regardless of the transmit data buffer status. When DIFS = 1 and SPTRAN = 0, a receive SPORTx_FS signal is generated regardless of the receive data buffer status. Note that the frame sync pulse marks the beginning of the data word. If DIFS is set, the frame sync pulse is issued on time, whether the transmit buffer has been loaded or not. If DIFS is cleared, the frame sync pulse is only generated if the transmit buffer has been loaded. If the receiver demands regular frame sync pulses, DIFS should be set, and the processor should keep loading the transmit buffer on time. For DIFS = 1, the core or DMA controller is responsible for streaming data to/from the buffers. If the real time requirements are not meet accordingly, the DERR_x error channel bit is set.
Channel Dependency

In addition to the DIFS bit, FS generation may be dependent on the buffer status of both channels. In standard protocol the setting of the FS_BOTH bit defines the logical conditions as follows. 0 = A OR B buffer update required for FS generation. 1 = A AND B buffer updates required for FS generation. For multichannel/packed modes the FS_BOTH bit is internally cleared. For I2S/left-justified protocol mode control is done internally as follows. A OR B if one channel enabled. A AND B if both channels enabled.

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Frame Sync Error Detection The SPORTs are capable of detecting underflow and overflow buffer errors as well as frame sync errors. They can detect frame syncs that occur before the last transmission or reception completes. When a serial port is receiving or transmitting, its bit count is set to a word length (for example SLEN = 32 bits). After each clock edge the bit count is decremented. After the word is received/transmitted the bit count reaches zero, and on next frame sync it is set to 32. When active transmission or reception is occurring, the bit count value is non-zero. When a frame sync with a bit count of non-zero is detected, a frame sync error occurs.
Internal Frame Sync Errors

Internal FS errors occur due to programming faults: SLEN > Frame

External Frame Sync Errors

Unexpected external FS errors are detected if: SLEN > Frame Error FS pulse only during a data transmission As shown in Figure 11-9, the frame sync error (which sets the error bit) is triggered when an early frame sync occurs during data transmission or reception or for late frame sync if the period of the frame sync is smaller then the serial word length (SLEN). However, the current transmit/receive operation continues without interruption. Note that a frame sync error is not detected in following cases. When there is no active data transmit/receive (SLEN counter is 0) and the frame sync pulse occurs due to noise in the input signal. It will be considered as a valid frame sync.

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Data Transfers

ERRONEOUS EARLY FS

SLEN COUNTER NOT ZERO => SPERRI INTERRUPT

DRIVE SCLK

DRIVE FS SDRIVE DATA SAMPLED FS SLEN COUNTER SAMPLED DATA 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0

D7

D6

D5

D4

D3

D2

D1

D0

Figure 11-9. Frame Sync Error Detection If there is already a buffer underflow error. The SPORT error logic does not operate (the bit count is not set and decremented) if there is a buffer error. When the frame sync pulse < SCLK period. If the SPORT is operating in TDM slave mode, the frame sync must be at the start of new frame for one SCLK cycle active then inactive. If using duty cycles of for example 50%, the FS error bits (SPERRSTAT) get automatically set.

Data Transfers
Serial port data can be transferred for use by the processor in two different methods:

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Core-driven word transfers DMA transfers between SPORTs and internal or external memory DMA transfers can be set up to transfer a configurable number of serial words between the serial port buffers (TXSPxA, TXSPxB, RXSPxA, and RXSPxB) and internal memory automatically. Core-driven transfers use SPORT interrupts to signal the processor core to perform single word transfers to/from the serial port buffers (TXSPxA, TXSPxB, RXSPxA, and RXSPxB).

Serial Shift Registers

The following sections describe the SPORT shift registers. Output Shift Register The transmit shift register receives from 3 to 32-bit data and serially shifts its data out externally off chip. The transmit shift register is clocked with the driving edge. Input Shift Register The receive shift register receives its data serially from off chip. Internally the receive shift register is byte wide and data received can either be transferred to the FIFO buffer or used in an address comparison. The receive shift register is clocked with the sampling edge.

Buffers
When programming the serial port channel (A or B) as a transmitter (SPTRAN = 1), only the corresponding TXSPxA and TXSPxB buffers become active while the receive buffers RXSPxA and RXSPxB remain inactive. Similarly, when the SPORT channel A and B are programmed as receive-only (SPTRAN = 0) the corresponding RXSPxA and RXSPxB are activated. Do not

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Data Transfers

attempt to read or write to inactive data buffers. If the processor operates on the inactive transmit or receive buffers while the SPORT is enabled, unpredictable results may occur. of Word lengths andless than 32 bits are automatically right-justified in the receive transmit buffers. Transmit Buffers The transmit buffers (TXSP70A, TXSP70B) are the 32-bit transmit data buffers for SPORT70 respectively. These buffers must be loaded with the data to be transmitted if the SPORT is configured to transmit on the A and B channels. The data is loaded automatically by the DMA controller or loaded manually by the program running on the processor core. The transmit buffers act like a two-location buffer because they have a data register plus an output shift register. Two 32-bit words may both be stored in the transmit queue at any one time. When the transmit register is loaded and any previous word has been transmitted, the register contents are automatically loaded into the output shifter. An interrupt occurs when the output transmit shifter has been loaded, signifying that the transmit buffer is ready to accept the next word (for example, the transmit buffer is not full). This interrupt does not occur when serial port DMA is enabled or when the corresponding mask bit in the LIRPTL/IRPTL register is set. Receive Buffers The receive buffers (RXSP70A, RXSP70B) are the 32-bit receive data buffers SPORT70 respectively. These 32-bit buffers become active when the SPORT is configured to receive data on the A and B channels. When a SPORT is configured as a receiver, the RXSPxA and RXSPxB registers are automatically loaded from the receive shifter when a complete word has been received. The data is then loaded to internal memory by the DMA controller or read directly by the program running on the processor core.

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Buffer Packing Received data words of 16 bits or less may be packed into 32-bit words, and transmitted 32-bit words may be unpacked into 16-bit words. Word packing and unpacking is selected by the PACK bit in the SPCTLx control registers. When PACK = 1, two successive received words are packed into a single 32-bit word, and each 32-bit word is unpacked and transmitted as two 16-bit words. The first 16-bit (or smaller) word is right-justified in bits 150 of the packed word, and the second 16-bit (or smaller) word is right-justified in bits 3116. This applies to both receive (packing) and transmit (unpacking) operations. Companding can be used with word packing or unpacking. When serial port data packing is enabled, the transmit and receive interrupts are generated for the 32-bit packed words, not for each 16-bit word. data packed into 32-bit words and stored When 16-bit received in theisprocessors internal memory, the in normal word space 16-bit words can be read or written with short word space addresses.
Companding

Since the values in the transmit and receive buffers are actually companded in place, the companding hardware can be used without transmitting (or receiving) any data, for example during testing or debugging. This operation requires one peripheral clock cycle of overhead, as described below. For companding to execute properly, program the SPORT registers prior to loading data values into the SPORT buffers. Note that companding is hard coded for the A channels only and is directional relative to the SPORT number (0, 2, 4, 6 transmit and 1, 3, 5, 7 receive).

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Data Transfers

Buffer Status Serial ports provide status information about data buffers via the DXS_A and DXS_B status bits and error status via DERR_x bits in the SPCTL register. Depending on the SPTRAN setting, these bits reflect the status of either the TXSPxy or RXSPxy data buffers. If your program causes the core processor to attempt to read from an empty receive buffer or to write to a full transmit buffer, the access is delayed until the buffer is accessed by the external I/O device. This delay is called a core processor hang. If you do not know if the core processor can access the receive or transmit buffer without a hang, the buffers status should be read first (in SPCTLx) to determine if the access can be made. The status bits in SPCTLx are updated during reads and writes from the core processor even when the serial port is disabled. If the SPORTs are should not write to the inactiveconfigured as transmitters, programscore keeps and buffers. If the
TXSPxA TXSPxB

writing to the inactive buffer, the transmit buffer status becomes full. This causes the core to hang indefinitely since data is never transmitted to the output shift register. If the SPORTs are configured as receivers, programs should not read from the inactive RXSPxA and RXSPxB buffers. If the core keeps reading from to the inactive buffer, the receive buffer status becomes empty. This causes the core to hang indefinitely since new data is never received via the input shift register. status bits in are Thecore processor even whenupdated duringisreads and writes from the the serial port disabled.
SPCTLx

Buffer Errors The following sections describe error conditions in the buffers. For more information see also Interrupts on page 11-51.

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Reception Error

Two complete 32-bit words can be stored in the receive buffer while a third word is being shifted in. The third word overwrites the second if the first word has not been read out (by the processor core or the DMA controller). When this happens, the receive overflow status bit is set in the serial port control register. Almost three complete words can be received without the receive buffer being read before an overflow occurs. The overflow status is generated on the last bit of the third word. The DERR_x status bits are sticky and are cleared only by disabling the serial port.
Transmission Error

Whenever the SPORT is required to transmit and the transmit buffer is empty. the underflow status bit is set (DERR_x). The DERR_x status bits are sticky and are cleared only by disabling the SPORT or by writing to the corresponding RW1C bits in the SPERRCTL register. Flushing Buffers The SPORT buffers are flushed by disabling the serial port or by writing to the RW1C error bits in the SPERRCTL register.

Core Transfers
The following sections provide information on core driven data transfers. Individual data words may also be transmitted and received by the serial ports, with interrupts occurring as each 32-bit word is transmitted or received. When a serial port is enabled and DMA is disabled, the SPORT interrupts are generated whenever a complete 32-bit word has been received in the receive buffer, or whenever the transmit buffer is not full. When performing core-interrupt driven access, (FS master DIFS=1 or external FS), the FS is generated (DIVx register) regardless of buffer status. Therefore the buffer access is in the responsibility of the application

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Data Transfers

which must meet real time requirements. The enabled interrupt is triggered if the transmit buffer has vacancy or the receive buffer new data. Any real time violation can be reported with the DERR-x bits to trigger an SPERRI exception. If interrupts are disabled, to avoid hanging the processor core, check the buffer's full/empty status when the processor core's program reads a word from a serial port's receive buffer or writes a word to its transmit buffer. The full/empty status can be read in the DXS bits of the SPCTLx register. Reading from an empty receive buffer or writing to a full transmit buffer causes the processor to hang, while it waits for the status to change. When performing core-driven transfers with DIFS=0, the first buffer access starts FS generation. This mode of operation allows data to be transmitted only at specific times. If using multichannel/packed mode active channel section registers should be enabled to prevent any core hang situations.

DMA Transfers
SPORT DMA provides a mechanism for receiving or transmitting an entire block of serial data before the interrupt is generated. When serial port DMA is not enabled, the SPORT generates an interrupt every time it receives or starts to transmit a data word. The processors on-chip DMA controller handles the DMA transfer, allowing the processor core to continue running until the entire block of data is transmitted or received. Service routines can then operate on the block of data rather than on single words, significantly reducing overhead. Each transmitter and receiver has its own DMA registers. The same DMA channel drives the left and right I2S channels for the transmitter or the receiver. The software application must stop multiplexing the left and right channel data received by the receive buffer, because the left and right data are interleaved in the DMA buffers.

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The SPORT DMA channels are assigned by default higher priority (fixed DMA channel priority enabled by default DCPR bit in SYSCTL register) than all other DMA channels (for example, the SPI port) because of their relatively low service rate and their inability to hold off incoming data. Having higher priority causes the SPORT DMA transfers to be performed first when multiple DMA requests occur in the same cycle. The serial port DMA channels are numbered and prioritized as shown in Table 3-29 on page 3-39. Due to the possible priority of other DMA channels if the DMA controller is not able to load the transmit buffer with the actual value from memory or read the actual value from receive buffer, then the previous value is transmitted/received. The error status DERR_x bit will report any exception by using the SPORT error interrupt (SPERRI). Note if the DMA transfers have completed, the FS continues to drive. For standard serial, I2S and left-justified modes, the frame sync generation is optional. SPORT DMA Group Priority Each SPORT module has 2 DMA channels (A and B). Two SPORT modules represent a SPORT group (SPORT10, SPORT32, SPORT54 and SPORT76) for DMA access. When a SPORT group (for example 4AB and 5AB channels) have data ready, the channel arbitrates by fixed priority method odd over even SPORT and A over B channel (which is the first arbitration stage). The winning channel requests the DMA bus arbiter to get control of the peripheral DMA bus (2nd stage of arbitration) or to the SPEP bus arbiter if access to external memory is required. For the I/O processor, only the SPORT groups are requesting for the peripheral bus. For more information, see Peripheral DMA Arbitration on page 3-36.

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Data Transfers

Standard DMA To set up a serial port DMA channel, write a set of memory buffer parameters to the SPORT DMA parameter registers as shown in Table 3-15 on page 3-15. Load the IISPxy, IMSPxy, and CSPxy registers with a starting address for the buffer, an address modifier, and a word count, respectively. The register contains the internal memory address for transfers to internal memory and the external memory address for transfers to external memory. For DMA-driven transfers, the serial port logic performs the data transfer from internal memory to/from the appropriate buffer depending on the SPTRAN bit setting. When both SPORT A and B channels are used in I2S/left-justified mode with standard DMA enabled, then the DMA count should be the same for both channels. Each SPORT DMA channel has a DMA enable bit (SDEN_A and SDEN_B) in its SPCTLx register. When DMA is disabled for a particular channel, the SPORT generates an interrupt every time it receives a data word or whenever there is a vacancy in the transmit buffer. For more information, see Table 3-15 on page 3-15. Once serial port DMA is enabled, the processors DMA controller automatically transfers received data words in the receive buffer to the buffer in internal or external memory, depending on the transfer type. Likewise, when the serial port is ready to transmit data, the DMA controller automatically transfers a word from internal or external memory to the transmit buffer. The controller continues these transfers until the entire data buffer is received or transmitted. Therefore, set the direction bit, the serial port enable bit, and DMA Enable bits before initiating any operations on the SPORT data buffers. If the processor operates on the inactive transmit or receive buffers while the SPORT is enabled, it can cause unpredictable results.

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Although the word lengths can be 3 to 32 bits, transmitting or receiving words smaller than 7 bits at the full clock rate of the serial port may cause incorrect operation when DMA chaining is enabled. Chaining locks the processor's internal I/O bus for several cycles while the new transfer control block (TCB) parameters are being loaded. Receive data may be lost (for example, overwritten) during this period. Moreover, transmitting or receiving words smaller than five bits may cause incorrect operation when all the DMA channels are enabled in standard DMA mode. DMA Chaining Each channel also has a DMA chaining enable bit (SCHEN_A and SCHEN_B) in its SPCTLx control register. Each SPORT DMA channel also has a chain pointer register (CPSPxy). The CPSPxy register functions are used in chained DMA operations. In chained DMA operations, the processors DMA controller automatically sets up another DMA transfer when the contents of the current buffer have been transmitted (or received). The chain pointer register (CPSPxy) functions as a pointer to the next set of buffer parameters stored in external or internal memory. The DMA controller automatically downloads these buffer parameters to set up the next DMA sequence. For more information on SPORT DMA chaining, see Chained DMA on page 3-31. DMA chaining occurs independently for the transmit and receive channels of each serial port. Each SPORT DMA channel has a chaining enable bit (SCHEN_A or SCHEN_B) that when set (= 1), enables DMA chaining and when cleared (= 0), disables DMA chaining. Writing all zeros to the address field of the chain pointer register (CPSPxy) also disables chaining.

The chain pointer register should be cleared first before chaining is enabled.
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Data Transfers

The I/O processor responds by auto-initializing the first DMA parameter registers with the values from the first TCB, and then starts the first data transfer. Note that in chained mode for DIFS = 0, setting the SPEN bit starts first loading the first TCB which fills up the transmit buffer. Since the buffer is non empty the first FS is driven. DMA Chain Insertion Mode It is possible to insert a single SPORT DMA operation or another DMA chain within an active SPORT DMA chain. Programs may need to perform insertion when a high priority DMA requires service and cannot wait for the current chain to finish. When DMA on a channel is disabled and chaining on the channel is enabled, the DMA channel is in chain insertion mode. This mode allows a program to insert a new DMA or DMA chain within the current chain without effecting the current DMA transfer. Chain insertion mode operates the same as non-chained DMA mode. When the current DMA transfer ends, an interrupt request occurs and no TCBs are loaded. This interrupt request is independent of the PCI bit state. Chain insertion should not be set up as an initial mode of operation. This mode should only be used to insert one or more TCBs into an active DMA chaining sequence. For more information, see Enter DMA Chain Insertion Mode on page 11-58. SPORT DMA to External Memory In previous SHARC processors, transferring data from a SPORT to external memory required placing that data temporarily in internal memory and then transferring it to external memory using DMA. The ADSP-214xx processors (Figure 11-2 on page 11-15) allow direct DMA

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Serial Ports (SPORTs)

transfers between SPORTs and external memory which removes this overhead, freeing up the core and internal memory for other peripherals. The SPORT DMA index and chain pointer registers have been expanded to be able to hold the external memory address.
SPORT SPEP Bus Priority

The SPORT groups which have external memory DMA access must arbitrate first for the SPEP bus which connects the SPORT to the external port interface. The priority for the SPEP bus is optional, the DCPR bit (SYSCTL register) defines if the priority is fixed or rotating. For the I/O processor, the 4 DMA channels are considered as a group and one arbitration request. For more information, see Peripheral DMA Arbitration on page 3-36.

Interrupts
Table 11-12 provides an overview of SPORT interrupts. Table 11-12. SPORT Interrupt Overview
Default Programmable Interrupt SP1I = P3I SP3I = P4I SP5I = P5I SP0I = P7I SP2I = P8I SP4I = P9I SP7I = P11I SP6I = P16I Sources Masking Service

DMA complete Core buffer service request Internal transfer completion Access completion Buffer underflow Buffer overflow Unexpected frame sync

N/A

RTI instruction

RW1C to SPERRCTLx + RTI instruction

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Interrupts

Sources
The SPORT module generates three local interrupt signalsone for each data channel (A and B) signal and a third used for error detection. The data channel interrupts are both logically ORed into one SPORT interrupt signal and the error detection interrupt is logically ORed with all SPORTs into one signal, SPERRI. The serial ports generate interrupts as described in the following sections. Core Buffer Service Request When DMA is disabled the processor core may read from the RXSPx buffer or write to the TXSPx buffer. An interrupt is generated when the receive buffer is not empty or the transmit buffer is not full. An interrupt occurs when the output transmit shifter has been loaded, signifying that the transmit buffer is ready to accept the next word (for example, the transmit buffer is not full). This interrupt does not occur when serial port DMA is enabled. An interrupt is generated when the receive buffer has been loaded with a received word (for example, the receive buffer is not empty). Data Buffer Packing When serial port data packing is enabled (PACK = 1 in the SPCTLx registers), the transmit and receive interrupts are generated for 32-bit packed words, not for each 16-bit word. DMA Complete When serial port data packing is enabled (PACK = 1 in the SPCTLx registers), the transmit and receive interrupts are generated for 32-bit packed words, not for each 16-bit word.

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Internal Transfer Complete Interrupts can be used to indicate the completion of the transfer of a block of serial data when the serial ports are configured for DMA. Each DMA channel has a count register (CSPxA/CSPxB), which must be initialized with a word count that specifies the number of words to transfer. The count register decrements after each DMA transfer on the channel. When the word count reaches zero, the SPORT generates an interrupt, then automatically stops the DMA channel. Access Complete The SPORT DMA interrupt can be programmed to be generated either when the transmit DMA count is expired (ETDINTEN = 0) or when the last bit of the last word is shifted out (ETDINTEN = 1). For chained DMA where ETDINTEN = 1: If PCI = 0, the interrupt is generated after that last word of last DMA block in the chain is shifted out. If PCI = 1, the interrupt is generated when the DMA counter expires for the initial DMA blocks in the chain and the last bit of the last word is shifted out for the last DMA block in the chain (CP is nonzero). For receive DMA, the interrupt behaves in the same way, independent of the value of ETDINTEN bit. Chained DMA For chained DMA, if the PCI bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the PCI bit is set (= 1), then a DMA interrupt is generated for each TCB.

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Interrupts

Buffer Over/Underflow Each SPORT can generate an interrupt if a channel buffer (DERRA_STAT, DERRB_STAT bits) or frame sync error (FSERR_STAT bit) occurs. These bits are located in the SPERRCTLx register. Similar to previous SHARC processors, the SPORTs can return the status of data buffer underflow and overflow conditions. Additionally, the SPORTs can also detect unexpected frame syncs occurring early, even before the last transmit or receive completes. An error interrupt is triggered on a data underflow/overflow, or frame sync error in their respective channels. Unexpected Frame Sync Errors Additionally, the SPORTs can also detect frame syncs that are occurring early, even before the last transmit or receive completes.

Masking
The SPORTxI signals are routed by default to programmable interrupts as described in the list below. To service SPORTs 1, 3, 5, 6, unmask (set = 1) the P3I, P4I, P5I, and P16I bits in the IMASK register. To service SPORTs 0, 2, 4, 7, unmask (set = 1) the P7IMSK, P8IMSK, P9IMSK, P11IMSK bits in the LIRPTL register. To service the SPERRI interrupt, unmask (set = 1) the SPERRI bit in the IMASK register. For example:
bit set IMASK P3I; bit set LIRPTL P7IMSK; bit set IMASK SPERRI; /* unmasks P3I interrupt */ /* unmasks P7I interrupt */ /* unmasks SPERRI interrupt */

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Similar to previous SHARC processors, the SPORTs report the status of the data buffers (transmit and receive). The DERRx_EN bits (SPERRCTLx register) enable the specific A or B channels. Additionally, the SPORTs can detect frame syncs that are occurring early, even before the last transmit or receive completes. To detect these errors, enable the FSERR_EN bit in the SPERRCTLx) register. The error interrupts must be unmasked by setting the SPERRI bit in the IMASK register. occur on clock SPORT interrupts the serial the second peripheraldriven(out. ) after the last bit of word is latched in or
PCLK

Service
Both the A and B channels share a common interrupt vector in the interrupt-driven data transfer mode, regardless of whether they are configured as a transmitter or receiver. The SPORT generates an interrupt when the transmit buffer has a vacancy or the receive buffer has data. To determine the source of an interrupt, programs must check the transmit or receive data buffer status bits (DXS_A, DXS_B) in the SPCTLx registers. For DMA programs the corresponding status bits in the SPMCTLx registers must be checked. Note that in most cases, if both channels are enabled with the same DMA count, there is no need to check the status since both channel interrupts are generated close to each other.

Standard DMA does not function properly in I2S/left-justified mode when two channels (A and B) are enabled with different DMA count values. In this case, the interrupt is generated for the least count only. If both the A and B channels of the SPORTs are used in I2S/left-justified mode with DMA enabled, then the DMA count value should be the same for both channels. This does not apply to chained DMA.

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Throughput

One error interrupt is connected for all SPORTs together. Therefore, when an error occurs, programs should first read the global error status interrupt register, SPERRSTAT, to identify which SPORT caused the error condition. The next step requires a RW1C (write 1 to clear) operation to the corresponding error bit in the local SPERRCTLx register. This operation also clears the SPERRSTAT bits. For frame sync errors, clear the FSERR_STAT bit (SPERRCTL register) which resets both channel bits SPENx or MCEx. For buffer channel errors, clear the DERRx_STAT bit (SPERRCTL register) which resets the channel bits ( SPENx or MCEx) and DERRx. For example:
ISR_SPERRI: ustat1 = dm(SPERRSTAT); bit TST ustat1 SP2_DERRA; If TF jump SP2_ERROR; SP2_ERROR: ustat3=dm(SPERRCTL2); bit set ustat3 DERRA_STAT; dm(SPERRCTL2)=ustat3; r5=dm(SPCTL2); rti; /* RW1C buffer status error bit */ /* dummy read for latency */ /* read error status from SP7-0 */ /* identify SPORT and cause */

Throughput
When the SPORT is operating in half-duplex mode, and both channels (A and B) are active, each SPORT has 112 M bit/s maximum total throughput.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

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Write Effect Latency For details on write effect latency, see the SHARC Processor Programming Reference. SPORT Effect Latency After a write to a SPORT control register, control and mode bit changes take effect in the second serial clock cycle (SCLK). The SPORT is ready to start transmitting or receiving three serial clock cycles after it is enabled in the SPCTLx control register. No serial clocks are lost from this point on. This delay also applies in slave mode (external clock/frame sync) for synchronization. Multichannel and packed operation is activated three serial clock cycles (SCLK) after the MCEA or MCEB bits are set. Internally generated frame sync signals activate four serial clock cycles after the MCEA or MCEB bits are set.

Programming Model
The section describes some programming procedures that are used to enable and operate the SPORTs.

Setting Up and Starting DMA Master Mode

To set up and initiate a master DMA operation, use the following procedure. 1. Clear the SPORT control registers (SPCTLx/SPMCTLx) which flushes the buffers. 2. Write to the appropriate DIVx register, setting the master clock and frame sync ratios.

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Programming Model

3. Configure all DMA parameter registers (index, modify and count). 4. Configure the SPORT protocol mode and enable DMA operation (SPCTLx).

Setting Up and Starting Chained DMA

To set up and initiate a chain of DMA operations, use the following procedure. 1. Clear the chain pointer register. 2. Clear the SPORT control registers (SPCTLx/SPMCTLx) which flushes the buffers. 3. For internal memory transfers, set up all TCBs in internal memory. 4. Write the address containing the index register value of the first TCB to the chain pointer register, which starts the chain. 5. Write to the SPCTLx register by setting the DMA enable bit to one and the chaining enable bit to one. Setting these bits loads the DMA parameter registers.

Enter DMA Chain Insertion Mode

Chain insertion lets the SPORTs insert a single SPORT DMA operation or another DMA chain within an active SPORT DMA chain. 1. Enter chain insertion mode by setting SDENx = 0 and SCHENx = 1 in the channels DMA control register. The DMA interrupt indicates when the current DMA sequence is complete. 2. Copy the address currently held in the chain pointer register to the chain pointer position of the last TCB in the chain that is being inserted.

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Serial Ports (SPORTs)

3. Write the start address of the first TCB of the new chain into the chain pointer register. 4. Resume chained DMA mode by setting SDENx = 1 and SCHENx = 1.

Setting Up and Starting Multichannel Mode

Unlike standard, left justified and I2S protocols, configuring the SPORTs for TDM/packed protocol requires programming two control registers. The SPCTL register is responsible for chained DMA control settings while the SPMCTL register is responsible for TDM control settings. As soon as the SPCTL register (SPENx bits cleared, DEN/CHEN bits set) and the chain pointer register are programmed, TCB loading (refer to IOP effect latency) starts which fills up the transmit buffer. However these samples are not transmitted until the MCEx bit (SPMCTL register) is set. Note that the DIFS bit is hard wired to 1 for TDM/packed protocols, setting the MCE bit in master mode automatically generates the FS. Use the control registers (SPCTLx/SPMCTLx) and active channel selection registers (SPxCSy and SPxCCSy) to configure the serial ports to run in multichannel mode as follows. For proper data alignment on sports in multichannel mode, the multichannel enable bit must be set last since the DIFS bit is hard wired to 1. 1. Clear all control registers (SPCTLx/y and SPMTCLxy) and chain pointer registers. 2. For DMA operation, configure the DMA parameter registers (Index, Modify and Count). For DMA chaining setup the TCBs according to the chain. 3. Configure the receiver SPORTx control register of SPORT pair (SPCTLx) and enable the standard/chaining bits. Do not enable the SPENx bits.

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Programming Model

4. Configure the transmitter SPORTx control register of a SPORTxy pair (SPCTLx) and enable the DMA/DMA chaining. 5. Configure the transmitter SPORTx control register of a SPORT pair (SPCTLx) and enable the standard/chaining bits. Do not enable the SPENx bits. 6. For DMA chaining, initialize the chain pointer register with the index register for the first chain to start chaining, filling up the transmit buffer. 7. Poll DMA chain loading complete status DMACHSxA bits OR the transmit buffer status DXS bit to be full. 8. Configure the number of channels, frame delay and enable MCEx bits for multichannel/packed mode for the SPORT pair (SPMCTLx). Multichannel Mode Backward Compatibility In previous SHARC models, the serial port pair used the same control register (SPMCTL01) to program multichannel mode. In the ADSP-214xx processors, this register is simply renamed to SPMCTL0 and a new identical register, SPMCTL1 has been added. Programs using the older code simply need to change from the SPMCTL01 register to the SPMCTL0 register or the SPMCTL1 register. The following steps should be taken to port the code to the ADSP-214xx products. 1. Instead of programming SPMCTLxy only, program both SPMCTLx and SPMCTLy registers. 2. In previous ADSP-2136x processors the data direction bit in the SPCTL register is hard coded in multichannel mode (where the even port is always the transmitter and the odd port is always the

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receiver). From the ADSP-21367/8/9 processors onward, the direction (SPTRAN bit) is honored and therefore should be set as required. 3. Routing models for hard coded multichannel pairs use the odd RX SPORT for the clock and frame sync. The TDV signal was multiplexed with the even TX SPORT frame sync output. From the ADSP-21367/8/9 processors onward, these limitations no longer apply. All SPORTs operate completely independently. Every SPORT requires the clock and frame sync to be routed. The TDV output signal is an independent output signal in the SRU unit.

Programming Packed Mode

Since packed mode is implemented on top of multichannel mode, programming this mode is the same as programming multichannel mode. Use the serial port control (SPCTLx) and multichannel selection registers (SPMCTLx) to configure the serial ports to run in packed mode as follows. 1. Clear all control registers (SPCTLx and SPMCTLx) 2. Configure the multichannel channel select registers (SPxCSy or SPxCCSy). 3. Set the OPMODE, CKRE bits in the SPCTLx register and (ICLK, IFS bits for master mode) to operate packed mode. The L_FIRST bit allows swapping left and right channels. Note the CKRE bit must be set in both receiver and transmitter. Clear the LSBF bit to run in packed mode. 4. Clear the
LSBF

bit to run in packed mode.

5. To emulate I2S in packed mode, set the MFD bit field to one and the NCH bit field according to the channels in the SPMCTLx register.

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Programming Model

The MFD bit field and the L_FIRST bit allow programs to manipulate the timing as follows. The MFD bit field selects the data delay in SCLK cycles after the frame sync occurred. The L_FIRST bit allows to swap the left and right channels.

External Frame Sync Operation

There are two procedures which allow programs to save SPORT initialization during an inactive frame sync: Read the DAI_PIN_STAT register of the frame sync to get the level prior to starting SPORT configuration. Route a MISCA register input to the external frame signal (rising or falling edge) as an interrupt trigger to generate an interrupt to start SPORT configuration. the register In the ADSP-214xx processors the ofbit instate of the external allows SPORT initialization regardless the
FSED SPCTLN

frame sync. The SPORT starts the transfer on the next valid rising or falling edge. This makes it easy to release the state machine and frame sync generators from reset. For example, if you configure the SPORT for a rising edge frame sync, there is no need to wait for a low/high level on the frame sync pin before releasing the SPORT state machine from reset.

Companding As a Function
Since the values in the transmit and receive buffers are actually companded in place, the companding hardware can be used without transmitting (or receiving) any data, for example during testing or debugging. This operation requires one peripheral clock cycle of overhead, as

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described below. For companding to execute properly, program the SPORT registers prior to loading data values into the SPORT buffers. To compress data in place without transmitting use the following procedure. 1. Set the SPTRAN bit to 1 in the SPCTLx register. The SPEN_A and SPEN_B bits should be = 0. 2. Enable companding in the DTYPE field of the SPCTLx transmit control register. 3. Write a 32-bit data word to the transmit buffer. Companding is calculated in this cycle. 4. Wait two cycles. Any instruction not accessing the transmit buffer can be used to cause this delay. This allows the serial port companding hardware to reload the transmit buffer with the companded value. 5. Read the 8-bit compressed value from the transmit buffer. To expand data in place, use the same sequence of operations with the receive buffer instead of the transmit buffer. When expanding data in this way, set the appropriate serial word length (SLEN) in the SPCTLx register. With companding enabled, interfacing the serial port to a codec requires little additional programming effort. If companding is not selected, two formats are available for received data words of fewer than 32 bitsone that fills unused MSBs with zeros, and another that sign-extends the MSB into the unused bits.

Debug Features
The following sections provide information on debugging features available with the serial ports.

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SPORT Loopback
When the SPORT loopback bit, SPL (bit 12), is set in the SPMCTLx register, the serial port is configured in an internal loopback connection as follows: SPORT0/SPORT1 work as a pair, SPORT2/SPORT3 work as a pair, SPORT4/SPORT5 work as a pair and SPORT6/SPORT7 work as a pair. Pairings of SPORTs (01, 23, 45 and 67) is only required for loopback mode which is valid for all non multichannel modes. bit all non The modeapplies toprogramsmultichannel modes. internally and The loopback enables to test the serial ports
SPL

to debug applications. In loopback mode, either of the two paired SPORTS can be transmitters or receivers. One SPORT in the loopback pair must be configured as a transmitter; the other must be configured as a receiver. For example, SPORT0 can be a transmitter and SPORT1 can be a receiver for internal loopback. Or, SPORT0 can be a receiver and SPORT1 can be the transmitter when setting up internal loopback. LoopBack Routing The SPORTs support an internal loopback mode by using the SRU. For more information, see Loopback Routing on page 10-39.

Buffer Hang Disable (BHD)

To support debugging buffer transfers, the processors have a buffer hang disable (BHD) bit. When set (= 1), this bit prevents the processor core from detecting a buffer-related stall condition, permitting debugging of this type of stall condition.

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The Input Data Port (IDP) compromises two units: the serial input port (SIP) and the parallel data acquisition port (PDAP). Located inside the DAI of the SHARC processor the IDP provides an efficient way of transferring data from DAI pin buffers, the external port, the asynchronous sample rate converters (ASRC) and the S/PDIF transceiver to the internal memory of SHARC. The IDP specifications are shown in Table 12-1. Table 12-1. IDP Port Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex No Yes Yes No No No Yes Yes No No No Yes No No N/A Yes Yes (External Port) Yes No No N/A Yes SIP PDAP

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Features

Table 12-1. IDP Port Specifications (Contd)

Feature Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Max Clock Operation Yes Yes Yes 8 No No No fPCLK/4 Yes Yes Yes 1 No No No fPCLK/4 SIP PDAP

Features
The following list describes the IDP features. The IDP provides a mechanism for a large number of asynchronous channels (up to eight). The IDP supports industry standard data formats, I2S, Left-justified and Right-justified for serial input ports. The PDAP supports four data packing modes for parallel data. The PDAP supports a maximum of 20-bits. Provides two data transfer types, through DMA or interrupt driven transfer by core.

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Pin Descriptions
Table 12-2 provides descriptions of the IDP pins used for the serial interface port. Table 12-2. SIP Pin Descriptions
Internal Node IDP70_CLK_I IDP70_FS_I I/O I I Description Serial Input Port Receive Clock Input. This signal must be generated externally and comply to the supported input formats. Serial Input Port Frame Sync Input. The frame sync pulse initiates shifting of serial data. This signal must be generated externally and comply to the supported input formats. Serial Input Port Data Input. Unidirectional data pin. Data signal must comply to the supported data formats.

IDP70_DAT_I

Table 12-3 provides descriptions of the IDP pins used for the parallel interface port. Table 12-3. PDAP Pin Descriptions
Internal Nodes PDAP_CLK_I Type I Description Parallel Data Acquisition Port Clock Input. Positive or negative edge of the PDAP clock input is used for data latching depending on the IDP_PDAP_CLKEDGE bit (29) of the IDP_PP_CTL register. Note that input has multiplexed. Parallel Data Acquisition Port Frame Sync Input. The PDAP hold signal determines whether the data is to be latched at an active clock edge or not. When the PDAP hold signal is HIGH, all latching clock edges are ignored and no new data is read from the input pins. The packing unit operates as normal, but it pauses and waits for the PDAP hold signal to be deasserted and waits for the correct number of distinct input samples before passing the packed data to the IDP FIFO. Note that the input has multiplexed control. Parallel Data Acquisition Port Data Input. The PDAP latches 20-bit parallel data which where packed into 32-bits by using different packing. Note that input has multiplexed control.

PDAP_HOLD_I

PDAP_DATA

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SRU Programming

Table 12-3. PDAP Pin Descriptions (Contd)

Internal Nodes PDAP_STRB_O Type O Description Parallel Data Acquisition Port Clock input. The PDAP packing unit asserts the output strobe whenever there is 32-bit data available for transfer to the IDP FIFO. The width of this pulse is equal to 2 x PCLK cycles. This signal can be used to synchronize external requests for new PDAP data. Note that input has multiplexed control.

Table 12-4 provides descriptions of the pin multiplexing between DAI and external port. For more information, see Pin Multiplexing on page 24-28. Table 12-4. Pin Multiplexing between DAI and External Port
Signal Serial Clock Frame Sync Data Strobe Out DAI IDP0_CLK_I IDP0_FS_I DAI_PB201 PDAP_STRB_O External Port ADDR[2] ADDR[3] ADDR[234] ADDR[0]

SRU Programming
The SRU (signal routing unit) needs to be programmed in order to connect the IDP to the SIP/PDAP as shown in Table 12-5. Table 12-5. SIP SRU Signal Connections
SIP Source No Sources DAI Connection Group A Group B Group C SIP Destination IDP70_CLK_I IDP70_DAT_I IDP70_FS_I

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Input Data Port (SIP, PDAP)

Table 12-6 shows the signal connections when using the PDAP on the DAI pins. Table 12-6. PDAP SRU Signal Connections
PDAP Source DAI Connection Group A Group B Group C PDAP_STRB_O Group D PDAP Destination PDAP_CLK_I IDP0_DAT_I PDAP_HOLD_I

Register Overview
This section provides brief descriptions of the major registers. For complete information see Input Data Port Registers on page A-172. IDP Control Registers (IDP_CTLx). The ADSP-2136x and ADSP-2137x SHARC processors have two IDP control registers. The IDP_CTL1-0 registers are used to control the SIP operations. PDAP Control Register (IDP_PP_CTL). The register (shown in Figure 12-1) is used to control all PDAP operations. IDP Status Register (DAI_STAT). Returns different types of status for SIP/PDAP core and DMA operations.

Clocking
The fundamental timing clock of the IDP module is peripheral clock/4 (PCLK/4). The IDP SIP/PDAP operates in slave mode only. The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

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Functional Description

Functional Description
The IDP provides up to eight serial input channelseach with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive audio channels in I2S, left-justified, or right-justified mode. One frame sync cycle indicates one 64-bit left-right pair, but data is sent to the FIFO as 32-bit words (that is, one-half of a frame at a time). Data transfer occurs on all channels from the SIP/PDAP to the IDP FIFO with fixed priority, from channel 0 (highest priority) to channel 7 (lowest priority). Transfers from this FIFO to internal memory can be performed either via DMA or by core interrupts. is shared by All other IDP channel 0correspondingSIP0 and PDAP.FIFO. 7 SIPs are connected to IDP channel of The DMA engine of the IDP implements DMA for all the 8 channels. It has eight sets of DMA parameter registers for 8 channels. Data from channel 0 is directed to internal memory location controlled by set of registers for channel 0 and so on. The parallel data is acquired through the parallel data acquisition port (PDAP) which provides a means of moving high bandwidth data to the cores memory space. The data may be sent to memory as one 32-bit word per input clock cycle or packed together (for up to four clock cycles worth of data). Figure 12-1 provides a graphical overview of the input data port architecture. Notice that each channel is independent and contains a separate clock and frame sync input. provides pump The IDPsince it is an easy way tothan theserial data into on-chip memory less complex traditional SPORT module, limited to unidirectional slave transfers only.

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Input Data Port (SIP, PDAP)

20-BIT DATA CONTROL

IDP
PDAP
CHANNEL 0

Serial Input Port

IDP_CLK0_I IDP INPUT CHANNEL ARBITER IDP_FS0_I IDP_DAT0_I SIP0 SERIAL TO PARALLEL 32-BIT CONVERSION

IOD0 BUS

PERIPHERAL CORE BUS

IDP_CLKx_I IDP_FSx_I IDP_DATx_I SIPx (x = 6 - 1) SERIAL TO PARALLEL 32-BIT CONVERSION CHANNEL x

IDP_FIFO 8 x 32-BIT

IDP_CLK0_7 IDP_FS0_7 IDP_DAT0_7 SIP7 SERIAL TO PARALLEL 32-BIT CONVERSION CHANNEL 7

Figure 12-1. Input Data Port

Operating Modes
The following sections provide information on the various operation modes used by the PDAP module. The IDP has access to the IDP FIFO in the three modes listed below. The bit settings that configure these modes are shown in Table 12-7. Core mode (SIP/PDAP) DMA mode (SIP/PDAP) DMA ping-pong mode (SIP/PDAP)

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Operating Modes

Table 12-7. IDP Operation Modes

IDP_CTL0 Global Control IDP Operation Modes Core SIP70 Core PDAP DAI Core PDAP EP DMA SIP70 DMA PDAP DAI DMA PDAP EP DMA Ping-pong SIP70 DMA Ping-pong PDAP DAI DMA Ping-pong PDAP EP IDP_EN 1 1 1 1 1 1 1 1 1 IDP_CTL1 Channel Control IDP_PP_CTL PDAP Control PDAP_PP _SELECT 0 0 1 0 0 1 0 0 1

IDP_ IDP_ENx IDP_ IDP_PINGx IDP_ DMA_EN DMA_ENx PDAP_EN 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1

PDAP Port Selection

The input to channel 0 of the IDP is multiplexed, and may be used either in the serial mode or in a direct parallel input mode. Setting the PDAP_EN bit high disables the connection of SIP0 to channel 0 of the FIFO. The data inputs can come either from the DAI pins or the external port ADDR pins. This is selected by the PDAP_PP_SELECT bit in the PDAP_CTL register. Figure 12-2 illustrates the data flow for IDP channel 0, where either the PDAP or serial input can be selected.

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Input Data Port (SIP, PDAP)

ADDR2 PDAP_CLK_I IDP0_CLK_I

PDAP Control
ADDR3 PDAP_HOLD_I IDP0_FS_I PDAP_STRB_O

DAI UNIT

ADDR2

ADDR23-4

INPUT DATA LATCH CHANNEL 0

DATA MASK UNIT

DAI_PB20-1

32-BIT DATA PACKING UNIT SIP DATA

IDP_FIFO

Figure 12-2. PDAP Port (Detail of IDP Channel 0)

Data Hold
When the PDAP_HOLD signal is high, all latching clock edges are ignored and no new data is read from the input pins. The packing unit operates as normal, but it pauses and waits for the PDAP_HOLD signal to be deasserted and waits for the correct number of distinct input samples before passing the packed data to the FIFO. Figure 12-3 on page 12-11 through Figure 12-5 on page 12-13 show different packing modes including valid data hold inputs. As shown in the figures, PDAP_DATA and PDAP_HOLD are driven by the inactive edges of the clock (falling edge in the above figures) and these signals are sampled by the active edge of the clock (rising edge in the figures).

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Operating Modes

PDAP Data Masking

For input data widths less than 20, inputs are aligned to the MSB pins. Additionally all PDAP inputs can be masked (IDP_PDAP_CTL register) to form user specific data streams from any input pins. Clearing the MASK bits (=0) disables data from the corresponding DAI or external port pin.

PDAP Data Packing

Multiple latched parallel sub word samples may be packed into 32-bit words for efficiency. The frame sync input is used to hold off latching of the next sample (that is, ignore the clock edges). The data then flows through the FIFO and is transferred by a dedicated DMA channel into the cores memory as with any IDP channel. As shown in Figure 12-2, the PDAP can accept input words up to 20 bits wide, or can accept input words that are packed as densely as four input words up to eight bits wide. The IDP_PDAP_PACKING bits define the packing format. Based on the PDAP packing the data buffer format changes as shown in Figure 12-9. No Packing No packing provides for 20 bits coming into the packing unit and 32 bits going out to the FIFO in a single cycle. On every clock edge, 20 bits of data are moved and placed in a 32-bit register, left-aligned. That is, bit 19 maps to bit 31. The lower bits, 110, are always set to zero. This mode sends one 32-bit word to FIFO for each input clock cyclethe DMA transfer rate matches the PDAP input clock rate.

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Input Data Port (SIP, PDAP)

PDAP_CLK_I

PDAP_HOLD_I

PDAP DATA

W0

W1

W2

W3

W4

PDAP_STROBE_O

PDAP_CLK_I

PDAP_HOLD_I

PDAP DATA

W0

W1

W2

W3

PDAP_STROBE_O

Figure 12-3. PDAP Hold Input (No Packing) Packing by 2 Packing by 2 moves data in two cycles. Each input word can be up to 16 bits wide. On clock edge 1, bits 194 are moved to bits 150 (16 bits) On clock edge 2, bits 194 are moved to bits 3116 (16 bits) This mode sends one packed 32-bit word to FIFO for every two input clock cyclesthe DMA transfer rate is one-half the PDAP input clock rate.

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Operating Modes

PDAP_CLK_I

PDAP_HOLD_I

PDAP DATA

W0

W1

W0

W1

W0

PDAP_STROBE_O

PDAP_CLK_I

PDAP_HOLD_I

PDAP DATA

W0

W1

W0

W1

PDAP_STROBE_O

Figure 12-4. PDAP Hold Input (Packing by 2) Packing by 3 Packing by 3 packs three acquired samples together. Since the resulting 32-bit word is not divisible by three, up to ten bits are acquired on the first clock edge and up to eleven bits are acquired on each of the second and third clock edges: On clock edge 1, bits 1910 are moved to bits 90 (10 bits) On clock edge 2, bits 199 are moved to bits 2010 (11 bits) On clock edge 3, bits 199 are moved to bits 3121 (11 bits) This mode sends one packed 32-bit word to FIFO for every three input clock cyclesthe DMA transfer rate is one-third the PDAP input clock rate.

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Input Data Port (SIP, PDAP)

Packing by 4 Packing by 4 moves data in four cycles. Each input word can be up to 8 bits wide. On clock edge 1, bits 1912 are moved to bits 70 On clock edge 2, bits 1912 are moved to bits 158 On clock edge 3, bits 1912 are moved to bits 2316 On clock edge 4, bits 1912 are moved to bits 3124 This mode sends one packed 32-bit word to FIFO for every four input clock cyclesthe DMA transfer rate is one-quarter the PDAP input clock rate.
PDAP_CLK_I

PDAP_HOLD_I

PDAP DATA

B0

B1

B2

B3

B0

PDAP_STROBE_O

PDAP_CLK_I

PDAP_HOLD_I

PDAP DATA

B0

B1

B2

B3

PDAP_STROBE_O

Figure 12-5. PDAP Hold Input (Packing by 4)

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Data Transfer

Data Transfer
The data from each of the eight IDP channels is inserted into an eight register deep FIFO, which can only be transferred to the cores memory space sequentially. Data is moved into the FIFO as soon as it is fully received. One of two methods can be used to move data from the IDP FIFO to internal memory: The core can remove data from the FIFO manually. This method of moving data from the IDP FIFO is described in the next section, Core Transfers on page 12-16. Eight dedicated DMA channels can sort and transfer data. This method of moving data from the IDP FIFO is described in DMA Transfers on page 12-19.

Buffers
The following sections provide information about the IDP buffers. Buffer Threshold Depth The IDP_FIFO register provides information about the output of the 8-deep IDP FIFO which have been filled by the SIP or the PDAP units. Normally, this register is used only to read and remove the top sample from the FIFO. Channel encoding provides for eight serial input types that correspond to the IDP_SMODEx bits in the IDP control registers. When using channels 07 in serial mode, this register format applies. When using channel 0 in parallel mode, refer to the description of the packing bits for PDAP mode. information in ThePDAP channel. Table 12-8 is not valid when data comes from the

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Input Data Port (SIP, PDAP)

Table 12-8. IDP_FIFO Register Bit Descriptions

Bit 20 Name CHAN_ENC Description IDP Channel Encoding. These bits indicate the serial input port channel number that provided this serial input data. Note: This information is not valid when data comes from the PDAP. Left/Right Channel Status. Indicates whether the data in bits 31-4 is the left or the right audio channel as dictated by the frame sync signal. The polarity of the encoding depends on the serial mode selected in IDP_SMODE for that channel. See Table A-88 on page A-173. Input Data (Serial). Some LSBs can be zero, depending on the mode.

LR_STAT

314

SDATA

Buffer Status The status of the IDP buffer at any time is reflected in the IDP_FIFOSZ bit field in the DAI_STAT0 register. Buffer Error Status The error status of the IDP buffer is reflected in the SRU_OVFx bit field in the DAI_STAT0 register. The error status can be cleared by setting the IDP_CLROVF bit or by disabling the IDP port Flushing the Buffer The IDP buffers are flushed by disabling the IDP Port or by setting the IDP_FFCLR bit. Buffer Hang Disable For more information, see Buffer Hang Disable on page 12-33.

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Data Transfer

Core Transfers
The core transfers require that the serial peripheral at the SIP writes data to the IDP_DATAx_I pin (DATA or DAI pins for PDAP) according to the selected input format used. These data are automatically moved to the IDP_FIFO register without DMA intervention. The output of the FIFO can be directly fetched by reading from the buffer. The IDP_FIFO buffer is used only to read and remove the top sample from the FIFO, which is a maximum of eight locations deep. When this register is read, the corresponding element is removed from the IDP FIFO, and the next element is moved into the IDP_FIFO register. A mechanism is provided to generate an interrupt when more than a specified number of words are in the FIFO. This interrupt signals the core to read the IDP_FIFO register.
IDP_FIFO

The number of data samples in the FIFO at any time is reflected in the IDP_FIFOSZ bit field (bits 31-28 in the DAI_STAT0 register), which tracks the number of samples in FIFO. The three LSBs of FIFO data are the encoded channel number. These are transferred as is for this mode. These bits can be used by software to decode the source of data. data internal memory is The maximumPDAPtransfer width to left-justified modes 32-bits, as in the case of data or I S and in single
2

channel mode using 32 bits of data. Therefore, PDAP or I2S and left-justified 32-bit modes cannot be used with other channels in the core/interrupt driven mode since no channel information is available in the data stream.

SIP Data Buffer Format An audio signal that is normally 24 bits wide is contained within the 32-bit word. Four bits are available for status and formatting data (compliant with the IEC 90958, S/PDIF, and AES3 standards). An additional

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Input Data Port (SIP, PDAP)

bit identifies the left-right one-half of the frame. If the data is not in IEC standard format, the serial data can be any data word up to 28 bits wide. Unlike DMA, the core requires a status information about which channel triggered the interrupt. It does this by reading the data buffer. The remaining three bits are used to encode one of the eight channels being passed through the FIFO to the core. The FIFO output may feed eight DMA channels, where the appropriate DMA channel (corresponding to the channel number) is selected automatically. mode, L/R channel status bit (Bit Regardless of the datathe received in the left channel 3) always specifies whether is or the right channel of the corresponding input frame, as shown in Figure 12-6.
AUDIO DATA 31 8 7 INVALID BITS 4 L/R 3 2 IDP CHNL 0

Figure 12-6. Principle Data Format for the SIP Note that each input channel has its own clock and frame sync input, so unused IDP channels do not produce data and therefore have no impact on FIFO throughput. The clock and frame sync of any unused input should be routed by the SRU to low to avoid unintentional acquisition. The framing format is selected by using the IDP_SMODEx bits (three bits per channel) in the IDP_CTL0 register. Bits 318 of the IDP_CTL0 register control the input format modes for each of the eight channels. The eight groups of three bits indicate the mode of the serial input for each of the eight IDP channels. Figure 12-8 and Figure 12-7 shows the IDP data buffer input format for the SIP (depending on SMODEx bits) for core access.

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Data Transfer

RIGHT-JUSTIFIED FORMAT, 24-BIT DATA WIDTH

24 BITS AUDIO DATA 4 BITS, SET TO ZERO L/R BIT 3 BITS IDP CHANNEL

RIGHT-JUSTIFIED FORMAT, 20-BIT DATA WIDTH

20 BITS AUDIO DATA 8 BITS, SET TO ZERO L/R BIT 3 BITS IDP CHANNEL

RIGHT-JUSTIFIED FORMAT, 18-BIT DATA WIDTH

10 BITS, SET TO ZERO L/R BIT 3 BITS IDP CHANNEL

18 BITS AUDIO DATA

RIGHT-JUSTIFIED FORMAT, 16-BIT DATA WIDTH

12 BITS, SET TO ZERO L/R BIT 3 BITS IDP CHANNEL

16 BITS AUDIO DATA

Figure 12-7. IDP Data Buffer Format SIP Right-Justified

I2S AND LEFT-JUSTIFIED FORMAT
24-BIT AUDIO DATA

VALIDITY BIT USER DATA CHANNEL STATUS BIT L/R BIT

3 BITS IDP CHANNEL

BLOCK STATUS BIT

I2S AND LEFT-JUSTIFIED FORMAT, 32-BIT DATA WIDTH

32 BIT DATA

Figure 12-8. IDP Data Buffer Format SIP I2S/Left-Justified (32 Bits)

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Input Data Port (SIP, PDAP)

The polarity of left-right encoding is independent of the serial mode frame sync polarity selected in IDP_SMODE for that channel (Table 12-3 on page 12-3). Note that I2S mode uses a LOW frame sync (left-right) signal to dictate the first (left) channel, and left-justified mode uses a HIGH frame sync (left-right) signal to dictate the first (left) channel of each frame. In either mode, the left channel has bit 3 set (= 1) and the right channel has bit 3 cleared (= 0). PDAP Data Buffer Format If the PDAP module is enabled the IDP data buffer format will change according to the PDAP packing bits (IDP_PDAP_CTL register) as shown in Figure 12-9.
NO PACKING 1x20-BIT

A 31 12 11 B 31 16 15 C 31 21 20 D 31 24 23 C 16 15 B B 10

RESERVED 0 A 0 A 0 A 8 7 0

PACKING BY 2 2x16-BIT PACKING BY 3 TRI-WORD PACKING BY 4 4x8-BIT

Figure 12-9. IDP Data Buffer Formats for the PDAP

DMA Transfers
The processors support two types of DMA transfers, standard and ping-pong. Eight dedicated DMA channels can sort and transfer the data into one buffer per source channel. When the memory buffer is full, the DMA channel raises an interrupt in the DAI interrupt controller.

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Data Transfer

Data Buffer Format for DMA The LSB bits 20 of the data format from the serial inputs are channel encoding bits. Since the data is placed into a separate buffer for each DMA channel (defined by parameter index registers), these bits are not required and are cleared (=0) when transferring data to internal memory through the DMA. However, bit 3 still contains the left/right status information. In the case of PDAP data or 32-bit I2S and left-justified modes, these three bits are a part of the 32-bit data. For serial input channels, data is received in an alternating fashion from left and right channels. Data is not pushed into the FIFO as a full left/right frame. Rather, data is transferred as alternating left/right words as it is received. For the PDAP and 32-bit (non-audio) serial input, data is transferred as packed 32-bit words. IDP DMA Group Priority The IDP module can be configured with up to eight DMA channels. When multiple channels have data ready, the channel arbitrates using the fixed arbitration method (which is the first arbitration stage). The winning channel requests the DMA bus arbiter to get control of the peripheral DMA bus (2nd stage of arbitration). The I/O processor considers the eight DMA channels as a single group and therefore one arbitration request. For more information, see Peripheral DMA Arbitration on page 3-36. Standard DMA The eight DMA channels each have a set of registers for standard DMA: an I (index register), an M (modify register), and a C (count register).

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Input Data Port (SIP, PDAP)

The IDP DMA parameter registers have these functions: Internal index registers (IDP_DMA_Ix). Index registers provide an internal memory address, acting as a pointer to the next internal memory location where data is to be written. Internal modify registers (IDP_DMA_Mx). Modify registers provide the signed increment by which the DMA controller post-modifies the corresponding internal memory Index register after each DMA write. Count registers (IDP_DMA_Cx). Count registers indicate the number of words remaining to be transferred to internal memory on the corresponding DMA channel. This DMA access is enabled when the IDP_EN bit and IDP_DMA_EN bit and the IDP_DMA_ENx bits register are set to select a particular channel. The DMA is performed according to the parameters set in the various DMA registers and IDP control registers. An interrupt is generated after end of DMA transfer (when the count = 0). Ping-Pong DMA In ping-pong DMA, the parameters have two memory index values (index A and index B), one count value and one modifier value. The DMA starts the transfer with the memory indexed by A. When the transfer is completed as per the value in the count register, the DMA restarts with the memory location indexed by B. The DMA restarts with index A after the transfer to memory with index B is completed as per the count value. The IDP DMA parameter registers have these functions: Internal index registers (IDP_DMA_IxA, IDP_DMA_IxB). Index A/B registers provide an internal memory address, acting as a pointer to the next internal memory location where data is to be written.

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Data Transfer

Internal modify registers (IDP_DMA_Mx). Modify registers provide the signed increment by which the DMA controller post-modifies the corresponding internal memory Index register after each DMA write. Ping-Pong Count registers (IDP_DMA_PCx). Count registers indicate the number of words remaining to be transferred to internal memory on the corresponding DMA channel. This mode is activated when the IDP_EN bit, the IDP_DMA_EN bit, the IDP_DMA_ENx bits, and the IDP_PINGx bits are set for a particular channel. An interrupt is generated after every ping and pong DMA transfer (when the count = 0). DMA is repeated Note that ping-pong (OR global until stopped by resetting the bits bit).
IDP_DMA_ENx IDP_DMA_EN

Multichannel DMA Operation The SIP/PDAP can run both standard and ping-pong DMAs in different channels. When running standard DMA, initialize the corresponding IDP_DMA_Ix, IDP_DMA_Mx and IDP_DMA_Cx registers. When running ping-pong DMA, initialize the corresponding IDP_DMA_IxA, IDP_DMA_IxB, IDP_DMA_Mx and IDP_DMA_PCx registers. DMA transfers for all 8 channels can be interrupted by changing the IDP_DMA_EN bit in the IDP_CTL0 register. None of the other control settings (except for the IDP_EN bit) should be changed. Clearing the IDP_DMA_EN bit (= 0) does not affect the data in the FIFO, it only stops DMA transfers. If the IDP remains enabled, an interrupted DMA can be resumed by setting the IDP_DMA_EN bit again. But resetting the IDP_EN bit flushes the data in the FIFO. If the bit is set again, the FIFO starts accepting new data. Programs can drop DMA requests from the FIFO if needed. If one channel has finished its DMA, and the global IDP_DMA_EN bit is still set (=1),

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Input Data Port (SIP, PDAP)

any data corresponding to that channel is ignored by the DMA machine. This feature is provided to avoid stalling the DMA of other channels, which are still in an active DMA state. To avoid data loss in the finished channel, programs can clear (=0) IDP_DMA_EN bit as discussed in previously. Multichannel FIFO Status The state of all eight DMA channels is reflected in the IDP_DMAx_STAT bits (bits 2417 of DAI_STAT register). These bits are set once the IDP_DMA_EN and IDP_DMA_ENx bits are set, and remain set until the last data from that channel is transferred. Even if IDP_DMA_EN and IDP_DMA_ENx bits remain set, the IDP_DMAx_STAT bits clear once the required number of data transfers takes place. that DMA channel is (that is, parameter reg Note are atwhen adefault values), thenot usedchannels corresponding isters their DMA
IDP_DMAx_STAT

bit is cleared (= 0).

If the combined data rate from the channels is more than the DMA can service, a FIFO overflow occurs. This condition is reflected for each channel by the individual overflow bits (SRU_OVFx) in the DAI_STAT0 register. These are sticky bits that must be cleared by writing to the IDP_CLROVR bit (bit 6 of the IDP_CTL0 register). When an overflow occurs, incoming data from IDP channels is not accepted into the FIFO, and data values are lost. New data is only accepted once space is again created in the FIFO.

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Interrupts

Interrupts
Table 12-9 provides an overview of IDP interrupts. Table 12-9. IDP Interrupt Overview
Default Programmable Interrupt DAIHI = P0I DAILI = P12 Sources DMA complete Core buffer service Buffer threshold Buffer overflow Masking DAI_IMASK_RE Service ROC from DAI_IRPTL_x + RTI instruction

Sources
The IDP module drives in a total of 10 interrupt signals. Eight signals drive the DMA channel status and two are responsible for FIFO status (overflow and threshold buffer). These interrupts are connected to the DAI_IRPTL latch register. The IDP port interface generates interrupts as described in the following sections. Core Buffer Service Request When DMA is disabled the processor core may read from the IDP_FIFO buffer. An interrupt is generated when the receive buffer is not empty. Interrupt Acknowledge The correct handling of the IDP interrupt requires that the ISR must read the DAI_IMASK_x register to clear the interrupt latch appropriately. Note that many interrupts are combined in the DAI interrupt. Refer to Interrupts on page 10-30.

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Input Data Port (SIP, PDAP)

Buffer Threshold When using the interrupt scheme, the IDP_NSET bits (bits 30 of the IDP_CTL0 register) can be set to N, so N + 1 data can be read from the FIFO in the interrupt service routine (ISR). The IDP_FIFO_GTN_INT bit in DAI_IMASK_X register allows the IDP to configure interrupts to respond with the core under different system conditions. DMA Complete Using DMA transfers overrides the mechanism used for interrupt-driven core reads from the FIFO. When the IDP_DMA_EN bit and at least one IDP_DMA_ENx of the IDP_CTL1 register are set, the eighth interrupt (IDP_FIFO_GTN_INT) in the DAI_IMASK_x registers is NOT generated. At the end of the DMA transfer for individual channels, interrupts are generated. These interrupts are generated after the last DMA data from a particular channel has been transferred to memory. These interrupts (IDP_DMAx_INT) are mapped from bits 1710 in the DAI_IMASK_x registers and generate interrupts when they are set (= 1). These bits are ORed and reflected in high level interrupts that are sent to the DAI interrupt controller. An interrupt is generated at the end of a DMA, which is cleared by reading the DAI_IMASK_x registers. Buffer Overflow If the data out of the FIFO (either through DMA or core reads) is not sufficient to transfer at the combined data rate of all the channels, then a FIFO overflow can occur. When this happens, new data is not accepted. Additionally, data coming from the serial input channels (except for 32-bit I2S and left-justified modes) are not accepted in pairs, so that alternate data from a channel is always from left and right channels. If overflow occurs, an interrupt is generated if the IDP_FIFO_OVR_INT bit in the

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Effect Latency

DAI_IMASK_x

register is set (sticky bits in DAI_STAT0 register are also set). Data is accepted again when space has been created in the FIFO. Note that the total FIFO depth per channel is 9 locations: 1 location for SIP to parallel data conversion + 8 locations for the IDP_FIFO.

In case for DMA overflow error handling the DAISTAT0 sets overflow bits on the respective channel. A RW1C operation to the FIFO flush bit in the IDP_CTL0 register also clears the DAI_STAT0 bits.

Masking
The DAIHI and DAILI signals are routed by default to programmable interrupt. To service the DAIHI, unmask (set = 1) the P0I bit in the IMASK register. To service the secondary DAILI, unmask (set = 1) the P12IMSK bit in the LIRPTL register. For DAI system interrupt controllers the DAI_IMASK_RE register must be unmasked. For example:
bit set IMASK P0I; bit set LIRPTL P12IMSK; /* unmasks P0I interrupt */ /* unmasks P12I interrupt */

Service
The correct handling of the IDP interrupt requires that the ISR read the DAI_IRPTL_x register to clear the interrupt latch appropriately. Note that all IDP interrupts are combined in the DAI interrupt. Note that the IDP_FIFO_GTN_INT interrupt is not cleared when the DAI_IRPTL_H/L registers are read. This interrupt is cleared automatically when the situation that caused the interrupt goes away.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific). 12-26 ADSP-214xx SHARC Processor Hardware Reference

Input Data Port (SIP, PDAP)

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

IDP Effect Latency

The IDP is ready to start receiving data one serial clock cycle (SCLK) after it is enabled by setting IDP_EN bit. No LRCLK edges are lost from this point on. Disabling IDP DMA by resetting the IDP_DMA_EN bit requires 1 PCLK cycle. Disabling an individual DMA channel by resetting the IDP_DMA_ENx bit requires 2 PCLK cycles.

Programming Model
The following sections provide procedures that are helpful when programming the input data port.

Setting Miscellaneous Bits

This sequence is used in most following programming models as intermediate step. Set the required values for: bits in the IDP_CTLx register to specify the frame sync format for the serial inputs (left-justified I2S, or right-justified mode).
IDP_SMODEx IDP_Pxx_PDAPMASK

bits in the IDP_PP_CTL register to specify the input mask, if the PDAP is used.

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Programming Model

bits in the IDP_PP_CTL register to specify input from the DAI pins or the DATA pins, if the PDAP is used.
IDP_PP_SELECT

bit (bit 29) in the IDP_PP_CTL register to specify if data is latched on the rising or falling clock edge, if the PDAP is used.
IDP_PDAP_CLKEDGE

Starting Core Interrupt-Driven Transfer

To start a core interrupt-driven data transfer: 1. Clear the IDP_EN bit which automatically clears the FIFO. 2. Keep the SCLK and frame sync inputs of the SIP and PDAP connected to low, by setting the proper values in the SRU registers. 3. Refer to Setting Miscellaneous Bits above. 4. Program the SRU registers to establish the proper connection to the SIP and/or PDAP being used. Keep the unused clock and frame sync signals connected to low. 5. Set the desired values for the N_SET variable using the IDP_NSET bits in the IDP_CTL0 register. 6. Set the IDP_FIFO_GTN_INT bit (bit 8 of the DAI_IMASK_RE register) to high and set the corresponding bit in the DAI_IMASK_FE register to low to unmask the interrupt. Set bit 8 of the DAI_IMASK_PRI register (IDP_FIFO_GTN_INT) as needed to generate a high priority or low priority core interrupt when the number of words in the FIFO is greater than the value of N set. 7. Enable the PDAP by setting IDP_PDAP_EN (bit 31 in the IDP_PP_CTL register), if required.

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Input Data Port (SIP, PDAP)

8. Enable the IDP by setting the IDP_EN bit (bit 7 in the IDP_CTL0 register) and the IDP_ENx bits in the IDP_CTL1 register. SHARC processors, before In olderenabled. However, thethe IDP startsisshifting datathe nextthe IDP is shifted data latched at frame sync edge only if the IDP is enabled. Therefore, whether the first channel received by the IDP is left/right depends on the instant when the IDP is enabled which may lead to channel swapping. Additional Notes When IDPs are used to receive data from external devices, there is a sequence to be followed to enable the IDP ports when configured to receive data in I2S mode. Failing to follow this sequence can give rise to channel shift or swap. 1. Connect the frame sync internally using the SRU (Signal Routing Unit) to the DAI interrupt. 2. Configure the DAI interrupt (MISCA) for the inactive edge of the frame sync. 3. Wait for the DAI interrupt, and enable the IDP port inside the DAI interrupt service routine. 4. Clear the DAI interrupt by reading the DAI interrupt latch register. This procedure ensures that the IDP ports are enabled at the correct time, avoiding issues like channel shift or swap in the received data.

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Programming Model

Starting A Standard DMA Transfer

To start a DMA transfer from the FIFO to memory: 1. Clear the IDP_EN bit which automatically clears the FIFO. 2. While the global IDP_DMA_EN and the IDP_EN bits are cleared (= 0), set the values for the DMA parameter registers that correspond to channels 70. 3. Keep the clock and the frame sync input of the serial inputs and/or the PDAP connected to low, by setting proper values in the SRU registers. 4. Refer to Setting Miscellaneous Bits on page 12-27 above. 5. Route all of the required inputs to the IDP by writing to the SRU registers 6. Enable the channels IDP_ENx and IDP_DMA_ENx bit settings. 7. Start the DMA by setting The IDP_PDAP_EN bit (bit 31 in IDP_PP_CTL register if the PDAP is required). The global IDP_DMA_EN bit of the IDP_CTL0 register to enable standard DMA on the selected channel. The global IDP_EN bit (bit 7 in the IDP_CTL0 register).

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Input Data Port (SIP, PDAP)

Starting a Ping-Pong DMA Transfer

To start a ping-pong DMA transfer from the FIFO to memory: 1. Clear the IDP_EN bit which automatically clears the FIFO. 2. While the global IDP_DMA_EN and IDP_EN bits are cleared (=0), set the values for the following DMA parameter registers that correspond to channels 70. 3. Keep the clock and the frame sync input of the serial inputs and/or the PDAP connected to LOW, by setting proper values in the SRU registers. 4. Refer to Setting Miscellaneous Bits on page 12-27 above. 5. Connect all of the required inputs to the IDP by writing to the SRU registers. 6. Enable the channels IDP_ENx, IDP_DMA_ENx and IDP_PINGx bit settings. 7. Start DMA by setting: The IDP_PDAP_EN bit (bit 31 in IDP_PP_CTL register if the PDAP is required). The global IDP_DMA_EN bit of the IDP_CTL0 register to enable the standard DMA of the selected channel. The global IDP_EN bit (bit 7 in the IDP_CTL0 register).

Servicing Interrupts for DMA

The following steps describe how to handle an IDP ISR for DMA. 1. An interrupt is generated and program control jumps to the ISR when the DMA for a channel completes.

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Programming Model

2. The program clears the IDP_DMA_EN bit in the IDP_CTL0 register. a. To ensure that the DMA of a particular IDP channel is complete, (all data is transferred into internal memory) wait until the IDP_DMAx_STAT bit of that channel becomes zero in the DAI_STAT register. This is required if a high priority DMA (for example a SPORT DMA) is occurring at the same time as the IDP DMA. b. As each DMA channel completes, a corresponding bit in either the DAI_IRPTL_L or DAI_IRPTL_H register for each DMA channel is set (IDP_DMAx_INT). 3. The program clears (= 0) the channel's IDP_DMA_ENx bit in the IDP_CTL1 register which has finished. 4. Reprogram the DMA registers for finished DMA channels. More than one DMA channel may have completed during this time period. For each, a bit is latched in the DAI_IRPTL_L or DAI_IRPTL_H registers. Ensure that the DMA registers are reprogrammed. If any of the channels are not used, then its clock and frame sync should be held LOW. 5. Read the DAI_IRPTL_L or DAI_IRPTL_H registers to see if more interrupts have been generated. If the value(s) are not zero, repeat step 4. If the value(s) are zero, continue to step 6. 6. Re-enable the IDP_DMA_EN bit in the IDP_CTL0 register (set to 1). 7. Exit the ISR. If a zero is read in step 5 (no more interrupts are latched), then all of the interrupts needed for that ISR have been serviced. If another DMA completes after step 5 (that is, during steps 6 or 7), as soon as the ISR

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Input Data Port (SIP, PDAP)

completes, the ISR is called again because the OR of the latched bits will not be nonzero again. DMAs in process run to completion. is not performed, If step 5 when IDP DMA isand a DMA channel expires during step 4, then, re-enabled, (step 6) the completed DMA is not reprogrammed and its buffer overruns. This unit is multiplexed with SIP0. The PDAP provides one clock input, one clock hold input and a maximum of 20 parallel data input pins. The positive or negative edge of the clock input is used for data latching. The clock hold input (PDAP_HLD_I) validates a clock edgeif this input is high then clock edge is masked for data latching. It supports four types of data packing mode selected by MODE bits in the IDP_PP_CTL register.

Debug Features
The following sections describe the features available for debugging the IDP.

Status Register Debug

The core may also write to the FIFO. When it does, the audio data word is pushed into the input side of the FIFO (as if it had come from the SRU on the channel encoded in the three LSBs). This can be useful for verifying the operation of the FIFO, the DMA channels, and the status portions of the IDP. The IDP_STAT1 register returns the current state of the read/write index pointers from FIFO.

Buffer Hang Disable

The IDP_BHD bit in IDP_CTL0 is used for buffer hang disable control. When there is no data in the FIFO, reading the IDP_FIFO register causes the core to hang. This condition continues until the FIFO contains valid data. Set-

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Debug Features

ting the IDP_BHD bit (= 1) prevents the core from hanging on reads from an empty IDP_FIFO register. Clearing this bit (= 0) causes the core to hang under the conditions described previously. If the IDP_BHD bit (bit 4 in the IDP_CTL0 register) is not set, attempts to read more data than is available in the FIFO results in a core hang.

Shadow Interrupt Registers

For more information, see Debug Features on page 2-15.

Core FIFO Write

The core may also write to the FIFO. When it does, the audio data word is pushed into the input side of the FIFO (as if it had come from the SRU on the channel encoded in the three LSBs). This can be useful for verifying the operation of the FIFO, the DMA channels, and the status portions of the IDP. The IDP_STAT1 register returns the current state of the read/write index pointers from FIFO. Note that if both the SIP/PDAP and the core try to write to the FIFO, the core has higher priority.

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13 ASYNCHRONOUS SAMPLE RATE CONVERTER

Sample rate converters (SRC) are frequently used in digital signal processing audio applications. In the ADSP-214xx processors, the most frequently used sample rate conversions are off-loaded into hardware modules that are dedicated for filter processing and reduce the instruction processing load on the core, freeing it up for other tasks. The specifications for the module are listed in Table 13-1. Table 13-1. ASRC Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex No Yes Yes No No No Yes No No N/A Yes Availability

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Features

Table 13-1. ASRC Specifications (Contd)

Feature Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Max Clock Operation No N/A N/A N/A N/A N/A Yes (RAM, ROM) fPCLK/4 Availability

Features
The ASRC for the SHARC processors has the features shown in the list below. 4 Asynchronous stereo SRCs operating in slave mode. Simple programming model. Controllable muting options (hardware, software and automatic). Automatically senses input and output sample frequencies. Supports left-justified, I2S, right-justified (16-,18-, 20-, 24-bits), and TDM serial port modes. Daisy-chain configuration in TDM modes for input and output ports to create a serial frame. Different protocols on input/output port allow format conversions. De-emphasis filter for 32, 44.1 and 48 KHz sampling frequencies. 13-2 ADSP-214xx SHARC Processor Hardware Reference

Asynchronous Sample Rate Converter

Up to 192 kHz sample rate input/output continuous sample ratios from 7.5:1 to 1:8. Group delay (latency of interpolation filter) is 16 samples. SNR from 128 to 140 dB (depending on processor model). Matched phase mode available (ADSP-21488 model only) to compensate for group delays. Can be used to de-jitter clocks in systems.

Pin Descriptions
The ASRC has two interfaces: an input port and an output port. Table 13-2 describes the six inputs and two outputs for the IP (input port) and OP (output port). Table 13-2. ASRC Pin Descriptions
ADSP-214xx Internal Node ASRC30_CLK_IP_I ASRC30_FS_IP_I ASRC30_DAT_IP_I ASRC30_CLK_OP_I ASRC30_FS_OP_I ASRC30_TDM_OP_I ASRC30_TDM_IP_O ASRC30_DAT_OP_O I/O Input Input Input Input Input Input Input Output Description ASRC input port clock input ASRC input port frame sync input ASRC input port data input ASRC output port clock input ASRC output port frame sync input ASRC output port TDM daisy chain data input ASRC output port TDM daisy chain data output ASRC output port data output

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SRU Programming

SRU Programming
The SRU (signal routing unit) needs to be programmed in order to connect the ASRCs to the output pins or any other peripherals. For normal operation, the data, clock, and frame sync signals need to be routed as shown in Table 13-3. Table 13-3. ASRC DAI/SRU Signal Routing
ASRC Source DAI Connection Group A ASRC30_DAT_IP_O ASRC30_TDM_OP_O Group B Group C ASRC30_DAT_OP_O Group D ASRC Destination ASRC30_CLK_IP_I ASRC30_CLK_OP_I ASRC30_DAT_IP_I ASRC30_TDM_OP_I ASRC30_FS_IP_I ASRC30_FS_OP_I

For information on using the SRU, see Rules for SRU Connections on page 10-19.

Register Overview
The ASRC uses five registers to configure and operate the ASRC module. For complete register and bit descriptions, see Asynchronous Sample Rate Converter Registers on page A-181. Control Registers (ASRCCTLx). Enable or disable the sample rate converters. They also specify the input and output data format. Mute Register (ASRCMUTE). Controls the connection of the mute in and mute out signal.

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Asynchronous Sample Rate Converter

Ratio Registers (ASRCRATx). Return the sample ratio between the input and out data stream and mute information (mute out).

Clocking
The fundamental timing clock of the ASRC module is peripheral clock/4 (PCLK/4) and is operating in slave mode only. The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

Functional Description
Figure 13-1 on page 13-6 shows a top level block diagram of the ASRC module and Figure 13-2 on page 13-8 shows architecture details. Conceptually, the sample rate converter interpolates the serial input data at a rate of 220 and samples the interpolated data stream by the output sample rate. In practice, a 64-tap FIR filter with 220 polyphases, a FIFO, a digital servo loop that measures the time difference between the input and output samples within 5 ps, and a digital circuit to track the sample rate ratio are used to perform the interpolation and output sampling.

I/O Ports
The I/O ports provide the interface through which data is transferred asynchronously into and out of the SRC modules. The SRC has a 3-wire interface for the serial input and output ports that supports left-justified, I2S, and right-justified (16-, 18-, 20-, 24-bit) modes. Additionally, the serial interfaces support TDM mode for daisy-chaining multiple SRCs to form a frame. The serial output data is dithered down to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is selected.

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Functional Description

SRC input to the sample The of theconverts the data from the serial rate atport serial input rate serial output port. The sample the port can be asynchronous with respect to the output sample rate of the output serial port.
S/PDIF RX SRCCTL MUTE Hard/Soft/Auto SRCMUTE Auto/Manual INTERRUPT

SRCx_TDM_IP_O

MUTE IN

MUTE OUT

SRCx_FS_IP_I SRCx_CLK_IP_I 64-BIT SERIAL INPUT SHIFT PORT (SIP) REG SMODE IN
DE-EMPHASIS FILTER SAMPLE RATE CONVERTER (SRC) RATIO

SRCx_DAT_IP_I

PCLK/4 SRCx_DAT_OP_O

SERIAL OUTPUT PORT (SOP) DITHER MATCHED PHASE SMODE OUT

SRCx_FS_OP_I 64-BIT SHIFT REG SRCx_CLK_OP_I

SRCx_TDM_OP_I

Figure 13-1. Top Level ASRC Block Diagram

De-Emphasis Filter
The de-emphasis filter is used to de-emphasize audio data that has been emphasized.

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Asynchronous Sample Rate Converter

Mute Control
When either the SRC starts up (or there is a change in sample ratio), the mute out signal (SRCx_MUTEOUT) is asserted (=1). The mute out signal stays high until the SRC settles on the new sample rate(s). While mute out is asserted high, the mute in signal should be asserted high as well. The mute in signal performs a soft mute of the audio input data when asserted and un mutes the input audio data softly when de-asserted. Note that it takes 4096 input port FS samples until the audio input data is completely muted and 4096 FS samples until the audio input data is completely un muted.

SRC Core
The sample rate converters RAM FIFO block adjusts the left and right input samples and stores them for the FIR filters convolution cycle. The ASRCx_FS_IP counter provides the write address (for scaling) to the FIFO block and the ramp input to the digital-servo loop. The ROM stores the coefficients for the FIR filter convolution and performs a high-order interpolation between the stored coefficients. The sample rate ratio block measures the sample rate by dynamically altering the ROM coefficients and scaling the FIR filter length and input data. The digital-servo loop automatically tracks the SRCx_FS_IP and SRCx_FS_OP sample rates and provides the RAM and ROM start addresses for the start of the FIR filter convolution. sample own local Unlike other peripherals, thewhich arerate converters the purpose of memories (RAM and ROM) dedicated for sample rate conversion only. The sample rate converter only operates asynchronously and is always a slave to the input and output ports.

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Functional Description

RAM FIFO The RAM FIFO receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the SRC and the scaling of the input data by the sample rate ratio before storing the samples in RAM. The input data is scaled by the sample rate ratio because as the FIR filter length of the convolution increases, so does the amplitude of the convolution output. To keep the output of the FIR filter from saturating, the input data is scaled down by multiplying it by (SRCx_FS_OP)/(SRCx_FS_IP) when SRCx_FS_OP<SRCx_FS_IP. The FIFO also scales the input data to mute and stop muting the SRC.
MUTE IN DATA

DATA

ROM A FIR FILTER

ADDR

STEREO DATA FROM IP

RAM FIFO 2x512 WORDS

ROM B ROM C

ADDR

HIGH ORDER INTERP

WRITE ADDR

ROM D
SCALE MUTE OUT START ADDR RAM/ROM

STEREO DATA TO OP

SRCx_FS_IP COUNTER

RAMP

DIGITAL SERVO LOOP

SRCx_FS_IP SRCx_FS_OP

SAMPLE RATE RATIO

SAMPLING RATE SENSING

EXTERNAL RATIO (MATCHED PHASE MODE)

Figure 13-2. Core Architecture Digital Servo Loop The digital-servo loop is essentially a ramp filter that provides the initial pointer to the address in RAM and ROM for the start of the FIR convolution. The RAM pointer is the integer output of the ramp filter while the ROM pointer is the fractional part. The digital-servo loop must be able to provide excellent rejection of jitter on the ASRCx_FS_IP and ASRCx_FS_OP clocks as well as measure the arrival of the ASRCx_FS_OP clock within 5 ps.

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Asynchronous Sample Rate Converter

The digital-servo loop also divides the fractional part of the ramp output by the ratio of (ASRCx_FS_IP)/(ASRCx_FS_OP) for the case when ASRCx_FS_IP > ASRCx_FS_OP, to dynamically alter the ROM coefficients. The digital-servo loop is implemented with a multi-rate filter. To settle the digital-servo loop filter quickly at startup or at a change in the sample rate, a fast mode has been added to the filter. When the digital-servo loop starts up or the sample rate is changed, the digital-servo loop kicks into fast mode to adjust and settle on the new sample rate. Upon sensing the digital-servo loop settling down to some reasonable value, the digital-servo loop kicks into normal or slow mode. During fast mode, the ASRCx_MUTE_OUT bit of the ASRC is asserted to mute the ASRC input which avoids clicks and pops. FIR Filter The FIR filter is a 64-tap filter in the case of ASRCx_FS_OP < ASRCx_FS_IP and is (ASRCx_FS_IP)/(ASRCx_FS_OP) 64 taps for the case when ASRCx_FS_IP > ASRCx_FS_OP. The FIR filter performs its convolution by loading in the starting address of the RAM address pointer and the ROM address pointer from the digital-servo loop at the start of the ASRCx_FS_OP period. The FIR filter then steps through the RAM by decrementing its address by 1 for each tap, and the ROM pointer increments its address by the (ASRCx_FS_OP/ASRCx_FS_IP) 220 ratio for ASRCx_FS_IP > 20 ASRCx_FS_OP or 2 for ASRCx_FS_OP < ASRCx_FS_IP. Once the ROM address rolls over, the convolution is complete. The convolution is performed for both the left and right channels, and the multiply/accumulate circuit used for the convolution is shared between the channels. Sample Rate Sensing The (SRCx_FS_IP)/(SRCx_FS_OP) sample rate ratio circuit is used to dynamically alter the coefficients in the ROM for the case when SRCx_FS_IP > SRCx_FS_OP. The ratio is calculated by comparing the output of an SRCx_FS_OP counter to the output of an SRCx_FS_IP counter. If

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Functional Description

> SRCx_FS_IP, the ratio is held at one. If SRCx_FS_IP > SRCx_FS_OP, the sample rate ratio is updated if it is different by more than two SRCx_FS_OP periods from the previous SRCx_FS_OP to SRCx_FS_IP comparison. This is done to provide some hysteresis to prevent the filter length from oscillating and causing distortion.
ASRCx_FS_OP

Digital Filter Group Delay 1 The RAM in the FIFO is 512 words deep for both left and right channels. An offset of 16 samples to the write address, provided by the SRCx_FS_IP counter, is added to prevent the RAM read pointer from overlapping the write address. The maximum decimation rate can be calculated from the RAM word is: depth = (512 16) 64 taps = 7.5:1. The 64 samples effect latency in the interpolation filter. This latency (group delay) depends on interpolation or decimation ratio and is determined as follows: 32 16 GDL = ---------- + ---------- seconds for SRC_FS_OP > SRC_FS_IP f S_IN f S_IN f S_IN 32 16 GDL = ---------- + ---------- --------------- seconds for SRC_FS_OP < SRC_FS_IP f S_IN f S_OUT f S_IN

Data Format
Figure 13-3 shows the data input format for a frame (stereo data). The frame format is valid for all protocols. For models which do not support matched phase mode the 8-bit data field is ignored.
1

Intuitively, the time interval required for a full-level input pulse to appear at the ASRCs output, at full level, is typically expressed in milliseconds (ms). More precisely, the derivative of the radian phase with respect to the radian frequency at a given frequency.

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Asynchronous Sample Rate Converter

AUDIO DATA LEFT CHANNEL, 24 BITS

MATCHED-PHASE DATA, 8 BITS

AUDIO DATA RIGHT CHANNEL, 24 BITS

MATCHED-PHASE DATA, 8 BITS

MSB (BIT 63)

Left-Justified, I2S, and TDM Mode

LSB (BIT 0)

MATCHED-PHASE DATA, 8 BITS

AUDIO DATA LEFT CHANNEL, 16 BITS - 24 BITS

MATCHED-PHASE DATA, 8 BITS

AUDIO DATA RIGHT CHANNEL, 16 BITS - 24 BITS

Right-Justified Mode

Figure 13-3. ASRC Data Frame Format by Protocol

Operating Modes
The ASRC can operate in TDM, I2S, left-justified, right-justified, and bypass modes. The serial ports of the processor can be used for moving the ASRC data to/from the internal memory. In I2S, left-justified and right-justified modes, the ASRCs operate individually. The serial data provided in the input port is converted to the sample rate of the output port.

TDM Input Mode

In TDM input port, several ASRCs can be daisy-chained together and connected to the serial input port of a SHARC processor or other processor (Figure 13-4). The ASRC IP contains a 64-bit parallel load shift register. When the SRCx_FS_IP_I pulse arrives, each ASRC parallel loads its left and right data into the 64-bit shift register. The input to the shift register is connected to SRCx_DATA_IP_I, while the output is connected to SRCx_TDM_IP_O. By connecting the SRCx_TDM_IP_O to the SRCx_DATA_IP_I of the next ASRC, a large shift register is created, which is clocked by ASRCx_CLK_IP_I. number of ASRCs that can be The by the maximum frequency of daisy-chained ,together is limited refer to the data
SRCx_CLK_xx_I

sheet for exact values. For example, if the maximum frequency of ADSP-214xx SHARC Processor Hardware Reference 13-11

Operating Modes

is x MHz, and the output sample rate is fS, then number of ASRCs (n) that can be connected in daisy chained fashion is: n 64 FS <= x MHz.
SRCx_CLK_xx_I

TDM Output Mode

In TDM output port, several ASRCs can be daisy-chained together and connected to the SPORT of an ADSP-214xx or other processor (Figure 13-4). The ASRC OP contains a 64-bit parallel load shift register. When the ASRCx_FS_OP_I pulse arrives, each ASRC loads its left and right data into the 64-bit shift register. The input to the shift register is connected to ASRCx_TDM_OP_I, and the output is connected to SRCx_DAT_OP_O. By connecting the SRCx_DAT_OP_O to the ASRCx_TDM_OP_I of the next ASRC, a large shift register is created, which is clocked by SRCx_CLK_OP_I. As shown in Figure 13-4, with three ASRCs in a daisy-chain connection, the serial clock for input/or output port is defined as: SCLK = 3 64 FS = 192 FS

Clock, FS

SRC2_DAT_IP_I

SRC1_DAT_IP_I

SRC0_DAT_IP_I

MASTER Tx
SPORT_Dx_O

SRC2_TDM_IP_O

SRC1_TDM_IP_O

SRC0_TDM_IP_O

TDM IP Daisy Chain

SPORT_Dx_I

SRC2_TDM_OP_I

SRC1_TDM_OP_I

SRC0_TDM_OP_I

MASTER Rx
Clock, FS

SRC2_DAT_OP_O

SRC1_DAT_OP_O

SRC0_DAT_OP_O

TDM OP Daisy Chain

Figure 13-4. TDM Input/Output Modes

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Asynchronous Sample Rate Converter

Matched-Phase Mode (ADSP-21488)

The matched phase mode of the sample rate converter, shown in Figure 13-5, is enabled by the SRCx_MPHASE bit. This mode is used to match the phase (group delay) between two or more adjacent sample rate converters that are operating with the same input and output clocks.
DATA INPUT 2 DATA INPUT 1

I2S IP
Clock, FS SPORT_Dx_O

SRC2_DAT_IP_I

SRC1_DAT_IP_I

SRC0_DAT_IP_I

SRC2_TDM_IP_O

SRC1_TDM_IP_O

SRC0_TDM_IP_O

MASTER

MASTER
SPORT_Dx_I

SRC2_TDM_OP_I PHASE SLAVE SRC2_DAT_OP_O

SRC1_TDM_OP_I PHASE SLAVE SRC1_DAT_OP_O

SRC0_TDM_OP_I PHASE MASTER SRC0_DAT_OP_O

Clock, FS

I2S OP
DATA OUTPUT 1 DATA OUTPUT 0

Figure 13-5. Typical Configuration for Matched-Phase Mode Operation Hysteresis of the (SRCx_FS_OP)/(SRCx_FS_IP) ratio circuit can cause phase mismatching between two ASRCs operating with the same input and output clocks. Since the hysteresis requires a difference of more than two ASRCx_FS_OP periods to update the SRCx_FS_OP and SRCx_FS_IP ratios, two ASRCs may have differences in their ratios from 0 to 4 SRCx_FS_OP period counts. The (SRCx_FS_OP)/(SRCx_FS_IP) ratio adjusts the filter length of the ASRC, which corresponds directly with the group delay. Thus, the magnitude in the phase difference depends upon the resolution of the

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Operating Modes

and ASRCx_FS_IP counters. The greater the resolution of the counters, the smaller the phase difference error.
ASRCx_FS_OP

When the slave SRC SRCx_MPHASE bit is set (=1), it accepts the sample rate ratio transmitted by another SRC, (the matched phase master) which has its SRCx_MPHASE bit cleared (=0), through its serial output. The phase master ASRC device transmits its SRCx_FS_OP/SRCx_FS_IP ratio through the data output pin (SRCx_DAT_OP_O) to the slaves ASRCs data input pins (SRCx_TDM_OP_I). The transmitted data (32-bit subframe) contains 24-bit data and 8-bits matched phase (see Figure 13-3 on page 13-11). The slave SRCs receive the 8-bit matched phase bits (instead of their own internally-derived ratio) if their SRCx_MPHASE bits set to 1, respectively. The SRCx_FS_IP and SRCx_FS_OP signals may be asynchronous with respect to each other in this mode. Note that there must be 64 SRCx_CLK_OP cycles per frame in matched-phase mode (2 24-bits data and 2 8-bits phase match). sends data on By default, the ADSP-21488 if the matched phasedpin is tiedits pin, but only low.
SRCx_DAT_OP_O SRCx_TDM_OP_I

The slaves simply ignore the matched phased data if their SRCx_MPHASE bits are cleared (= 0).

Bypass Mode
When the BYPASS bit is set (=1), the input data bypasses the sample rate converter and is sent directly to the serial output port. Dithering is disabled. This mode is ideal when the input and output sample rates are the same and ASRCx_FS_IP_I and ASRCx_FS_OP_I are synchronous with respect to each other. In matched phase bypass mode, the ASRCx_FS_OP_I should come at least one SRCx_CLK_xx_I period before ASRCx_FS_IP_I. Cases where this is not met could result in data loss. For example, if internal SPORTS are used then ASRCx_FS_OP_I and ASRCx_FS_IP_I could be driven by different SPORTS so that the timing of these signals could be

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Asynchronous Sample Rate Converter

controlled by enabling them at different times. This mode can also be used for passing through non-audio data since no processing is performed on the input data.

De-Emphasis Mode
The DEEMPHASIS bits choose the type of de-emphasis filter based on the input sample rate for 32, 44.1 or 48 kHz sampling rates.

Dithering Mode 1
Serial output data is dithered down to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is selected. In the case of 20, 18 and 16 bit word lengths, the least significant bits of the 24-bit word coming from the SRC into the serial output port are truncated. The DITHER_EN signal (not user configurable) automatically adds dithering to the 24-bit word before truncating to the appropriate output word length. The 21BIT_DITHER signal is used for the consumer version of the SRC to reduce the dynamic range performance to approximately 128 dB.

Muting Modes
The mute feature of the ASRC can be controlled automatically in hardware using the MUTE_IN signal by connecting it to the MUTE_OUT signal. Automatic muting can be disabled by setting (=1) the ASRCx_MUTE_EN bits in the ASRCMUTE register. Note by register connects signalthatthe default, the but not vice versa. the to signal,
ASRCMUTE MUTE_OUT MUTE_IN

The ASRC can be programmed to add triangular Probability Distribution Function (PDF) dither to the digital audio samples. It is advisable to add dither when the input word width exceeds the output word width, for example the input word is 20 bits and the output word is 16 bits. Triangular PDF is generally considered to create the most favorable noise shaping of the residual quantization noise.

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Operating Modes

Soft Mute When the ASRCx_SOFTMUTE bit in the ASRCCTL register is set, the MUTE_IN signal is asserted, and the ASRC performs a soft mute by linearly decreasing the input data to the ASRC FIFO to zero, (144 dB) attenuation as described for automatic hardware muting. A 12-bit counter, clocked by ASRCx_FS_IP_I, is used to control the mute attenuation. Therefore, the time it takes from the assertion of MUTE_IN to 144 dB, full mute attenuation is 4096 FS cycles. Likewise, the time it takes to reach 0 dB mute attenuation from the deassertion of MUTE_IN is 4096 FS cycles. Hard Mute When the ASRCx_HARD_MUTE bit in the ASRCCTL register is set, the ASRC immediately mutes the input data to the ASRC FIFO to zero, (144 dB) attenuation. Auto Mute When the ASRCx_AUTO_MUTE bit in the ASRCCTLx register is set, the ASRC communicates with the S/PDIF receiver peripheral to determine when the input should mute. Each ASRC is connected to the S/PDIF receiver to read the DIR_NOAUDIO bits. When the DIR_NOAUDIO bit is set (=1), the ASRC immediately mutes the input data to the ASRC FIFO to zero, ( 144 dB) attenuation. This mode is useful for automatic detection of non-PCM audio data received from the S/PDIF receiver.

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Interrupts
Table 13-4 provides an overview of ASRC interrupts Table 13-4. Overview of ASRC Interrupts
Default Programmable Sources Interrupt DAIHI = P0I DAILI = P12I ASRC initialization ASRC sample rate change Masking DAI_IMASK_x Service ROC from DAI_IRPTL_x + RTI instruction

Sources
Each ASRC module drives one interrupt signal (mute out asserted). All these signals are connected into the DAI_IRPTL latch register. The S/PDIF ports generate interrupts as described below. SRC Mute Out The SRC mute-out signal can be used to generate interrupts on their rising edge, falling edge, or both, depending on how the DAI interrupt mask registers (DAI_IMASK_RE/DAI_IMASK_FE) are programmed. This allows the generation of DAIHI/DAILI interrupts either entering mute, exiting muting or both. The SRCx_MUTE_OUT interrupt is generated only once when the SRC is locked (after 4096 FS input samples) and after changes to the sample ratio. Hard mute, soft mute, and auto mute only control the muting of the input data to the SRC.

Masking
The DAI_IMASK_x register must be unmasked accordingly. The DAIHI and DAILI signals are routed by default to programmable interrupt. To service the DAIHI, unmask (set = 1) the P0I bit in the IMASK register. To service the secondary DAILI, unmask (set = 1) the P12IMSK bit in the LIRPTL

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Effect Latency

register. For DAI system interrupt controllers the DAI_IMASK_RE or DAI_IMASK_FE register must be unmasked. For example:
bit set IMASK P0I; bit set LIRPTL P12IMSK; ustat1=dm(DAI_IMASK_RE); bit set ustat1 SRC0_MUTE_INT; dm(DAI_IMASK_RE)=ustat1; /* unmasks P0I interrupt */ /* unmasks P12I interrupt */ /* set SRC0 INT on RE */

Service
The ISR reads the DAI_IRPTL_x register to clear the interrupt request.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

ASRC Effect Latency

After the ASRC registers are configured the effect latency is 1.5 PCLK cycles minimum and 3 PCLK cycles maximum.

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Programming Model
The following is basic information on programming the ASRC module. 1. Program the SRCTLx register and keep the SRCx_ENABLE bit cleared. 2. Set the SRCx_ENABLE bit in SRCCTLx register. After 4096 input port FS cycles the ASRC has un muted.

Debug Features
The asynchronous sample rate converter allow the bypass mode. When the BYPASS bit is set (=1), the input data bypasses the sample rate converter and is sent directly to the serial output port. This mode can be used for testing both ports when the input and output sample rates are at the same frequency, therefore both in- and output ports can be routed to the same serial clock and frame sync.

Shadow Interrupt Registers

For more information, see Debug Features on page 2-15.

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Debug Features

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14 SONY/PHILIPS DIGITAL INTERFACE

The Sony/Philips Digital Interface (S/PDIF) is a standard audio data transfer format that allows the transfer of digital audio signals from one device to another without having to convert them to an analog signal. The digital audio interface carries three types of information; audio data, non audio data (compressed data) and timing information. Its specifications are listed in Table 14-1. Table 14-1. S/PDIF Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex No Yes Yes No No Yes No Yes No No No Yes No No N/A Yes No Yes No No N/A Yes Transmitter Receiver

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Features

Table 14-1. S/PDIF Specifications (Contd)

Feature Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Max Clock Operation No N/A N/A N/A N/A N/A No fPCLK/4 No N/A N/A N/A N/A N/A No fPCLK/4 Transmitter Receiver

Features
The S/PDIF interface has the following features. Supports one stereo channel or compressed audio streams. AES3-compliant S/PDIF transmitter and receiver. Transmitting a biphase mark encoded signal that may contain any number of audio channels (compressed or linear pulse code modulation) or non-audio data. S/PDIF receiver managing clock recovery with separate S/PDIF on-chip PLL. S/PDIF receiver direct supports DTS frames of 256, 512, 1024, 2048, and 4096 (4096 frames are not supported for the ADSP-2146x processors). Manage user status information and provide error-handling capabilities in both the transmitter and receiver.

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DAI allows interactions over DAI by serial ports, IDP and/or the external DAI pins to interface to other S/PDIF devices. This includes using the receiver to decode incoming biphase encoded audio streams and passing them via the SPORTs to internal memory for processing-or using the transmitter to encode audio or digital data and transfer it to another S/PDIF receiver in the audio system. It is important to be familiar with serial digital audio interface standards IEC-60958, EIAJ CP-340, AES3 and AES11.

Pin Descriptions
Table 14-2 provides descriptions of the pins used for the S/PDIF transmitter. Table 14-2. S/PDIF Transmitter Pin Descriptions
Internal Node DIT_CLK_I DIT_DAT_I DIT_FS_I DIT_HFCLK_I I/O Input Input Input Input Description Serial clock. Controls the rate at which serial data enters the S/PDIF module (64 FS). Serial Data. The format of the serial data can be I2S, and right- or left-justified. Serial Frame Sync. Input sampling clock. The over sampling clock (which is divided down according to the FREQMULT bit in the transmitter control register to generate the biphase clock) External Synchronization. Used for synchronizing the frame counter. If External synchronization is enabled (bit 15 of DITCTL is set), Frame counter resets at rising edge of LRCLK next to the rising edge of EXT_SYNC_I.

DIT_EXTSYNC_I

Input

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SRU Programming

Table 14-2. S/PDIF Transmitter Pin Descriptions (Contd)

Internal Node DIT_O DIT_BLKSTART_O I/O Output Output Description Transmit Biphase Mark Encoded Data Stream (AES3 format). Transmit Block Start. Indicates the last frame of the current block. This is high for the entire duration of the last frame. This can also be connected to the DAI interrupts 3122 using SRU_MISCx registers.

Table 14-3 provides descriptions of the pins used for the S/PDIF receiver. Table 14-3. S/PDIF Receiver Pin Descriptions
Internal Node DIR_I DIR_CLK_O DIR_TDMCLK_O DIR_FS_O DIR_DAT_O I/O Input Output Output Output Output Description Biphase mark encoded data receiver input stream. Extracted receiver sample clock output. This clock is 64 DIR_FS_O. Extracted receiver TDM clock out. This clock is 256 DIR_FS_O. Extracted receiver frame sync out. Extracted audio data output.

SRU Programming
The SRU (signal routing unit) is used to connect the S/PDIF transmitter biphase data out to the output pins or to the S/PDIF receiver. The serial clock, frame sync, data, and EXT_SYNC (if external synchronization is required) inputs also need to be routed through SRU (see Table 14-4).

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Table 14-4. S/PDIF DAI/SRU Signal Connections

S/PDIF TX Source DAI Connection Group A S/PDIF TX Destination DIT_CLK_I DIT_HFCLK_I DIT_EXTSYNC_I DIT_DAT_I DIT_FS_I

DIT_O

Group B Group C

DIT_O Group D DIT_BLKSTART_O DIT_BLKSTART_O Group E

The SRU (signal routing unit) needs to be programmed in order to connect the S/PDIF receiver to the output pins or any other peripherals and also for the connection to the input biphase stream. Program the corresponding SRU registers to connect the outputs to the required destinations (Table 14-5). The biphase encoded data and the external PLL clock inputs to the receiver are routed through the signal routing unit (SRU). The extracted clock, frame sync, and data are also routed through the SRU. Table 14-5. S/PDIF SRU Receiver Signal Connections
S/PDIF RX Source DIR_CLK_O DIR_TDMCLK_O DIR_DAT_O DIR_FS_O DIR_CLK_O DIR_TDMCLK_O DIR_DAT_O DIR_FS_O DAI Connection Group A Group B Group C Group D DIR_I S/PDIF RX Destination

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Register Overview

Register Overview
This section provides brief descriptions of the major registers. For complete information see Sony/Philips Digital Interface Registers on page A-195. Transmit Control Register (DITCTL). Contains control parameters for the S/PDIF transmitter. The control parameters include transmitter enable, mute information, over sampling clock division ratio, SCDF mode select and enable, serial data input format select and validity and channel status buffer selects. Transmit Channel Status Registers (DITCHANAx/Bx). Provide status bit information for transmitter subframe A and B in standalone mode. Transmit User Bit Registers (DITUSRBITAx/Bx). Provide user bit information for transmitter subframe A and B in standalone mode. Receive Control Register (DIRCTL). Contains control parameters for the S/PDIF receiver. The control parameters include mute information, error controls, SCDF mode select and enable, and S/PDIF PLL disable. Receive Status Register (DIRSTAT). The receiver also detects errors in the S/PDIF stream. These error bits are stored in the status register, which can be read by the core. Optionally, an interrupt may be generated to notify the core on error conditions. Receive Channel Status Registers (DIRCHANAx/Bx). Provide status information for receiver subframe A and B.

Clocking
The fundamental timing clock of the S/PDIF is peripheral clock/4 (PCLK/4). The clock to this module may be shut off for power savings.

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S/PDIF Transmitter
The following sections provide information on the S/PDIF transmitter.

Functional Description
The S/PDIF transmitter, shown in Figure 14-1, resides within the DAI, and its inputs and outputs can be routed via the SRU. It receives audio data in serial format, encloses the specified user status information, and converts it into the biphase encoded signal. The serial data input to the transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20 or 24 bits. Figure 14-2 shows the detail of the AES block. The serial data, clock, and frame sync inputs to the S/PDIF transmitter are routed through the signal routing unit (SRU). The S/PDIF transmitter output may be routed to an output pin via the SRU and then routed to another S/PDIF receiver or to components for off-board connections to other S/PDIF receivers. The output is also available to the S/PDIF receiver for loop-back testing through SRU. In addition to encoding the audio data in the bi-phase format, the transmitter also provides a way to easily add the channel status information to the outgoing bi-phase stream. There are status/user registers for a frame (192-bits/24 bytes) in the transmitter that correspond to each channel or subframe. For more information, see Transmitter Registers on page A-195.

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S/PDIF Transmitter

TRANSMITTER CONTROL REGISTER

DIT_CLK_I DIT_DATA_I DIT_FS_I S/PDIF SERIAL TO PARALLEL CONVERTER

AUDIO SAMPLES DIT_O AES3 (BIPHASE OUT) TRANSMITTER CONTROL

DIT_EXTSYNC_I TX_BIPHASE_CLK DIT_HFCLK_I BIPHASE CLOCK

Figure 14-1. S/PDIF Transmitter Block Diagram Validity bits for both channels may also be controlled by the transmitter control register. Optionally, the user bit, validity bit, and channel status bit are sent to the transmitter with each left/right sample. For each subframe the parity bit is automatically generated and inserted into the bi-phase encoded data. A mute control and support for double-frequency single-channel mode are also provided. The serial data input format may be selected as left-justified, I2S, or right-justified with 16-, 18-, 20- or 24-bit word widths. The over sampling clock is also selected by the transmitter control register.

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STATUS/USER BIT REGISTERS

BLK_START_O DAI

LRCLK LEFT DATA 24 24 SAMPLE LR INTERNAL BUFFER

BLK_START TX_ENABLE SAMPLE BIT BIPHASE ENCODER BIPHASE_OUT

RIGHT DATA U, V, CS LEFT U, V, CS RIGHT EXT SYNC

3 3

U, V, CS BITS

BIPHASE_CLK

BIPHASE_CLK 7

BIPHASE_TX_CLK FREQMULT 2 TX_CLK_GEN_SYNC M_COUNT

Figure 14-2. AES3 Output Block Input Data Formats The Figure 14-3 and Figure 14-4 show the format of data that is sent to the S/PDIF transmitter using a variety of protocol standards.
Bits 318: 24-Bit Audio Data 7 Validity Bit User Data Channel Status Block Start Padding (zero) 6 5 4 BITS 30

Figure 14-3. I2S and Left-Justified Formats

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S/PDIF Transmitter

format is used 16-bit data, the When IbeS placed from thewith 20-bit or24-bit audio data.audio data should MSB of the
2
Right-Justified Format, 24 Bits Bits 274: 24-Bit Audio Data Validity Bit User Data Channel Status Block Start 3 2 1 0

Right-Justified Format, 20 Bits Bits 278: 20-Bit Audio Data 7 Validity Bit User Data Channel Status Block Start Padding (zero) 6 5 4 BITS 30

Right-Justified Format, 18 Bits Bits 2710: 18-Bit Audio Data 9 Validity Bit User Data Channel Status Block Start Padding (zero) Right-Justified Format, 16 Bits Bits 2712: 16-Bit Audio Data 11 10 9 8 BITS 70 8 7 6 BITS 50

Validity Bit User Data Channel Status Block Start Padding (zero)

Figure 14-4. Right-Justified Formats

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Operating Modes
The S/PDIF transmitter can operate in standalone and full serial modes. The following sections describe these modes in detail. Full Serial Mode This mode is selected by clearing bit 9 in the DITCTL register. In this mode all the status bits, audio data and the block start bit (indicating start of a frame), come through the serial data stream (DIT_DATA_I) pin. The transmitter should be enabled after or at the same time as all of the other control bits. Standalone Mode This mode is selected by setting bit 9 in the DITCTL register. In this mode, the block start bit (indicating the start of a frame) is generated internally. The channel status bits come from the channel status buffer registers (DITCHANAx and DITCHANBx). The user status bits come from the user bits buffers (DITUSRBITAx and DITUSRBITBx) as shown in Figure 14-2 on page 14-9. be The channelisstatus buffer must for programmed before the S/PDIF transmitter enabled and used all the successive blocks of data. The validity bit for channel A and B are taken from bit 10 and bit 11 of the DITCTL register. In this mode only audio data comes from the DIT_DATA_I pin. All other data, including the status bit and block start bit is either generated internally or taken from the internal register. Once the user bits buffer registers (DITUSRBITA0-5 and DITUSRBITB0-5) are programmed, they are used only for the next block of data. This allows programs to change the user bit information in every block of data.

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S/PDIF Transmitter

To allow user bit updates, write a 0x1 to the DIT_USRUPD register that is used for further processing. If the DIT_AUTO bit in the DITCTL register is set: and if DITUSRUPD = 1, at every 192nd frame end, the user status bits are taken from user bits buffers and transmitted. Simultaneously, the DIT_USRUPD register is cleared automatically by hardware. and if DITUSRUPD = 0, at every 192nd frame end, then the user status bits are updated as zeros and transmitted. The DIT_USRUPD register remains low. For isterthe first block of transfer, write a one (1) to the and then enable the S/PDIF transmitter.
DITUSRUPD

reg-

In general, for the next block, programs can update user bits buffers at any time during the transfer of the current block (1 block = 192 frames). There are internal buffers to store the user status bits of the current block of transfer. In other words, at the beginning of every new block, the user status bit (DIT_USRPEND in the DITCTL register) from user bits buffers are copied to internal buffers and transmitted in each frame during the transfer. Note that since a frame contains 192 bits/8 = 24 bytes, six status/user registers are required to store each four bytes. Data Output Mode Two output data formats are supported by the transmitter; two channel mode and single-channel double-frequency (SCDF) mode. The output format is determined by the transmitter control register (DITCTL). In two channel mode, the left channel (channel A) is transmitted when the DIT_FS_I is high and the right channel (channel B) is transmitted when the DIT_FS_I is low.

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In SCDF mode, the transmitter sends successive audio samples of the same signal across both sub frames, instead of channel A and B. The transmitter will transmit at half the sample rate of the input bit stream. The DIT_SCDF bit (bit 4 in the DITCTL register) selects SCDF mode. When in SCDF mode, the DIT_SCDF_LR bit (bit 5 in the DITCTL register) register decides whether left or right channel data is transmitted.

S/PDIF Receiver
The S/PDIF receiver (Figure 14-5) is compliant with all common serial digital audio interface standards including IEC-60958, IEC-61937, AES3, and AES11. These standards define a group of protocols that are commonly associated with the S/PDIF interface standard defined by AES3, which was developed and is maintained by the Audio Engineering Society. The AES3 standard effectively defines the data and status bit structure of an S/PDIF stream. AES3-compliant data is sometimes referred to as AES/EBU compliant. This term highlights the adoption of the AES3 standard by the European Broadcasting Union.

Functional Description
default to receive in two-channel The S/PDIF receiver is enabled atprograms should disable the mode. If the receiver is not used, receiver as the digital PLL may produce unwanted switching noise. If the receiver is not used, programs should disable the digital PLL to avoid unnecessary switching. This is accomplished by writing into the DIR_RESET bit in the DIRCTL register. In most cases, when the S/PDIF receiver is used, this register does not need to be changed. After the SRU programming is complete, write to the DIRCTL register with control values. At this point, the receiver attempts to lock. For a detailed description of this register, see Receive Control Register (DIRCTL) on page A-200.

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S/PDIF Receiver

OFF-CHIP* LRCLK_REF_O DIGITAL PLL LRCLK_FB_O

CORE CLOCK

REFIN FBIN ANALOG PLL CLK

INT PLLCLK

SPDIF_EXTPLLCLK_I

512 x FS

FEEDBACK DIVIDER = 512

STREAM PREAMBLE DIR_CLK_O DIR_FS_O DIR_DAT_O DIR_TDMCLK_O

DIR_I (BIPHASE STREAM)

BIPAHSE DECODING REFRAMING LOGIC

S/PDIF RECEIVER *Off-chip analog PLL option is not supported

Figure 14-5. S/PDIF Receiver Block Diagram The input to the receiver (DIR_I) is a biphase encoded signal that may contain two audio channels (compressed or linear PCM) or non-audio data. The receiver decodes the single biphase encoded stream, producing an I2S compatible serial data output that consists of a serial clock, a left-right frame sync, and data (channel A/B). It provides the programmer with several methods of managing the incoming status bit information. The S/PDIF receiver receives any S/PDIF stream with a sampling frequency range of 32 kHz 15% to 192 kHz + 15% range. The channel status bits are collected into memory-mapped registers, while other channel status and user bytes must be handled manually. The block

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start bit, which replaces the parity bit in the serial I2S stream, indicates the reception of the Z preamble and the start of a new block of channel status and data bits. Clock Recovery The phased-locked loop for the AES3/SPDIF receiver is intended to recover the clock that generated the AES3/SPDIF biphase encoded stream. This clock is used by the receiver to clock in the biphase encoded data stream and also to provide clocks for either the SPORTs, sample rate converter, or the AES3/SPDIF transmitter. The recovered clock may also be used externally to the chip for clocking D/A and A/D converters. In order to maintain performance, jitter on the clock is sourced to several peripherals. In digital PLL mode (default), after the digital PLL is locked, the outputs from the S/PDIF receiver can have +/1 core clock cycle jitter in their period. Furthermore, once the PLL achieves lock, it is able to vary 15% in frequency over time. This allows for applications that do not use PLL unlocking. To be AES11 compliant, the recovered left/right clock must be aligned with the preambles within a + or 5% of the frame period. Since the PLL generates a clock 512 times the frame rate clock (512 FSCLK), this clock can be used and divided down to create the phase aligned jitter-free left/right clock. For more information on recovered clocks, see Clock Recovery on page 14-15. Output Data Format The extracted 24-bit audio data, V, U, C and block start bits are sent on the DIR_DAT_O pin in 32-bit I2S format as shown in Figure 14-3. The frame sync is transmitted on the DIR_FS_O pin and serial clock is transmitted on the DIR_CLK_O pin. All three pins are routed through the SRU.

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S/PDIF Receiver

Channel Status The channel status for the first bytes 40 (consumer mode) are collected into memory-mapped registers (DIRCTL and DIRCHANA/DIRCHANB registers). All other channel status bytes 235 (professional mode) must be manually extracted from the receiver data stream. first 5 channel status bytes (40-bit) for consumer Only theare stored into the S/PDIF receiver status registers.mode of a frame

Operating Modes
This section describes the receiver channel status for the different modes. Compressed or Non-linear Audio Data The S/PDIF receiver processes compressed as well as non-linear audio data according to the supported standards. The following sections describe how this peripheral handles different data. The AES3/SPDIF receiver is required to detect compressed or non-linear audio data according to the AES3, IEC60958, and IEC61937 standards. Bit 1 of byte 0 in the DIRSTAT register indicates whether the audio data is linear PCM, (bit 1=0), or non-PCM audio, (bit 1=1). If the channel status indicates non-PCM audio, the DIR_NOAUDIO bit flag is set. (This bit can be used to generate an interrupt.) The DIR_VALID bit (bit 3 in the DIRSTAT register) when set (=1) may indicate non-linear audio data as well. Whenever this bit is set, the VALIDITY bit flag is set in the DIR_RX_STAT register. MPEG-2, AC-3, DTS, and AAC compressed data may be transmitted without setting either the DIR_VALID bit or bit 1 of byte 0. To detect this data, the IEC61937 and SPMTE 337M standards dictate that there be a 96-bit sync code in the 16-, 20- or 24-bit audio data stream. This sync code consists of four words of zeros followed by a word consisting of 0xF872 and another word consisting of 0x4E1F. When this sync code is

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detected, the DIR_NOAUDIO bit flag is set. If the sync code is not detected again within 4096 frames, the DIR_NOAUDIO bit flag is deasserted. The last two words of the sync code, 0xF872 and 0x4E1F, are called the preamble-A and preamble-B of the burst preamble. Preamble-C of the burst preamble contains burst information and is captured and stored by the receiver. Preamble-D of the burst preamble contains the length code and is captured by the receiver. Even if the validity bit or bit 1 of byte 0 has been set, the receiver still looks for the sync code in order to record the preamble-C and D values. Once the sync code has not been detected in 4096 frames, the preamble-C and D registers are set to zero. S/PDIF The supportsreceiver in the ADSP-2147x and ADSP-2148x processors DTS frame sizes of 256, 512, 1024, 2048 and 4096. To enable support for 2048 and 4096 DTS frame sizes, set the DTS_CD_4K_EN bit in the DIRCTL register. In the ADSP-2146x processor, the on-chip S/PDIF receiver supports 256, 512 and 1024 DTS frames only. The DTS test kit frames with 2048 and 4096 frame sizes can be detected by adding the sync detection logic in software by using a software counter to check for the DTS header every 2048 and 4096 frames respectively.
Emphasized Audio Data

The receiver must indicate to the program whether the received audio data is emphasized using the channel status bits as detailed below. In professional mode, (bit 0 of byte 0 = 1), channel status bits 24 of byte 0 indicate the audio data is emphasized if they are equal to 110 or 111. In consumer mode, (bit 0 of byte 0 = 0), channel status bits 35 indicate the audio data is emphasized if they are equal to 100, 010 or 110. If emphasis is indicated in the channel status bits, the receiver asserts the EMPHASIS bit flag. This bit flag is used to generate an interrupt.

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S/PDIF Receiver

Single-Channel Double-Frequency Mode

Single-channel, double-frequency mode (SCDF) mode is selected with DIR_SCDF and DIR_SCDF_LR bits in the DIRCTL register. The DIR_B0CHANL/R bits in the DIRSTAT register also contain information about the SCDF mode. When the DIR_B0CHANL/R indicates single channel double frequency mode, the two subframes of a frame carry successive audio samples of the same signal. Bits 03 of channel status byte 1 are decoded by the receiver to determine one of the following: 0111 = single channel double frequency mode 1000 = single channel double frequency modestereo left 1001 = single channel double frequency modestereo right Clock Recovery Modes The S/PDIF receiver extracts audio data, channel status, and user bits from the biphase encoded AES3 and S/PDIF stream. In addition, a 50% duty cycle reference clock running at the sampling rate of the audio input data is generated for the PLL in the receiver to recover the oversampling clock.
Digital On-Chip PLL

The receiver can recover the clock from the biphase encoded stream using an on-chip digital PLL shown in Figure 14-5. Note the dedicated on-chip digital PLL is separate from the PLL that supplies the clock to the SHARC processor core and which is the default operation of the receiver. The left/right frame reference clock for the PLL is generated using the preambles. The recovered low jitter left/right frame clock from the PLL attempts to align with the reference clock. However, this recovered left/right clock, like the reference clock, is not phase aligned with the preambles.

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Interrupts
Table 14-6 provides an overview of S/PDIF interrupts. Table 14-6. Overview of S/PDIF Interrupts
Default Programmable Sources Interrupt DAIHI = P0I DAILI = P12I Block start Validity No audio Emphasized audio Status change Locked No audio stream CRC error Parity error Biphase error Masking DAI_IMASK_x Service

ROC from DAI_IRPTL_x DAI_IMASK_RE + RTI instruction

Sources
The S/PDIF module drives nine interrupt signals. Eight are status signals driven from SPDIFRX and one signal is driven from SPDIFTX (block start). These signals are connected into the DAI_IRPTL latch register Transmit Block Start The DIT_BLKSTART_O output signal, if routed to any miscellaneous interrupt bits (DAI_INT_31-22 in the SRU_MISCx register), triggers a block start interrupt during the last frame of current block.

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Interrupts

Receiver Status The following four receiver status generate an interrupt. Validity (DIR_VALID_INT) No audio (DIR_NOAUDIO_INT) Emphasized audio (DIR_EMPHASIS_INT) Status change (DIR_STATCNG_INT) Note the Status change interrupt is generated if any of the 40 status bits (bytes 40) have changed. Receiver Error The following four receiver error status bits generate an interrupt. Receiver Locked (DIR_LOCK_INT) No Audio Stream (DIR_NOSTREAM_INT) CRC Error (DIR_CRCERROR_INT) Parity or biphase Error (DIR_ERROR_INT) Notice that parity error and biphase error are ORed together to form a interrupt. The CRCERROR bit is not available in the DIRSTAT register. The CRCERROR interrupt latch bit is set whenever the CRC check of the channel status bits fails. The CRC check is only performed if channel status bit 0 of byte 0 is high, indicating professional mode.
DIR_ERROR_INT

Masking
For the S/PDIF receive the DAI_IMASK_RE register must be unmasked accordingly. For the S/PDIF transmit the DAI_IMASK_x register must be unmasked accordingly.

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The DAIHI and DAILI signals are routed by default to programmable interrupt.To service the DAIHI, unmask (set = 1) the P0I bit in the IMASK register. To service the secondary DAILI, unmask (set = 1) the P12IMSK bit in the LIRPTL register. For DAI system interrupt controllers the DAI_IMASK_RE or DAI_IMASK_FE register must be unmasked. For example:
bit set IMASK P0I; bit set LIRPTL P12IMSK; ustat1=dm(DAI_IMASK_RE); bit set ustat1 DIR_LOCK_INT; dm(DAI_IMASK_RE)=ustat1; /* unmasks P0I interrupt */ /* unmasks P12I interrupt */ /* set SPDIF RX lock */

Service
The ISR reads the DAI_IRPTL_x register to clear the interrupt request.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

Programming Model
The following sections provide information on programming the transmitter and receiver.

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Programming Model

Programming the Transmitter

Since the S/PDIF transmitter data input is not available to the core, programming the transmitter is as simple as: 1) connecting the SRU to the on-chip (serial ports or input data port) or off-chip (DAI pins) serial devices that provide the clock and data to be encoded, and 2) selecting the desired mode in the transmitter control register. This setup can be accomplished in three steps. 1. Connect the transmitters four required input signals and one biphase encoded output in the SRU. The four input signals are the serial clock (DIT_CLK_I), the serial frame sync (DIT_FS_I), the serial data (DIT_DAT_I), and the high frequency clock (DIT_HFCLK_I) used for the encoding. The only output of the transmitter is DIT_O. 2. If user bits are required, write 0x1 to the DITUSRUPD register for the first block of transfer. Also route the DIT_BLK_START_O signal to the DAI_INT_3122 (DAI_IRPTLx register). This generates interrupts during the last frame of the block (192), allowing changes of user bits for the next block. 3. Initialize the DITCTL register to enable the data encoding. 4. Manually set the block start bit in the data stream once per block (every 384 words). This is necessary if automatic generation of block start information is not enabled in the DITCTL register, (DIT_AUTO = 0).

Programming the Receiver

Since the S/PDIF receiver data output is not available to the core, programming the peripheral is as simple as connecting the SRU to the on-chip (serial ports or input data port) or off-chip (DAI pins) serial devices that provide the clock and data to be decoded, and selecting the

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desired mode in the receiver control register. This setup can be accomplished in two steps. 1. Connect the input signal and three output signals in the SRU for. The only input of the receiver is the biphase encoded stream, DIR_I. The three required output signals are the serial clock (DIR_CLK_O), the serial frame sync (DIR_FS_O), and the serial data (DIR_DAT_O). The high frequency clock (DIR_TDMCLK_O) derived from the encoded stream is also available if the system requires it. 2. Initialize the DIRCTL register to enable the data decoding. Note that this peripheral is enabled by default.

Interrupted Data Streams on the Receiver

When using the S/PDIF receiver with data streams that are likely to be interrupted, (in other words unplugged and reconnected), it is necessary to take some extra steps to ensure that the S/PDIF receivers digital PLL will re lock to the stream. The steps to accomplish this are described below. 1. Set up interrupts within the DAI so that the S/PDIF receiver can generate an interrupt when the stream is reconnected. 2. Within the interrupt service routine (ISR), stop and restart the digital PLL. This is accomplished by setting and then clearing bit 7 of the S/PDIF receiver control register. 3. Return from the ISR and continue normal operation. This method of resetting the digital PLL has been shown to provide extremely reliable performance when S/PDIF inputs that are interrupted or unplugged momentarily occur. The following procedure and the example code show how to reset the digital PLL. Note that all of the S/PDIF receiver interrupts are handled through the DAI interrupt controller.

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Programming Model

1. Initialize the No Stream Interrupt

/* Enable interrupts (globally) */ BIT SET MODE1 IRPTEN; /* unmask DAI Hi=Priority Interrupt */ bit set imask DAIHI; ustat1 = DIR_NOSTREAM_INT; /* Enable no-stream Interrupt on Falling Edge. Interrupt occurs when the stream is reconnected */ dm(DAI_IRPTL_FE) = ustat1; /* Enable Hi-priority DAI interrupt */ dm(DAI_IRPTL_PRI) = ustat1; /* If more than 1 DAI interrupt is being used, it is necessary to determine which interrupt occurred here */ /* Interrupt Service Routine for the DAI Hi-Priority Interrupt. This ISR triggered when the DIR sets no_stream bit */ _DAIisrH:

2. Reset the Digital PLL Inside of the ISR

r8=dm(DAI_IRPTL_H); ustat2=dm(DIRCTL); bit set ustat2 DIR_PLLDIS; dm(DIRCTL)=ustat2; bit clr ustat2 DIR_PLLDIS; dm(DIRCTL)=ustat2; /*reenable the digital pll */ /* bit_7 disables digital pll only */ /* Reading DAI_IRPTL_H clears interrupt */

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Debug Features
The following feature supports S/PDIF debugging.

Loopback Routing
The S/PDIF supports an internal loopback mode by using the SRU. For more information, see Loopback Routing on page 10-39.

Shadow Interrupt Registers

For more information, see Debug Features on page 2-15.

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Debug Features

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15 PRECISION CLOCK GENERATOR

The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D, are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. Table 15-1 lists the PCG specifications. Table 15-1. PCG Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Yes No N/A N/A N/A Yes No N/A N/A N/A No Yes No No No No No Yes No Yes No No PCGAB PCGCD

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Features

Table 15-1. PCG Specifications (Contd)

Feature Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Max Clock Operation No N/A N/A N/A N/A N/A No fPCLK No N/A N/A N/A N/A N/A No fPCLK PCGAB PCGCD

Features
The following list describes the features of the precision clock generators. Operates on the DAI and DPI units. PCG input clock selection from CLKIN, PCLK or external DAI pins. Provides four different clock dividers for serial clock, frame sync, phase (20-bit) and pulse width (16-bit). Phase shift allows adjustment of the frame sync relative to the serial clock and can be shifted the full period and wrap around. Provides pulse width control for arbitrary frame sync signal generation.

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Bypass mode for external frame sync manipulation. External trigger mode starts PCG operation. No additional jitter introduced since operation is independent of the on-chip PLL by using off-chip clocks.

Pin Descriptions
Table 15-2 provides the pin descriptions for the PCGs (x = unit A, B, C, or D). Table 15-2. PCG Pin Descriptions
Internal Nodes Inputs CLKIN PCLK PCG_SYNC_CLKx_I PCG_EXTx_I MISCA2_I MISCA3_I MISCA4_I MISCA5_I Outputs PCG_CLKx_O PCG_FSx_O O O Serial clock x output Frame sync x output I I I I I I I I External clock input for PCG x Internal peripheral clock input for PCG x External trigger used to enable the frame sync output External clock A input provided to the PCG x (not CLKIN) External frame sync used for bypass mode PCG A External frame sync used for bypass mode PCG B External frame sync used for bypass mode PCG C External frame sync used for bypass mode PCG D I/O Description

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SRU Programming

SRU Programming
To use the PCG, route the required inputs using the SRU as described Table 15-3. Also, use the SRU to connect the outputs to the desired DAI pin. Table 15-3. PCG SRU Connections
DAI Source PCG_SYNC_CLKA_O PCG_SYNC_CLKB_O DAI Group Group A DPI Group DAI Destination PCG_SYNC_CLKA_I PCG_SYNC_CLKB_I PCG_SYNC_CLKC_I PCG_SYNC_CLKD_I PCG_EXTA_I PCG_EXTB_I PCG_EXTC_I PCG_EXTD_I

PCG_FSA_O PCG_FSB_O PCG_CLKA_O PCG_CLKB_O PCG_FSA_O PCG_FSB_O PCG_CLKC_O* PCG_CLKD_O* PCG_FSC_O* PCG_FSD_O* PCG_CLKB_O PCG_FSA_O PCG_FSB_O

Group C Group D

Group B*

Group E

MISCA2_I MISCA3_I MISCA4_I MISCA5_I

cannot input. Setting A PCG clock output connectsbe fed to its ownlogic low, not to to
SRU_CLK4[4:0] = 28 PCG_CLKA_O. PCG_EXTA_I

Setting SRU_CLK4[9:5] = 29 connects PCG_EXTB_I to logic low, not to PCG_CLKB_0. The clock and frame sync signals of

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Precision Clock Generator

PCG C and D cannot be directly connected to other peripheral clock and frame sync signals. They can only be routed through the DAI pins.

Register Overview
The processor contains registers that are used to control the PCGs. Control Register 0 (PCG_CTLx0). Enables the clock and frame sync, it includes the frame sync divider and the upper half of the 20-bit phase value. Control Register 1 (PCG_CTLx1). Enables the clock and frame sources, it includes the clock divider and the lower half of the 20-bit phase value. Pulse Width Register (PCG_PWx). Contains the pulse with settings for normal mode (FSDIV > 1) or control bits for bypass mode (FSDIV = 1/0). Enables direct bypass or one shot mode. Synchronization Register (PCG_SYNCx). Enables PCLK as input clock to the PCGs. It also enables external FS trigger mode.

Clocking
The fundamental clock of the PCG is PCLK. The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

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Functional Description

Functional Description
The following sections provide information on the function of the precision clock generators.
PRECISION CLOCK GENERATOR SERIAL CLOCK BYPASS/ INVERT PCG_CLKABCD_O CLKDIV

PCG_SYNC_CLKx_I CLKIN

Ext. Trigger

OUTPUT DAI

FRAME SYNC PCLK PULSE WIDTH

INPUT DAI

FSDIV

FS PHASE

PCG_FSABCD_O

PCG_EXTx_I MISCA5-2_I

BYPASS/ INVERT ONE SHOT/ INVERT

PCG_FSCD_O INPUT DPI PCG_CLKCD_O

Figure 15-1. PCG Block Diagram

Serial Clock
Each of the four units (A, B, C, and D) produces a clock output. Serial clock generation from a unit is independently enabled and controlled. Sources for the serial clock generation can be either from the CLKIN, PCLK, or a DAI pin source. The clock output is derived from the input to the PCG with a 20-bit divisor. Note that the divider is working in normal mode for CLKxDIV > 1. For CLKxDIV = 0 or 1 the divider operates in bypass mode, (input clock is fed directly to its output). Note that in bypass mode, the clock at the output

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Precision Clock Generator

can theoretically run at up to the PCLK frequency. However the DAI/DPI pin buffers limit the speed to PCLK/4. Note that the clock output is always set (as closely as possible) to a 50% duty cycle. If the clock divisor is even, the duty cycle of the clock output is exactly 50%. If the clock divisor is odd, then the duty cycle is slightly less than 50%. The low period of the output clock is one input clock period more than the high period of the output clock. For higher values of an odd divisor, the duty cycle is close to 50%.

A PCG clock output cannot be fed to its own input.

Frame Sync
The following sections describe the use of frame syncs in the PCGs. Frame Sync Output Each of the four units (A through D) also produces a synchronization signal for framing serial data. The frame sync outputs are much more flexible since they need to accommodate the wide variety of serial protocols used by peripherals. Frame sync generation from a unit is independently enabled and controlled. Sources for the frame sync generation can be either from the crystal buffer output, PCLK, or an external pin source. There is only one external source pin for both frame sync and clock output for a unit. If an external source is selected for both frame sync and clock output for a unit, then they operate on the same input signal. Apart from enable and source select control bits, frame sync generation is controlled by a 20-bit divisor.

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Functional Description

Divider Mode Selection If frame sync divisor > 1 the PCG frame sync output frequency is equal to the input clock frequency, divided by a 20-bit integer. This integer is specified in the FSDIV bit field (bits 190 of the PCG_CTLx0 register). However if the frame sync divisor is zero or one, the PCGs frame sync clock generation unit is bypassed, and the frame sync input is connected directly to the frame sync output. For FSDIV=0, 1 the PCG_PWx registers have different functionality than in normal mode. Phase Shift Phase shift is a frame sync parameter that defines the phase shift of the frame sync with respect to the input clock of the same unit. This feature allows shifting of the frame sync signal in time relative to the clock input signal. Frame sync phase shifting is often required by peripherals that need a frame sync signal to lead or lag a clock signal. For example, the I2S protocol specifies that the frame sync transition from high to low occur one clock cycle before the beginning of a frame. Since an I2S frame is 64 clock cycles long, delaying the frame sync by 63 cycles produces the required framing. Phase shifting is represented as a full 20-bit value so that even when the frame sync is divided by the maximum amount, the phase can be shifted to the full range, from zero to one input clock short of the period. is specified a 2 x Phase shiftingbit field (bitsas2920)10-bit divider value in theand in of the register
FSxPHASE_HI PCG_CTLxO

the FSxPHASE_LO bit field (bits 2920) of the PCG_CTLx1 register. A single 20-bit value spans these two bit fields. The upper half of the word (bits 1910) is in the PCG_CTLxO register, and the lower half (bits 90) is in the PCG_CTLx1 register.

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The phase shift between clock and frame sync outputs may be programmed using the PCG_PW and PCG_CTLxx registers under these conditions: The input clock source for the clock generator output and the frame sync generator output is the same. The clock and frame sync are enabled at the same time using a single atomic instruction. The frame sync divisor is an integral multiple of the clock divisor. using a clock as a synchronous Whenbe enabled in aand frame sync instruction beforepair, the units must single atomic their parameters are modified. Both units must also be disabled in a single atomic instruction as shown below.
r0 = CLKDIV|PHASE_LO; dm(PCG_CTLA1) = r0; r0 = FSDIV|PHASE_HI|ENCLKA|ENFSA; dm(PCG_CTLA0) = r0; /* program dividers and enable CLK and FS */

0 (see Figure If the phase shift issame time. 15-2), the clock and frame sync outputs rise at the If the phase shift is 1, the frame sync output transitions one input clock period ahead of the clock transition. If the phase shift is divisor 1, the frame sync transitions divisor 1 input clock periods ahead of the clock transitions.

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Functional Description

CLOCK INPUT (FOR BOTH CLOCK AND FRAME SYNC)

CLOCK OUTPUT

FRAME SYNC OUTPUT (PHASE SHIFT = PERIOD -1)

FRAME SYNC OUTPUT (PHASE SHIFT = 0)

FRAME SYNC OUTPUT (PHASE SHIFT = 1)

FRAME SYNC OUTPUT (PHASE SHIFT = 2) ENABLE OTHER VALUES: CLOCK DIVISOR = 4 FRAME SYNC DIVISOR = 16 PULSE WIDTH = 8

Figure 15-2. Phase and Pulse Width Settings single frame sync of one cycle) If generating taken with respectpulses (the length sampling edges. If care must be to the drive and
SCLK

the rules are violated, for example if the SPORT is not driving data, it will not able to detect a valid sample edge. Pulse Width Pulse width is the number of input clock periods for which the frame sync output is high. A 16-bit value determines the width of the framing pulse. Settings for pulse width can range from zero to DIV 1. The pulse width should be less than the divisor of the frame sync. The pulse width of frame sync is specified in the PWFSx bits (150) and (3116) of the PCG_PWx registers.

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Default Pulse Width If the pulse width count is equal to 0 and if FSDIV bit field is even, then the actual pulse width of the frame sync output is equal to: For even divisors: frame sync divisor/2 If the pulse width count is equal to 0 and if FSDIV bit field is odd, then the actual pulse width of the frame sync output is equal to: For odd divisors: frame sync divisor 1/2 Input Clock Source Considerations The core phase-locked loop (PLL) has been designed to provide clocking for the processor core. Although the performance specifications of this PLL are appropriate for the core, they have not been optimized or specified for precision data converters where jitter directly translates into time quantization errors and distortion. Therefore the PCG allows the routing of external clock sources which are independent of the core PLL. Timing Example for I 2 S Mode For I2S mode, the frame sync should be driven at the falling edge of SCLK. In other words, the frame sync edge should coincide with the falling edge of the SCLK. To satisfy this requirement, the phase of the frame sync should be programmed accordingly in the PCG_CTLxx registers. For example, assume that the input clock source for both clock and frame sync are the same and both the clock and frame sync are enabled at the same time. Also assume that the clock divisor value needed to generate the required SCLK is CLKxDIV = 4. Then, for a 32-bit word length, the frame sync divisor value should be FSDIV = 64 CLKxDIV = 256.

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Operating Modes

By default, for phase = 0, the rising edge of both SCLK and frame sync will coincide. To make sure that the frame sync edges coincides with the falling edge of the SCLK, the phase value needs to be programmed as CLKxDIV/2 = 2. It can be done by following instructions:
ustat1=CLKDIV|((CLKDIV/2) << 20); dm(PCG_CTLx1) = ustat1;

For details on how to program phase of the frame sync see Programming Model on page 15-20.

Operating Modes
The following sections provide information on the operating modes of the precision clock generator.

Normal Mode
When the frame sync divisor is set to any value other than zero or one, the PCGs operates in normal mode. In normal mode, the frequency of the frame sync output is determined by the divisor where: Frequency of Frame Sync Output =

Input Frequency Divisor

The high period of the frame sync output is controlled by the value of the pulse width control. The value of the pulse width control should be less than the value of the divisor. The phase of the frame sync output is determined by the value of the phase control. If the phase is zero, then the positive edges of the clock and frame sync coincide when: the clock and frame sync dividers are enabled at the same time using an atomic instruction

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Precision Clock Generator

the divisors of the clock and frame sync are the same the source for the clock and frame sync is the same The number of input clock cycles that have already elapsed before the frame sync is enabled is equal to the difference between the divisor and the phase values. If the phase is a small fraction of the divisor, then the frame sync appears to lead the clock. If the phase is only slightly less than the frame sync divisor, then the frame sync appears to lag the clock. The frame sync phase should not be greater than the divisor.

Bypass Mode
When the frame sync divisor for the frame sync has a value of zero or one, the frame sync is in bypass mode, and the PCG_PWx registers have different functionality than in normal mode. 150 and the registers are In normal mode bits pulse width3118 ofIn bypass mode bits 152 used to program the count.
PCG_PWx

and 3118 are ignored. Bits 10 and 1716 are renamed to STROBEx and INFSx respectively. This is described in more detail below. If the STROBEx bit of PCG_PWx register is cleared, then the input is directly passed (see Figure 15-3) to the frame sync output either inverted or not inverted, depending on the INVFSx bit of the PCG_PWx registers.
CLOCK INPUT FOR FRAME SYNC

FRAME SYNC OUTPUT (INVFSA = 0, STROBEA = 0)

FRAME SYNC OUTPUT (INVFSA = 1, STROBEA = 0)

Figure 15-3. Bypass and Inverted Bypass

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Operating Modes

One-Shot Mode
In one-shot mode operation (see Figure 15-4), the PCG produces a series of periods but does not run continuously.
WHEN MISCA2 INPUT IS LOW, OUTPUTS ARE ALSO LOW

C LOCK INPUT FOR FRAME SYNC MISCA2_I

FRAME SYNC OUTPUT (INVFSA = 0, STROBEA = 1) FRAME SYNC OUTPUT (INVFSA = 1, STROBEA = 1)

Figure 15-4. One Shot Mode PCG A (MISCA2_I input) Bypass mode also enables the generation of a strobe pulse (one shot frame sync). Strobe usage ignores the divider counters and looks to the SRU to provide the input signal. Two bit fields determine the operation in this mode. In the bypass mode, if the STROBEx bit of PCG_PWx register is set to 1, then a one-shot pulse is generated. This one-shot pulse has the duration equal to the period of MISCAx_I for the PCGx unit. This pulse is generated either at the falling or rising edge of the input clock, depending on the value of the INVFSx bit of the PCG_PW register. The output pulse width is equal to the period of the SRU source signal MISCAx_I. The pulse begins at the second rising edge of MISCAx_I following a rising edge of the clock input. When the INVFSx bit is set, the pulse begins at the second rising edge of MISCAx_I coinciding with or following a falling edge of the clock input.

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a strobe period defined FS input Noticesignal specified byis the to be the period of theregisters). clock bit (
FSxSOURCE PCG_CTLx1

External Event Trigger

The trigger with the external clock is enabled by setting bits 0 and 16 of the PCG_SYNC register. Since the rising edge of the external clock is used to synchronize with the frame sync, the frame sync output is not generated until a rising edge of the external clock is sensed (Figure 15-5).
TRIGGER DELAY

CLKIN (INPUT)

EXT. TRIGGER (INPUT)

FSA (OUTPUT)

Figure 15-5. FS Output Synchronization With External Trigger Input External Event Trigger Delay The time delay between the rising trigger edge and the start of SCLK/FS varies between 2.5 to 3.5 input clock periods. If the input clock and the trigger signal are synchronous, the delay is 3 input clock periods. The following cases need to be considered: is the input source. In this case if the given trigger event is synchronous to PCLK, the delay is 3 PCLK periods. If the trigger signal is asynchronous with PCLK, the delay varies from 2.5 PCLK periods to 3.5 PCLK periods. (It depends on whether the trigger edge occurs in the positive half cycle or negative half cycle of PCLK.)
PCLK

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Operating Modes

is the input source. In this case if the given trigger signal is synchronous to CLKIN, the delay is 3 CLKIN periods. But if they are asynchronous to CLKIN, the delay can vary between 2.5 CLKIN periods to 3.5 CLKIN periods.
CLKIN

SRU is the input source. If the input clock and trigger signal are synchronous, the delay is exactly 3 input clock periods. If asynchronous, it varies between 2.5 to 3.5 input clock periods depending on the phase difference between the input clock and trigger signal.

Audio System Example

Figure 15-6 shows an example of the internal interconnections between the SPDIF receiver, ASRC, and the PCGs. The interconnections are made by programming the signal routing unit. It shows how to set up two precision clock generators using the S/PDIF receiver and an asynchronous sample rate converter (ASRC) to interface to an external audio DAC. The PCG is configured to provide a fixed ASRC/DAC output sample rate of 65.098 kHz. The input to the S/PDIF receiver is typically 44.1 kHz if supplied by a CD player, but can also be from other source at any nominal sample rate from about 22 kHz to 192 kHz. Similarly, the phase shift for frame syncs B, C, and D is specified in the corresponding PCG_CTLxO and PCG_CTLx1 registers. Three synchronous clocks are required in audio systems 1. Frame sync (FS) 2. Serial bit clock (64 FS) 3. Master DAC clock (256 FS)

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Precision Clock Generator

CD PLAYER
DAI_P19 SPDIFIN (FSIN, 44.1 kHz) SPDIF RX

ADSP-214xx
RxSCLK RxLRCLK SDATAIN FSYNCA (FSOUT) SCLKA (64 FSOUT) ASRC SDATAOUT

FSOUT = 65.1 kHz 24-BIT LEFT-JUSTIFIED DAI_P8 DAI_P9 DAI_P10

SDATAIN LRCLKIN SCLKIN

FCLKIN

PCG_ FSA_O PCG_ CLKA_O

STEREO DAC

PCG_ CLKB_O

SCLKB (256 FSOUT)

DAI_P11 MCLKIN LEFTOUT PCLK/4 HEAD PHONES RIGHTOUT

PCLK CCLK

PLL

CCLK2

CCLK4

Figure 15-6. PCG Setup for I2S or Left-Justified DAI Since each PCG has only two outputs, this example requires two PCGs. Furthermore, because the digital audio interface requires a fixed-phase relation between SCLK and FS, these two outputs should come from one PCG (PCG A) while the master clock comes from the 2nd (PCG B). The combined PCGs can provide a selection of synchronous clock frequencies to support alternate sample rates for the ASRCs and external DACs. However, the range of choices is limited by CLKIN and the ratio of PCG_CLKx_O:SCLK:FS which is normally fixed at 256:64:1 to support digital audio left-justified, I2S and right-justified interface modes. Many DACs also support 384, 512, and 786x FS for PCG_CLKx_O, which allows some additional flexibility in choosing CLKIN.

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Operating Modes

Note the falling edge of SCLK must always be synchronous with both edges of FS. This requires that the phase of the SCLK and FS signals for a common PCG (PCG A) be adjustable. While the frequency of the master DAC clock (PCG_CLKx_O) must be synchronous with the sample rate supplied to the external DAC, there is no fixed phase requirement. Set the clock divisor and source and low-phase word first, followed by the control register enable bits, which must be set together. When the PCG_PW register is set to zero (default) the FS pulse width is (divisor 2) for even divisors and (divisor 1) 2 for odd divisors. Alternatively, the PCG_PW register could be set high for exactly one-half the period of CLKIN cycles for a 50% duty cycle, provided the FS divisor is an even number.

Clock Configuration Examples

For a CLKIN = 33.330 MHz the two PCGs provide the three synchronous clocks PCGx_CLK, SCLK and FS for the SRCs and external DAC. These divisors are stored in 20-bit fields in the PCG_CTL registers. The integer divisors for several possible sample rates based on 33.330 MHz CLKIN are shown in Table 15-4. Table 15-4. Precision Clock Generator Division Ratios (33.330 CLKIN)
PCG Divisors Sample Rate kHz) 130.195 65.098 43.398 32.549 26.039 1 2 3 4 5 CLKDIV B 4 8 12 16 20 CLKDIV A 256 512 768 1024 1280 FSDIV A1

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Precision Clock Generator

Table 15-4. Precision Clock Generator Division Ratios (33.330 CLKIN) (Contd)
PCG Divisors Sample Rate kHz) 21.699 18.599 1 6 7 CLKDIV B 24 28 CLKDIV A FSDIV A1 1536 1792

The frame sync divisor should be an even integer in order to produce a 50% duty cycle waveform. See Frame Sync on page 15-7.

For more information on core clock setting, see Power Management Registers (PMCTL, PMCTL1) on page A-7.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

PCG Effect Latency

After the PCG registers are configured the effect latency is shown below. The latency to start the CLKOUT depends on the divisor value and input source as described below. Input clock through PCLK If the divisor value is 0 or 1 (bypassed) the latency is 1 PCLK cycle For other divisor values the latency is 3 PCLK cycles ADSP-214xx SHARC Processor Hardware Reference 15-19

Programming Model

Input clock through CLKIN If the divisor is 0 or 1 (bypassed) the latency can vary from 0 to 1 oscillator period. This is because clock generation starts with the immediate positive edge of the CLKIN. For other divisor values the latency can vary between 2 to 3 oscillator periods. This is because clock generation starts with the third positive edge of CLKIN. Input clock through SRU If the divisor is 0 or 1 (bypassed) the latency can vary from 0 to 1 input clock period. For example if the input clock has a period of 100 ns then this latency can be a maximum of 100 ns. For other divisor values the latency can vary between 2 to 3 input clock periods. For example if the input clock has a period of 100 ns then this latency can be between 200 and 300 ns.

Programming Model
The section describes which sequences of software steps required for successful PCG operation. If the PCG is being disabled in order to re-program a parameter, please use a delay after writing to the disable bit should be used. This delay in core clock (CCLK) cycles = (PCG source clock period/CCLK period). In summary, the following general procedure should be used. 1. Clear the PCG enable bits without modifying any other settings. 2. Wait for N CCLK cycles (N = PCG source clock period/processor clock period).

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Precision Clock Generator

3. Program all new parameters without setting the PCG enable bit. 4. Enable the PCG.

Frame Sync Phase Setting

The phase unit requires that the clock and FS is enabled simultaneously in an atomic instruction. 1. Write the clock divider/low 10-bit Phase divider to PCG_CTLx1 register. 2. Program the FS divider/high 10-bit phase divider, enable both the ENCLKx and ENFSx bits in the PCG_CTLx0 registers. Note that both units must be disabled in the same way.

External Event Trigger

The trigger with the external clock is enabled by setting bits 0 and 16 of the PCG_SYNC register. The phase must be programmed to 3, so that the rising edge of the external clock is in sync with the frame sync (Figure 15-5). Programming should occur in the following order. 1. Program the PCG_SYNC and the PCG_CTLA01, PCG_CTLB01 registers appropriately. 2. Enable clock or frame sync, or both. Since the rising edge of the external clock is used to synchronize with the frame sync, the frame sync output is not generated until a rising edge of the external clock is sensed.

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Debug Features

Debug Features
Care should be taken in cases where any input to the phase unit is modified. Any individual change of the CLKDIV or FSDIV dividers may cause a failure in PCG sync operation between the serial clock and the frame sync. Only the programming model ensures a correct setup for phase settings.

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16 SERIAL PERIPHERAL INTERFACE PORTS

The ADSP-214xx processors are equipped with two synchronous serial peripheral interface ports that are compatible with the industry-standard serial peripheral interface (SPI). Each SPI port also has its own set of registers (the secondary register set contains a B as in SPIBAUDB). The SPI ports support communication with a variety of peripheral devices including codecs, data converters, sample rate converters, S/PDIF or AES/EBU digital audio transmitters and receivers, LCDs, shift registers, microcontrollers, and FPGA devices with SPI emulation capabilities. The interface specifications are shown in Table 16-1. Table 16-1. SPI Port Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Yes Yes Yes Yes No No N/A Yes Yes Yes SPI/SPIB

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Features

Table 16-1. SPI Port Specifications (Contd)

Feature Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Max Clock Operation Yes Yes Yes 1 Yes Yes No fPCLK/4 (slave) fPCLK/8 (master) SPI/SPIB Yes (Core and DMA)

Features
The processors SPI ports provide the following features and capabilities. A simple 4-wire interface consisting of two data pins, a device select pin, and a clock pin. Special data formats to accommodate little and big endian data, different word lengths, and packing modes. Master and multiples slave (multi devices) in which the ADSP-214xx master processor can be connected to up to four other SPI devices. Parallel core and DMA access allow full duplex operation. Open drain outputs to avoid data contention and to support multimaster scenarios.

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Programmable baud rates, clock polarities, and phases (SPI mode 03). Master or slave booting from a master SPI device. See SPI Port Booting on page 24-12. DMA capability to allow transfer of data without core overhead. See DMA Transfers on page 16-24. Internal loopback mode (by connecting MISO to MOSI). Note the SPI interface does not support daisy chain operation, where the MOSI and MISO pins are internally connected through a FIFO, allowing bypass of data streams.

Pin Descriptions
The SPI protocol uses a 4-wire protocol to enable full-duplex serial communication. Table 16-2 provides detailed pin descriptions and Figure 16-1 shows the master-slave connections between two devices. Table 16-2. SPI Pin Descriptions
Internal Node SPI_CLK_I/O SPIB_CLK_I/O Type I/O Description SPI Clock Signal. This control line is clock driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates. The CLK line cycles once for each bit that is transmitted. It is an output signal if the device is configured as a master; it is an input signal if configured as a slave. SPI Slave Device Select. This is an active-low input signal that is used to enable slave devices. This signal is like a chip select signal for the slave devices and is provided by the master device. For a master device, it can act as an error input signal in a multi-master environment. In multi-master mode, if the SPI_DS_I input signal of a master is asserted (Low) an error has occurred. This means that another device is also trying to be the master.

SPI_DS_I SPIB_DS_I

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SRU Programming

Table 16-2. SPI Pin Descriptions (Contd)

Internal Node SPI_MOSI_I/O SPIB_MOSI_I/O Type I/O Description SPI Master Out Slave In. This data line transmits the output data from the master device and receives the input data to a slave device. This data is shifted out from the MOSI pin of the master and shifted into the MOSI input(s) of the slave(s). SPI Master In Slave Out. This data line transmits the output data from the slave device and receives the input data to the master device. This data is shifted out from the MISO pin of the slave and shifted into the MISO input of the master. There may be no more than one slave that is transmitting data during any particular transfer. SPI Slave Select Out. The slave select pins are used to address up to 4 slaves in a multi device system. This functionality can be routed to any of the DPI pins. This frees up the multiplexed core flags for other purposes. SPI Pin Buffer Enable Out Signal. Only driven in master mode. The SPIx_FLGx_PBEN_O signals are enabled if the corresponding DSxEN bits in the SPIFLAG register are set.

SPI_MISO_I/O SPIB_MISO_I/O

I/O

SPI_FLG3-0_O SPIB_FLG3-0_O

SPI_CLK_PBEN_O SPIB_CLK_PBEN_O SPI_MOSI_PBEN_O SPIB_MOSI_PBEN_O SPI_MISO_PBEN_O SPIB_MISO_PBEN_O SPI_FLG3-0_PBEN_O SPIB_FLG3-0_PBEN_O

SRU Programming
Both SPI and SPIB signals are available through the SRU2, and are routed as described in Table 16-3. Since the SPI supports a gated clock, it is recommended that programs enable the SPI clock output signal with its related pin buffer enable. This can be done using the macro SRU (SPI_CLK_PBEN_O, PBEN_03_I). If these signals are routed statically high as in SRU (high, PBEN_03_I) some SPI timing modes that are based on polarity and phase may not work correctly because the timing is violated.

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Serial Peripheral Interface Ports

Table 16-3. SPI SRU2 Signal Connections

SPI Source DPI Group Group A SPI Destination SPI_CLK_I SPIB_CLK_I SPI_DS_I SPIB_DS_I SPI_MOSI_I SPIB_MOSI_I SPI_MISO_I SPIB_MISO_I

SPI_CLK_O SPIB_CLK_O SPI_MOSI_O SPIB_MOSI_O SPI_MISO_O SPIB_MISO_O SPI_FLG30_O SPIB_FLG30_O SPI_CLK_PBEN_O SPIB_CLK_PBEN_O SPI_MOSI_PBEN_O SPIB_MOSI_PBEN_O SPI_MISO_PBEN_O SPIB_MISO_PBEN_O SPI_FLG30_PBEN_O SPIB_FLG30_PBEN_O

Group B

Group C

Register Overview
This section provides brief descriptions of the major registers. For complete information see Serial Peripheral Interface Registers on page A-219. SPI Control (SPICTLx). Configures the fundamental transfer initiation mode (core or DMA) and configure timing bits and enable the SPI port.

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Clocking

SPI DMA Control (SPIDMACx). Controls the DMA channel on the SPI. Corresponding status bits provide status or error information on transmission. SPI Flag (SPIFLAGx). Enables the chip selects output in master mode and returns status for errors in multiprocessor systems. SPI Status (SPISTATx). Provides information on transmission errors for the core. SPI Baud rate (SPIBAUDx). For master devices, the clock rate is determined by the 15-bit value of the baud rate registers (SPIBAUDx) as shown in Table 16-4. For slave devices, the value in the SPIBAUDx register is ignored.

Clocking
The fundamental timing clock of the SPI module is peripheral clock/4 (PCLK/4) for slave mode and peripheral clock/8 (PCLK/8) for master mode. In master mode the settings define the SPI master clock. Master Baud Rate = PCLK/(4 BAUDR) for BAUDR 232767. The baud rate settings are shown in Table 16-4. Table 16-4. SPI BAUD Rate PCLK = 200 MHz
BAUDR Bit Setting 0 1 2 3 4 Divider N/A N/A 8 12 16 SPICLK N/A N/A 25 16.66 12.5

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Table 16-4. SPI BAUD Rate PCLK = 200 MHz (Contd)

BAUDR Bit Setting 25 32,767 Divider 100 131068 SPICLK 2.0 (master boot) 1526 Hz

The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

Choosing the Pin Enable for the SPI Clock

When using the SPI in master mode, and the SPIxCLK signal is routed onto the DPI pin, then the DPI_PBENxx_I signal for that DPI pin being used for the clock must be connected to high. However, depending on the SPI mode being used (based on the setting of CPHASE and CLKPL bits in the SPICTL register), SPIx_CLK_PBEN_O signal may be used.
SPIx_CLK

Choosing the correct pin enable ensures that the very first edge on (DPI pin) output is not incorrectly chosen as a sampling edge by the slave SPI. Table 16-5 shows the correct pin enable to use for a chosen SPI mode.

Table 16-5. Pin Enable Selection by Mode

Mode 0 1 2 3 CLKPL 0 0 1 1 CPHASE 0 1 0 1 Pin Enable HIGH HIGH SPIx_CLK_PBEN_O SPIx_CLK_PBEN_O

All other SPI signals SPIx_MOSI, SPIx_MISO and SPIx_FLGx signals when routed on the DPI pins, the SPIx_MISO_PBEN_O, SPIx_MOSI_PBEN_O, or

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Functional Description

signals should be connected to corresponding DPI_PBENxx_I signals. The DPI_PBENxx_I signals should not be statically connected to high, as it affects the functioning of certain bits in the SPICTLx register.
SPIx_FLG_PBEN_O

Functional Description
Each SPI interface contain its own transmit shift (TXSR, TXSRB) and receive shift (RXSR, RXSRB) registers (not user accessible). The TXSRx registers serially transmit data and the RXSRx registers receive data synchronously with the SPI clock signal (SPICLK). Figure 16-1 shows a block diagram of the SHARC processor SPI interface. The data is shifted into or out of the shift registers on two separate pins: the master in slave out (MISO) pin and the master out slave in (MOSI) pin. During data transfers, one SPI device acts as the SPI master by controlling the data flow. It does this by generating the SPICLK and asserting the SPI device select signal (SPI_DS_I). The SPI master receives data using the MISO pin and transmits using the MOSI pin. The other SPI device acts as the SPI slave by receiving new data from the master into its receive shift register using the MOSI pin. It transmits requested data out of the transmit shift register using the MISO pin. Each SPI port contains a dedicated transmit data buffer (TXSPI, TXSPIB) and a receive data buffer (RXSPI, RXSPIB). Transmitted data is written to TXSPIx and then automatically transferred into the transmit shift register. Once a full data word has been received in the receive shift register, the data is automatically transferred into RXSPIx, from which the data can be read. When the processor is in SPI master mode, programmable flag pins provide slave selection. These pins are connected to the SPI_DS_I of the slave devices. The SPI has a single DMA engine which can be configured to support either an SPI transmit channel or a receive channel, but not both simultaneously. Therefore, when configured as a transmit channel, the received 16-8 ADSP-214xx SHARC Processor Hardware Reference

Serial Peripheral Interface Ports

data is essentially ignored. When configured as a receive channel, what is transmitted is irrelevant. A 4-word deep FIFO is included to improve throughput on the IOD0 bus.
SPIx_MOSI_I/O SPIx_MISO_I/O SPIx_CLK_I/O SPIx_DS_I SPIx_FLG_3-0_O

SPI CONTROL/STATUS

RXSR SHIFT REGISTER 8/16/32 BITS

TXSR SHIFT REGISTER 8/16/32 BITS

RXSPI REGISTER 1 DEEP

TXSPI REGISTER 1 DEEP

DMA FIFO 4 DEEP

PERIPHERAL CORE BUS IOD0 BUS

Figure 16-1. SPI Block Diagram

SPI Transaction
An SPI transaction defined start and end depend on whether the device is configured as a master or a slave, whether CPHASE mode is selected, and whether the transfer initiation mode is (TIMOD) selected. For a master SPI with CPHASE = 0, a transfer starts when either the TXSPI register is written

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Functional Description

or the RXSPI register is read, depending on the TIMOD selection. At the start of the transfer, the enabled slave-select outputs are driven active (low). However, the SPICLK starts toggling after a delay equal to one-half (0.5) the SPICLK period. For a slave with CPHASE = 0, the transfer starts as soon as the SPI_DS_I input transitions to low. For CPHASE = 1, a transfer starts with the first active edge of SPICLK for both slave and master devices. For a master device, a transfer is considered complete after it sends and simultaneously receives the last data bit. A transfer for a slave device is complete after the last sampling edge of SPICLK.

Single Master Systems

Figure 16-2 illustrates how the SHARC processor can be used as the slave SPI device. The 16-bit host (A Blackfin ADSP-BF53x processor) is the SPI master. The processor can be booted via its SPI interface to allow application code and data to be downloaded prior to runtime. B
ADSP-BF537
SCLK SPISSEL MOSI MISO

S
ADSP-214xx
DPI (SPI_CLK_I) DPI (SPI_DS_I) DPI (SPI_MOSI_I) DPI (SPI_MISO_O) SLAVE SPI DEVICE

Figure 16-2. SHARC Processor as SPI Slave Figure 16-3 shows an example SPI interface where the SHARC processor is the SPI master. With the SPI interface, the processor can be directed to alter the conversion resources, mute the sound, modify the volume, and power down the AD1855 stereo DAC.

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S
ADSP-214xx
DPI (SPI_CLK_O) DPI (SPI_FLG0_O) DPI (SPI_MOSI_O) MASTER DEVICE

a AD1855 STEREO 96 kHz DAC

CCLK CLATCH DATA

Figure 16-3. SHARC Processor as SPI Master

Multi Master Systems

The SPI does not have an acknowledgement mechanism to confirm the receipt of data. Without a communication protocol, the SPI master has no knowledge of whether a slave even exists. Furthermore, the SPI has no flow control. Slaves can be thought of as input/output devices of the master. The SPI does not specify a particular higher-level protocol for bus mastership. In some applications, a higher-level protocol, such as a command-response protocol, may be necessary. Note that the master must initiate the frames for both its command and the slaves response. Multi master mode allows an SPI system to transfer mastership from one SPI device to another. In a multi device SPI configuration, several SPI ports are connected and any one (but only one) of them can become a master at any given time. In this configuration, every MOSI pin in the SPI system is connected. Likewise, every MISO pin in the system is on a single node, and every SPICLK pin should be connected (see Figure 16-4). SPI transmission and reception are always enabled simultaneously, unless the broadcast mode has been selected. The masters FLAGx pins connect to each of the slave SPI devices in the system via their SPI_DS_I pins. To enable the different slaves, connect the

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Operating Modes

BUS ARBITRATION LOGIC

SPIFLGxy SPI_DS_I SPI #1

SPIFLGxy SPI_DS_I SPI #2

SPIFLGxy SPI_DS_I

SPI #3

SPICLK SPI_MOSI_PBEN_O (open drain) SPI_MISO_PBEN_O (open drain)

Figure 16-4. Multi-Master System slave SPI_DS_I pins to the DPI pins of the master SHARC. Since these flags are NOT open drain, slave select pins cannot be shorted together in a multi-master environment. To control slave selects, an external glue logic is required in a multi-master environment. Another feature is implemented to troubleshoot the bus mastership protocol. If a recent SHARC bus master receives an invalidly asserted SPI_DS_I signal, it triggers an error handling scenario using the MME bit (SPIMME bit for DMA) and ISSEN bit to reconfigure the SPI to slave mode, and jump into an ISR. This ensures that any potential driver conflict is solved. For more information, see Control Registers (SPICTL, SPICTLB) on page A-219.

Operating Modes
This sections describes the different mechanisms used for master or slave select operation modes.

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Transfer Initiate Mode

When the processor is enabled as a master, the initiation of a transfer is defined by the TIMOD bits (10). Based on these two bits and the status of the interface, a new transfer is started upon either a read of the RXSPIx registers or a write to the TXSPIx registers. This is summarized in Table 16-6. Table 16-6. Transfer Initiation
TIMOD 00 Function Core Receive and Transmit Transfer Initiated Upon Initiate new single word transfer upon read of RXSPI and previous transfer completed. The SPICLK is generated after the data is read from the buffer. In this configuration, a dummy read is needed initially to receive all the data transmitted from the transmitter. Action, Interrupt The SPI interrupt is latched in every core clock cycle in which the RXSPI buffer has a word in it. Emptying the RXSPI buffer or disabling the SPI port at the same time (SPIEN = 0) stops the interrupt latch.

01

Core Transmit Initiate new single word transfer The SPI interrupt is latched in every core and Receive upon write to TXSPI and previous clock cycle in which the TXSPI buffer is transfer completed. empty. Writing to the TXSPI buffer or disabling the SPI port at the same time (SPIEN = 0) stops the interrupt latch. Transmit or Receive with DMA Initiate new multiword transfer upon write to DMA enable bit. Individual word transfers begin with either a DMA write to TXSPI or a DMA read of RXSPI depending on the direction of the transfer as specified by the SPIRCV bit. If chaining is disabled, the SPI interrupt is latched in the cycle when the DMA count decrements from 1 to 0. If chaining is enabled, interrupt function is based on the PCI bit in the CP register. If PCI = 0, the SPI interrupt is latched at the end of the DMA sequence. If PCI = 1, then the SPI interrupt is latched after each DMA in the sequence.

10

11

Reserved

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Operating Modes

SPI Modes
The SPI supports four different combinations of serial clock phases and polarity called SPI modes. The application code can select any of these combinations using the CLKPL and CPHASE bits (10 and 11). Figure 16-5 on page 16-15 shows the transfer format when CPHASE = 0 and Figure 16-6 on page 16-16 shows the transfer format when CPHASE = 1. Each diagram shows two waveforms for SPICLKone for CLKPL = 0 and the other for CLKPL = 1. The diagrams may be interpreted as master or slave timing diagrams since the SPICLK, MISO, and MOSI pins are directly connected between the master and the slave. The MISO signal is the output from the slave (slave transmission), and the MOSI signal is the output from the master (master transmission). The SPICLK signal is generated by the master, and the SPI_DS_I signal represents the slave device select input to the processor from the SPI master. The diagrams represent 8-bit transfers (WL = 0) with MSB first (MSBF = 1). Any combination of the WL and MSBF bits of the SPICTL register is allowed. For example, a 16-bit transfer with the LSB first is one possible configuration. The clock polarity and the clock phase should be identical for the master device and slave devices involved in the communication link. The transfer format from the master may be changed between transfers to adjust to various requirements of a slave device. 0, the slave-select line, , be When) between= each word in the transfer. Even inmustslaveinactive ( SPI mode
CPHASE SPI_DS_I HIGH

when CPHASE = 0, the master should de assert the SPI_DS_I line between each transfer. When CPHASE = 1, SPI_DS_I may either remain active (LOW) between successive transfers or be inactive (HIGH).

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Serial Peripheral Interface Ports

Figure 16-5 shows the SPI transfer protocol for CPHASE = 0. Note that SPICLK starts toggling in the middle of the data transfer where the bit settings are WL = 0, and MSBF = 1.
1 2 3 4 5 6 7 8

CLOCK CYCLE#

SPI_CLK_O CLKPL=0 (SPI MODE 0) SPI_CLK_O CLKPL=1 (SPI MODE 2)

SPI_MOSI_O FROM MASTER

MSB

LSB

SPI_MISO_I FROM SLAVE SPI_FLG_I FROM MASTER

MSB

LSB

* = UNDEFINED

Figure 16-5. SPI Transfer Protocol for CPHASE = 0 Figure 16-6 shows the SPI transfer protocol for CPHASE = 1. Note that SPICLK starts toggling at the beginning of the data transfer where the bit settings are WL = 0, and MSBF = 1.

Slave Select Outputs

If the SPI is enabled and configured as a master, any of the 14 DPI I/O pins may be used as slave-select outputs. For each DSxEN bit which is set in the SPIFLG register, the corresponding SPI_FLGx_O is configured as a slave-select output. For example, if DS1EN = 1 is set, SPI_FLG1_O is driven as a slave-select. At the chip-level, SPI_FLG1_O can be connected to any of the DPI pins

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Operating Modes

CLOCK CYCLE#

SPI_CLK_O CLKPL=0 (SPI MODE 1) SPI_CLK_O CLKPL=1 (SPI MODE 3)

SPI_MOSI_O FROM MASTER

MSB

LSB

SPI_MISO_O FROM SLAVE SPI_DS_I TO SLAVE

MSB

LSB

* = UNDEFINED

Figure 16-6. SPI Transfer Protocol for CPHASE = 1 through SRU programming. For those DSxEN bits which are not set, the corresponding SPIx_FLGx_PBEN_O is driven low. The behavior of the SPI_FLGx output depends on the value of the CPHASE configuration bit. If CPHASE = 1, all selected outputs may either remain asserted (active-low) between transfers or be deasserted between transfers. This is controlled in software using the SPIFLGx bits (SPIFLG register). For example, to configure SPI_FLG1_O as a slave-select, set DS1EN = 1 and SPIFLG1 = 0. As soon as this SPIFLG register write takes effect, the SPI_FLG1_O (slave-select output pin) becomes active (Low). If needed, SPI_FLGx_O can be cycled high and low between transfers by setting the SPIFLG[x] bit to 1 and back to 0. Otherwise, SPI_FLGx_O remains active between transfers. If CPHASE = 0 or CHPASE = 1 and AUTOSDS = 1, all selected outputs are asserted only for the duration of the transfer. This is controlled by the internal SPI hardware. In this case, the SPIFLGx bits are ignored. For

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Serial Peripheral Interface Ports

example, to configure SPI_FLG1_O as a slave-select, it is only necessary to set DS1EN=1. Note that the SPI_FLGx_O signals behave as slave-select outputs only if the SPI module is enabled as a master. Otherwise, none of the bits in the SPIFLG register have any effect.

Variable Frame Delay for Slave

When the processor is configured as an SPI slave, the SPI master must drive an SPICLK signal that conforms with Figure 16-7. For exact timing parameters, please refer to the appropriate product data sheet. As shown in Figure 16-7, the SPI_DS_I lead time (T1), the SPI_DS_I lag time (T2), and the sequential transfer delay time (T3) must always be greater than or equal to one-half the SPICLK period. The minimum time between successive word transfers (T4) is two SPICLK periods. This time period is measured from the last active edge of SPICLK of one word to the first active edge of SPICLK of the next word. This calculation is independent from the configuration of the SPI (CPHASE, SPIMS, and so on). This is shown as: T4 = 1.5 SPI clock period + T3 and T3 = 0.5 SPICLK period for sequential transfer delay (STDC) = 0. T3 = STDC SPICLK period for STDC > 0. processors, a variable Unlike previous SHARCtiming flexibility. frame delay is included to increase SPI For a master device with CPHASE = 0 or CPHASE = 1 (with AUTOSDS set to 1 in the SPCTL register), this means that the slave-select output is inactive (high) for at least one-half the SPICLK period. In this case, T1 and T2 are each always be equal to one-half the SPICLK period.

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Data Transfers

T1

T2

SPI_CLK_I CPHASE=0

SPI_DS_I TO SLAVE T3 T4

Figure 16-7. SPICLK Timing When word to word delay is enabled (WTWDEN = 1) in the SPICTL register, then T3 may vary with respect to the value programmed using the STDC bits in the SPIBAUD register. So the word to word delay T4 is: T4 = 1.5 SPI clock period + T3 and T3 = 1.5 SPI clock period for STDC = 0, BAUDR = 1, RX master T3 = 0.5 SPI clock period for STDC = 0, in all other cases. T3 = STDC SPI clock period for STDC > 0.

Data Transfers
The SPI is capable of transferring data via the core and DMA. The following sections describe these transfer types.

Serial Shift Register

The SPI allows three different word lengths. The transmit and receive shift registers use these for different packing methods as described below. Output Shift Register The transmit shift register receives 32-bit wide data and serially shifts it out externally off-chip.

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32-bit word. The Shift register sends the entire 32-bit data. 16-bit word. When transmitting, the shift register sends out only the lower 16 bits of the word written to the SPI buffer. 8-bit word. When transmitting, the shift register sends out only the lower 8 bits of the word written to the SPI buffer. Input Shift Register The receive shift register receives its data serially from off chip. Internally the receive shift register is 32 bits wide and data received can be transferred to the buffer. 32-bit word. The shift register receives the entire 32-bit word. 16-bit word. When receiving, the shift register packs the 16-bit word to the lower 32 bits of the RXSPI buffer while the upper bits in the register are zeros. 8-bit word. When receiving, the SPI port packs the 8-bit word to the lower 32 bits of the RXSPI buffer while the upper bits in the registers are zeros.

Buffers
The SPI contains a transmit and receive buffer which operate as described below. Transmit Buffer The transmit buffer is accessible by both the core and DMA. Data is loaded into this register before being transmitted. Just prior to the beginning of a data transfer, the data in TXSPI is loaded into the shift register. A core read of TXSPI can be performed at any time and does not interfere with, or initiate, SPI transfers.

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Data Transfers

Receive Buffer The receive buffer is accessible by both the core and DMA. At the end of a data transfer, the data in the shift register is loaded into RXSPI. During a DMA receive operation, the data in the shift register is automatically read by the DMA. When RXSPI is read via the core, the RXS bit is cleared and an SPI transfer may be initiated (only if TIMOD = 00).
Buffer Packing

The SPI unpacks data when it transmits and packs data when it receives. In order to communicate with 8-bit SPI devices and store 8-bit words in internal memory, a packed transfer feature is built into the SPI port. PACKEN = 0: No buffer packing PACKEN = 1: 8 to 16-bit buffer packing 1 = 00 (8-bit When in This bit may be theonly when unpacks data.transfer).packing is bit When transmit mode,
WL PACKEN

enabled, two 8-bit words are packed into one 32-bit word. When the SPI port is transmitting, two 8-bit words are unpacked from one 32-bit word. When receiving, words are packed into one 32-bit word from two 8-bit words. The value 0xXXLMXXJK (where XX is any random value and JK and LM are data words to be transmitted out of the SPI port) is written to the TXSPI register. The processor transmits 0xJK first and then transmits 0xLM. The receiver packs the two words received, 0xJK and then 0xLM, into a 32-bit word. They appear in the RXSPI register as: 0x00LM00JK => if SGN is configured to 0 or L, J < 7 0xFFLMFFJK => if SGN is configured to 1 and L, J > 7

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Buffer Errors The following errors are reported in the SPISTAT register.
Transmission Error

This error bit is set when all the conditions of transmission are met and there is no new data in TXSPI (TXSPI is empty). In this case, what is transmitted depends on the state of the SENDZ bit in the SPICTL register. The TUNF bit is cleared by a write-1 (W1C) software operation.
Reception Error

The ROVF flag is set when a new transfer has completed before the previous data could be read from the RXSPI register. This bit indicates that a new word was received while the receive buffer was full. The ROVF bit is cleared by a software write-1 (W1C) operation. The state of the GM bit in the SPICTL register determines whether or not the RXSPI register is updated with the newly received data.
Transmit Collision Error

The TXCOL flag is set when a write to the TXSPI register coincides with the load of the shift register by a write to TXSPI through the core or DMA bus. This bit indicates that corrupt data may have been loaded into the shift register and transmitted. In this case, the data in TXSPI may not match with what was transmitted. It is important to note that this bit is never set when the SPI is configured as a slave with CPHASE = 0; the collision error may occur, but it wont be detected. In any case, this error can easily be avoided by proper software control as described below. To avoid the TXCOL condition, programs should write to TXSPI well before the load to the shift register takes place. This can be done by writing to TXSPI whenever TXS is cleared and refrain from writing to TXSPI when TXS is set. For slave mode this means that data should be in TXSPI before the first SPI clock edge (or the negative edge of device select) occurs.

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Data Transfers

However, a potential case of TXCOL arises when there is a TUNF condition while trying to write to TXSPI. In this case TXS is not set and attempts to send new data and it isnt clear if this write to TXSPI takes place when the load to the shift register is occurring (in other words a TXCOL condition). To be absolutely safe, when a TUNF = 1, write to the TXSPI register as soon as SPIF goes from 1 to 0. This ensures that TXSPI is written into well before the next load to the shift register takes place. The TXCOL bit is cleared by a software write-1 (W1C) operation.
Flush Buffer

The SPI RX/TX buffers are flushed by disabling the SPI port or by setting the TXFLSH/RXFLSH bits. The SPI DMA buffer is flushed only by setting the FIFOFLSH bit. of the three flush bits , None clearing. They have toinbeSPI ( cleared by, and software. ) is self explicitly the
TXFLSH RXFLSH FIFOFLSH

Core Buffer Status For core accesses to the SPI, master and slave modes operate differently as described below. 1. If core access to a SPI slave is unable to keep up with the transmit/receive stream during a transfer operation (because of an interrupt or any other reason) the SPI operates according to the states of the SENDZ and GM bits in the SPICTLx register. If SENDZ = 1 and the transmit buffer is empty, the device repeatedly transmits zeros on the MOSI pin. One word is transmitted for each new transfer initiate command. If SENDZ = 0 and the transmit buffer is empty, the device repeatedly transmits the last word transmitted before the transmit buffer became empty.

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If GM = 1 and the receive buffer is full, the device continues to receive new data from the MISO pin, overwriting the older data in the RXSPI buffer. If GM = 0 and the receive buffer is full, the incoming data is discarded, and the RXSPI register is not updated. 2. If core access to a SPI master is unable to keep up with the transmit/receive stream during a transfer operation (because of an interrupt or another reason) the SPI stalls the SPICLK until new data is read/written into the TXSPI/RXSPI buffers. In this scenario the TUNF/ROVF condition bits are set indicating an exception in the data stream. DMA Buffer Status If the DMA engine is unable to keep up with the transmit/receive stream during a transfer operation because of latency caused by using multiple DMA channels, the SPI operates according to the states of the SENDZ and GM bits in the SPICTLx register. If SENDZ = 1 and the transmit buffer is empty, the device repeatedly transmits zeros on the MOSI pin. One word is transmitted for each new transfer initiate command. If SENDZ = 0 and the transmit buffer is empty, the device repeatedly transmits the last word transmitted before the transmit buffer became empty. If GM = 1 and the receive buffer is full, the device continues to receive new data from the MISO pin, overwriting the older data in the RXSPI buffer. If GM = 0 and the receive buffer is full, the incoming data is discarded, and the RXSPI register is not updated.

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Data Transfers

Core Transfers
The RXS bit defines when the receive buffer can be read. The TXS bit defines when the transmit buffer can be filled. The end of a single word transfer occurs when the RXS bit is set. This indicates that a new word has been received and latched into the receive buffer, RXSPI. The RXS bit is set shortly after the last sampling edge of SPICLK. There is a 4 PCLK cycle latency for a master/slave device, depending on synchronization. This is independent of the CPHASE, TIMOD bit settings, and the baud rate. Backward Compatibility To maintain software compatibility with other SPI devices (68HC11), the SPI transfer finished bit (SPIF) is also available for polling. This bit may have slightly different behavior from that of other commercially available devices. For a slave device, SPIF is set at the same time as RXS. For a master device, SPIF is set one-half (0.5) of the SPICLK period after the last SPICLK edge, regardless of CPHASE or CLKPL. The baud rate determines when the SPIF bit is set. In general, SPIF is set after RXS, but at the lowest baud rate settings (SPIBAUD < 4). The SPIF bit is set before the RXS bit, and consequently before new data has been latched into the RXSPI buffer. Therefore, for SPIBAUD = 2 or SPIBAUD = 3, the processor must wait for the RXS bit to be set (after SPIF is set) before reading the RXSPI buffer. For larger SPIBAUD settings (SPIBAUD > 4), RXS is set before SPIF.

DMA Transfers
The SPI ports support both master and slave mode DMA. DMA is enabled for TIMOD bit = 10. before Enable the aSPI porttransfer enabling DMA.DMA engine is enabled. For master mode, DMA starts after the For slave mode the slave select pin (SPI_DS_I) needs to be asserted to start slave DMA operation.

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When enabled as a master, the DMA engine transmits or receives data as follows: If the SPI system is configured for transmitting, the DMA engine reads data from memory into the DMA FIFO. Data from the DMA FIFO is loaded into the TXSPIx buffer and then into the transmit shift register. This initiates the transfer on the SPI port. If configured to receive, data from the RXSPIx buffer is automatically loaded into the DMA FIFO as long as FIFO is not full. (It is recommended to flush the DMA FIFO before initiating the transfer, if there is no valid data in the FIFO). Once the data from RXSPIx gets written into the FIFO, the DMA engine reads data from the DMA FIFO and writes to memory. Then the SPI initiates the receive transfer. The SPI generates the programmed signal pulses on SPICLK and the data is shifted out of MOSI and in from MISO simultaneously. The SPI continues sending or receiving words until the DMA word count register transitions from 1 to 0. When the SPI is configured as master, the SPI continues to generate SPICLK until the DMA FIFO is full, even if the DMA word count transitions to zero. write to buffer during an active SPI Do notoperation the DMA data will be overwritten.transmit DMA because Similarly,
TXSPIx

do not read from the RXSPIx buffer during active SPI DMA receive operations. DMA interrupts are generated based on DMA events and are configured in the SPIDMACx registers. In order for a transmit DMA operation to begin, the transmit buffer (TXSPIx) must initially be empty (TXS = 0). While this is normally the case, this means that the TXSPIx buffer should not be used for any purpose other than SPI transfers. Writing to the TXSPIx buffer via the software sets the TXS bit.

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Data Transfers

master DMA, For receiveDMA FIFO arethe (even stops only when theisRXSPI buffer and full if the DMA count already
SPICLK

zero). Therefore, SPICLK runs for an additional five word transfers filling junk data in the RXSPIx buffer and DMA FIFO. The FIFOs must be flushed before a new DMA is initiated. In some slave devices such as SPI flash, the starting address is usually sent along with the read command in the beginning. The read address later increments automatically after every read. These additional clock cycles might fetch additional words in the FIFO from the SPI flash device and thus might result in unintended increment of the read address of the flash memory. If another read DMA has to be initiated to read the following data from the flash, flushing the DMA FIFO may not be practical as it might result in data loss. In such cases, either of the two following methods can be used to avoid the data loss: 1. Flush both the DMA FIFO and the SPI receive buffer, send a new read command with the appropriate start address to the slave device again, and then re-initialize the read DMA. The advantage of this method is that the successive DMA transfers can be made completely independent and thus even disabling the SPI after one DMA is done and re-enabling it again before initializing the next DMA does not result in any data loss. 2. After completion of a DMA transfer, do not flush the FIFO, and do not modify the contents of the SPICTL and SPIDMAC registers. Change the DMA index and modifier registers (if required), and finally re-initialize the DMA count register to initiate a new DMA. This method avoids software overhead required to flush the FIFO and send a new read command for each DMA. It should be noted that the SPI and the DMA engine cant be disabled when using this method. Also, the DMA index and/or modifier register values should be changed only after the ongoing DMA is finished and before loading the DMA count register for the next DMA transfer.

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DMA Chaining The serial peripheral interfaces support both single and chained DMA. However, unlike the serial ports, programs cannot insert a TCB in an active chain. For more information, see SPI TCB on page 3-15. Configuring and starting chained DMA transfers over the SPI port is the same as that of the serial ports, with one exception. Contrary to SPORT DMA chaining, (where the first DMA in the chain is configured by the first TCB), for SPI DMA chaining, the first DMA is not initialized by a TCB. Instead, the first DMA in the chain must be loaded into the SPI parameter registers (IISPI, IMSPI, CSPI, IISPIB, IMSPIB, CSPIB), and the chain pointer registers (CPSPI, CPSPIB) point to a TCB that describes the second DMA in the sequence. an address to the , Writing DMA sequence unless theregisters does ,not begin a chained , ,
CPSPIx IMSPIB, IISPI IMSPI CSPI IISPIB,

and CSPIB registers are initialized, SPI DMA is enabled, the SPI port is enabled, and SPI DMA chaining is enabled. DMA Transfer Count When the SPI is configured for receive/transmit DMA, the number of words configured in the DMA count register should match the actual data transmitted. When the SPI DMA is used, the internal DMA request is generated for a DMA count of four. In case the count is less than four, one DMA request is generated for all the bytes. For example, when a DMA count of 16 is programmed, four DMA requests are generated (that is, four groups of four). For a DMA count of 18, five DMA requests are generated (four groups of four and one group of two). In case the SPI DMA is programmed with a value more than the actual data transmitted, some bytes may not be received by the SPI DMA due to the condition for generating the DMA request.

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Interrupts

Full Duplex Operation The SPI interface allows full-duplex operation running the DMA channel to the transmit/receive path and core access to the alternate transmit/receive path. For full-duplex operation, set TIMOD = 10 which generates the interrupts for DMA only. Reads from the RXSPIx buffer are allowed at any time during transmit DMA. Note the TXS bit is cleared when the TXSPIx buffer is read but the DMA FIFO is not available in the receive path. The receive interface cannot generate an interrupt, but the RXS status bits can be polled. Writes to the TXSPIx buffer during an active SPI receive DMA operation are permitted. Note the RXS bit is cleared when the RXSPIx buffer is read but the DMA FIFO is not available in the transmit path. The transmit interface cannot generate an interrupt, but the TXS status bits can be polled.

Interrupts
Table 16-7 provides an overview of SPI interrupts. Table 16-7. Overview of SPI Interrupts
Default Programmable Interrupt SPIHI = P1I SPILI = P18I Sources Masking Service

DMA complete Core buffer service Internal transfer completion Access completion DMA buffer underflow DMA Buffer overflow Multimaster error Transmit collision error

TIMOD bit (SPICTL) INTEN bit (SPIDMAC)

RTI instruction

INTERR bit (SPIDMAC)

RW1C to SPISTAT + RTI instruction

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Sources
The SPI module drives one interrupt signal, SPIHI/SPILI. The internal status for core/DMA and protocol are logical ORed into the interrupt signal. The primary SPI uses the SPIHI interrupt and the secondary SPI uses the SPILI interrupt. Whenever an SPI interrupt occurs (regardless of the cause), the SPILI or SPIHI interrupts are latched. The SPI ports can generate interrupts as described in the following sections. Core Buffer Service Request When DMA is disabled the processor core may read from the RXSPI buffer or write to the TXSPI buffer. An interrupt is generated when the receive buffer is not empty or the transmit buffer is not full. If configured to generate an interrupt when RXSPI is full (TIMOD = 00), the interrupt becomes active 1 PCLK cycle after the RXS bit is set. Data Buffer Packing When SPI port data packing is enabled (PACKEN = 1 in the SPICTL registers), the transmit and receive interrupts are generated for 32-bit packed words, not for each 16-bit word. DMA Complete For receive or transmit DMA after the DMA counter is zero. Internal Transfer Complete Depending upon the state of INTETC bit the interrupt can be generated when the internal count becomes zero or the external transfer is complete. At the completion of a single DMA transfer when DMA count = 0 and INTETC bit is zero.

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Interrupts

Access Complete The DMA interrupt is generated when DMA count reaches zero (INTETC = 0) or the DMA interrupt is generated when last bit of last word is shifted out or when the last data is transferred externally (INTETC = 1). This setting also generates an interrupt at the completion of a number of DMA sequences when DMA chaining is enabled. Chained DMA For chained DMA, if the PCI bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the PCI bit is set (= 1), then a DMA interrupt is generated for each TCB.
DMA Buffer Over/Underflow

For DMA transfers (TIMOD = 10) interrupts are latched in case for receive buffer overflow (SPIOVF bit) or transmit buffer underflow (SPIUNV bit).
Multimaster Error

The SPIMME bit (1) is set when the SPI_DS_I input pin of a device that is enabled as a master is driven low by some other device in the system. This occurs in multimaster systems when another device is also trying to be the master.

Masking
The SPIHI and SPILI signals are routed by default to programmable interrupt. To service the primary SPI port, unmask (set = 1) the P1I bit in the IMASK register. To service the secondary SPIB port, unmask (set = 1) the P18IMSK bit in the LIRPTL register. For example:
bit set IMASK P1I; bit set LIRPTL P18IMSK; /* unmasks P1I interrupt */ /* unmasks P18I interrupt */

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The TIMOD bit in the SPICTL register determines whether the interrupt is based on DMA or on core buffer service request (TXSPI or RXSPI buffer). For DMA transfer status based interrupts, set the INTEN bit in the SPIDMAC register. Note that the SPIDMAC register must be initialized properly to enable DMA interrupts. In order to trigger data stream errors set the INTERR bit in the SPIDMAC register. This triggers an error interrupt condition when a receive buffer overflow (SPIRCV bit = 1) or a transmit buffer underflow (SPIRCV bit = 0) occur. To detect errors in a multi-master environment, set the ISSEN bit in the SPICTL register to trigger an interrupt for a conflict situation.

Service
As soon as DMA buffer under/overflow error is detected by reading the SPISTAT register, the ISR should perform a RW1C operation on the bit that caused the exception in the SPISTAT register. As soon as master error is detected, the following actions are taken: 1. The SPIMS control bit in SPICTL is cleared, configuring the SPI interface as a slave. 2. The SPIEN control bit in SPICTL is cleared, disabling the SPI system. 3. The MME status bit in SPISTAT is set. 4. An SPI interrupt is generated. These four conditions persist until the MME bit is cleared by a read-write 1-to-clear (RW1C type) software operation. Until the MME bit is cleared, the SPI cannot be re-enabled, even as a slave. Hardware prevents the program from setting either SPIEN or SPIMS while MME is set.

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Effect Latency

When MME is cleared, the interrupt is deactivated. Before attempting to re-enable the SPI as a master, the state of the SPI_DS_I input pin should be checked to ensure that it is high; otherwise, once SPIEN and SPIMS are set, another mode-fault error condition will immediately occur. The state of the input pin is reflected in the input slave select status bit (bit 7) in the SPIFLG register. As a result of SPIEN and SPIMS being cleared, the SPI data and clock pin drivers (MOSI, MISO, and SPICLK) are disabled. However, the slave-select output pins revert to control by the processor flag I/O module registers. This may cause contention on the slave-select lines if these lines are still being driven by the processor.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

SPI Effect Latency

After the SPI registers are configured the effect latency is 2 PCLK cycles to enable and 2 PCLK cycles to disable.

Programming Model
The section describes which sequences of software steps are required to get the peripheral working successfully.

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SPI Routing
For proper master operation configure the MOSI, MISO, SPICLK and SPI_FLGx_O master output select. For slave operation route the MOSI, MISO, SPICLK signals including the SPI_DS_I as slave select input.

Master Mode Transfers

For core or DMA transfers, when the SPI is configured as a master, the ports should be configured and transfers started using the following steps: 1. Route all required signals (MOSI, MISO, SPICLK) for master mode including the SPI_FLGx_O as slave select outputs. 2. Before enabling the SPI port, programs should specify which of the slave-select signals (DPI pins) to use, setting one or more of the required SPI flag select bits (DSxEN) in the SPIFLGx register. For DMA operation set TIMOD = 10. 3. Set AUTOSDS bit to 1, to ensure the slave-selects are automatically controlled by the SPI port. (When AUTOSDS = 0, only the CPHASE = 0 setting has automated control as with previous SHARC processors) 4. Write to the SPICTLx register and set the SPIMS bit to enable the device as a master. Configure the SPIBAUDx registers, and configuring the appropriate word length, transfer format, baud rate, and other necessary information. The next steps are dependant on whether the access is a core or a DMA access. Core Master Transfers When a device is to be used as a master, configure the ports using the following procedure.

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Programming Model

1. Initiate the SPI transfer by writing or reading to/from SPI buffers. The trigger mechanism for starting the transfer is dependant upon the TIMOD bits in the SPICTLx registers. See Table 16-6 on page 16-13 for more details. 2. The SPI generates the programmed clock pulses on SPICLK. The data is shifted out of MOSI and shifted in from MISO simultaneously. Before starting to shift, the transmit shift register is loaded with the contents of the TXSPIx registers. At the end of the transfer, the contents of the receive shift register are loaded into the RXSPI buffer. 3. With each new buffer access, the SPI continues to send and receive words, according to the SPI transfer mode (TIMOD bit in SPICTLx registers). See Table 16-6 on page 16-13 for more details. 4. If there are no further SPI buffer accesses the SPICLK signal is stalled until new core requests are received. DMA Master Transfers To configure the SPI port for master mode DMA transfers: 1. Define DMA receive (or transmit) transfer parameters by writing to the IISPIx, IMSPIx, and CSPIx registers. 2. Write to the SPIDMACx register to enable the SPI DMA engine (SPIDEN, bit 0). And configure the following: A receive access (SPIRCV = 1) or A transmit access (SPIRCV = 0)

Slave Mode Transfers

When the SPI is configured as a master, regardless of core or DMA the SPI ports should be configured and transfers started using the following steps.

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1. Route all required signals (MOSI, MISO, SPICLK) for slave mode including the SPI_DS_I as slave select input. 2. Write to the SPICTLx and keep the (SPIMS) cleared, enabling the device as a slave and configuring the SPI system by specifying the appropriate word length, transfer format and other necessary information. For DMA operation set TIMOD = 10. The next steps are dependant on whether the access is a core or a DMA access. Core Slave Transfers The following steps illustrate SPI operation in slave mode. 1. Write the data to be transmitted into the TXSPIx buffer to prepare for the data transfer. 2. When a device is enabled as a slave, the start of a transfer is triggered by a transition of the SPI_DS_I select signal to the active state (low) or by the first active edge of the clock (SPICLK), depending on the state of CPHASE. 3. The reception or transmission continues until SPI_DS_I is released or until the slave has received the proper number of clock cycles. 4. The slave device continues to receive or transmit with each new falling-edge transition on SPI_DS_I or active SPICLK clock edge. DMA Slave Transfers To configure the SPI port for slave mode DMA transfers: 1. Define DMA receive (or transmit) transfer parameters by writing to the IISPIx, IMSPIx, and CSPIx registers. 2. Write to the SPIDMACx register to enable the SPI DMA engine (SPIDEN, bit 0). And configure the following:

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Programming Model

A receive access (SPIRCV = 1) or A transmit access (SPIRCV = 0)

Chained DMA Transfers

The sequence for setting up and starting a chained DMA is outlined in the following steps. 1. Clear the chain pointer register. 2. Configure the TCB associated with each DMA in the chain except for the first DMA in the chain. 3. Write the first three parameters for the initial DMA to the IISPI, IMSPI, CSPI, IISPIB, IMSPIB, and CSPIB registers directly. 4. Configure the DMA settings for the entire sequence, enabling DMA and DMA chaining in the SPIDMAC register. 5. Begin the DMA by writing the address of a TCB (describing the second DMA in the chain) to the CPSPI, CPSPIB registers.

Stopping SPI Transfers

External transfer completion is indicated by the SPI status bit SPIFE. For core-driven transfers it shows that the read transfer ( TIMOD = 00) or write transfer (TIMOD = 01) has been completed on the external interface. For receive DMA the status bit is asserted when the DMA count becomes zero. For transmit DMA the SPIFE goes high when: the DMA count becomes zero and the DMA FIFO becomes empty and the TXSPI buffer becomes empty (TXS bit high) and transfer is complete (SPIF bit goes high)

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Note that the SPIFE bit can go high between two DMA blocks of a chained DMA.

Changing SPI Timing Configuration

Programs should take the following precautions when changing SPI configurations. The SPI configuration must not be changed during a data transfer. Change the clock polarity only when no slaves are selected. Change the SPI configuration when SPIEN = 0. For example, if operating as a master in a multislave system, and there are slaves that require different data or clock formats, then the master SPI should be disabled, reconfigured, and then re-enabled. However, when a SPI communication link consists of: 1. A single master and a single slave, 2.
CPHASE

= 1 and AUTOSDS = 0 for master, CPHASE = 1 for slave

3. The slaves slave select input is tied low Then the program can change the SPI configuration. In this case, the slave is always selected. Data corruption can be avoided by enabling the slave only after configuring both the master and slave devices.

Switching From Transmit DMA to a New DMA

The following sequences detail the steps for switching from transmit to transmit/receive DMA. In the first sequence the SPI is disabled then re enabled. In the second the SPI buffers and registers are cleared but the SPI itself is not disabled.

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Programming Model

Disabling SPI: 1. Poll the SPIFE bit in the SPISTAT register. If this bit is high the SPI can be disabled. The external transfer done interrupt (DMA done interrupt with INTETC bit set) can as well be used if polling SPIFE has to be avoided. 2. Clear the SPICTLx register to disable the SPI. Disabling the SPI also clears the RXSPIx/TXSPIx buffer and the buffer status. 3. Disable DMA by clearing the SPIDMACx register (write 0x00000000 to it). 4. Clear all errors by writing to the RW1C-type bits in the SPISTATx registers. This ensures that no interrupts occur due to errors from a previous DMA operation. 5. Reconfigure the SPICTLx register and enable the SPI ports. 6. Configure the new DMA by writing to the DMA parameter registers and the SPIDMACx registers and enable the DMA using the SPIDEN bit (bit 0). Not disabling SPI: 1. Poll the SPIFE bit in the SPISTAT register. If this bit is high the SPI buffer can be cleared. The external transfer done interrupt (DMA done interrupt with INTETC bit set) can be used to avoid polling the SPIFE bit. 2. Clear the RXSPIx/TXSPIx buffers and the buffer status without disabling the SPI. This can be done by ORing 0xC0000 with the present value in the SPICTLx register. For example, programs can use the RXFLSH and TXFLSH bits to clear RXSPIx/TXSPIx and the buffer status. 3. Clear the SPIDMAC register by writing 0x00000000 to it.

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4. Clear all errors by writing to the RW1C-type bits in the SPISTAT register. This ensures that no interrupts occur due to errors from a previous DMA operation. 5. Reconfigure the SPICTL register to remove the clear condition on the TXSPI/RXSPI registers. 6. Configure the new DMA by writing to the DMA parameter registers and the SPIDMACx registers and enable the DMA using the SPIDEN bit (bit 0).

Switching From Receive to a New DMA

Use the following sequence to switch from receive to transmit DMA. Note that TXSPIx and RXSPIx are registers but they may not contain any bits, only address information. In the first sequence the SPI is disabled then re enabled. In the second the SPI buffers and registers are cleared but the SPI itself is not disabled. Disabling SPI: 1. Poll the SPIFE bit in the SPISTAT register. If this bit =1 the SPI can be disabled. 2. Clear the SPICTLx registers to disable the SPI. Disabling the SPI also clears the RXSPIx/TXSPIx register contents and the buffer status. 3. Disable DMA and clear the DMA FIFO by setting the FIFOFLSH bit is the SPIDMACx register (write 0x00000080 to it). This ensures that any data from a previous DMA operation is cleared as the SPICLK signal runs for five more word transfers even after the DMA count falls to zero in the receive DMA. 4. Clear all errors by writing to the SPISTATx registers. This ensures that no interrupts occur due to errors from a previous DMA operation.

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Programming Model

5. Reconfigure the SPICTLx registers and enable the SPI. 6. Configure the new DMA by writing to the DMA parameter registers and the SPIDMACx registers and enable the DMA using the SPIDEN bit (bit 0). Since the flush bits (TXFLSH, RXFLSH, and FIFOFLSH) are not self clearing in the SPI, ensure that the FIFOFLSH bit in the SPIDMACx (which was set in step 3) is cleared in this step. No disabling SPI: 1. Poll the SPIFE bit in the SPISTAT register. If this bit =1 the SPI can be disabled. 2. Clear the RXSPIx/TXSPIx registers and the buffer status without disabling the SPI by ORing 0xC0000 with the present value in the SPICTLx registers. Use the RXFLSH (bit 19) and TXFLSH (bit 18) bits in the SPICTLx registers to clear the RXSPIx/TXSPIx registers and the buffer status. 3. Disable the DMA and clear the DMA FIFO using the FIFOFLSH bit in the SPIDMACx register (write 0x00000080 to it). This ensures that any data from a previous DMA operation is cleared because SPICLK runs for five more word transfers even after the DMA count is zero in receive DMA. 4. Clear all errors by writing to the RW1C-type bits in the SPISTATx registers. This ensures that no interrupts occur due to errors from a previous DMA operation. 5. Reconfigure the SPICTLx registers to remove the clear condition on the TXSPIx/RXSPIx registers. 6. Configure the new DMA by writing to the DMA parameter registers and the SPIDMACx register and enable the DMA using the SPIDEN bit (bit 0). Since the flush bits (TXFLSH, RXFLSH, and FIFOFLSH) are not self clearing in the SPI, ensure that the FIFOFLSH bit in the SPIDMACx (which was set in step 3) is cleared in this step.

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Serial Peripheral Interface Ports

Switching from Receive DMA to Receive DMA Without Disabling the SPI and DMA
For receive master DMA, the SPICLK stops only when the RXSPI buffer and DMA FIFO are full (even if the DMA count is already zero). Therefore, the SPICLK runs for an additional five word transfers, filling extra data in the RXSPIx buffer and DMA FIFO. In some SPI slave devices such as a SPI flash, the starting read address is usually sent along with the read command in the beginning. The read address later increments automatically after every read. These additional clock cycles might fetch additional words in the FIFO from the SPI flash device and thus might result in an unintended increment of the read address. If another read DMA has to be initiated to read the following data from the flash, the above programming model (disabling the DMA and or SPI) may not be practical as it might result in data loss. For such a case, the following programming model can be used. 1. Poll the SPIFE bit of the SPISTAT register. If this bit =1, this indicates that the previous DMA transfer is complete and the additional words (to keep the DMA FIFO and the RXSPI register full) are also received. 2. Re initialize the DMA index and modifier registers (if required). 3. Re initialize the DMA count register to the required non-zero value to initiate the new receive DMA.

DMA Error Interrupts

The SPIUNF and SPIOVF bits of the SPIDMACx registers indicate transmission errors during a DMA operation in slave mode. When one of the bits is set, an SPI interrupt occurs. The following sequence details the steps to respond to this interrupt.

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Programming Model

With SPI disabled: 1. Disable the SPI port by writing 0x00 to the SPICTLx registers. 2. Disable DMA and clear the DMA FIFO by FIFOFLSH bit in the SPIDMACx register. This ensures that any data from a previous DMA operation is cleared before configuring a new DMA operation. 3. Clear all errors by writing to the RW1C-type bits in the SPISTATx registers. This ensures that the error bits SPIOVF and SPIUNF (in the SPIDMACx registers) are cleared when a new DMA is configured. 4. Reconfigure the SPICTLx registers and enable the SPI using the SPIEN bit. 5. Configure DMA by writing to the DMA parameter registers and the SPIDMACx registers. With SPI enabled: 1. Disable DMA and clear the DMA FIFO by FIFOFLSH bit in the SPIDMACx register. This ensures that any data from a previous DMA operation is cleared before configuring a new DMA operation. 2. Clear the RXSPIx/TXSPIx registers and the buffer status without disabling SPI. This can be done by ORing 0xC0000 with the present value in the SPICTLx registers. Use the RXFLSH and TXFLSH bits to clear the RXSPIx/TXSPIx registers and the buffer status. 3. Clear all errors by writing to the RW1C-type bits in the SPISTAT register. This ensures that error bits SPIOVF and SPIUNF in the SPIDMACx registers are cleared when a new DMA is configured. 4. Reconfigure the SPICTL register to remove the clear condition on the RXSPI/TXSPI register bits. 5. Configure DMA by writing to the DMA parameter registers and the SPIDMACx register.

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Multi-Master Transfers The following steps show how to implement a system with two SPI devices. Since the slaves cannot initiate transfers over the bus, the master must send frames over the MOSI pin. This ensures that slaves can respond to the bus by sending messages over the MISO pin to the bus master. 1. Slave writes message to its MISO pin. 2. Slave starts polling its SPI_DS_I pin which is currently low. 3. Message is latched by current master and decoded. 4. Master deasserts the slave select signal and clears the SPIMS bit to become a slave. 5. If bus requester detects the SPI_DS_I pin high, it sets the SPIMS bit to get bus mastership. 6. The master selects a slave by driving its slave select flag pin.

Debug Features
The following sections provide information on features that help in debugging SPI software.

Shadow Receive Buffers

A pair of read-only (RO) shadow registers for the receive data buffers, RXSPI and RXSPIB are available for use in debugging software. These registers, RXSPI_SHADOW and RXSPIB_SHADOW, are located at different addresses from RXSPI, but their contents are identical to that of RXSPI. When RXSPI is read from core, the RXS bit is cleared (read only-to-clear) and an SPI transfer may be initiated (if TIMOD = 00). No such hardware action occurs when the shadow register is read. RXSPI_SHADOW is only accessible by the core.

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Debug Features

data one When transferringmasterfromDMASPI configured as slave to another SPI configured as in mode, the following steps should be followed to avoid data loss. 1. Enable slave SPI DMA. 2. Wait for the TX buffer of the slave to be full by polling the TXS bit (bit 3) of the SPIxSTAT register. 3. Enable the master SPI DMA.

Internal Loopback Mode

In this mode different types of loopback are possible since there is only one DMA channel available: Core receive and transmit transfers Transmit DMA and core receive transfers Core Transmit and DMA receive transfers To loop data back from MOSI to MISO, the MISO pin is internally disconnected. The MOSI pin will contain the value being looped back. Programs should set the SPIEN, SPIMS, and ILPBK bits in the SPICTLx register.

Loopback operation is only used in master mode.

Loopback Routing The SPI supports an internal loopback mode using the SRU. For more information, see Loopback Routing on page 10-39.

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17 PERIPHERAL TIMERS

In addition to the internal core timer, the ADSP-214xx processors contain identical 32-bit peripheral timers that can be used to interface with external devices. Each timer can be individually configured in three operation modes. The timers specifications are shown in Table 17-1. Table 17-1. Timer Specifications
Feature Connectivity Multiplexed Pinout SRU DPI Required SRU DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels No N/A N/A N/A Yes Yes N/A N/A N/A No Yes Yes Yes Timer10

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Features

Table 17-1. Timer Specifications (Contd)

Feature DMA Chaining Boot Capable Local Memory Max Clock Operation Timer10 N/A N/A No fPCLK/4

Features
The peripheral timers have the features described below. Independent general-purpose timers. Three operation modes (PWM, Width capture, external watchdog). Global control/status registers for synchronous operation of multiple timers. Buffered timer registers (Period and Width) to allow changes on the fly. Supported timer period in the range from 4 tPCLK to 2 109 tPCLK. core is controlled while the periph The timerstimercontrolled by by system registersregisters. For eral are memory-mapped information on system registers, the SHARC Processor Programming Reference.

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Pin Descriptions
The timer has only one pin which acts as input or output based on the timer mode as shown in Table 17-2. Table 17-2. Peripheral Timer Pin Descriptions
Internal Node TIMER10_I Type I Description Timer Signal. This input is active sampled during pulse width and period capture (width capture mode) or external event watchdog (external clock mode). Timer Signal. This output is active driven in pulse width modulation (PWM out mode). Timer Pin Buffer Enable Output Signal. This output is only driven in PWM out mode.

TIMER10_O TIMER10_PBEN_O

O O

SRU Programming
Since the timer has operation modes for input (capture and external clock mode) and output (PWM out mode), it requires bidirectional junctions. Table 17-3 shows the required SRU routing. Table 17-3. Peripheral Timer SRU2 Signal Connections
TIMERx Source TIMER10_O TIMER10_O TIMER10_PBEN_O DPI Group Group A Group B Group C TIMERx Destination TIMER10_I

See also DPI Routing Capabilities on page 10-24.

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Register Overview

Register Overview
The following sections provide brief descriptions of the primary registers used to program the timers. For complete information on the timer registers, see Peripheral Timer Registers on page A-260. Control Registers (TMxCTL). Controls the operation mode (external clock, width capture, PWM out) and enables interrupt flow. Bit for waveform control is also provided in this register. Global Status and Control Register (TMSTAT). Indicates the status of both timers using a single read. The TMSTAT register also contains timer enable bits. Within TMSTAT, each timer has a pair of sticky status bits, that require a write one-to-set (TIMxEN) or write one-to-clear (TIMxDIS) to enable and disable the timer respectively. Counter Registers (TMxCNT). When disabled, the timer counter retains its state. When re-enabled, the timer counter is re initialized from the period/width registers based on configuration and mode. The timer counter value should not be set directly by the software. It can be set indirectly by initializing the period or width values in the appropriate mode. The counter should only be read when the respective timer is disabled. This prevents erroneous data from being returned. Period Registers (TMxPRD). When enabled and running, the processor writes new values to the timer period and pulse width registers. The writes are buffered and do not update the registers until the end of the current period (when the timer counter register equals the timer period register). Pulse Width Register (TMxW). During the pulse width modulation (PWM_OUT), the width value is written into the timer width registers. Both width and period register values must be updated on the fly since the period and width (duty cycle) change simultaneously. To insure period and width value concurrency, a 32-bit period buffer and a 32-bit width buffer are used.

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Read-Modify-Write
The traditional read-modify-write operation to enable/disable a peripheral is different for the timers. For more information, see Peripheral Timer Registers on page A-260.

Clocking
The fundamental timing clock of the peripheral timers is peripheral clock (PCLK). The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

Functional Description
Each timer has one dedicated bidirectional chip signal, TIMERx. The two timer signals are connected to the 14 digital peripheral interface (DPI) pins through the signal routing unit (SRU). The timer signal functions as an output signal in PWM_OUT mode and as an input signal in WDTH_CAP and EXT_CLK modes. To provide these functions, each timer has four, 32-bit registers shown in Figure 17-1. During the pulse width modulation (PWM_OUT), the period value is written into the timer period registers. Both period and width register values must be updated on the fly since the period and width (duty cycle) change simultaneously. To insure the period and width value concurrency, a 32-bit period buffer and a 32-bit width buffer are used. During the pulse width and period capture (WDTH_CAP) mode, the period values are captured at the appropriate time. Since both the period and width registers are read-only in this mode, the existing 32-bit period and width buffers are used (see Figure 17-1). During the external event watchdog (EXT_CLK) mode, the period register is write-only. Therefore, the period buffer is used in this mode to insure

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Functional Description

high/low period value coherency. When the processor is in EXT_CLK mode, the width register is unused. When clocked internally, the clock source is the processors peripheral clock (PCLK). The timer produces a waveform with a period equal to 2 x TMxPRD and a width equal to 2 TMxW. The period and width are set through the TMxPRD300 and the TMxW300 bits. Bit 31 is ignored for both. The equation for the timer period is: 2 (2^DIV 1) tPCLK where DIV = period register 2(311)
PERIPHERAL CORE BUS 32 PERIOD BUFFER (32 BIT) 32 WIDTH BUFFER (32 BIT)

32

32 TIMERx_PERIOD (32 BIT)

32 TIMERx_WIDTH (32 BIT)

TIMERx_COUNTER (32 BIT) EXPIRE

EQUAL?

EQUAL?

CONTROL LOGIC

CONTROL LOGIC

32 (READ ONLY)

Figure 17-1. Timer Block Diagram with Buffered Period and Width Registers

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Operating Modes
The three operating modes of the peripheral timer; PWM_OUT, WDTH_CAP, and EXT_CLK, are described in Table 17-4 and the following sections. Table 17-4. Timer Bits Comparison
Bits PWM_OUT Mode WIDTH_CAP Mode EXT_CLK Mode Timer Control Registers (TMxCTL) TIMODE PULSE PRDCNT IRQEN Timer Status Register (TMSTAT) TMxOVF (IRQ also set) Set if Initialized with: Period < Width or Period == Width or Period == 0 Set if the Counter wraps (Error Condition) Unused 01 = PWM Out 10 = Width Capture 11 = External Clock 1 = Count at event rise 0 = Count at event fall Unused

1 = Generate High Width 1 = Measure High Width 0 = Generate Low Width 0 = Measure Low Width 1 = Generate PWM 0 = Single Width Pulse 1 = Measure Period 0 = Measure Width 1 = Enable Interrupt 0 = Disable Interrupt

TMxIRQ (If enabled) TIMxEN TIMxDIS Counter Registers TMxPRD TMxW TMxCNT

If PRDCNT: 1 = Set at end of Period 0 = Set at end of Width Enable and start timer Disable timer

Set after period expires and PCLK is running

WO: Period value WO: Width value

RO: Period value RO: Width value

WO: Period value Unused RO: Only if not enabled counts down on event

RO: Only if not enabled Counts down on PCLK

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Operating Modes

Pulse Width Modulation Mode (PWM_OUT)

In PWM_OUT mode, the timer supports on-the-fly updates of period and width values of the PWM waveform. The period and width values can be updated once every PWM waveform cycle, either within or across PWM cycle boundaries. To enable PWM_OUT mode, set the TIMODE10 bits to 01 in the timers configuration (TMxCTL) register. This configures the timers TIMERx signal as an output with its polarity determined by PULSE as follows: If PULSE is set (= 1), an active high width pulse waveform is generated at the TIMERx signal. If PULSE is cleared (= 0), an active low width pulse waveform is generated at the TIMERx signal. The timer is actively driven as long as the TIMODE field remains 01. Figure 17-2 shows a flow diagram for PWM_OUT mode. When the timer becomes enabled, the timer checks the period and width values for plausibility (independent of the value set with the PRDCNT bit) and does not start to count when any of the following conditions are true: Width is equal to zero Period value is lower than width value Width is equal to period On invalid conditions, the timer sets both the TIMxOVF and the TIMIRQx bits and the Count register is not altered. Note that after reset, the timer registers are all zero. The PWM_OUT timing is shown in Figure 17-3. As mentioned earlier, 2 x TMxPRD is the period of the PWM waveform and 2 x TMxW is the width. If the period and width values are valid after the timer is enabled, the count register is loaded with the value resulting from 0xFFFF FFFF width. The timer counts upward to 0xFFFF FFFF.

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PERIPHERAL CORE BUS

TIMERx_PERIOD

TIMERx_WIDTH

PCLK

TIMERx_COUNTER

RESET

EQUAL? YES TIMER_ENABLE

EQUAL? YES

ASSERT 1 0 INTERRUPT PULSE PWMOUT LOGIC

DEASSERT

PERIOD_CNT

TIMERx_O

Figure 17-2. Timer Flow Diagram PWM_OUT Mode Instead of incrementing to 0xFFFF FFFF, the timer then reloads the counter with the value derived from 0xFFFF FFFF (period width) and repeats.

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Operating Modes

PCLK

PERIOD

P/2

WIDTH cycle W_BUF cycle P_BUF cycle

W/2

X=P-W

COUNTER

W-1

X-1

ZERO cycle TIMERx_O cycle IRQ

Figure 17-3. PWM_OUT Timing PWM Waveform Generation If the PRDCNT bit is set, the internally-clocked timer generates rectangular signals with well-defined period and duty cycles. This mode also generates periodic interrupts for real-time processing. The 32-bit period (TMxPRD) and width (TMxW) registers are programmed with the values of the timer count period and pulse width modulated output pulse width. When the timer is enabled in this mode, the TIMERx signal is pulled to a deasserted state each time the pulse width expires, and the signal is asserted again when the period expires (or when the timer is started).

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To control the assertion sense of the TIMERx_O signal, the PULSE bit in the corresponding TMxCTL register is either cleared (causes a low assertion level) or set (causes a high assertion level). When enabled, a timer interrupt is generated at the end of each period. An ISR must clear the interrupt latch bit TIMxIRQ and might alter period and/or width values. In pulse width modulation applications, the program can update the period and pulse width values while the timer is running. a program updates register Whenalways be written to the timer configuration, the update only must last, even if it is necessary to
TMxW

one of the registers. When the TMxW value is not subject to change, the ISR reads the current value of the TMxW register and rewrites it again. On the next counter reload, all of the timer control registers are read by the timer. To generate the maximum frequency (or minimum period) on the TIMERx_O output signal, set the period value to 2 and the pulse width to 1. This makes the TIMERx signal toggle every 2 PCLK clock cycles as shown in Figure 17-9 on page 17-21. Assuming PCLK = 133 MHz: Maximum period = 2 (231 1) 7.5 ns = 32 seconds. requires a If your applicationChapter 8, more sophisticated PWM output generator, refer to Pulse Width Modulation. Single-Pulse Generation If the PRDCNT bit is cleared, the PWM_OUT mode generates a single pulse on the TIMERx_O signal. This mode can also be used to implement a well defined software delay that is often required by state machines. The pulse width (= 2 TMxW) is defined by the width register and the period register should be set to a value greater than the pulse width register. At the end of the pulse, the interrupt latch bit (TIMxIRQ) is set and the timer is stopped automatically. If the PULSE bit is set, an active high pulse

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Operating Modes

is generated on the TIMERx_O signal. If the PULSE bit is not set, the pulse is active low. Pulse Mode The waveform produced in PWM_OUT mode with PRDCNT = 1 normally has a fixed assertion time and a programmable deassertion time (via the TMxW register). When both timers are running synchronously by the same period settings, the pulses are aligned to the asserting edge as shown in Figure 17-4. Note that the timer does not support toggling of the PULSE bit in each period.
PERIOD 1 PULSE = 1 TMR0

ACTIVE HIGH

PULSE = 1

TMR1

ACTIVE HIGH

TIMER ENABLE

Figure 17-4. Timers with Pulses Aligned to Asserting Edge

Pulse Width Count and Capture Mode (WDTH_CAP)

To enable WDTH_CAP mode, set the TIMODE10 bits in the TMxCTL register to 10. This configures the TIMERx signal as an input signal with its polarity determined by PULSE. If PULSE is set (= 1), an active high width pulse waveform is measured at the TIMER_Ix signal. If PULSE is cleared (= 0), an active low width pulse waveform is measured at the TIMERx_I signal. The internally-clocked timer is used to determine the period and pulse width of externally-applied rectangular waveforms. The period and

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Peripheral Timers

width registers are read-only in WDTH_CAP mode. The period and pulse width measurements are with respect to a clock frequency of PCLK 2. Figure 17-5 shows a flow diagram for WDTH_CAP mode. In this mode, the timer resets words of the count in the TMxCNT register value to 0x0000 0001 and does not start counting until it detects the leading edge on the TIMERx_I signal.
PERIPHERAL CORE BUS

TIMERx_PERIOD

TIMERx_WIDTH

PCLK

TIMERx_COUNTER

RESET

PULSE TIMERx_I

PULSE

TIMERx_I

LEADING EDGE DETECT

TIMER_ENABLE

TRAILING EDGE DETECT

TMxOVF PERIOD_CNT INTERRUPT LOGIC

INTERRUPT

Figure 17-5. Timer Flow Diagram WDTH_CAP Mode When the timer detects a first leading edge, it starts incrementing. When it detects the trailing edge of a waveform, the timer captures the current value of the count register (= TMxCNT 2) and transfers it into the TMxW width registers. At the next leading edge, the timer transfers the current value of the count register (= TMxCNT 2) into the TMxPRD period register.

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Operating Modes

The count registers are reset to 0x0000 0001 again, and the timer continues counting until it is either disabled or the count value reaches 0xFFFF FFFF. In this mode, programs can measure both the pulse width and the pulse period of a waveform. To control the definition of the leading edge and trailing edge of the TIMERx_I signal, the PULSE bit in the TMxCTL register is set or cleared. If the PULSE bit is cleared, the measurement is initiated by a falling edge, the count register is captured to the WIDTH register on the rising edge, and the period register is captured on the next falling edge. The PRDCNT bit in the TMxCTL register controls whether an enabled interrupt is generated when the pulse width or pulse period is captured. If the PRDCNT bit is set, the interrupt latch bit (TIMxIRQ) gets set when the pulse period value is captured. If the PRDCNT bit is cleared, the TIMxIRQ bit gets set when the pulse width value is captured. If the PRDCNT bit is cleared, the first period value has not yet been measured when the first interrupt is generated. Therefore, the period value is not valid. If the interrupt service routine reads the period value anyway, the timer returns a period value of zero. When the period expires, the period value is loaded in the TMxPRD register. A timer interrupt (if enabled) is also generated if the count register reaches a value of 0xFFFF FFFF. At that point, the timer is disabled automatically, and the TIMxOVF status bit is set, indicating a count overflow. The TIMxIRQ and TIMxOVF bits are sticky bits, and programs must explicitly clear them. The WDTH_CAP timing is shown in Figure 17-6. The first width value captured in WDTH_CAP mode is erroneous due to synchronizer latency. To avoid this error, programs must issue two NOP instructions between setting WDTH_CAP mode and setting TIMxEN.

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Peripheral Timers

PCLK

TIMERx_I
synchronized

cycle COUNTER W-1 W W+1 P-2 P-1 P 0 1 2

W_BUF cycle P_BUF cycle PERIOD cycle WIDTH cycle IRQ

P/2

W/2

Figure 17-6. WDTH_CAP Timing (Period Count = 1)

External Event Watchdog Mode (EXT_CLK)

Figure 17-7 shows a flow diagram for EXT_CLK mode. To enable EXT_CLK mode, set the TIMODE10 bits in the TMxCTL register to 11 in the TMxCTL register. This samples the TIMERx_I signal as an input. Therefore, in EXT_CLK mode, the TMxCNT register should not be read when the counter is running. The operation of the EXT_CLK mode is as follows: 1. Program the TMxPRD period register with the value of the maximum timer external count. 2. Set the TIMxEN bits. This loads the period value in the count register and starts the countdown. 3. When the period expires, an interrupt, (TIMxIRQ) occurs.

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Operating Modes

After the timer is enabled, it waits for the first rising edge on the TIMERx_I signal. The rising edge forces the count register to be loaded by the value (0xFFFF FFFF TMxPRD). Every subsequent rising edge increments the count register. After reaching the count value 0xFFFF FFFE, the TIMxIRQ bit is set and an interrupt is generated. The next rising edge reloads the count register with (0xFFFF FFFF TMxPRD) again.
PERIPHERAL CORE BUS

TIMERx_PERIOD

CLOCK TIMERx_COUNTER RESET EQUAL? LEADING EDGE DETECT TIMERx_I

Y INTERRUPT TIMER_ENABLE PULSE

Figure 17-7. Flow Diagram EXT_CLK Mode The EXT_CLK timing is shown in Figure 17-8. The configuration bit, PRDCNT, has no effect in this mode. Also, TIMxOVF is never set and the width register is unused.

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Peripheral Timers

TIMERx_I

PERIOD

cycle P_BUF P

cycle COUNTER P P-1 P-2 2 1 0 P P-1 P-2

sync delay

IRQ

Figure 17-8. EXT_CLK Timing

Interrupts
Table 17-5 provides an overview of timer interrupts. Table 17-5. Overview of Timer Interrupts
Default Programmable Interrupt GPTMR0I = P2I GPTMR1I = P10I Sources Masking Service

Timer Expire Timer Overflow

IRQEN-bit (TMxCTL)

RW1C to TMxSTAT + RTI instruction

Sources
The timer module drives one interrupt signal, GPTIMERxI. Each timer generates a unique interrupt request signal. A common register latches these interrupts so that a program can determine the interrupt source without reference to the timer's interrupt signal. The timers can

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Interrupts

generate interrupts under the conditions described in the following sections. PWM_OUT Mode Depends on the PRDCNT bit setting as follows. 1 = Set at the end of period 0 = Set at the end of width WDTH_CAP Mode Depends on the PRDCNT bit setting as follows. 1 = Set at the end of period 0 = Set at the end of width EXT_CLK Mode Set after Period expires and PCLK is running PWM_OUT Mode Set for programming errors initialized with: Period < Width or Period == Width or Period == 0 WDTH_CAP Mode Set if the counter wraps, error condition.

Masking
The GPTMR0I and GPTMR1I signals are routed by default to programmable interrupt. To service the GPTMR0I signal, unmask (set = 1) the P2I bit in

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Peripheral Timers

the IMASK register. To service the secondary GPTMR1I, unmask (set = 1) the P10IMSK bit in the LIRPTL register. For example:
bit set IMASK P2I; bit set LIRPTL P10IMSK; /* unmasks P2I interrupt */ /* unmasks P10I interrupt */

To enable a timers interrupt, set the IRQEN bit in the timer's configuration (TMxCTL) register With the IRQEN bit cleared, the timer does not set its interrupt latch (TIMxIRQ) bits. To poll the TIMxIRQ bits without generating a timer interrupt, programs can set the IRQEN bit while leaving the timer's interrupt masked.

Service
The TMSTAT register contains an interrupt latch bit (TIMxIRQ) and an overflow/error indicator bit (TIMxOVF) for each timer. With interrupts enabled, ensure that the interrupt service routine (ISR) clears the TIMxIRQ latch before the RTI instruction to assure that the interrupt is not serviced erroneously. In external clock (EXT_CLK) mode, the latch should be reset at the very beginning of the interrupt routine so as not to miss any timer event. These sticky bits are set by the timer hardware and may be watched by software. They need to be cleared in the TMSTAT register by software explicitly.To clear, write a one to the corresponding bit in the TMSTAT register as shown in Listing 17-1.

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Effect Latency

Listing 17-1. Clearing Sticky Bits

TMR0_ISR: ustat2=TIM0IRQ; dm(TM0STAT)=ustat2; r10=dm(TM0CTL); instructions; instructions; RTI; /* RW1C the Timer0 bit */ /* dummy read for write latency */

Interrupt andoroverflow bits may be cleared simultaneously with timer enable disable.
Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

Timers Effect Latency

After the timer registers are configured the effect latency is 3 PCLK cycles enable and 2 PCLK cycles disable. The timer starts 3 PCLK cycles after the TIMEN bit is set. When the timer is enabled, the count register is loaded according to the operation mode specified in the TMxCTL register. When the timer is disabled, the counter registers retain their state; when the timer is re-enabled, the counter is reinitialized based on the operating mode (Figure 17-9). The program should never write the counter value directly.

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TIMER ENABLE
CCLK

SET TIM EN

TIMER ENABL ED

PCL K

PWMOUT TCOUNT = XX TCOUNT = XX TCOUNT =XX TCOUNT =1 TCOUNT =2 TCOUNT =3 T COUNT =4 TMx PRD = 0X2 TMx W = 0X1 SET TIM DIS TIMER DISABLED

TIMER DISABLE

CCL K TCOUNT =M T COUNT =M +1 TCOUNT =M +1 T COUNT =M+ 1 T COUNT =M+ 1

Figure 17-9. Timer PWM Enable and Disable Timing

Programming Model
The section describes which sequences of software steps are required to get the peripheral working successfully. To enable an individual timer, set the timers TIMxEN bit in the TMSTAT register. To disable an individual timer, set the timers TIMxDIS bit in the TMSTAT register. To enable both timers in parallel, set all the TIMxEN bits in the TMSTAT register. Before enabling a timer, always program the corresponding timers configuration (TMxCTL) register. This register defines the timers operating mode, the polarity of the TIMERx signal, and the timers interrupt behavior. Do not alter the operating mode while the timer is running. For more information, see Timer Control Registers (TMxCTL) on page A-261.

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Programming Model

PWM Out Mode

Use the following procedure to configure and run the timer in PWM out mode. 1. Reset the TIMEN bit and set the configuration mode to 01 to select PWM_OUT operation. This configures the TIMERx_O pin as an output pin with its polarity determined by the PULSE bit. The timer outputs a positive active pulse width at the TIMERx_O pin. The timer outputs a negative active pulse width at the TIMERx_O pin. 2. Initialize the period before the width register values. Insure that the period value is greater than the width value. 3. Set the TIMEN bit. The timer performs boundary exception checks on the period and width values: If (width == 0 or Period < width or period == width) both the OVF_ERR and IRQ bits are set. If there are no exceptions, the width value is loaded into the counter and it starts counting. The timer produces PWM waveform with a period of 2 x period and a width of 2 x width. When 2 x width expires, the counter is loaded with 2x(period width) and continues counting. When 2 x period expires, the counter is loaded with 2 x width value again and the cycle repeats. When the width or period expires, the IRQ bit (if enabled) is set depending on the PRDCNT bit.

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Peripheral Timers

When IRQ is sensed, read the status register (TMxSTAT) and perform the appropriate read-write-to-clear.

WDTH_CAP Mode
Use the following procedure to configure and run the timer in WDTH_CAP out mode. 1. Reset the TIMEN bit and set the configuration mode to 10 to select WDTH_CAP operation. This configures the TIMERx_I pin as an input pin with its polarity determined by the PULSE bit. The timer measures a positive active pulse width at the TIMERx_I pin. The timer measures a negative active pulse width at the TIMERx_I pin. 2. The PRDCNT bit determines when the IRQ status bit (if enabled) is set. If (PRDCNT == 1), IRQ is set when the period expires and the value is captured. If (PRDCNT == 0), IRQ is set when the width expires and the value is captured. 3. Valid period and width values are set in their respective registers when IRQ is set. The period and width values are measured with respect to PCLK. This makes this mode coherent with the PWM_OUT mode, where the output waveforms have a period of 2 x period and a width of 2 x width.

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Programming Model

Note that the first period value will not have been measured when the first width is measured, so it is not valid. The timer sets and returns a period value of zero in this case. When the period expires, the period value is placed into the period register. When IRQ is sensed, read the status and perform the appropriate RW1C operation.

EXT_CLK Mode
Use the following procedure to configure and run the timer in EXT_CLK out mode. 1. Reset the TIMEN bit and set the configuration mode to 11 to select EXT_CLK operation. This configures the TIMERx_I pin as an input pin regardless of the setting of the PULSE bit. Note that the timer always samples the rising edge in this mode. The period register is WO and the width register is unused in this mode. 2. Initialize the period register with the value of the maximum external count. 3. Set the TIMEN bit. This loads the period value in the counter and starts the count down. When the period expires, it is reloaded with the period value and the cycle repeats. Counter counts with each edge of the input waveform, asynchronous to PCLK. When the period expires, IRQ (if enabled) is set and TMR_IRQ is asserted. An external clock can trigger the Timer to issue an interrupt and wake up an idle processor. Reads of the count register are not supported in EXT_CLK mode.

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Peripheral Timers

Debug Features
The following section provides information on debugging features available with the timer.

Loopback Routing
The timer support an internal loopback mode by using the SRU. For more information, see Loopback Routing on page 10-39. An emulation halt will not stop the timer period counter.

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Debug Features

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18 SHIFT REGISTER ADSP-2147x

ADSP-2147x processors incorporate an 18 stage serial in, serial/parallel out Shift Register (SR). The serial inserial out mode can be used to delay the serial data by a fixed amount of time. The serial output can also be used to cascade the shift register modules on two or more processors. The serial inparallel out mode can be used to convert the serial data to parallel. Table 18-1 lists the shift register specifications. Table 18-1. Shift Register Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex N/A N/A N/A N/A N/A No Yes Yes No No N/A Availability

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Features

Table 18-1. Shift Register Specifications (Contd)

Feature Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation Yes N/A N/A N/A N/A N/A No fPCLK/4 Availability

Features
The following list describes the features of the shift register. 18-stage serial/parallel shift register. 18-bit parallel data latch. 18 parallel output signals (SR_LDO17-0) with can be three-stated. Serial data input (SR_SDI) and output pins (SR_SDO) allows cascading of multiple SR registers. SRU routing unit allows the input selection for clock and data from SPORT7-0, PCGA-B, DAI Pin buffer 81 or external SR pins. Pin buffers remain three-stated coming out of reset until configured by software as outputs.

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Shift Register ADSP-2147x

Pin Descriptions
The pin descriptions for the shift register are described in the ADSP-2147x data sheet.

SRU Programming
To use the shift register, route the required inputs using the SRU as described in Table 18-2, taking not of the following. The SR_SCLK, SR_LAT, and SR_SDI inputs must come from the same source except in the cases: where SR_SCLK comes from PCGA/B then SPORT07 generates the SR_LAT and SR_SDI signals or where SR_SCLK and SR_LAT come from PCGA/B then SPORT07 generates the SR_SDI signal. Configure CKRE = 1 (SPCTL register) when using SPORT07 as a source of SR_SCLK_I, SR_LAT_I, and SR_DAT_I signals. Table 18-2. SR SRU Connections
Shift Register Source SR_SCLK_O (dedicated pin) SR_LAT_O (dedicated pin) SR_SDAT_O (dedicated pin) DAI Connection Group H Group I Shift Register Destination SR_CLK_I SR_LAT_I SR_SDI_I

The shift register input pins (SR_CLK_I, SR_LAT_I, SR_SDI_I) are routed by default to the external shift register pins (SR_CLK, SR_LAT, SR_SDI).

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Register Overview

Register Overview
The processor contains registers that are used to control the shift register. Control Register (SR_CTL). Used to clear/reset the shift register in software, select the data source for the SR_SDO pin out of the 18 bits of the register, and to enable parallel data output. Complete bit descriptions can be found at Shift Register Control Register on page A-206. Clock Routing Register (SRU_CLK_SHREG). Configures the clock source. For more information, see Destination Control Signal Register (SR_CLK_SHREG) on page A-151. Data Routing Register (SRU_DAT_SHREG). Configures the data source. For more information, see Group I Shift Register Serial Data Routing Register (ADSP-2147x) on page A-152.

Clocking
The shift register requires two clock inputs: SR_SCLK_I for the serial shift register and SR_LAT_I for the latch. The source of these clocks is selectable out of many sources such as the SPORTs, PCGA/B, DAI pin buffers 81, or dedicated SR_SCLK and SR_LAT input pins. The data is shifted on the rising edge of the SR_SCLK_I and the data from the shift register is transferred to the latch on rising edge of the SR_LAT_I. If both clocks are connected together, the shift register is always one clock pulse ahead of the latch.

Functional Description
The Shift Register module consists of an 18-stage serial shift register, 18-bit latch, and three-state output buffers. Three-state buffers are implemented in I/O buffers. The shift register and latch have separate clocks.

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Shift Register ADSP-2147x

Data is shifted on the positive-going transitions of the SR_SCLK_I input. The data in each flip-flop is transferred to the respective latch on a positive-going transition of the SR_LAT_I input. The shift register has a serial data input (SR_SDI_I) and a serial data output (SR_SDO) for cascading. A common active low asynchronous reset (SR_CLR_I) is provided for 18-bit shift register and for 18-bit latch. As shown in the Figure 18-1, the latch has 18 parallel outputs to drive three-state output buffers. Data in the latch appears at the output whenever the output enable input (SR_LDOE_I) is high.
SW RESET SR RESET HW RESET SR_CTL[6-2] 5 DAI_PB08-01_O
CLR

8 PCG_CLKA_O PCG_CLKB_O PCG_FSA_O PCG_FSB_O

SR_SCLK_I SR_SDI_I

18-STAGE SHIFT REGISTER

SR_SDO 18

18

SR_SDI* SR_SCLK* SR_LAT*

SR_LAT_I
EN

THREE-STATE OUTPUT BUFFERS

SRU
18-BIT LATCH
CLR

SR_LDO[17-0] 18

SPORTx_DA/DB_O SPORTx_FS_O

SHIFT REGISTER BLOCK SR_CTL[0]

OE

SPORTx_CLK_O I/O BUFFERS

*DEDICATED PINS (NOT DAI/DPI PINS)

Figure 18-1. Shift Register Block Diagram The SR_CLR_I signal is derived from an dedicated pin (SR_CLR), and a software programmable reset (SR_SW_CLR bit in the SR_CTL register). If either of these two signals goes low, then SR_CLR_I goes low. The serial data

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Operating Modes

output (SR_SDO) can be selected from any one of the 18-bit registers outputs. Selection of the source is provided through software using the SR_CTL register. A common active low asynchronous reset ( SR_CLR_I) is provided for the shift register and for the latch.

Operating Modes
This section describes the two operation modes used by the shift register.

Serial Data Output

The shift register outputs serial data on the SR_SDO pins based on the SR_SDO_SEL bits in the SR_CTL register. These bits select which serial data of the 18-bit stream are moved to the serial output. By default if all the SR_SDO_SEL bits are cleared, the LSB data is output. This mode is for useful if multiple SR registers need to be cascaded.
SR_SCLK

SR_SDI

SR_LAT

RESET/ SR_SW_CLR

SR_LDOE SR_LDO

0x00003 0x00006 0x0000D 0x0001A 0x00035 0x0006A 0x000D6

SR_SDO (LSB)

Figure 18-2. Shift Register Timing

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Shift Register ADSP-2147x

Parallel Data Output

If the SR_LDOE bit in the SR_CTL register is set, the output stage of the parallel data latch is enabled. Data in the latch appears at the output whenever this bit is set. The data in each flip-flop is transferred to the respective latch on a positive-going transition of the SR_LAT_I input. If both clocks are connected together, the shift register is always one clock pulse ahead of the latch.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

Shift Register Effect Latency

After the SR register is configured, the maximum effect latency is 2 PCLK cycles.

Programming Model
Since the SR_CTL, SRU_CLK_SHREG, and SRU_DAT_SHREG register signals come from the peripheral clock domain (PCLK) to the SR_SCLK_I and

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Programming Model

SR_LAT_I

domain, there are timing violations for one SR_SCLK_I period. To avoid this program the following registers in the order listed. 1. The SRU_CLK_SHREG, and SRU_DAT_SHREG registers. 2. The SR_CTL register. 3. Drive the SR_SCLK_I, SR_LAT_I, and SR_SDI_I input signals. 4. The SR_CTL, SRU_CLK_SHREG, and SRU_DAT_SHREG registers are in PCLK domain. There may be timing violations for signals crossing PCLK domain to the SR_SDCLK_I and SR_LAT_I domain. To avoid this first program SR_CTL, SRU_CLK_SHREG, and SRU_DAT_SHREG registers and then drive on SR_SDCLK_I, SR_LAT_I, and SR_SDI_I.

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19 REAL-TIME CLOCK ADSP-2147x/ADSP-2148x

The ADSP-2147x processors contain a real-time clock (RTC) which provides a set of digital watch features to the processor, including time of day, alarm, and stopwatch countdown. It is typically used to implement either a real-time watch or a life counter. The RTC specifications are shown in Table 19-1. Table 19-1. RTC Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer N/A Yes No N/A N/A N/A No No N/A No N/A Yes Availability

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Table 19-1. RTC Specifications (Contd)

Feature Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation Availability N/A N/A N/A N/A No No fPCLK

Features
The RTC interface has the following features. Provides a 1 Hz clock with Second, Minute, Hour and Day Counter (0 to 32767 days). Alarm Feature available with time of day interrupt. Operates on a dedicated supply from an external 3.3 V battery. Stopwatch function available. Standard two pin interface with external 32.768 kHz crystal, 6 pF capacitor on each pin and 100 M resistor between the pins. RTC Power switches to that of I/O Supply when chip is powered on, saving battery life. Calibration Feature available to correct time once a day; application can use RTCXTALIN pin to determine calibration settings.

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Real-Time Clock ADSP-2147x/ADSP-2148x

Pin Descriptions
The pins used for the real-time clock are described in the ADSP-2147x and the ADSP-2148x SHARC Processor data sheets.

Clocking
The RTC timer has a 32.768 kHz crystal external to the processor. An internal clock divider scales the crystal clock down to a 1 Hz reference clock (RTCLKOUT pin) which triggers all RTC counters. The RTC interface is clocked internally with PCLK. For clock power management refer to Chapter 23, Power Management.

Register Overview
This section provides basic information on the RTC control and status registers only. Complete bit information can be found at Real-Time Clock Registers on page A-115. The RTC_CTL, RTC_STAT, and RTC_INITSTAT registers are user registers located in the RTC core voltage domain and can be directly accessed over the peripheral bus. Control Register (RTC_CTL). Controls RTC functions and the RTC interrupt enable functions. Status Register (RTC_STAT). Reports RTC status and interrupt status. Initialization Status Register (RTC_INITSTAT). Reports the register status of the 1 Hz domain.

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Functional Description

The RTC_CLOCK, RTC_ALARM, RTC_INIT, and RTC_STPWTCH are 1 Hz registers located in the RTC I/O voltage domain and are accessed indirectly by shadow registers in 1 Hz ticks. These register (except RTC_INIT) do not have default reset settings. Clock Count Register (RTC_CLOCK). Used to read or write the current time and is updated every second. Alarm Count Register (RTC_ALARM). Used to control the alarm functions. Stopwatch Count Register (RTC_STPWTCH). Used to have the count-down value for the stopwatch function. Initialization Register (RTC_INIT). Used for calibration purpose and for RTC power-down.

Functional Description
The RTC provides a set of digital watch features to the SHARC processor. It uses an external 32.768 kHz crystal with external capacitors and provides Second, Minute, Hour and Day counts along with an Alarm and Stopwatch feature. The RTC operates on a dedicated external 3.3 V Lithium coin cell which is never powered off. A block diagram of the RTC is shown in Figure 19-1.

Power Supply Partitioning

The RTC logic is partitioned between the processor core supply voltage and RTC I/O supply voltage. The RTC functions on a separate power island on the RTC supply voltage. When the core supply voltage is absent, interrupts are ignored.

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Real-Time Clock ADSP-2147x/ADSP-2148x

PCLK Core Voltage

PCLK RTC Core Voltage STOPWATCH COUNT RTC IRQ INTERRUPT CTRL PCLK PWD

PCLK I/O Voltage

PCLK I/O Voltage IO BATTERY CELL

1 Hz

PRE SCALE

XTAL 32768 Hz

CTRL DATA 8-BIT SHADOW REGS 1 Hz COUNT UPDATE DATA 64-BIT

CLOCK/ ALARM COUNTERS

PERIPHERAL CORE BUS

Figure 19-1. RTC Block Diagram When the processors I/O supply is above a certain threshold, the RTC switches to the I/O supply to conserve battery power. power Batteryoff. supply can operate the RTC when the I/O voltage if turned The RTC is partitioned into two blocks. The counting and clock function is provided in the I/O voltage domain (VDDEXT), while the control and access function and the user interface are provided in the core voltage domain. The RTC I/O operates on a dedicated power supply provided by the external 3.3 V (nominal) lithium coin cell. The RTC also has the ability to switch to the I/O supply (VDDEXT). The RTC core operates on the nominal core voltage supply (VDDINT). The interface between both blocks is provided by a set of level shifters. The partitioning at chip level is shown in Figure 19-1.

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Functional Description

Battery Life
To increase the battery life of the external 3.3V cell, maximum functionality is kept in the RTC core voltage which runs off the chip supply with only basic clock circuitry inside the RTC IO voltage. This means: The seconds, minutes, hours and days counters reside inside the RTC IO voltage. The alarm register and comparators reside inside the RTC IO voltage. This allows programs to power down the rest of the chip without the alarm being reset. The programmable interface registers, through which the application reads or writes the current time and alarm settings, are part of the RTC core voltage. In order to set the current time and/or alarm, software writes into the shadow registers in the RTC core voltage are performed. The data is then transferred into the corresponding register in the RTC IO voltage by hardware. The RTC core voltage runs primarily on the processors peripheral clock while the RTC IO voltage runs primarily on a self generated 1 Hz clock. The synchronization circuitry sits inside the RTC core voltage. The stopwatch circuitry is inside the RTC core voltage and operates on a 1Hz clock, level shifted from the RTC IO voltage.

Digital Watch Counters

The primary function of the RTC is to maintain an accurate day count and time of day. The RTC accomplishes this by means of four counters: 60-second counter 60-minute counter

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Real-Time Clock ADSP-2147x/ADSP-2148x

24-hour counter 32768-day counter The RTC increments the 60-second counter once per second and increments the other three counters when appropriate. The 32768-day counter increments each day at midnight (23 hours, 59 minutes, 59 seconds). Interrupts can be issued periodically, either every second, every minute, every hour, or every day. Each of these interrupts can be independently controlled. The RTC block diagram is shown in Figure 19-2.
EVENT EVENT EVENT EVENT 1 Hz TICK

DAYS COUNTER

HOURS COUNTER

MINUTES COUNTER

SECONDS COUNTER

RTXI 32.768 kHz

9 Y EQUAL? Y EQUAL?

5 Y EQUAL?

6 Y EQUAL?

RTC_ALARM REGISTER

WRITE RTC_STPWTCH REGISTER

SET ALARM EVENT DAY ALARM EVENT NORMAL Y COUNTDOWN EQUAL 0? STOPWATCH COUNTER 16 RST

STOPWATCH EVENT

Figure 19-2. RTC Block Diagram ADSP-214xx SHARC Processor Hardware Reference 19-7

Functional Description

The RTC provides a set of digital watch features. The internal oscillator generates a 32768 Hz signal using the crystal which is scaled down to 1Hz and used to clock the second, minute, hour and day counters. The 32768 day counter increments each day at midnight (during the change from 23:59:59). The counter operates on the RTC supply (either the external battery or I/O supply) and is active irrespective of the status of the processor core supply (VDDINT). When the processor core and I/O supply are valid: the current time is updated every second into the RTC clock register (RTC_CLOCK) interrupts can be issued periodically every second, every minute, every hour or every day Each of the interrupts can be independently controlled, described in Interrupts on page 19-13. It is the responsibility of the program to set the correct time by a software write into the RTC_CLOCK register. Once set, the counters maintain time as long as the RTC supply is valid.

Writes to the 1 Hz Registers

Writes to the RTC 1 Hz registers are synchronized to the 1 Hz RTC clock. When setting the time of day, do not factor in the delay when writing to the RTC 1 Hz registers. The most accurate method of setting the RTC is to monitor the seconds (1 Hz) event flag or to program an interrupt for this event and then write the current time to the RTC status register (RTC_STAT) in the interrupt service routine (ISR). The new value is inserted ahead of the incremented value. Hardware adds one second to the written value (with appropriate carries into minutes, hours and days) and loads the incremented value at the next 1 Hz tick, when it represents the then-current time.

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Writes posted at any time are properly synchronized to the 1 Hz clock. Writes complete at the rising edge of the 1 Hz clock. A write posted just before the 1 Hz tick may not be completed until the 1 Hz tick one second later.

Reads From the 1 Hz Registers

There is no latency when reading 1 Hz registers, as the values come from the shadow registers. The shadows are updated and ready for reading by the time any RTC interrupts or event flags for that second are asserted. Once the internal core logic completes its initialization sequence after PCLK starts, there is no point in time when it is unsafe to read the 1 Hz for synchronization reasons. They always return coherent values, although the values may be unknown.

Operating Modes
The following sections provide information on the operating modes available to the real-time clock.

Alarm
The RTC provides two alarm features, programmed with the RTC alarm register (RTC_ALARM). The first is a time of day alarm (hour, minute, and second). When the alarm interrupt is enabled, the RTC generates an interrupt each day at the time specified. The second alarm feature allows the application to specify a day as well as a time. When the day alarm interrupt is enabled, the RTC generates an interrupt on the day and time specified. The alarm interrupt and day alarm interrupt can be enabled or disabled independently.

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Functional Description

Day Alarm
The second alarm feature allows the application to specify a day as well as a time. When the day alarm interrupt is enabled, the RTC generates an interrupt on the day and time specified. The alarm interrupt and day alarm interrupt can be enabled or disabled independently.

Stopwatch
The RTC stopwatch count register (RTC_STPWTCH) contains the countdown value for the stopwatch. The stopwatch counts down seconds from the programmed value and generates an interrupt (if enabled) when the count reaches 0. The counter stops counting at this point and does not resume counting until a new value is written to RTC_STPWTCH. Once running, the counter may be overwritten with a new value. This allows the stopwatch to be used as a watchdog timer with a precision of one second. The stopwatch can be programmed to any value between 0 and (216 1) seconds, which is a range of 18 hours, 12 minutes, and 15 seconds. Typically, software should wait for a 1 Hz tick, then write the RTC_STPWTCH register. One second later, RTC_STPWTCH changes to the new value and begins decrementing. Because the register write occupies nearly one second, the time from writing a value of N until the stopwatch interrupt is nearly N + 1 seconds. To produce an exact delay, software can compensate by writing N 1 to get a delay of nearly N seconds. This implies that a delay of 1 second with the stopwatch cannot be achieved. Writing a value of 1 immediately after a 1 Hz tick results in a stopwatch interrupt nearly two seconds later. To wait one second, software should just wait for the next 1 Hz tick.

Calibration for Accuracy

To guard against the possibility of long term (> 1 day) errors, the RTC provides a calibration feature using 4 bits of the RTC_INIT register (not available for the stopwatch function). 19-10 ADSP-214xx SHARC Processor Hardware Reference

Real-Time Clock ADSP-2147x/ADSP-2148x

This is a simple a time correction at the end of every day (when the clock register changes from a Day:Hour:Min:Sec value of XXX:23:59:59 to YYY:00:00:00). It functions by adding or subtracting an integer number of seconds (maximum of 7) from the start of the next day, to correct accumulated time error over the course of the previous day. The number of seconds that are added or subtracted is defined in the RTC_INIT register, CALIB field. As an example, if there is a 50 ppm error in the 1Hz frequency, this translates into 86400 50 ppm seconds (=+4.32 seconds) error at the end of the day. That is at 00:00:00, RTC time is 4.32 seconds ahead of actual time. The RTC can correct this by adding 4 seconds (if 4 is the value written into the calibration register) to the time at 00:00:00. Therefore, from 23:59:59, the timer counter jumps directly to 00:00:04, (there is no 00:00:00 to 00:00:03 time occurrences). At the instant it jumps to 00:00:04, the error reduces to +0.32 seconds over the course of the day, which is only 3.7 ppm. As a second example, if there is a +50 ppm error in the 1Hz frequency, this also translates into 86400 50ppm seconds (= 4.32 seconds) error at the end of the day which in this case the time has to be subtracted. This is corrected in the RTC by counting 00:00:00 to 00:00:03 twice, so that the time is effectively subtracted. As soon as the RTC reaches 00:00:04, the error reduces to 0.32 seconds over the course of the previous day and accumulated error is minimized. When the RTC is powered up for the first time, the calibration values are written once to ensure proper functionality. (If they are not to be used, write 0000). These register bits are sticky, which means that once set, they retain their value irrespective of the status of core supply. The addition or subtraction of time can only be in integer multiples of seconds. Zero to seven seconds can be added or subtracted using 4 bits. The MSB indicates addition (0) or subtraction (1). The three LSBs

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Functional Description

indicate number of seconds (0 7 represented by their binary 3 bit equivalents). Because the clock runs at a time period of one second (@ 1 Hz frequency) 0.25 or 0.5 second resolution is not possible. The calibration technique introduces a guard band for alarm by definition. In case the alarm is set within the duration of the time (Day:00:00:00 to Day:00:00:06) corrected by the calibration register, then it occurs at the nearest corrected time. This is shown in the following two examples. If the CALIB value in the RTC_INIT register is 0101, the RTC clock jumps from 23:59:59 to 00:00:05 due to calibration. If the alarm is set to 00:00:01, it occurs at the RTC time 00:00:05. If the CALIB value in the RTC_INIT register is 1101, then the RTC clock counts from 00:00:00 to 00:00:04 twice and then moves to 00:00:05. If the alarm is set to 00:00:01, it occurs at the RTC time 00:00:05.

For calibration purposes the

Accuracy

RTCLKOUT

pin drives the 1 Hz clock.

In order to perform calibration on the bench, use the RTXI pin and check the ppm deviation from 32.768 kHz. This ppm error is the same as in the internal 1Hz clock (RTCLKOUT pin) and the calibration register should be updated with the corresponding values as explained in Calibration for Accuracy above. Note that total accuracy is <= +/ 35 ppm, <+/1.5 minutes per month of error, inclusive of any inaccuracies of the RTC input crystal at room temperature. This is achieved with a crystal of +/ 10 ppm error at 25C. A crystal error of +/20 ppm translates into a maximum inaccuracy of +/45 ppm.

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Real-Time Clock ADSP-2147x/ADSP-2148x

Interrupts
The RTC has one interrupt that is programmable through the programmable interrupt priority control register (see Appendix 2, Interrupt Control). The RTCI source bit is used to connect the RTC interrupt to the peripheral interrupt inputs of the core. Table 19-2 provides and overview of RTC interrupts. Table 19-2. RTC Interrupt Overview
Default Programmable Interrupt RTC not connected by default Sources Second Minute Hour Day Alarm Daily alarm 1Hz clock fail Masking RTC_CTL Service Read to clear RTC_STAT + RTI instruction

Sources
The RTC module generates in total 8 local interrupts which are grouped into 4 counter status, 2 alarm status and 2 system status interrupts. All eight signals are logically ORed into 1 RTC interrupt signal which must be routed into a programmable interrupt. The RTC port can generate interrupts under the conditions described in the following sections. RTC Counter These conditions are based on the RTC counter. Per second Per minute Per hour

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Interrupts

Per day Alarm Daily alarm 1 Hz Register Write Completion Completion of a write to any 1 Hz registers (RTC_CLOCK, RTC_INIT, RTC_ALARM and RTC_STPWTCH). Emulation The module allows programs to enable/disable interrupts for debug purposes. 1 Hz Clock Errors The module generates interrupts on 1 Hz clock failures.

Masking
The RTCI signal is not routed by default to programmable interrupts.To service the RTCI, unmask (set = 1) any programmable interrupt bit in the IMASK/ LIRPTL register. Interrupts can be individually unmasked using the RTC interrupt control register (RTC_CTL). To identify clock errors in the 1Hz domain, programs need to unmask the CKFAIL_INTEN bit in the RTC_CTL register.

Service
In the service routine the RTC_STAT register should be read to identify the cause of the interrupt. While reading the status register the RTC automatically clears the respective status bit ensuring that the cause has been cleared before ending the routine.

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Real-Time Clock ADSP-2147x/ADSP-2148x

Note that the pending RTC interrupt is cleared whenever all enabled and set bits in the RTC_STAT register are read, or when all bits in the RTC_CTL register corresponding to pending events are cleared.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

Real-Time Clock Effect Latency

After the RTC registers are configured the effect latency is 2 PCLK cycles.

Programming Model
The following sections provide basic programming steps for the RTC interface.

1 Hz Register Write Latency

Writes of the alarm, clock, stopwatch and initialization registers is performed in a two step sequence:

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Interrupts

1. The desired values are programmed into a shadow register in the processors core voltage domain and operating on the its peripheral clock (PCLK). 2. The contents of the shadow register are synchronized onto the contents of the RTCs internal clock register which operates on the 1 Hz clock in the I/O voltage domain. between the voltage and RTC voltage To ensure that writessynchronized,corewrite commands should be domain are properly all issued immediately after a seconds event in the RTC_STAT register. This two step sequence results in a write latency of up to 1 second. While the write sequence is ongoing, the write pending (WR_PEND) bit is set in the RTC_STAT register and is cleared by hardware when the process is complete. Resetting or powering down the peripherals while a write is in progress, (WR_PEND bit is set) is forbidden. Subsequent writes to the same register before completion of the previous write are ignored. Do not write to the , registersattemptthe RTC oscillator is powered down or when the when or
RTC_CLOCK RTC_ALARM RTC_BUSDIS RTC_SWTCH

bit is set.
RTC_INIT WR_PEND

During after write register, sure thatinitialization, bit is acleared of the attempting writesmake the before to other registers.

Power-Up, Power-Down and Reset

A programmable register bit is provided to power down the RTC. Here power-down is interpreted as a crystal oscillator disable, which would reduce power dissipation to only leakage current. Once set or reset, this bit retains its value unless changed, irrespective of the status of core supply.

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Real-Time Clock ADSP-2147x/ADSP-2148x

The inclusion of the power-down bit (RTC_PDN) as well as the possibility that the RTC may not be used in certain applications introduces specific constraints on the power-up and reset behavior of the RTC. These are described below. 1. When the RTC is powered-up for the first time, it remains in an undefined state until the core powers-up and the corresponding power-down bit in the RTC_INIT register is written by software. Programs should clear RTC_PDN if the RTC function is desired and set if it is not. 2. After clearing the RTC_PDN bit the application has to wait at least until the first seconds event before it writes the timer and alarm registers. This is because the oscillator has a startup time before the clock is generated. This sequence applies only to the first time the RTC supply (battery or I/O) is connected. Once the RTCPDN bit is set or reset, its value is retained as long as RTC supply (battery or I/O) is valid. 3. After the RTC supply is connected for the first time and the RTC_PDN bit has been cleared, the application is free to power-up and power -down the core supply any number of times without loss of RTC functionality (provided the RTC supplybattery or I/O, is valid). Conversely, if the RTC_PDN bit has been set, then the RTC oscillator remains disabled irrespective of the status of the core supply. 4. The current status of the RTC power-down is updated by hardware into the initialization status register (RTC_INITSTAT) register. This is useful when the rest of the processor wakes up from power-down and needs to know the status of the RTC. 5. Whenever the processor core wakes up from power-down, the values of the RTC_CLOCK, RTC_ALARM and RTC_SWTCH registers is zero until the first seconds event after power-up. At the first seconds event, an arbitrary value is uploaded into these registers. To put ADSP-214xx SHARC Processor Hardware Reference 19-17

Interrupts

them in a defined state software must write the desired value into these registers.In case the RTC_CLOCK and RTC_ALARM have been set before core power-down and subsequent power-up, their values are valid throughout, but can be read by the program only after the first seconds event after power-up.

Status Flags
up event The unknown values in the registersisat powerintocan causethe regisflags to set before the correct value written each of ters. By catching the 1 Hz clock edge, the write to RTC_CLOCK can occur a full second before the write to RTC_ALARM. This would cause an extra second of delay between the validity of RTC_CLOCK and RTC_ALARM, if the value of the RTC_ALARM out of reset is the same as the value written to RTC_CLOCK. Wait for the writes to complete on these registers before using the flags and interrupts associated with their values. The following is a list of flags along with the conditions under which they are valid: Seconds (1 Hz) Event flag Always set on the positive edge of the 1 Hz clock and after shadow registers have updated after waking from power-down. This is valid as long as the RTC 1 Hz clock is running. Use this flag or interrupt to validate the other flags. Write Complete always valid. Write Pending Status always valid. Minutes Event flag valid only after the second field in RTC_STAT is valid. Hours Event flag valid only after the minute field in RTC_STAT is valid.

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Real-Time Clock ADSP-2147x/ADSP-2148x

24 Hours Event flag valid only after the hour field in RTC_STAT is valid. Stopwatch Event flag valid only after the RTC_SWCNT register is valid. Alarm Event flag valid only after the registers are valid. Day Alarm Event flag same as alarm. Writes posted together at the beginning of the same second take effect together at the next 1 Hz tick. The following sequence is safe and does not result in any spurious interrupts from a previous state. 1. Wait for 1 Hz tick. 2. Write new values for RTC_CLOCK, RTC_ALARM, and/or RTC_SWCNT. 3. Write 1s to clear the RTC_CLOCK flags for Alarm, Day Alarm, Stopwatch, and/or per-interval. 4. Write new value for RTC_CTL with Alarm, Day Alarm, Stopwatch, and/or per-interval interrupts enabled. 5. Wait for 1 Hz tick. 6. New values have taken effect simultaneously.
RTC_STAT

and RTC_ALARM

Debug Features
The following section provides information on debugging features available with the real time clock (RTC).

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Interrupts

Emulation Considerations
An emulation halt can optionally mask all RTC interrupts by setting the EMU_INTDIS bit in RTC_CTL register.

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20 WATCHDOG TIMER ADSP-2147x, ADSP-2148x

The ADSP-2147x and ADSP-2148x processors include a 32-bit watchdog timer (WDT) that can be used to implement a software watchdog function. The timer can improve system reliability by forcing the processor to a known state through generation of a system reset if the timer expires before being reloaded by software. The WDT specifications are shown in Table 20-1. Table 20-1. Watchdog Timer Specifications
Feature Connectivity Multiplexed Pinout SRU DPI Required SRU DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Core Data Access No N/A N/A N/A N/A N/A N/A No No No No Availability

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Features

Table 20-1. Watchdog Timer Specifications (Contd)

Feature DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Clock Operation Availability N/A N/A N/A N/A N/A WDTCLKIN

Features
The following list provides a brief description of the watchdog timers features. Programmable time out period with about 1 second with 12 MHz clock. Time out resets the DSP and asserts the external reset (WDTRSTO pin). DSP is reset internally to the chip upon WDT time out. WDT has its own clock (WDT_CLKIN) that is independent from the SHARC CLKIN and any other clock derived from CLKIN. An internal oscillator to provide the clock input. This internal oscillator provides a 2 MHz (typical frequency) clock. Status bit available for the processor to read which is cleared on hardware reset assertion it is not cleared on WDT generated reset.

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WatchDog Timer ADSP-2147x, ADSP-2148x

Programmable trip counter which allows programs to set the number of times the WDT can expire before the WDTRSTO signal is asserted continuously. WDT space is locked and can be accessed only after unlocking the space using commands.

Pin Descriptions
The pins used for the watchdog timer are described in the ADSP-2147x and ADSP-2148x data sheets.

Register Overview
The following sections provide brief descriptions of the primary registers used to program the timers. For more information, see Peripheral Timer Registers on page A-260. Control Register (WDTCTL). The control register is a 32-bit system memory-mapped register used to configure the watchdog timer. Any writes made by the Software to the Register will keep it enabled. Only an External Hardware Reset can disable WDT. Count Register (WDTCNT). Holds the 32-bit unsigned count value. The WDTCNT register must always be accessed with 32-bit read/writes. Current Count Status Register (WDTCURCNT). Contains the current count value of the watchdog timer. Reads to WDTCURCNT return the current count value. Status Register (WDTSTATUS). Contains the watchdog timer status information. This register is not cleared by the WDT generated reset.

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Clocking

Trip Register (WDTTRIP). Sets the number of times that the WDT can expire before the WDTRSTO pin is continually asserted until the next time hardware reset is applied. Unlock Register (WDTUNLOCK). Protects the WDT configuration space (WDTCTL, WDTCNT, WDTCURCNT and WDTTRIP registers) against accidental writes from the processor core. Clock Select Register (WDTCLKSEL). Selects one of the 2 clock sources for WDTCLK, an external source (external clock connected to WDT_CLKIN or a ceramic resonator connected between WDT_CLKIN and WDT_CLKO) or from internal oscillator. For more information, see Clocking on page 20-4.

Internal oscillator is only supported on ADSP-2147x processor models.

Clocking
The WDT provides three options for the clock source. 1. An external clock source can be provided on WDT_CLKIN pin. 2. A ceramic resonator connected between the WDT_CLKIN pin and the WDT_CLKO pin combined with internal circuitry to generate a clock. The ceramic resonator should be either a CERALOCK CSTCR4M00G53-R0 (4 MHz) or CERALOCK CSTCC2M00G56-R0 (2 MHz). 3. An internal RC oscillator. This internal RC oscillator provides a 2 MHz (typical frequency) clock. This feature is only applicable for ADSP-2147x processors.

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WatchDog Timer ADSP-2147x, ADSP-2148x

Functional Description
The watchdog timer is used to supervise the stability of the system software. Software initializes the 32-bit count value of the timer, and then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reload the timer, has stopped running due to an external event or software error. When used in this way, software reloads the watchdog timer in a regular manner so that the downward counting timer never expires. An expiring timer then indicates that system software might be out of control. The watchdog timer resets both the core and the internal peripherals. After an external reset, the WDT must be disabled by default. Software must be able to determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. As shown in Figure 20-1 the clock source for the watchdog timer can be selected from either the internal RC oscillator or from an external oscillator. performs a software the The expired timermore information, seereset (reset core andon peripherals). For Processor Reset page 24-3. After an external reset, the WDT must be disabled by default. Software must be able to determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register.

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Operating Mode

PERIPHERAL CORE BUS

BUS INTERFACE

WDT REGISTERS PCLK/WDTCLK SYNC

CHIP RESET

AND
WDT_RSTO

WDT RESET

COUNTER AND RESET LOGIC

PCLK/WDTCLK SYNC

WATCH DOG TIMER

WDTCLK CLOCK GENERATOR (Resonator/Oscillator) WDTCLKSEL

WDT_CLKIN

WDT_CLKO

Figure 20-1. Watchdog Timer Block Diagram

Operating Mode
The WDT operates in trip count mode as described below.

Trip Count
The WDT contains a software programmable trip counter register that sets the number of times that the timer can expire before the WDTRSTO pin is continually asserted (until the next time hardware reset is applied). The trip counter is not cleared by the WDT generated reset. This gives software the ability to count the number of WDT generated resets using the CURTRIPVAL bits in the WDTTRIP register.

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WatchDog Timer ADSP-2147x, ADSP-2148x

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

Watchdog Timers Effect Latency

After the WDT registers are configured the effect latency is 2 PCLK cycles enable and 2 PCLK cycles disable.

Programming Model
If enabled, the 32-bit watchdog timer counts downward every WDT_CLKIN cycle. When it becomes 0, the system is reset. The counter value can be read through the 32-bit WDTCURCNT register. The WDTCURCNT register cannot, however, be written directly. Rather, software writes the watchdog period value into the 32-bit WDTCNT register before the watchdog is enabled. Once the watchdog is started, the period value cannot be altered. To start the watchdog timer: 1. Unlock the WDT configuration registers by writing the unlock command value to the WDTUNLOCK register. Select the WDTCLK by programming the WDTCLKSEL bit. By default, the resonator output is WDTCLK. 2. Set the trip counter value for the watchdog timer by writing to the WDTTRIP register.

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Programming Model

3. Set the count value for the watchdog timer by writing the count value into the watchdog period register (WDTCNT). Since the watchdog timer is not yet enabled, the write to the WDTCNT registers automatically pre-loads the WDTCURCNT register as well. Note that sufficient time must be provided for the write to the WDTCURCNT register to occur (2.5 WDTCLK cycles max.), before enabling WDT. 4. Enable the watchdog timer in WDTCTL. 5. Lock the WDT configuration registers by writing to the WDTUNLOCK register. The watchdog timer begins counting down, decrementing the value in the WDTCURCNT register every WDT_CLKIN cycle. If software does not serve the watchdog in time, WDTCURCNT continues decrementing until it reaches 0 and the system is reset. The counter now reloads the WDTCURCNT value from WDTCNT and keeps decrementing. Additionally, the WDRO latch bit in the WDTSTATUS register is set and can be interrogated by software. This occurs up to the number of times programmed in the WDTTRIP register. When WDTTRIP expires, WDT holds the WDTRSTO asserted. 6. To prevent the watchdog from expiring, software serves the watchdog by unlocking the WDT configuration space and performing dummy writes to the WDTCURCNT register address in time. The values written are ignored, but the write command cause the WDTCURCNT register to be reloaded from the WDTCNT register. If the watchdog is enabled with a zero value loaded to the counter, WDT expires immediately and resets the system. The WDRO bit of the watchdog control register is also set.

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WatchDog Timer ADSP-2147x, ADSP-2148x

Debug Features
The following section provides information on debugging features available with the watchdog timer.

Emulation Considerations
An emulation halt stops the WDT counter. The WDT resumes counting after being released from emulation halt. Single stepping is not supported for WDT in emulation mode.

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Debug Features

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21 UART PORT CONTROLLER

The universal asynchronous receiver/transmitter (UART) is a full-duplex peripheral compatible with the PC-style, industry-standard UART. The interface specifications are shown in Table 21-1. Table 21-1. UART Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access Yes Yes Yes Yes Yes Yes Yes Yes No No N/A Yes Yes Yes Availability

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Features

Table 21-1. UART Specifications (Contd)

Feature DMA Channels DMA Chaining Boot Capable Local Memory Max Clock Operation Availability 2 Yes No No fPCLK/16

Features
The UART converts data between serial and parallel formats. The serial format follows an asynchronous protocol that supports various word lengths, stop bits, and parity generation options. The UART primary features are listed below Figure 21-1 on page 21-6 shows the functional block. Compatible with the RS-232 and RS-485 Standards Data packing support for efficient memory usage Full duplex DMA operation Multiprocessor communication using 9 bit addressing Autobaud detection support The UART includes interrupt handling hardware The UARTs do not support MODEM functionality.

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UART Port Controller

SRU Programming
The SRU (signal routing unit) needs to be programmed in order to connect the UART signals to the output pins or connect the output of the transmitter to the receiver. The UART signals need to be routed as shown in Table 21-2. Table 21-2. UART SRU2 Signal Connections
UART0 Source UART0_TX_O UART0_TX_O UART0_TX_PBEN_O DPI Connection Group A Group B Group C UART0 Destination UART0_RX_I

Register Overview
The processor provides a set of PC-style, industry-standard control and status registers for the UART. These memory-mapped IOP registers are byte-wide registers that are mapped as half-words with the most significant byte zero-filled. Transmit Control Register (UART0TXCTL). Global control for TX core or DMA operation. Receive Control Register (UART0RXCTL). Global control for RX core or DMA operation. Line Control Register (UART0LCR). Controls the format of the data character frames. It selects word length, number of stop bits and parity. Divisor Latch High/Low Register (UART0DLL/UART0DLH). Characterize the UART bit rate. The divisor is split into the divisor latch low byte (UART0DLL) and the divisor latch high byte (UART0DLH).

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Clocking

Mode Control Register (UART0MODE). Controls packing and address modes. Interrupt Enable Control Register (UART0IER). Enables interrupt requests from system handling. Line Status Register (UART0LSR). Returns status of controls format of the data character frames as overrun or framing errors and break interrupts. Transmit Status Register (UART0TXSTAT). Returns status of DMA operation. Receive Status Register (UART0RXSTAT). Returns status of DMA operation and Rx errors. Interrupt Identification Status Register (UART0IIR). Provides status of all interrupts and combines them into one channel.

Clocking
The fundamental timing clock of the UART module is peripheral clock/16 (PCLK/16). The bit rate is characterized by the peripheral clock (PCLK) and the 16-bit divisor. The divisor is split into the UART divisor latch low byte register (UARTDLL) and the UART divisor latch high byte register (UARTDLH). These registers form a 16-bit divisor. The baud clock is divided by 16 so that: Divisor = 1 when UARTDLL = 1 UARTDLH = 0 Divisor = 65,535 when
UARTDLL

= UARTDLH = FF
UARTDLH UARTDLL

formed the and The 16-bit divisorresulting by the highest possible clock registers resets to 0x0001, in frequency by default. The UARTDLH and UARTDLL registers can be programmed by software before or after turning on the clock.

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UART Port Controller

Table 21-3 provides example divide factors required to support most standard baud rates. Table 21-3. UART Baud Rate Examples With 100 MHz PCLK
Baud Rate 2400 4800 9600 19200 38400 57600 115200 921,600 6,250,000 Divisor Latch Actual (DL) 2604 1302 651 326 163 109 54 7 1 2400.15 4800.31 9600.61 19,171.78 38,343.56 57,339.45 115,740.74 892,857.14 6,250,000 % Error 0.006 0.007 0.006 0.147 0.147 0.452 0.469 3.119

selection frequencies, even multiples Careful baud rates,ofcan result in lower that is,percentages. of desired error
PCLK

The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

Functional Description
The UART supports multiprocessor communication using 9-bit address detection. This allows the units to be used in multi-drop networks using the RS-485 data interface standard. The UART has its own set of control and status registers (Figure 21-1).

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Functional Description

UARTx_RX_I

RX SR

RX RBR

MASTER RX DMA

RX CONTROL

LINE CONTROL/ STATUS

BAUD GENERATOR

DIVISOR LATCH

UART DMA ARBITER/DATA MUX

PERIPHERAL CORE BUS

TX CONTROL

LINE CONTROL/ STATUS CORE INTERFACE

UARTx_TX_O

TX SR

TX RBR

MASTER TX DMA

Figure 21-1. UART Functional Block Diagram The UART is a DMA-capable peripheral with support for separate transmit and receive DMA master channels. It can be used in either DMA or core modes of operation. The core mode requires software management of the data flow using either interrupts or polling. The DMA method requires minimal software intervention as the DMA engine itself moves the data. For more information, see DMA Transfers on page 21-14. Either one of the peripheral timers can be used to provide a hardware-assisted autobaud detection mechanism for use with the UART. See the Autobaud Detection on page 21-21.

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IOD0 BUS

UART Port Controller

Serial Communication
The UART follows an asynchronous serial communication protocol with these options: 5 8 data bits 1 or 2 stop bits None, even, or odd parity Baud rate = PCLK/(16 divisor), divisor value can be from 1 to 65,536 All data words require a start bit and at least one stop bit. With the optional parity bit, this creates a 7 to 12-bit range for each word. The format of received and transmitted character frames is controlled by the line control register (UARTLCR). Data is always transmitted and received least significant bit (LSB) first. Figure 21-2 shows a typical physical bit stream measured on the transmit pin.
DATA BITS STOP BIT(S)

D0

D1

D2

D3

D4

D5

D6

D7

START BIT

LSB

PARITY BIT (OPTIONAL, ODD OR EVEN)

Figure 21-2. Bit Stream on the Transmit Pin Transmit and receive channels are both buffered. The UARTTHR register buffers the transmit shift register (UARTTSR) and the UARTRBR register buffers the receive shift register (UARTRSR). The shift registers are not directly accessible by software.

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Operating Modes

Operating Modes
The packed and unpacked UART operation modes are described in the following sections.

Data Packing/Unpacking
The UART provides packed and unpacked modes of data transfer to and from the internal memory of the processors. This mode is set using the UARTPACK bit (bit 0) in the UARTMODE register. In unpacked mode, the data word is appended to the left with 24 zeros during transmission or reception. In packed mode, two words of data are transmitted or received with their corresponding higher bytes filled with zeros. For example, consecutive data words 0xAB and 0xCD are packed as 0x00CD 00AB in the receiver, and 0x00CD 00AB is transmitted as two words of 0xAB and 0xCD successively from the transmitter. Packing is available in both I/O and DMA modes. A control bit, UARTPKSYN, can be used to re synchronize the packing. For information on using the UART for DMA transfers, see DMA Transfers on page 21-14. provided to use The packed feature isefficient manner. the internal memory of the processor in a more Note that in packed mode, both the transmitter and receiver operate with an even number of words. A transmit-buffer-empty or receive-buffer-full interrupt is generated only after an even number of words are transferred.

Programs must use care when using the packing feature in 9-bit mode.
Data Transfer Types
The UART is capable of transferring data using both the core and DMA. Note that data packing is available using both data transfer types. For

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UART Port Controller

more information, see Data Packing/Unpacking on page 21-8.

Serial Shift Registers

The UART contains two serial shift registers described below. Output Shift Register The data is moved to the internal transmit shift register (UARTTSR) where it is shifted out at a baud rate equal to PCLK/(16 Divisor) with start, stop, and parity bits appended as required. Input Shift Register The number of stop bits is always assumed to be 1. After detection of the start bit, the received word is shifted into the receive shift register (UARTRSR) at a baud rate of PCLK/(16 Divisor). After the appropriate number of bits (including stop bit) is received, the data are updated and the UARTRSR register is transferred to the UART receive buffer register (UARTRBR).

Buffers
The UART contains a single data buffer register for transmission and reception. These buffers are described in the following sections. Transmit Buffer A write to the UART transmit holding register (UARTTHR) initiates the transmit operation. All data words begin with a 1-to-0 transition start bit. This 32-bit write only register uses only 18 bits. The other bits are filled with zeros during writes. In no-pack mode (default), only the lower byte is usedall other bits are zero filled. Note that data is transmitted and received by the least significant bit (LSB) first followed by the most significant bits (MSBs).

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Data Transfer Types

Receive Buffer The receive operation uses the same data format as the transmit configuration, except that shown in Figure 21-4. After the transfer of the received word to the UARTRBR buffer and the appropriate synchronization delay, the data ready status flag (UARTDR) is updated. A sampling clock equal to 16 times the baud rate samples the data as close to the midpoint of the bit as possible. Because the internal sample clock may not exactly match the asynchronous receive data rate, the sampling point drifts from the center of each bit. The sampling point is synchronized again with each start bit, so the error accumulates only over the length of a single word. A receive filter removes spurious pulses of less than two times the sampling clock period. the destructive nature reading this register, a shadow Becauseisofprovided for reading theofcontents of the corresponding register main register. For more information, see Debug Features on page 21-24.

Buffer Status
The transfer of data from the UARTTHR register to the transmit shift register sets the transmit holding register empty status flag (UARTTHRE) in the UART line status register (UARTLSR). After the appropriate number of bits (including stop bit) is received, the status is updated in the UART line status register (UARTLSR).

Buffer Packing
In packing mode, both the high and low bytes are used (Figure 21-3 on page 21-11). This mode is set using the UARTPACK bit in the UARTMODE register. In unpacked mode, the data word is appended to the left with 24 zeros during transmission or reception.

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UART Port Controller

In packed mode, two words of data are transmitted or received with their corresponding higher bytes filled with zeros. For example, consecutive data words 0xAB and 0xCD are packed as 0x00CD 00AB in the receiver, and 0x00CD 00AB is transmitted as two words of 0xAB and 0xCD successively from the transmitter.
PKSYN,

Packing is available in both core and DMA modes. A control bit, UARTcan be used to re synchronize the packing. For information on using the UART for DMA transfers, see DMA Transfers on page 21-14. provided to use the internal memory the The packed feature isefficient manner. In packed mode, bothofthe processor in a more transmitter and receiver operate with an even number of words. A transmit-buffer-empty or receive-buffer-full interrupt is generated only after an even number of words are transferred.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Zero-Filled

Higher Byte (2316) TX9D1

15 14 13 12

11 10

Zero-Filled

Lower Byte (70) TX9D0

Figure 21-3. UART0 Transmit Holding Register (Packing Enabled)

9-Bit Transmission Mode

The TX9D bits are the ninth bit in 9-bit transmission mode. A write to the UART transmit holding register (UARTTHR) initiates the transmit operation and reads from this address return the UARTRBR register. To select 9-bit transmission mode in the transmitter, set the UARTTX9 bit in the UART0MODE register. The 9-bit data (TX9D + 1 byte) can be directly written to the UART0THR buffereither in packed or unpacked format. The UART

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Data Transfer Types

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

Zero-Filled

Higher Byte (2316) RX9D1

15 14 13 12

11 10

Zero-Filled

Lower Byte (70) RX9D0

Figure 21-4. UART0 Receive Buffer Register transmitter transmits the TX9D bit instead of the parity bit. During 9-bit transmission mode, the parity select controls and the word length select do not have any effect. For the receiver, set the UARTRX9 bit in the UART0MODE register. Set the address enable bit (UARTAEN) to enable address detection. If the received ninth bit is high, the received word is shifted from the RSR register to the UART_RBR buffer which generates an address detection interrupt. Read the UART0RBR buffer to find out if the device is being addressed. If the device is being addressed, the address enable (UARTAEN bit) should be cleared to allow further data and address bytes to be read into the receive buffer. In 9-bit mode, the address detect interrupt can be generated whenever the receiver gets an address word, irrespective of the packing mode. This helps programs respond to an address word immediately. The program is expected to take into account these features when using packed mode. 9-bit mode parity in During the detecttransmission reception mayhas to be calculatedthe software to errors. The be stopped when receiver receives another address which is different from its own.

Programs must use care when using the packing feature in 9-bit transmission mode.

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UART Port Controller

Flushing the Buffer

The UART receive and transmit buffers are flushed by disabling the UART receive and transmit ports.

Core Transfers
Core transfers move data to and from the UART by the processor core. To transmit a character, load it into the UART0THR register. Received data can be read from the UARTRBR register. The processor must write and read one character at time. To prevent any loss of data and misalignments of the serial data stream, the UART line status register (UARTLSR) provides two status flags for handshakingUART0THRE and UARTDR. The UART0THRE flag is set when the UART0THR register is ready for new data and cleared when the processor loads new data into the UART0THR register. Writing this register when it is not empty overwrites the register with the new value and the previous character is never transmitted. The UARTDR flag signals when new data is available in the UARTRBR register. This flag is cleared automatically when the processor reads from this register. Reading the UARTRBR register when it is not full returns the previously received value. When the UARTRBR register is not read in time, newly received data overwrites the UARTRBR register and the overrun (UARTOE) flag is set. With interrupts disabled, these status flags can be polled to determine when data is ready to move. Note that because polling can be processor-intensive, it is not typically used in real-time signal processing environments.

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Data Transfer Types

DMA Transfers
The UART interface support both standard and chained DMA. However, unlike the serial ports, programs cannot insert a TCB in an active chain using the UART. In the UART, separate receive and transmit DMA channels move data between the UART and memory. The software does not have to move data, it just has to set up the appropriate transfers either through normal DMA or DMA chaining. Software can write up to two words into the UART0THR register before enabling the UART clock. As soon as the UART DMA engine is enabled, those two words are sent. See also Functional Description on page 3-23. To perform DMA transfers, the UART has a special set of receive and transmit registers. These registers are listed in Standard DMA Parameter Registers on page 3-4. No additional buffering is provided in the UART DMA channel, so the latency requirements are the same as core transfers. However, the latency is determined by the bus activity and arbitration mechanism and not by the processor loading and interrupt priorities. DMA through the UART is started by setting up values in the DMA parameter registers and then writing to the transmit and receive control registers, enabling the module using the UARTEN bits (in the UART0TXCTL and UARTRXCTL registers) and enabling DMA using the UARTDEN bits. A DMA can be interrupted by resetting the UARTDEN bit in the control register. A DMA request that is already in the pipeline completes normally.

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UART Port Controller

UART DMA Group Priority The UART module has two DMA channels, one for reads and the second for writes. The two channels are grouped together. When both channels have data ready, the read channel always wins with fixed priority (which is the first arbitration stage). The winning channel requests the DMA bus arbiter to get control of the peripheral DMA bus (2nd stage of arbitration). The I/O processor considers the two DMA channels as a single group and therefore one arbitration request. For more information, see Peripheral DMA Arbitration on page 3-36. DMA Chaining DMA chaining is enabled by setting the UARTCHEN bit in the transmit and receive control registers. When chaining is enabled at the end of a current DMA, the next set of DMA parameters are loaded from internal memory and a new DMA starts. The index of the memory location is written in the chain pointer register. DMA parameter values reside in consecutive memory locations as shown in Table 3-17 on page 3-16. Chaining ends when the chain pointer register contains address 0x00000 for the next parameter block.

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Interrupts

Interrupts
Table 21-4 provides an overview of UART interrupts. Table 21-4. Overview of UART Interrupts
Default Programmable Interrupt DPII = P14I Sources Masking Service

DMA complete Core buffer service Address detection RX overrun error RX parity error RX frame error

DPI_IMASK_RE UART0IER

RTI instruction

ROC from UART0LSR + RTI instruction DMA: ROC from UART0RXSTAT + RTI instruction UART0IER

Separate UART0RXI and UART0TXI not connected by default

Sources
The UART0 module generates 10 local interrupts which are grouped into five system status, four error status and on3 transmit DMA interrupt. Nine signals are logically ORed into one UART0RXI output interrupt signal which is routed by default as a DPI interrupt into the core IVT address map. The transmit DMA signal is routed into the UART0TXI interrupt which is also routed by default as a DPI interrupt into the core IVT address map. two interrupt outputs The UART hasinterrupts. In core modereferred to as the and line the buffer service and
UART0RXI UART0TXI

status are mapped into the single UART0RXI interrupt.

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UART Port Controller

Separate interrupt lines are provided for error signals. Line error handling can be configured completely independently from the receive/transmit setup. The UART port can generate interrupts as described in the following sections. Core Buffer Service Request When DMA is disabled the processor core may read from the UARTTHR buffer or write to the UARTTHR buffer. An interrupt is generated when the receive buffer is full (UARTRBFIE) or transmit buffer is empty (UARTTBEIE). A transmitter empty interrupt is generated if both the TSR + THR registers (UARTTXFIE) are empty. Address Detection Generate a receive interrupt when an address is detected in 9-bit mode (UARTADI). DMA Complete For DMA, the transmit interrupt is generated when a DMA in transmit mode is complete whereas the receive interrupt is generated when a receive DMA is complete or when a receive error occurs. For information on using the UART for DMA transfers, see DMA Transfers on page 21-14, and Appendix 2, Interrupt Control. Chained DMA For chained DMA, if the PCI bit is cleared (= 0), the DMA complete interrupt is generated only after the entire chained DMA access is complete. If the PCI bit is set (= 1), then a DMA interrupt is generated for each TCB.

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Interrupts

Line Status Error The receive error interrupt is generated for the following cases. On a receive overrun error On a receive parity error On a receive framing error On a break error interrupt

Masking
The DPI signal is routed by default to a programmable interrupt. To service the DPI, unmask (set = 1) the P14I bit in the IMASK register. For the DPI system interrupt controller the DPI_IMASK_RE register must be unmasked. For example:
bit set IMASK P14I; ustat1=dm(DPI_IMASK_RE); bit set ustat1 UART0_TX_INT; dm(DPI_IMASK_RE)=ustat1; /* unmasks P14I interrupt */ /* set UART TX Int */

The separate UART0RXI and UART0TXI signals are not routed by default to programmable interrupt. To service the UART0TXI/UART0RXI, unmask (set = 1) any programmable interrupt bit in the IMASK/LIRPTL register. With the UART enabled (UARTEN bit, UART0TXCTL/UART0RXCTL) the UART line status interrupt is unmasked by setting UARTLSIE bit (UARTIER register). The UARTRBFIE and UARTTBEIE bits (UARTIER register) are set to enable core buffer service request in the register for When thetransfers, thebit is set module immediately issues core transmit UART an
UARTTBEIE UARTIER

interrupt.

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UART Port Controller

With UART DMA enabled (UARTDEN bit, UART0TXCTL/UART0RXCTL) the UART uses dedicated DMA channels for receive and transmit operations.

Service
The following sections describe interrupt servicing for the UART. when is The for the interrupt is automatically clearedfor DMA mode only , and read,
DPI_INT DPI_IRPTL MISCBxI UART0RXI UART0TXI

interrupts. Further, the UART0RXI interrupt for core mode must be cleared in the ISR by following the UART interrupt acknowledge mechanism (see IIR section). Core Buffer Service Request When initiating the transmission of a string, no special handling of the first character is required. Let the interrupt service routine (ISR) load the first character from memory and write it to the UARTTHR register in the normal manner. Accordingly, the UARTTBEIE bit should be cleared if the string transmission has completed. Alternatively, UART writes and reads can be accomplished by ISRs. Note that the UART0LSR status register should always be read before the receive buffer register (UART0RBR). Address detection (9 bit UART) can also generate the interrupt both in I/O and DMA modes. To check for the 9th bit being high, programs should read the UART0RBRSH (shadow) register. The UART interrupt identification register (UARTIIR) reflects the UART interrupt status (see Table 21-4) by bundling all UART0RXI interrupt sources to a single interrupt channel and servicing them all by the same software routine. The transmit interrupt request is cleared by writing new data to the UART0THR register or by reading the UART0IIR register. Please note the special role of the UARTIIR register read in the case where the service routine does not want to transmit further data. If software

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Effect Latency

stops transmission, it must read the UARTIIR register to reset the interrupt request. As long as the UARTIIR register reads receive service (0x04) or receive status line (0x06) indicating that another interrupt of higher priority is pending, the transmit service (0x01) latch cannot be cleared by reading the UARTIIR register. Errors The UART0LSR register reports the cause of the interrupt. The error interrupts can be determined by reading the UART0LSR status register. The bits causing the interrupt must be RW1C. The UART0RXSTAT register reports if the interrupt is due to receive DMA errors. The error interrupts can be determined by reading the UART0LSR status register. The bits causing the interrupt must be cleared through the RW1C operation. This clears the UARTERRIRQ bit in the UART0RXSTAT register.

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

UART Effect Latency

After the UART registers are configured the effect latency is 2 PCLK cycles. Note that when transmitting data the effective data on DPI pins cant be seen immediately after 2 PCLK cycles because the time which the UART takes to start driving data depends on the baud rate settings.

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UART Port Controller

Programming Model
The following sections provide some programming procedures for core and DMA data transfers. The UART allows mapping the interrupts via the DPI interrupt (default) or separately by programming UART0TXI and UART0RXI to any other programmable interrupt.

Autobaud Detection
When the baud rate of the incoming signal is not known, one of the general-purpose timers can be used in width capture mode to automatically calculate the baud rate. Do not enable the UART until the width is captured by the timer. To perform autobaud detection, use the following procedure. 1. The UART RX input signal is fed to a DPI pin buffer. This buffer is used as an input (DPI_PBENxx_I is low). The pin buffer output (DPI_PBxx_O) is routed to both inputs UART0RX_I and TIMERx_I. 2. Configure the timer in width capture mode with the timer interrupt enabled. Inside the ISR, the program should read the width of the incoming signal and disable the timer. 3. Send test data through the host device that can be used for calculating the baud rate of the incoming signal. A NULL character (0x00) can be used for this purpose. 4. The baud rate can be derived from the width of timer as follows: BAUDR = Width (8 (number of zero data bits + 1)). 5. When using a NULL character, the number of zero data bits is 8. Programs can also send some other pattern for this purpose. Once the baud rate is calculated inside the timer ISR, the UART can be programmed with the calculated baud rate.

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Programming Model

DMA Transfers
The following is the general procedure for transferring data using DMA. 1. Clear the global UARTTXCTL/UARTRXCTL register. 2. Configure the UART DMA parameter registers (index, modify and count). 3. Configure the UARTLCR, UARTDLL, UARTDLH, UARTIER, UARTSCR and UARTMODE registers (see the DLAB bit). 4. Enable the DMA by setting the UARTEN and DMAEN bits in the UARTTXCTL/ UARTRXCTL registers. Setting Up and Starting Chained DMA To start a chain pointer DMA use the following steps. 1. Clear the chain pointer register 2. Initialize the chain pointer register with the address of the DMA descriptor table. Set the PCI bit if an interrupt is needed at the end of each DMA block. 3. Set up the appropriate control register to enable the UART transmitter and receiver, chain pointer, and DMA (UARTDEN, UARTEN, UARTCHEN bits). Once chain pointer DMA is enabled, the DMA engine fetches the index, modify, count, and chain pointer values from the memory address specified in the chain pointer register. Once the DMA parameters are fetched, normal DMA starts. This process is continued until the chain pointer register contains all zeros.

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UART Port Controller

Notes on Using UART DMA The following should be noted when performing DMA through the UART. DMA can be interrupted by resetting the UARTDEN bit, but none of the other control settings should be changed. If the UART is enabled again, then interrupted DMA can be resumed by resetting the UARTDEN bit. Disabling the UART by resetting the enable UARTEN bit flushes data in the transmit/receive buffer. Resetting the UART during a DMA operation is prohibited and leads to data loss. Do not disable chaining (UARTCHEN bit) when a chaining DMA is in progress. During a receive DMA, a read of the receiver buffer (UARTRBR) is not allowed. If needed, programs should read the receiver shadow buffer (UARTRBRSH).

Core Transfers
The following is the general procedure for transferring data using the core. 1. Clear the global UARTTXCTL/UARTRXCTL registers. 2. Configure the UARTLCR, UARTDLL, UARTDLH, and UARTMODE registers (see the DLAB bit). 3. Program the UARTIER registers to generate interrupt when the transmit buffer is empty and / or the receive buffer is full. 4. Enable the UART by setting the UARTEN bit in the UARTTXCTL/ UARTRXCTL registers.

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Debug Features

5. Inside the ISR, check for the interrupt triggered and write to the transmit buffer in case of transmit buffer empty and read from the receive buffer in case of receive buffer fill event. 9-Bit Transmission and Packing Transfers Programs should write the UARTPKSYN bit (bit 1) with a 1 each time an address is received. This starts the reception of the following data from the lower half-word of the UARTRBR register. The address-detect interrupt is generated whenever the UART receiver receives an address, irrespective of the packing. The DR bit in the UARTLSR register can be used to discover whether the address is in the lower (DR = 0) or higher half-word (DR = 1). The LSR register must be read before reading the UARTRBR register, because the latter clears the DR bit. Reading the UARTRBR register clears both the address-detect and the data-ready interrupts. In non-packed mode, when the address-detect interrupt is generated, it means that the data is ready in the RBR buffer while in packed mode, this is not the case.

Debug Features
The following sections describe the debugging features available on the UART.

Shadow Registers
Because of the destructive nature of reading the following registers: interrupt identification (UARTIIR), line status (UARTLSR) and read buffer (UARTRBR) shadow registers are provided for reading the contents of the corresponding main registers. The shadow registers, (UARTIIRSH), (UARTLSRSH) and (UARTRBRSH) return exactly the same contents as the main register, but without changing the registers status in any way.

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UART Port Controller

Shadow Buffer
Because of the destructive nature of reading the read buffer (UART0RBR) a shadow buffer is provided. The shadow buffer (UART0RBRSH) returns exactly the same contents as the main buffer, but without changing the registers status in any way.

Shadow Interrupt Registers

For more information, see Debug Features on page 2-15.

Loopback Routing
The UART supports an internal loopback mode by using the SRU. For more information, see Loopback Routing on page 10-39.

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Debug Features

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22 TWO WIRE INTERFACE CONTROLLER

The two wire interface (TWI) controller allows a device to interface to an inter-IC bus as specified by Philips. The TWI is fully compatible with the widely used I2C bus standard. It is designed with a high level of functionality and is compatible with multi-master, multi-slave bus configurations. To preserve processor bandwidth, the TWI controller can be set up with transfer initiated interrupts to service FIFO buffer data reads and writes only. Protocol related interrupts are optional.The TWI specifications are shown in Table 22-1. Table 22-1. TWI Specifications
Feature Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing SRU2 DPI Required SRU2 DPI Default Routing Interrupt Control Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex Transmission Full Duplex Yes Yes No No N/A Yes Yes Yes Availability

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Features

Table 22-1. TWI Specifications (Contd)

Feature Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Boot Capable Local Memory Max Clock Operation Yes Yes No N/A N/A No No 400 kHz Availability

Features
The TWI is fully compatible with the widely used I2C bus standard. It was designed with a high level of functionality and is compatible with multimaster, multislave bus configurations. To preserve processor bandwidth, the TWI controller can be set up and a transfer initiated with interrupts only. This allows the processor to service FIFO buffer data reads and writes. Protocol-related interrupts are optional. The TWI master controller includes the features described in the list that follows. Simultaneous master and slave operation on multiple device systems Support for multimaster data arbitration Support for fast mode (400 KHz) 7-bit addressing 100K bits/second and 400K bits/second data rates

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General call address support Master clock synchronization and support for clock low extension Separate multiple-byte receive and transmit FIFOs Low interrupt rate Individual override control of data and clock lines in the event of a bus lockup Input filter for spike suppression The TWI moves 8-bit data externally while maintaining compliance with the I2C bus protocol.

Pin Descriptions
Table 22-2 shows the pins for the TWI. Two bidirectional pins externally interface the TWI controller to the I2C bus. The interface is simple and no other external connections or logic are required. Table 22-2. TWI Pins
Internal Node TWI_CLK_I TWI_DATA_I TWI_CLK_PBEN_O Type I I O Description TWI Clock Signal. Serial clock input. TWI Data Signal. Serial receive data input. TWI Clock Signal. This output signal is used to drive the TWI clock off chip Note since the TWI output signals must operate in open drain it should be routed to a DPI PBEN input. TWI Data Signal. This output signal is used to drive the TWI data off chip. Note that since the TWI output signals must operate in open drain it should be routed to a DPI PBEN input.

TWI_DATA_PBEN_O

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SRU Programming

SRU Programming
The TWI signals are available through the SRU2, and are routed as described in Table 22-3. Table 22-3. TWI DPI/SRU2 Signal Connections
TWI Source DPI Connection Group A TWI_CLK_PBEN_O TWI_DATA_PBEN_O Group C TWI Destination TWI_CLK_I TWI_DATA_I

Clocking
The fundamental timing clock of the TWI module is peripheral clock (PCLK). Serial clock frequencies can vary from 400 kHz to less than 20 kHz. The resolution of the generated clock is 1/10 MHz or 100 ns.
CLKDIV

= TWI_CLOCK period 10 MHz time reference

For example, for an TWI_CLOCK of 400 kHz (period = 1/400 kHz = 2500 ns) and an internal time reference of 10 MHz (period = 100 ns):
CLKDIV

= 2500 ns 100 ns = 25

For an TWI_CLOCK with a 30% duty cycle, then CLKLOW = 17 and CLKHI = 8. Note that CLKLOW and CLKHI add up to CLKDIV. The clock to this module may be shut off for power savings. For more information, see Disabling Peripheral Clocks on page 23-11.

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Two Wire Interface Controller

Register Overview
This section provides brief descriptions of the major registers. For complete information see Two Wire Interface Registers on page A-243. Slave Mode Control Register (TWISCTL). Controls the logic associated with slave mode operation. Settings in this register do not affect master mode operation and should not be modified to control master mode functionality. Slave Mode Status Register (TWISSTAT). During and at the conclusion of slave mode transfers, the TWISSTAT holds information on the current transfer. Generally, slave mode status bits are not associated with the generation of interrupts. Master mode operation does not affect slave mode status bits. Master Mode Control Register (TWIMCTL). Controls the logic associated with master mode operation. Bits in this register do not affect slave mode operation and should not be modified to control slave mode functionality. Master Mode Status Register (TWIMSTAT). Holds information during master mode transfers and at their conclusion. Generally, master mode status bits are not directly associated with the generation of interrupts but offer information on the current transfer. Slave mode operation does not affect master mode status bits. Control Timer Register (TWIMITR). Enables the TWI module and establishes a relationship between the peripheral clock (PCLK) and the TWI controllers internally-timed events. The internal time reference is derived from PCLK using the prescaled value shown below. PRESCALE = fPCLK/10 MHz Serial Clock Divider Register (TWIDIV). During master mode operation, the TWIDIV register values are used to create the high and low durations of the TWI_CLOCK. ADSP-214xx SHARC Processor Hardware Reference 22-5

Functional Description

FIFO Control Register (TWIFIFOCTL). The FIFO control register affects only the FIFO and is not tied in any way with master or slave mode operation. FIFO Status Register (TWIFIFOSTAT). The fields in the TWI FIFO status register indicate the state of the FIFO buffers receive and transmit contents. The FIFO buffers do not discriminate between master data and slave data. By using the status and control bits provided, the FIFO can be managed to allow simultaneous master and slave operation.

Functional Description
Figure 22-1 illustrates the overall architecture of the TWI controller. The peripheral interface supports the transfer of 32-bit wide data and is used by the processor in the support of register and FIFO buffer reads and writes. The register block contains all control and status bits and reflects what can be written or read as outlined by the programmers model. Status bits can be updated by their respective functional blocks. The FIFO buffer is configured as a 1-byte-wide, 2-deep transmit FIFO buffer and a 1-byte-wide, 2-deep receive FIFO buffer. The transmit shift register serially shifts its data out externally off chip. The output can be controlled to generate acknowledgements or it can be manually overwritten. The receive shift register receives its data serially from off chip. The receive shift register is 1 byte wide and data received can either be transferred to the FIFO buffer or used in an address comparison.

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Two Wire Interface Controller

TRANSMIT SHIFT REGISTER FIFO

TWI_DATA_PBEN_O (OPEN DRAIN)

ARBITRATION

RECEIVE SHIFT REGISTER PERIPHERAL CORE BUS

TWI_DATA_I

TWI INTERFACE ADDRESS COMPARE

PCLK PRESCALER IRQ REGISTERS CLOCK GENERATION TWI_CLK_I TWI_CLK_PBEN_O (OPEN DRAIN)

Figure 22-1. TWI Block Diagram The address compare block supports address comparison in the event the TWI controller module is accessed as a slave. The prescaler block must be programmed to generate a 10 MHz time reference relative to the peripheral clock. This time base is used for filtering data and timing events specified by the electrical parameters in the data sheet (see the I2C bus specification from Philips), as well as for TWI_CLOCK clock generation. The clock generation module is used to generate an external serial clock (TWI_CLOCK) when in master mode. It includes the logic necessary for synchronization in a multimaster clock configuration and clock stretching when configured in slave mode.

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Functional Description

The TWI controllers clock output follows these rules: 1. Once the clock high (CLKHI) count is complete, the serial clock output is driven low and the clock low (CLKLOW) count begins. 2. Once the clock low count is complete, the serial clock line is three-stated and the clock synchronization logic enters into a delay mode (shaded area) until the TWI_CLOCK line is detected at a logic 1 level. At this time, the clock high count begins. The TWI controller only issues a clock during master mode operation and only at the time a transfer has been initiated. If arbitration for the bus is lost, the serial clock output immediately three-states. If multiple clocks attempt to drive the serial clock line, the TWI controller synchronizes its clock with the other remaining clocks. This is illustrated in Figure 22-2.
HIGH COUNT TWI CONTROLLER CLOCK LOW COUNT

SECOND MASTER CLOCK

TWI_CLOCK RESULT

Figure 22-2. TWI Clock Synchronization The TWI controller follows the transfer protocol of the Philips I2C Bus Specification version 2.1 dated January 2000. A simple complete transfer is diagrammed in Figure 22-3.

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Two Wire Interface Controller

7-BIT ADDRESS

R/W

ACK

8-BIT DATA

ACK

S = START P = STOP ACK = ACKNOWLEDGE

Figure 22-3. Standard Data Transfer To better understand the mapping of TWI controller register contents to a basic transfer, Figure 22-4 details the same transfer as above noting the corresponding TWI controller bit names. In this illustration, the TWI controller successfully transmits one byte of data. The slave has acknowledged both address and data.
S MADDR[6:0] MDIR ACK XMITDATA8[7:0] ACK P

S = START P = STOP ACK = ACKNOWLEDGE

Figure 22-4. Data Transfer With Bit Illustration

Bus Arbitration
The TWI controller initiates a master mode transmission (TWIMEN) only when the bus is idle. If the bus is idle and two masters initiate a transfer, arbitration for the bus begins. This is illustrated in Figure 22-5. The TWI controller monitors the serial data bus (TWI_DATA) while the TWI_CLOCK is high. If TWI_DATA is determined to be an active logic 0 level while the internal TWI controllers data is a logic 1 level, the TWI controller has lost arbitration and ends generation of clock and data. Note that arbitration is performed not only at serial clock edges, but also during the entire time TWI_CLOCK is high.

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Functional Description

TWI_CLOCK (BUS)

TWI CONTROLLER DATA

SECOND MASTER DATA

TWI_DATA (BUS)

ARBITRATION LOST START

Figure 22-5. TWI Bus Arbitration

Start and Stop Conditions

Start and stop conditions involve serial data transitions while the serial clock is at logic 1 level. The TWI controller generates and recognizes these transitions. Typically, start and stop conditions occur at the beginning and at the conclusion of a transmission, with the exception of repeated start combined transfers, as shown in Figure 22-6.
TWI_CLOCK (BUS)

TWI_DATA (BUS)

START

STOP

Figure 22-6. TWI Start and Stop Conditions

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Two Wire Interface Controller

The TWI controllers special-case start and stop conditions include: TWI controller addressed as a slave-receiver If the master asserts a stop condition during the data phase of a transfer, the TWI controller concludes the transfer (TWISCOMP). TWI controller addressed as a slave-transmitter If the master asserts a stop condition during the data phase of a transfer, the TWI controller concludes the transfer (TWISCOMP) and indicates a slave transfer error (TWISERR). TWI controller as a master-transmitter or master-receiver If the stop bit is set during an active master transfer, the TWI controller issues a stop condition as soon as possible to avoid any error conditions (as if data transfer count had been reached).

Operating Modes
The following sections provide information on the operation modes of the interface.

General Call Addressing

The TWI controller always decodes and acknowledges a general call address if it is enabled as a slave (TWISEN) and if general call is enabled using the TWIGCE bit. General call addressing (0x00) is indicated by the setting of the GCALL bit, and by the nature of the transfer, the TWI controller is a slave-receiver. If the data associated with the transfer is to be not acknowledged (NAKed), the TWINAK bit can be set. If the TWI controller is to issue a general call as a master-transmitter, the appropriate address and transfer direction can be set along with loading transmit FIFO data.

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Data Transfer

Slave Mode Addressing

With the appropriate selection of 7-bit addressing using the TWISLEN bit, the corresponding number of address bits (SADDR) are referenced during the address phase of a transfer.

Master Mode Addressing

Whether enabled as a master-transmitter or master-receiver with 7-bit addressing using the TWIMLEN bit, the TWI master performs all addressing and data transfers as required. This includes generating the repeated start condition, re-transmission of the 7-bits of the first address byte, and acknowledgement and generation of a new transfer direction change (indicated by the TWIMLEN bit).

Fast Mode
Fast mode (400 kHz) uses essentially the same mechanics as standard mode (100 kHz). It is the electrical specifications and timing that are different. When fast mode is enabled using the TWIFAST bit, the following timings are modified to meet the electrical requirements. Serial data rise times before arbitration evaluation (tr) Stop condition setup time from serial clock to serial data (tSUSTO) Bus free time between a stop and start condition (tBUF)

Data Transfer
The TWI uses its transmit and receive buffers for data transfer (no DMA capability). These buffers are described in the following sections.

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Two Wire Interface Controller

Serial Shift Register

The TWI has both an input and output serial shifter which are described below. Output Shift Register The transmit shift register receives byte wide buffer data or register data (address) and serially shifts its data out externally off chip. The output can be controlled for generation of acknowledgements or can be manually over-written Input Shift Register The receive shift register receives its data serially from off chip. Internally the receive shift register is byte wide and data received can either be transferred to the buffer or used in an address comparison.

Buffers
The TWI has multiple receive and transmit data buffers for 8 and 16-bit data, which are described in the following sections. Each buffer is accessed independently of the other and can be accessed simultaneously. As an example, a write to the transmit buffer could occur at the same time a receive shift register writes to the receive buffer. 8-Bit Transmit Buffer The TWI 8-bit transmit FIFO register (TXTWI8) shown in Figure 22-7 holds an 8-bit data value written into the FIFO buffer. Transmit data is entered into the corresponding transmit buffer in a first-in, first-out order. Although peripheral bus writes are 32 bits, a write access to the TXTWI8 register adds only one transmit data byte to the FIFO buffer. With each access, the transmit status (TWITXS) field in the TWIFIFOSTAT register is

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Data Transfer

updated. If an access is performed while the FIFO buffer is full, the core waits until there is at least one byte space in the transmit FIFO buffer and then completes the write access.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XMTDATA8 (70) Transmit FIFO 8-Bit Data

Figure 22-7. 8-Bit Transmit FIFO Register 16-Bit Transmit Buffer The TWI 16-bit FIFO transmit register (TXTWI16) shown in Figure 22-8 holds a 16-bit data value written into the FIFO buffer. Although peripheral bus writes are 32 bits, a write access to the TXTWI16 register adds only two transmit data bytes to the FIFO buffer. To reduce interrupt output rates and peripheral bus access times, a double byte transfer data access can be performed. Two data bytes can be written, effectively filling the transmit FIFO buffer with a single access. The data is written in little-endian byte order where byte 0 is the first byte to be transferred and byte 1 is the second byte to be transferred. With each access, the transmit status (TWITXS) field in the TWIFIFOSTAT register is updated. If an access is performed while the FIFO buffer is not empty, the core waits until the FIFO buffer is completely empty and then completes the write access.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XMTDATA16 (158) Byte1Transmitted second

XMTDATA16 (70) Byte0Transmitted first

Figure 22-8. 16-Bit Transmit FIFO Register

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Two Wire Interface Controller

8-Bit Receive Buffer The TWI 8-bit FIFO receive register (RXTWI8) shown in Figure 22-9 holds an 8-bit data value read from the FIFO buffer. Receive data is read from the corresponding receive buffer in a first-in, first-out order. Although peripheral bus reads are 32 bits, a read access to the RXTWI8 register can only access one receive data byte from the FIFO buffer. With each access, the receive status (TWIRXS) field in the TWIFIFOSTAT register is updated. If an access is performed while the FIFO buffer is empty, the core waits until there is at least one byte in the receive FIFO buffer and then completes the read access.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RCVDATA8 (70) Receive FIFO 8-bit Data

Figure 22-9. 8-Bit Receive FIFO Register 16-Bit Receive Buffer The TWI 16-bit FIFO receive register (RXTWI16) shown in Figure 22-10 holds a 16-bit data value read from the FIFO buffer. Although peripheral bus reads are 32 bits, a read access to the RXTWI16 register can only access two receive data bytes from the FIFO buffer. To reduce interrupt output rates and peripheral bus access times, a double-byte receive data access can be performed. Two data bytes can be read, effectively emptying the receive FIFO buffer with a single access.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RCVDATA16(158) Byte1

RCVDATA16 (70) Byte0

Figure 22-10. 16-Bit Receive FIFO Register

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Data Transfer

The data is read in little-endian byte order where byte 0 is the first byte received and byte 1 is the second byte received.

Buffer Status
TAT

With each write access, the transmit status (TWITXS) field in the TWIFIFOSregister is updated. If an access is performed while the FIFO buffer is full, the core waits until there is at least one byte space in the transmit FIFO buffer and then completes the write access. With each read access, the receive status (TWIRXS) field in the TWIFIFOSTAT register is updated. If an access is performed while the FIFO buffer is empty, the core waits until there is at least one byte in the receive FIFO buffer and then completes the read access.

Buffer Error The master status register (TWIMSTAT) reports buffer writes/underflow errors (TWIWERR) or buffer read/overflow errors (TWIRERR). Flushing the Buffer The TWI RX/TX buffers are flushed only by setting the FIFOFLUSH bit. Buffer Hang Disable For more information, see Buffer Hang Disable on page 22-16.

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Interrupts
Table 22-4 provides an overview of TWI interrupts. Table 22-4. Overview of TWI Interrupts
Default Programmable Sources Interrupt DPII = P14I Separate TWII not connected by default Master TX complete Master buffer service Slave initiative Slave complete Master error Slave error Slave overflow Masking DPI_IMASK_RE TWIIMASK TWIIMASK Service RW1C to TWIIRPTL + RTI instruction

Sources
The TWI module generates eight local interrupts which are grouped into five system status and three error status interrupts. All eight signals are logically ORed into one TWI output interrupt signal which is routed by default as a DPI interrupt into the core IVT address map. The TWI port generates interrupts as described in the following sections. Slave Status Transfer initiate or transfer complete. Master Status Transfer complete or TX/RX buffer service. Error Transfer error or transfer overflow.

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Interrupts

Masking
The DPI signal is routed by default to programmable interrupt. To service the DPI, unmask (set = 1) the P14I bit in the IMASK register. For DPI system interrupt controller the DPI_IMASK_RE register must be unmasked. For example:
bit set IMASK P14I; ustat1=dm(DPI_IMASK_RE); bit set ustat1 TWI_INT; dm(DPI_IMASK_RE)=ustat1; /* unmasks P14I interrupt */ /* set TWI Int */

The separate TWII signal is not routed by default to programmable interrupts. To service the TWII, unmask (set = 1) any programmable interrupt bit in the IMASK/LIRPTL register. The local interrupts can be unmasked by setting the corresponding bits in TWIIMASK register.

Service
For the default DPI interrupt, reading the DPI_IRPTL register for a TWI service request does not clear the request. Instead, the ISR must first read the TWIIRPTL register to identify the root cause and write 1 to that bit to clear the request as shown in Listing 22-1.

The is readinterrupt is automatically cleared when the for DMA , and register for the
DPI_INT MISCBxI UART0TXI UART0RXI

DPI_IRPTL

mode only interrupts. The TWI interrupt must be cleared in the ISR by following the TWI interrupt acknowledge mechanism. For more information, see Interrupt Latch Register (TWIIRPTL) on page A-256.

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Listing 22-1. Clearing Transmit Buffer Interrupt

TWI_ISR: ustat1 = dm(TWIIRPTL); bit TST ustat1 TWITXINT; IF TF jump TX_BUF; TX_BUF: dm(TWIIRPTL) = ustat1; r0=dm(TWIMCTL); instruction; rti; /* RW1C to clear TWI TX buffer interrupt */ /* dummy read*/ /* read IRPTL to identify cause*/ /* test TX buffer bit*/

Effect Latency
The total effect latency is a combination of the write effect latency (core access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming Reference.

TWI Effect Latency

After the TWI registers are configured the effect latency is 1.5 PCLK cycles minimum and 2 PCLK cycles maximum.

Programming Model
The following sections include information for general setup, slave mode, and master mode, as well as guidance for repeated start conditions.

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Programming Model

General Setup
General setup refers to register writes that are required for both slave mode and master mode operation. General setup should be performed before either the master or slave enable bits are set. Programs should enable the TWI controller through the TWIMITR register and set the prescale value. Program the prescale value to the binary representation of fPCLK/10 MHz. All values should be rounded up to the next whole number. The TWIEN enable bit must be set. Note that once the TWI controller is enabled, a bus busy condition may be detected.

SRU Programming Mode

Since the TWI data/clock output requires open drain connectivity following SRU programming is required regardless of master/slave mode: Listing 22-2. TWI Pin Routing
SRU(LOW, DPI_PBxx_I); SRU(TWI_DATA_PBEN_O, DPI_PBENxx_I); SRU(DPI_PBxx_O, TWI_DATA_I); /* input buffer is low */ /* TWI data output*/ /* TWI data input */

Listing 22-3. TWI Clock Pin Routing

SRU2(LOW, DPI_PByy_I); SRU2(TWI_CLK_PBEN_O, DPI_PBENyy_I); SRU2(DPI_PByy_O, TWI_CLK_I); /* input buffer is low */ /* TWI clock output*/ /* TWI clock input*/

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Slave Mode
When enabled, slave mode supports both receive and transmit data transfers. It is not possible to enable only one data transfer direction and not acknowledge (NAK) the other. This is reflected in the following setup. 1. Program the TWISADDR register. The appropriate 7 bits are used in determining a match during the address phase of the transfer. 2. Program the TXTWI8 or TXTWI16 register. These are the initial data values to be transmitted in the event the slave is addressed as a transmitter. This is an optional step. If no data is written and the slave is addressed and a transmit is required, the TWI clock is stretched and an interrupt is generated. 3. Program the TWIFIFOCTL register. Indicate if transmit (or receive) FIFO buffer interrupts should occur with each byte transmitted (received) or with each 2 bytes transmitted (received). 4. Program the TWIIMASK register. Enable bits associated with the desired interrupt sources. As an example, programming the value 0x000F results in an interrupt output to the processor when a valid address match is detected, a valid slave transfer completes, a slave transfer has an error, or a subsequent transfer has begun but the previous transfer has not been serviced. 5. Program the TWISCTL register. This prepares and enables slave mode operation. As an example, programming the value 0x0005 enables slave mode operation, requires 7-bit addressing, and indicates that data in the transmit FIFO buffer is intended for slave mode transmission.

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Programming Model

Table 22-5 shows what the interaction between the TWI controller and the processor might look like when the slave is addressed as a receiver. Table 22-5. Slave Mode Setup Interaction (Slave Addressed as Receiver)
TWI Controller Master Processor Interrupt: TWISINIT Slave transfer has been Change on the next sides always. initiated. Interrupt Acknowledge: RW1C the TWIIRPTL register. Interrupt: TWIRXS Receive buffer has 1 or 2 Read receive FIFO buffer. bytes (according to TWIRXINT). Change on the next sides always. Interrupt Acknowledge: RW1C the TWIIRPTL register ... Interrupt: TWISCOMP Slave transfer complete. ... Read receive FIFO buffer. Acknowledge: Clear interrupt source bits.

Master Mode Clock Setup

Master mode operation is set up and executed on a per-transfer basis. An example of programming steps for a receive and for a transmit are given separately in following sections. The clock setup programming step listed here is common to both transfer types. Program the TWIDIV register. This defines the clock high duration and clock low duration.

Master Mode Transmit

Follow these programming steps for a single master mode transmit: 1. Program the TWIMADDR register. This defines the address transmitted during the address phase of the transfer.

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Two Wire Interface Controller

2. Program the TXTWI8 or TXTWI16 registers. This is the initial data transmitted. It is considered an error to complete the address phase of the transfer and not have data available in the transmit FIFO buffer. 3. Program the TWIFIFOCTL register. Indicate if transmit FIFO buffer interrupts should occur with each byte transmitted (8 bits) or with each 2 bytes transmitted (16 bits). 4. Program the TWIIMASK register. Enable the bits associated with the desired interrupt sources. For example, programming the value 0x0030 results in an interrupt output to the processor when the master transfer completes, or if a master transfer error has occurred. 5. Program the TWIMCTL register. This prepares and enables master mode operation. As an example, programming the value 0x0201 enables master mode operation, generates a 7-bit address, sets the direction to master-transmit, uses standard mode timing, and transmits 8 data bytes before generating a stop condition. Table 22-6 shows what the interaction between the TWI controller and the processor might look like using this example. Table 22-6. Master Mode Transmit Setup Interaction
TWI Controller Master Interrupt: TWITXINT Transmit buffer has 1 or 2 bytes empty (according to XMTINTLEN). ... Interrupt: TWIMCOM Master transfer complete. Processor Write transmit FIFO buffer. Change on the next sides always. Interrupt Acknowledge: RW1C the TWIIRPTL register. ... Change on the next sides always. Interrupt Acknowledge: RW1C the TWIIRPTL register

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Programming Model

Master Mode Receive

Follow these programming steps for a single master mode transmit: 1. Program the TWIMADDR register. This defines the address transmitted during the address phase of the transfer. 2. Program the TWIFIFOCTL register. Indicate if receive FIFO buffer interrupts should occur with each byte received (8 bits) or with each 2 bytes received (16 bits). 3. Program the TWIIMASK register. Enable bits associated with the desired interrupt sources. For example, programming the value 0x0030 results in an interrupt output to the processor in the event that the master transfer completes, and the master transfer has an error. 4. Program the TWIMCTL register. Ultimately this prepares and enables master mode operation. As an example, programming the value 0x0201 enables master mode operation, generates a 7-bit address, sets the direction to master-receive, uses standard mode timing, and receives 8 data bytes before generating a stop condition. Table 22-7 shows what the interaction between the TWI controller and the processor might look like using this example. Table 22-7. Master Mode Receive Setup Interaction
TWI Controller Master Interrupt: TWIRXINT Receive buffer has 1 or 2 bytes (according to RCVINTLEN). ... Interrupt: TWIMCOM Master transfer complete. Processor Read receive FIFO buffer. Change on the next sides always. Interrupt Acknowledge: RW1C the TWIIRPTL register. ... Read receive FIFO buffer. Change on the next sides always. Interrupt Acknowledge: RW1C the TWIIRPTL register.

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Repeated Start Condition

In general, a repeated start condition is the absence of a stop condition between two transfers initiated by the same master. The two transfers can be of any direction type. Examples include a transmit followed by a receive, or a receive followed by a transmit. During a repeated start transfer, each interrupt must be serviced correctly to avoid errors. The following sections are intended to assist the programmer with service routine development. Transmit/Receive Repeated Start Sequence Figure 22-11 illustrates a repeated start data transmit followed by a data receive sequence.
S 7-BIT ADDRESS ACK 8-BIT DATA ACK S 7-BIT ADDRESS ACK 8-BIT DATA ACK P

TWITXINT INTERRUPT TWIMCOM INTERRUPT

TWIRXINT INTERRUPT TWIMCOM INTERRUPT

Figure 22-11. Transmit/Receive Data Repeated Start The tasks performed at each interrupt are: interrupt Generated every time the transmit FIFO has one or two byte locations available to be written. To service this interrupt, write a byte or word into the transmit FIFO registers (TXTWI8 or TXTWI16). During one of these interrupts (preferably the first time), do the following:
TWITXINT

Set the TWIRSTART bit (or earlier when TWIMCTL register is programmed first). Set the TWIMDIR bit to indicate the next transfer direction is receive. This should be done before the addressing phase of the next transfer begins.

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Programming Model

interrupt Generated because all data has been transferred (DCNT = 0). If no errors occur, a start condition is initiated. At this time, program the following bits of TWI_MASTER_CTRL register:
TWIMCOM

Clear TWIRSTART (if this is the last transfer). Re-program DCNT with the desired number of bytes to receive. interrupt Generated due to the arrival of a byte into the receive FIFO. Simple data handling is all that is required.
TWIRXINT TWIMCOM

interrupt Transfer is complete.

Receive/Transmit Repeated Start Sequence Figure 22-12 illustrates a repeated start data receive followed by a data transmit sequence. The shading indicates the slave has the bus.
S 7-BIT ADDRESS ACK 8-BIT DATA ACK S 7-BIT ADDRESS ACK 8-BIT DATA ACK P

TWIRXINT INTERRUPT TWIMCOM INTERRUPT

TWITXINT INTERRUPT TWIMCOM INTERRUPT

Figure 22-12. Receive/Transmit Data Repeated Start The tasks performed at each interrupt are:
TWIRXINT

interrupt

This interrupt is generated due to the arrival of one or two data bytes into the receive FIFO. The TWIRSTART bit should be set at this time (or earlier) and TWIMDIR should be cleared to reflect the change in direction of the next transfer. The TWIMDIR bit must be cleared before the addressing phase of the subsequent transfer begins.

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TWIMCOM

interrupt

This interrupt has occurred due to the completion of the data receive transfer. At this time the data transmit transfer begins. The TWIDCNT field should be set to reflect the number of bytes to be transmitted. Clear the TWIRSTART bit if this is the last transfer.
TWITXINT

interrupt

This interrupt is generated when there is one or two bytes of empty space in the FIFO. Simple data handling is all that is required.
TWIMCOM

interrupt

The transfer is complete.

Electrical Specifications
All logic complies with the electrical specification outlined in the Philips I2C Bus Specification version 2.1 dated January, 2000.

Debug Features
The following section provides information on debugging features available with the TWI.

Buffer Hang Disable

To support debugging buffer transfers, the processors have a buffer hang disable (BHD) bit in the TWIFIFOCTL register. When set (=1), this bit prevents the processor core from detecting a buffer-related stall condition, permitting debugging of this type of stall condition. For more information, see Buffer Hang Disable (BHD) on page 11-64.

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Debug Features

Shadow Interrupt Registers

For more information, see Debug Features on page 2-15.

Loopback Routing
The controller supports an internal loopback mode by using the SRU. For more information, see Loopback Routing on page 10-39.

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23 POWER MANAGEMENT

This chapter describes how to control the power use of the SHARC by controlling the clocks that run each peripheral.

Features
The following list describes the power management features. The PLL has various multiplier and divisor settings to generate a flexible core clock. Allows changes to the output clock during runtime.
RESETOUT

pin can be used for boot handshake or as a debug aid.

Resetting the PLL is possible without performing a new power-up sequence. Power savings controls the shut-down of individual clocks to peripherals. For information on which peripherals are enable after reset, see Peripherals Enabled by Default on page 23-10.

Register Overview
Power Management Control Register (PMCTL). Governs the operation of the PLL and configures the PLL settings. Power Management Control Register 1 (PMCTL1). This register controls the various peripherals clocks. ADSP-214xx SHARC Processor Hardware Reference 23-1

Phase-Locked Loop (PLL)

Phase-Locked Loop (PLL)

The following sections describe the clocking system of the SHARC processor. This information is critical to ensure designs that work correctly and efficiently.

Functional Description
To provide the clock generation for the core and system, the processor uses an analog PLL with programmable state machine control. The PLL design serves a wide range of applications. It emphasizes embedded applications and low cost for general-purpose processors, in which performance, flexibility, and control of power dissipation are key features. This broad range of applications requires a range of frequencies for the clock generation circuitry. The input clock may be a crystal, an oscillator, or a buffered, shaped clock derived from an external system clock oscillator. The clock system is shown in Figure 23-1.

CLKIN PRE DIVIDER INDIV BIT

INPUT CLOCK DIVIDER

PHASE DETECT

LOOP FILTER

CCLK VCO PCLK OUTPUT SDCLK/ CLOCK GENERATOR DDR2CLK POST MLBCLK DIVIDER LCLK

DIVIDER

PLLM BIT OR CLK_CFG1-0 BYPASS PLLD + PERIPHERAL DIVIDER BITS CLOCK SELECTION

Figure 23-1. Clocking System Subject to the maximum VCO frequency, the PLL supports a wide range of multiplier ratios of the input clock, CLKIN. To achieve this wide

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Power Management

multiplication range, the processor uses a combination of programmable multipliers in the PLL feedback circuit and output configuration blocks. The processor uses an on-chip, phase-locked loop (PLL) to generate its internal clock, which is a multiple of the CLKIN frequency. The PLL requires some time to achieve phase lock and CLKIN must be valid for a minimum time period during reset before the RESET signal can be deasserted. external crystal use, For information on minimum clock setup,for a detailed diagramand frequency, and range for any given
CLKIN

along with specific equations on the derivation of VCO frequency with reference to CLKIN, see the appropriate product data sheet.

PLL Input Clock

If an external clock oscillator is used, it should NOT drive the CLKIN pin when the processor is not powered. The clock must be driven immediately after power-up; otherwise, internal gates stay in an undefined (hot) state and can draw excess current. After power-up, allow sufficient time for the oscillator to start up, reach full amplitude, and deliver a stable CLKIN signal to the processor before the reset is released. This may take several milliseconds and depends on the choice of crystal, operating frequency, loop gain and capacitor ratios. For details on timing, refer to the appropriate product data sheet.

Pre-Divider Input
This unit divides the PLL input clock by 2 if enabled (using the INDIV bit). The pre-divider input is part of the PLL loop, therefore, if a program changes the PLL input clock (affecting the VCO frequency), the PLL must be put in bypass mode before the change can take effect. This is described in Bypass Mode on page 23-7.

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Phase-Locked Loop (PLL)

PLL Multiplier
The PLL multiplier bits are used to divide the VCO clock down to the CLKIN input (see Figure 23-1). The multiplier settings are controlled by hardware or software and based on the PLL multiplier settings below. Hardwarethrough the clock configuration pins (CLK_CFG10) Softwarethe hardware settings are overridden through the PLLM bits PLLM Hardware Control On power-up, the CLK_CFG10 pins are used to select core to CLKIN ratios which cannot be changed during runtime. After booting however, numerous other ratios (slowing or speeding up the clock) can be selected through software control. For information on the internal clock to CLKIN frequency ratios supported by the various processors, see the product specific data sheet. PLLM Software Control Programs control the PLL through the PMCTL register. The PLL multiplier (PLLM) bits can be configured to set a multiplier range of 0 to 63. This allows the PLL to be programmed dynamically in software to achieve a higher or slower core instruction rate depending on a particular systems requirements. The reset value of the PLLM bits is derived from the CLK_CFG10 pin multiply ratio settings. This value can be reprogrammed in the boot kernel to take effect immediately after start- up.

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PLL VCO
The VCO is the output stage of the PLL. It feeds the output clock generator which provides core and peripheral clocks as shown in Table 23-1. Two settings have an impact on the VCO frequency: The INDIV bit enables the CLKIN input pre-divider by 2. The PLLM bits and the CLK_CFG10 pins control the PLL multiplier unit. Changing the VCO frequency requires a new condition for the PLL circuitry. Therefore, the core needs to wait a specific settling time in bypass mode before it can be released for further activities (typically 4096 CLKIN cycles). Table 23-1. VCO Encodings
VCO Frequency1 PLLM Bit Settings 0 1 2 N = 362 63 1 INDIV = 0 128x 2x 4x 2Nx 126x INDIV = 1 64x 1x 2x Nx 63x

For operational limits for the VCO clock see the appropriate product data sheet.

Output Clock Generator

The output clock generator post-divides the VCO clock to the core ratio or peripherals ratio and synchronizes all output clocks. It is fed with the VCO clock and does not provide any feedback back to the PLL circuit.

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Phase-Locked Loop (PLL)

If the DIVEN bit is set, new post divider ratios are picked up on the fly and the clocks smoothly transition to their new values within 14 core clock (CCLK) cycles. divider ratio Postrequire bypasschanges ( not mode.
PLLD, DDR2CKR, SDCKR

and LCKR bits) do

The output clock generator block also controls bypass mode. For a description of the PMCTL bits, see Power Management Registers (PMCTL, PMCTL1) on page A-7. Core Clock (CCLK) The PLLD bits define the VCO output clock to core clock ratio to build the processor core clock (CCLK). The post divider can be changed any time and new division ratios are implemented on the fly. IOP Clock (PCLK) The peripheral clock is derived from the core clock with a fixed post divisor of 2. This clock is the master clock for most peripherals including the I/O processor (IOP). Peripheral Clocks (SDRAM/DDR2/Link Port) The SDRAM, DDR2, and link port derive their clocks directly from the core clock. These peripherals have a default divider (refer to PMCTL register). The DIVEN bit needs to be set whenever there is a change from the default ratio (similar to core PLLD bits).

Default PLL Hardware Settings

Table 23-2 demonstrates the internal core clock switching frequency across a range of CLKIN frequencies for the ADSP-2146x processor. The minimum operational range for any given frequency may be constrained by the operating range of the phase-locked loop. Note that the goal in 23-6 ADSP-214xx SHARC Processor Hardware Reference

Power Management

selecting a particular clock ratio for an application is to provide the highest permissible internal frequency for a given CLKIN frequency. For more information on available clock rates, see the appropriate product data sheet. Table 23-2. Selecting Core to CLKIN Ratio (ADSP-2146x)
Typical Crystal and Clock Oscillators Inputs 12.500 Clock Ratios (CLK_CFG Pins) 6:12 16:1 32:1 1 2 N/A 200 400 100 266.66 N/A 16.667 25.000 33.333 40.000 50.000

Core CLK (MHz)1 150 400 N/A 200 N/A N/A 240 N/A N/A 300 N/A N/A

For operational limits for the core clock frequency see the appropriate product data sheet. For ADSP-2147x and ADSP-2148x models, the ratio is 8:1.

needs ensure that the the core clock The applicationbootingtoare not exceeded.limits isofachieved by variafrequency after This tion of the CLK_CFG pins or the CLKIN signal.

Operating Modes
The following sections provide information on the various options for clock operation.

Bypass Mode
Bypass mode must be used if any runtime VCO clock change is required. Setting the PLLBP bit bypasses the entire PLL circuitry. In bypass mode, the core runs at CLKIN speed. Once the PLL has settled into the new VCO frequency, (which may take 4096 CLKIN cycles) the PLLBP bit may be

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Power-Up Sequence

cleared to release the core from bypass mode. For more information, see Back to Back Bypass on page 23-17. changes require bypass mode, Only VCO frequency as a standard operating mode. therefore this mode is not intended

Normal Mode
The normal mode is the regular mode and is effective if the PLLBP bit is cleared. In normal mode the PLL has locked and multiplies CLKIN to the desired VCO clock. The output clock generator post-divides and provides the clock tree to the I/O. frequency can happen The change of PLLduring operation). at any time (for example after power-up or

Clocking Golden Rules

The five rules below should be followed to ensure proper processor operation. 1. After power-up the CLK_CFG pins should not exceed the maximum core speed. 2. Software should guarantee minimum/maximum CCLK speed. 3. Software should guarantee maximum VCO clock speed. 4. Bypass requires 4096 CLKIN cycles. 5. Post-divider changes require 14 CCLK cycles.

Power-Up Sequence
The proper power-up sequence is critical to correct processor operation as described in the following sections.

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PLL Start-Up
Before the PLL can start settling, the RESET signal should be asserted for several micro-seconds under the following conditions. For PLL information, see the appropriate product data sheet. Valid and stable core voltage (VDDINT) Valid and stable I/O voltage (VDDEXT and VDD_DDR2) Valid and stable clock input (CLKIN) The chip reset circuit is shown in Figure 23-2. The PLL needs time to lock to the CLKIN frequency before the core can execute or begin the boot process. A delayed core reset signal (RESETOUT) is triggered by a 12-bit counter after RESET transitions from low to high (approximately 400 s for minimum CLKIN). The delay circuit is activated at the same time the PLL is triggered for settling after reset is deasserted.
RESET CLKIN
PLL_RESET CLKIN

Core Reset Delay Circuit

ENA_CNT CLKIN CORE_RST

PLL

12-bit Counter Count 4096 CLKIN Cycles

Delayed Internal Core Processor Reset

RESETOUT

Figure 23-2. Chip Reset Circuit After the external processor RESET signal is deasserted, the PLL starts settling. The rest of the chip is held in reset for 4096 CLKIN cycles after RESET is deasserted by an internal reset signal.

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Power-Up Sequence

advantage delayed that The number of of the without core reset ispower the PLL can be reset any times having to down the system. If there is a brownout situation, the external watchdog circuit only has to control the RESET signal. For more information on device power-up, see the appropriate product data sheet.

Peripherals Enabled by Default

When the processor is powered up the SDRAM, DDR2, S/PDIF receiver and real time clock controllers are enabled and all other peripherals disabled. If the any of the default peripherals is not to be used they can be disabled by following the steps in the sections below. SDRAM Controller After reset is de-asserted the SDCLK output is enabled by default. If the SDRAM interface is not used, the following bit should be configured. In the SDCTL register, set (=1) the DSDCTL bit to disable the controller and its I/O pads. DDR2 Controller After reset is de-asserted the DDR2CLK output is enabled by default. If the DDR2 interface is not used, the following bits should be configured. 1. In the DDR2CTL0 register, set (=1) the DIS_DDR2CTL, DIS_DDR2CLK1 and DIS_DDR2CKE bits to disable the controller and its clocks. 2. In the DDR2PADCTL0 register (bits 9, 19 and 29) and DDR2PADCTL1 register (bits 9 and 19), set (=1) all the PWD bits to power-down the pad receivers.

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Power Management

S/PDIF RX Controller If the receiver is not used, programs should disable the receiver and its digital PLL to avoid unnecessary switching. This is accomplished by setting the DIR_RESET bit in the DIRCTL register. Real-Time Clock Controller There is no way to disable the RTC counters from software. If a given system does not require the RTC functionality, then it may be disabled with hardware tie-offs. Tie the RTXI pin to EGND, tie the RTCVDD pin to EVDD, and leave the RTXO pin unconnected. The RTC_INIT register is provided to power down the RTC. Power-down is interpreted as a crystal oscillator disable, which reduces I/O power dissipation to only leakage current by setting the RTC_PWD bit. Furthermore the bus logic and its level shifters between the core and I/O voltage domain can be disabled to further reduce leakage by setting RTC_BUSDIS bit. Once set or reset, this mode retains its value unless changed, irrespective of the status of core supply.

Disabling Peripheral Clocks

The PMCTL1 register (Table A-4 on page A-11) provides bits which are used to disable the individual clocks to the peripherals. Note that all clocks are enabled by default.

Routing Units
In DAI Default Routing on page 10-24 and DPI Default Routing on page 10-27 the default routing scheme after reset are listed. Programs should check if all unused inputs are tied high or low. For example the DAI pin 1 which has many default connections.

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Power-Up Sequence

Packages Without an External Port For reduced package sizes (88 and 100 lead) without external port connectivity it is recommended to disable the external port clock as soon as possible (since it is enabled by default) by setting the EPOFF bit in PMCTL1 register.

Example for Clock Management

The following example shows a method for using the power saving features in the SHARC processors for the SPI.
ustat2 = dm(PMCTL1); bit set ustat2 SPIOFF; /* disable internal peripheral clock for SPI module. */ dm(PMCTL1) = ustat2;

General Notes on Power Savings

The following are some additional methods for reducing power. The lower the operation frequency, the lower the power consumption. The core and peripherals should be operated at the lowest frequency that meets the system's requirements. Active power is proportional to the processor's core clock frequency. Reducing the case temperature lowers leakage power. Leakage power increases exponentially to junction temperature. For core pauses programs should execute the IDLE instruction. Note that an interrupt is required to release the processor from IDLE. Dont leave input pins floating. In some cases leakage draws current in the region of milliamps. For more information, consult the product specific data sheet. If an external resistor is problematic, change the input to an output if possible (flag input).

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Power Management

Programming Models
For SDRAM programming models (AMI, SDRAM, DDR2), see Programming Models on page 4-150.

Post Divider
Use the following procedure and the example shown in Listing 23-1 to program or reconfigure the divider. 1. Disable any peripheral (configured with PCLK=CCLK/2). Note that the peripherals cannot be enabled when changing VCO to core clock ratio. 2. Select the PLLD divider by setting the PLLD bits (67) in the PMCTL register and enable the DIVEN bit. 3. Wait 15 CCLK cycles. During this time, the new divisor ratios are picked up on the fly and the clocks smoothly transition to their new values after a maximum of 14 core clock CCLK cycles. 4. Re-enable the peripherals. Listing 23-1. Post Divider
ustat2 = dm(PMCTL); bit clr ustat2 PLLBP; bit set ustat2 DIVEN|PLLD4; dm(PMCTL) = ustat2; lcntr = 15, do wait until lce; wait: nop; /* bypass disabled*/ /* set and enable post divisor */

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Programming Models

Multiplier and Post Divider Programming Model

There are two allowable procedures to program the VCO. The first method is shown in Listing 23-2. 1. Set the PLL multiplier and divisor value and enable the divisor by setting the DIVEN bit. 2. After one core clock cycle, place the PLL in bypass mode by setting (= 1) the PLLBP bit. Clear the DIVEN bit while placing the PLL into bypass mode. 3. Wait in bypass mode until the PLL locks (4096 CLKIN cycles). 4. Take the PLL out of bypass mode by clearing (= 0) the bypass bit. Clear the DIVEN bit while taking the PLL out of bypass mode. 5. Wait 15 core cycles before next activity. The second method is described below and shown in Listing 23-3. 1. Set the PLL multiplier and divisor values and place the PLL in bypass mode by setting the PLLBP bit. 2. Wait in the bypass mode until the PLL locks (4096 CLKIN cycles). 3. Take the PLL out of bypass mode by clearing the bypass bit. 4. Wait for one core clock cycle. 5. Enable the divisor by setting the DIVEN bit. 6. Wait 15 core cycles before next activity.

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Listing 23-2. VCO Programming: First Method

ustat2 = dm(PMCTL); bit clr ustat2 PLLM63|PLLD16; /* Clear the old multiplier and divider values */ bit set ustat2 DIVEN | PLLD4 |PLLM16; dm(PMCTL) = ustat2; bit set ustat2 PLLBP; bit clr ustat2 DIVEN; dm(PMCTL) = ustat2; waiting_loop: r0 = 4096; /* wait for PLL to lock at new rate (requirement for VCO change) */ lcntr = r0, do pllwait until lce; pllwait: nop; ustat2 = dm(PMCTL); /* Reading the PMCTL register value returns the DIVEN bit value as zero */ bit clr ustat2 PLLBP; dm(PMCTL) = ustat2; /* take PLL out of Bypass, PLL is now at new CCLK) */ /* The DIVEN bit should be cleared while taking the PLL out of bypass mode */ lcntr = 15, do pllwait1 until lce; pllwait1: nop; /* Put PLL in bypass mode. */ /* clear the DIVEN bit */ /* The DIVEN bit should be cleared while placing the PLL in bypass mode */ /* set a multiplier of 16 and a divider of 4 */

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Programming Models

Listing 23-3. VCO Programming: Second Method

ustat2 = dm(PMCTL); bit clr ustat2 PLLM63| PLLD16; /* Clear the old multiplier and divider values */ bit set ustat2 PLLBP | PLLD4 |PLLM16; dm(PMCTL) = ustat2; waiting_loop: r0 = 4096; /* wait for PLL to lock at new rate (requirement for VCO change) */ lcntr = r0, do pllwait until lce; pllwait: nop; ustat2 = dm(PMCTL); /* Reading the PMCTL register value returns the DIVEN bit value as zero. The DIVEN bit should be cleared while taking the PLL out of bypass mode bit clr ustat2 PLLBP; dm(PMCTL) = ustat2; bit set ustat2 DIVEN; dm(PMCTL) = ustat2; lcntr = 15, do pllwait1 until lce; pllwait1: nop; /* Enable the divider */ /* take PLL out of Bypass, PLL is now at new CCLK) */ */ /* set a multiplier of 16 and a divider of 4 */

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Back to Back Bypass

Use this steps and the example shown in Listing 23-4 if the application needs to re-enter the bypass mode. 1. Disable the bypass bit in the PMCTL register. 2. Wait 6 core clock cycles. 3. Enable the bypass bit. Listing 23-4. Back to Back Bypass
ustat3 = dm(PMCTL); bit clr ustat3 PLLBP; dm(PMCTL) = ustat3; nop;nop;nop;nop; ustat4 = dm(PMCTL); bit set ustat4 PLLBP; dm(PMCTL) = ustat4;

/* PLLBP is cleared */

/* PLLBP is set */

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Programming Models

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24 SYSTEM DESIGN

This chapter discusses different processor reset methods, boot modes and pin multiplexing. In addition, information about high speed design is illustrated with some examples of supervisor circuits used in conjunction with the SHARC processor. These topics are located in the following sections. Processor Reset on page 24-3 Processor Booting on page 24-7 Pin Multiplexing on page 24-28 High Frequency Design on page 24-34 System Components on page 24-43 it recommended that you Before proceeding with this chaptercoreisarchitecture. This informabecome familiar with the SHARC tion is presented in the SHARC Processor Programming Reference.

Features
The following list describes the features for reset and multiplexing. Five reset options: hardware, software, emulation, running reset and watchdog reset. Different master or slave boot mechanisms. Hardware and software reset for processor booting. ADSP-214xx SHARC Processor Hardware Reference 24-1

Pin Descriptions

Two pin multiplexing groups: core flag pins and external port pins. DAI/DPI units work together with multiplexing logic provides system design flexibility.

Thermal Diode
The processors incorporate thermal diode to monitor the die temperature. The thermal diode of is a grounded collector, PNP Bipolar Junction Transistor (BJT). For complete information on thermal diodes, see the Thermal Characteristics section of the processor specific data sheet.

Pin Descriptions
Refer to the appropriate product data sheet for pin information, including package pinouts for the currently available package options.

Register Overview
The following registers are used for processor reset, booting, and pin multiplexing. Software Reset Control Register (SYSCTL). Controls the software reset mechanism. Running Reset Control Register (RUNRSTCTL). Controls the functionality of the RESETOUT pin as running reset input. EP Control Register (EPCTL). Controls the memory chip selects for AMI on the external port memory space during boot. EP DMA control register (DMACx). Controls the receive configuration for external boot DMA.

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AMI Control Register (AMICTL1). Controls the AMI port configuration for external port boot mode. Link Port Control Register 0 (LCTL0). Controls the receive DMA for link port mode during boot. SPI Control Register (SPICTL). Controls the configuration for SPI as master or slave during SPI boot. SPI DMA Control Register (SPIDMAC). Configures the SPI as receive DMA which generates an interrupt during boot. SPI Slave Select Control Register (SPIFLGx). Controls the slave select configuration for SPI as master during SPI boot. SPI Baudrate Register (SPIBAUD). Controls the SPICLK frequency for master mode during boot.

Processor Reset
After power-up, a RESET is required to place the processor into a known good state. Table 24-1 shows the differences between a hardware reset (RESET pin deasserted) or a software reset (setting bit 0 in the SYSCTL register) and gives an overview of the different reset methods.

Hardware Reset
All members of the SHARC processor family support the hardware reset controlled with the RESET pin. The deassertion of this pin enables the PLL and asserting it resets the PLL. In the time it takes the PLL to acquire lock (set to 4096 CLKIN cycles), the processor, internal memory, and the peripherals are held in reset. Upon completion of the 4096 CLKIN cycles, the chip is brought out of reset. This is indicated on the RESETOUT pin for the valid boot modes. For more information, see Processor Booting on page 24-7.

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Processor Reset

Table 24-1. Reset Function Overview

Reset Function
RESETOUT RESETOUT

Hardware Reset Output 4096 CLKIN cycles asserted Yes Yes No Yes Yes Yes No

Software Reset Output

Running Reset Input

Pin Pulse

2 PCLK cycles asserted N/A No Yes No Yes Yes No No No Yes No Yes (except SDRAM/DDR2) No No No

PLL Core Internal Memory1 Peripherals Booting Power Management Emulation Unit2

1 Internal memory array does not have reset. Only power up/down can change array contents, (or direct read/write by the core or DMA). However, if data exists in shadow FIFOs then that data is reset with any of the above resets. The logic outside the memory array is reset by all of the above three reset types, only the memory array contents remain unchanged. 2 There is an independent reset (TRST) for the emulation interface. Enhanced Emulation (BTC) related logic is reset by the three resets types (HW Reset, SW Reset, Running Reset). Furthermore, no other part of the emulator is affected by the reset types. TRST resets the whole emulator function, including BTC.

Software Reset
In addition to the hardware reset, there is also support for a software reset, which is asserted by setting bit 0 of the SYSCTL register.

Running Reset
When running reset is asserted (RESETOUT pin acting as an input and asserted) and recognized, note the following. The core-PLL is NOT reset, and continues to run.

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Internal memory SRAM contents remain unaltered. The processor core and peripherals are reset exactly as if a Power-on (hardware) reset is asserted, except: The SDRAM/DDR2 controllers continue to run and refresh as programmed. The contents of external SDRAM/DDR2 are unaffected, and retain their values prior to a running reset. A system boot is NOT initiated. Instead, the program counter is cleared and program execution begins from the very first location of program memory (from the reset interrupt vector table). Running reset allows programs to: Execute self-modifying code that has previously overwritten existing code in external memory. Activate an external watchdog in cases where there is a malfunction or exception within a peripheral. Perform a context reset of the processor sufficient to restore the state, (in cases where a complete boot is not required). register is reset only assertion hardware The software reset, emulator reset, on by writingoftoa the approprireset, or
RUNRSTCTL

ate bits of the RUNRSTCTL register via software. For emulation reset, see the SHARC Processor Programming Reference, JTAG chapter. System Considerations It is important that an external 10 k pull-up resistor is placed on the RESETOUT pin if it is intended to be used as an input for initiating a run-

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Processor Reset

ning reset as shown in Figure 24-1. ensure It is alsoa extremely important tonot drivethat an external device,after such as micro controller, does this signal during or coming out of a power-on or hard-reset. Figure 24-1 shows the active state of the pin during and after RESET. The processor is actively driving this pin as an output. If the system uses an external host or micro controller to control running reset, ensure that the external device waits until the processor driver has been internally disabled (by writing to the RUNRSTCTL register) before actively driving this signal at RESET. Connect the RESETOUT pin to an open-drain pin on the host side, or use an external three-state buffer.
ADSP-214xx

VDD

RESETOUT

10 k

PAD DRIVER
RUNRSTIN

Ensure that host processor has an open-drain output and is not actively driving this pin during or after RESET

RUNNING RESET CONTROL

Figure 24-1. RESETOUT Pin Multiplexed with RUNRSTIN There are several possible methods that can be used to implement running reset. The following illustrates one example of a running reset implementation involving an SHARC processor and a host processor.

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External Host

In an AVR (audio-video receiver) system, a host microcontroller may communicate with the processor using the serial peripheral interface (SPI) or, if no SPI pins are available on the host device, it can use spare flag I/Os to connect with the SPI of a SHARC as shown in Figure 24-2. In this case, the host implements the SPI protocol on the port pins.
VDD

Use an external pull-up if host pin does not have an external pull-up
10 k HOST PROCESSOR OPEN-DRAIN

ADSP-2146x

RUNRSTIN

Figure 24-2. Example System Interface With an External Host

Processor Booting
When a processor is initially powered up, its internal SRAM is undefined. Before actual program execution can begin, the application must be loaded from an external non-volatile source such as flash memory or a host processor. This process is known as bootstrap loading or booting and is automatically performed by the processor after power-up or after a hard or software reset. processors dont have The SHARCboot scenario. Instead aan on-chip boot ROM which controls the hard coded DMA uploads the boot kernel into the core before the application is booted.

ADSP-214xx SHARC Processor Hardware Reference

SPI OR PORT PINS

SPI PORT

24-7

Processor Booting

Boot Mechanisms
In order to ensure proper device booting, the following hardware mechanisms are available on the processor. Peripheral boot configuration pins configure which peripheral boot stream is activated after power-up. Depending on model and package selection, 2 or 3 boot configuration pins are available. Refer to the product specific datasheet for more information. Peripheral control and DMA parameter settings define the DMA channel which is started after RESETOUT is asserted based on the boot configuration pins. Peripheral interrupt is enabled after reset for the boot peripheral. During kernel load the core is put in IDLE. After the interrupt is generated the core jumps to reset location and starts kernel execution.

External Port Booting

The ADSP-214xx processors allow booting through the external port. The boot setting is configured through the boot configuration pins. The asynchronous memory interface (AMI) supports an 8-bit user boot called AMI boot. Only the MS1 signal is used for AMI (FLASH/EEPROM) booting. Table 24-2 shows the bit settings for AMI boot. These bits are described in detail in AMI Control Registers (AMICTLx) on page A-27. After RESETOUT deasserted, the processor starts to drive:
ADDR230

Chip select MS1 to the EPROM/FLASH

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System Design

AMI_RD

strobe with 23 SDCLK cycle wait states

Read input data 70 pin is disabled during external The data streams of 4x8-bit data wordsport booting.by the The received are packed
ACK

AMIRX

buffer into 32-bit words least significant bit (LSB) first, and passed through the DMAs 6 deep external port buffer DFEP0 into the internal memory (Figure 24-3).
8-bit to 32-bit packing

AMIRX

DFEP0

32

32

32

DMA

Internal Memory

DATA[7:0]

Figure 24-3. External Port Data Packing The external port DMA channel 0 (DMAC0) is used when downloading the boot kernel information to the processor. At reset, the DMA parameter registers are initialized to the values listed in Table 24-4. In this configuration, the loader kernel is read via DMA from the FLASH. If the application needs to speed-up read accesses, programs should change the wait states (WS bits, see Table 24-2) in the kernel file. After the kernel is executed, the new wait state settings are applied and processor booting continues.

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Processor Booting

Table 24-2. AMICTL1 Boot Settings (0x5C1)

Bit 0 21 3 4 5 106 1311 1614 17 2018 21 Name AMIEN BW PKDIS MSWF ACKEN WS HC IC FLSH RHC PREDIS Setting AMI enable (set = 1) Bus width = 8-bit (00) Packing, 8-bit to 32-bit (cleared = 0) Most significant word first (cleared = 0) ACK pin disabled (cleared = 0) 23 wait state cycles = 10111 Bus hold cycle at the end of write access = 000 No bus idle cycle = 000 Buffer holds data (cleared = 0) Read hold cycle at the end of read access = 000 Disable Predictive Reads (cleared = 0)

Table 24-3. EPCTL Boot Settings (0xF0)

Bit 0 1 2 3 54 76 108 1412 1815 2119 Name B0SD B1SD B2SD B3SD EPBR DMAPR FRZDMA FRZCR DATE FRZSP Setting No SDRAM bank 0 (cleared = 0) No SDRAM bank 1 (cleared = 0) No SDRAM bank 2 (cleared = 0) No SDRAM bank 3 (cleared = 0) Rotating priority core vs. DMA (11) Rotating priority EPDMA ch0 vs. EPDMA ch1 (11) No DMA freezing (00) No core freezing (00) No pack mode (0000) (ADSP-2147x/2148x only) No SPORT DMA freezing (000)

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Table 24-4. DMAC0 Boot Settings (0x1000001)

Bit 0 1 2 3 4 5 7 8 9 12 1716 20 21 22 23 24 25 Name DMAEN TRAN CHEN DLEN CBEN DFLSH WRBEN OFCEN TLEN INTIRT DFS DMAS CHS TLS WBS EXTS DIRS Setting DMA enabled (set = 1) Write to internal memory (cleared = 0) No DMA chaining (cleared = 0) No delay line DMA (cleared = 0) No circular DMA (cleared = 0) Disabled (cleared = 0) Disabled (cleared = 0) Disabled (cleared = 0) Disabled (cleared = 0) Disabled (cleared = 0) Status (cleared = 00) Status (cleared = 0) Status (cleared = 0) Status (cleared = 0) Status (cleared = 0) External access pending (set = 1) Status (cleared = 0)

Table 24-5. Parameter Initialization for External Port Boot

Parameter Register IIEP0 IMEP0 ICEP0 EIEP0 Initialization Value 0x92000 0x1 0x180 0x4000000 384 32-bit transfers External memory select 1 start address Comment Start of block 0 (IVT_START_ADDRESS 2 Column)

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Processor Booting

Table 24-5. Parameter Initialization for External Port Boot (Contd)

Parameter Register EMEP0 ECEP0 Initialization Value 0x1 0x180 384 32-bit transfers Comment

SPI Port Booting

The SHARC processors support booting from a host processor using SPI slave mode or booting from an SPI flash, SPI PROM, or a host processor via SPI master mode. Both SPI boot modes (master and slave) support 8-, 16-, or 32-bit SPI devices. For bit settings, see the product specific processor data sheet. slave) LSBF format In both (master3 andselected boot modes, theand clock phaseis=used and SPI mode is (clock polarity 1). Both SPI boot modes use default routing with the DPI pin buffers For more information, see DPI Default Routing on page 10-27. Master Boot Mode In master boot mode, the processor initiates the booting operation by: 1. Activating the SPICLK signal and asserting the SPI_FLG0_O signal to the active low state. 2. Writing the read command 0x03 and 24-bit address 0x000000 to the slave device as shown in Figure 24-4. Master boot mode is used when the processor is booting from an SPI-compatible serial PROM (16-bit address), serial FLASH (24-bit address), or slave host processor (no address). The specifics of booting from these devices are discussed individually. SPI master booting uses the default bit settings shown in Table 24-7.

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Table 24-6. SPIDMAC Master/Slave Boot Settings (0x7)

Bit SPIDEN SPIRCV INTEN SPICHEN FIFOFLSH INTERR Setting Set (= 1) Set (= 1) Set (= 1) Cleared (= 0) Cleared (= 0) Cleared (= 0) Comment SPI DMA SPI receive SPI interrupt SPI DMA chaining FIFO flush SPI DMA error interrupts

Table 24-7. SPICTL Master Boot Settings (0x5D06)

Bit SPIEN SPIMS MSBF WL DMISO SENDZ SPIRCV CLKPL CPHASE Setting Set (= 1) Set (= 1) Cleared (= 0) 10 Cleared (= 0) Set (= 1) Set (= 1) Set (= 1) Set (= 1) Comment SPI enabled Master device LSB first 32-bit SPI receive shift register word length MISO enabled Send zeros Receive DMA enabled Active low SPI clock Toggle SPICLK at the beginning of the first bit

The SPI DMA channel is used when downloading the boot kernel information to the processor. At reset, the DMA parameter registers are initialized to the values listed in Table 24-8.

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Processor Booting

Table 24-8. Parameter Initialization Values for SPI Master Boot

Parameter Register SPIBAUD SPIFLG IISPI IMSPI CSPI Initialization Value 0x64 0xFE01 0x92000 0x1 0x180 Comment SPICLK = fPCLK/100 SPI_FLG0_O used as slave-select Start of block 0 (IVT_START_ADDRESS 2 Column) 32-bit data transfers 384 32-bit transfers

Master Read Command The transfer is initiated by the transferring the necessary header information on the MOSI pin (consisting of the read opcode and the starting 24-bit address of the block to be transferred, which is usually all zeros). The read opcode is fixed as 0xC0 (LSBF format) and is 8 bits long. The 8-bits that are received following the read opcode should be programmed to 0xA5. If the 8-bits are different from 0xA5 the master boot transfer is aborted. The transfer continues until 384 x 32-bit words have been transferred which may correspond to the loader program (just as in the slave boot mode). of VisualDSP tools The loader toolinformation (0xA5). automatically includes the SPI master header 1. Default state of SPICLK signal high (out of reset). 2. Deasserting the SPI_FLG0_O signal (chip select) to the active low state and toggling the SPICLK signal. 3. Reading the read command 0x03 (MSBF format to match the LSBF format) and address 0x00 from the slave device. SHARC Unlike previousSPI masterprocessors, the pin (DPIispin 01) is three-stated for boot mode during reset. It recomMOSI

mended to either leave the SPICLK signal (DPI3) floating or add an external pull-up resistor. The chip select signal going low a bit 24-14 ADSP-214xx SHARC Processor Hardware Reference

System Design

before this erroneous rising edge may lead to boot failure as the read command may not be recognized by the FLASH device properly. The is because the reset configuration of the SPI port for SPI master boot is CLKPL = 1 which means that the SPICLK signal should be HIGH when idle. For more detailed information on the SPI master read command refer to the tools Loader manual. Slave Boot Mode In slave boot mode, the host processor initiates the booting operation by activating the SPICLK signal and asserting the SPI_DS_I signal to the active low state. The 256-word kernel is loaded 32 bits at a time, through the SPI receive shift register (RXSR). To receive 256 instructions (48-bit words) properly, the SPI DMA initially loads a DMA count of 0x180 (384) 32-bit words, which is equivalent to 0x100 (256) 48-bit words. Note that for SPI slave boot SPI_DS_I should only be asserted after RESETOUT has deasserted. booting mode, the input When in SPI slavehost to initiate the boot transfers as signal isincontrolled by the SPI shown
SPI_DS_I

Table 24-9. Since the SPI host initiates the transfers, a handshake between master and slave is required for synchronization. One possible solution is to use the slaves SPI_MISO_O signal as handshake signal. If a pause is required, the slave transmits zeros or ones to the master. Another solution is to connect this signal to the masters flag input to generate an interrupt for the same purpose.

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Processor Booting

Table 24-9. SPICTL Slave Boot Settings (0x4D22)

Bit SPIEN SPIMS MSBF WL DMISO SENDZ SPIRCV CLKPL CPHASE Setting Set (= 1) Cleared (= 0) Cleared (= 0) 10, 32-bit SPI Set (= 1) MISO Cleared (= 0) Set (= 1) Set (= 1) Set (= 1) Comment SPI enabled Slave device LSB first Receive shift register word length MISO disabled Send last word Receive DMA enabled Active low SPI clock Toggle SPICLK at the beginning of the first bit

The SPI DMA channel is used when downloading the boot kernel information to the processor. At reset, the DMA parameter registers are initialized to the values listed in Table 24-10. Table 24-10. Parameter Initialization for SPI Slave Boot
Parameter Register SPIDMAC IISPI IMSPI CSPI Initialization Value 0x0000 0007 0x92000 0x1 0x180 Comment Enable receive, interrupt on completion Start of block 0 (IVT_START_ADDRESS 2 Column) 32-bit data transfers 384 32-bit transfers

SPI Boot Packing In all SPI boot modes, the data word size in the shift register is hardwired to 32 bits. Therefore, for 8- or 16-bit devices, data words are packed into the shift register to generate 32-bit words least significant bit (LSB) first, which are then shifted into internal memory. The relationship between

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System Design

the 32-bit words received into the RXSPI register and the instructions that need to be placed in internal memory is shown in the following sections. For more information about 32- and 48-bit internal memory addressing, see the Memory chapter in the SHARC Processor Programming Reference. As shown in Figure 24-4, two words shift into the 32-bit receive shift register (RXSR) before a DMA transfer to internal memory occurs for 16-bit SPI devices. For 8-bit SPI devices, four words shift into the 32-bit receive shift register before a DMA transfer to internal memory occurs.
WORDS INSTRUCTIONS IN INTERNAL MEMORY
[0x8C000] 0x1122 33445566 [0x8C001] 0x7788 AABBCCDD

32-BIT HOST 16-BIT HOST 8-BIT HOST

33445566 5566 66 55 3344 44 33

CCDD1122 1122 22 11 CCDD

7788AABB AABB 7788 88 77

DD CC BB AA

t=0

t=96 SPICLK

Figure 24-4. Instruction Packing for Different Hosts When booting, the processors expect to receive words into the RXSPI register seamlessly. This means that bits are received continuously without breaks. For more information, see Core Transfers on page 16-24. For different SPI host sizes, the processor expects to receive instructions and data packed in a least significant word (LSW) format. Figure 24-4 shows how a pair of instructions are packed for SPI booting using a 32-, 16-, and an 8-bit device. These two instructions are received as three 32-bit words. The following sections examine how data is packed into internal memory during SPI booting for SPI devices with widths of 32, 16, or 8 bits.

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32-Bit SPI Packing

Figure 24-5 shows how a 32-bit SPI host packs 48-bit instructions executed at PM addresses PMaddr0 and PMaddr1. The 32-bit word is shifted to internal program memory during the 256-word kernel load. The following example shows a 48-bit instruction executed:
[PMaddr0] 0x112233445566 [PMaddr1] 0x7788AABBCCDD

32-bit Word N

RXSPI

RXSR

32

32

32

DMA

Internal Memory

SPI_MOSI_I/SPI_MISO_I

Figure 24-5. 32-Bit SPI Master/Slave Packing The 32-bit SPI host packs or prearranges the data as:
SPI word 1= SPI word 2 = SPI word 3 = 0x33445566 0xCCDD1122 0x7788AABB

The initial boot of the 256-word loader kernel requires a 32-bit host to transmit 384 x 32-bit words. The SPI DMA count value of 0x180 is equal to 384 words.

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16-Bit SPI Packing

Figure 24-6 shows how a 16-bit SPI host packs 48-bit instructions at PM addresses PMaddr0 and PMaddr1. For 16-bit hosts, two 16-bit words are packed into the shift register to generate a 32-bit word. The 32-bit word shifts to internal program memory during the kernel load. The following code shows a 48-bit instruction executed:
[PMaddr0] 0x112233445566 [PMaddr1] 0x7788AABBCCDD

16-bit Word N

RXSR

RXSPI

32

32

32

DMA

Internal Memory

SPI_MOSI_I/SPI_MISO_I

Figure 24-6. 16-Bit SPI Master/Slave Packing The 16-bit SPI host packs or prearranges the data as:
SPI word 1 = SPI word 2 = SPI word 3 = SPI word 4 = SPI word 5 = SPI word 6 = 0x5566 0x3344 0x1122 0xCCDD 0xAABB 0x7788

The initial boot of the 256-word loader kernel requires a 16-bit host to transmit 768 16-bit words. Two packed 16-bit words comprise the 32-bit word. The SPI DMA count value of 0x180 is equivalent to 384 words. Therefore, the total number of 16-bit words loaded is 768.

ADSP-214xx SHARC Processor Hardware Reference

16-bit Word N

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Processor Booting

8-Bit SPI Packing

Figure 24-7 shows how an 8-bit SPI host packs 48-bit instructions executed at PM addresses PMaddr0 and PMaddr1. For 8-bit hosts, four 8-bit words pack into the shift register to generate a 32-bit word. The 32-bit word shifts to internal program memory during the load of the 256-instruction word kernel. The following code shows a 48-bit instruction executed:
[PMaddr0] 0x112233445566 [PMaddr1] 0x7788AABBCCDD
8-bit Word N 8-bit 8-bit Word N Word N

RXSR

32

RXSPI

32

32

DMA

Internal Memory

8-bit Word N

SPI_MOSI_I/SPI_MISO_I

Figure 24-7. 8-Bit SPI Slave Packing The 8-bit SPI host packs or prearranges the data as:
SPI word 1 = SPI word 2 = SPI word 3 = SPI word 4 = SPI word 5 = SPI word 6= 0x66 0x55 0x44 0x33 0x22 0x11 SPI word 7 = SPI word 8 = SPI word 9 = SPI word 10 = SPI word 11 = SPI word 12= 0xDD 0xCC 0xBB 0xAA 0x88 0x77

The initial boot of the 256-word loader kernel requires an 8-bit host to transmit 1536 x 8-bit words. The SPI DMA count value of 0x180 is equal

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System Design

to 384 words. Since one 32-bit word is created from four packed 8-bit words, the total number of 8-bit words transmitted is 1536.

Link Port Booting

Booting is supported through link port 0. The BOOT_CFGx values for selecting link port boot are located in the product specific data sheet. The booting procedure is the same as any other boot mode. The acknowledge signal (LACK0) is asserted at RESET since the link port is configured as a receiver. The host initiates the transfer by toggling the link port clock (LCLK0). Boot data is shifted in 8-bits every clock cycle through the LDAT0x pins. The received data streams of 4 x 8-bit is packed by the 2 deep RXLB0 buffer into 32-bit words, least significant bit (LSB) first, and passed into the internal memory (Figure 24-8). Once the DMA is completed, a link port 0 interrupt (P1I) occurs. If BOOT_CFGx is programmed for link port boot, P1I is programmed as the link port 0 interrupt at reset and the interrupt is unmasked at reset. Otherwise, P1I is programmed as the SPIHI interrupt at reset. link port For deasserted.boot, has
REGISTER (8 TO 32)

LCLK0

should only be asserted after RESETOUT

RECEIVE PACK

32

RXLB0

32

32

DMA

Internal Memory

LDATA[7:0]

Figure 24-8. Link Port Data Packing

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Processor Booting

Table 24-11 shows the link port control settings after reset. Table 24-11. LCTL0 Boot Settings (0x403)
Bit 0 1 2 3 7 8 9 10 11 12 Name LEN LDEN LCHEN LTRAN BHD LTRQ_MSK LRRQ_MSK DMACH_IRPT_MSK LPIT_MSK TXFR_DONE_MSK Setting Link port enabled (set = 1) DMA enabled (set = 1) DMA Chaining (cleared = 0) Receive operation (cleared = 0) Buffer hang disabled (cleared = 0) LP transmit request mask (cleared = 0) LP receive request mask (cleared = 0) LP DMA channel interrupt unmask (P1I) (set = 1) LP Invalid transmit mask (cleared = 0) External transfer done interrupt mask (cleared = 0)

The DMA parameters for the Link Port0 channel are configured as shown in Table 24-12. Table 24-12. Parameter Initialization for Link Boot
Parameter Register Elf splitter IILP0 IMLP0 ICLP0 Initialization Value 0x92000 0x1 0x180 Comment Start of block 0 (IVT_START_ADDRESS 2 Column) 32-bit data transfers 384 32-bit transfers

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Kernel Boot Time

This section illustrates the minimum required booting time for the kernels (provided by the tools). There are five timing windows which describe together the entire boot process shown in the list below and Table 24-13. 1. 2.
RESET

to RESETOUT (core is in reset) to chip select boot source (activate the boot DMA)

RESETOUT

3. Load Kernel DMA (256 words) 4. Load application (user dependent) 5. Load IVT (256 words) Table 24-13. Boot Times
Boot Mode SPI Master SPI Slave
RESET to RESETOUT RESETOUT to Boot Kernal DMA (256 Chip Select Words)

Comment N=384, 768 or 1536 for I/O = 32, 16 or 8 N=384, 768 or 1536 for I/O = 32, 16 or 8

4096 CLKIN 4096 CLKIN

1 PCLK

(I/O PCLK 100 + 4 PCLK) N

Host drives signal (I/O PCLK 100 + 2 PCLK) N 5 PCLK 24 SDCLK 1536

External Port Link Port0

4096 CLKIN 4096 CLKIN

Host drives signal LCLK0 1536

The complete time for booting can be estimated by adding all 5 timing windows. Loading Kernel and Loading IVT both have the same size, however the default access time (wait states) for the IVT loading can be changed in the kernel by the user.

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Programming Model

ROM Booting
There are two access types (modes) available for ROM booting: secured and non secured modes which are described below. Secured ROM (hardware security switch = 1). In this mode:
BOOTCFG2-0

pins are ignored.

Emulation is enabled only when the user enters a valid key. IIVT is placed into the internal ROM. It can be changed to the internal RAM by setting IIVT bit of SYSCTL register. Code always executes from internal ROM. Non Secured ROM (hardware security switch = 0). In this mode:
BOOTCFG2-0

pins select the booting modes.

Emulation is always enabled. IIVT is placed into the internal RAM except for the case where BOOTCFG2-0 = 011.

Programming Model
This section describes the operation of the boot process. This process is accomplished using the default loader kernel (Visual DSP Tools) to generate the boot stream. For more details, refer to the loader source files.

Running Reset
Using the SPI protocol with additional control words and commands, running reset can become an addition command from the host or from the processor as described in the following procedure.

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1. The host initiates a running reset by informing the processor over the command interface. 2. The processor receives the command and completes any unfinished work which may also include writing to the RUNRSTCTL register. 3. Wait at least 5 CCLK cycles to ensure that the pin is configured as an input. 4. When the processor is ready to accept the running reset, it signals the host over the command interface. 5. The host drives the running reset input into the processor.

Running The Boot Kernel

The following sections provide information on the use of the boot kernal with the SHARC processors. Loading the Boot Kernel Using DMA 1. At reset, the processor is hardwired (using the boot configuration pins) to load 256 x 48-bit instruction words via a DMA starting at IVT_START_ADDRESS. 2. The sequencer is put into IDLE until the boot interrupt occurs. Executing the Boot Kernel 1. The DMA completes (counter zero) and the interrupt associated with the peripheral that the processor is booting from is activated. 2. The processor jumps to the applicable interrupt vector location and executes the RTI instruction located there (only). own kernel, you ensure If using yourpoints loader IVT locationmustthe bootthat the RTI instruction to the of peripheral.

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Programming Model

Loading the Application 1. Once the kernel is executed (initialization of some core and external peripheral registers and such as AMI or SDRAM), the kernel prepares a DMA for further data. 2. After this the DMA starts and the core waits in IDLE until an interrupt is generated. 3. The kernel then reads the header data from a memory scratch location, decodes the header and configures a loop which loads all of the headers corresponding data. 4. Step 3 is repeated until all headers are executed. Loading the Applications Interrupt Vector Table 1. The last header is recognized by the kernel indicating that booting has nearly finished. 2. The kernel prepares a 256 x 48-word DMA starting at IVT_START_ADDRESS. This overrides the kernel with the applications IVT. However, the application needs to temporarily include the RTI instruction at the peripheral interrupt address, allowing a return from interrupt. Moreover, the last instruction in the final routine is a jump (db) including an IDLE. 3. The RTI instruction overrides the IVT address where user code is stored. types (Loading the Boot Kernel Using DMA While both DMAApplications Interrupt Vector Table) seem simand Loading the ilar, loading the kernel is accomplished using hardware while loading the IVT is accomplished using software.

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System Design

kernel to dedicated It is very important to match the dedicatedboot type)the the elfboot type (for example SPI kernel and SPI in loader property page. If this is not done, the RTI instruction (in Loading the Applications Interrupt Vector Table) will not be placed at the correct address. This causes execution errors. Starting Program Execution The processed interrupt returns the sequencer to the reset location by performing the two following steps. 1. Overriding the RTI instruction with user code. 2. Starting program execution from the reset location. For other details relating to processor booting, see the boot loader source files that ship with the VisualDSP tools.

Memory Aliasing in Internal Memory

The boot loader takes advantage of memory aliasing which is essential to understand the boot mechanisms. For information on memory aliasing, see the SHARC Processor Programming Reference, Memory chapter. During the boot process, word packing (for example 8 to 32-bit) is performed over the SPI. In other words, the kernel is not loaded directly with 256 x 48-bit words, instead it is loaded with 384 x 32-bit packed words (2-column access). The same physical memory for instruction boot is loaded via DMA in normal word (NW) 2 column. However, after booting the same physical memory region is fetched by the sequencer in NW 3-column. For example the loader kernel itself has a NW 2 columns count of 256 x 3/2 = 384 words but the kernel is executed with 256 instruction fetches.

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Pin Multiplexing

Note that the interrupt vector table addresses are defined as:
IVT_Start_Addr

= 0x8C000 and IVT_End_Addr = 0x8C0FF.

Pin Multiplexing
The SHARC processors provide extensive functionality using a low pin count (reducing system cost). They do this through extensive use of pin multiplexing. The following sections provide information on this feature. Although the processors have the efficient and flexible DAI and DPI routing options, there are also I/O pins which are shared by some peripherals. The following sections discusses these options. interfaces are On the ADSP-2146x processors the AMI and DDR2 AMI controlcompletely independent (not multiplexed). Only the ler address/memory selects and data pins are shared and therefore all pins discussed in this section refer to the AMI controller. Therefore, the naming conventions DATAx and ADDRx used below refer to the AMI_DATAx and AMI_ADDRx pins for ADSP-2146x processors.

Core FLAG Pins Multiplexing

This module also includes the multiplexers of the FLAG0-3 pins shown in Figure 24-9. The FLAG0-2 pins can act as core FLAGS0-2 or IRQ0-2, or a memory select MS2 (FLAG2 pin) and the FLAG3 pin can act as a core FLAG3 or the TMREXP signal of the core timer or as a memory select MS3. ) input after reset. Flag pins ( flags areare connected ascan multiplexed using the exterIf more than four required, they
FLG3-0

nal port pins in the SYSCTL register or the DPI pins in the DPI registers. For a detailed flag description refer to the SHARC Processor Programming Reference. Table 24-14 provides information on FLAG function based on

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System Design

the settings of the memory select enable, the flag timer expired and the FLAG2 interrupt bits in the system control register. Table 24-14. Flag 32 Truth Table (SYSCTL Register)
MSEN Bit 0 0 0 0 1 TMREXPEN Bit IRQ2EN Bit 0 0 1 1 0 0 1 0 1 0 FLAG3 Function FLAG2 Function
FLAG3 FLAG3 TMREXP TMREXP MS3 FLAG2 IRQ2 FLAG2 IRQ2 MS2

Backward Compatibility The FLAG/IRQ (0, 1, 2, 3) pins retain their old functionality and programming. No changes are required for old programs. The select lines for multiplexes are controlled by the SYSCTL register. For more information, see System Control Register (SYSCTL) on page A-5.

External Port Pin Multiplexing

Various peripherals use the external port for off-chip communication. These peripherals use multiplexed I/O pins and have the (functions) shown: External Port (AMI/SDRAM/DDR2) PDAP (input) FLAGs (I/O) PWM channels (output)

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Pin Multiplexing

Backward Compatibility The multiplexing scheme is not backward compatible with previous SHARC processors. On previous SHARC processors only the external port data pins are multiplexed. With the ADSP-214xx processors, address and data pins of the external port are multiplexed. Multiplexed External Port Pins The external port address and data pins are used to multiplex the external port interface with other peripherals. Table 24-15 provides the pin settings. Table 24-15. EPDATA Truth Table (SYSCTL Register)
EPDATA 000 001 010 011 100 101 110 111 FLAGS/PWM1501 Reserved PDAP (DATA + CTRL) Reserved Three-state all pins FLAGS70 ADDR238 ADDR230 Reserved Reserved FLAGS150 ADDR70 DATA70 DATA70

1 These signals can be FLAGS or PWM or mix of both but can be selected only in groups of four. Their functionality is decided by the bits FLAGS/PWM_SEL of SYSCTL register.

Table 24-15 shows the following options. The FLAG15-0 signals can be mapped to the lower set of eight data pins (DATA7-0) and lower eight address pins (ADDR7-0) such that FLAG7-0 signals map to DATA7-0 and FLAG15-8 signals map to ADDR7-0 respectively (EPDATA = 011).

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FLAGS/PWM can be mapped (in groups of four) to the upper 16 address pins (ADDR23-8) such that FLAG3-0/PWM3-0 signals map to ADDR11-8, FLAG7-3/PWM7-3 signals map to ADDR15-12, FLAG11-8/PWM11-8 signals map to ADDR19-16, FLAG15-12/PWM15-12 signals map to ADDR23-20 respectively (EPDATA = 011). PDAP data/control can be completely moved to external port address pins (ADDR23-0). In this mode, PDAP_DATA19-0 input signals are mapped to ADDR23-4, PDAP_HOLD input signal is mapped to ADDR3, PDAP_CLK input signal is mapped to ADDR2, and PDAP STROBE output signal is mapped to ADDR0.

Parallel Connection of Flag Pins via External Port and DPI Pins
The various external port multiplexing (shown in Figure 24-9 on page 24-33) and DPI routing options allow situations where the flag direction paths from the core to the external port or DPI pins operates in parallel as described below. For FLAG30 In output mode, if the same flag is mapped to both external port pins and FLAG3-0 pins, then the output is driven to both pins. In input mode, if the same flag is mapped to both external port pins and FLAG3-0 pins, then the input from external port pins has priority. For FLAG154 In output mode, if the same flag is mapped to both external port pins and DPI pins, then the output is driven from both pins.

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Pin Multiplexing

In input mode, if the same flag is mapped to both external port pins and DPI pins, then the input from the external port pins has priority. In input mode, if the same flags are mapped to both the upper AMI (ADDR23-8) and lower AMI (ADDR7-0, DATA7-0) pins, then the input from lower AMI pins have priority. The FLAG154 SRU2 connections are shown in Table 24-16. Table 24-16. FLAG SRU2 Signal Connections
FLAG Source DPI Connection Group A FLAG154_O FLAG15-4_PBEN_O Group B Group C FLAG Destination FLAG154_I

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System Design

FLAG0 IRQ0

M U X

FLAG0_PIN

FLAG1 PWM15-4 (ADSP-2147X, ADSP-2148X) FLAGS15-4 FLAG2 FLAGS3-0 PWM3-0 IRQ2 M U X MS2 3-0 FLAG3 FLAGS7-4 PWM7-4 TMREXP MULTIPLEXING IN GROUPS OF 4 ONLY MS3 M U X FLAG3_PIN M U X FLAG2_PIN IRQ1 DPI PINS M U X FLAG1_PIN FLAG3-0 PINS DATA7-0 ADDR7-0 ADDR23-8

M U X 7-4

FLAGS11-8 PWM11-8 M U X

11-8

ADDR23-8 PDAP_DATA19-4 FLAGS/PWM15-0 M U X

FLAGS15-12 M U X

PWM15-12

15-12

ADDR7-0 PDAP_DATA/CTRL FLAGS15-8 M U X

DATA7-0 SOLID LINES INDICATE DEFAULT ROUTING (ALL PINS) AFTER RESET FLAGS7-0

M U X

Figure 24-9. Pin Multiplexing

ADSP-214xx SHARC Processor Hardware Reference

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Processor Identification Register

Processor Identification Register

The SHARC processor models have a memory-mapped version control register, REVPID, shown in Figure 24-10 and described in Table 24-17, that identifies the processor model and its silicon revision number. processor identification via the JTAG instruction ( For SHARC Processor Programming Reference. the
31 30 29 28 0 0 0 0 27 26 25 24 0 0 0 0 23 22 0 0 21 20 0 0 19 18 17 16 0 0 0 0

IDCODE)

see

15 14 13 12 11 10 0 0 0 0 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

SIREV (74) Silicon Revision

PROCID (30) Processor Model

Figure 24-10. REVPID Register Table 24-17. REVPID Register Bit Descriptions (RO)
Bit 30 Name PROCID Description Processor Model. The processor model is shown below. 0101 = ADSP-2146x SHARC products 0110 = ADSP-2148x SHARC products 0111 = ADSP-2147x SHARC products Silicon Revision. For the silicon revision number bits (74), refer to the processor specific anomaly sheet.

74

SIREV

High Frequency Design

Because the processor must be able to operate at very high clock frequencies, signal integrity and noise problems must be considered for circuit board design and layout. The following sections discuss these topics and

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suggest various techniques to use when designing and debugging target systems.

Circuit Board Design

The processor is a CMOS device. It has input conditioning circuits which simplify system design by filtering or latching input signals to reduce susceptibility to glitches or reflections. The following sections describe why these circuits are needed and their effect on input signals. Clock Input Specifications and Jitter The clock input signal must be free of ringing and jitter. Clock jitter can easily be introduced into a system where more than one clock frequency exists. Jitter should be kept to an absolute minimum. High frequency jitter on the clock to the processor may result in abbreviated internal cycles. Keep the portions of the system that operate at different frequencies as physically separate as possible. The clock supplied to the processor must have a maximum rise time and must meet or exceed a high and low voltage of VIH and VIL, respectively. Refer to the appropriate product data sheet for exact specifications. RESETOUT Circuit boards should have a test pad for the RESETOUT pin This pin can be used as handshake signal for booting or as clock out (CLKIN frequency) for a debug aid to verify the processor is active and running. Input Pin Hysteresis Hysteresis (shown in Figure 24-11) is used on all SHARC input signals. Hysteresis causes the switching point of the input inverter to be slightly

ADSP-214xx SHARC Processor Hardware Reference

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High Frequency Design

above 1.4 V (VT) for a rising edge (VT+) and slightly below 1.4 V for a falling edge (VT). The value of the hysteresis is approximately 100 mV. Refer to the appropriate product data sheet for exact specifications.
VDDEXT VIH VT+ VT VTVIL GND ENABLES VTENABLES VT+

Figure 24-11. Input Pin Hysteresis The hysteresis is intended to prevent multiple triggering of signals that are allowed to rise slowly, as might be expected for example on a reset line with a delay implemented by an RC input circuit. Hysteresis is not used to reduce the effect of ringing on processor input signals with fast edges, because the amount of hysteresis that can be used on a CMOS chip is too small to make a difference. The small amount of hysteresis allowed is due to restrictions on the tolerance of the VIL and VIH TTL input levels under worst-case conditions. Clock and Control Signal Transitions All clocks and control signals MUST transition between VIL and VIH (or VIH and VIL) in a monotonic manner. Pull-Up/Pull-Down Resistors The pin descriptions in the product specific data sheets includes recommendations on how to handle pins on interfaces that are disabled or for

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unused pins on interfaces that are enabled. Generally, if internal pull-ups (IPU) or pull-downs (IPD) are included, the pins can be left floating. Any pin that is output only can always be left floating. If internal pull-ups and pull-downs are not included or disabled, pins can normally still be floated with no functional issues for the device. However, this may allow additional leakage current. Although the recommendations normally indicate using external pull-up resistors, pull-down resistors can also be used. The leakage is the same whether pull-ups or pull-downs are used. Connections directly to power or ground can be used only if the pins can be guaranteed to never be configured as outputs. Memory Select Pins When the multiplexed memory selects, MS3-2, are enabled as outputs, the pull-up resistors are automatically enabled. For example, if MS2 and MS3 are used, they require that stronger external pull-up resistors are connected. For more details on resistor values, refer to the product specific data sheet. Edge-Triggered I/O It is recommended that GPIO output pins that are used to drive an edge-sensitive signal like an interrupt (IRQ2-0, DAI/DPI pins) have series termination resistors to prevent glitches on the signal transitions. It is equally important that GPIO inputs that are edge-sensitive be driven from sources that have series termination resistors. The values for the series resistor can be determined by simulating with the IBIS models. These models can be found on the Analog Devices web site. Asynchronous Inputs The processor has several asynchronous inputs such as IRQ2-0, FLAG30, ACK and the DAI/DPI pins and reset inputs RESET, TRST, running reset

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High Frequency Design

which can be asserted in arbitrary phase to the reference clocks. The processor synchronizes the reset inputs to the CLKIN input while the peripheral inputs are synchronized to the PCLK prior to recognizing them. The delay associated with recognition is called the synchronization delay. Any asynchronous input must be valid prior to the recognition point in a particular cycle. If an input does not meet the setup time on a given cycle, it may be recognized in the current cycle or during the next cycle. To ensure recognition of an asynchronous input, it must be asserted for at least one PCLK cycle plus setup and hold time, except for RESET, which must be asserted for at least four CLKIN processor cycles. The minimum time prior to recognition (the setup and hold time) is specified in the appropriate product data sheet.

Decoupling and Grounding

Designs should use an absolute minimum of four bulk capacitors (2 10 F for VDDINT and 2 10 F for VDDEXT). Furthermore a minimum of 20 10nF ceramic bypass capacitors (5 per chip corner for VDDINT and VDDEXT). Capacitors type, value and placement is criticalespecially for floating point computations, which draw more power. If the bulk/bypass capacitors are insufficient, the power rails may drop, causing errors. Therefore sufficient capacitor backup is important.

Circuit Board Layout

This section gives recommendations to physical layouts for high speed designs. Place the oscillator close to the destination. Place the series termination close to the clock source.

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For trace routing: Place a GND plane below the oscillator and buffer. Place a solid GND reference plane under the clock traces. Do not route the digital signals near or under the clock sources.

ESD/EOS Protection Circuits

To protect the core against fast transients it is recommended that designs use 3 serially-connected diodes to protect the nominal core supply line. The 3-diode stack compensates for the ~2 mV/C temperature coefficient of each diode. Note that it is important that the selected diode have a fast turn-on time (ideally <1 ns) and a low ON resistance under high-current, forward-biased operation. Additionally, a Schottky diode (Figure 24-12) should be added in parallel to handle any negative transient voltage spikes.
+V SUPPLY PLANE

SCHOTTKY DIODE

GND PLANE

Figure 24-12. Schottky Diode

Other Recommendations and Suggestions

Use more than one ground plane on the PCB to reduce crosstalk. Be sure to use lots of vias between the ground planes. One VDD plane for each supply is sufficient. These planes should be in the center of the PCB.

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High Frequency Design

To reduce crosstalk, keep critical signals such as clocks, strobes, and bus requests on a signal layer next to a ground plane away from, or lay out these signals perpendicular to, other non-critical signals. If possible, position the processors on both sides of the board to reduce area and distances. To allow better control of impedance and delay, and to reduce crosstalk, design for lower transmission line impedances. Experiment with the board and isolate crosstalk and noise issues from reflection issues. This can be done by driving a signal wire from a pulse generator and studying the reflections while other components and signals are passive. The capacitors should be placed close to the package as shown in Figure 24-13. The decoupling capacitors should be tied directly to the power and ground planes with vias that touch their solder pads. Surface-mount capacitors are recommended because of their lower series inductances (ESL) and higher series resonant frequencies. Connect the power and ground planes to the processors power supply pins directly with vias, do not use traces. The ground planes should not be densely perforated with vias or traces as this reduces their effectiveness. In addition, there should be several large tantalum capacitors on the board. can in Designs24-13,use either bypass placement case shownshould try to Figure or combinations of the two. Designs minimize signal feedthroughs that perforate the ground plane.

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BYPASS CAPACITORS ON NON-COMPONENT (BOTTOM) SIDE OF BOARD, BENEATH DSP PACKAGE

BYPASS CAPACITORS ON COMPONENT (TOP) SIDE OF BOARD, AROUND DSP PACKAGE

Figure 24-13. Bypass Capacitor Placement

EZ-KIT Lite Schematics

The EZ-KIT Lite evaluation system schematics are a good starting reference. Because the EZ-KIT Lite board is for evaluation and development, extra circuitry is provided in some cases. Read the EZ-KIT Lite board schematic carefully, because sometimes a component is not populated and sometimes it has been added to make it easier to access. The design database for the SHARC processor EZ-KIT Lite boards is available online and contains all of the electronic information required for design, layout, fabrication, and assembly:
ftp://ftp.analog.com/pub/tools/Hardware/Reference_Designs

Oscilloscope Probes
When making high speed measurements, be sure to use a bayonet type or similarly short (< 0.5 inch) ground clip, attached to the tip of the oscilloscope probe. The probe should be a low capacitance active probe with 1 pF or less of loading. The use of a standard ground clip with four inches of ground lead causes ringing to be seen on the displayed trace and makes the signal appear to have excessive overshoot and undershoot.

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High Frequency Design

A 1 GHz or better sampling oscilloscope is needed to see the signals accurately.

Recommended Reading
The text High-Speed Digital Design: A Handbook of Black Magic is recommended for further reading. This book is a technical reference that covers the problems encountered in state-of-the-art, high frequency digital circuit design. It is also an excellent source of information and practical ideas. Topics covered in the book include: High-Speed Properties of Logic Gates Measurement Techniques Transmission Lines Ground Planes and Layer Stacking Terminations Vias Power Systems Connectors Ribbon Cables Clock Distribution Clock Oscillators High-Speed Digital Design: A Handbook of Black Magic, Johnson & Graham, Prentice Hall, Inc., ISBN 0-13-395724-1. High-Speed Signal Propagation: Advanced Black Magic, Johnson & Graham, Prentice Hall, Inc., ISBN 0-13-084408-X.

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System Components
This section provides some recommendations for other components to use when designing a system for your processor.

Power Management Circuits

The the ADSP-2147x and ADSP-2148x SHARC processors require a minimum of two power supplies. The ADSP-2146x processors, requires an additional supply for its DDR2 interface. The power consumption numbers are available in the respective product data sheet or EE-notes. Refer to the following link for more information on the ADPxxxx series power supplies:
http://www.analog.com/en/power-management/switching-regulators-integrated-fet-switches/products/index.html

Supervisory Circuits
It is important that a processor (or programmable device) have a reliable active RESET that is released once the power supplies and internal clock circuits have stabilized. The RESET signal should not only offer a suitable delay, but it should also have a clean monotonic edge. Analog Devices has a range of microprocessor supervisory ICs with different features. Features include one or more of the following. Power-up reset Optional manual reset input Power low monitor Backup battery switching

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System Components

The part number series for reset and supervisory circuits from Analog Devices are as follows. ADM69x ADM70x ADM80x ADM1232 ADM181x ADM869x A simple power-up reset circuit is shown in Figure 24-14 using the ADM809-RART reset generator. The ADM809 provides an active low RESET signal whenever the supply voltage is below 2.63 V. At power-up, a 240 ms active reset delay is generated to give the power supplies and oscillators time to stabilize. Another part, the ADM706TAR, provides power on RESET and optional manual RESET. It allows designers to create a more complete supervisory circuit that monitors the supply voltage. Monitoring the supply voltage allows the system to initiate an orderly shutdown in the event of power failure. The ADM706TAR also allows designers to create a watchdog timer that monitors for software failure. This part is available in an 8-lead SOIC package. Figure 24-15 shows a typical application circuit using the ADM706TAR.

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VDDEXT 10F VDDEXT

V D D IN T

VCC

VDDINT

ADM809-RART
RESET RESET

ADSP-214xx

S
GND

GND

Figure 24-14. Simple Reset Generator

VDDEXT

VSENSE 100nF

10F VDDEXT 100nF

2 4 Vt=+1.25V 1 6 RESET

ADM706TAR
VCC PFI MR WDI RST PFO WDO GND

RESET 7 5 8 3 IRQ0

ADSP-214xx

IRQ1

FLAG0 GND

Figure 24-15. Reset Generator and Power Supply Monitor

ADSP-214xx SHARC Processor Hardware Reference

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Definition of Terms

Definition of Terms
Booting When a processor is initially powered up, its internal SRAM and many other registers are undefined. Before actual program execution can begin, the application must be loaded from an external non-volatile source such as flash memory or a host processor. This process is known as bootstrap loading or booting and is automatically performed by the processor after power-up or after a software reset. Boot Kernel The boot kernel is an executable file which schedules the entire boot process. The temporary location of the kernel resides in the processors Interrupt vector location (IVT). The IVT typically has a maximum size of 256 x 48 words. After booting, the kernel overwrites this area. These kernel files (DXE, ASM) are supplied with the VisualDSP++ development tools for all boot modes. For more information on the kernels, refer to the tools documentation Boot Master/Slave How a processor boots is dependent on the peripheral used. See Processor Booting on page 24-7. Boot Modes The boot mode is identified by the BOOT_CFGx pins that are used in the boot process. No Boot Mode In legacy mode, the processor does not boot. Instead, it starts fetching instructions directly from external memory. The SHARC ADSP-214xx processors onwards do not support this mode.

24-46

ADSP-214xx SHARC Processor Hardware Reference

System Design

ROM Boot Mode For BOOT_CFGx pins = 011, the processor executes from internal ROM. Only specific versions of the processors support this mode.

ADSP-214xx SHARC Processor Hardware Reference

24-47

Definition of Terms

24-48

ADSP-214xx SHARC Processor Hardware Reference

A REGISTER REFERENCE

The SHARC processors have general-purpose and dedicated registers in each of their functional blocks. The register reference information for each functional block includes bit definitions, initialization values, and memory-mapped addresses (for I/O processor registers). Note that this appendix only contains information for the control and or status registers. All peripheral DMA parameter (IOP) registers (for example index, modify, count, chain pointer) are listed and described in Chapter 3, I/O Processor. This reference does not include core related control and status registers. These registers are described in the SHARC Processors Programming Reference. The registers are grouped under the following headings. Overview on page A-2 System and Power Management Registers on page A-5 External Port Registers on page A-20 Peripheral Registers on page A-62 DAI Signal Routing Unit Registers on page A-123 Peripherals Routed Through the DAI on page A-154 DPI Signal Routing Unit Registers on page A-207 Peripherals Routed Through the DPI on page A-219 Register Listing on page B-1

ADSP-214xx SHARC Processor Hardware Reference

A-1

Overview

When writing programs, it is often necessary to set, clear, or test bits in the processors registers. While these bit operations can all be done by referring to the bits location within a register or (for some operations) the registers address with a hexadecimal number, it is much easier to use symbols that correspond to the bits or registers name. For convenience and consistency, Analog Devices supplies a header file that provides these bit and registers definitions. An #include file is provided with VisualDSP++ tools and can be found in the VisualDSP/214xx/include directory.

Overview
The I/O processors registers are accessible as part of the processors memory map. Register Listing on page B-1 lists the I/O processors memory-mapped registers and provides a brief description of each register. Since the I/O processor registers are memory-mapped, the processors architecture does not allow programs to directly transfer data between these registers and other memory locations, except as part of a DMA operation. To read or write I/O processor registers, programs must use the processor core registers. The register names for I/O processor registers are not part of the processors assembly syntax. To ease access to these registers, programs should use the header file containing the registers symbolic names and addresses.

Register Diagram Conventions

The register drawings in this appendix provide at-a-glance information about specific registers. They are designed to give experienced users basic information about a register and its bit settings. When using these registers, the following should be noted.

A-2

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

In cases where there are multiple registers that have the same bits (such as serial ports), one register drawing is shown and the names and addresses of the other registers are simply listed. Also, depending on peripheral (such as ASRC), if two different ASRC ports are programmed in the same register, one peripheral is defined with a x the other with a y index. The bit descriptions in the figures are intentionally brief, containing only the bit mnemonic, location, and function. More detailed information can be found in the tables that follow the register drawings and in the chapters that describe the particular module. Shaded bits are reserved. The VisualDSP++ tools suite contains the complete listing of registers in a header file, def214xx.h. Register Listing on page B-1 provides a complete list of user accessible registers, their addresses, and their state at reset.

Bit Types and Settings

There are several bit types used in SHARC registers. These are described in Table A-1. In general, control register bits are read-write (RW) and status register bits are read-only (RO). In exceptional cases, bit types are shown in the Bit column in parenthesis where for example a RO bit is used in a control register or for read-write-one-to-clear (RW1C) bits. Also note that the setting after reset (default setting) of most bits is 0 (cleared). In cases where this is not true, this is shown in the Description column in parenthesis.

ADSP-214xx SHARC Processor Hardware Reference

A-3

Overview

Table A-1. Bit Type Definitions

Bit Type RW RO ROC Description Read-Write Read-Only Read-Only-to-Clear Usage RW bits are used primarily in control registers and DMA parameter and count registers. RO bits are used primarily in status registers and Shadow registers/buffers for debug aid. ROC bits are similar to RO bits however the read changes the status bits. Can be used for example to acknowledge interrupt signals properly which clears the request logic. These bits are sticky. WOC bits are used primarily in data FIFOs. Each write automatically updates the FIFO status. RW1C bits are sticky bits used primarily in status registers for correct interrupt acknowledge (some peripherals). These bits are sticky and their status is only cleared after a write. RW1S bits need to be set for an action and hardware clears them by itself. An example is the PLL DIVEN bit or the SDRAM power-up sequence start bit.

WOC RW1C

Write-Only-to-Clear Read-Write-1-to-Clear

RW1S

Read-Write-1-to-Set

have reserved to register, pro Many registersnot change the bits. When writingbits.aFor example: grams should registers reserved Change bit 22 and bit 25 only:
ustat1 = dm(IOP_register); bit set ustat1 BIT22; bit clr ustat1 BIT25; dm(IOP_register)=ustat1; /* read */ /* modify */ /* modify*/ /* write */

reserved bits, the read value is If reading or the reset value of these bits. the last written value to these bits

A-4

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

System and Power Management Registers

The registers described in the following sections are used to control system wide operations and power management.

System Control Register (SYSCTL)

The SYSCTL register configures memory use, interrupts, and many aspects of pin multiplexing. (For more information, see Pin Multiplexing on page 24-28.) Bit descriptions for this register are shown in Figure A-1 and described in Table A-2.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PWMONDPIEN DPI Pins as PWM Signals BUSLK Bus Lock FSYNC Force Synchronization PWM3EN Pulse Width Modulation Select PWM2EN Pulse Width Modulation Select PWM1EN Pulse Width Modulation Select

IRQ0EN Flag0 in IRQx Mode IRQ1EN Flag1 in IRQx Mode IRQ2EN Flag2 in IRQx Mode TMREXPEN Flag3 in TMPEXP Mode MSEN Memory Select Enable EPDATA (2321) Data Pin Mode Select PWM0EN Pulse Width Modulation Select

Figure A-1. SYSCTL Register

ADSP-214xx SHARC Processor Hardware Reference

A-5

System and Power Management Registers

Table A-2. SYSCTL Register Bit Descriptions (RW)

Bit 150 16 Name Description The bits are used for controlling core function. Refer to the SHARC Processor Programming Reference. IRQ0EN Flag0 Interrupt Mode. 0 = Flag0 pin is a general-purpose I/O pin. Permits core writes. 1 = Flag0 pin is allocated to interrupt request IRQ0. Flag1 Interrupt Mode. 0 = Flag1 pin is a general-purpose I/O pin. Permits core writes. 1 = Flag1 pin is allocated to interrupt request IRQ1. Flag2 Interrupt Mode. 0 = Flag2 pin is a genera-purpose I/O pin. Permits core writes. 1 = Flag2 pin is allocated to interrupt request IRQ2. Flag Timer Expired Mode. 0 = Flag3 pin is a general-purpose I/O pin. Permits core writes. 1 = Flag3 pin output is timer expired signal (TMREXP). Memory Select Enable. Selects between FLGx/AMI_MSx/IRQx or TMREXP. Together with bits 1918 generate a truth table. Detailed modes of programming for these bits are given in Core FLAG Pins Multiplexing on page 24-28. 0 = FLAG/IRQx pins are selected 1 = Enables FLAG2 and 3 (IRQ2 and TIMEXP) as MS2 and 3 AMI Mode Select. Selects between multiplexed AMI, Flags, PWM and PDAP interfaces on the AMI bus. For detailed programming modes for these bits, see Multiplexed External Port Pins on page 24-30. Pulse Width Modulation Select. When set (=1), enables PWM30. For more information, see Pin Multiplexing on page 24-28. Reserved for ADSP-2147x and ADSP-2148x. Pulse Width Modulation Select. When set (=1), enables PWM74. For more information, see Pin Multiplexing on page 24-28. Pulse Width Modulation Select. When set (=1), enables PWM118. For more information, see Pin Multiplexing on page 24-28.

17

IRQ1EN

18

IRQ2EN

19

TMREXPEN

20

MSEN

2321

EPDATA

24

PWM0EN

25

PWM1EN

26

PWM2EN

A-6

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-2. SYSCTL Register Bit Descriptions (RW) (Contd)

Bit 27 Name PWM3EN Description Pulse Width Modulation Select. When set (=1), enables PWM1512. For more information, see Pin Multiplexing on page 24-28. Force Synchronization of the Shared Memory Bus (ADSP-2146x only). 0 = Do not force synchronization of multiple processors arbitration in the system. 1 = Force synchronization of multiple processor arbitration in the system. Used for synchronization of DSPs in a multiple processor system, after reprogramming of PLL to another clock ratio. Clear this bit after sync achieved (allow enough time for the PLL to settle and lock to new ratio). Bus Lock Request (ADSP-2146x only). Requests bus lock where the processor maintains bus master control if set, (=1) or does not request bus lock (normal bus master control) if cleared (=0). Enable PWM Signals on the DPI Pins. Enables the PWM signals on DPI pins. When this bit is set (=1), the flags (415) which are routed to the DPI pins can be used as PWM signals. Applicable only for ADSP-2148x and ADSP-2147x processors.

28

FSYNC

29

BSLK

30

PWMONDPIEN

31

Reserved

Power Management Registers (PMCTL, PMCTL1)

The following sections describe the registers associated with the processors power management functions. The PMCTL register, shown in Figure A-2 is a 32-bit memory-mapped register. This register contains bits to control phase lock loop (PLL) multiplier and divider (both input and output) values, PLL bypass mode, and clock control for enabling peripherals (see Table A-3 on page A-8). This register also contains status bits, which keep track of the status of the CLK_CFG pins (RO). The reset value of PMCTL is dependent on the CLK_CFG pins (bits 50 and 1716).

ADSP-214xx SHARC Processor Hardware Reference

A-7

System and Power Management Registers

The PMCTL1 register, shown in Figure A-3 and described in Table A-4, contains the bits for shutting down the clocks to various peripherals and selecting one of the three FIR/IIR/FFT accelerators.

Writes to this register have an effect latency of two

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PCLK

cycles.

LCKR (2221) Link Port Clock Ratio (ADSP-2146x only)

CRAT (1716) PLL Clock Ratio EPCKR Core Clock to EP Clock

15 14 13 12

11 10

PLLBP PLL Bypass DIVEN PLL Divider Enable

PLLM (50) PLL Multiplier PLLD (76) PLL Divider INDIV Input Divider

Figure A-2. PMCTL Register Table A-3. PMCTL Register Bit Descriptions (RW)
Bit 50 Name PLLM Description PLL Loop Pre multiplier. PLLM = 0 PLL multiplier = 128 0<PLLM<63 PLL multiplier = 2 PLLM Reset value = CLK_CFG[1:0] ADSP-2146x Settings ADSP-2147x2148x Settings 00 = 000110 = 6x 00 = 000110 = 8x 01 = 100000 = 32x 01 = 100000 = 32x 10 = 010000 = 16x 10 = 010000 = 16x 11 = 000110 (Reserved) 11 = 000110 (Reserved)

A-8

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-3. PMCTL Register Bit Descriptions (RW) (Contd)

Bit 76 Name PLLD Description PLL Divider (Output Post Divider). 00 = clock divider = 2 01 = clock divider = 4 10 = clock divider = 8 11 = clock divider = 16 PLL Input Clock Pre Divider. 0 = Divide by 1 1 = Divide by 2 Output Clock Divider Change Enable. Enables the post divider to allow core and peripheral clock variations. 0 = Post divider is disabled 1 = Post divider is enabled for the PLLD, SDCKR, DDR2CKR and LCKR bits. When the PLL is programmed using the multipliers and the post dividers, the DIVEN and PLLBP bits should NOT be programmed in the same core clock cycle. Note that this bit is self clearing.

INDIV

9 (RW1S)

DIVEN

1110 12

Reserved CLKOUTEN Clockout Enable. Mux select for CLKOUT and RESETOUT. 0 = Mux output = RESETOUT 1 = Mux output = CLKOUT The CLKOUT functionality is not characterized and only used for test purposes.

1413 15

Reserved PLLBP PLL Bypass Mode Indication. 0 = PLL is in normal mode 1 = Put PLL in bypass mode PLL Hardware Configuration Ratio, CLK_CFG10 pins. After reset, both CLK_CFG pins define the CLKIN to core clock ratio. This ratio can be changed with the PLLM and PLLD bits. CRAT = CLK_CFG[1:0] ADSP-2146x Settings ADSP-2147x/2148x Settings 00 = 6x 00 = 8x 01 = 32x 01 = 32x 10 = 16x 10 = 16x 11 = (Reserved) 11 = (Reserved)

1716 (RO)

CRAT

ADSP-214xx SHARC Processor Hardware Reference

A-9

System and Power Management Registers

Table A-3. PMCTL Register Bit Descriptions (RW) (Contd)

Bit 2018 Name EPCKR Description External Port Clock Ratio. Core clock to AMI/SDRAM or DDR2 clock. For DDR2 clock 125 MHz is min. ADSP-2146x Settings ADSP-2147x/2148x Settings 000 = RATIO = 2.0 000 = RATIO = 2.0 010 = RATIO = 3.0 001 = RATIO = 2.5 100 = RATIO = 4.0 (AMI only) 010 = RATIO = 3.0 all other settings = reserved 011 = RATIO = 3.5 100 = RATIO = 4.0 all other settings = reserved Link Port Clock Ratio. Core clock to link port clock (ADSP-2146x only). 00 = RATIO = 2.0 01 = RATIO = 2.5 10 = RATIO = 3.0 (default) 11 = RATIO = 4.0

2221

LCKR

3123

Reserved

A-10

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

MLBOFF MLB Clock Shutdown ACCSEL (1817) Accelerator Select

ACCOFF Accelerator Clocks Shutdown

15 14 13 12

11 10

LP1OFF LP1 Clock Shutdown (ADSP-2146x) RTCOFF RTC Clock Shutdown (ADSP-2147x/ADSP-2148x) LP0OFF LP0 Clock Shutdown (ADSP-2146x) TMROFF Timer Clock Shutdown SPIOFF SPI Clock Shutdown SP67OFF SP6/7 Clock Shutdown SP45OFF SP4/5 Clock Shutdown SP23OFF SP2/3 Clock Shutdown

UART0POFF UART Clock Shutdown TWIOFF TWI Clock Shutdown PWMOFF PWM Clock Shutdown DTCPOFF DTCP Clock Shutdown DAIOFF Shutdown Clock to DAI Peripherals EPOFF EP Clock Shutdown SP01OFF SP0/1 Clock Shutdown

Figure A-3. PMCTL1 Register Table A-4. PMCTL1 Register Bit Descriptions (RW)
Bit 0 Name UART0OFF Description Shutdown Clock to UART. 0 = UART is in normal mode 1 = Shutdown clock to UART Shutdown Clock to TWI. 0 = TWI is in normal mode 1 = Shutdown clock to TWI Shutdown Clock to PWM30. 0 = PWM is in normal mode 1 = Shutdown clock to PWM

TWIOFF

PWMOFF

ADSP-214xx SHARC Processor Hardware Reference

A-11

System and Power Management Registers

Table A-4. PMCTL1 Register Bit Descriptions (RW) (Contd)

Bit 3 Name DTCPOFF Description Shutdown Clock to MTM/DTCP. 0 = MTM is in normal mode 1 = Shutdown clock to MTM Shutdown Clock to DAI. Shutdown clock to DAI related peripheralsASRC, S/PDIF, PCGAD, IDP, PDAP and DAI routing registers SRU. 0 = DAI is in normal mode 1 = Shutdown clock to DAI Shutdown Clock to External Port (AMI/SDRAM/DDR2). 0 = External port is in normal mode 1 = Shutdown clock to external port Shutdown Clock to SPORT 0, 1. 0 = SPORTs in normal mode 1 = Shutdown clock to SPORTs Shutdown Clock to SPORT 2, 3. 0 = SPORTs in normal mode 1 = Shutdown clock to SPORTs Shutdown Clock to SPORT 4, 5. 0 = SPORTs in normal mode 1 = Shutdown clock to SPORTs Shutdown Clock to SPORT 6, 7. 0 = SPORTs in normal mode 1 = Shutdown clock to SPORTs Shutdown Clock to SPI/SPIB. 0 = SPI in normal mode 1 = Shutdown clock to SPI Shutdown Clock to Peripheral Timers 0/1. 0 = Timer is in normal mode 1 = Shutdown clock to timer Shutdown Clock to Link Port 0. 0 = LP0 is in normal mode 1 = Shutdown clock to LP0 This bit is reserved for the ADSP-2147x and ADSP-2148x)

DAIOFF

EPOFF

SP01OFF

SP23OFF

SP45OFF

SP67OFF

10

SPIOFF

11

TMROFF

12

LP0OFF

A-12

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-4. PMCTL1 Register Bit Descriptions (RW) (Contd)

Bit 13 Name LP1OFF/ RTCOFF Description Shutdown Clock to Link Port 1 (ADSP-2146x). 0 = LP1 is in normal mode 1 = Shutdown clock to LP1 Shutdown Clock to Real Time Clock (ADSP-2147x/ADSP-2148x). 0 = RTC is in normal mode 1 = Shutdown clock to RTC

1514 16

Reserved ACCOFF Shutdown Clock to Accelerator. 0 = Accelerator is in normal mode 1 = Shutdown clock to accelerator Accelerator Select. 00 = Select FIR 01 = Select IIR 10 = Select FFT 11 = Reserved Shutdown Clock to Media Local Bus. 0 = MLB is in normal mode 1 = Shutdown clock to MLB

1817

ACCSEL

19

MLBOFF

3120

Reserved

Running Reset Control Register (RUNRSTCTL)

The RUNRSTCTL register is used to control the running reset functionality and is described in Table A-5.

ADSP-214xx SHARC Processor Hardware Reference

A-13

Programmable Interrupt Priority Control Registers

Table A-5. Running Reset Control Register Bit Descriptions (RW)

Bit 0 Name PM_RUNRST_PINEN Description Configures the RESETOUT pin for RUNRST input. 0 = RESETOUT pin is RESETOUT 1 = RESETOUT pin is RUNRST input Enable the Running Reset Functionality. If this bit is cleared, attempting to cause a running reset by toggling the RUNRSTIN pin has no affect. 0 = Running reset disabled 1 = Running reset enabled

PM_RUNRST_EN

312

Reserved

Programmable Interrupt Priority Control Registers

The processor core supports 19 programmable prioritized interrupts. Any peripheral interrupt output may be connected to any programmable priority interrupt input. Table A-6 lists the sources.

Source Signals
Table A-6. Default Interrupt Routing
Selection Code Source (Peripheral) Description Destination (Default Programmable Interrupt) P0I P1I P2I P3I P4I

00000 (0x0) 00001 (0x1) 00010 (0x2) 00011 (0x3) 00100 (0x4)

DAIHI SPIHI GPTMR1I SP1I SP3I

DAI high priority SPI high priority GP Timer 0 SPORT1 SPORT3

A-14

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-6. Default Interrupt Routing (Contd)

Selection Code Source (Peripheral) Description Destination (Default Programmable Interrupt) P5I P6I P7I P8I P9I P10I P11I P12I P13I P14I P15I P16I P17I SPI B low priority UART0 receive P18I

00101 (0x5) 00110 (0x6) 00111 (0x7) 01000 (0x8) 01001 (0x9) 01010 (0xA) 01011 (0xB) 01100 (0xC) 01101 (0xD) 01110 (0xE) 01111 (0xF) 10000 (0x10) 10001 (0x11) 10010 (0x12) 10011 (0x13) 10100 (0x14) 10101 (0x15) 10110 (0x16) 10111 (0x17) 11000 (0x18) 11001 (0x19) 11010 (0x1A) 11011 (0x1B) 11100 (0x1C) 11101 (0x1D)

SP5I SP0I SP2I SP4I EPDM0I GPTMR1I SP7I DAILI EPDM1I DPII MTMI SP6I Disabled SPILI UART0RxI Disabled UART0TxI Disabled TWII PWMI LP0I/RTCI LP1I ACC0I ACC1I MLBI

SPORT5 SPORT0 SPORT2 SPORT4 External port DMA0 GP Timer 1 SPORT7 DAI low priority External Port DMA1 DPI Memory-to-Memory SPORT6

UART0 transmit

Two Wire Interface Pulse Width Modulator Link port0/Real time clock Link port 1 Accelerator DMA Accelerator MAC Media Local Bus

ADSP-214xx SHARC Processor Hardware Reference

A-15

Programmable Interrupt Priority Control Registers

Table A-6. Default Interrupt Routing (Contd)

Selection Code Source (Peripheral) Description Destination (Default Programmable Interrupt)

11110 (0x1E) 11111 (0x1F)

Disabled Software Select logic level high (1)

Destination Signal Control Registers (PICRx)

This 32-bit read/write registers, shown in Figure A-4 through Figure A-7, control programmable priority interrupts and default interrupt sources. An example is shown below.
31 30 29 28 0 0 0 0 27 26 25 24 0 0 0 0 23 22 0 0 21 20 0 0 19 18 17 16 0 0 0 0

P5I (2925) Programmable Interrupt 5 P4I (2420) Programmable Interrupt 4

P3I (1915) Programmable Interrupt 3

15 14 13 12 11 10 0 0 0 0 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

P3I (1915) P2I (1410) Programmable Interrupt 2 P0I (40) Programmable Interrupt 0 P1I (95) Programmable Interrupt 1

Figure A-4. PICR0 Register

A-16

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30 29 28 0 0 0 0

27 26 25 24 0 0 0 0

23 22 0 0

21 20 0 0

19 18 17 16 0 0 0 0

P11I (2925) Programmable Interrupt 11 P10I (2420) Programmable Interrupt 10

P9I (1915) Programmable Interrupt 9

15 14 13 12 11 10 0 0 0 0 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

P9I (1915) P8I (1410) Programmable Interrupt 8 P6I (40) Programmable Interrupt 6 P7I (95) Programmable Interrupt 7

Figure A-5. PICR1 Register

31 30 29 28 0 0 0 0 27 26 25 24 0 0 0 0 23 22 0 0 21 20 0 0 19 18 17 16 0 0 0 0

P17I (2925) Programmable Interrupt 17 P16I (2420) Programmable Interrupt 16

P15I (1915) Programmable Interrupt 15

15 14 13 12 11 10 0 0 0 0 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

P15I (1915) P14I (1410) Programmable Interrupt 14 P12I (40) Programmable Interrupt 12 P13I (95) Programmable Interrupt 13

Figure A-6. PICR2 Register

ADSP-214xx SHARC Processor Hardware Reference

A-17

Programmable Interrupt Priority Control Registers

31 30 29 28 0 0 0 0

27 26 25 24 0 0 0 0

23 22 0 0

21 20 0 0

19 18 17 16 0 0 0 0

15 14 13 12 11 10 0 0 0 0 0 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

P18I (40) Programmable Interrupt 18

Figure A-7. PICR3 Register

DAI/DPI Interrupt Control Registers

The DAI interrupt registers are listed in Table A-7 and shown in Figure A-8. Note that for each of these registers the bit names and numbers are the same. Table A-7. DAI Interrupt Registers
Register DAI_IRPTL_H (ROC) DAI_IRPTL_HS (RO) DAI_IRPTL_L (ROC) DAI_IRPTL_LS (RO) DAI_IMASK_PRI (RW) DAI_IMASK_RE (RW) DAI_IMASK_FE (RW) Description High priority interrupt latch register Shadow high priority interrupt latch register Low priority interrupt latch register Shadow low priority interrupt latch register Core interrupt priority assignment register Rising edge interrupt mask register Falling edge interrupt mask register

A-18

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DAI_31_INT DAI_30_INT DAI_29_INT DAI_28_INT DAI_27_INT DAI_26_INT DAI_25_INT DAI_24_INT

IDP_DMA6_INT IDP_DMA7_INT SRC0_MUTE_INT SRC1_MUTE_INT SRC2_MUTE_INT SRC3_MUTE_INT DAI_22_INT DAI_23_INT

15 14 13 12

11 10

IDP_DMA5_INT IDP_DMA4_INT IDP_DMA3_INT IDP_DMA2_INT IDP_DMA1_INT IDP_DMA0_INT IDP_FIFO_OVR_INT IDP_FIFO_GTN_INT

DIR_VALID_INT DIR_LOCK_INT DIR_NOSTREAM_INT DIR_CRCERROR_INT DIR_NOAUDIO_INT DIR_EMPHASIS_INT DIR_ERROR_INT DIR_STATCNG_INT

Figure A-8. DAI Interrupt Latch/Mask register The DPI interrupt registers are shown in Figure A-9 and listed in Table A-8. Note that for each of these registers the bit names and numbers are the same. Table A-8. DPI Interrupt Registers
Register DPI_IRPTL (ROC) DPI_IRPTL_SH (RO) DPI_IMASK_RE (RW) DPI_IMASK_FE (RW) Description Interrupt Latch Register Shadow Interrupt Latch Register Rising Edge Interrupt Mask Register Falling Edge Interrupt Mask Register

ADSP-214xx SHARC Processor Hardware Reference

A-19

External Port Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

15 14 13 12

11 10

DPI_13_INT DPI_12_INT DPI_11_INT DPI_10_INT DPI_09_INT DPI_08_INT

UART0_TX_INT UART0_RX_INT TWI_INT DPI_05_INT DPI_06_INT DPI_07_INT

Figure A-9. DPI Interrupt Latch/Mask Register

External Port Registers

The registers in the following sections include the external port, the DDR2/SDRAM controller, and the AMI registers.

External Port Control Register (EPCTL)

The following registers are used to control the asynchronous memory interface (AMI), the DDR2 and SDRAM controller, and the shared memory interface. Bits 03 select a DRAM memory bank. For the ADSP-2146x processors the memory is DDR2. For the ADSP-2147x and ADSP-2148x processors the memory is SDRAM. The external port control register can be programmed to arbitrate the accesses between the processor core and DMA, and between different DMA channels. This register is shown in Figure A-10 and described in Table A-9.

A-20

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

FRZSP (2119) Arbitration Freezing Length for SPORT DMA

DATEN (1815) Data Mask Enable

15 14 13 12

11 10

DATEN (1815) FRZCR (1412) Arbitration Freezing Length for CORE Accesses FRZDMA (108) Arbitration Freezing Length for DMA DMAPR (76) DMA Channel Priority for CH0 and CH1 EPBR (54) External Port Bus Priority

B0SD Bank 0 Memory B1SD Bank 1 Memory B2SD Bank 2 Memory B3SD Bank 3 Memory

Figure A-10. EPCTL Register Table A-9. EPCTL Register Bit Descriptions (RW)
Bit 0 Name B0SD Description Select Bank 0 Memory. 0 = Bank 0 non-DRAM 1 = Bank 0 DDR2 for 2146x/SDRAM for 2147x/8x Select Bank 1 Memory. 0 = Bank 1 Non-DRAM 1 = Bank 0 DDR2 for 2146x/SDRAM for 2147x/8x Select Bank 2 Memory. 0 = Bank 2 Non-DRAM 1 = Bank 0 DDR2 for 2146x/SDRAM for 2147x/8x Select Bank 3 Memory. 0= Bank 3 Non-DRAM 1 = Bank 0 DDR2 for 2146x/SDRAM for 2147x/8x

B1SD

B2SD

B3SD

ADSP-214xx SHARC Processor Hardware Reference

A-21

External Port Registers

Table A-9. EPCTL Register Bit Descriptions (RW) (Contd)

Bit 54 Name EPBR Description External Port Bus Priority. 00 = Priority order from highest to lowest is SPORT, external port DMA, core 01 = Priority order from highest to lowest is external port DMA, SPORT, core 10 = Highest priority is core. SPORT and external port DMA are in rotating priority 11 = Rotating priority (default) External Port DMA Channel Priority. 00 = Reserved 01 = Reserved 10 = EP DMA channel 0 high priority 11 = Rotating priority (default) Arbitration Freezing Length for DMA. 000 = No Freezing 001 = 4 Accesses 010 = 8 Accesses 011 = 16 Accesses 100 = 32 Accesses 101 = Page size (DDR2/SDRAM1) All others reserved

76

DMAPR

108

FRZDMA

11 1412

Reserved FRZCR Arbitration Freezing Length for CORE Accesses. 000 = No Freezing 001 = 4 Accesses 010 = 8 Accesses 011 = 16 Accesses 100 = 32 Accesses 101 = Page size (DDR2/SDRAM1) All others reserved

A-22

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-9. EPCTL Register Bit Descriptions (RW) (Contd)

Bit 1815 Name DATEN Description External Port Data Mask Enable (ADSP-2147x/ADSP-2148x). In packing disable mode (PKDIS=0) the AMI memory controller masks byte wise data with zeros. The 16-bit data bus has two bytes of data. For example, if DATEN10 is 01, data byte 0 is masked with zeros and so on. 0000 = no effect 0001 = Data70 is zero 0010 = Data158 is zero 0011 = Data150 are zero All other settings reserved These bits are reserved for the ADSP-2146x models. Arbitration Freezing Length for SPORT DMA. 000 = No Freezing 001 = 4 Accesses 010 = 8 Accesses 011 = 16 Accesses 100 = 32 Accesses 101 = Page size (DDR2/SDRAM1) All others reserved

2119

FRZSP

3122 1

Reserved

The EPCTL register automatically reads the DRAM controller page size setting (DDR2 or SDRAM).

External Port DMA Control Registers (DMACx)

The DMAC01 registers control the DMA function of their respective DMA channels as described in Operating Modes on page 4-122. These registers apply to all processors described in this manual and are shown in Figure A-11 and described in Table A-10.

ADSP-214xx SHARC Processor Hardware Reference

A-23

External Port Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DIRS DMA Transfer Direction Status EXTS DMA External Interface Status WBS Delay Line Write Back Status

DFS (1716) DMA FIFO Status DMAS DMA Transfer Status CHS DMA Chaining Status TLS Tap List Loading Status

15 14 13 12

11 10

INTIRT Internal DMA Completion interrupt (Control) TLEN Tap List DMA Enable OFCEN On the Fly Control Loading Enable WRBEN Enable Write Back of EPEI After Reads/Writes DFLSH Flush DMA FIFO

DEN DMA Enable TRAN DMA Direction CHEN Chaining Enable DLEN Delay Line DMA Enable CBEN Circular Buffering Enable

Figure A-11. DMACx Registers Table A-10. External Port DMA Register Bit Descriptions (RW)
Bit 0 Name DEN Description DMA Enable. 0 = External port channel x DMA is disabled 1 = Enable External port DMA for channel x DMA Direction. Determines the DMA data direction. For internal to internal transfers, TRAN must be set. 0 = Write to internal memory (external reads) 1 = Read from internal memory (external writes) Note: If delay line DMA is enabled then the TRAN bit doesnt have any effect. For delay line DMA, transfer direction depends on the state of delay line transfers. Enable Chaining. 0 = Chaining disabled 1 = Chaining enabled

TRAN

CHEN

A-24

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-10. External Port DMA Register Bit Descriptions (RW) (Contd)
Bit 3 Name DLEN Description Enable Delay Line DMA. DLEN is applicable only if CHEN=1. 0 = Delay-line DMA disabled 1 = Delay-line DMA enabled Circular Buffering Enable. 0 = Disables circular buffering with delay line DMA 1 = Enables circular buffering with delay line DMA Circular buffering can be used with normal DMA as well, if circular buffering is enabled with chaining in normal DMA then ELEP and EBEP should be part of the TCB. Flush DMA FIFO. The buffer is only flushed if this bit is set. It can be set with the enable bit. It takes 6 core cycles to flush the buffer. Also clears the DFS bit.

CBEN

5 (RW1S)

DFLSH

6 7

Reserved WRBEN Enable Write Back of EIEP After Reads/Writes. Write back is automatically enabled for delay line DMA. WRBEN is applicable only if chaining is enabled (CHEN = 1) On the Fly Control Loading Enable. The control bits in CPEP register are used to describe the next TCB behavior if OFCEN is set and therefore the DMA controls can be changed from TCB to TCB. 0 = Disables the control bits in CPEP register 1 = Enables the control bits in CPEP register. Note if chaining is enabled with OFCEN bit set then TRAN bit has no effect, and direction is determined by CPD bit in CPEP register. Scatter/Gather (Tap List) DMA Enable. 0 = Disables the tap list based scatter/gather DMA 1 = Enables the tap list based scatter/gather DMA

OFCEN

TLEN

1110 12

Reserved INTIRT Internal DMA Completion Interrupt (Control). 0 = Interrupt on access completion (internal/external DMA completion depending on external read/write) 1 = Interrupt on internal DMA completion This bit is provided for backward compatibility with older SHARC processors.

1513

Reserved

ADSP-214xx SHARC Processor Hardware Reference

A-25

External Port Registers

Table A-10. External Port DMA Register Bit Descriptions (RW) (Contd)
Bit 1716 (RO) Name DFS Description DMA FIFO Status. 00 = FIFO empty 01 = FIFO partially full 11 = FIFO full 10 = Reserved

1918 20 (RO)

Reserved DMAS DMA Transfer Status. 0 = DMA idle 1 = DMA in progress DMA Chaining Status. 0 = DMA chain loading is not active 1 = DMA chain loading is active TAP List Loading Status. 1 = TAP list loading is active 0 = TAP list loading is not active Delay Line Write Pointer Write Back Status. 0 = Write pointer write back is not active 1 = Write pointer write back is active DMA External Interface Status. 0 = DMA external interface does not have any access pending 1 = DMA external interface has access pending DMA Transfer Direction Status. 0 = DMA direction is external reads 1 = DMA direction is external writes This is useful for delay line DMA where the transfer direction changes with the state of the DMA state machine. For standard DMA, DIRS reflects the state of the TRAN bit.

21 (RO)

CHS

22 (RO)

TLS

23 (RO)

WBS

24 (RO)

EXTS

25 (RO)

DIRS

3126

Reserved

A-26

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Asynchronous Memory Interface Registers (AMI)

The next two sections describe the control and status registers for the AMI. AMI Control Registers (AMICTLx) The AMICTL03 registers control the mode of operations for the four banks of external memory. This register is shown in Figure A-12 and described in Table A-11. Note for all AMI timing bit settings, all defined cycles are derived from the SDRAM clock.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PREDIS Disable Predictive Reads RHC (2018) Read Hold Cycle

IC Bus Idle Cycle FLSH AMI Buffer Flush

15 14 13 12

11 10

IC (1614) HC (1311 Bus Hold Cycle WS (106) Wait States ACKEN ACK Pin Enable MSWF Most Significant Word First

AMIEN AMI Enable BW External Data Bus Width PKDIS Packing/Unpacking Disable

Figure A-12. AMICTLx Registers

ADSP-214xx SHARC Processor Hardware Reference

A-27

External Port Registers

Table A-11. AMICTLx Register Bit Descriptions (RW)

Bit 0 Name AMIEN Description AMI Enable. Enables the AMI controller for the dedicated external bank. 0 = AMI is disabled 1 = AMI is enabled To access an external memory bank, the AMIEN bit in the corresponding AMICTLx register has to be set. If any of the AMIEN bits are set, then the AMI is enabled and can access memory. However, bank selects cannot be driven for that bank whose AMIEN is not set (but read/write strobes can occur). Any access made to a bank whose AMIEN bit is not set occurs at WS = 2 and 8-bit mode without any hold/idle cycles. In any case this access occurs without the bank select and is a void access. Moreover, the AMIEN bit should not be cleared when an access is on-going (when the AMIS bit in the AMISTAT register is set). External Data Bus Width (ADSP-2147x/ADSP-2148x). 00 = 8-bit 01 = 16-bit 10, 11 = Reserved These bits are reserved for the ADSP-2146x models. Packing Disable. 8/16-bit data received packed to 32-bit data. Similarly, 32-bit data to be transmitted is unpacked to two 16-bit data or four 8-bit data. For disable packing 8/16-bit data received zero-filled, for transmitted data only 16-bit or the 8-bit LSB part of the 32-bit data is written to external memory. ADSP-2146x Settings ADSP-2147x/2148x Settings 0 = 8 to 32 packing 0 = 8/16 to 32 packing 1 = no packing 1 = no packing Most Significant Word First. Applicable only with packing disabled (PKDIS=0). 1st 8/16-bit word read/write occupies the least significant position in the 32-bit packed word or 1st 8/16-bit word read/write occupies the most significant position in the 32-bit packed word. ADSP-2146x Settings ADSP-2147x/2148x Settings 0 = 1st 8 bit is LSW 0 = 1st 8/16 bit is LSW 1 = 1st 8 bit is MSW 1 = 1st 8/16 bit is MSW

21

BW

PKDIS

MSWF

A-28

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-11. AMICTLx Register Bit Descriptions (RW) (Contd)

Bit 5 Name ACKEN Description Enable the ACK pin. If enabled, reads/writes to devices must be extended by the corresponding devices by pulling ACK low. When ACKEN is set, then the ACK pin is sampled after the wait state value is programmed. Wait States. 00000 = Reserved (wait state value of 32 if used) 00001 = wait state = 1 (min if ACK input used) 00010 = wait state = 2 ... 11111 = Wait state = 31 Bus Hold Cycle at the End of Write Access. 000 = Disable bus hold cycle 001 = Hold address for one external port clock cycle 010 = Hold address for two external port clock cycles ... 111 = Hold address for seven cycles Bus Idle Cycle. Default Idle cycles are inserted whenever read to write in a bank or read to read between two external banks or a read to the SDC occurred. A bus idle cycle is an inactive bus cycle that the processor automatically generates to avoid data bus driver conflicts. Such a conflict can occur when a device with a long output disable time continues to drive after RD is deasserted, while another device begins driving on the following cycle. Idle cycles are also required to provide time for a slave in one bank to three-state its ACK driver, before the slave in the next bank enables its ACK driver. 000 = 0 idle cycles 001 = 1 idle cycle 111 = 7 idle cycles AMI Packing Buffer Flush. 0 = Buffer holds the data 1 = The buffer is only flushed if this bit is set. It can be set with the AMIEN bit. It takes four core cycles to flush the buffer.

106

WS

1311

HC

1614

IC

17 (RW1S)

FLSH

ADSP-214xx SHARC Processor Hardware Reference

A-29

External Port Registers

Table A-11. AMICTLx Register Bit Descriptions (RW) (Contd)

Bit 2018 Name RHC Description Read Hold Cycle. Controls the delay between two reads. 000 = Disable read hold cycle 001 = Hold address for one cycle ... 111 = Hold address for seven cycles Disable Predictive Reads. 0 = Predictive reads enabled 1 = Predictive reads disabled For more information, see Predictive Reads on page 4-26.

21

PREDIS

3122

Reserved

AMI Status Register (AMISTAT) This 32-bit, read-only register provides status information for the AMI interface and can be read at any time. This register is shown in Figure A-13 and described in Table A-12.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12

11 10

AMIS External Interface Status

AMIMS External Bus Master

Figure A-13. AMISTAT Register

A-30

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-12. AMISTAT Register Bit Descriptions (RO)

Bit 0 Name AMIMS Description AMI External Bus Master. ADSP-2146x Settings ADSP-2147x/2148x Settings 0 = Reserved 0 = SDRAM Controller 1 = AMI (always master*) 1 = AMI controller (default) *Since the AMI and DDR2 pins are independent on the ADSP-2146x products, AMIMS always reads 1. External Interface Status. 0 = AMI interface idle 1 = AMI access pending

21

AMIS

154

Reserved

SDRAM Registers
This section provides complete descriptions of the SDRAM controllers memory-mapped registers for SDRAM programming. Programs may write to the SDRAM control registers as long as the controller is not accessing memory devices. Otherwise, the controller responds to any writes to its registers after it finishes any ongoing memory accesses. Control Register (SDCTL) The SDRAM memory control register includes all programmable parameters associated with the SDRAM access timing and configuration. This register is shown in Figure A-14 and described in Table A-13.

ADSP-214xx SHARC Processor Hardware Reference

A-31

External Port Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

SDADDRMODE Address Map Mode PGSZ 128 Page size is 128 bits SDRAW (2927) Row Address Width STDRCD (2624) SDRAM tRCD Specification SDBUF Pipeline Option with External Register Buffer

X16DE SDRAM External Data Path Width SDTWR (1817) SDRAM tWR Specification SDORF Optional Refresh FAR Force Auto Refresh FPC Force Precharge Force LMR Force Auto Load Mode Register

15 14 13 12

11 10

SDSRF SDRAM Self Refresh Enable SDPSS SDRAM Power-up Sequence Start SDCAW (1312) SDRAM Bank Column Address Width SDPM SDRAM Power-Up Mode

SDCL (20) CAS Latency DSDCTL Disable SDCLK and Control Signals SDTRAS (74) SDRAM tRAS Specification SDTRP (108) SDRAM tRP Specification

Figure A-14. SDCTL Register

A-32

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-13. SDCTL Register Bit Descriptions (RW)

Bit 10 Name SDCL Description CAS Latency. 23 SDCLK cycles. The delay in clock cycles between when the SDRAM detects the read command and when it provides the data at its output pins. 00, 01 = Reserved 10 = 2 cycles (default) 11 = 3 cycles A CAS latency of 2 is supported only up to 133 MHz SDCLK. Disable Controller and Clocks. Used to enable or disable the SDC and its pins. If DSDCTL is set, any access to SDRAM address space does not occur externally and all SDC control pins are in their inactive states and the SDRAM clock is not running. 0 = Active 1 = Disabled When not using SDRAM or when using parts without an external port, systems should set this bit as early as possible after booting to reduce power consumption. If the SDSRA bit is set (self-refresh), setting the DSDCTL bit freezes the SDCLK to reduce power.

DSDCTL

3 74

Reserved SDTRAS tRAS Specification. Row Active Open Delay is 115 SDCLK cycles. Based on the system clock frequency and the timing specifications of the SDRAM used. Programmed parameters apply to all four banks in the external memory. Refer to the SDRAM data sheet. tRP Specification. Row Precharge Delay is 18 SDCLK cycles. Based on the system clock frequency and the timing specifications of the SDRAM used. Programmed parameters apply to all four banks in the external memory. Refer to the SDRAM data sheet. Power-Up Mode. The SDPM and SDPSS bits work together to specify and trigger an SDRAM power-up (initialization) sequence. If the SDPM bit is set (=1), the SDC performs a precharge all command, followed by a load mode register command, followed by eight auto-refresh cycles. If the SDPM bit is cleared (=0), the SDC performs a precharge all command, followed by eight auto-refresh cycles, followed by a load mode register command. Refer to the SDRAM data sheet.

108

SDTRP

11

SDPM

ADSP-214xx SHARC Processor Hardware Reference

A-33

External Port Registers

Table A-13. SDCTL Register Bit Descriptions (RW) (Contd)

Bit 1312 Name SDCAW Description Bank Column Address Width. The number of columns in an internal bank. Also referred to as page size. 00 = 8 bits 01 = 9 bits 10 = 10 bits 11 = 11 bits Power-Up Sequence Start. The power-up sequence is triggered by setting this bit. Note that there is a latency for this first access to SDRAM because the SDRAM power-up sequence takes many cycles to complete. 0 = No effect 1 = Enable power-up on next SDRAM access Self-Refresh Enable. When the SDSRF bit is set to 1, self-refresh entry command is triggered. Once the SDC completes any active transfers, the SDC executes the sequence of commands to put the SDRAM into self-refresh mode. Any access to the enabled SDRAM bank causes the SDC to trigger a self-refresh exit command. External 16-bit Data Path Width. Programs should always set (=1) this bit. 0 = Reserved 1 = 16-bit tWR Specification. Write To Precharge Delay) is 13 SDCLK cycles. Based on the system clock frequency and the timing specifications of the SDRAM used. Programmed parameters apply to all four banks in the external memory. Refer to the SDRAM data sheet. Optional Auto-Refresh Command. 0 = Auto-refresh occurs when refresh counter expires 1 = Auto-refresh not performed Force Auto-Refresh Command. Performs an auto-refresh immediately. 0 = No effect 1 = Force auto-refresh

14 (RW1S)

SDPSS

15 (RW1S)

SDSRF

16

X16DE

1817

SDTWR

19

SDORF

20 (RW1S)

FAR

A-34

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-13. SDCTL Register Bit Descriptions (RW) (Contd)

Bit 21 (RW1S) 22 (RW1S) Name FPC Description Force Precharge. Performs a precharge all immediately. 0 = No effect 1 = Force precharge Force Load Mode Register Command. This command performs a load mode register command immediately. 0 = No effect 1 = Force MR Pipeline Option with External Register Buffer. 0 = No buffer option 1 = External SDRAM CTL/ADDR control buffer enable tRCD Specification. RAS to CAS Delay is = 17 SDCLK cycles. Based on the system clock frequency and the timing specifications of the SDRAM used. Programmed parameters apply to all four banks in the external memory (0x1 default). See the SDRAM data sheet. Row Address Width. 000=8, 001=9 010=10, 011=11 100=12, 101=13 110=14, 111=15 Page Size of 128 Words. This bit allows programs to configure the SDC for a page size of 128 words (7 bits) which supports most available 32 Mb SDRAMs. 0 = No effect, page size decided by SDCAW bits. 1 = Page size 128 words. Column width = 7 bits, override CAW settings. Select Address Mapping. This bit selects how data is stored in memory. 0 = Bank interleaving 1 = Page interleaving

FMR

23

SDBUF

2624

SDTRCD

2927

SDRAW

30

PGSZ 128

31

SDADDRMODE

ADSP-214xx SHARC Processor Hardware Reference

A-35

External Port Registers

Refresh Rate Control Register (SDRRC) The SDRAM refresh rate control register provides a flexible mechanism for specifying the auto-refresh timing. This register is shown in Figure A-15. For information on using the SMODIFY bit see SDRAM Read Optimization on page 4-57.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SDMODIFY(2017) Read Modifier

SDROPT Read Optimization Enable

15 14 13 12

11 10

RDIV (110) Average Refresh Interval

Figure A-15. SDRRC Register Table A-14. SDRRC Register Bit Descriptions (RW)
Bit 110 Name RDIV Description Refresh Interval. RDIV setting defines the average refresh interval between two subsequent refresh commands. The formula is shown in Refresh Rate Control on page 4-35. Note that the SDRAM manufacturer data sheets distinguish between commercial, industrial and automotive grades.

1512 16

Reserved SDROPT Read Optimization. If set (=1) enables read optimization to improve read throughput for core or external port DMA access. 0 = Disabled 1 = Enabled (default)

A-36

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-14. SDRRC Register Bit Descriptions (RW) (Contd)

Bit 2017 Name SDMODIFY Description SDRAM Read Modifier. According to SDROPT bit this bit should be set to match the DAG or DMA modifier. 0000 = 0 0001 = 1 (default) 1111 = 15

3121

Reserved

Control Status Register 0 (SDSTAT0) The SDRAM control status register provides information on the state of the SDC. This information can be used to determine when it is safe to alter SDC control parameters or as a debug aid. This register is shown in Figure A-16 and described in Table A-15.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

SDPEND SDRAM Pipeline Status SDRS SDRAM In Reset State

SDCI SDRAM Controller Idle SDSRA SDRAM Self-Refresh Active SDPUA SDRAM Power-Up Active

Figure A-16. SDSTAT0 Register Table A-15. SDSTAT0 Register Bit Descriptions (RO)
Bit 0 Name SDCI Description SDC Idle. This bit is set if the SDC is performing a command or auto-refresh. If no access, this bit is cleared. 0 = SDC idle 1 = SDC access

ADSP-214xx SHARC Processor Hardware Reference

A-37

External Port Registers

Table A-15. SDSTAT0 Register Bit Descriptions (RO) (Contd)

Bit 1 Name SDSRA Description SDC Self-Refresh Mode. If set, controller is in self-refresh mode. 0 = Non self-refresh mode (SDCKE pin high) 1 = Self-refresh mode (SDCKE pin low) SDC Power-Up Active. If set, controller is in power-up mode. 0 = Non power-up mode (SDPSS bit cleared in SDCTL) 1 = Power-up mode (SDPSS-bit set in SDCTL) SDC Reset State. If set, power-up sequence occurred. 0 = No power-up sequence 1 = Power-up sequence occurred

SDPUA

SDRS

54 6

Reserved SDPEND SDC Controller Pipeline Status. 0 = No access pending in controller pipeline 1 = Read/Write access pending in controller pipeline.

317

Reserved

Controller Status Register 1 (SDSTAT1) This register reports the SDRAM bank active/idle status. This register is shown in Figure A-17 and described in Table A-16.
31 30 29 28 27 26 25 24 11 10 9 8 23 22 7 6 21 20 19 18 17 16 5 4 3 2 1 0

15 14 13 12

Bit Field (1512) External Bank 1 Status Bit Field (118) External Bank 3 Status

Bit Field (30) External Bank 0 Status Bit Field (74) External Bank 2 Status

Figure A-17. SDSTAT1 Register

A-38

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-16. SDSTAT1 Register Bit Descriptions (RO)

Bit Field 30 Field Name External Bank 0 Status Description External Bank 0 Active/Precharge State. xxx1 = Internal bank 0 in open state xxx0 = Internal bank 0 in precharge state xx1x = Internal bank 1 in open state xx0x = Internal bank 1 in precharge state 1xxx = Internal bank 3 in open state 0xxx = Internal bank 3 in precharge state External Bank 0 Active/Precharge State. xxx1 = Internal bank 0 in open state xxx0 = Internal bank 0 in precharge state xx1x = Internal bank 1 in open state xx0x = Internal bank 1 in precharge state 1xxx = Internal bank 3 in open state 0xxx = Internal bank 3 in precharge state External Bank 0 Active/Precharge State. xxx1 = Internal bank 0 in open state xxx0 = Internal bank 0 in precharge state xx1x = Internal bank 1 in open state xx0x = Internal bank 1 in precharge state 1xxx = Internal bank 3 in open state 0xxx = Internal bank 3 in precharge state External Bank 0 Active/Precharge State. xxx1 = Internal bank 0 in open state xxx0 = Internal bank 0 in precharge state xx1x = Internal bank 1 in open state xx0x = Internal bank 1 in precharge state 1xxx = Internal bank 3 in open state 0xxx = Internal bank 3 in precharge state

74

External Bank 1 Status

118

External Bank 2 Status

1512

External Bank 3 Status

ADSP-214xx SHARC Processor Hardware Reference

A-39

External Port Registers

DDR2 Registers
This section provides complete descriptions of the DDR2 controllers memory-mapped registers for DDR2 programming Programs may write to the DDR2 control registers as long as the controller is not accessing memory devices. Otherwise, the controller responds to any writes to its registers after it finishes any ongoing memory accesses. DDR2 Control Register 0 (DDR2CTL0) The DDR DDR2CTL0 register includes the programmable parameters associated with the DDR configuration. Figure A-18 and Table A-17 show the corresponding control bit definitions.

The

and DDR2PSS bits are automatically cleared on the next clock edge cycle after they are set.

FEMRx, FLMR, FDLLCAL, FAR, FPC, SREF_EXIT, DDR2SRF,

A-40

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DDR2MODIFY (3128) Read Modifier DDR2OPT Read Optimization Enable SREF_EXIT Self Refresh Exit DDR2BUF Enable Pipeline FEMR Force EMR1 Register Write FLMR Force MR Register Write

DDR2WDTHx16 Must always be set to 1 for ADSP-2146x. FEMR3 Force EMR3 Register Write DDR2SRF Self Refresh Entry Mode DDR2ORF Disable Auto Refresh Mode FAR Force Auto Refresh FPC Force Precharge

15 14 13 12

11 10

DDR2PSS Powerup Start DDR2ADDRMODE Address Mapping Mode FDLLCAL Force On-chip DLL Calibration FEMR2 Force EMR2 Register Write DDR2RAW (119) DDR2 Row Address Width

DIS_DDR2CTL DDR2 Enable DIS_DDR2CLK1 Disable DDR2 Clock 1 DDR2BC (32) DDR2 Bank Count DIS_DDR2CKE DDR2 CKE Disable DDR2CAW (75) Bank Column Address Width SH_DLL_DIS Internal DLL Disable

Figure A-18. DDR2CTL0 Register

ADSP-214xx SHARC Processor Hardware Reference

A-41

External Port Registers

Table A-17. DDR2CTL0 Register Bit Descriptions (RW)

Bit 0 Name DIS_DDR2CTL Description Disable DDR2 Control Pins. If set, no accesses to external DDR2 DRAM address spaces occur. All associated control pins (DDR2 CLK, DDR2_RAS, DDR2_CAS, DDR2_WE, DDR2_CS, DDR2_ODT except DDR2_CKE) are in their inactive states 0 = Enable Control Pins 1 = Disable Control Pins This bit should not be set when DDR2 interface is active. It can be set in self-refresh mode to reduce pin power consumption. Disable DDR2 Clock 1. Used to disable the 2nd output clock of the controller. By default, both output clocks are driven. 0 = Activate 1 = Disable (default) Bank Count4 or 8 Bank Device. 00 = Reserved 01 = 4 Bank device 10 = 8 Bank device (default) 11 = Reserved Precharge Power-Down Mode. If set, the DDR2CKE signal is deasserted to bring the DDR2 into precharge power-down mode. Note that memory banks are not refreshed in this mode. 1 = Enter Precharge Power-down Mode 0 = Exit Precharge Power-down Mode Bank Column Address Width. Number of columns in an internal bank. Also referred to as page size. 000 = Page width 256 001 = Page width 512 010 = Page width 1024 011 = Page width 2048 100 = Page width 4096 Other values are reserved SHARC DDR2 Controller DLL Disable. Bypass on-chip DLL for debug mode only. 0 = Enable SHARC low/high byte DLL 1 = Disable SHARC low/high byte DLL

DIS_DDR2CLK1

32

DDR2BC

DIS_DDR2CKE

75

DDR2CAW

SH_DLL_DIS

A-42

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-17. DDR2CTL0 Register Bit Descriptions (RW) (Contd)

Bit 119 Name DDR2RAW Description Row Address Width. 000 = 8 bits 001 = 9 bits ... 111 = 15 bits Force EMR2 Register Write. Forces EMR2 only if the banks are all precharged. 0 = No effect 1 = Force EMR2 register write to DDR2 Force DLL External Bank Calibration. Triggers a calibration by multiple read commands for sensing the phase delay between internal DDR2 clocks and the received DQS signals. Only assigned external banks (EPCTL register) allow calibration. 0 = No effect 1 = Trigger DLL for external bank calibration

12 (RW1S)

FEMR2

13 (RW1S)

FDLLCAL

14

DDR2ADDRMODE Select the Address Mapping. This bit selects how the data are stored in the DDR2 memory. 0 = Page interleaving map (consecutive pages/different banks) 1 = Bank interleaving map (consecutive banks) DDR2PSS Power-Up Sequence Start. The power-up sequence is started by setting this bit. Note that the entire power-up sequence takes many cycles to complete. The more external banks assigned, the longer the power-up time. 0 = No effect 1 = Trigger power-up sequence Note that the power-up sequence does NOT require a memory access to be executed. If using forced commands, this bit should be cleared. External 16-bit Data Path Width. Programs should always set (=1) this bit. 0 = Reserved 1 = 16-bit Force EMR3 Register Write. Forces EMR3 only if the banks are all precharged. 0 = No effect 1 = Force EMR3 register write to DDR2

15 (RW1S)

16

DDR2WDTHx16

17 (RW1S)

FEMR3

ADSP-214xx SHARC Processor Hardware Reference

A-43

External Port Registers

Table A-17. DDR2CTL0 Register Bit Descriptions (RW) (Contd)

Bit 18 (RW1S) 19 Name DDR2SRF Description Self-Refresh Mode. 0 = No effect 1 = Enters self-refresh mode Auto-Refresh Command. If this bit is set, the auto-refresh command is not issue to the DDR2 memory. This mode allows data streaming connection to FPGA were the refresh is not required. 0 = Auto-refresh command occurs when refresh counter expires. 1 = Auto-refresh not performed Force Auto-Refresh. This bit allows programs to explicitly trigger an auto-refresh command. To use this bit requires that bit 21 is also set, otherwise the DDR2 may crash. 0 = No effect 1 = Force auto-refresh Force Precharge All. This bit allows programs to explicitly trigger a PREA command. 0 = No effect 1 = Force precharge Force Load Mode Register. Forces MR only if the banks are all precharged. 0 = No effect 1 = Force MR register write to DDR2 Force EMR1 Register Write. Forces EMR1 only if the banks are all precharged. 0 = No effect 1 = Force EMR1 register write to DDR2 Enable Pipeline. Enabled this bit if the nominal capacitive load is exceeded by connecting DDR2 chips in parallel (4 x IO4). 0 = Disable 1 = External DDR2 control/address buffer enable Self-Refresh Exit.

DDR2ORF

20 (RW1S)

FARF

21 (RW1S)

FPC

22 (RW1S)

FLMR

23 (RW1S)

FEMR

24

DDR2BUF

25 (RW1S)

SREF_EXIT

A-44

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-17. DDR2CTL0 Register Bit Descriptions (RW) (Contd)

Bit 27 Name DDR2OPT Description Read Optimization Enable. 0 = Disable read optimization 1 = Enable read optimization (default) Read Modifier (In Optimization Mode). 0000 = Modifier 0 0001 = Modifier 1 (default) 1111 = Modifier 15 Note that these bits only are only effective in SISD mode.

3128

DDR2MODIFY

DDR2 Timing Control Register 1 (DDR2CTL1) The DDR2CTL1 register includes the programmable parameters associated with the DDR access timing. Figure A-19 and Table A-18 show the DDR timing control bit definitions. All the values are defined in terms of number of DDR2 clock cycles.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DDR2TFAW (2925) tFAW Setting

DDR2TRTP (2119) tRTP Setting DDR2TRRD (2422) tRRD Setting

15 14 13 12

11 10

DDR2TRCD (1512) tRCD Setting DDR2TWTR (119) tWTR Setting

DDR2TRAS (40) tRAS Setting DDR2TRP (85) tRP Setting

Figure A-19. DDR2CTL1 Register

ADSP-214xx SHARC Processor Hardware Reference

A-45

External Port Registers

Table A-18. DDR2CTL1 Register Bit Descriptions (RW)

Bit 40 Name DDR2TRAS Description Row Active Time. 00000 = Reserved 00001 = 1 clock cycle 00010 = 2 clock cycles 11111 = 31 clock cycles (0x6 default) Row Precharge Time. Note that for 8 banked devices the timing spec becomes tRP + 1tCK. 0000 = Reserved 0001 = 1 clock cycle 0010 = 2 clock cycles 1111 = 15 clock cycles (0x3 default) Write to Read Delay. 000 = Reserved 001 = 1 clock cycle 010 = 2 clock cycles (default) 111 = 7 clock cycles RAS to CAS Delay. 000 = Reserved 001 = 1 clock cycle 010 = 2 clock cycles 111 = 7 clock cycles (0x3 default)

85

DDR2TRP

119

DDR2TWTR

1512

DDR2TRCD

1816 2119

Reserved DDR2TRTP Read to Precharge Delay. 000 = Reserved 001 = 1 clock cycle 010 = 2 clock cycles (default) 111 = 7 clock cycles

A-46

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-18. DDR2CTL1 Register Bit Descriptions (RW) (Contd)

Bit 2422 Name DDR2TRRD Description Row to Row Activation Delay. 000 = Reserved. 001 = 1 clock cycle (default) 010 = 2 clock cycles 111 = 7 clock cycles Force Activation Window. For 8 banked devices up to 4 banks open in activation window. For 4 banked devices the settings are ignored. 00000 = Reserved 00001 = 1 clock cycle 00010 = 2 clock cycles 11111 = 31 clock cycles (0xA default)

2925

DDR2TFAW

3130

Reserved

DDR2 Control Register 2 (DDR2CTL2) Figure A-20 and Table A-19 show the DDR2 control register 2 bit definitions. Values written into this register are loaded into the DDR2 mode register during power up (or when Force LMR bit in the DDR2CTL0 register is set). This register should be initialized before starting the Initialization sequence. contents should not be changed while ThisisregistersAlso whenever this register contents areDDR2 interface active. changed a initialization sequence must be executed to reflect this register contents in to the DDR2 mode register.

ADSP-214xx SHARC Processor Hardware Reference

A-47

External Port Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

15 14 13 12

11 10

DDR2MR (1514) Mode Register DDR2DTWR (119) Write Recovery Time DDR2DLLRST DLL Reset

DDR2BL (20) Burst Length DDR2CAS (64) CAS Latency

Figure A-20. DDR2CTL2 Register Table A-19. DDR2CTL2 Register Bit Descriptions (RW)
Bit 20 Name DDR2BL Description Burst Length. 010 = BL = 4 All other settings reserved. Burst Type. 0 = Sequential Other setting reserved. CAS Latency. 000 = Reserved 001 = Reserved 010 = 2 clock cycles (default) 111 = 7 clock cycles Test Mode. Bit cleared test mode is not supported. DLL DDR2 Memory Reset. Debug mode only. 0 = Normal 1 = Reset

DDR2BT

64

DDR2CAS

7 8 (RW1S)

Test mode DDR2DLLRST

A-48

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-19. DDR2CTL2 Register Bit Descriptions (RW) (Contd)

Bit 119 Name DDR2TWR Description Write Recovery Time. 000 = Reserved 001 = 2 clock cycle 010 = 3 clock cycles (default) ... 110 = 7 clock cycles 111 = Reserved This bit cleared, slow exit power-down not supported. Mode Register. Set to 00.

1312 1514 (RO) 3116

Active Power down Exit DDR2MR Reserved

DDR2 Control Register 3 (DDR2CTL3) The DDR2CTL3 register includes the programmable parameters associated with the DDR2 extended mode register (EMR1). Figure A-21 and Table A-20 show the bit definitions. All the values are defined in terms of number of clock cycles. Values written into this register are loaded into the DDR2 extended mode register during power up (or when Force EMR bit in DDR2CTL0 is set). This register should be initialized before starting the initialization sequence. contents should not be changed while DDR2 inter ThisisregistersAlso, whenever this registers contents are changed, face active. an initialization sequence must be executed to reflect this register contents in to the extended mode register.

ADSP-214xx SHARC Processor Hardware Reference

A-49

External Port Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

15 14 13 12

11 10

DDR2EXTMR1 (1514) Mode Register 1 DDR2OBDIS Output Buffer Disable DDR2DQSDIS DQS/DQS Enable DDR2ODT150 On Die Termination

DDR2DLLDIS Memory DLL Disable DDR2OPDS Output Drive Strength DDR2ODT75 On Die Termination DDR2AL (53) Additive Latency

Figure A-21. DDR2CTL3 Register Table A-20. DDR2CTL3 Register Bit Descriptions (RW)
Bit 0 Name DDR2DLLDIS Description DDR2 Memory DLL Disable. Debug mode only. 0 = Enable DDR2 low/high byte DLLs 1 = Disable DDR2 low/high byte DLLs DDR2 Memory Output Drive Strength for Data and DQS. 0 = Full strength 1 = Reduced strength Note the Output Drive Strength for DDR2 Controller is fixed to: full strength for Data and DQS half strength for CLK, ADDR and CMD Additive Latency. Additive latency reduces command bus conflicts to enable commands to be issued more efficiently. Note that the DDR2 controller performance is primary regardless of the AL settings. 000 = 0 clock cycles. 001 = 1 clock cycles. 101 = 5 clock cycles. 110, 111 = Reserved. See Additive Latency on page 4-102. On Die Termination Value. Bit 6 and 2 are required for truth table. 00 = ODT disabled 01 = 75 ohm 10 = 150 ohm 11 = 50 ohm

11

DDR2OPDS

53

DDR2AL

6, 2

DDR2ODT

A-50

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-20. DDR2CTL3 Register Bit Descriptions (RW) (Contd)

Bit 97 10 Name OCD Calibration Mode. DDR2DQSDIS Description All bits cleared. OCD calibration not supported. Differential DQS/DQS Disable. 0 = Enable DQS and DQS 1 = Disable DQS (default) Bit cleared, x8 read DQS not supported. Output Buffer Disable. 0 = Enable 1 = Disable Bit cleared Extended Mode Register 1. Set to 01.

11 12

RDQS Disable DDR2OBDIS

13 1514 (RO) 3116 1

Future use DDR2EXTMR1 Reserved

When a program sets (or clears) the OPDS bit in the DDR2CTL3 register, the drive strengths of the DDR2 memorys data and strobe pins is driven by the memory device at reduced (or full) strength, respectively. By default, the bit is cleared (full drive strength). However, drive strengths of address, control, and differential clock pins which are outputs from the controller are fixed and not affected. Also note that from a controller standpoint, address, control, and clock signals are always driven at half drive strength, while data and strobe pins are always driven at full drive strength.

DDR2 Control Register 4 (DDR2CTL4) The DDR2CTL4 register includes the programmable parameters associated with the DDR2 extended mode register 2 (EMR2). Table A-21 shows the DDR2 control register bit definition. All the values are defined in terms of number of clock cycles. Values written into this register are loaded into the DDR2 extended mode register 2 during power up (or when the force EMR2 bit in the DDR2CTL0 register is set). This register should be initialized before starting the initialization sequence.

ADSP-214xx SHARC Processor Hardware Reference

A-51

External Port Registers

contents should not be changed while ThisisregistersAlso whenever this register contents areDDR2 interface active. changed an initialization sequence must be executed to reflect this register contents in to the DDR2 extended mode register 2. Table A-21. DDR2CTL4 Register Bit Descriptions (RW)
Bit 130 1514 (RO) 3116 Name Self Refresh Rate DDR2EXTMR2 Reserved Description (all bits cleared) 2x self-refresh rate high temp not supported Extended Mode Register 2. Set to 10.

DDR2 Control Register 5 (DDR2CTL5) The DDR2CTL5 register includes the programmable parameters associated with the DDR2 extended mode register 3 (EMR3).Table A-22 shows the DDR2 control register bit definition. All the values are defined in terms of number of clock cycles. Values written into this register are loaded into the DDR2EMR3 register during power up (or when the Force EMR3 bit in DDR2CTL0 is set). This register should be initialized before starting the initialization sequence. be This registers contents should notthis changed while the DDR2 interface is active. Also, whenever registers contents are changed an initialization sequence must be executed to reflect this registers contents in the DDR2EMR3 register.

A-52

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-22. DDR2CTL5 Register Bit Descriptions (RW)

Bit 130 1514 (RO) 3116 Name Future use DDR2EXTMR3 Reserved Description All bits cleared Extended Mode Register 3. Set to 11.

Refresh Rate Control Register (DDR2RRC) The DDR2 refresh rate control register (Figure A-22 and Table A-23) provides a flexible mechanism for specifying the auto-refresh timing. For more information, see Refresh Rate Control on page 4-78.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

tRFC (2821) Row Refresh Cycle

15 14 13 12

11 10

RDIV (130) Average Periodic Refresh

Figure A-22. DDR2RRC Register Table A-23. DDR2RRC Register Bit Descriptions (RW)
Bit 130 Name RDIV Description RDIV setting defines the average refresh interval between two subsequent refresh commands. The formula is shown in Refresh Rate Control on page 4-78. Note that the DDR2 manufacturer data sheets distinguish between commercial, industrial and automotive grades.

2014

Reserved

ADSP-214xx SHARC Processor Hardware Reference

A-53

External Port Registers

Table A-23. DDR2RRC Register Bit Descriptions (RW)

Bit 2821 Name tRFC Description Row refresh cycle is the time after the refresh command to refresh a row. Programmable from 0 to 255 (0x14 default). Note that the DDR2 manufacturer data sheets distinguish between commercial, industrial and automotive grades.

3129

Reserved

Controller Status Register 0 (DDR2STAT0) The register (Figure A-23 and Table A-24) provides information on the state of the controller. This information can be used to determine when it is safe to alter DDR2 controller control parameters or as a debug aid.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

DDR2DLLCALDONE Calibration Complete DDR2DLLCAL Calibration Active DDR2PD Precharge Power-Down Status DDR2MSE Access Error

DDR2CI Controller Idle Status DDR2SRA Self Refresh Active DDR2PUA Power Sequence Active DDR2RS Reset State

Figure A-23. DDR2STAT0 Register

A-54

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-24. DDR2STAT0 Register Bit Descriptions (RO)

Bit 0 Name DDR2CI Description Controller Idle Status. 0 = Controller busy performing access or auto-refresh 1 = Controller idle (default) Self-Refresh Active. 0 = Not in self-refresh mode 1 = Active Power-Up Sequence Active. 0 = DDR2 not in power-up 1 = DDR2 in power-up initialization sequence DLL Reset. 0 = A power-up to DDR2 has been initialized since last DDR2 controller reset 1 = No power-up sequence occurred since last DDR2 controller reset (default) Access Error (sticky bit). 0 = No Error 1 = An access request to DDR2 occurred while the interface is disabled (DIS_DDR2CTL bit set in DDR2CTL0 register) Write a 0 to clear this bit (if set, sticky bit).

DDR2SRA

DDR2PUA

DDR2RS

4 (RW)

DDR2MSE

5 6

Reserved DDR2PD Precharge Power-Down Status. 0 = Not in precharge power-down 1 = DDR2 in precharge power-down state (DIS_DDR2CKE bit set and DDR2CKE signal deasserted) DLL External Bank Calibration Status. 0 = Not in DLL calibration sequence 1 = DLL calibration active This bit is set during the DLL external bank calibration and cleared if finished.

DDR2DLLCAL

ADSP-214xx SHARC Processor Hardware Reference

A-55

External Port Registers

Table A-24. DDR2STAT0 Register Bit Descriptions (RO) (Contd)

Bit 8 Name DDR2DLLCAL DONE Description DLL External Bank Calibration After Reset Status. 0 = A DLL calibration sequence is not happened since last DDR2 controller reset 1 = A DLL calibration sequence occurred since last DDR2 controller reset Note this bit is only set for first calibration after reset and remains set.

319

Reserved

Controller Status Register 1 (DDR2STAT1) This register reports the DDR2 bank active/idle status. This register is shown in Figure A-24 and described in Table A-25.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Bit Field (3124) External Bank 3 Status

Bit Field (2316) External Bank 2 Status

15 14 13 12

11 10

Bit Field (158) External Bank 1 Status

Bit Field (70) External Bank 0 Status

Figure A-24. DDR2STAT1 Register

A-56

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-25. DDR2STAT1 Register Bit Descriptions (RO)

Bit Field 70 Field Name External Bank 0 Status Description External Bank 0 Active/Precharge State. xxxxxxx1 = Internal bank 0 in open state xxxxxxx0 = Internal bank 0 in precharge state xxxxxx1x = Internal bank 1 in open state xxxxxx0x = Internal bank 1 in precharge state 1xxxxxxx = Internal bank 7 in open state 0xxxxxxx = Internal bank 7 in precharge state External Bank 0 Active/Precharge State. xxxxxxx1 = Internal bank 0 in open state xxxxxxx0 = Internal bank 0 in precharge state xxxxxx1x = Internal bank 1 in open state xxxxxx0x = Internal bank 1 in precharge state 1xxxxxxx = Internal bank 7 in open state 0xxxxxxx = Internal bank 7 in precharge state External Bank 0 Active/Precharge State. xxxxxxx1 = Internal bank 0 in open state xxxxxxx0 = Internal bank 0 in precharge state xxxxxx1x = Internal bank 1 in open state xxxxxx0x = Internal bank 1 in precharge state 1xxxxxxx = Internal bank 7 in open state 0xxxxxxx = Internal bank 7 in precharge state External Bank 0 Active/Precharge State. xxxxxxx1 = Internal bank 0 in open state xxxxxxx0 = Internal bank 0 in precharge state xxxxxx1x = Internal bank 1 in open state xxxxxx0x = Internal bank 1 in precharge state 1xxxxxxx = Internal bank 7 in open state 0xxxxxxx = Internal bank 7 in precharge state

158

External Bank 1 Status

2316

External Bank 2 Status

3124

External Bank 3 Status

ADSP-214xx SHARC Processor Hardware Reference

A-57

External Port Registers

DLL0 Control Register 1 (DLL0CTL1) The DLL0CTL1 register shown in Figure A-25 and described in Table A-26 includes the programmable parameters associated with the DLL0 device. Note that it takes at least 9 core clock cycles to perform a DLL reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

RESETCAL Reset the DQS Phase Calibration Logic

RESETDLL Reset DLL Control Logic RESETDAT Reset Data Capture Logic

Figure A-25. DLL0CTL1 Register Table A-26. DLL0CTL1 Register Bit Descriptions (RW)
Bit 80 9 Name Reserved RESETDLL Reset DLL Control Logic. Active high, when active, it resets the DLL control logic only, including the 90 degree DQS shifter. 0 = No effect 1 = Reset DLL0 control logic Reset Data Capture Logic. Active high, when active, it resets the data capture logic only, including P and N buffers. 0 = No effect 1 = Reset DLL0 data capture logic Reset DQS Phase Calibration Logic. Active high, when active, it resets the DQS phase calibration logic. 0 = No effect 1 = Reset DLL0 DQS phase calibration logic Description

10

RESETDAT

11

RESETCAL

3112

Reserved

A-58

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

DLL1 Control Register 1 (DLL1CTL1) The DLL1CTL1 register shown in Figure A-26 and described in Table A-27 includes the programmable parameters associated with the DLL1 device. Note that it takes at least 9 core clock cycles to perform a DLL reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

RESETCAL Reset the DQS Phase Calibration Logic

RESETDLL Reset DLL Control Logic RESETDAT Reset Data Capture Logic

Figure A-26. DLL1CTL1 Register Table A-27. DLL1CTL1 Register Bit Descriptions (RW)
Bit 80 9 Name Reserved RESETDLL Reset DLL Control Logic. Active high, when active, it resets the DLL control logic only, including the 90 degree DQS shifter. 0 = No effect 1 = Reset DLL1 control logic Reset Data Capture Logic. Active high, when active, it resets the data capture logic only, including P and N buffers. 0 = No effect 1 = Reset DLL1 data capture logic Reset DQS Phase Calibration Logic. Active high, when active, it resets the DQS phase calibration logic. 0 = No effect 1 = Reset DLL1 DQS phase calibration logic Description

10

RESETDAT

11

RESETCAL

3112

Reserved

ADSP-214xx SHARC Processor Hardware Reference

A-59

External Port Registers

DLL Status Registers (DLL0STAT0, DLL1STAT0) The DLL0STAT0 status register indicates the DLL lock status. Table A-28. DLL0STAT0 Register Bit Descriptions (RW)
Bit 029 30 Name Reserved DLL_LOCKED Reset DLL Control Logic. If this bit is set, indicates that the on-chip DLL for DDR2 controller has locked. After reset is de-asserted the DLL automatically locks to the default DDR2 CLK frequency even if the controller is not enabled. Reserved Description

31

DDR2 Pad Control Register 0 (DDR2PADCTL0) The DDR2PADCTL0 register shown in Figure A-27 and described in Table A-29 includes the programmable parameters associated with the DDR2 DATA, DQS and DDR2CLK pads.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DDR2CLK_PWD Receiver Power Down

DQS_PWD Receiver Power Down

15 14 13 12

11 10

DATA_PWD Receiver Power Down

Figure A-27. DDR2PADCTL0 Register

A-60

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-29. DDR2PADCTL0 Register Bit Descriptions (RW)

Bit 80 9 Name Reserved DATA_PWD Data Pad Receiver Power Down. 0 = Normal mode 1 = Power-down mode Description

1810 19

Reserved DQS_PWD DQS Pad Receiver Power Down. 0 = Normal mode 1 = Power-down mode

2820 29

Reserved DDR2CLK_PWD Clock Pad Receiver Power Down. 0 = Normal mode 1 = Power-down mode Reserved

3130

DDR2 Pad Control Register 1 (DDR2PADCTL1) The DDR2PADCTL1 register shown in Figure A-28 and described in Table A-30 includes the programmable parameters associated with the DDR2 Command (CS, CAS, RAS, WE, ODT) and Address pad control.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CMD_PWD Receiver Power Down

15 14 13 12

11 10

ADDR_PWD Receiver Power Down

Figure A-28. DDR2PADCTL1 Register

ADSP-214xx SHARC Processor Hardware Reference

A-61

Peripheral Registers

Table A-30. DDR2PADCTL1 Register Bit Descriptions (RW)

Bit 80 9 Name Reserved ADDR_PWD Address Pad Receiver Power Down. 0 = Normal mode 1 = Power-down mode Description

1810 19

Reserved CMD_PWD Command Pad Receiver Power Down. 0 = Normal mode 1 = Power-down mode

2831

Reserved

Peripheral Registers
The registers in the following sections are used for the peripherals that are not routed through the signal routing units (SRU, SRU2).

Link Port Registers

The following sections describe the link port status and control registers. Control Register (LCTLx) Figure A-29 and Table A-31 describe the bit fields within this register.

A-62

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

15 14 13 12

11 10

EXTTXFR_DONE_MSK External Transfer Done Mask LPIT_MSK Invalid Transmit Interrupt Mask DMACH_IRPT_MSK DMA Channel Interrupt Mask LRRQ_MSK Link Port Receive Request Mask LTRQ_MSK Link Port Transmit Request Mask LP_BHD Buffer Hang Disable

LEN Link Buffer Enable LDEN Link Buffer DMA Enable LCHEN Link Buffer DMA Chaining Enable LTRAN Link Buffer Transfer Direction LSYNC_EN Link Port Transmitter Logic Synchronizer Enable

Figure A-29. LCTLx Registers Table A-31. LCTLx Register Bit Descriptions (RW)
Bit 0 Name LEN Description Link Port Enable. Enables if set (=1) or disables if cleared (=0) the link port. When the bit transitions from high to low the link buffer x is flushed which takes 2 core clock cycles. The corresponding LSTAT and LRERR bits are also cleared. Link Buffer DMA Enable. Enables (if set, =1) or disables (if cleared, = 0) DMA transfers link buffer x (LBUF). Link Buffer DMA Chaining Enable. Enables (if set, =1) or disables (if cleared, =0) DMA chaining link buffer x (LBUF). Link Buffer Transfer Direction. This bit selects the transfer direction (transmit if set, =1) (receive if cleared, = 0) for link buffer x (LBUF).

1 2 3 54 6

LDEN LCHEN LTRAN Reserved LSYNC_EN

Link Port Transmitter Logic Synchronizer Enable. Enables the synchronizer logic within the link port transmitter. This bit is undefined for ADSP-2146x rev 0.0 and is only available for silicon rev 0.1 and beyond. See the processor IC anomaly list available on the web. 0 = Link port transmitter logic is not enabled. 1 = Link port transmitter logic is enabled.

ADSP-214xx SHARC Processor Hardware Reference

A-63

Peripheral Registers

Table A-31. LCTLx Register Bit Descriptions (RW) (Contd)

Bit 7 Name LP_BHD Description Buffer Hang Disable. 0 = Core stalls when read from empty receive or write to full transmit buffer attempted 1 = Prevents a core hang. Transmit Request Mask. 0 = Mask 1 = Unmask

LTRQ_MSK

LRRQ_MSK Receive Request Mask. 0 = Mask 1 = Unmask DMACH_ IRPT_MSK DMA Channel Count Interrupt Mask. Must be set to generate interrupt if DMA count is zero and is compatible with traditional SHARC processors. 0 = Mask 1 = Unmask

10

11

LPIT_MASK Invalid Transmit Interrupt Mask. 0 = Mask 1 = Unmask EXTTXFR_ DONE_ MSK External Transfer Done Interrupt Mask. Valid for core and DMA accesses. If set interrupt is generated when the FIFO is empty. Note if bit 10 is also set for DMA, two interrupts are generated, one for DMA count = 0 and one for FIFO empty. 0 = Mask 1 = Unmask

12

3113

Reserved

A-64

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Status Registers (LSTATx) Figure A-30 and Table A-32 describe the bit fields within this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

LPBS Link Port Bus Status (Tx) LERR Link Buffer Rx Pack Error Status FFST (65) Link Buffer Status EXTTXFR_DONE External Transfer Done Interrupt

LTRQ Link Port Tx Request Status LRRQ Link Port Rx Request Status DMACH_IRPT DMA Channel Interrupt LPIT Link Port Invalid Tx Interrupt

Figure A-30. LSTATx Register Table A-32. LSTATx Register Bit Descriptions (RO)
Bit 0 (ROC) Name LTRQ Description Transmit Request Status. Indicates when another processor is attempting to send data through a particular link port. Two processors can communicate without prior knowledge of the transfer direction, link port number, or exactly when the transfer is to occur. Receive Request Status. Indicates when another processor is attempting to receive data through a particular link port. Two processors can communicate without prior knowledge of the transfer direction, link port number, or exactly when the transfer is to occur. DMA Channel Count Interrupt. An internal transfer complete interrupt is generated by the transmitter once the word count is zero by setting bit 10 (DMACH_IRPT_MSK) in the LCTL register. When DMA is not enabled, this interrupt is generated when the word count is zero. Also, when DMA is enabled, the DMA engine checks if DMA has been completed.

1 (ROC)

LRRQ

2 (ROC)

DMACH_IRPT

ADSP-214xx SHARC Processor Hardware Reference

A-65

Peripheral Registers

Table A-32. LSTATx Register Bit Descriptions (RO) (Contd)

Bit 3 (ROC) Name LPIT Description Invalid Transmit Interrupt. Generated when the transmitter is driving LCLKx high because the receiver has not asserted LACKx and LCLKx goes low due to a processor reset. External Transfer Done Interrupt. Generated by the transmitter once the external transfer is completed Link Buffer Status. 00 = empty, 01 = reserved, 10 = one word, 11 = full (Cleared when the Link Port is disabled) Link Buffer Receive Pack Error Status. 0 = Packing complete 1 = Packing incomplete Bus Status (Transmitter). To safely disable link port transmit operation first poll the FFST bit and second the LPBS bit. 0 = Bus is idle 1 = Bus busy

4 (ROC) 65

EXTTXFR_DONE FFST

LERR

LPBS

319

Reserved

Memory-to-Memory DMA Register

The following DMA related registers are used when performing internal-to-internal DMA through the MTM port. DMA Control (MTMCTL Register) The MTMCTL register (Figure A-31) allows programs to transfer blocks of 64-bit data from one internal memory location to another. The MTM module must set the MTMFLUSH bit to clear the buffer which takes 6 core clock cycles

A-66

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

MTMDMA0ACT (RO) Memory Write DMA Status

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MTMDMA1ACT (RO) Memory Read DMA Status

MTMFLUSH (RW1S) 1=Flush the FIFO and reset the read/write pointers

MTMDEN MTM DMA Enable 0=Disable 1=Enable

Figure A-31. MTMCTL Register (RW)

Pulse Width Modulation Registers

The following registers control the operation of pulse width modulation on the processor. Global Control Register (PWMGCTL) This register enables or disables the four PWM groups, in any combination and provides synchronization across the groups. Note that disable bits have higher priority over the enable bits (bit 1 higher as bit 0 and so on). This 16-bit register is shown in Figure A-32. For the PWM global control register, the traditional read-modify-write operations to disable the PWM group have changed. The action is to directly writethis simplifies the enable/disable of the PWM groups and can be done with fewer instructions. For example, instead of the following code:
ustat3 = dm(PWMGCTL); bit set ustat3 PWM_DIS0; dm(PWMGCTL) = ustat3; /* PWM General Control Register */ /* disables group 0 */

Use:
ustat3 = PWM_DIS0; dm(PWMGCTL) = ustat3;

ADSP-214xx SHARC Processor Hardware Reference

A-67

Peripheral Registers

Writes to the enable and disable bit-pairs for a PWM group works as follows. = 0, PWM_ENx = 0 No action PWM_DISx = 0, PWM_ENx = 1 Enable the PWM group PWM_DISx = 1, PWM_ENx = x Disable the PWM group
PWM_DISx

For reads, the interpretation is as follows.

PWM_DISx PWM_DISx

= 0, PWM_ENx = 0 PWM group is disabled = 1, PWM_ENx = 1 PWM group is enabled

Any other read combination is not possible. Reads of the PWMGCTL register returns the enable status on both the enable and disable bits.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM_SYNCDIS3 PWM Group 3 Disable PWM_SYNCEN3 PWM Group 3 Enable PWM_SYNCDIS2 PWM Group 2 Disable PWM_SYNCEN2 PWM Group 2 Enable PWM_SYNCDIS1 PWM Group 1 Disable PWM_SYNCEN1 PWM Group 1 Enable PWM_SYNCDIS0 PWM Group 0 Disable PWM_SYNCEN0 PWM Group 0 Enable

PWM_EN0 PWM Group 0 Enable PWM_DIS0 PWM Group 0 Disable PWM_EN1 PWM Group 1 Enable PWM_DIS1 PWM Group 1 Disable PWM_EN2 PWM Group PWM_DIS2 PWM Group PWM_EN3 PWM Group PWM_DIS3 PWM Group 2 Enable 2 Disable 3 Enable 3 Disable

Figure A-32. PWMGCTL Register

A-68

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-33. PWMGCTL Register Bit Descriptions (RW)

Bit 0, 2. 4, 6 1, 3, 5, 7 8, 10, 12, 14 9, 11, 13, 15 Name PWM_ENx0 PWM_DISx PWM_SYNCENx PWM_SYNCDISx Function PWM Group x Enable PWM Group x Disable PWM Group x Enable PWM Group x Disable

Global Status Register (PWMGSTAT) This register provides the status of each PWM group (Table A-34). The status bits are set depending on the IRQEN bit. The ISR needs to write one to clear the status bits. Table A-34. PWMGSTAT Register Bit Descriptions (RW1C)
Bit 0 1 2 3 154 Name PWM_STAT0 PWM_STAT1 PWM_STAT2 PWM_STAT3 Reserved Function PWM Group 0 Period Completion Status PWM Group 1 Period Completion Status PWM Group 2 Period Completion Status PWM Group 3 Period Completion Status

Control Register (PWMCTLx) These registers, shown in Figure A-33 and described in Table A-35, are used to set the operating modes of each PWM block. They also allow programs to disable interrupts from individual groups.

ADSP-214xx SHARC Processor Hardware Reference

A-69

Peripheral Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

15 14 13 12

11 10

PWM_IRQEN Interrupt Enable PWM_UPDATE Update Mode

PWM_ALIGN Align Mode PWM_PAIR Pair Mode

Figure A-33. PWMCTLx Register Table A-35. PWMCTLx Register Bit Descriptions (RW)
Bit 0 Name PWM_ALIGN Description Align Mode. 0 = Edge-aligned. The PWM waveform is left-justified in the period window. 1 = Center-aligned. The PWM waveform is symmetrical. Pair Mode. 0 = Non-paired mode. The PWM generates independent signals (for example xH, xL) 1 = Paired mode. The PWM generates the complementary signal from the high side output (xL=/xH). Update Mode. 0 = Single update mode. The duty cycle values are programmable only once per PWM period. The resulting PWM patterns are symmetrical about the mid-point of the PWM period. 1 = Double update mode. A second update of the PWM registers is implemented at the mid-point of the PWM period. PWM_UPDATE mode has only effect for center aligned mode (PWM_ALIGN=1).

PWM_PAIR

PWM_UPDATE

43 5

Reserved PWM_IRQEN Enable PWM Interrupts. 0 = Interrupts not enabled 1 = Interrupts enabled

316

Reserved

A-70

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Status Registers (PWMSTATx) These 16-bit registers, described in Table A-36, report the status of the phase and mode for each PWM group. Table A-36. PWMSTATx Register Bit Descriptions (RO)
Bit 0 Name PWM_PHASE Description PWM Phase Status. Set during center aligned mode in the second half of each PWM period. Allows programs to determine the particular half-cycle (first or second) during PWM interrupt service routine, if required. 0 = First half 1 = Second half (default) In edge aligned mode this bit is always set.

1 2

Reserved PWM_PAIRSTAT PWM Paired Mode Status. 0 = Inactive paired mode 1 = Active paired mode

153

Reserved

Output Disable Registers (PWMSEGx) These 16-bit registers, shown in Figure A-34 and described in Table A-37, control the output signals of the four PWM groups. The output signals are enabled by default.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AHAL_XOVR Crossover Enable for AH/AL Pair BHBL_XOVR Crossover Enable for BH/BL Pair PWM_AL Channel A Low Disable

PWM_BH Channel B High Disable PWM_BL Channel B Low Disable PWM_AH Channel A High Disable

Figure A-34. PWMSEGx Register

ADSP-214xx SHARC Processor Hardware Reference

A-71

Peripheral Registers

Table A-37. PWMSEGx Register Bit Descriptions (RW)

Bit 0 Name PWM_BH Description Channel B High Disable. Enables or disables the channel B output signal. 0 = Enable 1 = Disable Channel B Low Disable. Enables or disables the channel B output signal. 0 = Enable 1 = Disable Channel A High Disable. Enables or disables the channel A output signal. 0 = Enable 1 = Disable Channel A Low Disable. Enables or disables the channel A output signal. 0 = Enable 1 = Disable Crossover Enable for BH/BL Pair. 0 = Disable 1 = Enable Crossover Enable for AH/AL Pair. 0 = Disable 1 = Enable

PWM_BL

PWM_AH

PWM_AL

BHBL_XOVR

AHBL_XOVR

156

Reserved

Polarity Select Registers (PWMPOLx) These 16-bit registers, described in Table A-38, control the polarity of the four PWM groups which can be set to either active high or active low. Note that bit 1 has priority over bit 0, bit 3 over bit 2 and so on. In paired mode, it is expected to maintain polarity coherency by setting the same polarity for both the high and low side of a PWM pair.

A-72

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-38. PWMPOLx Register Bit Descriptions (RW)

Bit 0 Name PWM_POL1AL Description Channel AL Polarity 1. 0 = Channel AL polarity 0 1 = Channel AL polarity 1 (default) Channel AL Polarity 0. 0 = Channel AL polarity 0 1 = Channel AL polarity 1 (default) Channel AH Polarity 1. 0 = Channel AH polarity 0 1 = Channel AH polarity 1 (default) Channel AH Polarity 0. 0 = Channel AH polarity 0 1 = Channel AH polarity 1 (default) Channel BL Polarity 1. 0 = Channel AL polarity 0 1 = Channel AL polarity 1 (default) Channel BL Polarity 0. 0 = Channel AL polarity 0 1 = Channel AL polarity 1 (default) Channel BH Polarity 1. 0 = Channel BH polarity 0 1 = Channel BH polarity 1 (default) Channel BH Polarity 0. 0 = Channel BH polarity 0 1 = Channel BH polarity 1 (default)

PWM_POL0AL

PWM_POL1AH

PWM_POL0AH

PWM_POL1BL

PWM_POL0BL

PWM_POL1BH

PWM_POL0BH

158

Reserved

Period Registers (PWMPERIODx) These 16-bit RW registers control the unsigned period of the four PWM groups. This register is double buffered for double update mode. A change in one half cycle of PWM switching period only takes effect in the next half period.

ADSP-214xx SHARC Processor Hardware Reference

A-73

Peripheral Registers

Duty Cycle High Side Registers (PWMAx, PWMBx) The 16-bit duty-cycle control registers (RW) directly control the A/B (twos-complement) duty cycles of the two pairs of PWM signals. Duty Cycle Low Side Registers (PWMALx, PWMBLx) The 16-bit duty-cycle control registers (RW) directly control the AL/BL duty cycles (twos-complement) of the non-paired PWM signals. These can be different from the AH/BH cycles. Dead Time Registers (PWMDTx) These 16-bit RW registers set up a short time delay (10-bit, unsigned) between turning off one PWM signal and turning on its complementary signal. Debug Status Registers (PWMDBGx) These 16-bit registers aid in software debug activities. Table A-39. PWMDBGx Register Bit Descriptions (RO)
Bit 0 1 2 3 15:4 Name PWM_AL PWM_AH PWM_BL PWM_BH Reserved Function Channel A Low Output Signal for S/W Observation Channel A High Output Signal for S/W Observation Channel B Low Output Signal for S/W Observation Channel B High Output Signal for S/W Observation

A-74

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

FFT Accelerator Registers

The following sections describe the registers used to program and debug the FFT accelerator. General Control Register (FFTCTL1) The global control register (FFTCTL1) shown in Figure A-35 and described in Table A-39 is used to enable, start, and reset the FFT module. It is also used to enable DMA and debug operation.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

FFT_DBG Debug Mode Enable FFT_DMAEN DMA Enable

FFT_RST Accelerator Reset FFT_EN Accelerator Enable FFT_START Accelerator Start

Figure A-35. FFTCTL1 Register Table A-40. FFTCTL1 Register Bit Descriptions (RW)
Bits 0 Name FFT_RST Description Reset Accelerator. Setting this bit puts the accelerator into reset mode. Explicit clearing of this bit is necessary to take the accelerator out of reset. 0 = Normal operation 1 = Resetthe input/output buffers are immediately flushed. Accelerator Enable. 0 = Disable 1 = Enable Start Accelerator. 0 = Idle 1 = Start

FFT_EN

FFT_START

ADSP-214xx SHARC Processor Hardware Reference

A-75

Peripheral Registers

Table A-40. FFTCTL1 Register Bit Descriptions (RW) (Contd)

Bits 3 Name FFT_DMAEN Description DMA Enable. 0 = Disable 1 = Enable

54 6

Reserved FFT_DBG Debug Mode Enable. 0 = Disable 1 = Enable

317

Reserved

Control Register (FFTCTL2) The FFT control register, shown in Figure A-36 and described in Table A-41, is used to set up individual FFT parameters (such as length) and how the module process the FFT, such as data packing.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NOVER256 (2821)

HDIM (2016)

15 14 13 12

11 10

FFT_LOG2HDIM (1512) VDIM (117) FFT_LOG2VDIM (63) FFT_CPACKOUT Complex Word Output Packing (<512 words)

FFT_RPT Accelerator Repeat FFT_CPACKIN Complex Word Input Packing (<512 words)

Figure A-36. FFTCTL2 Register

A-76

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-41. FFTCTL2 Register Bit Descriptions (RW)

Bits 0 Name FFT_RPT Description Accelerator Repeat. See No Repeat Mode and Repeat Mode on page 7-13 0 = Go to idle when done 1 = Repeat when done Complex Word Input Packing for <512 Words. 0 = No packing, first all reals, then all imag are received by the accelerator 1 = Complex numbers are packed Real/Imag. For >256 words, this bit is always set. Complex Word Output Packing for <512 Words. 0 = No packing, first all reals, then all imag are sent by the accelerator 1 = Complex numbers are packed Real/Imag. For >256 words, this bit is always set. Log2 (VDIM). VDIM/16. Vertical Column Dimension of the FFT computation matrix. V = 16, VDIM = 1 V = 32, VDIM = 2 V = 64, VDIM = 3 V = 128, VDIM = 4 V = 256, VDIM = 5 Log2 (HDIM). HDIM/16. Horizontal Column Dimension of the FFT computation matrix. For small FFTs, (<512 points) only VDIM required HDIM = 0. N/256 = HDIM VDIM (used for large FFTs)

FFT_CPACKIN

FFT_CPACKOUT

63 117

FFT_LOG2VDIM VDIM

1512 2016

FFT_LOG2HDIM HDIM

2821 3129

NOVER256 Reserved

ADSP-214xx SHARC Processor Hardware Reference

A-77

Peripheral Registers

Multiplier Status Register (FFTMACSTAT) The FFT_MACSTAT register, described in Table A-42, can be written only in debug mode. The status bits are sticky and are cleared when read. Table A-42. FFT_MACSTAT Register Bit Descriptions (ROC)
Bits 0 1 2 3 314 Name FFT_NAN FFT_DENORM FFT_OVR FFT_UDR Reserved Bits 30 follow the IEEE STD for floating point numbers. Description

DMA Status Register The bits in the status register, described in Table A-43 report DMA status information. Table A-43. FFTDMASTAT Register Bit Descriptions (RO)
Bits 0 1 2 (ROC) 3 4 5 (ROC) 316 Name ICPLD IDMASTAT IDMACHIRPT OCPLD ODMASTAT ODMACHIRPT Reserved Description Input Chain Pointer Loading Input DMA in Progress Input DMA Channel Interrupt Output Chain Pointer Loading Output DMA in Progress Output DMA Channel Interrupt

A-78

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Debug Registers (FFTDADDR, FFTDDATA) Bits 310 is the FFT_DDATA register correspond to the data to be read or written. When a data write is performed first this register is loaded with data which needs to be written, then the FFT_DADDRESS register is loaded with the write address of the location. Note that these registers should be written/read only in debug mode. In Table A-44, A is a meaningful address bit. Table A-44. DADDRESS Register Bit Descriptions (RW)
Bits 120 Name ADDRESS Description Address Bit. Access to local memory requires debug mode. The MSB bits of the address decode the memory location. 000AAAAAAAAAA = read data memory (2^10) 100AAAAAAAAAA = write data memory (2^10) 010xAAAAAAAAA = read coefficient memory (2^9) 110xAAAAAAAAA = write coefficient memory (2^9) A = valid address bits

3113

Reserved

FIR Accelerator Registers

The following sections describe the registers used to program and debug the FIR accelerator. Global Control Register (FIRCTL1) The FIRCTL1 register, shown in Figure A-37 and described in Table A-45, is used to configure the global parameters for the accelerator. These include the number of channels, channel auto iterate, DMA enable, and accelerator enable.

ADSP-214xx SHARC Processor Hardware Reference

A-79

Peripheral Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

FIR_RND (1614) Rounding Mode Select For Floating-point Mode

15 14 13 12

11 10

FIR_RND (1614) Rounding Mode FIR_TC Twos-Complement Format FIR_FXD Fixed-point Accelerator Select FIR_CCINTR Channel Complete Interrupt

FIR_EN Accelerator Enable FIR_CH (51) Number of Channels FIR_DMAEN DMA Enable FIR_CAI Channel Auto Iterate

Figure A-37. FIRCTL1 Register Table A-45. FIRCTL1 Register Bit Descriptions (RW)
Bits 0 Name FIR_EN Description FIR Enable. 0 = FIR disabled 1 = FIR enabled Number of Channels. Programmable between 031 0 = FIR_CH1 31 = FIR_CH32

51

FIR_CH321

76 8

Reserved FIR_DMAEN DMA Enable. 0 = DMA disabled 1 = DMA enabled Channel Auto Iterate. 0 = TDM Processing stops (idle) once all channels are over 1 = Moves to first channel and continues TDM processing in a loop when all channels are over

FIR_CAI

10

Reserved

A-80

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-45. FIRCTL1 Register Bit Descriptions (RW) (Contd)

Bits 11 Name FIR_CCINTR Description Channel Complete Interrupt. 0 = Interrupt is generated only when all channels are done 1= Interrupt is generated after each channel is done Fixed-Point Accelerator Select. 0 = 32-bit IEEE floating-point 1 = 32-bit fixed point Twos-Complement Format Input Select For Fixed-Point Mode. 0 = Unsigned integer 1 = Signed integer Rounding Mode Select For Floating-Point Mode. 000 = IEEE round to nearest (even) 001 = IEEE round to zero 010 = IEEE round to +ve infinity 011 = IEEE round to -ve infinity 100 = Round to nearest Up 101 = Round away from zero 110 = Reserved 111 = Reserved

12

FIR_FXD

13

FIR_TC

1614

FIR_RND

3117

Reserved

Channel Control Register (FIRCTL2) The FIRCTL2 register, shown in Figure A-38 and described in Table A-46, is used to configure the channel specific parameters such as filter TAP length, window size, sample rate conversion, up/down sampling and ratio.

ADSP-214xx SHARC Processor Hardware Reference

A-81

Peripheral Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

FIR_UPSAMP Up Sampling Enable FIR_SRCEN Sample Rate Conversion Enable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WINDOW (2314) Window Size FIR_RATIO Up/Down Sampling Ratio

WINDOW (2314) Window Size

TAPLEN (110) Tap Length

Figure A-38. FIRCTL2 Register Table A-46. FIRCTL2 Register Bit Descriptions (RW)
Bits 110 1312 2314 Name TAPLEN Reserved WINDOW Window Size. Window size specifies the number of sample/block to process (sample based processing = window size of 1) Description Tap Length. Programmable between 04095 Tap Length = TAPLEN + 1

24 2725 28 29

Reserved FIR_RATIO Reserved FIR_SRCEN Sample Rate Conversion Enable. 0 = Disabled 1 = Enabled Up Sampling Enable. 0 = Down Sampling 1 = Up sampling UP/DOWN Sampling Ratio. Sampling Ratio = RATIO + 1

30

FIR_UPSAMP

31

Reserved

A-82

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

FIR MAC Status Register (FIRMACSTAT) This register, shown in Figure A-39 and described in Table A-47, provides the status of MAC operations. The status of all four multipliers/adders are available separately for programs to poll. In fixed-point mode only the ARIx bits are used (all other bits are reserved).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FIR_MACAINV3 FIR_MACARI3 FIR_MACARZ3 FIR_MACMINV3

FIR_MACARI2 FIR_MACAINV2 FIR_MACMRZ3 FIR_MACMRI3

15 14 13 12

11 10

FIR_MACARZ2 FIR_MACMINV2 FIR_MACMRI2 FIR_MACMRZ2 FIR_MACAINV1 FIR_MACARI1 FIR_MACARZ1 FIR_MACMINV1

FIR_MACMRZ0 FIR_MACMRI0 FIR_MACMINV0 FIR_MACARZ0 FIR_MACARI0 FIR_MACAINV0 FIR_MACMRZ1 FIR_MACMRI1

Figure A-39. FIRMACSTAT Register Table A-47. FIRMACSTAT Register Bit Descriptions (RO)
Bits 0 1 2 3 4 5 Name FIR_MACMRZ0 FIR_MACMRI0 FIR_MACMINV0 FIR_MACARZ0 FIR_MACARI0 FIR_MACAINV0 Description Multiplier Result Zero. Set if multiplier 0 results is zero. Multiplier Result Infinity. Set if multiplier 0 results is infinity. Multiply Invalid. Set if multiplier 0 multiply operation is invalid. Adder Result Zero. Set if a adder 0 results is zero. Adder Result Infinity. Set if adder 0 results is infinity. Indicates overflow in fixed-point mode. Addition Invalid. Set if a adder 0 addition is invalid.

ADSP-214xx SHARC Processor Hardware Reference

A-83

Peripheral Registers

Table A-47. FIRMACSTAT Register Bit Descriptions (RO) (Contd)

Bits 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 3124 Name FIR_MACMRZ1 FIR_MACMRI1 FIR_MACMINV1 FIR_MACARZ1 FIR_MACARI1 FIR_MACAINV1 FIR_MACMRZ2 FIR_MACMRI2 FIR_MACMINV2 FIR_MACARZ2 FIR_MACARI2 FIR_MACAINV2 FIR_MACMRZ3 FIR_MACMRI3 FIR_MACMINV3 FIR_MACARZ3 FIR_MACARI3 FIR_MACAINV3 Reserved Description Multiplier Result Zero. Set if multiplier 1 results is zero. Multiplier Result Infinity. Set if multiplier 1 results is infinity. Multiply Invalid. Set if multiplier 1 multiply operation is invalid. Adder Result Zero. Set if a adder 1 results is zero. Adder Result Infinity. Set if adder 1 results is infinity. Indicates overflow in fixed-point mode. Addition Invalid. Set if a adder 1 addition is invalid. Multiplier Result Zero. Set if multiplier 2 results is zero. Multiplier Result Infinity. Set if multiplier 2 results is infinity. Multiply Invalid. Set if multiplier 2 multiply operation is invalid. Adder Result Zero. Set if a adder 2 results is zero. Adder Result Infinity. Set if adder 2 results is infinity. Indicates overflow in fixed-point mode. Addition Invalid. Set if a adder 2 addition is invalid. Multiplier Result Zero. Set if multiplier 3 results is zero. Multiplier Result Infinity. Set if multiplier 3 results is infinity. Multiply Invalid. Set if multiplier 3 multiply operation is invalid. Adder Result Zero. Set if a adder 3 results is zero. Adder Result Infinity. Set if adder 3 results is infinity. Indicates overflow in fixed-point mode. Addition Invalid. Set if a adder 3 addition is invalid.

A-84

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

FIR DMA Status Register (FIRDMASTAT) The information provided by this register, shown in Figure A-40 and described in Table A-48, are, chain pointer loading, coefficient DMA, data preload DMA, processing in progress, window complete, all channels complete.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

FIR_DMACPLD CURITER (1312) Current MAC Iteration CURCHNL (117) Current Channel FIR_DMAACDONE All Channels Done FIR_DMAWDONE Processing of Current Channel Done FIR_DMAWRBK Write Back Updated Index Pointers Chain Pointer Load Status FIR_DMACLD Coefficient Loading FIR_DMADLD Data Preload FIR_DMAPPGS MAC Processing in Process

Figure A-40. FIRDMASTAT Register Table A-48. FIRDMASTAT Register Bit Descriptions (RO)
Bits 0 1 2 3 4 5 (ROC) Name FIR_DMACPLD FIR_DMACLD FIR_DMADLD FIR_DMAPPGS FIR_DMAWRBK FIR_DMAWDONE Description Chain Pointer Loading Status. High indicates state machine in chain pointer load state. Coefficient Loading. Data Preload. MAC Processing in Progress. Writing Back the Updated Index Registers. Processing of Current Channel Done. (Sticky Cleared on register read). The FIR_CCINTR bit will not affect the FIR_DMAWDONE Status Bit

ADSP-214xx SHARC Processor Hardware Reference

A-85

Peripheral Registers

Table A-48. FIRDMASTAT Register Bit Descriptions (RO)

Bits 6 (ROC) Name Description FIR_DMAACDONE All Channels Done. (Sticky Cleared on register read). The FIR_CCINTR bit will not affect the FIR_DMAACDONE Status Bit. CURCHNL CURITER Reserved Current Channel. Channel that is being processed in the TDM slot. Zero indicates the last slot. Current MAC Iteration. Current MAC iteration in multi iteration mode. Zero indicates the final iteration.

117 1312 3114

FIR Debug Registers (FIRDEBUGCTL, FIRDBGADDR) This register, shown in Figure A-41 and described in Table A-49, control the debug operation of the FIR accelerator and should only be used in debug mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

FIR_ADRINC Address Auto Increment FIR_DBGMEM Local Memory Access

FIR_DBGMODE Debug Mode Enable FIR_HLD Hold or Single Step FIR_RUN Release MAC

Figure A-41. FIRDEBUGCTL Register

A-86

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-49. FIRDEBUGCTL Register Bit Descriptions (RW)

Bits 0 Name FIR_DBGMO DE Debug Mode Enable. 0 = Disable 1 = Enable For local memory access, the FIRCTL1 register can be cleared. Hold Or Single Step. The function of this bit is based on the FIR_DBGMEM bit setting. For FIR_DBGMEM = 0: 1 = Single step for FIR_DBGMEM = 1: 1 = Hold data Release MAC. This bit is self clearing after one FIR clock cycle.

FIR_HLD

2 (RW1S) 3 4 5

FIR_RUN Reserved FIR_DBGME M FIR_ADRINC

Local Memory Access. If set, the data and coefficients memory can be indirectly accessed. Address Auto Increment. If this bit is set, the address register auto increments on DBGMEMWRDAT write and DBGMEMRDDAT reads.

316

Reserved

IIR Accelerator Registers

The following sections describe the registers used to program and debug the FIR accelerator. IIR Global Control Register (IIRCTL1) The IIRCTL1 register, shown in Figure A-42 and described in Table A-50, is used to configure the global parameters for the accelerator. These include number of channels, channel auto iterate, DMA enable, and accelerator enable.

ADSP-214xx SHARC Processor Hardware Reference

A-87

Peripheral Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

IIR_RND (1614) Rounding Mode Select For Floating-point Mode

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IIR_RND (1614) Rounding Mode IIR_FORTYBIT 40-Bit Floating-Point Select IIR_CCINTR Channel Complete Interrupt IIR_SS Save Biquad State

IIR_EN Accelerator Enable NCH (51) Number of Channels IIR_DMAEN DMA Enable IIR_CAI Channel Auto Iterate

Figure A-42. IIRCTL1 Register Table A-50. IIRCTL1 Register Bit Descriptions (RW)
Bits 0 Name IIR_EN Description IIR Enable. 0 = IIR disabled 1 = IIR enabled Number of Channels. Programmable between 023 Channels = NCH + 1

51 76 8

IIR_NCH Reserved IIR_DMAEN

DMA Enable. 0 = Disable 1 = Enable Channel Auto Iterate. 0 = TDM processing stops (idle) once all channels complete processing 1 = Moves to first channel and continues TDM processing in a loop when all channels complete processing Save Biquad State. Stores the Dk registers settings into the internal memory. This can be used to save the biquad states before switching to another high priority accelerator task.

IIR_CAI

10

IIR_SS

A-88

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-50. IIRCTL1 Register Bit Descriptions (RW) (Contd)

Bits 11 Name IIR_CCINTR Description Channel Complete Interrupt. 0 = Interrupt is generated only when all channels are done (default) 1 = Interrupt is generated after each channels is done (default) 40-Bit Floating-Point Format Select. 0 = 32-bit IEEE floating-point 1 = 40-bit IEEE floating-point

12

IIR_FORTYBIT

13 1614

Reserved IIR_RND Rounding Mode Select For Floating-point Mode. 000 = IEEE round to nearest (even) 001 = IEEE round to zero 010 = IEEE round to +ve infinity 011 = IEEE round to -ve infinity 100 = Round to nearest Up 101 = Round away from zero 110 = Reserved 111 = Reserved

3117

Reserved

IIR Channel Control Register (IIRCTL2) The IIRCTL2 register, shown in Figure A-43 and described in Table A-51, is used to configure the channel specific parameters. These include number of biquads and window size.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IIR_WINDOW (2314) Window Size

15 14 13 12

11 10

IIR_WINDOW (2314) Window Size

IIR_BIQUADS (30) Number of Biquads

Figure A-43. IIRCTL2 Register

ADSP-214xx SHARC Processor Hardware Reference

A-89

Peripheral Registers

Table A-51. IIRCTL2 Register Bit Descriptions (RW)

Bits 30 134 2314 Name IIR_BIQUADS Reserved IIR_WINDOW Window Size Parameter. Window size specifies the number of sample/block to process (sample based processing = window size of 1) Description Number of Biquads. Programmable between 011. Number of Biquads = BIQUADS + 1

3124

Reserved

IIR MAC Status Register (IIRMACSTAT) The IIRMACSTAT register, shown in Figure A-44 and described in Table A-52, provides the status of MAC operations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IIR_MRZ IIR_AINV IIR_ARI IIR_ARZ IIR_MRI IIR_MINV

Figure A-44. IIRMACSTAT Register Table A-52. IIRMACSTAT Register Bit Descriptions (RO)
Bits 0 1 2 3 4 5 316 Name IIR_MRZ IIR_MRI IIR_MINV IIR_ARZ IIR_ARI IIR_AINV Reserved Description Multiplier Result Zero. Set if multiplier results is zero. Multiplier Result Infinity. Set if multiplier results is infinity. Multiply Invalid. Set if multiply operation is invalid. Adder Result Zero. Set if adder results is zero. Adder Result Infinity. Set if adder results is infinity. Addition Invalid. Set if addition is invalid.

A-90

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

IIR DMA Status Register (IIRDMASTAT) The IIR DMA registers are described in Data Transfer on page 7-14. The IIRDMASTAT register, shown in Figure A-45 and described in Table A-53, provides the status of DMA operations. All the bits in this register are read only.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

IIR_DMAURCHNL (117) Current Channel IIR_DMAACDONE All Channels Done IIR_DMAWDONE Processing of Current Channel Done IIR_DMASVDK Saving Updated Dk State in Internal Memory

IIR_DMACPL Chain Pointer Load Status IIR_DMACNDKLD Coefficient Loading IIR_DMAPPGS MAC Processing in Process IIR_DMAWRBK Write Back Updated Index Pointers

Figure A-45. IIRDMASTAT Register Table A-53. IIRDMASTAT Register Bit Descriptions (RO)
Bits 0 1 2 3 4 5 (ROC) Name IIR_DMACPL IIR_DMACnDkLD IIR_DMAPPGS IIR_DMAWRBK IIR_DMASVDk IIR_DMAWDONE Description Chain Pointer Loading Status. 1 = state machine in chain pointer load state Coefficient and Dk Loading. MAC Processing In Progress. Writing Back Updated Index Registers. Saving Updated Dk State in Internal Memory. Processing of Current Channel Done. Sticky, cleared on register read. The IIR_CCINTR bit will not affect the IIR_DMAWDONE Status Bit

ADSP-214xx SHARC Processor Hardware Reference

A-91

Peripheral Registers

Table A-53. IIRDMASTAT Register Bit Descriptions (RO) (Contd)

Bits 6 (ROC) Name IIR_DMAACDONE Description All Channels Done. Sticky, cleared on register read. The IIR_CCINTR bit will not affect the IIR_DMAACDONE Status Bit Current Channel. Channel that is being processed in the TDM slot. Zero indicates the last slot.

117 3112

IIR_DMACURCHNL Reserved

IIR Debug Registers (IIRDEBUGCTL, IIRDEBUGADDR) The IIRDEBUGCTL register, shown in Figure A-46 and described in Table A-54, controls the debug mode operation of the IIR accelerator. Note that these registers should only be used in debug mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

IIR_ADRINC Address Auto Increment IIR_DBGMEM Local Memory Access

IIR_DBGMODE Debug Mode Enable IIR_HLD Hold or Single Step IIR_RUN Release MAC

Figure A-46. IIRDEBUGCTL Register

A-92

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-54. IIRDEBUGCTL Register Bit Descriptions (RW)

Bits 0 Name IIR_DBGMODE Description Debug Mode Enable. 0 = Disable 1 = Enable For local memory access, the IIRCTL1 register can be cleared. Hold or Single Step. The function of this bit is based on the IIR_DBGMEM bit setting. For IIR_DBGMEM = 0: 1 = Single step For IIR_DBGMEM = 1: 1 = Hold data Release the MAC. This bit is self clearing after one IIR clock cycle.

IIR_HLD

2 (RW1S) 3 4 5

IIR_RUN Reserved IIR_DBGMEM IIR_ADRINC

Local Memory Access. If set, the data and coefficients memory can be indirectly accessed. Address Auto Increment. If this bit is set, the address register auto increments on IIRDBGWRDATA_H/ IIRDBGWRDATA_L writes and IIRDBGRDDATA_H/ IIRDBGRDDATA_L reads.

316

Reserved

Media Local Bus Registers

The registers in this section are used to program and get status information for the MLB interface and the specific channels used. MLB System Registers This section lists all different control and status registers related to the MLB controller.

ADSP-214xx SHARC Processor Hardware Reference

A-93

Peripheral Registers

Device Control Configuration Register (MLB_DCCR)

This register, shown in Figure A-47 and described in Table A-55, controls the device enable/disable, clock rate, lock status and addressing.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MDE MLB Device Enable LBM Loopback Mode Enable MCS (2928) MLB Clock Select M5PS MLB 5-pin Select
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MRS MLB Software Reset MHRE MLB Hardware Reset Enable MLE MLB Little-Endian Mode MLK MLB Lock

MDA (70) MLB Device Address

Figure A-47. MLB_DCCR Register Table A-55. MLB_DCCR Register Bit Descriptions (RW)
Bit 70 Name MDA Description MLB Device Address. Determines the unique device address (DA) for ADSP-214xx MediaLB device. MLB device address is 16 bits. Bits 15 9 and LSB are always zero. Only bits 81 vary and they are defined by MLB_DCCR bits 70. Device addresses are used by the system channel MLBSCAN command. MDA Device Address 00000001 0000 000'0 0000 001'0 = 0x0002 00000010 0000 000'0 0000 010'0 = 0x0004 00000011 0000 000'0 0000 100'0 = 0x0006 ---11111110 0000 000'1 1111 110'0 = 0x01FC For further information on assigning the device address, refer to the MLB specification.

228 23 (RW1S)

Reserved MRS MLB Software Reset. When set, resets the MLB physical and link layer logic. Hardware clears this bit automatically.

A-94

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-55. MLB_DCCR Register Bit Descriptions (RW) (Contd)

Bit 24 Name MHRE Description MLB Hardware Reset Enable. Enables hardware to automatically reset the MLB physical and link layer logic upon the reception MLB reset system command. 0 = Hardware reset option disabled 1 = MLB reset causes hardware reset MLB Little-Endian Mode. 0 = Big-Endian mode 1 = Little-Endian mode MLB Lock. When set, indicates that MLB port is synchronized to the incoming MLB frame. If MLK is clear (unlocked), it is set after FRAMESYNC is detected at the same position for three consecutive frames. If MLK is set (locked), it is cleared after not receiving FRAMESYNC at the expected time for two consecutive frames. While MLK is set, FRAMESYNC patterns occurring at locations other than the expected one are ignored. MLB 5-Pin Select. 0 = 3-pin MLB mode 1 = 5-pin MLB mode (legacy protocol to emulate MediaLB in software) MLB Clock Select. 00 = 256Fs supports 8 quadlets per frame 01 = 512Fs supports 16 quadlets per frame 10 = 1024Fs supports 32 quadlets per frame 11 = reserved Loopback Mode Enable. 0 = Loopback disabled 1 = Loopback enabled MLB Device Enable. 0 = MLB disabled 1 = MLB enabledThe MLB local channel buffer is immediately flushed by a HW or SW reset only

25

MLE

26 (RO)

MLK

27

M5PS

2928

MCS

30

LBM

31

MDE

ADSP-214xx SHARC Processor Hardware Reference

A-95

Peripheral Registers

System Status Register (MLB_SSCR)

This register, shown in Figure A-48 and described in Table A-56, allows system software to monitor and control the status of the MLB network. The register is updated once per frame by hardware during the MLB system channel. The bits of this register are not valid until the ADSP-214xx is locked to the MLB interface (except for the bits associated with MLB lock and unlock, SDMU and SDML). System software must service events before the start of the next MLB frame to prevent the current frame status from being lost.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

SSRE System Service Request Enable SDMU System Detects MLB Unlock SDML System Detects MLB Lock SDSC System Detects Subcommand

SDR System Detects Reset Command SDNL System Detects Network Lock SDNU System Detects Network Unlock SDCS System Detects Channel Scan

Figure A-48. MLB_SSCR Register Table A-56. MLB_SSCR Register Bit Descriptions (RW1C)
Bit 0 1 2 3 Name SDR SDNL SDNU SDCS Description System Detects Reset Command. When set, indicates MLB device has received MLBReset system command. System Detects Network Lock. When set, indicates the MLB device has received Most lock system command. System Detects Network Unlock. When set, indicates the MLB device has received MOST unlock system command. System Detects Channel Scan. When set, indicates the MLB device has received the MLBScan system command. The device address is stored in the SDCR register.

A-96

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-56. MLB_SSCR Register Bit Descriptions (RW1C) (Contd)

Bit 4 Name SDSC Description System Detects Subcommand. When set, indicates the MLB device has received the MLBSubCmd system command. The device command is stored in the SDCR register and decoding is performed by software. System Detects MLB Lock. When set, indicates the MLB device has locked onto the MLB frame. System Detects MLB Unlock.When set, indicates the MLB device has unlocked from the MLB frame. System Service Request Enable. When set, indicates that the MLB device needs service. Write 1 to set.

5 6

SDML SDMU

7 (RW1S) SSRE 318 Reserved

System Data Configuration Register (MLB_SDCR)

This register, described in Table A-57, allows system software to receive control information from the MLB controller. The MLB_SDCR register is updated once per frame by the hardware during the MLB system channel. This register is loaded with the data from the MLBDAT_IN signal during the system channel quadlet. System software must read the MLB_SDCR register before the start of the next MLB frame to prevent the current data from being lost. Table A-57. MLB_SDCR Register Description (RO)
Bit 310 Name SDATA Description System Channel Data.

ADSP-214xx SHARC Processor Hardware Reference

A-97

Peripheral Registers

System Mask Configuration Register (MLB_SMCR)

This register, described in Table A-58, allows system software to mask system status interrupts. When a mask bit is set, the corresponding system channel interrupt is masked.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

SMMU System Masks MLB Unlock SMML System Masks MLB Lock SMSC System Masks Subcommand

SMR System SMNU System SMNL System SMCS System

Masks Reset Command Masks Network Unlock Masks Network Lock Masks Channel Scan

Figure A-49. MLB_SMCR Register Table A-58. MLB_SMCR Register Bit Descriptions (RW)
Bit 0 2 1 3 4 5 Name SMR SMNU SMNL SMCS SMSC SMML Description System Masks Reset Command. When set, this bit masks system interrupts for Mlb Reset system command. System Masks Network Unlock. When set, this bit masks system interrupts for the MOST_unlock system command. System Masks Network Lock. When set, this bit masks system interrupts for the MOST_Lock system command. System Masks Channel Scan. When set, this bit masks system interrupts for MlbScan system command. System Masks Subcommand. When set, this bit masks system interrupts for MlbSubCmd (0xE6) system command. System Masks MLB Lock. When set, this bit masks system interrupts generated when MLB lock is detected. At reset, MLB lock events are masked, (SMML = 1).

A-98

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Register Reference

Table A-58. MLB_SMCR Register Bit Descriptions (RW) (Contd)

Bit 6 Name SMMU Description System Masks MLB Unlock. When set, this bit masks system interrupts generated when a MediaLB unlock is detected. At reset, MediaLB unlock events are masked (SMMU = 1).

317

Reserved

Channel Interrupt Status Register (MLB_CICR)

The channel interrupt status register reflects the channel interrupt status of the individual logical channels. The channel status update (CSU) bits are set by hardware when a channel interrupt is generated. The CSU bits are sticky and can only be reset by software. To clear a particular bit in this register, software must clear all of the unmasked status bits in the corresponding MLB_CSCRx registers. Table A-59. MLB_CICR Register Description (RO)
Bit 300 31 Name CSU Reserved Description Channel Status Update.

DMA Base Address Registers

The DMA address is constituted by a 5-bit base in the MLB base registers (for the corresponding channel mode select) and a 14-bit offset configured using the BCA bits in the MLB_CCBCRx register.
Synchronous Base Address Register (MLB_SBCR)

The MLB_SBCR, described in Table A-60, holds the base address of the system memory buffers of all synchronous channels in the device.

ADSP-214xx SHARC Processor Hardware Reference

A-99

Peripheral Registers

Table A-60. MLB_SBCR Register Bit Descriptions (RW)

Bit 40 155 2016 3121 Name STBA Reserved SRBA Reserved Synchronous receive base address for DMA mode Description Synchronous transmit base address for DMA mode

Asynchronous Base Address Register (MLB_ABCR)

The MLB_ABCR register, described in Table A-61, holds the base address of the system memory buffers of all asynchronous channels in the device. Table A-61. MLB_ABCR Register Bit Descriptions (RW)
Bit 40 155 2016 3121 Name ATBA Reserved ARBA Reserved Asynchronous receive base address for DMA mode Description Asynchronous transmit base address for DMA mode

Control Base Address Register (MLB_CBCR)

The MLB_CBCR register, described in Table A-62, hold the base address of the system memory buffers of all control channels in the device. Table A-62. MLB_CBCR Register Bit Descriptions (RW)
Bit 40 155 2016 3121 Name CTBA Reserved CRBA Reserved Control receive base address for DMA mode Description Control transmit base address for DMA mode

A-100

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Logical Channel Registers The MLB controller supports up to 31 logical channels. Therefore the variable in the register names is valid for x = 030. This section lists all different control and status registers related to the logical channels.
Channel Control Registers (MLB_CECRx)

These registers define the basic attributes of a given logical channel, such as the channel enable, channel direction, and channel address. Note the definition of the bit fields is dependent on the CTYPE bit field. If the selection is synchronous channels (default) than the Figure A-51 and Table A-64 are valid. If the CTYPE bits are asynchronous/control then the Figure A-50 and Table A-63 may apply. Figure A-50 and Table A-63 provide information for asynchronous and control channels and Figure A-51 and Table A-64 provide information for synchronous channels.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CE Channel x Enable CTRAN Channel x Transmit Select CTYPE (2928) Channel x Type Select

MASK (2316) Channel x Interrupt Mask MDS (2625) Channel x Mode Select PCE Packet Count Enable, I/O Mode
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCTH (128) Packet Count Threshold, I/O Mode

CA (70) Channel Address

Figure A-50. MLB_CECRx Register (Asynchronous and Control Channels)

ADSP-214xx SHARC Processor Hardware Reference

A-101

Peripheral Registers

Table A-63. MLB_CECRx Register Bit Descriptions for Asynchronous and Control Channels (RW)
Bit 70 Name CA Description Channel Address. These bits determine the channel address associated with this logical channel. MLB channel address is 16 bits; bits 159 and LSB are always zero. Only bits 81 vary and they are defined by MLB_CECRx bits 70. Channel Address 00000001 0x0002 00000010 0x0004 00000011 0x0006 00000100 0x0008 ............. 11111111 0x01FE For further information on assigning the device address, refer to the MLB specification. Packet Count Threshold, I/O Mode. Software can program this field with the number of packets to receive before generating an Rx packet-count service request. This service request is generated independent of, and in addition to, other service requests generated via the standard buffer threshold mechanism. In DMA mode these bits are reserved.

128

PCTH

1513 16

Reserved MASK0 Mask Protocol Error. When set, masks protocol error channel interrupts for this logical channel. This bit valid for all Rx channel types. This is valid for asynchronous and control Tx channels only. Mask Detect Break. When set, masks detect break channel interrupt for this logical channel. This bit is valid for asynchronous and control channels only. Masks Receive Service Request. When set, masks Rx channel service request interrupts for this logical channel. Mask Buffer Done. When set, masks buffer done channel interrupts for this logical channel. Masks Transmit Service Request. When set, masks Tx channel service request interrupts for this logical channel. Mask Buffer Start. When set, masks buffer start channel interrupts for this logical channel.

17

MASK1

18

MASK2 (I/O) MASK2 (DMA)

19

MASK3 (I/O) MASK3 (DMA)

A-102

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-63. MLB_CECRx Register Bit Descriptions for Asynchronous and Control Channels (RW) (Contd)
Bit 20 21 22 2423 2625 Name MASK4 Reserved MASK6 Reserved MDS Channel x Mode Select. 00 = Ping-pong DMA mode (default) 01 = reserved (only valid for synchronous channels) 10 = I/O mode enable 11 = Reserved Packet Count Enable. Enable the Rx packet counter. This bit is valid for asynchronous and control Rx channels in I/O mode. 0 = Disable 1 = Enable Channel x Type Select. 00 = Synchronous (default) 01 = Reserved 10 = Asynchronous 11 = Control Channel x Transmit Select. 0 = Receive (default) 1 = Transmit Channel x Enable. 0 = Channel n disabled (default) 1 = Enabled Mask Lost Frame Synchronization. When set, masks lost frame synchronization channel interrupts for this logical channel. Description Mask Buffer Error. When set, masks buffer error channel interrupts for this logical channel.

27

PCE

2928

CTYPE

30

CTRAN

31

CE

ADSP-214xx SHARC Processor Hardware Reference

A-103

Peripheral Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

CE Channel x Enable CTRAN Channel x Transmit Select CTYPE (2928) Channel x Type Select

MASK (2316) Channel x Interrupt Mask MDS Channel x Mode Select FSE Frame Synchronization Enable

15 14 13 12

11 10

FSCD Frame Synchronization Channel Disable FSPC (128) Frame Synchronization Physical Channel Count

CA (70) Channel Address

Figure A-51. MLB_CECRx Register (Synchronous Channels) Table A-64. MLB_CECRx Register Bit Descriptions for Synchronous Channels (RW)
Bit 70 Name CA Description Channel Address. These bits determine the channel address associated with this logical channel. MLB channel address is 16 bits; bits 159 and LSB are always zero. Only bits 81 vary and they are defined by MLB_CECRx bits 70. 00000001 0x0002 00000010 0x0004 00000011 0x0006 00000100 0x0008 ............. 11111111 0x01FE Frame Synchronization Physical Channel Count. Defines the number of physical channels (quadlets) expected to match this logical channels channel address each MLB frame.

128

FSPC

1413 15 1617

Reserved FSCD Reserved Frame Synchronization Channel Disable. When set, disables this logical channel when frame synchronization is lost.

A-104

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Register Reference

Table A-64. MLB_CECRx Register Bit Descriptions for Synchronous Channels (RW)
Bit 18 Name MASK2 (I/O) Description Masks Receive Service Request. When set, masks Rx channel service request interrupts for this logical channel. MASK2 (DMA) Mask Buffer Done. When set, masks buffer done channel interrupts for this logical channel. Masks Transmit Service Request. When set, masks Tx channel service request interrupts for this logical channel. MASK3 (DMA) Mask Buffer Start. When set, masks buffer start channel interrupts for this logical channel. MASK4 MASK5 MASK6 Reserved Reserved MDS Channel x Mode Select. 00 = Ping-pong DMA mode (default) 01 = Circular buffering DMA 10 = I/O mode enable 11 = Reserved Frame Synchronization Enable. When set, enables streaming channel frame synchronization for this logical synchronous channel. Channel x Type Select. 00 = Synchronous (default) 01 = Reserved 10 = Asynchronous 11 = Control Channel x Transmit Select. 0 = Receive (default) 1 = Transmit Channel x Enable. 0 = Channel x disabled (default) 1 = Enabled Mask Buffer Error. When set, masks buffer error channel interrupts for this logical channel. Reserved Mask Lost Frame Synchronization. When set, masks lost frame synchronization channel interrupts for this logical channel. MASK3 (I/O)

19

20 21 22 23 24 2625

27 2928

FSE CTYPE

30

CTRAN

31

CE

ADSP-214xx SHARC Processor Hardware Reference

A-105

Peripheral Registers

Channel Status Configuration Registers (MLB_CSCRx)

This register, shown in Figure A-52 and described in Table A-65, shows the status of the current and previous buffer for the logical channel. For all bits a 1 means the condition exists. Setting any of the STS110 bits clears the interrupt acknowledge for the corresponding interrupt channel.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BM Channel x Buffer Empty BF Channel x Buffer Full

RDY Next Buffer Ready GBREAK Generate Break

11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12

STS (11) Reserved (I/O) Previous Buffer Start (DMA) STS (10) Reserved (I/O) Previous Buffer Done (DMA) STS (9) Receive Packet Start (I/O) Previous Buffer Detect Break (DMA) STS (8) Transmit Service Request (I/O) Receive Packet Abort (DMA) STS (6) Lost Frame Sync

STS (0) Current Buffer Protocol Error STS (1) Current Buffer Detect Break STS (2) Receive Service Request (I/O) Current Buffer Done (DMA) STS (3) Transmit Service Request (I/O) Current Buffer Start (DMA) STS (4) Buffer Error STS (5) DMA Host Bus Error

Figure A-52. MLB_CECRx Register

A-106

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-65. MLB_CSCRx Register Description (RW1C)

Bit 0 Name STS0 Description Current Buffer Protocol Error. Indicates that either a TX channel has detected an RxStatus of ReceiverProtocolError (72h), an RX channel has detected an invalid command for a given channel type, or an additional ControlStart (30h) or AsyncStart (20h) command has been received while in the middle of a packet. This bit is valid for all RX channel types and valid for only asynchronous and control TX channels. Current Buffer Detect Break. Indicates that either a TX channel has detected a receiver break response, ReceiverBreak (70h), or an RX channel has detected a transmitter break command, ControlBreak (36h) or AsyncBreak (26h), while processing the Current Buffer. This bit is valid for asynchronous and control channels only. Receive Service Request (I/O). Indicates that an RX channel is requesting service from system software. Receive service requests are issued if the number of free quadlets in the local channel buffer is less than or equal to LCBCRn.TH[9:0]. This bit is valid for all channel types. Current Buffer Done (DMA). Indicates that the last quadlet from the last packet (in the Current Buffer) has been successfully transmitted or received. This bit is valid for all channel types. Transmit Service Request. Indicates that a TX channel is requesting service from system software. Transmit service requests are issued if the number of valid quadlets in the local channel buffer is less than or equal to LCBCRn.TH[9:0]. This bit is valid for all channel types. Current Buffer Start. Indicates that the DMA controller has started processing the Current Buffer. This bit is set after the contents of CNBCRn have been loaded into CCBCRn, the CSCRn.RDY bit has been cleared (for ping-pong buffering), and hardware is available to accept the next buffer. This bit is valid for all channel types. Buffer Error. Indicates that either a TX channel has detected a buffer underflow (attempt to pop data from an empty buffer), or an RX channel has detected a buffer overflow (attempt to push data onto a full buffer). This bit is valid for synchronous RX/TX (CECRn.FCE = 0) channels only. DMA Host Bus Error. Indicates that a DMA bus error has been detected. Lost Frame Sync. Indicates that the logical channel has lost synchronization with the MediaLB frame. This bit is valid for synchronous channels only.

STS1

STS2 (I/O)

STS2 (DMA) 3 STS3 (I/O)

STS3 (DMA)

STS4

5 6 7

STS5 (DMA) STS6 Reserved

ADSP-214xx SHARC Processor Hardware Reference

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Peripheral Registers

Table A-65. MLB_CSCRx Register Description (RW1C) (Contd)

Bit 8 Name STS8 (I/O) Description Receive Packet Abort. Indicates that an RX channel has detected an aborted packet. Received packets are aborted if the receiver generates a break response, ReceiverBreak (70h), or detects a transmitter packet break command; ControlBreak (36h) or AsyncBreak (26h). This bit can also indicate the RX channel has detected a transmit command protocol error. This interrupt can be used by system software to detect when it has encountered the beginning of an aborted packet. This bit is valid for asynchronous and control RX channels only. Previous Buffer Protocol Error. Indicates that either a TX channel has detected an RxStatus of ReceiverProtocolError (72h), a RX channel has detected an invalid command for this channel type, or an additional AsyncStart (20h) or ControlStart (30h) command has been received while in the middle of a packet. This bit is valid for all RX channels and valid for only asynchronous and control TX channels. Receive Packet Start. Indicates that an RX channel has detected a transmitter packet start command; ControlStart (30h) or AsyncStart (20h). This status bit can be used by system software to detect when it has reached the end of an aborted packet. This bit is valid for asynchronous and control RX channels only. Previous Buffer Detect Break. Indicates that either a TX channel has detected a receiver break response, ReceiverBreak (70h), or an RX channel has detected a transmitter break command, ControlBreak (36h) or AsyncBreak (26h), while processing the Previous Buffer. This bit is valid for all channel types. Previous Buffer Done. Indicates that the last quadlet of the Previous Buffer has been successfully transmitted or received. This bit is valid for all channel types. Reserved in I/O mode. Previous Buffer Start. Indicates the first quadlet of the Previous Buffer has been successfully transmitted or received. This bit is valid for all channel types. Reserved in I/O mode.

STS8 (DMA)

STS9 (I/O)

STS9 (DMA)

10

STS10 (DMA) STS11 (DMA) Reserved RDY

11

1512 16

Next Buffer Ready (DMA Mode). This bit is reserved for I/O mode. 0 = Next buffer ready for ping-pong DMA. Hardware clears this bit after the buffer begins to be processed. 1 = Next buffer ready for circular buffer DMA. Software should clear this RW1C bit only when buffer processing needs to be stopped.

17 (RW)

GBREAK Generate Break. 0 = No break 1 = Generate break

A-108

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-65. MLB_CSCRx Register Description (RW1C) (Contd)

Bit 2918 Name Reserved Channel x Buffer Full. When set, buffer is full. Channel x Buffer Empty. When set, buffer is empty. Description

30 (RO) BF 31 (RO) BM

Channel x Current Buffer Configuration Registers (MLB_CCBCRx)

The registers, described in Table A-66, allow software to monitor the address pointer and buffer length of the current DMA buffer in internal memory when the logical channel is configured in DMA mode. When configured in I/O mode, this register implements the Rx data buffer. The definition of the bit fields in this register vary depending on the selected channel type. The 5-bit offset of the DMA address comes from the base address registers. Table A-66. MLB_CCBCRx Register Bit Descriptions (RO)
Bit 10 152 1716 3118 BCA BFA Name Description Reserved for other channel types Buffer Final Address. Reserved for other channel types Buffer Current Address.

Channel x Next Buffer Configuration Registers (MLB_CNBCRx)

These registers, described in Table A-67, allows system software to set the start and end address of the next buffer in internal memory for the logical channel in DMA mode. When configured in I/O mode, these registers

ADSP-214xx SHARC Processor Hardware Reference

A-109

Peripheral Registers

implement the Tx data buffer. The definition of bit fields in this register vary dependant on the selected channel type. Table A-67. MLB_CNBCRx Register Description (RW)
Bit 10 152 1716 3118 BEA Reserved BSA Next Buffer Start Address. Name Description Reserved for other channel types Next Buffer End Address.

Local Buffer Configuration Registers (MLB_LCBCRx)

These registers, described in Table A-68, allow software to optimize the use of the local channel buffer memory. These registers should only be written by software while the logical channel is disabled. The size of the local channel buffer RAM is 124 words. At reset, this RAM is shared equally by all 31 channels with four words for each channel. The buffer depth can be up to 124 words (quadlets), when only one channel is used. Table A-68. MLB_LCBCRx Register Description (RW)
Bit 120 Name SA Description Buffer Start Address. Determines the starting address (in quadlets/4) of the channel buffer for the logical channel x. Reset value = {120, 116, 112 4, 0} for x = 30:0 0x0000 = start address offset of 0 words 0x0001 = start address offset of 4 words 0x0002 = start address offset of 8 words 0x001E = start address offset of 120 words 0x001F to 0x1FFF = Reserved

A-110

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-68. MLB_LCBCRx Register Description (RW)

Bit 2113 Name BD Description Buffer Depth. Defines the depth (in quadlets/41) of the local channel buffer for the logical channel x. 0x000 = depth = 4 words 0x001 = depth = 8 words 0x002 = depth = 12 words 0x01E = depth = 124 words 0x01F to 0x1FF = Reserved Reset value = 4 for all x=0:30 Buffer Threshold. Defines the threshold (in quadlets/2) of the local channel buffer for the logical channel x in I/O mode. Hardware uses this threshold value to determine when to issue an I/O service request to system software. Reset value = 2 for all x = 0:30 0x000 = threshold = 0 word 0x001 = threshold = 2 words 0x002 = threshold = 4 words . 0x03D = threshold = 122 words 0x03E to 0x3FF = Reserved Reserved in DMA mode

3122

TH

Watchdog Timer Registers

The following sections provide bit descriptions for the registers associated with the watchdog timer. Control (WDTCTL) The watchdog control register (WDTCTL), is a 32-bit system memory-mapped register used to configure the watchdog timer. A write to the WDT_EN bit enables the watchdog timer. This register is protected against accidental writes from the processor core by the watchdog unlock register (WDTUNLOCK). Attempts by the core to write to WDTCTL without an unlock command causes the WDT to expire, and reset the system. This condition

ADSP-214xx SHARC Processor Hardware Reference

A-111

Peripheral Registers

is captured in the watchdog exception field ( WDT_ERR bit in the WDTSTATUS register). Writes made by software to this register keep it enabled. Only an External hardware reset can clear WDTCTL. Reads from this register when WDT is disabled return 0x0, and when WDT is enabled, always return 0x1. Status (WDTSTATUS) The WDTSTATUS register, shown in Figure A-53 and described in Table A-69, contains the watchdog timer status information. This register is not cleared by the WDT generated reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

WDT_ERR Watchdog Exception

WDT_ROLL_OVER Watchdog Roll over

Figure A-53. WDTSTATUS Register Table A-69. WDTSTATUS Register Bit Descriptions (RW1C)
Bit 0 Name WDT_ROLL_OVER Description Watchdog Roll Over. Indicates that DSP core attempted to write to WDT configuration space without an unlock command. Bit is set when the above exception occurs. Software can determine whether the watchdog has expired by interrogating this bit. This is a sticky bit that is set whenever the watchdog timer count rolls over. Watchdog Error. Indicates that watchdog timer has expired. Bit is set when counter expires. Attempts by the core to write to the WDT configuration space without an unlock command, causes the WDT to expire and this condition is captured in the watchdog exception field. This is a sticky bit that is set whenever the above exception occurs.

WDT_ERR

A-112

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Current Count (WDTCURCNT) The WDTCURCNT register contains the current count value of the watchdog timer. Reads to WDTCURCNT return the current count value. For added safety, this register can only be updated when WDT configuration space is unlocked by programming the command in the WDTUNLOCK register. Values cannot be stored directly in WDTCURCNT, but are instead copied from WDTCNT. Enabling the watchdog timer does not automatically reload WDTCURCNT from WDTCNT. The WDTCURCNT register is a 32-bit unsigned system memory-mapped register that must be accessed with 32-bit reads and writes. Trip Counter (WDTTRIP) The WDT contains a software programmable register WDTTRIP that sets the number of times that the WDT can expire before the WDTRSTO pin is continually asserted until the next time hardware reset is applied. This register is unaffected by WDT generated reset. This register can only be updated when the WDT is disabled and WDT configuration space is unlocked by programming the command in the WDTUNLOCK register.

Writes to the cycles.

WDTCLK Bit 30 Name TRIPVAL

WDTCURCNT

register have a maximum latency of 2.5

Table A-70. WDTTRIP Register Bit Descriptions (RW)

Description Current Value of Trip Counter. This is the trip counter value, programmable from 0 to 15. The number of times WDT can expire is programmable by the TRIPVAL field Reading this register also gives the current value of the trip counter. Current Number of WDT Resets. Reports all current WDT generated resets (WDTRSTO asserted).

74 (RO)

CURTRIPVAL

ADSP-214xx SHARC Processor Hardware Reference

A-113

Peripheral Registers

Clock Select (WDTCLKSEL) This register, described in Table A-71, can only be updated when the WDT is disabled and WDT configuration space is unlocked by programming the command in the WDTUNLOCK register. Writes to the WDTCLKSEL register are ignored after the WDT is enabled. Note that his register is reset on external hardware reset only. This ensures that the selected clock source remains the same even after a WDT generated reset is asserted. Table A-71. WDTCLKSEL Register Bit Descriptions (RW)
Bit 0 Name Description WDT_CLK_INT_OSC Clock Select. When this bit = 0, the WDTCLK source can be an external clock applied to the WDT_CLKIN pin or an external ceramic oscillator connected to the WDT_CLKIN and WDT_CLKO pins. 0 = Selects ceramic oscillator output or external clock 1 = Selects internal RC oscillator output WDT_OSCPWRDWN Internal RC Oscillator Power Down. 0 = Oscillator is powered up 1 = Oscillator is powered down Internal RC Oscillator Reset. 0 = Oscillator is reset 1 = Oscillator out of reset

WDT_OSCNONRST

Period (WDTCNT) The WDTCNT register holds the 32-bit unsigned count value. The WDTCNT register must always be accessed with 32-bit read/writes. The watchdog count register holds the programmable count value. A valid write to the watchdog count register also pre loads the watchdog current counter. For added safety, the watchdog count register can only be updated when the WDT is disabled and WDT configuration space is unlocked by programming the command in the WDTUNLOCK register.

A-114

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Unlock (WDTUNLOCK) The WDTUNLOCK register protects the WDT configuration space against accidental writes from the processor core. Before attempting to write to the WDT configuration space, the core must unlock the WDT by writing the command value (0xAD21AD21) to this register. Attempts by the core to write to WDT configuration space without this command causes the WDT to expire. This exception is captured in the WDTSTATUS register. After configuring the WDT configuration space, the core needs to lock it again by writing any value other than the command value to the register.

Real-Time Clock Registers

The following sections describe the registers associated with the real-time clock (RTC). Control Register (RTC_CTL) This register, shown in Figure A-54 and described in Table A-72 control interrupt generation for the RTC.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

EMU_INTDIS Disables RTC interrupts in emulation mode CKFAIL_INTEN 1Hz Clock Fail Interrupt Enable STPWTCH_INTEN Stopwatch Interrupt Enable DAYALRM_INTEN Day Alarm Interrupt Enable ALRM_INTEN Alarm Interrupt Enable

WRDONE_INTEN Register Write Done Interrupt Enable SEC_INTEN Seconds Interrupt Enable MIN_INTEN Minutes Interrupt Enable HR_INTEN Hours Interrupt Enable DAY_INTEN Days Interrupt Enable

Figure A-54. RTC_CTL Register

ADSP-214xx SHARC Processor Hardware Reference

A-115

Peripheral Registers

Table A-72. RTC_CTL Register Bit Descriptions (RW)

Bit 0 Name WRDONE_INTEN Description Register Write Done Interrupt Enable. 0 = Register Write Done interrupt disabled 1 = Register Write Done interrupt enabled Seconds Interrupt Enable. 0 = Seconds interrupt disabled 1 = Seconds interrupt enabled Minutes Interrupt Enable. 0 = Minutes interrupt disabled 1 = Minutes interrupt enabled Hours Interrupt Enable. 0 = Hours interrupt disabled 1 = Hours interrupt enabled Days Interrupt Enable. 0 = Days interrupt disabled 1 = Days interrupt enabled Alarm Interrupt Enable. 0 = Alarm interrupt disabled 1 = Alarm interrupt enabled Day Alarm Interrupt Enable. 0 = Day alarm interrupt disabled 1 = Day alarm interrupt enabled Stopwatch Interrupt Enable. 0 = Stopwatch interrupt disabled 1 = Stopwatch interrupt enabled RTC 1Hz Clock Fail Interrupt Enable. Indicates that the oscillator failed to start. 0 = RTC 1Hz clock fail interrupt disabled 1 = RTC 1Hz clock fail interrupt enabled Disables/Enables RTC Interrupts in Emulation Mode. 0 = RTC interrupts enabled (if the individual interrupt enable bit is set) in emulation mode 1 = RTC interrupts disabled in emulation mode

SEC_INTEN

MIN_INTEN

HR_INTEN

DAY_INTEN

ALRM_INTEN

DAYALRM_INTEN

STPWTCH_INTEN

CKFAIL_INTEN

EMU_INTDIS

3110

Reserved

A-116

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Status Register (RTC_STAT) This register, shown in Figure A-55, The RTC Status register contains the RTC event flags and RTC interrupt status. These bits are sticky. Once set by the event, each bit remains set until cleared by a software read of this register. These sticky bits are independent of the interrupt enable bits in RTC_CTL register. Values are cleared by reading RTC_STAT register, except for the WR_PEND, ALRM_PEND and DAYALRM_PEND bits. Writes to any bit of this register has no effect. This register is cleared at reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

RTC_CKFAIL 1Hz Clock Status SW_EXP Stopwatch Counter Expired DAYALRM Day Alarm Flag DAY Day Event Flag ALRM Alarm Flag

WR_PEND Write Pending WR_DONE Write Complete Flag SEC Second Event Flag MIN Minute Event Flag HOUR Hour Event Flag

Figure A-55. RTC_STAT Register Table A-73. RTC_STAT Register Bit Descriptions (ROC)
Bit 0 (RO) Name WR_PEND Description 1 Hz Register Write Pending. Shows that write to 1 Hz registers (RTC_CLOCK, RTC_ALARM, RTC_SWTCH and RTC_INIT register) is pending. This bit is automatically cleared/set by hardware. 1 Hz Register Write Done. Returns status of write access to 1 Hz registers. 0 = Write pending. 1 = Write done

WR_DONE

ADSP-214xx SHARC Processor Hardware Reference

A-117

Peripheral Registers

Table A-73. RTC_STAT Register Bit Descriptions (ROC) (Contd)

Bit 2 Name SEC Description Second Event Flag. 0 = Second event has not occurred 1 = Second event has occurred Minute Event Flag. 0 = Minute event has not occurred 1 = Minute event has occurred (clock counter value x:y:z:59) Hour Event Flag. 0 = Hour event has not occurred 1 = Hour event has occurred (clock counter value x:y:59:59) Day Event Flag. 0 = Day event has not occurred 1 = Day event has occurred (clock counter value x:23:59:59) Alarm Flag. 0 = Daily alarm has not occurred 1 = Daily alarm has occurred Time of Day Flag. 0 = Alarm has not occurred 1 = Alarm has occurred Stop Watch Counter Expiration Flag. 0 = Stop watch counter has not expired 1 = Stop watch counter expired 1 Hz Clock Status. 0 = RTC 1 Hz clock is functional 1 = RTC 1 Hz clock failed

MIN

HOUR

DAY

6 (RO)

ALRM

7 (RO)

DAYALRM

SW_EXP

RTC_CKFAIL

Stopwatch Count Register (RTC_STPWTCH) This register, shown in Figure A-56, contains the countdown value for the stop watch. The stopwatch counts down seconds from the programmed value and generates an interrupt (if STPWTCH_INTEN = 1) when the count reaches 0. The register can be programmed to any value between 0 and

A-118

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

(216 1) seconds (that is, a range of 18 hours, 12 minutes and 15 seconds).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

STOP_WATCH Stop Watch Counter Value

Figure A-56. RTC_STPWTCH Register (RW) Clock Register (RTC_CLOCK) This register, shown in Figure A-57, is used to read or write the current time. It has no reset and an undefined value when the module is first powered up. This register is updated every second. If RTC is already running when the core starts up, the values read from RTC_CLOCK are zero until the first second event occurs. In this case, programs must wait for the second event and then read the register. Writes of invalid time values are forbidden.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

HOUR (16-12) (Cont) DAY (31-17) Day Count 032767 Hour Count 023

15 14 13 12

11 10

HOUR (16-12) Hour Count 023 MINUTE (11-6) Minute Count 059 SECOND (5-0) Second Count 059

Figure A-57. RTC_CLOCK Register (RW)

ADSP-214xx SHARC Processor Hardware Reference

A-119

Peripheral Registers

Alarm Register (RTC_ALARM) This register, shown in Figure A-58, is programmed by software for the time (in hours, minutes, and seconds) the alarm interrupt occurs. Reads and writes can occur at any time. The alarm interrupt occurs whenever the hour, minute, and second fields first match those of the RTC status register. The day interrupt occurs whenever the day, hour, minute, and second fields first match those of the RTC status register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

HOUR (16-12) (Cont) DAY (31-17) Alarm Day 032767 Alarm Hour 023

15 14 13 12

11 10

HOUR (16-12) Alarm Hour 023 MINUTE (11-6) Alarm Minute 059 SECOND (5-0) Alarm Second 059

Figure A-58. RTC Alarm Register (RW) Initialization Register (RTC_INIT) This register, shown in Figure A-59 and described in Table A-74, provides the calibration function, powers down the unit, and grounds these buses.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

RTC_BUSDIS Output Bus Disable

CALIB (30) Time Calibration RTC_PDN Power Down

Figure A-59. RTC_INIT Register

A-120

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-74. RTC_INIT Register Bit Descriptions (RW)

Bit 30 Name CALIB Description Time Calibration. Max 7 seconds. Calibration value is added/subtracted from the time every day at midnight. 1001 -> 1 second 1010 -> 2 second ---------------------1111 -> 7 second 0001 -> +1 second 0010 -> +2 second ----------------------0111 -> +7 second RTC Power Down. Active high. Write 1 to power down RTC oscillator, 0 to power up RTC oscillator. This bit must be compulsorily written once during first RTC oscillator power-up. 0 = RTC oscillator running 1 = Powers down RTC oscillator Bus Disable. Disables the bus and level shifter between core and IO domain. Setting this bit grounds this logic and prevents floating node consumption when the RTC is not used. 0 = Bus logic is enabled (RTC in use) 1 = Bus logic is disabled (RTC not in use)

RTC_PDN

RTC_BUSDIS

ADSP-214xx SHARC Processor Hardware Reference

A-121

Peripheral Registers

Initialization Status Register (RTC_INITSTAT) Figure A-60 and Table A-75 describe the bits in the RTC_INITSTAT register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

CALIB_STAT Calibration Status RTCPDN_STAT Oscillator Power Down

ALRM_PEND Alarm Occurred DAYALRM_PEND Day Alarm Occurred

Figure A-60. RTC_INITSTAT Register Table A-75. RTC_INITSTAT Register Bit Descriptions (RO)
Bit 0 (ROC) Name ALRM_PEND Description Time Calibration. Indicates that an alarm has occurred. (Useful if core has powered down or reset in the middle). 0 = No daily alarm has occurred 1 = A daily alarm has occurred This bit is cleared on reading RTC_INITSTAT. RTC Power Down. Indicates that an alarm has occurred. (Useful if core has powered down or reset in the middle.) 0 = No day alarm has occurred 1 = A day alarm had occurred This bit is cleared on reading RTC_INITSTAT. Power Down Status. Status of RTC oscillator powerdown bit. 0 = The RTC oscillator is running 1 = The RTC oscillator is powered down Calibration Status. Indicates whether CALIB value in the RTC_INIT register has been successfully programmed in the RTC. It should be equal to the value of CALIB.

1 (ROC)

DAYALRM_PEND

RTCPDN_STAT

63

CALIB_STAT

A-122

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

DAI Signal Routing Unit Registers

The digital applications interface is comprised of a group of peripherals and the signal routing unit (SRU). These register groups are described in the sections that follow. For each group, the source signals (outputs) and all associated destination signals (inputs) are listed.

Group A Clock Routing

The group A clock sources are listed in Table A-76. Source Signals Table A-76. Group A Sources Serial Clock
Selection Code 00000 (0x0) 00001 (0x1) 00010 (0x2) 00011 (0x3) 00100 (0x4) 00101 (0x5) 00110 (0x6) 00111 (0x7) 01000 (0x8) 01001 (0x9) 01010 (0xA) 01011 (0xB) 01100 (0xC) Source Signal DAI_PB01_O DAI_PB02_O DAI_PB03_O DAI_PB04_O DAI_PB05_O DAI_PB06_O DAI_PB07_O DAI_PB08_O DAI_PB09_O DAI_PB10_O DAI_PB11_O DAI_PB12_O DAI_PB13_O Description (Source Selection) Pin Buffer 1 Pin Buffer 2 Pin Buffer 3 Pin Buffer 4 Pin Buffer 5 Pin Buffer 6 Pin Buffer 7 Pin Buffer 8 Pin Buffer 9 Pin Buffer 10 Pin Buffer 11 Pin Buffer 12 Pin Buffer 13

ADSP-214xx SHARC Processor Hardware Reference

A-123

DAI Signal Routing Unit Registers

Table A-76. Group A Sources Serial Clock (Contd)

Selection Code 01101 (0xD) 01110 (0xE) 01111 (0xF) 10000 (0x10) 10001 (0x11) 10010 (0x12) 10011 (0x13) 10100 (0x14) 10101 (0x15) 10110 (0x16) 10111 (0x17) 11000 (0x18) 11001 (0x19) 11010 (0x1A) 11011 (0x1B) 11100 (0x1C) 11101 (0x1D) 11110 (0x1E) 11111 (0x1F) Source Signal DAI_PB14_O DAI_PB15_O DAI_PB16_O DAI_PB17_O DAI_PB18_O DAI_PB19_O DAI_PB20_O SPORT0_CLK_O SPORT1_CLK_O SPORT2_CLK_O SPORT3_CLK_O SPORT4_CLK_O SPORT5_CLK_O DIR_CLK_O DIR_TDMCLK_O PCG_CLKA_O PCG_CLKB_O LOW HIGH Description (Source Selection) Pin Buffer 14 Pin Buffer 15 Pin Buffer 16 Pin Buffer 17 Pin Buffer 18 Pin Buffer 19 Pin Buffer 20 SPORT 0 Clock SPORT 1 Clock SPORT 2 Clock SPORT 3 Clock SPORT 4 Clock SPORT 5 Clock SPDIF Receive Clock Output SPDIF Receive TDM Clock Output Precision Clock A Output Precision Clock B Output Logic Level Low (0) Logic Level High (1)

A-124

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Destination Signal Control Registers (SRU_CLKx) The SRU_CLKx registers are shown in Figure A-61 through Figure A-66.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPORT5_CLK_I (2925) Serial Port 5 Clock Input

SPORT3_CLK_I (1915) Serial Port 3 Clock Input SPORT4_CLK_I (2420) Serial Port 4 Clock Input

15 14 13 12

11 10

SPORT3_CLK_I (1915) SPORT2_CLK_I (1410) Serial Port 2 Clock Input SPORT0_CLK_I (40) Serial Port 0 Clock Input SPORT1_CLK_I (95) Serial Port 1 Clock Input

Figure A-61. SRU_CLK0 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SRC2_CLK_OP_I (2925) Sample Rate Converter 2 Clock Output Input

SRC1_CLK_OP_I (1915) Sample Rate Converter 1 Clock Output Input SRC2_CLK_IP_I (2420) Sample Rate Converter 2 Clock Input Input

15 14 13 12

11 10

SRC1_CLK_OP_I (1915) Sample Rate Converter 1 Clock Output Input SRC1_CLK_IP_I (1410) Sample Rate Converter 1 Clock Input Input

SRC0_CLK_IP_I (40) Sample Rate Converter 0 Clock Input Input SRC0_CLK_OP_I (95) Sample Rate Converter 0 Clock Output Input

Figure A-62. SRU_CLK1 Register (RW)

ADSP-214xx SHARC Processor Hardware Reference

A-125

DAI Signal Routing Unit Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

IDP2_CLK_I (2925) Input Data Port 2 Clock Input

IDP0_CLK_I (cont) (1915) Input Data Port 0 Clock Input IDP1_CLK_I (2420) Input Data Port 1 Clock Input

15 14 13 12

11 10

IDP0_CLK_I (1915) DIT_CLK_I (1410) SPDIF Transmitter Clock Input SRC3_CLK_OP_I (95) Sample Rate Converter 3 Clock Output Input SRC3_CLK_IP_I (40) Sample Rate Converter 3 Clock Input Input

Figure A-63. SRU_CLK2 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DIT_HFCLK_I (2925) SPDIF Oversampling Clock Input

IDP6_CLK_I (cont) (1915) Input Data Port Channel 6 Clock Input IDP7_CLK_I (2420) Input Data Port Channel 7 Clock Input

15 14 13 12

11 10

IDP6_CLK_I (1915) IDP5_CLK_I (1410) Input Data Port Channel 5 Clock Input IDP3_CLK_I (40) Input Data Port Channel 3 Clock Input IDP4_CLK_I (95) Input Data Port Channel 4 Clock Input

Figure A-64. SRU_CLK3 Register (RW)

A-126

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

PCG_SYNC_CLKB_I (2925) Precision Clock Generator Clock B Sync Input

DIT_EXT_SYNC_I (1915) S/PDIF Transmitter Clock Input PCG_SYNC_CLKA_I Precision Clock Generator Clock A Sync Input

15 14 13 12

11 10

DIT_EXT_SYNC_I (1915) PCG_EXTB_I (95) Precision Clock Generator External Clock B Input

PCG_EXTA_I (40) Precision Clock Generator External Clock A Input

Figure A-65. SRU_CLK4 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PCG_EXTD_I Precision Clock Generator External Clock D Input

PCG_SYNC_CLKD_I Precision Clock Generator Clock D Sync Input PCG_EXTC_I Precision Clock Generator External Clock C Input

15 14 13 12

11 10

PCG_SYNC_CLKD_I Precision Clock Generator Clock D Sync Input PCG_SYNC_CLKC_I Precision Clock Generator Clock C Sync Input

SPORT6_CLK_I Serial Port 6 Clock Input SPORT7_CLK_I Serial Port 7 Clock Input

Figure A-66. SRU_CLK5 Register (RW)

ADSP-214xx SHARC Processor Hardware Reference

A-127

DAI Signal Routing Unit Registers

Group B Serial Data Routing

The data sources are based on the 6-bit values shown in Table A-77. Source Signals Table A-77. Group B Sources Serial Data
Selection Code 000000 (0x0) 000001 (0x1) 000010 (0x2) 000011 (0x3) 000100 (0x4) 000101 (0x5) 000110 (0x6) 000111 (0x7) 001000 (0x8) 001001 (0x9) 001010 (0xA) 001011 (0xB) 001100 (0xC) 001101 (0xD) 001110 (0xE) 001111 (0xF) 010000 (0x10) 010001 (0x11) 010010 (0x12) 010011 (0x13) 010100 (0x14) Source Signal DAI_PB01_O DAI_PB02_O DAI_PB03_O DAI_PB04_O DAI_PB05_O DAI_PB06_O DAI_PB07_O DAI_PB08_O DAI_PB09_O DAI_PB10_O DAI_PB11_O DAI_PB12_O DAI_PB13_O DAI_PB14_O DAI_PB15_O DAI_PB16_O DAI_PB17_O DAI_PB18_O DAI_PB19_O DAI_PB20_O SPORT0_DA_O Description (Source Selection) Pin Buffer 1 Pin Buffer 2 Pin Buffer 3 Pin Buffer 4 Pin Buffer 5 Pin Buffer 6 Pin Buffer 7 Pin Buffer 8 Pin Buffer 9 Pin Buffer 10 Pin Buffer 11 Pin Buffer 12 Pin Buffer 13 Pin Buffer 14 Pin Buffer 15 Pin Buffer 16 Pin Buffer 17 Pin Buffer 18 Pin Buffer 19 Pin Buffer 20 SPORT 0A Data

A-128

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-77. Group B Sources Serial Data (Contd)

Selection Code 010101 (0x15) 010110 (0x16) 010111 (0x17) 011000 (0x18) 011001 (0x19) 011010 (0x1A) 011011 (0x1B) 011100 (0x1C) 011101 (0x1D) 011110 (0x1E) 011111 (0x1F) 100000 (0x20) 100001 (0x21) 100010 (0x22) 100011 (0x23) 100100 (0x24) 100101 (0x25) 100110 (0x26) 100111 (0x27) 101000 (0x28) 101100(0x2C) 101101(0x2D) 101110(0x2E) 101111(0x2F) 110000(0x30) 110001(0x31)111101(0x3D) Source Signal SPORT0_DB_O SPORT1_DA_O SPORT1_DB_O SPORT2_DA_O SPORT2_DB_O SPORT3_DA_O SPORT3_DB_O SPORT4_DA_O SPORT4_DB_O SPORT5_DA_O SPORT5_DB_O SRC0_DAT_OP_O SRC1_DAT_OP_O SRC2_DAT_OP_O SRC3_DAT_OP_O SRC0_TDM_IP_O SRC1_TDM_IP_O SRC2_TDM_IP_O SRC3_TDM_IP_O DIR_DAT_O SPORT6_DA_O SPORT6_DB_O SPORT7_DA_O SPORT7_DB_O DIT_O Reserved Description (Source Selection) SPORT 0B Data SPORT 1A Data SPORT 1B Data SPORT 2A Data SPORT 2B Data SPORT 3A Data SPORT 3B Data SPORT 4A Data SPORT 4B Data SPORT 5A Data SPORT 5B Data SRC0 Data Out SRC1 Data Out SRC2 Data Out SRC3 Data Out SRC0 Data Out SRC1 Data Out SRC2 Data Out SRC3 Data Out SPDIF RX Serial Data Out SPORT 6A Data SPORT 6B Data SPORT 7A Data SPORT 7B Data SPDIF TX Biphase Stream

ADSP-214xx SHARC Processor Hardware Reference

A-129

DAI Signal Routing Unit Registers

Table A-77. Group B Sources Serial Data (Contd)

Selection Code 111110 (0x3E) 111111 (0x3F) Source Signal LOW HIGH Description (Source Selection) Logic Level Low (0) Logic Level High (1)

Destination Signal Control Registers (SRU_DATx) The serial data routing control registers, shown in Figure A-67 through Figure A-73 route serial data to the serial ports (A and B data channels) and the input data port.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPORT2_DA_I (2924) Serial Port 2 Data Channel A Input SPORT1_DB_I (2318) Serial Port 1 Data Channel B Input

SPORT1_DA_I (1712) (cont) Serial Port 1 Data Channel A Input

15 14 13 12

11 10

SPORT1_DA_I (1712) SPORT0_DB_I (116) Serial Port 0 Data Channel B Input SPORT0_DA_I (50) Serial Port 0 Data Channel A Input

Figure A-67. SRU_DAT0 Register (RW)

A-130

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

SPORT4_DB_I (2924) Serial Port 4 Data Channel B Input SPORT4_DA_I (2318) Serial Port 4 Data Channel A Input

SPORT3_DB_I (1712) (cont) Serial Port 3 Data Channel B Input

15 14 13 12

11 10

SPORT3_DB_I (1712) SPORT3_DA_I (116) Serial Port 3 Data Channel A Input SPORT2_DB_I (05) Serial Port 2 Data Channel B Input

Figure A-68. SRU_DAT1 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SRC2_DAT_IP_I (2924) Sample Rate Converter 2 Data Input Input SRC1_DAT_IP_I (2318) Sample Rate Converter 1 Data Input Input

SRC0_DAT_IP_I (1712) (cont) Sample Rate Converter 0 Data Input Input

15 14 13 12

11 10

SRC0_DAT_IP_I (1712) SPORT5_DB_I (116) Serial Port 5 Data Channel B Input SPORT5_DA_I (50) Serial Port 5 Data Channel A Input

Figure A-69. SRU_DAT2 Register (RW)

ADSP-214xx SHARC Processor Hardware Reference

A-131

DAI Signal Routing Unit Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

SRC3_TDM_OP_I (2924) Sample Rate Converter 3 TDM Output Input

SRC1_TDM_OP_I (1712) (cont) Sample Rate Converter 1 TDM Output Input SRC2_TDM_OP_I (2318) Sample Rate Converter 2 TDM Output Input

15 14 13 12

11 10

SRC1_TDM_OP_I (1712) SRC0_TDM_OP_I (116) Sample Rate Converter 0 TDM Output Input SRC3_DAT_IP_I (50) Sample Rate Converter 3 Data Input Input

Figure A-70. SRU_DAT3 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IDP3_DAT_I (2924) Input Data Port 3 Data Input

IDP1_DAT_I (1712) (cont) Input Data Port 1 Data Input IDP2_DAT_I (2318) Input Data Port 2 Data Input

15 14 13 12

11 10

IDP1_DAT_I (1712) IDP0_DAT_I (116) Input Data Port 0 Data Input

DIT_DAT_I (50) SPDIF Transmit Data Input

Figure A-71. SRU_DAT4 Register (RW)

A-132

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DIR_I (2924) SPDIF Biphase Receiver Stream IDP7_DAT_I (2318) Input Data Port 7 Data Input

IDP6_DAT_I (1712) (cont) Input Data Port 6 Data Input

15 14 13 12

11 10

IDP6_DAT_I (1712) IDP5_DAT_I (116) Input Data Port 5 Data Input

IDP4_DAT_I (05) Input Data Port 4 Data Input

Figure A-72. SRU_DAT5 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPORT7_DB_I Serial Port 7 Data Channel BA Input

SPORT7_DA_I Serial Port 7 Data Channel A Input

15 14 13 12

11 10

SPORT7_DA_I Serial Port 7 Data Channel A Input SPORT6_DB_I Serial Port 6 Data Channel B Input

SPORT6_DA_I Serial Port 6 Data Channel A Input

Figure A-73. SRU_DAT6 Register (RW)

Group C Frame Sync Routing

The frame sync sources are based on the 5-bit values described in Table A-78.

ADSP-214xx SHARC Processor Hardware Reference

A-133

DAI Signal Routing Unit Registers

Source Signals Table A-78. Group C Sources Frame Sync

Selection Code 00000 (0x0) 00001 (0x1) 00010 (0x2) 00011 (0x3) 00100 (0x4) 00101 (0x5) 00110 (0x6) 00111 (0x7) 01000 (0x8) 01001 (0x9) 01010 (0xA) 01011 (0xB) 01100 (0xC) 01101 (0xD) 01110 (0xE) 01111 (0xF) 10000 (0x10) 10001 (0x11) 10010 (0x12) 10011 (0x13) 10100 (0x14) 10101 (0x15) 10110 (0x16) 10111 (0x17) Source Signal DAI_PB01_O DAI_PB02_O DAI_PB03_O DAI_PB04_O DAI_PB05_O DAI_PB06_O DAI_PB07_O DAI_PB08_O DAI_PB09_O DAI_PB10_O DAI_PB11_O DAI_PB12_O DAI_PB13_O DAI_PB14_O DAI_PB15_O DAI_PB16_O DAI_PB17_O DAI_PB18_O DAI_PB19_O DAI_PB20_O SPORT0_FS_O SPORT1_FS_O SPORT2_FS_O SPORT3_FS_O Description (Source Selection) Pin Buffer 1 Pin Buffer 2 Pin Buffer 3 Pin Buffer 4 Pin Buffer 5 Pin Buffer 6 Pin Buffer 7 Pin Buffer 8 Pin Buffer 9 Pin Buffer 10 Pin Buffer 11 Pin Buffer 12 Pin Buffer 13 Pin Buffer 14 Pin Buffer 15 Pin Buffer 16 Pin Buffer 17 Pin Buffer 18 Pin Buffer 19 Pin Buffer 20 SPORT 0 Frame Sync SPORT 1 Frame Sync SPORT 2 Frame Sync SPORT 3 Frame Sync

A-134

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-78. Group C Sources Frame Sync (Contd)

Selection Code 11000 (0x18) 11001 (0x19) 11010 (0x1A) 11011 (0x1B) 11100 (0x1C) 11101 (0x1D) 11110 (0x1E) 11111 (0x1F) Source Signal SPORT4_FS_O SPORT5_FS_O DIR_FS_O Reserved PCG_FSA_O PCG_FSB_O LOW HIGH Precision Frame Sync A Output Precision Frame Sync B Output Logic Level Low (0) Logic Level High (1) Description (Source Selection) SPORT 4 Frame Sync SPORT 5 Frame Sync SPDIF RX Frame Sync Output

Destination Signal Control Registers (SRU_FSx) The frame sync routing control registers are shown in Figure A-74 through Figure A-78.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPORT5_FS_I (2925) Serial Port 5 Frame Sync Input

SPORT3_FS_I (1915) (cont) Serial Port 3 Frame Sync Input SPORT4_FS_I (2420) Serial Port 4 Frame Sync Input

15 14 13 12

11 10

SPORT3_FS_I (1915) SPORT2_FS_I (1410) Serial Port 2 Frame Sync Input SPORT0_FS_I (40) Serial Port 0 Frame Sync Input SPORT1_FS_I (95) Serial Port 1 Frame Sync Input

Figure A-74. SRU_FS0 Register (RW)

ADSP-214xx SHARC Processor Hardware Reference

A-135

DAI Signal Routing Unit Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

SRC2_FS_OP_I (2925) Sample Rate Converter 2 Frame Sync Output Input

SRC1_FS_OP_I (1915) (cont) Sample Rate Converter 1 Frame Sync Output Input SRC2_FS_IP_I (2420) Sample Rate Converter 2 Frame Sync Input Input

15 14 13 12

11 10

SRC1_FS_OP_I (1915) SRC1_FS_IP_I (1410) Sample Rate Converter 1 Frame Sync Input Input

SRC0_FS_IP_I (40) Sample Rate Converter 0 Frame Sync Input Input SRC0_FS_OP_I (95) Sample Rate Converter 0 Frame Sync Output Input

Figure A-75. SRU_FS1 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IDP2_FS_I (2925) Input Data Port Channel 2 Frame Sync Input

IDP0_FS_I or PDAP_HOLD_I (1915) (cont) Input Data Port Channel 0 Frame Sync Input IDP1_FS_I (2420) Input Data Port Channel 1 Frame Sync Input

15 14 13 12

11 10

IDP0_FS_I or PDAP_HOLD_I (1915) DIT_FS_I (1410) SPDIF 3 Oversampling Clock Input

SRC3_FS_IP_I (40) Sample Rate Converter 3 Frame Sync Input Input SRC3_FS_OP_I (95) Sample Rate Converter 3 Frame Sync Output Input

Figure A-76. SRU_FS2 Register (RW)

A-136

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

IDP7_FS_I (2420) Input Data Port Channel 7 Frame Sync Input

IDP6_FS_I (1915) (cont) Input Data Port Channel 6 Frame Sync Input

15 14 13 12

11 10

IDP6_FS_I (1915) IDP5_FS_I (1410) Input Data Port Channel 5 Frame Sync Input IDP4_FS_I (95) Input Data Port Channel 4 Frame Sync Input IDP3_FS_I (40) Input Data Port Channel 3 Frame Sync Input

Figure A-77. SRU_FS3 Register (RW)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPORT7_FS_I (95) Serial Port 7 Frame Sync Input

SPORT6_FS_I (40) Serial Port 6 Frame Sync Input

Figure A-78. SRU_FS4 Register (RW)

Group D Pin Buffer Signal Assignments

Table A-79 lists the 7-bit source signals which may be assigned to the pin buffers. Source Signals Table A-79. Group D Sources Pin Signal Assignments
Selection Code 0000000 (0x0) 0000001 (0x1) 0000010 (0x2) 0000011 (0x3) Source Signal DAI_PB01_O DAI_PB02_O DAI_PB03_O DAI_PB04_O Description (Source Selection) Pin Buffer 1 Pin Buffer 2 Pin Buffer 3 Pin Buffer 4

ADSP-214xx SHARC Processor Hardware Reference

A-137

DAI Signal Routing Unit Registers

Table A-79. Group D Sources Pin Signal Assignments (Contd)

Selection Code 0000100 (0x4) 0000101 (0x5) 0000110 (0x6) 0000111 (0x7) 0001000 (0x8) 0001001 (0x9) 0001010 (0xA) 0001011 (0xB) 0001100 (0xC) 0001101 (0xD) 0001110 (0xE) 0001111 (0xF) 0010000 (0x10) 0010001 (0x11) 0010010 (0x12) 0010011 (0x13) 0010100 (0x14) 0010101 (0x15) 0010110 (0x16) 0010111 (0x17) 0011000 (0x18) 0011001 (0x19) 0011010 (0x1A) 0011011 (0x1B) 0011100 (0x1C) 0011101 (0x1D) Source Signal DAI_PB05_O DAI_PB06_O DAI_PB07_O DAI_PB08_O DAI_PB09_O DAI_PB10_O DAI_PB11_O DAI_PB12_O DAI_PB13_O DAI_PB14_O DAI_PB15_O DAI_PB16_O DAI_PB17_O DAI_PB18_O DAI_PB19_O DAI_PB20_O SPORT0_DA_O SPORT0_DB_O SPORT1_DA_O SPORT1_DB_O SPORT2_DA_O SPORT2_DB_O SPORT3_DA_O SPORT3_DB_O SPORT4_DA_O SPORT4_DB_O Description (Source Selection) Pin Buffer 5 Pin Buffer 6 Pin Buffer 7 Pin Buffer 8 Pin Buffer 9 Pin Buffer 10 Pin Buffer 11 Pin Buffer 12 Pin Buffer 13 Pin Buffer 14 Pin Buffer 15 Pin Buffer 16 Pin Buffer 17 Pin Buffer 18 Pin Buffer 19 Pin Buffer 20 SPORT 0A Data SPORT 0B Data SPORT 1A Data SPORT 1B Data SPORT 2A Data SPORT 2B Data SPORT 3A Data SPORT 3B Data SPORT 4A Data SPORT 4B Data

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Register Reference

Table A-79. Group D Sources Pin Signal Assignments (Contd)

Selection Code 0011110 (0x1E) 0011111 (0x1F) 0100000 (0x20) 0100001 (0x21) 0100010 (0x22) 0100011 (0x23) 0100100 (0x24) 0100101 (0x25) 0100110 (0x26) 0100111 (0x27) 0101000 (0x28) 0101001 (0x29) 0101010 (0x2A) 0101011 (0x2B) 0101100 (0x2C) 0101101 (0x2D) 0101110 (0x2E) 0101111 (0x2F) 0110000 (0x30) 0110001 (0x31) 0110100 (0x34) 0110101 (0x35) 0110110 (0x36) 0110111 (0x37) 0111000 (0x38) 0111001 (0x39) Source Signal SPORT5_DA_O SPORT5_DB_O SPORT0_CLK_O SPORT1_CLK_O SPORT2_CLK_O SPORT3_CLK_O SPORT4_CLK_O SPORT5_CLK_O SPORT0_FS_O SPORT1_FS_O SPORT2_FS_O SPORT3_FS_O SPORT4_FS_O SPORT5_FS_O SPORT6_DA_O SPORT6_DB_O SPORT7_DA_O SPORT7_DB_O PDAP_STRB_O DIT_BLKSTART_O SPORT6_CLK_O SPORT7_CLK_O SPORT6_FS_O SPORT7_FS_O PCG_CLKA_O PCG_CLKB_O Description (Source Selection) SPORT 5A Data SPORT 5B Data SPORT 0 Clock SPORT 1 Clock SPORT 2 Clock SPORT 3 Clock SPORT 4 Clock SPORT 5 Clock SPORT 0 Frame Sync SPORT 1 Frame Sync SPORT 2 Frame Sync SPORT 3 Frame Sync SPORT 4 Frame Sync SPORT 5 Frame Sync SPORT 6A Data SPORT 6B Data SPORT 7A Data SPORT 7B Data PDAP Data Transfer Request Strobe S/PDIF TX Block Start Output SPORT 6 Clock SPORT 7 Clock SPORT 6 Frame Sync SPORT 7 Frame Sync Precision Clock A Precision Clock B

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Table A-79. Group D Sources Pin Signal Assignments (Contd)

Selection Code 0111010 (0x3A) 0111011 (0x3B) 0111100 (0x3C) 0111101 (0x3D) 0111110 (0x3E) 0111111 (0x3F) 1000000 (0x40) 1000001 (0x41) 1000010 (0x42) 1000011 (0x43) 1000100 (0x44) 1000101 (0x45) 1000110 (0x46) 1000111 (0x47) 1001000 (0x48) 1001001 (0x49) 1001010 (0x4A) 1001011 (0x4B) 1001100 (0x4C) 1001101 (0x4D) 1001110 (0x4E) 1001111 (0x4F) 1010000 (0x50) 1011001 (0x51) 1011010 (0x52) 1010011 (0x53) Source Signal PCG_FSA_O PCG_FSB_O Reserved SRC0_DAT_OP_O SRC1_DAT_OP_O SRC2_DAT_OP_O SRC3_DAT_OP_O DIR_DAT_O DIR_FS_O DIR_CLK_O DIR_TDMCLK_O DIT_O SPORT0_TDV_O SPORT1_TDV_O SPORT2_TDV_O SPORT3_TDV_O SPORT4_TDV_O SPORT5_TDV_O SPORT6_TDV_O SPORT7_TDV_O Reserved Reserved PCG_CLKC_O PCG_CLKD_O PCG_FSC_O PCG_FSD_O Precision Clock C Precision Clock D Precision Frame Sync C Precision Frame Sync D SRC0 Data Output SRC1 Data Output SRC2 Data Output SRC3 Data Output SPDIF_RX Data Output SPDIF_RX Frame Sync Output SPDIF_RX Clock Output SPDIF_RX TDM Clock Output SPDIF TX Biphase Encoded Data Output SPORT0 Transmit Data Valid Output SPORT1 Transmit Data Valid Output SPORT2 Transmit Data Valid Output SPORT3 Transmit Data Valid Output SPORT4 Transmit Data Valid Output SPORT5 Transmit Data Valid Output SPORT6 Transmit Data Valid Output SPORT7 Transmit Data Valid Output Description (Source Selection) Precision Frame Sync A Precision Frame Sync B

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Table A-79. Group D Sources Pin Signal Assignments (Contd)

Selection Code 1010100 1111101 1111110 (0x7E) 1111111 (0x7F) Source Signal Reserved LOW HIGH Logic Level Low (0) Logic Level High (1) Description (Source Selection)

Destination Signal Control Registers (SRU_PINx) Each physical pin (connected to a bonded pad) may be routed using the pin signal assignment registers shown in Figure A-79 through Figure A-83.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DAI_PB04_I (2721) DAI Pin Buffer 4 Input

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DAI_PB03_I (2014) (cont) DAI Pin Buffer 3 Input

DAI_PB03_I (2014) DAI_PB02_I (137) DAI Pin Buffer 2 Input

DAI_PB01_I (60) DAI Pin Buffer 1 Input

Figure A-79. SRU_PIN0 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DAI_PB07_I (2014) (cont) DAI_PB08_I (2721) DAI Pin Buffer 8 Input DAI Pin Buffer 7 Input

15 14 13 12

11 10

DAI_PB07_I (2014) DAI_PB06_I (137) DAI Pin Buffer 6 Input

DAI_PB05_I (60) DAI Pin Buffer 5 Input

Figure A-80. SRU_PIN1 Register (RW)

ADSP-214xx SHARC Processor Hardware Reference

A-141

DAI Signal Routing Unit Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DAI_PB12_I (2721) DAI Pin Buffer 12 Input

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DAI_PB11_I (2014) (cont) DAI Pin Buffer 11 Input

DAI_PB11_I (2014) DAI_PB10_I (137) DAI Pin Buffer 10 Input

DAI_PB09_I (60) DAI Pin Buffer 9 Input

Figure A-81. SRU_PIN2 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DAI_PB16_I (2721) DAI Pin Buffer 16 Input

DAI_PB15_I (2014) (cont) DAI Pin Buffer 15 Input

15 14 13 12

11 10

DAI_PB15_I (2014) DAI_PB14_I (137) DAI Pin Buffer 14 Input

DAI_PB13_I (60) DAI Pin Buffer 13 Input

Figure A-82. SRU_PIN3 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DAI_PB20_I_INVERT DAI_PB19_I_INVERT DAI_PB20_I (2721) DAI Pin Buffer 20 Input

DAI_PB19_I (2014) (cont) DAI Pin Buffer 19 Input

15 14 13 12

11 10

DAI_PB19_I (2014) DAI_PB18_I (137) DAI Pin Buffer 18 Input

DAI_PB17_I (60) DAI Pin Buffer 17 Input

Figure A-83. SRU_PIN4 Register (RW)

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Group E Miscellaneous Signals

The miscellaneous signal routing registers correspond to the group E miscellaneous signals, listed in Table A-80. Source Signals Table A-80. Group E Sources Miscellaneous Signals
Selection Code 00000 (0x0) 00001 (0x1) 00010 (0x2) 00011 (0x3) 00100 (0x4) 00101 (0x5) 00110 (0x6) 00111 (0x7) 01000 (0x8) 01001 (0x9) 01010 (0xA) 01011 (0xB) 01100 (0xC) 01101 (0xD) 01110 (0xE) 01111 (0xF) 10000 (0x10) 10001 (0x11) 10010 (0x12) 10011 (0x13) Source Signal DAI_PB01_O DAI_PB02_O DAI_PB03_O DAI_PB04_O DAI_PB05_O DAI_PB06_O DAI_PB07_O DAI_PB08_O DAI_PB09_O DAI_PB10_O DAI_PB11_O DAI_PB12_O DAI_PB13_O DAI_PB14_O DAI_PB15_O DAI_PB16_O DAI_PB17_O DAI_PB18_O DAI_PB19_O DAI_PB20_O Description (Output Source Selection) Pin Buffer 1 Output Pin Buffer 2 Output Pin Buffer 3 Output Pin Buffer 4 Output Pin Buffer 5 Output Pin Buffer 6 Output Pin Buffer 7 Output Pin Buffer 8 Output Pin Buffer 9 Output Pin Buffer 10 Output Pin Buffer 11 Output Pin Buffer 12 Output Pin Buffer 13 Output Pin Buffer 14 Output Pin Buffer 15 Output Pin Buffer 16 Output Pin Buffer 17 Output Pin Buffer 18 Output Pin Buffer 19 Output Pin Buffer 20 Output

ADSP-214xx SHARC Processor Hardware Reference

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DAI Signal Routing Unit Registers

Table A-80. Group E Sources Miscellaneous Signals (Contd)

Selection Code 10100 (0x14) 10101 (0x15) 10110 (0x16) 10111 (0x17) 11000 (0x18) 11001 (0x19) 11010 (0x1A) 11011 (0x1B) 11100 (0x1C) 11101 (0x1D) 11110 (0x1E) 11111 (0x1F) Source Signal SPORT0_FS_O SPORT1_FS_O SPORT2_FS_O SPORT3_FS_O SPORT4_FS_O SPORT5_FS_O DIT_BLKSTART_O PCG_FSA_O PCG_CLKB_O PCG_FSB_O LOW HIGH Description (Output Source Selection) SPORT0 Frame Sync SPORT1 Frame Sync SPORT2 Frame Sync SPORT3 Frame Sync SPORT4 Frame Sync SPORT5 Frame Sync S/PDIF TX Block Start Output Precision Frame Sync A Precision Clock B Precision Frame Sync B Logic Level Low (0) as a Source Logic Level High (1) as a Source

A-144

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Register Reference

Destination Signal Control Registers (SRU_MISCx) Miscellaneous registers are shown in Figure A-84 and Figure A-85.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INV_MISCA5_I Invert Miscellaneous Input A5 INV_MISCA4_I Invert Miscellaneous Input A4 MISCA5_I Miscellaneous A0 Input

DAI_INT_31_I (Cont) DAI Interrupt 31 MISCA3_I (Cont) Miscellaneous A3 Input MISCA4_I Miscellaneous A4 Input

15 14 13 12

11 10

DAI_INT_31_I DAI Interrupt 31 MISCA3_I Miscellaneous A3 Input DAI_INT_30_I DAI Interrupt 30 MISCA2_I Miscellaneous A2 Input

DAI_INT_28_I DAI Interrupt 28 MISCA0_I Miscellaneous A0 Input DAI_INT_29_I DAI Interrupt 29 MISCA1_I Miscellaneous A1 Input

Figure A-84. SRU_EXT_MISCA Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DAI_INT_27_I DAI Interrupt 27 DAI_INT_26_I DAI Interrupt 26

DAI_INT_25_I DAI Interrupt 25

15 14 13 12

11 10

DAI_INT_25_I DAI Interrupt 25 DAI_INT_24_I DAI Interrupt 24 DAI_INT_22_I DAI Interrupt 22 DAI_INT_23_I DAI Interrupt 23

Figure A-85. SRU_EXT_MISCB Register (RW)

ADSP-214xx SHARC Processor Hardware Reference

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DAI Signal Routing Unit Registers

Group F DAI Pin Buffer Enable

The 6-bit source encodings are listed in Table A-81. Source Signals Table A-81. Group F Sources Pin Output Enable
Selection Code 000000 (0x0) 000001 (0x1) 000010 (0x2) 000011 (0x3) 000100 (0x4) 000101 (0x5) 000110 (0x6) 000111 (0x7) 001000 (0x8) 001001 (0x9) 001010 (0xA) 001011 (0xB) 001100 (0xC) 001101 (0xD) 001110 (0xE) 001111 (0xF) 010000 (0x10) 010001 (0x11) 010010 (0x12) 010011 (0x13) 010100 (0x14) Source Signal LOW HIGH MISCA0_O MISCA1_O MISCA2_O MISCA3_O MISCA4_O MISCA5_O SPORT0_CLK_PBEN_O SPORT0_FS_PBEN_O SPORT0_DA_PBEN_O SPORT0_DB_PBEN_O SPORT1_CLK_PBEN_O SPORT1_FS_PBEN_O SPORT1_DA_PBEN_O SPORT1_DB_PBEN_O SPORT2_CLK_PBEN_O SPORT2_FS_PBEN_O SPORT2_DA_PBEN_O SPORT2_DB_PBEN_O SPORT3_CLK_PBEN_O Description (Output Source Selection) Logic Level Low (0) Logic Level High (1) Miscellaneous Control A0 Output Miscellaneous Control A1 Output Miscellaneous Control A2 Output Miscellaneous Control A3 Output Miscellaneous Control A4 Output Miscellaneous Control A5 Output SPORT 0 Clock Output Enable SPORT 0 Frame Sync Output Enable SPORT 0 Data Channel A Output Enable SPORT 0 Data Channel B Output Enable SPORT 1 Clock Output Enable SPORT 1 Frame Sync Output Enable SPORT 1 Data Channel A Output Enable SPORT 1 Data Channel B Output Enable SPORT 2 Clock Output Enable SPORT 2 Frame Sync Output Enable SPORT 2 Data Channel A Output Enable SPORT 2 Data Channel B Output Enable SPORT 3 Clock Output Enable

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Register Reference

Table A-81. Group F Sources Pin Output Enable (Contd)

Selection Code 010101 (0x15) 010110 (0x16) 010111 (0x17) 011000 (0x18) 011001 (0x19) 011010 (0x1A) 011011 (0x1B) 011100 (0x1C) 011101 (0x1D) 011110 (0x1E) 011111 (0x1F) 100000 (0x20) 100001 (0x21) 100010 (0x22) 100011 (0x23) 100100 (0x24) 100101 (0x25) 100110 (0x26) 100111 (0x27) 101000 (0x28) 101001 (0x29) 101010 (0x2A) 101011 (0x2B) 101100 (0x2C) 101101 (0x2D) 100111 (0x2E) Source Signal SPORT3_FS_PBEN_O SPORT3_DA_PBEN_O SPORT3_DB_PBEN_O SPORT4_CLK_PBEN_O SPORT4_FS_PBEN_O SPORT4_DA_PBEN_O SPORT4_DB_PBEN_O SPORT5_CLK_PBEN_O SPORT5_FS_PBEN_O SPORT5_DA_PBEN_O SPORT5_DB_PBEN_O SPORT6_CLK_PBEN_O SPORT6_FS_PBEN_O SPORT6_DA_PBEN_O SPORT6_DB_PBEN_O SPORT7_CLK_PBEN_O SPORT7_FS_PBEN_O SPORT7_DA_PBEN_O SPORT7_DB_PBEN_O SPORT0_TDV_PBEN_O SPORT1_TDV_PBEN_O SPORT2_TDV_PBEN_O SPORT3_TDV_PBEN_O SPORT4_TDV_PBEN_O SPORT5_TDV_PBEN_O SPORT6_TDV_PBEN_O Description (Output Source Selection) SPORT 3 Frame Sync Output Enable SPORT 3 Data Channel A Output Enable SPORT 3 Data Channel B Output Enable SPORT 4 Clock Output Enable SPORT 4 Frame Sync Output Enable SPORT 4 Data Channel A Output Enable SPORT 4 Data Channel B Output Enable SPORT 5 Clock Output Enable SPORT 5 Frame Sync Output Enable SPORT 5 Data Channel A Output Enable SPORT 5 Data Channel B Output Enable SPORT 6 Clock Output Enable SPORT 6 Frame Sync Output Enable SPORT 6 Data Channel A Output Enable SPORT 6 Data Channel B Output Enable SPORT 7 Clock Output Enable SPORT 7 Frame Sync Output Enable SPORT 7 Data Channel A Output Enable SPORT 7 Data Channel B Output Enable SPORT 0 Transmit Data Valid Output SPORT 1 Transmit Data Valid Output SPORT 2 Transmit Data Valid Output SPORT 3 Transmit Data Valid Output SPORT 4 Transmit Data Valid Output SPORT 5 Transmit Data Valid Output SPORT 6 Transmit Data Valid Output

ADSP-214xx SHARC Processor Hardware Reference

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DAI Signal Routing Unit Registers

Table A-81. Group F Sources Pin Output Enable (Contd)

Selection Code 101110 (0x2F) Source Signal SPORT7_TDV_PBEN_O Description (Output Source Selection) SPORT 7 Transmit Data Valid Output Reserved

110000 (0x30)1111111 (0x3F)

Destination Signal Control Registers (SRU_PBENx) The pin buffer enable registers are shown in Figure A-86 through Figure A-89.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PBEN05_I DAI Port 5 Pin Buffer Enable Input

PBEN03_I (2318) (cont) DAI Port 3 Pin Buffer Enable Input PBEN04_I DAI Port 4 Pin Buffer Enable Input
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PBEN03_I PBEN02_I DAI Port 2 Pin Buffer Enable Input PBEN01_I DAI Port 1 Pin Buffer Enable Input

Figure A-86. SRU_PBEN0 (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PBEN10_I DAI Port 10 Pin Buffer Enable Input

PBEN08_I (2318) (cont) DAI Port 8 Pin Buffer Enable Input PBEN09_I DAI Port 9 Pin Buffer Enable Input
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PBEN08_I PBEN07_I DAI Port 7 Pin Buffer Enable Input

PBEN06_I DAI Port 6 Pin Buffer Enable Input

Figure A-87. SRU_PBEN1 (RW)

A-148

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Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

PBEN13_I PBEN15_I DAI Port 15 Pin Buffer Enable Input PBEN14_I DAI Port 14 Pin Buffer Enable Input
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PBEN13_I DAI Port 13 Pin Buffer Enable Input PBEN12_I DAI Port 12 Pin Buffer Enable Input

PBEN11_I DAI Port 11 Pin Buffer Enable Input

Figure A-88. SRU_PBEN2 (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PBEN18_I PBEN20_I DAI Port 20 Pin Buffer Enable Input PBEN19_I DAI Port 19 Pin Buffer Enable Input
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PBEN18_I DAI Port 18 Pin Buffer Enable Input PBEN17_I DAI Port 17 Pin Buffer Enable Input

PBEN16_I DAI Port 16 Pin Buffer Enable Input

Figure A-89. SRU_PBEN3 (RW)

ADSP-214xx SHARC Processor Hardware Reference

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DAI Signal Routing Unit Registers

Group H Shift Register Clock Routing (ADSP-2147x)

Table A-82 shows the list of sources for the SR_SCLK_I and SR_LAT_I input signals. Source Signals Table A-82. Group H Sources Shift Register Clock Routing
Selection Code 00000 (0x0) 00001 (0x1) 00010 (0x2) 00011 (0x3) 00100 (0x4) 00101 (0x5) 00110 (0x6) 00111 (0x7) 01000 (0x8) 01001 (0x9) 01010 (0xA) 01011 (0xB) 01100 (0xC) 01101 (0xD) 01110 (0xE) 01111 (0xF) 10000 (0x10) 10001 (0x11) 10010 (0x12) Source Signal LOW HIGH SPORT0_CLK_O SPORT1_CLK_O SPORT2_CLK_O SPORT3_CLK_O SPORT4_CLK_O SPORT5_CLK_O SPORT6_CLK_O SPORT7_CLK_O SPORT0_FS_O SPORT1_FS_O SPORT2_FS_O SPORT3_FS_O SPORT4_FS_O SPORT5_FS_O SPORT6_FS_O SPORT7_FS_O SR_SCLK_O Description (Output Source Selection) Logic Level Low (0) Logic Level High (1) SPORT 0 Clock Output SPORT 1 Clock Output SPORT 2 Clock Output SPORT 3 Clock Output SPORT 4 Clock Output SPORT 5 Clock Output SPORT 6 Clock Output SPORT 7 Clock Output SPORT 0 Frame Sync Output SPORT 1 Frame Sync Output SPORT 2 Frame Sync Output SPORT 3 Frame Sync Output SPORT 4 Frame Sync Output SPORT 5 Frame Sync Output SPORT 6 Frame Sync Output SPORT 7 Frame Sync Output Dedicated SR_SCLK Pin

A-150

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Table A-82. Group H Sources Shift Register Clock Routing (Contd)

Selection Code 10011 (0x13) 10100 (0x14) 10101 (0x15) 10110 (0x16) 10111 (0x17) 11000 (0x18) 11001 (0x19) 11010 (0x1A) 11011 (0x1B) 11100 (0x1C) 11101 (0x1D) 11110 (0x1E) 11111 (0x1F) Source Signal SR_LAT_O PCG_CLKA_O PCG_CLKB_O PCG_FSA_O PCG_FSB_O DAI_PB01_O DAI_PB02_O DAI_PB03_O DAI_PB04_O DAI_PB05_O DAI_PB06_O DAI_PB07_O DAI_PB08_O Description (Output Source Selection) Dedicated SR_LAT Pin PCG Clock A Output PCG Clock B Output PCG Frame Sync A Output PCG Frame Sync B Output Pin Buffer 1 Pin Buffer 2 Pin Buffer 3 Pin Buffer 4 Pin Buffer 5 Pin Buffer 6 Pin Buffer 7 Pin Buffer 8

Destination Control Signal Register (SR_CLK_SHREG) Figure A-90 shows the programmable options for SR_SCLK_I and SR_LAT_I input signals.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SR_LAT_I (95) Latch Input

SR_SCLK_I (40) Serial Clock Input

Figure A-90. SR_CLK_SHREG Register (RW)

ADSP-214xx SHARC Processor Hardware Reference

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DAI Signal Routing Unit Registers

Group I Shift Register Serial Data Routing Register (ADSP-2147x)

Table A-83 show the list of sources for the SR_SDI_I input signal. Source Signals Table A-83. Group I Sources Shift Register Serial Data Routing
Selection Code 00000 (0x0) 00001 (0x1) 00010 (0x2) 00011 (0x3) 00100 (0x4) 00101 (0x5) 00110 (0x6) 00111 (0x7) 01000 (0x8) 01001 (0x9) 01010 (0xA) 01011 (0xB) 01100 (0xC) 01101 (0xD) 01110 (0xE) 01111 (0xF) 10000 (0x10) 10001 (0x11) 10010 (0x12) 10011 (0x13) Source Signal LOW HIGH SPORT0_DA_O SPORT0_DB_O SPORT1_DA_O SPORT1_DB_O SPORT2_DA_O SPORT2_DB_O SPORT3_DA_O SPORT3_DB_O SPORT4_DA_O SPORT4_DB_O SPORT5_DA_O SPORT5_DB_O SPORT6_DA_O SPORT6_DB_O SPORT7_DA_O SPORT7_DB_O SR_SDAT_O DAI_PB01_O Description (Output Source Selection) Logic Level Low (0) Logic Level High (1) SPORT 0 Data Channel A SPORT 0 Data Channel B SPORT 1 Data Channel A SPORT 1 Data Channel B SPORT 2 Data Channel A SPORT 2 Data Channel B SPORT 3 Data Channel A SPORT 3 Data Channel B SPORT 4 Data Channel A SPORT 4 Data Channel B SPORT 5 Data Channel A SPORT 5 Data Channel B SPORT 6 Data Channel A SPORT 6 Data Channel B SPORT 7 Data Channel A SPORT 7 Data Channel B Dedicated SR_SDI Pin Pin Buffer 1

A-152

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Register Reference

Table A-83. Group I Sources Shift Register Serial Data Routing (Contd)
Selection Code 10100 (0x14) 10101 (0x15) 10110 (0x16) 10111 (0x17) 11000 (0x18) 11001 (0x19) 11010 (0x1A) 11011 (0x1B) 11111 (0x1F) Source Signal DAI_PB02_O DAI_PB03_O DAI_PB04_O DAI_PB05_O DAI_PB06_O DAI_PB07_O DAI_PB08_O Reserved Description (Output Source Selection) Pin Buffer 2 Pin Buffer 3 Pin Buffer 4 Pin Buffer 5 Pin Buffer 6 Pin Buffer 7 Pin Buffer 8

Destination Control Signal Register (SR_DAT_SHREG) Figure A-91 shows the programmable options for the SR_SDI_I input signal.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

SR_SDI_I (40) Serial Data Input Enable

Figure A-91. SR_DAT_SHREG Register (RW)

DAI Pin Buffer Registers (DAI_PIN_STAT)

The register shown in Figure A-92 returns the status of DAI_PB201 pin buffers. This register is updated at PCLK/2 rate.

ADSP-214xx SHARC Processor Hardware Reference

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Peripherals Routed Through the DAI

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DAI_PB20 DAI_PB19

DAI_PB17 DAI_PB18

15 14 13 12

11 10

DAI_PB16 DAI_PB15 DAI_PB14 DAI_PB13 DAI_PB12 DAI_PB11 DAI_PB10 DAI_PB09

DAI_PB01 DAI_PB02 DAI_PB03 DAI_PB04 DAI_PB05 DAI_PB06 DAI_PB07 DAI_PB08

Figure A-92. DAI_PIN_STAT Register (RO)

Peripherals Routed Through the DAI

The following sections provide information on the peripherals that are explicitly routed through the digital applications interface. For more information, see DAI Signal Routing Unit Registers on page A-123.

Serial Port Registers

The following section describes serial port (SPORT) registers. SPORT Divisor Registers (DIVx) These registers, shown in Figure A-93, allow programs to set the frame sync divisor and clock divisor.

A-154

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Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

FSDIV Frame Sync Divisor

15 14 13 12

11 10

CLKDIV Clock Divisor

Figure A-93. DIVx Register (RW) Serial Control Registers (SPCTLx) The SPCTLx registers (Figure A-94, Figure A-95 and Figure A-96 and Table A-84 on page A-158) are transmit and receive control registers for the corresponding serial ports (SPORT 0 through 7). These registers change depending on operating mode. For more information, seeOperating Modes on page 11-28 especially Table 11-9 and Table 11-10.

ADSP-214xx SHARC Processor Hardware Reference

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Peripherals Routed Through the DAI

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DXS_A (3130) Data Buffer Channel A Status DERR_A Channel A Error Status DXS_B (2827) Data Buffer Channel B Status DERR_B Channel B Error Status SPTRAN SPORT Data Direction SPEN_B SPORT Enable B BHD Buffer Hang Disable FS_BOTH Frame Sync Both

LFS Active Low Frame Sync LAFS Late Frame Sync SDEN_A DMA Channel A Enable SCHEN_A DMA Channel A Chaining Enable SDEN_B DMA Channel B Enable SCHEN_B DMA Channel B Chaining Enable

15 14 13 12

11 10

DIFS Data Independent FS IFS Internally-Generated FS FSR Frame Sync Requirement CKRE Clock Edge for Data Frame Sync Sampling OPMODE SPORT Operation Mode

SPEN_A SPORT Enable A DTYPE (21) Data Type LSBF Least Significant Bit Format SLEN (84) Serial word length1 PACK 16/32 Packing ICLK Internally Generated SPORTx_CLK

Figure A-94. SPCTLx Register for Standard Serial Mode

A-156

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Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DXS_A (3130) Data Buffer Channel A Status DERR_A Channel A Error status DXS_B (2827) Data Buffer Channel B Status DERR_B Channel B Error Status SPTRAN SPORT Data Direction BHD Buffer Hang Disable

LMFS/L_FIRST Active Low Multichannel Frame Sync Select/Channel Order First SDEN_A SPORT DMA Channel A Enable SCHEN_A SPORT DMA Channel A Chaining Enable SDEN_B SPORT DMA Channel B Enable SCHEN_B SPORT DMA Channel B Chaining Enable
11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12

IFS Internal Frame Sync Select CKRE Clock Rising Edge Select OPMODE SPORT Operation Mode ICLK Internal Clock Select

DTYPE (21) Data Type LSBF Serial Word Bit Order SLEN (84) Serial Word Length PACK 16/32 Packing

Figure A-95. SPCTLx Register Packed and Multichannel Mode

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31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DXS_A (3130) Data Buffer Channel A Status DERR_A Channel A Error Status DXS_B (2827) Data Buffer Channel B Status DERR_B Channel B Error Status SPTRAN SPORT Transaction SPEN_B SPORT Enable B BHD Buffer Hang Disable

L_FIRST Channel First Select LAFS OPMODE SDEN_A DMA Channel A Enable SCHEN_A DMA Channel A Chaining Enable SDEN_B DMA Channel B Enable SCHEN_B DMA Channel B Chaining Enable

15 14 13 12

11 10

DIFS Data Independent Frame Sync OPMODE SPORT Operation Mode MSTR I2S Serial and L/R Clock Master

SPEN_A SPORT Enable A SLEN (84) Serial Word Length 1 PACK 16/32 Packing

Figure A-96. SPCTLx Register for I2S and Left-Justified Modes Table A-84. SPCTLx Register Bit Descriptions (All Modes, RW)
Bit 0 Name SPEN_A Description Enable Channel A Serial Port. 0 = Serial port A channel disabled 1 = Serial port A channel enabled Note if the bit changes from one (=1) to zero (=0) the data buffers are automatically flushed which takes 6 core cycles. This bit gets cleared if the RW1C error bits in SPERRCTL are cleared. This bit is reserved when the SPORT is in packed or multichannel modes.

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Table A-84. SPCTLx Register Bit Descriptions (All Modes, RW) (Contd)
Bit 21 Name DTYPE Description Data Type Select. Selects the data type formatting for standard serial mode transmissions. For standard serial mode A channels, selection of companding mode and MSB format are exclusive: 00 = Right-justify, zero-fill unused MSBs 01 = Right-justify, sign-extend unused MSBs 10 = Compand using -law 11 = Compand using A-law For standard serial mode B channels: 0 = Right-justify, zero-fill unused MSBs 1 = Right-justify, sign-extend unused MSBs The transmit buffer does not zero-fill or sign-extend transmit data words; this only takes place for the receive buffer. For multichannel/packed mode A channels, selection of companding mode and MSB format are inclusive: x0 = Right-justify, zero-fill unused MSBs x1 = Right-justify, sign-extend unused MSBs 1x = Compand using -law 1x = Compand using A-law For multichannel/packed mode B channels: 0 = Right-justify, zero-fill unused MSBs 1 = Right-justify, sign-extend unused MSBs The transmit buffer does not zero-fill or sign-extend transmit data words; this only takes place for the receive buffer. For all B channels, companding is not available. This bit is reserved when the SPORT is in I2S or left-justified modes. 3 LSBF Serial Word Endian Select. 0 = Big endian (MSB first) 1 = Little endian (LSB first) This bit is internally set when the SPORT is in I2S or left-justified modes 84 SLEN Serial Word Length Select. Selects the word length in bits where the SLEN field = serial word length 1 For standard/packed and multichannel modes SLEN = 231 (3 to 32 bits) For I2S and left-justified modes SLEN = 731 (8 to 32 bits)

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Table A-84. SPCTLx Register Bit Descriptions (All Modes, RW) (Contd)
Bit 9 Name PACK Description 16-Bit to 32-Bit Word Packing Enable. When PACK = 1, two successive received words are packed into a single 32-bit word, and each 32-bit word is unpacked and transmitted as two 16-bit words. 0 = Disable 16- to 32-bit word packing 1 = Enable 16- to 32-bit word packing Internal Clock Select. 0 = Select external transmit clock. The clock signal is accepted as an input on the SPORTx_CLK_I signals and the serial clock divisors in the DIVx registers are ignored. The externally-generated serial clock does not need to be synchronous with the processors system clock. 1 = Select internal transmit clock. The SPORTx_CLK_O signals are outputs and the clock frequency is determined by the value of the serial clock divisor (CLKDIV bit) in the DIVx registers. Master Select. For I2S and left-justified mode, the MSTR bit selects the source for clock and frame sync. 0 = External clock and frame sync 1 = Internal clock and frame sync Note the externally-generated serial clock and FS does not need to be synchronous with the processors system clock. 11 OPMODE SPORT Operation Mode. 0 = DSP standard /multichannel mode 1 = I2S, packed, left-justified mode Clock Edge Select. Determines the clock signal to sample data and selects the frame sync. For sampling receive data and frame syncs: 1 = Selects the rising edge of SPORTx_CLK. 0 = The processor selects the falling edge of SPORTx_CLK for sampling receive data and frame syncs. Note that transmit data and frame sync signals change their state on the clock edge that is not selected. For example, the transmit and receive functions of any two SPORTs connected together should always select the same value for CKRE so internally-generated signals are driven on one edge and received signals are sampled on the opposite edge. This bit is internally set when the SPORT is in I2S or left-justified mode.

10

ICLK/ MSTR

12

CKRE/ Reserved

A-160

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Register Reference

Table A-84. SPCTLx Register Bit Descriptions (All Modes, RW) (Contd)
Bit 13 Name FSR/ Reserved Description Frame Sync Required Select. Selects whether the serial port requires (if set, = 1) or does not require a transfer frame sync (if cleared, = 0). This bit is internally set when the SPORT is in I2S or left-justified, multichannel or packed mode. 14 IFS/ Reserved Internal Frame Sync Select. Selects whether the serial port uses an internally generated frame sync (if set, = 1) or uses an external frame sync (if cleared, = 0). This bit is reserved when the SPORT is in I2S or left-justified mode. 15 DIFS/ Reserved Data Independent Frame Sync Select. 1 = Serial port uses a data-independent frame sync (sync at selected interval) 0 = Serial port uses a data-dependent frame sync (sync when TX FIFO is not empty or when RX FIFO is not full). This bit is internally set when the SPORT is in packed or multichannel modes. 16 LFS/L_FIRST Polarity Level Frame Sync. This bit selects the logic level of the (transmit or receive) frame sync signals for standard and multichannel modes if the FSED bit in SPCTLNx register is cleared (=0). 0 = Active high frame sync 1 = Active low frame sync Polarity Edge Frame Sync. This bit selects the logic edge of the (transmit or receive) frame sync signals for multichannel mode if the FSED bit in SPCTLNx register is set (=1). 0 = Rising edge frame sync 1 = Falling edge frame sync Channel Order First Select. Selects left/right channel first for Left-justified/(I2S/packed protocol after frame sync edge. 0 = Left channel first (left justified) 1 = Right channel first (left justified) 0 = Right channel first (I2S/packed) 1 = Left channel first ((I2S/packed)

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Table A-84. SPCTLx Register Bit Descriptions (All Modes, RW) (Contd)
Bit 17 Name Description LAFS/OPMODE Late Transmit Frame Sync Select. This bit selects when to generate the /Reserved frame sync signal. This bit selects a late frame sync if set (= 1) during the first bit of each data word. This bit selects an early frame sync if cleared (= 0) during the serial clock cycle immediately preceding the first data bit 0 = Early frame sync (FS before first bit) 1 = Late frame sync (FS during first bit) OPMODE Protocol (I2S or Left-Justified Protocol Select). 0 = I2S mode 1 = Left-justified mode This bit is reserved when the SPORT is in packed or multichannel modes. 18 SDEN_A Enable Channel A Serial Port DMA. 0 = Disable serial port channel A DMA 1 = Enable serial port channel A DMA Enable Channel A Serial Port DMA Chaining. 0 = Disable serial port channel A DMA chaining 1 = Enable serial port channel A DMA chaining SPORT DMA Enable Channel B. 0 = Disable serial port channel B DMA 1 = Enable serial port channel B DMA SPORT DMA Chaining Channel B Enable. 0 = Disable serial port channel B DMA chaining 1 = Enable serial port channel B DMA chaining FS Both Enable. If both channels (A/B) are enabled in standard serial mode: 0 = Issue FS if data is present in either transmit buffer 1 = Issue FS if data is present in both transmit buffers This bit is internally cleared when the SPORT is in packed or multichannel modes. For I2S and Left justified this bit is internally cleared for one enabled channel and set for both enabled channels.

19

SCHEN_A

20

SDEN_B

21

SCHEN_B

22

FS_BOTH/ Reserved

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Register Reference

Table A-84. SPCTLx Register Bit Descriptions (All Modes, RW) (Contd)
Bit 23 Name BHD Description Buffer Hang Disable. 0 = Causes the processor core to hang when it attempts to write to a full buffer or read from an empty buffer. 1 = Disables the core-hang and a core read from an empty receive buffer returns previously-read (invalid) data and core writes to a full transmit buffer to overwrite (valid) data that has not yet been transmitted. SPORT Channel B Enable. 0 = Serial port B channel disabled 1 = Serial port B channel enabled Note that if the bit changes from one (=1) to zero (=0) the data buffers are automatically flushed which takes 6 core cycles. This bit gets cleared if the RW1C error bits in SPERRCTL are cleared. Reserved when the SPORT is in packed or multichannel modes. 25 SPTRAN Data Transfer Direction. This bit controls the data direction of the serial port channel A and B signals. 0 = Receive on both channels A and B. The RXSPxA and RXSPxB buffers are activated, while the receive shift registers are controlled by SPORTx_CLK and SPORTx_FS. The TXSPxA and TXSPxB buffers are inactive. 1 = Transmit on both channels A and B. The TXSPxA and TXSPxB buffers are activated, while the transmit shift registers are controlled by SPORTx_CLK and SPORTx_FS. The RXSPxA and RXSPxB buffers are inactive. Channel B Error Status. This bit provides transmit underflow or receive overflow status. If FSR = 1, the DERR_x bit indicates whether the SPORTx_FS signal (from an internal or external source) occurred while the DXS_x buffer was empty or full. 0 = No SPORTx_FS signal occurred while TXSPxA/B buffer is empty/full. 1 = SPORTx_FS signal occurred while TXSPxA/B buffer is empty/full. This bit gets cleared if the RW1C error channel bit in SPERRCTL is cleared. Channel B Data Buffer Status. Indicates the status of the serial port's channel B data buffer (RXSPxB or TXSPxB) as follows: 00 = Empty 10 = Partially full 11 = Full

24

SPEN_B/ Reserved

26 (RO)

DERR_B

2827 (RO)

DXS_B

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Table A-84. SPCTLx Register Bit Descriptions (All Modes, RW) (Contd)
Bit 29 (RO) 3130 (RO) Name DERR_A DXS_A Description Channel A Error Status (sticky). Refer to DERR_B Channel A Data Buffer Status. Refer to DXS_B

SPORT Control 2 Registers (SPCTLNx) These registers (where x signifies SPORT 0 through 7) allow programs to set frame sync edge detection for I2S compatibility. These registers also allow interrupts to be generated when transmit DMA count is expired or when the last bit of last word is shifted out. that these registers do not exist Note(ADSP-212xx, ADSP-213xx). on previous SHARC processors
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

COMPANDEN Enable Companding on 1st Non-zero Active Channel DISFSCNFLCT Disable FS Underflow Error DISTUVERR Disable FS Conflict Error DISFSWERR Disable FS Error

I2SEFE I2S Extra Frame Edge ETDINTEN External Transfer Done Interrupt FSED Frame Sync Edge Detection

Figure A-97. SPCTLNx Register

A-164

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Register Reference

Table A-85. SPCTLNx Register Bit Descriptions (RW)

Bit 0 Name I2SEFE Description I2S Extra Frame Edge. If set, SPORT generates the last LRCLK if configured as I2S master (valid only for DMA). If cleared, (reset value), behaves similar to previous SHARCs. External Transfer Done Interrupt. If set, interrupt occurs only after the last bit of last word in the DMA is shifted out. If cleared, interrupt occurs when the DMA counter expires. For chain pointer DMA, if set, interrupt occurs: 1) If PCI=0 only after that last word of the last DMA block in the chain is shifted out. 2) If PCI=1, when DMA counter expires for the initial DMA blocks (CP is nonzero) in the chain and the last bit of the last word is shifted out for the last DMA block in the chain. For receive DMA, interrupt behaves in the same way independent of the bit setting. Frame Sync Edge Detection. In multichannel mode: 1 = Start transmitting/receiving only after the SPORTs detect an active edge of an external frame sync (even if the SPORTs are enabled at any instant of an active frame sync). This is done only when SPORTs are programmed for external FS mode (IFS = 0). 0 = Behaves similar to previous SHARCs (default). Disable Frame Sync Error. Serial ModeIf an external frame sync is of more than one SCLK width, a frame sync error is generated. If this bit is set, the frame sync error is generated only on an active edge of premature frame sync during valid data transmission/reception. Late Frame Sync ModeIf a frame sync is not active during the whole transmission/reception a frame sync error is generated. An error is not generated even if the frame sync is of more than one SCLK width or if it is not active throughout the transmit/receive. Disable Underflow Error. If single channel is enabled in multichannel mode, and if a premature frame sync occurs (for example: word length = 16 bits, frame sync duration 14 SCLK) during the transmission of last word in a DMA, then the TX underflow error bit is set (DERR_x bit), even though this premature frame sync does not cause any underflow and the SPORT does not try to drive data for this premature frame sync. If this bit is set, no spurious TX underflow error is generated for this premature frame sync.

ETDINTEN

FSED

DISFSWERR (Applies to ADSP-2147x, ADSP-2148x)

DISTUVERR (Applies to ADSP-2147x, ADSP-2148x)

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Table A-85. SPCTLNx Register Bit Descriptions (RW) (Contd)

Bit 5 Name DISFSCNFLCT (Applies to ADSP-2147x, ADSP-2148x) Description Disable Frame Sync Conflict Error. If single channel is enabled in multichannel mode, and if the frame sync duration is one less than the word length (example word length is 16 bits and frame sync duration is 15 SCLK cycles), then every second frame sync should be taken as an invalid frame sync and no data should be transmitted/received for that frame sync. However data is also transmitted/received for premature frame syncs. If this bit is set, no data is transmitted/received for premature frame syncs. Companding on First Active Channel Enable. If companding for any active channel is enabled in multichannel mode, and the first active channel is not the zeroth channel, and companding is enabled for the first active channel (for example channel 2), then from second frame onwards, companding for the first active channel (channel 2) does not occur. If this bit is set, companding occurs for the first active channel, even if it is not the zeroth channel. For more information, see Companding Limitations (ADSP-2146x) on page 11-25.

COMPANDEN (Applies to ADSP-2147x, ADSP-2148x)

SPORT Multichannel Control Registers (SPMCTLx) The serial ports in the ADSP-214xx processors work individually, not in pairs. Therefore, each SPORT has its own multichannel control register. These registers are shown in Figure A-98 (where x = SPORTs 0, 2, 4, and 6 and y = SPORTs 1, 3, 5, and 7) and described in Table A-86. Note that in ADSP-2136x SHARC processors there is one SPMCTLxy register for each TDM pair, therefore programs can write to one register for both SPORTs. On the ADSP-214xx SHARC processors, each sport has its own register, so only one write into both SPMCTLx registers is required to operate the SPORTs as pairs. Since there is no change in SPMCTLx register bit definitions, the same value can be written into both SPMCTLx registers in order to make legacy programs for the ADSP-2136x processors operate correctly.
SPMCTLx

A-166

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Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DMACHSyB SPORTy Channel B Status DMA Chaining Status DMACHSyA SPORTy Channel A Status DMA Chaining Status DMACHSxB SPORTx Channel B Status DMA Chaining Status DMACHSxA SPORTx Channel A Status DMA Chaining Status DMASyB SPORTy Channel B DMA Status
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHNL (2216) Current Channel Status MCEB Multichannel Enable B Channels DMASxA SPORTx Channel A DMA Status DMASxB SPORTx Channel B DMA Status DMASyA SPORTy Channel A DMA Status

SPL SPORT Loopback NCH (115) Number of Channels 1

MCEA Multichannel Enable A Channels MFD (41) Multichannel Frame Delay

Figure A-98. SPMCTLx Registers Multichannel/Packed Mode Table A-86. SPMCTLx Register Bit Descriptions (RW)
Bit 0 Name MCEA Description Multichannel Mode Enable, A Channels. Packed and multichannel A modes only. One of two configuration bits that enable and disable multichannel mode on serial port channels. See OPMODE bit (17). 0 = Disable multichannel A operation 1 = Enable multichannel A operation/packed mode. The corresponding SPEN_A bit in the SPCTL register should be cleared. If the bit transitions from high to low, the buffer (TDM/packed) is cleared which takes 6 CCLK cycles. The DERR_A bit is also cleared. Multichannel Frame Delay. The interval, in number of serial clock cycles, between the multichannel frame sync pulse and the first data bit. These bits provide support for different types of T1 interface devices. Valid values range from 0 to 15 with bits 41. Values of 1 to15 correspond to the number of intervening serial clock cycles. A value of 0 corresponds to no delay. The multichannel frame sync pulse is concurrent with first data bit.

41

MFD

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Table A-86. SPMCTLx Register Bit Descriptions (RW) (Contd)

Bit 115 Name NCH Description Number of Multichannel Slots (minus one). Select the number of channel slots (maximum of 128) to use for multichannel operation. Valid values for actual number of channel slots range from 1 to 128. Use this formula to calculate the value for NCH: NCH = Actual number of channel slots 1. SPORT Loopback Mode. Enables if set (= 1) or disables if cleared (= 0) the channel loopback mode. Loopback mode enables debug capabilities. Loopback works under the configurations show inLoopback Routing on page 10-39 where either of the two paired SPORTs can be set up to transmit or receive, depending on their SPTRAN bit setting. Only the transmitter acts as master to generate the clock and frame sync. The SPL bit applies to all non multichannel modes.

12

SPL

1513 2216 (RO) 23

Reserved CHNL MCEB Current Channel Selected. Identify the currently selected transmit channel slot (0 to 127). Multichannel B Mode Enable. Packed and multichannel B modes only. One of two configuration bits that enable and disable multichannel mode on serial port channels. See OPMODE bit (17). 0 = Disable multichannel B operation 1 = Enable multichannel B operation/packed mode the corresponding SPEN_B bit in the SPCTL register should be cleared. If the bit transitions from high to low, the buffer (TDM/packed) is cleared which takes 6 core clock cycles. The DERR_B bit is also cleared. DMAxA DMA Channel Status. 0 = Inactive 1 = Active DMAxB DMA Channel Status. 0 = Inactive 1 = Active DMAyA DMA Channel Status. 0 = Inactive 1 = Active DMAyB DMA Channel Status. 0 = Inactive 1 = Active

24 (RO)

DMASxA

25 (RO)

DMASxB

26 (RO)

DMASyA

27 (RO)

DMASyB

A-168

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Table A-86. SPMCTLx Register Bit Descriptions (RW) (Contd)

Bit 28 (RO) Name DMACHSxA Description DMAxA DMA Chaining Status. 0 = Inactive 1 = Active DMAxB DMA Chaining Status. 0 = Inactive 1 = Active DMAyA DMA Chaining Status. 0 = Inactive 1 = Active DMAyB DMA Chaining Status. 0 = Inactive 1 = Active

29 (RO)

DMACHSxB

30 (RO)

DMACHSyA

31 (RO)

DMACHSyB

SPORT Active Channel Select Registers (SPxCSy) Each bit, 310, set (=1) in one of the four SPxCS30 registers corresponds to the active channel, 1270, on a multichannel mode serial port. When these registers activate a channel (by setting the respective bits in these registers to 1, the serial port transmits or receives the word in that channels position of the data stream. When a channels bit in these registers is cleared (=0), the serial ports data transmit pin three-states during the channels transmit time slot if the serial port is configured as transmitter. If the serial port is configured as the receiver it ignores the incoming data. SPORT Compand Registers (SPxCCSy) Each bit, 310, set (=1) in one of the four SPxCCS30 registers corresponds to the active companding channel, 1270, on a multichannel mode serial port. Only SPORT0/2/4/6/A supports transmit directions and SPORT1/3/5/7/A supports receive directions. When these registers activate companding for a channel, the SPORT applies the companding from the serial ports DTYPE selection to the word transmitted or received in that channels position of the data stream. When a channels bit in these

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registers is cleared (=0), the SPORT does not compand the outgoing or incoming data during the channels time slot. Error Control Register (SPERRCTLx) The SPERRCTLx registers control and report the status of the interrupts generated by each SPORT (see Figure A-99, Table A-87).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

FSERR_STAT Frame Sync Interrupt Status DERRB_STAT Channel B Interrupt Status DERRA_STAT Channel A Interrupt Status

DERRA_EN Enable Channel A Error Detection DERRB_EN Enable Channel B Error Detection FSERR_EN Enable Frame Sync Error Detection

Figure A-99. SPERRCTLx Register Table A-87. SPERRCTLx Register Bit Descriptions (RW)
Bit 0 Name DERRA_EN Description Enable Channel A Error Detection. 0 = Disable 1 = Enable Enable Channel B Error Detection. 0 = Disable 1 = Enable Enable Frame Sync Error Detection. 0 = Disable 1 = Enable

DERRB_EN

FSERR_EN

3 4 (RW1C)

Reserved DERRA_STAT Channel A Interrupt Status. SPTRAN = 0 Receive overflow status SPTRAN = 1 Transmit underflow status

A-170

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Table A-87. SPERRCTLx Register Bit Descriptions (RW) (Contd)

Bit 5 (RW1C) Name DERRB_STAT Description Channel B Interrupt Status. SPTRAN = 0 Receive overflow status SPTRAN = 1 Transmit underflow status Frame Sync Interrupt Status. 0 = No frame sync error 1 = Frame sync error detected

6 (RW1C)

FSERR_STAT

SPORT Error Status Register (SPERRSTAT) The SPERRSTAT register combines the status of all SPORT interrupts (see Figure A-100).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SP0_FSERR SP7_FSERR SP6_FSERR SP5_FSERR SP4_FSERR SP1_FSERR SP2_FSERR SP3_FSERR

15 14 13 12

11 10

SP7_DERRB SP7_DERRA SP6_DERRB SP6_DERRA SP5_DERRB SP5_DERRA SP4_DERRB SP4_DERRA

SP0_DERRA SP0_DERRB SP1_DERRA SP1_DERRB SP2_DERRA SP2_DERRB SP3_DERRA SP3_DERRB

Figure A-100. SPERRSTAT Register (RO)

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Input Data Port Registers

The input data port (IDP) provides an additional input path to the processor core. The IDP can be configured as 8 channels of serial data or 7 channels of serial data and a single channel of up to a 20-bit wide parallel data. Input Data Port Control Register 0 (IDP_CTL0) Use this register to configure and enable the IDP and each of its channels. The register is shown in Figure A-101 and described in Table A-88.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IDP_SMODE7 (3129) Channel 7 Serial Mode Select IDP_SMODE6 (2826) Channel 6 Serial Mode Select

IDP_SMODE2 (1614) IDP_SMODE3 (1917) Channel 3 Serial Mode Select IDP_SMODE4 (2220) Channel 4 Serial Mode Select IDP_SMODE5 (2523) Channel 5 Serial Mode Select
11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12

IDP_SMODE2 (1614) Channel 2 Serial Mode Select IDP_SMODE1 (1311) Channel 1 Serial Mode Select IDP_SMODE0 (108) Channel 0 Serial Mode Select IDP_EN Global IDP Enable

IDP_NSET (30) Buffer Threshold Depth IDP_BHD Buffer Hang Disable IDP_DMA_EN Global IDP DMA Enable IDP_CLROVER Clear FIFO Overflow

Figure A-101. IDP_CTL0 Register

A-172

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Register Reference

Table A-88. IDP_CTL0 Register Bit Descriptions (RW)

Bits 30 Name IDP_NSET Description Buffer Threshold Depth. The setting of these bits represent a threshold number of entries (N) in the FIFO. When the FIFO fills to a point where it has greater (N+1) than N words (data in FIFO exceeds the value set in the IDP_NSET bit field), a DAI interrupt is latched with the IDP_FIFO_GTN_INT bit in the DAI_IRPTL_x register. Only the core can use this feature to detect when data needs to be read. The maximum IDP_NSET= 7, otherwise no interrupt is generated. IDP Buffer Hang Disable. Reads of an empty FIFO or writes to a full FIFO to cause a core hang. This condition continues until the FIFO has valid data (in the case of reads) or the FIFO has at least one empty location (in the case of writes). This can be used in debug operations. 0 = Core hang is enabled 1 = Core hang is disabled DMA Enable. Enables DMA on all IDP channels. This bit is the global control for standard and ping-pong DMA. 0 = Channel disabled 1 = Channel enabled FIFO Overflow Clear Bit. Clears the FIFO and the SRU_OVFx bits in the DAI_STAT register. Enable IDP. This bit enables the IDP. This is a global control bit. This bit needs to be set for all operations modes including DMA. When this bit transitions from high to low the buffer is flushed which takes 2 core clock cycles. Writing a 1 to bit 31 of the IDP_CTL1 register also flushes the FIFO. To enable the IDP for DMA, two separate bits in two different registers must be set. The first are the global IDP_EN and IDP_DMA_EN bits in the IDP_CTL0 register and the second are the specific channel enable bits, located in the IDP_CTL1 register.

IDP_BHD

IDP_DMA_EN

6 (RW1S) 7

IDP_CLROVR IDP_EN

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Table A-88. IDP_CTL0 Register Bit Descriptions (RW) (Contd)

Bits 108 1311 1614 1917 2220 2523 2826 3129 Name IDP_SMODE0 IDP_SMODE1 IDP_SMODE2 IDP_SMODE3 IDP_SMODE4 IDP_SMODE5 IDP_SMODE6 IDP_SMODE7 Description Serial Input Data Format Mode Select. These eight inputs (0 7), each of which contains 3 bits, indicate the mode of the serial input for each of the eight IDP channels. Input format: 000 = Left-justified 24 bits 001 = I2S mode 24 bits 010 = Left-justified 32 bits 011 = I2S 32 bits 100 = Right-justified 24 bits 101 = Right-justified 20 bits 110 = Right-justified 18 bits 111 = Right-justified 16 bits Note the SMODEx bits define the IDP buffer input format for core access. For I2S and left-justified single channel modes, it receives 32 bits of data from the SDATA pins. No L/R bit is added in these modes.

Input Data Port Control Register 1 (IDP_CTL1) Use the IDP_CTL1 register to configure and enable individual IDP channels. The register is shown in Figure A-102 and described in Table A-89.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IDP_FFCLR Clear IDP FIFO IDP_INTEN Independent Channel Synchronization Enable

IDP_PINGx (2316) IDP Channel x Ping-pong DMA Enable

15 14 13 12

11 10

IDP_DMA_ENx (158) IDP Channel x DMA Enable

IDP_ENx (70) IDP Channel x Enable

Figure A-102. IDP_CTL1 Register

A-174

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Register Reference

Table A-89. IDP_CTL1 Register Bit Descriptions (RW)

Bit 70 Name IDP_ENx Description IDP Channel x Enable. These are the enable bits for accepting data from individual channels. Corresponding IDP_ENx must be set with IDP_EN bit to get data from channel x. If IDP_EN bit is not set then this bit has no effect. 0x00 = all channels cleared 0xFF = all channels enabled (default) IDP DMA Enable. These are the DMA enable bits for individual channels. Corresponding IPD_DMA_ENx must be set with IDP_DMA_EN bit for DMA transfer of data from channel x. If the global DMA_EN bit is not set then this bit has no effect. 0x00 = all channels cleared 0xFF = all channels enabled (default) IDP Ping-Pong DMA Channel x Enable. These are the Ping-Pong DMA enable bits for individual channels. Corresponding IDP_PINGx must be set to start ping-pong DMA from channel x. This bit requires the IDP_DMA_ENx bit and IDP_DMA_EN bit are set. Independent Channel Synchronization Enable. This is the enable bit for independent channel synchronization. If this bit is set, the IDP channels will start shifting in data from the first active edge of the LRCLK based on the setting of FAEx. If this bit is cleared (reset value), then the ADSP-214xx behaves like previous SHARC processors.

158

IDP_DMA_ENx

2316

IDP_PINGx

24

IDP_INTEN

3025 31 (RW1S)

Reserved IDP_FFCLR Clear IDP FIFO. Setting this bit to 1 clears the IDP FIFO and the IDP_FIFOSZ bits. This bit can be set together with the enable bit.

ADSP-214xx SHARC Processor Hardware Reference

A-175

Peripherals Routed Through the DAI

Input Data Port Control Register 2 (IDP_CTL2) This register controls the first active edge selection for channel synchronization. The register is shown in Figure A-103 and described in Table A-90.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

FAEx (70) First Active Edge for Channel x

Figure A-103. IDP_CTL2 Register Table A-90. IDP_CTL2 Register Bit Descriptions (RW)
Bit 70 Name FAEx Description First Active Edge for Channel x. 1= nth IDP channel starts shifting in data from the first rising edge of LRCLK after IDP is enabled. This data is latched after the next falling edge of LRCLK. 0 = nth IDP channel starts shifting in data from the first falling edge of LRCLK after IDP is enabled. This data is latched after the next rising edge of LRCLK. Reset value of all these bits is 0. These bits are used only if IDP_INTEN bit (IDP_CTL1[24]) is set.

831

Reserved

Parallel Data Acquisition Port Control Register (IDP_PP_CTL) The IDP_PP_CTL register (shown in Figure A-104 and described in Table A-91) provides 20 mask bits that allow the input from any of the 20 pins to be ignored. For more information on the operation of the parallel data acquisition port, see Chapter 12, Input Data Port (SIP, PDAP). For information on the pin multiplexing that is used in conjunction with this module, see A-176 ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Pin Multiplexing on page 24-28.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IDP_PDAP_EN IDP_PDAP_RESET IDP_PDAP_CLKEDGE IDP_PDAP_PACKING (2827) IDP_PP_SELECT

IDP_P17_PDAPMASK IDP_P18_PDAPMASK IDP_P19_PDAPMASK IDP_P20_PDAPMASK

15 14 13 12

11 10

IDP_P16_PDAPMASK IDP_P15_PDAPMASK IDP_P14_PDAPMASK IDP_P13_PDAPMASK IDP_P12_PDAPMASK IDP_P11_PDAPMASK IDP_P10_PDAPMASK IDP_P09_PDAPMASK

IDP_P01_PDAPMASK IDP_P02_PDAPMASK IDP_P03_PDAPMASK IDP_P04_PDAPMASK IDP_P05_PDAPMASK IDP_P06_PDAPMASK IDP_P07_PDAPMASK IDP_P08_PDAPMASK

Figure A-104. IDP_PP_CTL Register Table A-91. IDP_PP_CTL Register Bit Descriptions (RW)
Bit 190 Name IDP_P201_ PDAPMASK Description Parallel Data Acquisition Port Mask. For each of the parallel inputs: 0 = Input data from PDAP_20-1 are masked 1 = Input data from PDAP_20-1 are unmasked After this masking process, data gets passed along to the packing unit.

2520 26

Reserved IDP_PP_ SELECT PDAP Port Select. This bit selects which peripheral is connected to the PDAP unit. 0 = Data/control bits are read from DAI pins 1 = Data/control bits are read from AMI_ADDR pins

ADSP-214xx SHARC Processor Hardware Reference

A-177

Peripherals Routed Through the DAI

Table A-91. IDP_PP_CTL Register Bit Descriptions (RW) (Contd)

Bit 2827 Name IDP_PDAP_ PACKING Description Packing. Selects PDAP packing mode. These bits mask parallel sub words from the 20 parallel input signals and packs them into a 32-bit word. The bit field indicates how data is packed. Selection of packing mode is made based on the application. 00 = 8- to 32-bit (packing by 4) 01 = (11, 11, 10) to 32-bit (packing by 3) 10 = 16- to 32-bit (packing by 2) 11 = 20- to 32-bit (no packing). 12 LSBs are cleared For input data width less than 20-bits, inputs are aligned to MSB pins. PDAP Sampling Clock Edge Select. Setting this bit (= 1) causes the data to latch on the falling edge (PDAP_CLK_I signal). Clearing this bit (= 0) causes data to latch on the rising edge (default). Notice that in all four packing modes, data is read on a clock edge, but the specific edge used (rising or falling) is not indicated. 0 = Data is latched on the rising edge 1 = Data is latched on the falling edge PDAP Reset. A reset clears any data in the packing unit waiting to get latched into the IDP FIFO. This bit resets the counter of the PDAP for packing alignment. This bit always returns a value of zero when read. PDAP Enable. 0 = Disconnects all PDAP inputs (data/control) from use as parallel input channel 1 = Connects all PDAP inputs (data/control) from use as parallel input channel. IDP channel 0 cannot be used as a serial input port with this setting

29

IDP_PDAP_ CLKEDGE

30 (RW1S) 31

IDP_PDAP_ RESET IDP_PDAP_ EN

IDP Status Register (DAI_STAT0) The IDP DMA status register shown in Figure A-105 and described in Table A-92 reflects the status of the standard and ping-pong DMA channels.

A-178

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

IDP_DMA0_STAT IDP_FIFOSZ Buffer Status IDP_DMA7_STAT IDP_DMA6_STAT IDP_DMA5_STAT IDP_DMA1_STAT IDP_DMA2_STAT IDP_DMA3_STAT IDP_DMA4_STAT DMA Active Status for IDP Channel

15 14 13 12

11 10

SRU_OVF7 SRU_OVF6 SRU_OVF5 SRU_OVF4 SRU_OVF3 SRU_OVF2 SRU_OVF1 SRU_OVF0 IDP Channel Overflow

SRU_PING0_STAT SRU_PING1_STAT SRU_PING2_STAT SRU_PING3_STAT SRU_PING4_STAT SRU_PING5_STAT SRU_PING6_STAT SRU_PING7_STAT Ping-pong DMA Channel Status

Figure A-105. DAI_STAT0 Register Table A-92. DAI_STAT0 Register Bit Descriptions (RO)
Bit 70 Name SRU_PINGx_ STAT Description Ping-Pong DMA Channel A/B Status. Indicates the status of ping-pong DMA in each respective channel (70). 0 = Ping DMA (channel A) is active 1 = Pong DMA (channel B) is active Overflow Channel Status (sticky). Provides overflow status information for each channel (bit 8 for channel 0 through bit 15 for channel 7). 0 = IDP channel input no overflow 1 = IDP channel input overflow has occurred These bits get cleared by reading the DAI_IRPTL register

158

SRU_OVFx

16

Reserved

ADSP-214xx SHARC Processor Hardware Reference

A-179

Peripherals Routed Through the DAI

Table A-92. DAI_STAT0 Register Bit Descriptions (RO) (Contd)

Bit 2417 Name Description IDP_DMAx_STAT Input Data Port DMA Channel Status. These bits reflect the state of all eight DMA channels and are set once IDP_DMA_EN is set and remain set until the last data of that channel is transferred. Even if IDP_DMA_EN is set (=1), this bit goes low once the required number of data transfers occur. Note that if DMA through some channel is not intended, this bit goes high. 0 = DMA is not active 1 = DMA is active Reserved IDP_FIFOSZ IDP FIFO Size Status. Indicates valid number of samples in the IDP FIFO. 0000 = IDP FIFO empty 1000 = IDP FIFO full

2725 3128

IDP Status Register 1 (DAI_STAT1) Since the core allows writes to the IDP_FIFO, the DAI_STAT1 register stores the different read or writes indexes with a maximum of 8 entries each. Table A-93. DAI_STAT1 Register Bit Descriptions (RO)
Bit 30 Name FIFO_WRI Description Write Index Pointer. Reflects the write index status during core writes to the IDP_FIFO. 0000 = No write done 1000 = 8 writes done Read Index Pointer. Reflects the read index status during core reads from the IDP_FIFO. 0000 = No read done 1000 = 8 reads done

74

FIFO_RDI

318

Reserved

A-180

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Asynchronous Sample Rate Converter Registers

The asynchronous sample rate converter (ASRC) is composed of five registers which are described in the following sections. Control Registers (SRCCTLx) The SRCCTLn control registers (read/write) control the operating modes, filters, and data formats used in the sample rate converter. For n = 0, the register controls the SRC0 and SRC1 modules and for n = 1 it controls the SRC2 and SRC3 modules (x = 0, 2 and y = 1, 3). The bit settings for these registers are shown in Figure A-106 and described in Table A-94.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SRCy_ENABLE SRCy Enable SRCy_MPHASE SRCy Matched Phase Mode Enable SRCy_LENOUT (2928) SRCy Output Word Length SRCy_SMODEOUT (2726) SRCy Serial Output Format SRCy_DITHER SRCy Dither Enable SRCy_SOFTMUTE SRCy Soft Mute Enable SRCx_ENABLE SRCx Enable SRCx_MPHASE SRCx Matched Phase Mode Enable SRCx_LENOUT (1312) SRCx Output Word Length SRCx_SMODEOUT (1110) SRCx Serial Output Format SRCx_DITHER SRCx Dither Enable SRCx_SOFTMUTE SRC0 Soft Mute Enable

SRCy_HARD_MUTE SRCy Hard Mute Enable SRCy_AUTO_MUTE SRCy Auto Hard Mute Enable (from SPDIF RX) SRCy_SMODEIN (2018) SRCy Serial Input Format SRCy_BYPASS SRCy Bypass Mode SRCy_DEEMPHASIS (2322) SRCy De-emphasis Filter

15 14 13 12

11 10

SRCx_HARD_MUTE SRCx Hard Mute Enable SRCx_AUTO_MUTE SRCx Auto Hard Mute Enable (from SPDIF RX) SRCx_SMODEIN (42) SRCx Serial Input Format SRCx_BYPASS SRCx Bypass Mode SRCx_DEEMPHASIS (2018) SRCx De-emphasis Filter

Figure A-106. SRCCTLx Register

ADSP-214xx SHARC Processor Hardware Reference

A-181

Peripherals Routed Through the DAI

Table A-94. SRCCTLx Register Bit Descriptions (RW)

Bit 0 1 Name SRCx_HARD_MUTE SRCx_AUTO_MUTE Description Hard Mute. Hard mutes SRC 0, 2. 1 = Mute (default) Auto Hard Mute. Auto hard mutes SRC 0, 2 when non audio is asserted by the SPDIF receiver. 0 = No mute 1 = Mute (default) Serial Input Format. Selects the serial input format for SRC 0, 2 as follows: 000 = Default, format is left-justified 001 = I2S 010 = TDM 100 = 24-bit right-justified 101 = 20-bit right-justified 110 = 18-bit right-justified 111 = 16-bit right-justified Bypass SRCx. Output of SRC 0, 2 is the same as the input. De-emphasis Filter Select. Used to de-emphasize audio data that has been emphasized. The type of de-emphasis filter is selected by the SRCx_DEEMPHASIS bits and is based on the input sample rate (SRCx_FS_IP_I signal) as follows: enables de-emphasis on incoming audio data for SRC 0, 2. 00 = No de-emphasis 01 = 32 kHz 10 = 44.1 kHz 11 = 48 kHz Soft Mute. Enables soft mute on SRC 0, 2. 0 = No mute 1 = Mute (default) Dither Enable. Enables dithering before truncation on SRC 0, 2 when a word length less than 24 bits is selected. 0 = Truncation only 1 = Dithering before truncation

24

SRCx_SMODEIN

5 67

SRCx_BYPASS SRCx_DEEMPHASIS

SRCx_SOFTMUTE

SRCx_DITHER

A-182

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-94. SRCCTLx Register Bit Descriptions (RW) (Contd)

Bit 1011 Name SRCx_SMODEOUT Description Serial Output Format. Selects the serial output format on SRC 0, 2 as follows: 00 = Left-justified 01 = I2S 10 = TDM mode 11 = Right-justified. The right-justified serial data out mode assumes 64 SCLK cycles per frame, divided evenly for left and right. For the other modes these 8 LSBs contain zeros. Output Word Length Select. Selects the serial output word length on SRC 0, 2 as follows: 00 = 24 bits 01 = 20 bits 10 = 18 bits 11 = 16 bits Any word length less than 24 bits has dither added to the unused LSBs if SRCx_DITHER is enabled (= 1). SRCx_MPHASE Match Phase Mode Select. Configures the SRC 0, 2 modules to not use their own internally-generated sample rate ratio but use an externally-generated ratio. Used with TDM data. (ADSP-21488 only) 0 = Matched phase slave disabled 1 = Matched phase slave enabled Note this setting must be cleared for the phase master. SRCx Enable. Enables SRC 0, 2. When (set = 1), or when the sample rate (frame sync) between the input and output changes, the SRC begins its initialization routine where; 1) MUTE_OUT is asserted, 2) soft mute control counter for input samples is set to maximum attenuation (144 dB). Note that SRC power-up completion is finished by clearing the SRCx_MUTEOUT bit in SRCRATx register. Writes to the SRCCTLx register should be at least one cycle before setting the SRCx_ENABLE. When setting and clearing this bit, it should be held low for a minimum of 5 PCLK cycles. Programs should disable the SRC when changing modes. Hard Mute. Hard mutes SRC 1, 3. 1 = Mute (default)

1213

SRCx_LENOUT

14

MPHASE

15

SRCx_ENABLE

16

SRCy_HARD_MUTE

ADSP-214xx SHARC Processor Hardware Reference

A-183

Peripherals Routed Through the DAI

Table A-94. SRCCTLx Register Bit Descriptions (RW) (Contd)

Bit 17 Name SRCy_AUTO_MUTE Description Auto Hard Mute. Auto hard mutes SRC 1, 3 when non audio is asserted by the SPDIF receiver. 0 = No mute 1 = Mute (default) Serial Input Format. Selects the serial input format for SRC 1, 3 as follows: 000 = Default, format is left-justified 001 = I2S 010 = TDM 100 = 24-bit right-justified 101 = 20-bit right-justified 110 = 18-bit right-justified 111 = 16-bit right-justified Bypass Mode Enable. Output of SRC 1, 3 is the same as input. De-emphasis Filter Select. Enables de-emphasis on incoming audio data for SRC 1, 3. 00 = No de-emphasis 01 = 32 kHz 10 = 44.1 kHz 11 = 48 kHz Soft Mute. Enables soft mute on SRC 1, 3. 0 = No mute 1 = Mute (default) Dither Enable. Enables dithering before truncation on SRC 0, 2 when a word length less than 24 bits is selected. 0 = Truncation only 1 = Dithering before truncation Serial Output Format. Selects the serial output format for SRC 1, 3 as follows. 00 = Left-justified 01 = I2S 10 = TDM mode 11 = Right-justified

1820

SRCy_SMODEIN

21 2223

SRCy_BYPASS SRCy_DEEMPHASIS

24

SRCy_SOFTMUTE

25

SRCy_DITHER

2627

SRCy_SMODEOUT

A-184

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-94. SRCCTLx Register Bit Descriptions (RW) (Contd)

Bit 2829 Name SRCy_LENOUT Description Output Word Length Select. Selects the serial output word length for SRC 1, 3 as follows: 00 = 24 bits 01 = 20 bits 10 = 18 bits 11 = 16 bits Any word length less than 24 bits has dither added to the unused LSBs if SRCx_DITHER is enabled (= 0). SRCy_MPHASE Match Phase Mode Select. Configures the SRC 0, 2 modules to not use their own internally-generated sample rate ratio but use an externally-generated ratio. Used with TDM data. (ADSP-21488 only) 0 = Matched phase slave disabled 1 = Matched phase slave enabled Note this setting must be cleared for the phase master. SRCy Enable. Enables SRC 1, 3. When set (= 1), or when the sample rate (frame sync) between the input and output changes, the SRC begins its initialization routine where; 1) MUTE_OUT is asserted, 2) soft mute control counter for input samples is set to maximum attenuation (144 dB). Note that SRC power-up completion is finished by clearing the SRCx_MUTEOUT bit in SRCRATx register. Writes to the SRCCTLx register should be at least one cycle before setting the SRCx_ENABLE. When setting and clearing this bit, it should be held low for a minimum of 5 PCLK cycles. Programs should disable the SRC when changing modes.

30

MPHASE

31

SRCy_ENABLE

Mute Register (SRCMUTE) This register connects an SRCx mute input and output when the SRC0_MUTE_ENx bit is cleared (=0). This allows SRCx to automatically mute input while the SRC is initializing (0 = automatic muting and 1 = manual muting). Bit 0 controls SRC0, bit 1 controls SRC1, bit 2 controls SRC2, and bit 3 controls SRC3.

ADSP-214xx SHARC Processor Hardware Reference

A-185

Peripherals Routed Through the DAI

Ratio Registers (SRCRATx) These registers report the mute and I/O sample ratio as follows: the SRCRAT0 register reports for SRC0 and SRC1 and the SRCRAT1 register reports the mute and I/O sample ratio for SRC2 and SRC3 (X = SRC0 and SRC1, Y = SRC2 and SRC3). The registers are shown in Figure A-107 and Figure A-108 and described in Table A-95.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SRC1_MUTEOUT SRC1 Mute Output Enabled

SRC1_RATIO (3016) SRC1 Ratio Bit Field

15 14 13 12

11 10

SRC0_MUTEOUT SRC0 Mute Output Enabled

SRC0_RATIO (140) SRC0 Ratio Bit Field

Figure A-107. SRCRAT0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SRC3_MUTEOUT SRC3 Mute Output Enabled

SRC3_RATIO (3016) SRC3 Ratio Bit Field

15 14 13 12

11 10

SRC2_MUTEOUT SRC2 Mute Output Enabled

SRC2_RATIO (140) SRC 2 Ratio Bit Field

Figure A-108. SRC SRCRAT1 Register

A-186

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-95. SRCRATx Register Bit Descriptions (RO)

Bit 140 Name SRCx_RATIO Description Sampling Ratio of Frame Syncs. These bits can be read to find the ratio of output to input sampling frequency (SRCx_FS_OP_I/SRCx_FS_IP_I). This ratio is reported in 4.11 (integer.fraction) format where the 15-bit value of the normal binary number is comprised of 4 bits for the integer and 11 bits for the fraction. Mute Status. The SRCx_MUTEOUT bits in SRCRATx register report the status of the MUTE_OUT signal. Once the SRCx_MUTEOUT signal is cleared, the ratio can be read. When the SRCx_ENABLE is set or there is a change in the sample ratio, the MUTE_OUT signal is asserted. The MUTE_OUT signal remains asserted until the digital servo loops internal fast settling mode is complete. When the digital servo loop has switched to slow settling mode, the MUTE_OUT signal is deasserted. Reset = 0x80008000. Sampling Ratio of Frame Syncs. See bits 140. Mute Status. See bit 15.

15

SRCx_MUTEOUT

3016 31

SRCy_RATIO SRCy_MUTEOUT

Precision Clock Generator Registers

The precision clock generator (PCG) consists of four identical units. Each of these units (A, B, C, and D) generates one clock (CLKA_O CLKB_O, CLKC_O or CLKD_O) and one frame sync (FSA_O, FSB_O, FSC_O or FSD_O) output. Control Registers (PCG_CTLxy) Two control registers (y=0, 1) operate for each unit. The control registers enable clocks, frame syncs, and select divisors for each unit. These registers are shown in Figure A-109 and Figure A-110 and described in Table A-96 and Table A-97. Note the different units (x = A, B, C, D) any clock unit can be chosen.

ADSP-214xx SHARC Processor Hardware Reference

A-187

Peripherals Routed Through the DAI

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

ENCLKx Enable Clock A/B/C/D ENFSx Enable Frame Sync A/B/C/D

FSxPHASE_HI (2920) Frame Sync A/B/C/D Phase

15 14 13 12

11 10

FSxDIV (190) Frame Sync A/B/C/D Divisor

Figure A-109. PCG_CTLx0 Registers Table A-96. PCG_CTLx0 Register Bit Descriptions (RW)
Bit 190 Name FSxDIV Description Divisor for Frame Sync A/B/C/D. This 20-bit field frame sync divider is multiplexed: FSxDIV >1 PCGx is in normal mode FSxDIV =0,1 PCGx is in bypass mode Fore more information on bypass mode, refer to the STROBEx and INVFSx bits of the PCG_PWx register. Phase for Frame Sync A/B/C/D. This field represents the upper half of the 20-bit value for the channel A/B/C/D frame sync phase. See also FSXPHASE_LO (Bits 29-20) in Table A-97. Enable Frame Sync A/B/C/D. 0 = Specified frame sync generation disabled 1 = Specified frame sync generation enabled Enable Clock A/B/C/D. 0 = Specified clock generation disabled 1 = Specified clock generation enabled

2920

FSxPHASE_HI

30

ENFSx

31

ENCLKx

A-188

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

CLKxSOURCE Clock A/B/C/D Source FSxSOURCE Frame Sync A/B/C/D Source

FSxPHASE_LO (2920) Frame Sync A/B/C/D Phase 9:0

15 14 13 12

11 10

CLKxDIV (190) CLK A/B/C/D Divisor

Figure A-110. PCG_CTLx1 Register Table A-97. PCG_CTLx1 Register Bit Descriptions (RW)
Bit 190 2920 Name CLKxDIV FSxPHASE_LO Description Divisor for Clock A/B/C/D. Phase for Frame Sync A/B/C/D. This field represents the lower half of the 20-bit value for the channel A/B/C/D frame sync phase. See also FSXPHASE_HI (Bits 29-20) in PCG_CTLx1 described on on page A-188. Frame Sync Source. Master clock source for frame sync A/B/C/D. 0 = CLKIN pin selected for specified frame sync 1 = PCG_EXTX_I selected for specified frame sync This frame sync period is also a reference for the strobe period in one shot mode. Clock Source. Master clock source for clock A/B/C/D. 0 = CLKIN pin selected for specified clock 1 = PCG_EXTx_I selected for specified clock

30

FSxSOURCE

31

CLKxSOURCE

Clock Inputs The CLKxSOURCE bit (bit 31 in the PCG_CTLx1 registers) specifies the input source for the clock of the respective units (A, B, C, and D). When this bit is cleared (= 0), the input is sourced from the external oscillator/crystal, as shown in Figure 15-1 on page 15-6. When set (= 1), the input is sourced ADSP-214xx SHARC Processor Hardware Reference A-189

Peripherals Routed Through the DAI

from DAI. The CLKxSOURCE bit is overridden if CLKx_SOURCE_IOP bit in the PCG_SYNCx register is set. If the CLKx_SOURCE_IOP bit is set, the input is sourced from the peripheral clock (PCLK). Pulse Width Registers (PCG_PWx) Pulse width is the number of input clock periods for which the frame sync output is high. Pulse width should be less than the divisor of the frame sync. The pulse width control registers are shown in Figure A-111 and Figure A-112 and described in Table A-98 and Table A-99. Note that where letters and slashes appear, for example A/B/C/D, any clock unit can be chosen. If the STROBEA/B/C/D bits of the pulse width control register (PCG_PW, PCG_PW2) is reset to 0, then the input is directly passed to the frame sync output, either not inverted or inverted, depending on the INVFSA, INVFSB, INVFSC and INVFSD bits of the PCG_PW and PCG_PW2 registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PWFSB (3116) Pulse Width Frame Sync B/D

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWFSA (150) Pulse Width Frame Sync A/C

Figure A-111. PCG_PWx Registers (in Normal Mode) Table A-98. PCG_PWx Register Bit Descriptions (in Normal Mode) (RW)
Bit 150 3116 Name PWFSA PWFSB Description Pulse Width for Frame Sync A/C. Note: This is valid when not in bypass mode Pulse Width for Frame Sync B/D. Note: This is valid when not in bypass mode

A-190

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

In bypass mode, if the least significant bit (LSB) of the PCG_PW register is set to 1, then a one-shot pulse is generated. This one-shot-pulse has a duration equal to the period of MISCA2_I for unit A, MISCA3_I for unit B, MISCA4_I for unit C, and MISCA5_I for unit D (see DAI Routing Capabilities on page 10-22). This pulse is generated either at the rising or at the falling edge of the input clock, depending on the value of the INVFSA, INVFSB, INVFSC, and INVFSD bits of the PCG_PW and PCG_PW2 registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INVFSB Active Low Frame Sync B/D

STROBEB One Shot Frame Sync B/D

15 14 13 12

11 10

INVFSA Active Low Frame Sync A/C

STROBEA One Shot Frame Sync A/C

Figure A-112. PCG_PWx Registers (in Bypass Mode) Table A-99. PCG_PWx Register Bit Descriptions (in Bypass Mode) (RW)
Bit 0 Name STROBEx Description One Shot Frame Sync A/C. Frame sync is a pulse with duration equal to one period of the MISCA2_I signal (PCG A) MISCA4_I signal (PCG C) repeating at the beginning of every frame. Note: This is valid in bypass mode only. Active Low Frame Sync Select for Frame Sync A/C. 0 = Active high frame sync 1 = Active low frame sync

INVFSx

152 16

Reserved (In bypass mode, bits 15-2 are ignored.) STROBEx One Shot Frame Sync B/D. Frame sync is a pulse with duration equal to one period of the MISCA3_I signal (PCG B) MISCA5_I signal (PCG D) repeating at the beginning of every frame. Note: This is valid in bypass mode only.

ADSP-214xx SHARC Processor Hardware Reference

A-191

Peripherals Routed Through the DAI

Table A-99. PCG_PWx Register Bit Descriptions (in Bypass Mode) (RW) (Contd)
Bit 17 Name INVFSx Description Active Low Frame Sync Select. 0 = Active high frame sync 1 = Active low frame sync

3118

Reserved (In bypass mode, bits 3118 are ignored.)

PCG Frame Synchronization Registers (PCG_SYNCx) These registers (x = 0, 1), shown in Figure A-113, and Figure A-114 and described in Table A-100 and Table A-101, allow programs to synchronize the clock frame syncs units with external frame syncs. Note the CLKxSOURCE bits (PCG_CTLx1 register) are overridden if CLKx_SOURCE_IOP bits (bit 2) in the PCG_SYNCx registers are set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FSB_SOURCE_IOP Enable FSB Input Source CLKB_SOURCE_IOP Enable Clock B Input Source

FSB_SYNC Enable Synchronization of FSB with External LRCLK CLKB_SYNC Enable Synchronization of clock B with External LRCLK

15 14 13 12

11 10

FSA_SOURCE_IOP Enable FSA Input Source CLKA_SOURCE_IOP Enable Clock A Input Source

FSA_SYNC Enable Synchronization of FSA with External LRCLK CLKA_SYNC Enable Synchronization of Clock A with External LRCLK

Figure A-113. PCG_SYNC1 Register

A-192

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-100. PCG_SYNC1 Register Bit Descriptions (RW)

Bit 0 Name FSA_SYNC Description Enable Synchronization of Frame Sync A With External Frame Sync. 0 = Frame sync disabled 1 = Frame sync enabled Enable Synchronization of Clock A With External Frame Sync. 0 = Clock disabled 1 = Clock enabled Enable Clock A Input Source. 0 = Output selected by CLKASOURCE bit 1 = PCLK (PCLK=CCLK/2 derived from core PLL) selected for clock A. Enable Frame Sync A Input Source. 0 = Output selected by FSASOURCE bit 1 = PCLK (PCLK=CCLK/2 derived from core PLL) selected for frame sync A. Enable Synchronization of Frame Sync B With External Frame Sync. 0 = Frame sync disabled 1 = Frame sync enabled Enable Synchronization of Clock B With External Frame Sync. 0 = Clock disabled 1 = Clock enabled EnabLe Clock B Input Source. 0 = Output selected by CLKBSOURCE bit 1 = PCLK (PCLK=CCLK/2 derived from core PLL) selected for clock B. Enable Frame Sync B Input Source. 0 = Output selected by FSBSOURCE bit 1 = PCLK (PCLK=CCLK/2 derived from core PLL) selected for frame sync B.

CLKA_SYNC

CLKA_SOURCE_IOP

FSA_SOURCE_IOP

16

FSB_SYNC

17

CLKB_SYNC

18

CLKB_SOURCE_IOP

19

FSB_SOURCE_IOP

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A-193

Peripherals Routed Through the DAI

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

FSD_SOURCE_IOP Enable Frame Sync D Input Source CLKD_SOURCE_IOP Enable Clock D Input Source

FSD_SYNC Enable Synchronization of FSD with External LRCLK CLKD_SYNC Enable Synchronization of Clock D with External LRCLK

15 14 13 12

11 10

FSC_SOURCE_IOP Enable Frame Sync C Input Source CLKC_SOURCE_IOP Enable Clock C Input Source

FSC_SYNC Enable Synchronization of FSC with External LRCLK CLKC_SYNC Enable Synchronization of Clock C with External LRCLK

Figure A-114. PCG_SYNC2 Register Table A-101. PCG_SYNC2 Register Bit Descriptions (RW)
Bit 0 Name FSC_SYNC Description Enable Synchronization of Frame Sync C With External Frame Sync. 0 = Frame sync disabled 1 = Frame sync enabled Enable Synchronization of Clock C With External Frame Sync. 0 = Clock disabled 1 = Clock enabled Enable Clock C Input Source. 0 = Output selected by CLKCSOURCE bit 1 = PCLK selected for clock C Enable Frame Sync C Input Source. 0 = Output selected by FSCSOURCE bit 1 = PCLK selected for frame sync C Enable Synchronization of Frame Sync D With External Frame Sync. 0 = Frame sync disabled 1 = Frame sync enabled

CLKC_SYNC

CLKC_SOURCE_IOP

FSC_SOURCE_IOP

16

FSD_SYNC

A-194

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-101. PCG_SYNC2 Register Bit Descriptions (RW) (Contd)

Bit 17 Name CLKD_SYNC Description Enable Synchronization of Clock D With External Frame Sync. 0 = Clock disabled 1 = Clock enabled Enable Clock D Input Source. 0 = Output selected by CLKDSOURCE bit 1 = PCLK selected for clock D Enable Frame Sync D Input Source. 0 = Output selected by FSDSOURCE bit 1 = PCLK selected for frame sync D

18

CLKD_SOURCE_IOP

19

FSD_SOURCE_IOP

Sony/Philips Digital Interface Registers

The following sections describe the registers that are used to configure, enable, and report status information for the S/PDIF transceiver. Transmitter Registers The following sections describe the S/PDIF transmitter registers.
Transmit Control Register (DITCTL)

This 32-bit registers bits are shown in Figure A-115 and described in Table A-102.

ADSP-214xx SHARC Processor Hardware Reference

A-195

Peripherals Routed Through the DAI

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DIT_B0CHANR (3124) Channel Status Byte 0 for Subframe B

DIT_B0CHANL (2316) Channel Status Byte 0 for Subframe A

11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12

EXT_SYNC_EN External Sync Enable DIT_USRPEND Status Bit DIT_BLKSTART Block Start DIT_VALIDR Validity Bit B DIT_VALIDL Validity Bit A DIT_AUTO Automatically Block Start

DIT_EN Transmitter Enable DIT_MUTE Mute Serial Data Output DIT_FREQ (32) Oversampling ratio DIT_SCDF Single Channel Double Frequency Mode Enable DIT_SCDF_LR Select SCDF Channel DIT_SMODE_IN (86) Serial Data Input Format

Figure A-115. DITCTL Register Table A-102. DITCTL Register Bit Descriptions (RW)
Bit 0 Name DIT_EN Description Transmitter Enable. Enables the transmitter and resets the control registers to their defaults. 0 = Transmitter disabled 1 = Transmitter enabled Mute. Mutes the serial data output. Frequency Multiplier. Sets the over sampling ratio to the following: 00 = 256 frame sync 01 = 384 frame sync Single-Channel, Double-Frequency Mode Enable. 0 = 2 channel mode 1 = SCDF mode Select Single-Channel, Double-Frequency Mode. 0 = Left channel 1 = Right channel

1 32

DIT_MUTE DIT_FREQ

DIT_SCDF

DIT_SCDF_LR

A-196

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-102. DITCTL Register Bit Descriptions (RW) (Contd)

Bit 86 Name DIT_SMODEIN Description Serial Data Input Format. Selects the input format as follows: 000 = Left-justified 001 = I2S 010 = Reserved 011 = Reserved 100 = Right-justified, 24-bits 101 = Right-justified, 20-bits 110 = Right-justified, 18-bits 111 = Right-justified, 16-bits Automatically Generate Block Start. Automatically generate block start. When enabled, the transmitter is in standalone mode where it inserts block start, channel status, and validity bits on its own. If the channel status or validity buffer needs to be enabled (after the SRU programming is complete), first write to the buffers with the required data and then enable the buffers by setting the DIT_AUTO bit. 0 = Manually start block transfer according to input stream status bits 1 = Automatically start block transfer. Validity Bit A. Use with channel status buffer. Validity Bit B. Use with channel status buffer. Block Start. Status bit that indicates block start (when bit 9, DIT_AUTO = 1). 0 = Current word is not block start 1 = Current word is block start User Bits Pending. This bit is set if the update of the internal buffer from the DITUSRBITA/Bx registers has not completed yet.

DIT_AUTO

10 11 12 (RO)

DIT_VALIDL DIT_VALIDR DIT_BLKSTART

13 (RO)

DIT_USRPEND

14 15

Reserved EXT_SYNC_EN External Sync Enable. When set (Regardless of bit 9) the internal frame counter is set to zero at an internal LRCLK rising edge followed by an DIT_EXTSYNC_I rising edge. Channel Status Byte 0 for Subframe A. Channel Status Byte 0 for Subframe B.

2316 3124

DIT_B0CHANL DIT_B0CHANR

ADSP-214xx SHARC Processor Hardware Reference

A-197

Peripherals Routed Through the DAI

Transmit Status Bit Registers for Subframe A/B (DITCHANAx/Bx)

These registers provide status information for transmitter subframe A and B. The first five bytes of the channel status may be written all at once to the control registers for both A and B channels. As the data is serialized and transmitted, the appropriate bit is inserted into the channel status area of the 192-word frame. Note that these registers are used in standalone mode only. There are six channel status registers associated with subframe A (left channel) and six user bits buffer registers associated with subframe B (right channel). Since a block owns 2 x 192 frames, 24 bytes per frame are required for storage. Note that status byte 0 is available in the DITCTL register. These registers are listed with their locations in Table A-103 and Table A-104. Table A-103. DITCHANAx Registers (RW)
Register DITCTL DITCHANA0 DITCHANA1 DITCHANA2 DITCHANA3 DITCHANA4 DITCHANA5 BYTE1 BYTE5 BYTE9 BYTE13 BYTE17 BYTE21 BYTE2 BYTE6 BYTE10 BYTE14 BYTE18 BYTE22 Bits 70 Bits 158 Bits 2316 BYTE0 BYTE3 BYTE7 BYTE11 BYTE15 BYTE19 BYTE23 BYTE4 BYTE8 BYTE12 BYTE16 BYTE20 Reserved Bits 3124

Table A-104. DITCHANBx Registers (RW)

Register DITCTL DITCHANB0 DITCHANB1 BYTE1 BYTE5 BYTE2 BYTE6 BYTE3 BYTE7 Bits 70 Bits 158 Bits 2316 Bits 3124 BYTE0 BYTE4 BYTE8

A-198

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Register Reference

Table A-104. DITCHANBx Registers (RW) (Contd)

Register DITCHANB2 DITCHANB3 DITCHANB4 DITCHANB5 Bits 70 BYTE9 BYTE13 BYTE17 BYTE21 Bits 158 BYTE10 BYTE14 BYTE18 BYTE22 Bits 2316 BYTE11 BYTE15 BYTE19 BYTE23 Bits 3124 BYTE12 BYTE16 BYTE20 Reserved

Transmit User Bits Buffer Registers for Subframe A/B Registers (DITUSRBITAx/Bx)

Once programmed, these registers are used only for the next block of data. This allows programs to change the user bit information with every block of data. After writing to the appropriate registers to change the user bits for the next block, DITUSRBITAx and DITUSRBITBx must be written to enable the use of these bits. Note these registers are used in standalone mode only. There are six user bits buffer registers associated with subframe A (left channel) and six user bits buffer registers associated with subframe B (right channel). These registers are listed with their locations in Table A-105 and Table A-106. Table A-105. DITUSRBITAx Registers (RW)
Register DITUSRBITA0 DITUSRBITA1 DITUSRBITA2 DITUSRBITA3 DITUSRBITA4 DITUSRBITA5 Bits 70 BYTE0 BYTE4 BYTE8 BYTE12 BYTE16 BYTE20 Bits 158 BYTE1 BYTE5 BYTE9 BYTE13 BYTE17 BYTE21 Bits 2316 BYTE2 BYTE6 BYTE10 BYTE14 BYTE18 BYTE22 Bits 3124 BYTE3 BYTE7 BYTE11 BYTE15 BYTE19 BYTE23

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Peripherals Routed Through the DAI

Table A-106. DITUSRBITBx Registers (RW)

Register DITUSRBITB0 DITUSRBITB1 DITUSRBITB2 DITUSRBITB3 DITUSRBITB4 DITUSRBITB5 Bits 70 BYTE0 BYTE4 BYTE8 BYTE12 BYTE16 BYTE20 Bits 158 BYTE1 BYTE5 BYTE9 BYTE13 BYTE17 BYTE21 Bits 2316 BYTE2 BYTE6 BYTE10 BYTE14 BYTE18 BYTE22 Bits 3124 BYTE3 BYTE7 BYTE11 BYTE15 BYTE19 BYTE23

User Bit Update Register (DITUSRUPD)

This register is a 1-bit wide register (RW). After writing to the user bits registers (DITURSBITAx and DITUSRBITBx), a value of 0x1 must be written into DITUSRUPD register to enable the use of these bits in the next block of transfer. Receiver Registers The following sections describe the receiver registers.
Receive Control Register (DIRCTL)

This 32-bit register, described in Table A-107 is used to set up error control and single-channel double-frequency mode.

A-200

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

15 14 13 12

11 10

DIR_DTS_CD_4K_EN DTS_CD 4096 Frames Support Enable DIR_RESET Soft Reset DIR_PLLDIS Disable PLL DIR_MUTE Mute

DIR_BIPHASE (10) Parity Biphase Error Control DIR_LOCK_ERR (32) Lock Error Control DIR_SCDF_LR Single Channel Double Frequency Mode Enable DIR_SCDF Single-Channel, Double-Frequency Mode Enable

Figure A-116. DIRCTL Register Table A-107. DIRCTL Register Bit Descriptions (RW)
Bit 10 Name DIR_BIPHASE Description Parity Biphase Error Control. When a parity or biphase error occurs, the audio data will be handled according to these bits. 00 = No action taken 01 = Hold last valid sample 10 = Replace invalid sample with zeros 11 = Reserved Lock Error Control. When the DIR_LOCK bit in the DIRSTAT register is deasserted, it means the PLL has become unlocked and the audio data is handled according to these bit settings. 00 = No action taken 01 = Hold last valid sample 10 = Send zeros after the last valid sample 11 = Soft mute of the last valid audio is performed (as if NOSTREAM is asserted). This is valid only when linear PCM audio data is in the stream. When non-linear audio data is in the stream, this mode defaults to the case of DIR_LOCK_ERR10 bits = 10. Single-Channel, Double-Frequency Channel Select. 0 = Left channel 1 = Right channel

32

DIR_LOCK_ERR

DIR_SCDF_LR

ADSP-214xx SHARC Processor Hardware Reference

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Peripherals Routed Through the DAI

Table A-107. DIRCTL Register Bit Descriptions (RW) (Contd)

Bit 5 Name DIR_SCDF Description Single-Channel, Double-Frequency Mode Enable. 0 = 2 channel mode enabled 1 = SCDF mode Mute. 0 = Mute disabled 1 = Mute serial data outputs, maintaining clocks (digital black)

DIR_MUTE

87 9

Reserved DIR_RESET Reset S/PDIF Receiver. By default, the S/PDIF receiver is always enabled. If this bit is set, the S/PDIF receiver and digital PLL are disabled.

10 11

Reserved DIR_DTS_CD_ 4K_EN DTS_CD 4096 Frames Support Enable. If this bit is set, and if NON-AUDIO preamble is detected, then the DIR_NOAUDIOLR bit is asserted high and remains high if another NON AUDIO preamble is detected within 4096 frames, otherwise it is cleared. The assertion and deassertion of DIR_NOAUDIO bit can generate the DIR_NOAUDIO_INT DAI interrupt, if unmasked in the DAI_IRPTL_FE/DAI_IRPTL_RE interrupt mask registers. This bit is supported with on-chip Digital PLL only. This bit is applicable only for the ADSP-2147x and ADSP-2148x processors.

3112

Reserved

Receive Status Register (DIRSTAT)

The Status register consists of status bits (VALIDITY, NONAUDIO, NOSTREAM, BIPHERR, PARITYERR and LOCK), indicate the status of various functions supported by S/PDIF Receiver. It also has the lower byte of the 40-bit channel status information. The VALIDITY, NOSTREAM, BIPHERR, PARITYERR and LOCK bits are sticky and cleared on read. This register also contains the lower byte of the 40-bit channel status information. The bit settings for these registers are shown in Figure A-117 and described in Table A-108.

A-202

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DIR_B0CHANR (3124) Channel Status Byte 0 for Subframe B

DIR_B0CHANL (2316) Channel Status Byte 0 for Subframe A

15 14 13 12

11 10

DIR_BIPHASEERROR Biphase Error DIR_PARITYERROR Parity bit. Indicates parity error DIR_NOSTREAM Stream Disconnected DIR_LOCK Lock Receiver

DIR_NOAUDIOL Non-Audio Subframe Mode Channel 1 DIR_NOAUDIOR Non-Audio Subframe Mode Channel 2 DIR_NOAUDIOLR Non-Audio Subframe Mode Channel 1 and 2 DIR_VALID Validity Bit. ORed value of channel 1 and 2

Figure A-117. DIRSTAT Register Table A-108. DIRSTAT Register Bit Descriptions (RO)
Bit 0 Name DIR_NOAUDIOL Description Non-Audio Subframe Mode Channel 1. Based on SMPTE 337M. 0 = Not non-audio subframe mode 1 = Non-audio subframe mode, channel 1 Non-Audio Subframe Mode Channel 2. Based on SMPTE 337M. 0 = Not non-audio subframe mode 1 = Non-audio subframe mode, channel 2 Non-Audio Frame Mode Channel 1 and 2. Based on SMPTE 337M. 0 = Not non-audio frame mode 1 = Non-audio frame mode Validity Bit (sticky). ORed bits of channel 1 and 2. 0 = Linear PCM data 1 = Non-linear audio data

DIR_NOAUDIOR

DIR_NOAUDIOLR

3 (ROC)

DIR_VALID

ADSP-214xx SHARC Processor Hardware Reference

A-203

Peripherals Routed Through the DAI

Table A-108. DIRSTAT Register Bit Descriptions (RO) (Contd)

Bit 4 (ROC) Name DIR_LOCK Description Lock Receiver (sticky). When set (=1), the digital PLL of receiver is locked, the corresponding DIR_LOCK bit is set. This bit can be polled to detect the DIR_LOCK condition. After the receiver is locked, the other status bits in DIRSTAT and the channel status (DIRCHANL/R) registers can be read. Interrupts can be also used with some status bits. 0 = Receiver not locked 1 = Receiver locked No Stream Error (sticky). Asserted when the AES3/SPDIF stream is disconnected. When this bit is asserted and the audio data in the stream is linear PCM, the receiver performs a soft mute of the last valid sample from the AES3/SPDIF stream. A soft mute consists of taking the last valid audio sample and slowly and linearly decrementing it to zero, over a period of 4096 frames. During this time, the PLL three-states the charge pump until the soft mute has been completed. If non-linear PCM audio data is in the AES3/SPDIF stream when the NOSTREAM bit is asserted, the receiver sends out zeros after the last valid sample. 0 = Stream not disconnected 1 = Stream disconnected (default) Parity Bit (sticky). When cleared, (=0), indicates that the AES3/SPDIF stream was received with the correct parity, or even parity. When set (=1), indicates that an error has occurred, and the parity is odd. 0 = No parity error 1 = Parity error Biphase Error (sticky). When set (=1), indicates that a bi-phase error has occurred and the data sampled from the biphase stream may not be correct. 0 = No biphase error 1 = Biphase error

5 (ROC)

DIR_NOSTREAM

6 (ROC)

DIR_PARITYERROR

7 (ROC)

DIR_BIPHASEERROR

158 2316 3124

Reserved DIR_B0CHANL DIR_B0CHANR Channel Status Byte 0 for Subframe A. Channel Status Byte 0 for Subframe B.

A-204

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Receive Status Registers for Subframe A (DIRCHANA)

The S/PDIF receiver stores a maximum of 5 bytes (40-bit) status information. Note that status byte 0 is available in the DIRCTL register. This 32-bit register is described in Table A-109. Table A-109. DIRCHANAx Registers (RO)
Register DIRSTAT DIRCHANA BYTE1 BYTE2 Bits 70 Bits 158 Bits 2316 BYTE0 BYTE3 BYTE4 Bits 3124

Receive Status Registers for Subframe B (DIRCHANB)

The S/PDIF receiver stores a maximum of 5 bytes (40-bit) status information. Note that status byte 0 is available in the DIRCTL register. This 32-bit register is described in Table A-110. Table A-110. DIRCHANBx Registers (RO)
Register DIRSTAT DIRCHANB BYTE1 BYTE2 BYTE3 Bits 70 Bits 158 Bits 2316 Bits 3124 BYTE0 BYTE4

ADSP-214xx SHARC Processor Hardware Reference

A-205

Peripherals Routed Through the DAI

Shift Register Control Register

The following section provides bit information for the shift register module. Control Register (SR_CTL) This register, shown in Figure A-118 and described in Table A-111, enables the peripheral.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

SR_SDO_SEL (62) Serial Data Out Select Input

SR_LDOE Parallel Data Output Enable SR_SW_CLR Software Clear/Reset

Figure A-118. SR_CTL Register Table A-111. SR_CTL Register Bit Descriptions (RW)
Bit 0 Name SR_LDOE Description Parallel Data Output Enable. This bit enables the parallel SR_LD0170 output pins. It is cleared on chip reset (RESET) and/or asynchronously on dedicated SR_CLR pin. Software Clear/Reset. If this bit is 0, then the reset is active. 0 = Shift register cleared 1 = Shift register enabled Serial Data Out Multiplexers Select Input. These bits select which parallel word is shifted through the SR_SDO pin. 00000 = LSB selected. 10001 = MSB selected.

SR_SW_CLR

62

SR_SDO_SEL

317

Reserved

A-206

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

DPI Signal Routing Unit Registers

The digital peripheral interface is comprised of a group of peripherals and the signal routing unit 2 (SRU2).

Group A Miscellaneous Signals

The registers and input signals for group A are summarized in Figure A-119 through Figure A-124 and Table A-112. Source Signals Table A-112. Group A Connections
Selection Code 00000 (0x0) 00001 (0x1) 00010 (0x2) 00011 (0x3) 00100 (0x4) 00101 (0x5) 00110 (0x6) 00111 (0x7) 01000 (0x8) 01001 (0x9) 01010 (0xA) 01011 (0xB) 01100 (0xC) 01101 (0xD) 01110 (0xE) 01111 (0xF) Signal LOW HIGH DPI_PB01_O DPI_PB02_O DPI_PB03_O DPI_PB04_O DPI_PB05_O DPI_PB06_O DPI_PB07_O DPI_PB08_O DPI_PB09_O DPI_PB10_O DPI_PB11_O DPI_PB12_O DPI_PB13_O DPI_PB14_O Description (Source Selection) Logic Level Low (0) Logic Level High (1) External Pin 1 External Pin 2 External Pin 3 External Pin 4 External Pin 5 External Pin 6 External Pin 7 External Pin 8 External Pin 9 External Pin 10 External Pin 11 External Pin 12 External Pin 13 External Pin 14

ADSP-214xx SHARC Processor Hardware Reference

A-207

DPI Signal Routing Unit Registers

Table A-112. Group A Connections (Contd)

Selection Code 10000 (0x10) 10001 (0x11) 10010 (0x12) 10011 (0x13) 10100 (0x14) 10101-11111 Signal TIMER0_O TIMER1_O Reserved UART0_TX_O Reserved Reserved UART0 Transmitter Output Description (Source Selection) Timer0 Output Timer1 Output

Destination Control Signal Registers (SRU2_INPUTx)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPIB_MISO_I (2925) SPI B MISO Input

SPI_CLK_I (1915) cont SPI Clock Input SPIB_MOSI_I (2420) SPI B MOSI Input

15 14 13 12

11 10

SPI_CLK_I (1915) SPI Clock Input SPI_DS_I (1411) SPI Device Select Input

SPI_MOSI_I (40) SPI MOSI Input SPI_MISO_I (95) SPI MISO Input

Figure A-119. SRU2_INPUT0 Register (RW)

A-208

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

TWI_CLK_I (2925) TWI Serial Clock Input

TWI_DATA_I (2420) TWI Serial Data Input

15 14 13 12

11 10

SPIB_DS_I (40) UART0_RX_I (1411) UART 0 Receiver Input SPIB Device Select Input SPIB_CLK_I (95) SPI B Clock Input

Figure A-120. SRU2_INPUT1 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FLAG6_I (2925) Flag 6 Input

FLAG4_I (1915) cont Flag 4 Input FLAG5_I (2420) Flag 5 Input

15 14 13 12

11 10

FLAG4_I (1410) Flag 4 Input

TIMER0_I (40) Timer 0 Input TIMER1_I (95) Timer 1 Input

Figure A-121. SRU2_INPUT2 Register (RW)

ADSP-214xx SHARC Processor Hardware Reference

A-209

DPI Signal Routing Unit Registers

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

FLAG12_I (2925) Flag 12 Input

FLAG10_I (1915) cont Flag 10 Input FLAG11_I (2420) Flag 11 Input

15 14 13 12

11 10

FLAG10_I (1915) Flag 10 Input FLAG9_I (1410) Flag 9 Input

FLAG7_I (40) Flag 7 Input FLAG8_I (95) Flag 8 Input

Figure A-122. SRU2_INPUT3 Register (RW)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MISCB2_I (2925) Miscellaneous B2 Input MISCB1_I (2420) Miscellaneous B1 Input

MISCB0_I (1915) Miscellaneous B0 Input

15 14 13 12

11 10

MISCB0_I (1915) FLAG15_I (1410) Flag 15 Input

FLAG13_I (40) Flag 13 Input FLAG14_I (95) Flag 14 Input

Figure A-123. SRU2_INPUT4 Register (RW)

A-210

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

MISCB8_I (2925) Miscellaneous B8 Input

MISCB6_I (1915) Miscellaneous B6 Input MISCB7_I (2420) Miscellaneous B7 Input

15 14 13 12

11 10

MISCB6_I (1915) MISCB5_I (1410) Miscellaneous B5 Input

MISCB3_I (40) Miscellaneous B3 Input MISCB4_I (95) Miscellaneous B4 Input

Figure A-124. SRU2_INPUT5 Register (RW)

Group B Pin Assignment Signal

Group B connections, shown in Figure A-125 through Figure A-127 and Table A-113, are used to route output signals to the 14 DPI pins. ADSP-2147x and ADSP-2148x processors, For theunits 31 can be routed to the DPI pins. See the outputs of PWM locations 0x23 0x2E in Table A-113. Source Signals Table A-113. Group B Signals
Binary 000000 (0x0) 000001 (0x1) 000010 (0x2) 000011 (0x3) 000100 (0x4) 000101 (0x5) Signal LOW HIGH DPI_PB01_O DPI_PB02_O DPI_PB03_O DPI_PB04_O Description (Source Selection) Logic Level Low (0) Logic Level High (1) External Pin 1 External Pin 2 External Pin 3 External Pin 4

ADSP-214xx SHARC Processor Hardware Reference

A-211

DPI Signal Routing Unit Registers

Table A-113. Group B Signals (Contd)

Binary 000110 (0x6) 000111 (0x7) 001000 (0x8) 001001 (0x9) 001010 (0xA) 001011 (0xB) 001100 (0xC) 001101 (0xD) 001110 (0xE) 001111 (0xF) 010000 (0x10) 010001 (0x11) 010010 (0x12) 010011 (0x13) 010100 (0x14) 010101 (0x15) 010110 (0x16) 010111 (0x17) 011000 (0x18) 011001 (0x19) 011010 (0x1A) 011011 (0x1B) 011100 (0x1C) 011101 (0x1D) 011110 (0x1E) 011111 (0x1F) Signal DPI_PB05_O DPI_PB06_O DPI_PB07_O DPI_PB08_O DPI_PB09_O DPI_PB10_O DPI_PB11_O DPI_PB12_O DPI_PB13_O DPI_PB14_O TIMER0_O TIMER1_O Reserved UART0_TX_O Reserved SPI_MISO_O SPI_MOSI_O SPI_CLK_O SPI_FLG0_O SPI_FLG1_O SPI_FLG2_O SPI_FLG3_O SPIB_MISO_O SPIB_MOSI_O SPIB_CLK_O SPIB_FLG0_O MISO from SPI MOSI from SPI Clock Output from SPI Slave Select 0 from SPI Slave Select 1 from SPI Slave Select 2 from SPI Slave Select 3 from SPI MISO from SPIB MOSI from SPIB Clock Output from SPIB Slave Select 0 from SPIB UART0 Transmitter Output Description (Source Selection) External Pin 5 External Pin 6 External Pin 7 External Pin 8 External Pin 9 External Pin 10 External Pin 11 External Pin 12 External Pin 13 External Pin 14 Timer0 Output Timer1 Output

A-212

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-113. Group B Signals (Contd)

Binary 100000 (0x20) 100001 (0x21) 100010 (0x22) 100011 (0x23) 100100 (0x24) 100101 (0x25) 100110 (0x26) 100111 (0x27) 101000 (0x28) 101001 (0x29) 101010 (0x2A) 101011 (0x2B) 101100 (0x2C) 101101 (0x2D) 101110 (0x2E) 101111 (0x2F) 110000 (0x30) 110001 (0x31) 110010 (0x32) Signal SPIB_FLG1_O SPIB_FLG2_O SPIB_FLG3_O FLAG4_O FLAG5_O FLAG6_O FLAG7_O FLAG8_O FLAG9_O FLAG10_O FLAG11_O FLAG12_O FLAG13_O FLAG14_O FLAG15_O PCG_CLKC_O PCG_CLKD_O PCG_FSC_O PCG_FSD_O Description (Source Selection) Slave Select 1 from SPIB Slave Select 2 from SPIB Slave Select 3 from SPIB Flag/PWM 4 Output1 Flag/PWM 5 Output Flag/PWM 6 Output Flag/PWM 7 Output Flag/PWM 8 Output Flag/PWM 9 Output Flag/PWM 10 Output Flag/PWM 11 Output Flag/PWM 12 Output Flag/PWM 13 Output Flag/PWM 14 Output Flag/PWM 15 Output Precision Clock Generator Clock C Out Precision Clock Generator Clock D Out Precision Clock Generator Frame Sync C Out Precision Clock Generator Frame Sync D Out

110011111111 Reserved 1 PWM not available on ADSP-2146x models.

ADSP-214xx SHARC Processor Hardware Reference

A-213

DPI Signal Routing Unit Registers

Destination Signal Control Registers (SRU2_PINx)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DPI_PB05_I (2924) DPI pin buffer 5 Input

DPI_PB03_I (1712) cont DPI Pin Buffer 3 Input DPI_PB04_I (2318) DPI Pin Buffer 4 Input

15 14 13 12

11 10

DPI_PB03_I (1712) DPI Pin Buffer 3 Input DPI_PB02_I (116) DPI Pin Buffer2 Input DPI_PB01_I (50) DPI Pin Buffer 1 Input

Figure A-125. SRU2_PIN0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DPI_PB10_I (2924) DPI Pin Buffer 10 Input

DPI_PB08_I (1712) cont DPI Pin Buffer 8 Input DPI_PB09_I (2318) DPI Pin Buffer 9 Input

15 14 13 12

11 10

DPI_PB08_I (1712) DPI Pin Buffer 8 Input DPI_PB07_I (116) DPI Pin Buffer 7 Input DPI_PB06_I (50) DPI Pin Buffer 6 Input

Figure A-126. SRU2_PIN1 Register

A-214

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

DPI_PB14_I (2318) DPI Pin Buffer 14 Input

DPI_PB13_I (1712) cont DPI Pin Buffer 13 Input

15 14 13 12

11 10

DPI_PB13_I (1712) DPI Pin Buffer 13 Input DPI_PB12_I (116) DPI Pin Buffer 12 Input DPI_PB11_I (50) DPI Pin Buffer 11 Input

Figure A-127. SRU2_PIN2 Register

Group C Pin Enable

Group C signals, shown in Table A-114, are used to specify whether each DPI pin is used as an output or an input by setting the source for the pin buffer enable. When a pin buffer enable (DPI_PBENxx_I) is set (= 1), the signal present at the corresponding pin buffer input (DPI_PBxx_I) is driven off chip as an output. When a pin buffer enable is cleared (= 0), the signal present at the corresponding pin buffer input is ignored. The pin enable control registers activate the drive buffer for each of the 14 DPI pins. When the pins are not enabled (driven), they can be used as inputs. The registers that control group C settings are shown in Figure A-128 through Figure A-130. as output, the The TWI outputformust operateandan open-drainbe connectedDPI input pins used TWI data clock should to logic level 0.

ADSP-214xx SHARC Processor Hardware Reference

A-215

DPI Signal Routing Unit Registers

Source Signals Table A-114. Group C Signals

Binary 000000 (0x0) 000001 (0x1) 000010 (0x2) 000011 (0x3) 000100 (0x4) 000101 (0x5) 000110 (0x6) 000111 (0x7) 001000 (0x8) 001001 (0x9) 001010 (0xA) 001011 (0xB) 001100 (0xC) 001101 (0xD) 001110 (0xE) 001111 (0xF) 010000 (0x10) 010001 (0x11) 010010 (0x12) 010011 (0x13) 010100 (0x14) 010101 (0x15) 010110 (0x16) 010111 (0x17) Signal LOW HIGH MISCB0_O MISCB1_O MISCB2_O TIMER0_PBEN_O TIMER1_PBEN_O Reserved UART0_TX_PBEN_O Reserved SPIMISO_PBEN_O SPIMOSI_PBEN_O SPICLK_PBEN_O SPIFLG0_PBEN_O SPIFLG1_PBEN_O SPIFLG2_PBEN_O SPIFLG3_PBEN_O SPIBMISO_PBEN_O SPIBMOSI_PBEN_O SPIBCLK_PBEN_O SPIBFLG0_PBEN_O SPIBFLG1_PBEN_O SPIBFLG2_PBEN_O SPIBFLG3_PBEN_O Pin Enable for MISO from SPI Pin Enable for MOSI from SPI Pin Enable for CLK from SPI Pin Enable for Slave Select 0 from SPI Pin Enable for Slave Select 1 from SPI Pin Enable for Slave Select 2 from SPI Pin Enable for Slave Select 3 from SPI Pin Enable for MISO from SPIB Pin Enable for MOSI from SPIB Pin Enable for CLK from SPIB Pin Enable for Slave Select 0 from SPIB Pin Enable for Slave Select 1 from SPIB Pin Enable for Slave Select 2 from SPIB Pin Enable for Slave Select 3 from SPIB Pin Enable for UART 0 Transmitter Description (Source Selection) Logic Level Low (0) Logic Level High (1) Miscellaneous Control 0 Miscellaneous Control 1 Miscellaneous Control 2 Enable for Timer 0 Output Enable for Timer 1 Output

A-216

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-114. Group C Signals (Contd)

Binary 011000 (0x18) 011001 (0x19) 011010 (0x1A) 011011 (0x1B) 011100 (0x1C) 011101 (0x1D) 011110 (0x1E) 011111 (0x1F) 100000 (0x20) 100001 (0x21) 100010 (0x22) 100011 (0x23) 100100 (0x24) 100101 (0x25) 100110 (0x26) 100111 (0x27) 101000 (0x28) 101001 (0x29) 101010 (0x2A) 101011 (0x2B) 101100111111 Signal FLAG4_PBEN_O FLAG5_PBEN_O FLAG6_PBEN_O FLAG7_PBEN_O FLAG8_PBEN_O FLAG9_PBEN_O FLAG10_PBEN_O FLAG11_PBEN_O FLAG12_PBEN_O FLAG13_PBEN_O FLAG14_PBEN_O FLAG15_PBEN_O TWI_DATA_PBEN_O TWI_CLK_PBEN_O MISCB3_O MISCB4_O MISCB5_O MISCB6_O MISCB7_O MISCB8_O Reserved Description (Source Selection) Pin Enable for Flag 4 Output Pin Enable for Flag 5 Output Pin Enable for Flag 6 Output Pin Enable for Flag 7 Output Pin Enable for Flag 8 Output Pin Enable for Flag 9 Output Pin Enable for Flag 10 Output Pin Enable for Flag 11 Output Pin Enable for Flag 12 Output Pin Enable for Flag 13 Output Pin Enable for Flag 14 Output Pin Enable for Flag 15 Output Data Output Enable from TWI Clock Output Enable from TWI Miscellaneous Control 3 Miscellaneous Control 4 Miscellaneous Control 5 Miscellaneous Control 6 Miscellaneous Control 7 Miscellaneous Control 8

ADSP-214xx SHARC Processor Hardware Reference

A-217

DPI Signal Routing Unit Registers

Destination Control Signal Registers (SRU2_PBENx)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DPI_PBEN05_I (2924) DPI Pin Buffer Enable 5 Input

DPI_PBEN03_I (1712) cont DPI Pin Buffer Enable 3 Input DPI_PBEN04_I (2318) DPI Pin Buffer Enable 4 Input

15 14 13 12

11 10

DPI_PBEN03_I (1712) DPI Pin Buffer Enable 3 Input DPI_PBEN02_I (116) DPI Pin Buffer Enable 2 Input

DPI_PBEN01_I (50) DPI Pin Buffer Enable 1 Input

Figure A-128. SRU2_PBEN0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DPI_PBEN10_I (2924) DPI Pin Buffer Enable 10 Input

DPI_PBEN08_I (1712) cont DPI Pin Buffer Enable 8 Input DPI_PBEN09_I (2318) DPI Pin Buffer Enable 9 Input
11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12

DPI_PBEN08_I (1712) DPI Pin Buffer Enable 8 Input DPI_PBEN07_I (116) DPI Pin Buffer Enable 7 Input

DPI_PBEN06_I (50) DPI Pin Buffer Enable 6 Input

Figure A-129. SRU2_PBEN1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DPI_PBEN14_I (2318) DPI Pin Buffer Enable 14 Input

DPI_PBEN13_I (1712) cont DPI Pin Buffer Enable 13 Input

15 14 13 12

11 10

DPI_PBEN13_I (1712) DPI Pin Buffer Enable 13 Input DPI_PBEN12_I (116) DPI Pin Buffer Enable 12 Input

DPI_PBEN11_I (50) DPI Pin Buffer Enable 11 Input

Figure A-130. SRU2_PBEN2 Register A-218 ADSP-214xx SHARC Processor Hardware Reference

Register Reference

DPI Pin Buffer Status Register (DPI_PIN_STAT)

The register is shown in Figure A-131 returns the status of DPI_PB141 pin buffers. This register is updated at PCLK/2 rate.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

DPI_PB14 DPI_PB13 DPI_PB12 DPI_PB11 DPI_PB10 DPI_PB09 DPI_PB08

DPI_PB01 DPI_PB02 DPI_PB03 DPI_PB04 DPI_PB05 DPI_PB06 DPI_PB07

Figure A-131. DPI_PIN_STAT Register

Peripherals Routed Through the DPI

The following sections provide information on the peripherals that are explicitly routed through the digital peripheral interface.

Serial Peripheral Interface Registers

The following sections describe the registers associated with the two serial peripheral interfaces (SPIs). Control Registers (SPICTL, SPICTLB) The SPI control (SPICTL) registers are used to configure and enable the SPI system. The bit settings for these registers are shown in Figure A-132

ADSP-214xx SHARC Processor Hardware Reference

A-219

Peripherals Routed Through the DPI

and described in Table A-115.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WTWDEN Word to Word Delay Enable AUTOSDS Auto Slave Device Select ILPBK Internal Loopback Enable RXFLSH Receive Buffer Flush

SGN Sign Extend Data SMLS Seamless Transfer TXFLSH Transmit Buffer Flush

15 14 13 12

11 10

PACKEN 8-Bit Packing Enable SPIEN SPI System Enable OPD Open Drain Output Enable for Data Pins SPIMS Master Slave Mode Bit CLKPL Clock Polarity CPHASE Clock Phase

TIMOD (01) Transfer Initiation Mode SENDZ Send Zero or Last Byte GM Fetch/Discard Incoming Data ISSEN Input Slave Select Enable DMISO Disable MISO Pin (Broadcast) WL (87) Word Length MSBF Most Significant Byte First

Figure A-132. SPICTL, SPICTLB Registers (Bits 150)

A-220

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-115. SPICTL Register Bit Descriptions (RW)

Bit 10 Name TIMOD Description Transfer Initiation Mode. Defines transfer initiation mode and interrupt generation. 00 = Initiate transfer by read of receive buffer. Interrupt active when receive buffer is full. 01 = Initiate transfer by write to transmit buffer. Interrupt active when transmit buffer is empty. 10 = Enable DMA transfer mode. Interrupt configured by DMA. 11 = Reserved Send Zero. Send zero or the last word when TXSPI is empty. 0 = Send last word 1 = Send zeros Get Data. When RXSPI is full, get data or discard incoming data. 0 = Discard incoming data 1 = Get more data, overwrites the previous data Input Slave-Select Enable. Enables slave-select input (SPI_DS_I pin) for the master. SPI_DS_I operation depends on the SPI configuration. If the SPI is a slave, SPI_DS_I acts as the slave-select input. The state of this input pin is observable in bit 7 of the SPIFLGx register. As master, SPI_DS_I can serve as an error-detection input in a multimaster environment. The ISSEN-bit enables this feature. When ISSEN =1, the SPI_DS_I input is the master mode error input; otherwise, SPI_DS_I is ignored. 0 = Disable 1 = Enable Disable MISO Pin. Disables MISO as an output. This is needed in an environment where a master wishes to transmit to various slaves at one time (broadcast). However, only one slave is allowed to transmit data back to the master. This bit should be set for all slaves, except the one from whom the master wishes to receive data. Different CPUs or processors can take turns being master, and one master may simultaneously shift data into multiple slaves (broadcast mode). However, only one slave may drive its output to write data back to the master at any given time. This must be enforced in the broadcast mode, where several slaves can be selected to receive data from the master, but only one slave can be enabled to send data back to the master. The (DMISO) bit disables MISO as an output. 0 = MISO enabled 1 = MISO disabled

SENDZ

GM

ISSEN

DMISO

ADSP-214xx SHARC Processor Hardware Reference

A-221

Peripherals Routed Through the DPI

Table A-115. SPICTL Register Bit Descriptions (RW) (Contd)

Bit 6 87 Name Reserved WL Word Length. SPI port can transmit and receive three word widths: 00 = 8 bits 01 = 16 bits 10 = 32 bits 8-bit word. 8-bit word. When transmitting, the SPI port sends out only the lower eight bits of the word written to the SPI buffer. When receiving, the SPI port packs the 8-bit word to the lower 32 bits of the RXSPI buffer while the upper bits in the registers are zeros. 16-bit word. When transmitting, the SPI port sends out only the lower 16 bits of the word written to the SPI buffer. When receiving, the SPI port packs the 16-bit word to the lower 32 bits of the RXSPI buffer while the upper bits in the register are zeros. 32-bit word. No packing of the RXSPI or TXSPI registers is necessary as the entire 32-bit register is used for the data word. Most Significant Byte First. 0 = LSB sent/received first 1 = MSB sent/received first Clock Phase. Selects the transfer format. 0 = SPICLK starts toggling at the middle of 1st data bit 1 = SPICLK starts toggling at the start of 1st data bit (default setting) Clock Polarity. 0 = Active high SPICLK (SPICLK low is the idle state) 1 = Active low SPICLK (SPICLK high is the idle state) Note that the CLKPL/CPHASE bits define the SPI mode. SPI Master Select. Configures SPI module as master or slave. 0 = Device is a slave device 1 = Device is a master device Description

MSBF

10

CPHASE

11

CLKPL

12

SPIMS

A-222

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-115. SPICTL Register Bit Descriptions (RW) (Contd)

Bit 13 Name OPD Description Open Drain Output Enable. Enables open drain data output enable for MOSI and MISO pins. 0 = Drive (MOSI and MISO driven) 1 = Open drain (MOSI and MISO three-stated). In a multimaster/slave SPI system, the data output pins (MOSI and MISO) can be configured to behave as open drain drivers to prevent contention and possible damage to pin drivers. An external pull-up resistor is required on both the MOSI/MISO pins when this option is selected. When the OPD bit is set and the SPI ports are configured as masters, the SPI_MOSI_O pin is three-stated. Instead the SPI_MOSI_PBEN_O pin is driven and act as output enable pin. Note that the corresponding DPI input buffer pin should be tied to GND. Similarly, when OPD is set and the SPI ports are configured as slaves, the SPI_MISO_O pin is three-stated. Instead the SPI_MISO_PBEN_O pin is driven and act as output enable pin. Note that the corresponding DPI input buffer pin should be tied to GND. See Pin Buffers as Open Drain on page 10-13. SPI Port Enable. Enables the SPI port. If configured as a master (SPIMS=1) and SPIEN=0, the MOSI and SPICLK outputs are disabled, and the MISO input is ignored. If configured as a slave (SPIMS=0) and SPIEN=0, the MOSI and SPICLK inputs are ignored, and the MISO output is disabled. The SPIEN and SPIMS bits can be cleared by hardware if the MME-bit is set. For SPI slaves, the slave-select input (SPI_DS_I) acts like a reset for the internal SPI logic. For this reason, the SPI_DS_I line must be error free. The SPIEN bit can also be used as a software reset of the internal SPI logic. An exception to this is the RW1C-type (read-write 1-to-clear) bits in the SPISTATx registers. These bits remain set if they are already set. Note: always clear the RW1C-type bits in SPISTATx registers before re-enabling the SPI, as these bits do not get cleared even if the SPI is disabled. This can be done by writing 0xFF to the SPISTATx registers. In the case of an MME error, enable the SPI ports after SPI_DS_I is deasserted. 0 = SPI module is disabled 1 = SPI module is enabled. When this bit transitions from high to low the RX and TX buffers are flushed which takes 2 core clock cycles.

14

SPIEN

ADSP-214xx SHARC Processor Hardware Reference

A-223

Peripherals Routed Through the DPI

Table A-115. SPICTL Register Bit Descriptions (RW) (Contd)

Bit 15 Name PACKEN Description Packing Enable. The SPI unpacks data when it transmits and packs data when it receives. In order to communicate with 8-bit SPI devices and store 8-bit words in internal memory, a packed transfer feature is built into the SPI port. 0 = No packing 1 = 8 to 16-bit packing Note: This bit may be 1 only when WL = 00 (8-bit transfer). When in transmit mode, the PACKEN bit unpacks data. When packing is enabled, two 8-bit words are packed into one 32-bit word. When the SPI port is transmitting, two 8-bit words are unpacked from one 32-bit word. When receiving, words are packed into one 32-bit word from two 8-bit words. The value 0xXXLMXXJK (where XX is any random value and JK and LM are data words to be transmitted out of the SPI port) is written to the TXSPI register. The processor transmits 0xJK first and then transmits 0xLM. The receiver packs the two words received, 0xJK and then 0xLM, into a 32-bit word. They appear in the RXSPI register as: 0x00LM00JK => if SGN is configured to 0 or L, J < 7 0xFFLMFFJK => if SGN is configured to 1 and L, J > 7 Sign Extend. 0 = No sign extension 1 = Sign extension Seamless Transfer. 0 = Seamless transfer disabled. After each word transfer there is a delay before the next word transfer starts. The delay is 2.5 SPICLK cycles 1 = Seamless transfer enabled. There is no delay before the next word starts, a seamless operation. Not supported in mode TIMOD1-0 = 00 and CPHASE=0 for all modes. Flush Transmit Buffer. Write a 1 to clear TXSPI. 0 = TXSPI not cleared 1 = TXSPI cleared. This bit can be set together with the enable bit. Note this bit is not self-clearing Clear RXSPI. Write a 1 to clear RXSPI. 0 = RXSPI not cleared 1 = RXSPI cleared. This bit can be set together with the enable bit. Note this bit is not self-clearing

16

SGN

17

SMLS

18

TXFLSH

19

RXFLSH

A-224

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-115. SPICTL Register Bit Descriptions (RW) (Contd)

Bit 20 Name ILPBK Description Internal Loopback. This mode interconnects the MOSI with the MISO pins internally. In this mode the SPIMS bit must be set. 0 = No internal loopback 1 = Internal loopback enabled Auto Slave device Select. 0 = Auto slave device select controlled by SPI hardware only for CPHASE=0 1 = Auto slave device select controlled by SPI hardware regardless for CPHASE setting Feature not supported if SMLS-bit is set Word to Word Delay Enable. According to AUTOSDS bit, the length of the chip de-select pulse is programmable. 0 = Word to word delay is fixed. (See the product specific data sheet.) 1 = Word to word delay programmable by SPIBAUD[25:20]. This feature not supported if the SMLS bit is set.

21

AUTOSDS

22

WTWDEN

3123 Reserved

DMA Configuration Registers (SPIDMAC, SPIDMACB) These 17-bit SPI registers are used to control DMA transfers and are shown in Figure A-133 and described in Table A-116.

ADSP-214xx SHARC Processor Hardware Reference

A-225

Peripherals Routed Through the DPI

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

SPICHS DMA Chain Loading Status

15 14 13 12

11 10

SPIDMAS DMA Transfer Status SPIERRS DMA Error Status SPISx (1312) DMA FIFO Status SPIMME Multimaster Error SPIUNF Transmit Underflow Error SPIOVF Receive Overflow Error INTERR Enable Interrupt on Error

SPIDEN DMA Enable SPIRCV DMA Write/Read INTEN Enable DMA Interrupt on Transfer INTETC Interrupt on External Transfer Complete Enable SPICHEN SPI DMA Chaining Enable FIFOFLSH DMA FIFO Clear

Figure A-133. SPIDMAC, SPIDMACB Registers Table A-116. SPIDMAC, SPIDMACB Register Bit Descriptions (RW)
Bit 0 Name SPIDEN Description DMA Enable. 0 = Disable 1 = Enable DMA Write/Read. 0 = SPI transmit (read from internal memory) 1 = SPI receive (write to internal memory) Enable DMA Interrupt on Transfer. 0 = Disable 1 = Enable

SPIRCV

INTEN

A-226

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-116. SPIDMAC, SPIDMACB Register Bit Descriptions (RW) (Contd)

Bit 3 Name INTETC Description Interrupt on External Transfer Complete Enable. Selects interrupt event for transmit DMA 0 = DMA interrupt generated when DMA count reaches zero. 1 = DMA interrupt generated when last bit of last word is shifted out. Note: both INTEN and INTETC bits, when enabled, generate an interrupt for INTETC. SPI DMA Chaining Enable. 0 = Disable 1 = Enable

SPICHEN

65 7

Reserved FIFOFLSH DMA FIFO Clear. If this bit is set, it takes 2 core clock cycles to flush the buffer. It clears the SPIS bit. 0 = Disable 1 = Enable Clearing the SPIEN/SPIDEN bits have no affect on the buffer Note this bit is not self-clearing Enable Interrupt on Error. 0 = Disable 1 = Enable Receive OverFlow Error (SPIRCV = 1). 0 = Successful transfer 1 = Error data received with RXSPI full Transmit Underflow Error (SPIRCV = 0). 0 = Successful transfer 1 = Error occurred in transmission with no new data in TXSPI Multimaster Error. 0 = Successful transfer 1 = Error during transfer DMA FIFO Status. 00 = FIFO empty 11 = FIFO full 10 = FIFO partially full 01 = Reserved

INTERR

9 (RO)

SPIOVF

10 (RO)

SPIUNF

11 (RO)

SPIMME

1312 (RO)

SPIS

ADSP-214xx SHARC Processor Hardware Reference

A-227

Peripherals Routed Through the DPI

Table A-116. SPIDMAC, SPIDMACB Register Bit Descriptions (RW) (Contd)

Bit 14 (RO) Name SPIERRS Description DMA Error Status. This bit is set if SPIOVF, SPIUNF or DPIMME bits are set. 0 = Successful DMA transfer 1 = Errors during DMA transfer DMA Transfer Status. 0 = DMA idle 1 = DMA in progress DMA Chain Loading Status. 0 = Chain idle 1 = Chain loading in progress

15 (RO)

SPIDMAS

16 (RO)

SPICHS

3117

Reserved

Baud Rate Registers (SPIBAUD, SPIBAUDB) These SPI registers are used to set the bit transfer rate for a master device. When configured as slaves, the value written to these registers is ignored. The (SPIBAUDx) registers can be read from or written to at any time. Bit descriptions are provided in Table A-117. Note that the minimum value of BAUDR = 0x2, since the max SPICLK = PCLK/8 in master mode. Table A-117. SPIBAUD, SPIBAUDB Register Bit Descriptions (RW)
Bit 0 151 Name Reserved BAUDR Baud Rate Enable. Enables the master SPICLK per the equation: SPICLK baud rate = PCLK /(4 x BAUDR) Default = 0 Description

1916 2520

Reserved STDC Sequential Transfer Delay. The word to word delay(T4) = 1.5 SPI CLK Period + T3 and T3 = 0.5 SPICLK period for STDC = 0. T3 = STDC SPICLK period for STDC > 0.

3126

Reserved

A-228

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Status (SPISTAT, SPISTATB) Registers The SPISTAT and SPISTATB registers are used to detect when an SPI transfer is complete, if transmission/reception errors occur, and the status of the TXSPI and RXSPI FIFOs. The bit settings for these registers are shown in Figure A-134 and described in Table A-118.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

SPIFE External Transaction Complete TXCOL Transmit Collision Error RXS RXSPI Data Buffer Status ROVF Reception Error (Overflow)

SPIF SPI Transaction Complete MME Multimaster Error TUNF Transmission Error (Underflow) TXS TXSPI Data Buffer Status

Figure A-134. SPISTAT, SPISTATB Registers Table A-118. SPISTAT Register Bit Descriptions (RO)
Bit 0 (RO) 1 (RW1C) Name SPIF MME Description SPI Transmit or Receive Transfer Complete. SPIF is set when an SPI single-word transfer is complete. Multimaster Error or Mode-Fault Error. MME is set in a master device when some other device tries to become the master. In multimaster mode, if the SPI_DS_I input signal of a master is asserted (low) an error has occurred. This means that another device is also trying to be the master. Clears the SPIMME bit.

ADSP-214xx SHARC Processor Hardware Reference

A-229

Peripherals Routed Through the DPI

Table A-118. SPISTAT Register Bit Descriptions (RO) (Contd)

Bit 2 (RW1C) Name TUNF Description Transmission Error. TUNF is set when transmission occurred with no new data in TXSPI register. The TUNF bit (2) is set when all of the conditions of transmission are met and there is no new data in TXSPI (TXSPI is empty). In this case, the transmission contents depend on the state of the SENDZ bit in the SPICTL register. Clears the SPIUNF bit. Transmit Data Buffer Status. TXSPI data buffer status. 0 = Empty 1 = Full Reception Error. ROVF is set when data is received with receive buffer full. Receive Data Buffer Status. The ROVF flag (bit 4) is when a new transfer has completed before the previous data is read from the RXSPI register. This bit indicates that a new word was received while the receive buffer was full. The ROVF flag is cleared by a RW1C-type software operation. The state of the GM bit in the SPICTL register determines whether the RXSPI register is updated with the newly received data or whether that new data is discarded. 0 = Empty 1 = Full Transmit Collision Error. When TXCOL is set, it is possible that corrupt data was transmitted. The TXCOL flag (bit 6) is set when a write to the TXSPI register coincides with the load of the shift register. The write to TXSPI can be via the software or the DMA. This bit indicates that corrupt data may have been loaded into the shift register and transmitted. In this case, the data in TXSPI may not match what was transmitted. This error can easily be avoided by proper software control. The TXCOL bit is cleared by a RW1C-type software operation. Note that this bit is never set when the SPI is configured as a slave with CPHASE = 0. The collision may occur, but it cannot be detected.

3 (RO)

TXS

4 (RW1C) 5 (RO)

ROVF RXS

6 (RW1C)

TXCOL

A-230

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-118. SPISTAT Register Bit Descriptions (RO) (Contd)

Bit 7 (RO) Name SPIFE Description External Transaction Complete. Set (= 1) when the SPI transaction is complete on the external interface. This bit is very useful in DMA mode showing that the peripheral has completed all the external transfers corresponding to the DMA programmed. For more information, see Transfer Initiate Mode on page 16-13 and DMA Transfers on page 16-24.

318

Reserved

SPI Port Flags Registers (SPIFLG, SPIFLGB) The SPIFLG and SPIFLGB registers are used to enable individual SPI slave-select lines when the SPI is enabled as a master. This register is ignored if the SPI is programmed as s slave. The bit settings for these registers are shown in Figure A-135 and described in Table A-119.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

SPIFLGx (118) SPI Device Select Control ISSS Status of input Slave-select Pin

DSxEN (30) SPI Device Select Enable

Figure A-135. SPIFLG, SPIFLGB Registers Table A-119. SPIFLG, SPIFLGB Register Bit Descriptions (RW)
Bit 30 Name DSxEN Description SPI Device Select Enable. Enables or disables the corresponding output signal to the SRU2 be used for SPI slave-select. 0 = Disable SPIFLGx output enable 1 = Enable SPIFLGx output enable Note DS0EN bit is set in SPI master mode only.

64

Reserved

ADSP-214xx SHARC Processor Hardware Reference

A-231

Peripherals Routed Through the DPI

Table A-119. SPIFLG, SPIFLGB Register Bit Descriptions (RW) (Contd)

Bit 7 (RO) Name ISSS Description Input Slave Service Select. Reflects the service selection for the slave-select input pin (SPI_DS_I). 0 = SPI_DS_I pin ignored 1 = SPI_DS_I pin used as multimaster error detection (default for SPI only) SPI Device Select Control. Selects (if cleared, = 0) a corresponding DPI pin (depending on pin routing) output to be asserted for an SPI slave-select. For AUTOSDS=1, there is automatic HW control regardless of CPHASE setting 0000 = All SPIFLGx cleared 1111 = All SPIFLGx set (default)

118

SPIFLGx

1231

Reserved

UART Control and Status Registers

The processor provides a set of PC-style, industry-standard control and status registers for each UART. These IOP registers are byte-wide registers that are mapped as half-words with the most significant byte zero-filled. Global Control Registers (UART0TXCTL, UART0RXCTL) Use these global registers (described in Table A-120 and Table A-121) to enable the UART receive or transmit controllers for core data transfers and both standard DMA or chained DMA.

A-232

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-120. UART0TXCTL Register Descriptions (RW)

Bit 0 Name UARTEN Description Transmit Control Enable. This global bit must be set to enable the transmit path. 0 = Disable UART TX 1 = Enable UART TX If this bit transitions from high to low the TX buffer is flushed which takes 7 core clock cycles. DMA Enable. 0 = Disable DMA 1 = Enable DMA on the specified channel

UARTDEN

UARTCHEN Chain Pointer DMA Enable. 0 = Disable chained DMA 1 = Enable chained DMA on the specified channel

Table A-121. UART0RXCTL Register Descriptions (RW)

Bit 0 Name UARTEN Description Receive Control Enable. This global bit must be set to enable the receive path. 0 = Disable UART RX 1 = Enable UART RX If this bit transitions from high to low the RX buffer is flushed which takes 7 core clock cycles. DMA Enable. 0 = Disables DMA 1 = Enables DMA on the specified channel Chain Pointer DMA Enable. 0 = Disable chained DMA 1 = Enable chained DMA on the specified channel

UARTDEN

UARTCHEN

ADSP-214xx SHARC Processor Hardware Reference

A-233

Peripherals Routed Through the DPI

Divisor Latch Registers (UART0DLL, UART0DLH) The bit rate is characterized by the peripheral clock (PCLK) and the 16-bit divisor (2 x 8-bit. The divisor is split into the UART divisor latch low byte register (UART0DLL) and the UART divisor latch high byte register (UART0DLH), both shown in Figure A-136.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

Divisor Latch Low or High Byte (70)

Figure A-136. UART Divisor Latch Registers (UART0DLL, UART0DLH) Mode Register (UART0MODE) The UART mode register controls miscellaneous settings as shown in Figure A-137 and described Table A-122.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

UARTPACK UARTPST (65) Pin Status UARTAEN Enable Address Detect UARTRX9 Enable 9-Bit Tx in Receive Packing Enable UARTPKSYN Synchronize Data Packing in Rx UARTTX9 Enable 9-Bit Tx in Transmitter

Figure A-137. UART0MODE Register

A-234

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Register Reference

Table A-122. UART0MODE Register Bit Descriptions (RW)

Bit 0 Name UARTPACK Description Packing Enable. 0 = No pack 1 = Packing enabled. Consecutive data words (example 0xAB and 0xCD) are packed as 0x00CD 00AB in the receiver, and 0x00CD 00AB is transmitted as two words of 0xAB and 0xCD successively from the transmitter. For more information, see Data Packing/Unpacking on page 21-8. Synchronize Data Packing in RX. When written with a 1, the next data byte goes to the lower byte position of the RBR register. This bit always returns zero on reads. Enable 9-Bit Data in Transmitter. 0 = Word length select (WLS) 1 = 9-bit Enable 9-Bit Data in Receiver. 0 = Word length select (WLS) 1 = 9-bit Enable Address Detect (If UARTRX9 = 1). 0 = Disable address detection; all bytes are received 1 = Enable address detection; interrupt and load of RBR when RX9D is set Transmit Pin Status Control. Changes the status/level of the transmit pin for a disabled UART TX control (UARTEN=0 in UART0TXCTL). 00 = UART0_TX_O is low 01 = UART0_TX_O is three-stated (default) 10 = UART0_TX_O is three-stated 11 = UART0_TX_O is high

1 (RW1S)

UARTPKSYN

UARTTX9

UARTRX9

UARTAEN

65

UARTPST

ADSP-214xx SHARC Processor Hardware Reference

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Line Control Register (UART0LCR) The UART line control register (shown in Figure A-138 and described in Table A-123) controls the format of received and transmitted character frames. registers the Some UARTmapped tosharesamesame IOPasaddress. The registers are the address the
UART0RBR UART0DLL

and registers. The UART0DLH registers are mapped to the same address as the interrupt enable registers (UART0IER). Note that the UARTDLAB bit in the UART0LCR register must be set before the UART divisor latch registers can be accessed. If the UARTDLAB bit is cleared, access to the UART0THR and UART0RBR or UART0IER registers occurs.
UART0THR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

UARTDLAB Divisor Latch Access UARTSB Set Break UARTSTP Stick Parity UARTEPS Even Parity Select

UARTWLS (10) Word Length Select UARTSTB Stop Bits UARTPEN Parity Enable

Figure A-138. UART0LCR Register

A-236

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Register Reference

Table A-123. UART0LCR Register Bit Descriptions (RW)

Bit 10 Name UARTWLS Description Word Length Select. 00 = 5-bit word(UARTWLS5) 01 = 6-bit word(UARTWLS6) 10 = 7-bit word(UARTWLS7) 11 = 8-bit word(UARTWLS8) Stop Bits. 0 = 1 stop bit 1 = 2 stop bits for non-5-bit word length or 1 1/2 stop bits for 5-bit word length Parity Enable. 0 = Parity not transmitted or checked 1 = Transmit and check parity Even Parity Select. 0 = Odd parity when PEN = 1 and STP = 0 1 = Even parity when PEN = 1 and STP = 0 Stick Parity. Forces parity to defined value if set and PEN = 1. 0 = Parity transmitted and checked as 1 1 = Parity transmitted and checked as 0 Set Break. The UART transmit pin is three-state after reset. This bit is used to force the transmit pin to zero if the UARTEN bit set in UART0TXCTL register. Using this bit the UART TX pin can be used as a flag pin when the UART is not used. 0 = UART0_TX_O pin is high 1 = UART0_TX_O pin is low Divisor Latch Access Bit. Because some IOP registers share the same address, this bit provides access as follows. 0 = Enable access to UART0THR, UART0RBR, and UART0IER registers 1 = Enable access to UART0DLL and UART0DLH registers

UARTSTB

UARTPEN

UARTEPS

UARTSTP

UARTSB

UARTDLAB

ADSP-214xx SHARC Processor Hardware Reference

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Line Status Register (UART0LSR) The UART line status register (UART0LSR) contains UART status information as shown in Figure A-139 and described in Table A-124. There is also a shadow register, UART0LSRSH, that allows programs to read the contents of the corresponding main register without affecting the status the UART.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

UARTRX9D 9th Bit UARTTEMT TSR and UART0_THR Empty UARTTHRE UART0_THR Empty UARTBI Break Interrupt

UARTDR Data Ready UARTOE Overrun Error UARTPE Parity Error UARTFE Framing Error

Figure A-139. UART0LSR Register Table A-124. UART0LSR Register Bit Descriptions (RO)
Bit 0 Name UARTDR Description Data Ready. This bit is cleared when the UART receive buffer (UART0RBR) is read. 0 = No new data 1 = UART0_RBR holds new data Overrun Error. 0 = No overrun 1 = UART0RBR overwritten before read Parity Error. 0 = No parity error 1 = Parity error Framing Error. 0 = No error 1 = Invalid stop bit error

1 (ROC1, 2) UARTOE

2 (ROC1, 2) UARTPE

3 (ROC1, 2) UARTFE

A-238

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Register Reference

Table A-124. UART0LSR Register Bit Descriptions (RO) (Contd)

Bit 4 (ROC )
2

Name UARTBI

Description Break Interrupt. Indicates that Rx pin was held low for more than the max word length. 0 = No break interrupt 1 = Break interrupt. UART0_THR Empty. The UARTTHRE bit indicates that the UART transmit channel is ready for new data, and software can write to the UART0THR register. Writes to UART0THR clear the UARTTHRE bit. It is set again when data is copied from UART0THR to the transmit shift register (UART0TSR). The UARTTEMT bit can be evaluated to determine whether a recently initiated transmit operation has been completed. 0 = Not empty 1 = Empty (default) TSR and UART0_THR Empty. 0 = Full 1 = Both empty 9th bit of the received character-address detect

UARTTHRE

UARTTEMT

7 1 2

UARTRX9D

These bits are read-only in the UART0LSRSH (shadow) register. This bit is cleared by a read of the UART0LSR register.

Interrupt Enable Register (UART0IER) The interrupt enable register (shown in Figure A-140) is used to enable requests for system handling of empty or full states of UART data registers. Unless polling is used as a means of action, the UARTRBFIE and/or UARTTBEIE bits in this register are normally set.

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31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

15 14 13 12

11 10

UARTADIE Enable Address Detect Interrupt in 9-Bit Mode UARTTXFIE Enable Transmitter Empty Interrupt

UARTRBFIE Enable Receive Buffer Full Interrupt UARTTBEIE Enable Transmit Buffer Empty Interrupt UARTLSIE Enable Line Status Interrupt

Figure A-140. UART0IER Register Table A-125. UART0IER Register Bit Descriptions (RW)
Bit 0 Name UARTRBFIE Description Enable Receive Buffer Full Interrupt. 0 = No interrupt 1 = Generate RX interrupt if UARTDR bit in UART0LSR is set Enable Transmit Buffer Empty Interrupt. 0 = No interrupt 1 = Generate TX interrupt if UARTTHRE bit in UART0LSR is set Enable Line Status Interrupt. 0 = No interrupt 1 = Generate line status interrupt if any of UART0LSR[41] is set Enable Transmit Empty Interrupt (TEMT = TSR + THR empty). 0 = No interrupt 1 = Generate TX interrupt if UARTTEMT bit in UART0LSR is set Enable Address Detect Interrupt in 9-Bit Mode. 0 = No interrupt 1 = Generate RX interrupt when address is detected in 9-bit mode

UARTTBEIE

UARTLSIE

UARTTXFIE

UARTADIE

A-240

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Register Reference

Interrupt Identification Registers (UART0IIR, UART0IIRSH) For legacy reasons, the UART interrupt identification register (UART0IIR, shown in Figure A-141) still reflects the UART interrupt status. Legacy operation may require bundling all UART interrupt sources to a single interrupt channel and servicing them all by the same software routine. For more information, see Appendix 2, Interrupt Control.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

UARTISTAT (31) In the order of interrupt priority, highest first

UARTNOINT Pending Interrupt

Figure A-141. UART0IIR Register Table A-126. UART0IIR Register Bit Descriptions (RO)
Bit 0 Name UARTNOINT Description Pending Interrupt. When UARTNOINT bit cleared it signals that an interrupt is pending. 0 = Interrupt pending 1 = No interrupt pending (default) In the Order of Interrupt Priority, Highest First. 011 = Receive line status. Read UART0LSR to clear interrupt request. 100 = Address detect. Read RBR to clear interrupt request. 010 = Receive data ready. Read UART RBR to clear interrupt request. 001 = UART0THR empty. Write UART0THR or read UART0IIR to clear interrupt request, when priority = 4. 000 = TEMT = transmitter empty (UART THR & TSR empty). Write UART0THR or read UART0IIR to clear interrupt request, when priority = 5. In the case where both interrupts are signalling, the UART0IIR register reads 0x06. When a UART interrupt is pending, the interrupt service routine (ISR) needs to clear the interrupt latch explicitly.

31 (ROC1)

UARTISTAT

These bits are read-only in the UART0IIRSH (shadow) register.

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Peripherals Routed Through the DPI

There is also a shadow register, UART0IIRSH. This register allows programs to read the contents of the corresponding main register without affecting the status of the UART. Scratch Register (UART0SCR) This register (Figure A-142) is used for general-purpose data storage and does not control the UART hardware in any way.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

Scratch (70)

Figure A-142. UART0SCR Registers (RW) DMA Status Registers (UART0TXSTAT, UART0RXSTAT) These read-only registers (described in Table A-127 and Table A-128) provide DMA status information. Table A-127. UART0TXSTAT Register Bit Descriptions (RO)
Bit 0 1 Name Reserved UARTDMASTAT DMA Status. Provides DMA status. 0 = TX DMA is inactive 1 = TX DMA is active DMA Chaining Status. Provides DMA chaining status. 0 = TX DMA chain loading is inactive 1 = TX DMA chain loading is active Description

UARTCHSTAT

A-242

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-128. UART0RXSTAT Register Bit Descriptions (RO)

Bit 0 (ROC) Name UARTERRIRQ Description Receive Channel Error Interrupt. 0 = No error interrupt 1 = Error interrupt generated due to receive error (parity/overrun/framing). This bit is cleared on a read of the UART0LSR register. DMA Status. Provides DMA status. 0 = RX DMA is inactive 1 = RX DMA is active DMA Chaining Status. Provides DMA chaining status. 0 = RX DMA chain loading is inactive 1 = RX DMA chain loading is active

UARTDMASTAT

UARTCHSTAT

Two Wire Interface Registers

The two wire interface (TWI) registers provide all control and status bits for this peripheral. Status bits can be updated by their respective functional blocks. Master Internal Time Register (TWIMITR) The TWIMITR register, shown in Figure A-143 and described in Table A-129), is used to enable the TWI module as well as to establish a relationship between the peripheral clock (PCLK) and the TWI controllers internally-timed events. The internal time reference is derived from PCLK using the prescaled value: PRESCALE = fPCLK/10 MHz
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

TWIEN TWI Enable

PRESCALE (60) Prescale

Figure A-143. TWIMITR Register

ADSP-214xx SHARC Processor Hardware Reference

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Table A-129. TWIMITR Register Bit Descriptions (RW)

Bit 06 Name PRESCALE Description Prescale. The number of peripheral clock (PCLK) periods used in the generation of one internal time reference. The value of PRESCALE must be set to create an internal time reference with a period of 10 MHz. This is represented as a 7-bit binary value. TWI Enable. This bit must be set for slave or master mode operation. It is recommended that this bit be set at the time PRESCALE is initialized and remain set. This guarantees accurate operation of bus busy detection logic. 0 = Disable TWI 1 = Enable TWI master and slave mode operation. If this bit transitions from high to low the buffer is flushed which takes 2 clock cycles

TWIEN

Clock Divider Register (TWIDIV) During master mode operation, the SCL clock divider register (shown in Figure A-144 and described in Table A-130) values are used to create the high and low durations of the serial clock (SCL). Serial clock frequencies can vary from 400 KHz to less than 20 KHz. The resolution of the clock generated is 1/10 MHz or 100 ns.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

CLKHI (158)

CLKLOW (70)

Figure A-144. TWIDIV Register

A-244

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Register Reference

Table A-130. TWIDIV Register Bit Descriptions (RW)

Bit 70 158 Name CLKLOW CLKHI Description Clock Low. Number of internal time reference periods the serial clock (TWI_CLK) is held low. Represented as an 8-bit binary value. Clock High. Number of internal time reference periods the serial clock (TWI_CLK) waits before a new clock low period begins (assuming a single master). Represented as an 8-bit binary value.

Master Control Register (TWIMCTL) The TWI master mode control register (shown in Figure A-145 and described in Table A-131) controls the logic associated with master mode operation. Bits in this register do not affect slave mode operation and should not be modified to control slave mode functionality.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

TWISCLOVR Serial Clock Override TWISDAOVR Serial Data Override TWIDCNT (136) Number of Data Bytes to Transfer TWIRSTART Repeat Start

TWIMEN Master Mode Enable TWIMLEN Master Address Length TWIMDIR Master Transfer Direction TWIFAST Fast Mode TWISTOP Issue Stop Condition

Figure A-145. TWIMCTL Register

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Table A-131. TWIMCTL Register Bit Descriptions (RW)

Bit 0 Name TWIMEN Description Master Mode Enable. Clears itself at the completion of a transfer. This includes transfers terminated due to errors. 0 = Master mode functionality is disabled. If MEN is cleared during operation, the transfer is aborted and all logic associated with master mode transfers are reset. Serial data and serial clock (TWI_DATA, TWI_CLOCK) are no longer driven. Write 1-to-clear status bits are not effected. 1 = Master mode functionality is enabled. A START condition is generated if the bus is idle. Master Address Length. 0 = Address is 7-bit 1 = Reserved. Setting this bit to one causes unpredictable behavior. Master Transfer Direction. 0 = The initiated transfer is master transmit 1 = The initiated transfer is master receive Fast Mode. 0 = Standard mode timing specifications in use (100 kHz) 1 = Fast mode timing specifications in use (400 kHz) Issue STOP Condition. 0 = Normal transfer operation 1 = The transfer concludes as soon as possible avoiding any error conditions (as if data transfer count had been reached) and at that time the interrupt source register is updated along with any associated status bits. Repeat START. 0 = Transfer concludes with a STOP condition 1 = Rather than issuing a STOP condition at the conclusion of the current transfer (DCNT = 0), issue a repeated START condition, followed by an address byte at the beginning of the next transmission. The current transfer is concluded with updates to the appropriate status and interrupt bits. If errors occurred during the previous transfer, a repeat START does not occur. In the absence of any errors, master enable (MEN) does not clear itself on a repeat start. Data Transfer Count. Indicates the number of data bytes to transfer. As each data word is transferred, the data transfer count is decremented. When DCNT is zero, a STOP (or restart condition) is issued. Setting DCNT to 0xFF disables the counter. In this transfer mode, data continues to be transferred until it is concluded by setting the STOP bit.

TWIMLEN

TWIMDIR

TWIFAST

TWISTOP

TWIRSTART

136

TWIDCNT

A-246

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-131. TWIMCTL Register Bit Descriptions (RW) (Contd)

Bit 14 Name TWISDAOVR Description Serial Data (TWI_DATA) Override. For use when direct control of the Serial Data line is required. Normal master and slave mode operation should not require override operation. 0 = Normal serial data operation under the control of the transmit shift register and acknowledge logic 1 = Serial data output is driven to an active zero level, overriding all other logic. This state is held until the bit location is cleared. Serial Clock (TWI_Clock) Override. For use when direct control of the serial clock line is required. Normal master and slave mode operation should not require override operation. 0 = Normal serial clock operation under the control of master mode clock generation and slave mode clock stretching logic 1 = Serial clock output is driven to an active zero level, overriding all other logic. This state is held until the bit location is cleared.

15

TWISCLOVR

Master Address Register (TWIMADDR) During the addressing phase of a transfer, the TWI controller, with its master enabled, transmits the contents of the TWI master mode address register (TWIMADDR, shown in Figure A-146). When programming this register, omit the read/write bit. That is, only the upper 7 bits that make up the slave address should be written to this register. For example, if the slave address is 1010000X, then TWIMADDR is programmed with 1010000, which corresponds to 0x50. When sending out the address on the bus, the TWI controller appends the read/write bit as appropriate, based on the state of the TWIMDIR bit in the master mode control register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

MADDR (60) Master Mode Address

Figure A-146. TWIMADDR Register (RW)

ADSP-214xx SHARC Processor Hardware Reference

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Peripherals Routed Through the DPI

Master Status Register (TWIMSTAT) The TWI master mode status register (TWIMSTAT, shown in Figure A-147 and described in Table A-132) holds information during master mode transfers and at their conclusions. Generally, master mode status bits are not directly associated with the generation of interrupts but offer information on the current transfer. Slave mode operation does not affect master mode status bits.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

TWIBUSY Bus Busy TWISCLSEN Serial Clock Sense TWISDASEN Serial Data Sense TWIWERR Buffer Write Error

TWIMPROG Master Tx in Progress TWILOST Lost Arbitration TWIANAK Address Not Acknowledged TWIDNAK Data Not Acknowledged TWIRERR Buffer Read Error

Figure A-147. TWIMSTAT Register Table A-132. TWIMSTAT Register Bit Descriptions (RO)
Bit 0 Name TWIMPROG Description Master Transfer In Progress. 0 = Currently no transfer is taking place. This can occur once a transfer is complete or while an enabled master is waiting for an idle bus. 1 = A master transfer is in progress. Lost Arbitration. 0 = The current transfer has not lost arbitration with another master. 1 = The current transfer was aborted due to the loss of arbitration with another master.

1 (RW1C) TWILOST

A-248

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-132. TWIMSTAT Register Bit Descriptions (RO) (Contd)

Bit Name Description Address Not Acknowledged. 0 = The current master transfer has not detected a NAK during addressing. 1 = The current master transfer was aborted due to the detection of a NAK during the address phase of the transfer. Data Not Acknowledged. 0 = The current master transfer has not detected a NAK during data transmission. 1 = The current master transfer was aborted due to the detection of a NAK during data transmission. Buffer Read Error. 0 = The current master transmit has not detected a buffer read error. 1 = The current master transfer was aborted due to a transmit buffer read error. At the time data was required by the transmit shift register, the buffer was empty. Buffer Write Error. 0 = The current master receive has not detected a receive buffer write error. 1 = The current master transfer was aborted due to a receive buffer write error. The receive buffer and receive shift register were both full at the same time. Serial Data Sense. For use when direct sensing of the serial data line is required. The register value is delayed due to the input filter (nominally 50 ns). Normal master and slave mode operation should not require this feature. 0 = An inactive one is currently being sensed on serial data line. 1 = An active zero is currently being sensed on serial data line. The source of the active driver is not known and can be internal or external. 2 (RW1C) TWIANAK

3 (RW1C) TWIDNAK

4 (RW1C) TWIRERR

5 (RW1C) TWIWERR

TWISDASEN

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Table A-132. TWIMSTAT Register Bit Descriptions (RO) (Contd)

Bit 7 Name TWISCLSEN Description Serial Clock Sense. For use when direct sensing of the serial clock line is required. The register value is delayed due to the input filter (nominally 50 ns). Normal master and slave mode operation should not require this feature. 0 = An inactive one is currently being sensed on SCLK. 1 = An active zero is currently being sensed on SCLK. The source of the active driver is not known and can be internal or external. Bus Busy. Indicates whether the bus is currently busy or free. This indication applies to all devices. Upon a START condition, setting the register value is delayed due to the input filtering. Upon a STOP condition, clearing the register value occurs after time tBUF. 0 = The bus is free. The clock and data bus signals have been inactive for the appropriate bus free time. 1 = The bus is busy. Clock and/or data activity has been detected.

TWIBUSY

Slave Mode Control Register (TWISCTL) The TWI slave mode control register (shown in Figure A-148 and described in Table A-133), controls the logic associated with slave mode operation. Settings in this register do not affect master mode operation and should not be modified to control master mode functionality.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

TWIGCE General Call Enable TWINAK Not Acknowledge

TWISEN Slave Enable TWISLEN Slave Address Length TWIDVAL Slave Transmit Data Valid

Figure A-148. TWISCTL Register

A-250

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-133. TWISCTL Register Bit Descriptions (RW)

Bit 0 Name TWISEN Description Slave Enable. 0 = The slave is not enabled. No attempt is made to identify a valid address. If cleared during a valid transfer, clock stretching ceases, the serial data line is released and the current byte is not acknowledged. 1 = The slave is enabled. Enabling slave and master modes of operation concurrently is allowed. Slave Address Length. 0 = Address is a 7-bit address 1 = Reserved. Setting this bit to 1 causes unpredictable behavior. Slave Transmit Data Valid. 0 = Data in the transmit FIFO is for master mode transmits and is not allowed to be used during a slave transmit, and the transmit FIFO is treated as if it is empty. 1 = Data in the transmit FIFO is available for a slave transmission. Not Acknowledged. 0 = Slave receive transfer generates an ACK at the conclusion of a data transfer. 1 = Slave receive transfer generates a data NAK at the conclusion of a data transfer. The slave is still considered to be addressed. General Call Enable. General call address detection is available only when slave mode is enabled. 0 = General call address matching is not enabled 1 = General call address matching is enabled. Regardless of the selected address length of slave address, a general call slave receive transfer is accepted. All status and interrupt source bits associated with transfers are updated.

TWISLEN

TWIDVAL

TWINAK

TWIGCE

Slave Address Register (TWISADDR) The TWI slave mode address register (shown in Figure A-149) holds the slave mode address, which is the valid address that the slave-enabled TWI controller responds to. The TWI controller compares this value with the received address during the addressing phase of a transfer.

ADSP-214xx SHARC Processor Hardware Reference

A-251

Peripherals Routed Through the DPI

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

15 14 13 12

11 10

SADDR (60) Slave Mode Address

Figure A-149. TWISADDR Register (RW) Slave Status Register (TWISSTAT) During and at the conclusion of slave mode transfers, the TWI slave mode status register (shown in Figure A-150) holds information on the current transfer. Generally slave mode status bits are not associated with the generation of interrupts. Master mode operation does not affect the slave mode status bits.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

TWIGC General Call

TWISDIR Slave Transfer Direction

Figure A-150. TWISSTAT Register Table A-134. TWISSTAT Register Bit Descriptions (RO)
Bit 0 Name TWISIDR Description Slave Transfer Direction. This bit self clears if slave mode is disabled (SEN = 0) 0 = At the time of addressing, the transfer direction was determined to be slave receive. 1 = At the time of addressing, the transfer direction was determined to be slave transmit. General Call. This bit self clears if slave mode is disabled (SEN = 0) 0 = At the time of addressing, the address was not determined to be a general call. 1 = At the time of addressing, the address was determined to be a general call.

TWIGC

A-252

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

FIFO Control Register (TWIFIFOCTL) The TWI FIFO control register (shown in Figure A-151 and described in Table A-135) affects only the FIFO and is not tied in any way with master or slave mode operation.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

TWIBHD Buffer Hang Disable TWIRXINT2 Receive Buffer Interrupt Length TWITXINT2 Transmit Buffer Interrupt Length

TWITXFLUSH Transmit Buffer Flush TWIRXFLUSH Receive Buffer Flush

Figure A-151. TWIFIFOCTL Register Table A-135. TWIFIFOCTL Register Bit Descriptions (RW)
Bit 0 Name TWITXFLUSH Description Transmit Buffer Flush. 0 = Normal operation of the transmit buffer and its status bits 1 = Flush the contents of the transmit buffer and update the status to indicate the buffer is empty. This state is held until this bit is cleared. During an active transmit, the transmit buffer in this state responds as if the transmit buffer is empty. Receive Buffer Flush. 0 = Normal operation of the receive buffer and its status bits. 1 = Flush the contents of the receive buffer and update the status to indicate the buffer is empty. This state is held until this bit is cleared. During an active receive the receive buffer in this state responds to the receive logic as if it is full.

TWIRXFLUSH

ADSP-214xx SHARC Processor Hardware Reference

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Table A-135. TWIFIFOCTL Register Bit Descriptions (RW) (Contd)

Bit 2 Name TWITXINT2 Description Transmit Buffer Interrupt Length. Determines the rate at which transmit buffer interrupts are generated. Interrupts may be generated with each byte transmitted or after two bytes are transmitted. 0 = An interrupt (TWITXINT) is set when TWITXS indicates one or two bytes in the FIFO are empty (01 or 00). 1 = An interrupt (TWITXINT) is set when TWITXS indicates two bytes in the FIFO are empty (00). Receive Buffer Interrupt Length. Determines the rate at which receive buffer interrupts are generated. Interrupts may be generated with each byte received or after two bytes are received. 0 = An interrupt (TWIRXINT) is set when TWIRXS indicates one or two bytes in the FIFO are full (01 or 11). 1 = An interrupt (TWIRXINT) is set when TWIRXS indicates two bytes in the FIFO are full (11). Receive Buffer Hang Disable. 0 = Core read of FIFO happens only when Rx FIFO has a valid byte. Write of FIFO happens only when Tx FIFO has at least one empty space. 1 = Core read/write happens irrespective of FIFO status

TWIRXINT2

TWIBHD

FIFO Status Register (TWIFIFOSTAT) The fields in the TWI FIFO status register (shown in Figure A-152 and described in Table A-136) indicate the state of the FIFO buffers receive and transmit contents. The FIFO buffers do not discriminate between master data and slave data. By using the status and control bits provided, the FIFO can be managed to allow simultaneous master and slave operation.

A-254

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Register Reference

31 30

29 28 27 26 25 24

23 22

21 20 19 18 17 16

15 14 13 12

11 10

TWIRXS (32) Receive FIFO Status

TWITXS (10) Transmit FIFO Status

Figure A-152. TWIFIFOSTAT Register Table A-136. TWIFIFOSTAT Register Bit Descriptions (RO)
Bit 10 Name TWITXS Description Transfer FIFO Status. These read-only bits indicate the number of valid data bytes in the FIFO buffer. The status is updated with each FIFO buffer write using the peripheral data bus or read access by the transmit shift register. Simultaneous accesses are allowed. 00 = FIFO is empty. Either a single- or double-byte peripheral write of the FIFO goes through immediately. 01 = FIFO contains one byte of data. A single byte peripheral write of the FIFO goes through immediately. A double-byte peripheral write waits until the FIFO is empty 11 = FIFO is full and contains two bytes of data. 10 = Reserved Receive FIFO Status. These read-only bits indicate the number of valid data bytes in the receive FIFO buffer. The status is updated with each FIFO buffer read using the peripheral data bus or write access by the receive shift register. Simultaneous accesses are allowed. 00 = FIFO is empty. 01 = FIFO contains one byte of data. A single-byte peripheral read of the FIFO goes through immediately. A double-byte peripheral read waits until the FIFO is full. 11 = FIFO is full and contains two bytes of data. Either a single- or double-byte peripheral read of the FIFO is allowed. 10 = Reserved

32

TWIRXS

ADSP-214xx SHARC Processor Hardware Reference

A-255

Peripherals Routed Through the DPI

Interrupt Latch Register (TWIIRPTL) The TWI interrupt source register (shown in Figure A-153 and described in Table A-137) contains information about functional areas requiring servicing. Many of the bits serve as an indicator to further read and service various status registers. After servicing the interrupt source associated with a bit, the user must clear that interrupt source bit. All bits are sticky and RW1C.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

TWIRXINT Receive FIFO Service TWITXINT Transmit FIFO Service TWIMERR Master Transfer Error TWIMCOM Master Transfer Complete

TWISINIT Slave Transfer Initiated TWISCOMP Slave Transfer Complete TWISERR Slave Transfer Error TWISOVF Slave Overflow

Figure A-153. TWIIRPTL Register Table A-137. TWIIRPTL Register Bit Descriptions (RW1C)
Bit 0 Name TWISINIT Description Slave Transfer Initiated. 0 = A transfer is not in progress. An address match has not occurred since the last time this bit was cleared. 1 = The slave has detected an address match and a transfer has been initiated. Slave Transfer Complete. 0 = The completion of a transfer not detected 1 = The transfer is complete and either a stop, or a restart was detected.

TWISCOMP

A-256

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-137. TWIIRPTL Register Bit Descriptions (RW1C) (Contd)

Bit 2 Name TWISERR Description Slave Transfer Error. 0 = No errors detected 1 = An error has occurred. A restart or stop condition has occurred during the data receive phase of a transfer. Slave Overflow. 0 = No overflow detected 1 = The slave transfer complete (TWISCOMP) was set at the time a subsequent transfer has acknowledged an address phase. The transfer continues, however, it may be difficult to delineate data of one transfer from another. Master Transfer Complete. 0 = The completion of a transfer not detected 1 = The initiated master transfer is complete. In the absence of a repeat start, the bus is released. Master Transfer Error. 0 = No errors detected 1 = A master error occurred. The conditions surrounding the error are indicated by the master status register (TWIMSTAT). Transmit FIFO Service. If XMTINTLEN2 in the TWIFIFOCTL register is 0, this bit is set each time the TWITXS field in the TWIFIFOSTAT register is updated to either 01 or 00. If XMTINTLEN is 1, this bit is set each time TWITXS is updated to 00. 1 = The transmit FIFO buffer has one or two 8-bit locations available to be written. 0 = FIFO does not require servicing or TWITXS field has not changed since this bit was last cleared. Receive FIFO Service. If RCVINTLEN2 in the TWIFIFOCTL register is 0, this bit is set each time the TWIRXS field in the TWIFIFOSTAT register is updated to either 01 or 11. If RCVINTLEN2 is 1, this bit is set each time TWIRXS is updated to or 11. 0 = No errors have been detected. 1 = The FIFO does not require servicing or the TWIRXS field has not changed since this bit was last cleared.

TWISOVF

TWIMCOM

TWIMERR

TWITXINT

TWIRXINT

ADSP-214xx SHARC Processor Hardware Reference

A-257

Peripherals Routed Through the DPI

Interrupt Enable Register (TWIIMASK) The TWI interrupt mask register (shown in Figure A-154 and described in Table A-138) enables interrupt sources to assert the interrupt output. Each enable bit corresponds with one interrupt latch bit in the TWI interrupt latch register (TWIIRPTL). Reading and writing the TWIIMASK register does not affect the contents of the TWIIRPTL register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

TWIRXINT Receive FIFO Service Interrupt Enable TWITXINT Transmit FIFO Service Interrupt Enable TWIMERR Master Transfer Complete Interrupt Enable TWIMCOM Master Transfer Complete Interrupt Enable

TWISINIT Slave Transfer Initiate Interrupt Enable TWISCOMP Slave Transfer Complete Interrupt Enable TWISERR Slave Transfer Error Interrupt Enable TWISOVF Slave Overflow Interrupt Enable

Figure A-154. TWIIMASK Register Table A-138. TWIIMASK Register Bit Descriptions (RW)
Bit 0 Name TWISINIT Description Slave Transfer Initiate Interrupt Enable. 0 = The corresponding interrupt source is prevented from asserting the interrupt output. 1 = The corresponding interrupt source asserts the interrupt output. Slave Transfer Complete Interrupt. 0 = The corresponding interrupt source is prevented from asserting the interrupt output. 1 = The corresponding interrupt source asserts the interrupt output. Slave Transfer Error Interrupt. 0 = The corresponding interrupt source is prevented from asserting the interrupt output. 1 = The corresponding interrupt source asserts the interrupt output.

TWISCOMP

TWISERR

A-258

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-138. TWIIMASK Register Bit Descriptions (RW) (Contd)

Bit 3 Name TWISOVF Description Slave Overflow Interrupt Enable. 0 = The corresponding interrupt source is prevented from asserting the interrupt output. 1 = The corresponding interrupt source asserts the interrupt output. Master Transfer Complete Interrupt Enable. 0 = The corresponding interrupt source is prevented from asserting the interrupt output. 1 = The corresponding interrupt source asserts the interrupt output. Master Transfer Error Interrupt Enable. 0 = The corresponding interrupt source is prevented from asserting the interrupt output. 1 = The corresponding interrupt source asserts the interrupt output. Transmit FIFO Service Interrupt Enable. 0 = The corresponding interrupt source is prevented from asserting the interrupt output. 1 = The corresponding interrupt source asserts the interrupt output. Receive FIFO Service Interrupt Enable. 0 = The corresponding interrupt source is prevented from asserting the interrupt output. 1 = The corresponding interrupt source asserts the interrupt output.

TWIMCOM

TWIMERR

TWITXINT

TWIRXINT

ADSP-214xx SHARC Processor Hardware Reference

A-259

Peripherals Routed Through the DPI

Peripheral Timer Registers

The timer peripheral module provides general-purpose timer functionality. It consists of three identical timer units. Each timer has memory-mapped registers. They are described in the following sections. Read-Modify-Write Timer Control Register For the timer global control register, the traditional read-modify-write operations to disable a timer have changed. The action is to directly write which simplifies timer enable/disable and can be accomplished with fewer instructions. Example: Instead of:
ustat3=dm(TMCTL); bit set ustat3 TIM1DIS; dm(TMCTL)=ustat3; /* Timer Control Register */ /* disables timer 1 */

Use:
ustat3 = TIM1DIS; dm(TMCTL)=ustat3;

Writes to the enable and disable bit-pair for a timer works as follows. = 0, TIMxEN = 0 No action TIMxDIS = 0, TIMxEN = 1 Enable the timer TIMxDIS = 1, TIMxEN = x Disable the timer
TIMxDIS

For reads, the interpretation is as follows.

TIM1DIS TIM1DIS

= 0, TIMxEN = 0 Timer is disabled = 1, TIMxEN = 1 Timer is enabled

Any other read combination is not possible. Reading the TMxCTL register returns the enable status on both the enable and disable bits.

A-260

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Timer Control Registers (TMxCTL) All timer clocks are gated off when the specific timers configuration register is set to zero at system reset or subsequently reset by user programs. These registers are shown in Figure A-155.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

IRQEN Interrupt Enable PRDCNT Period Count

TIMODE (10) Timer Mode PULSE Pulse Edge Select

Figure A-155. TMxCTL Register Table A-139. TMxCTL Register Bit Descriptions (RW)
Bit 10 Name TIMODE Description Timer Mode. 00 = Reset 01 = PWM_OUT mode (TIMODEPWM) 10 = WDTH_CAP mode (TIMODEW) 11 = EXT_CLK mode (TIMODEEXT) Pulse Edge Select. 1 = Positive active pulse 0 = Negative active pulse Period Count. 1 = Count to end of period 0 = Count to end of width Interrupt Enable. 1 = Enable 0 = Disable

PULSE

PRDCNT

IRQEN

ADSP-214xx SHARC Processor Hardware Reference

A-261

Peripherals Routed Through the DPI

Timer Status Register (TMSTAT) The global status register TMSTAT is shown in Figure A-156. Status bits are sticky and require a RW1C operation. During a status register read access, all reserved or unused bits return a zero. Each timer generates a unique processor interrupt request signal, TIMxIRQ. A common status register latches these interrupts. Interrupt bits are sticky and must be cleared to assure that the interrupt is not reissued. Each timer is provided with its own sticky status register TIMxEN bit. To enable or disable an individual timer, the TIMxEN bit is set or cleared. For example, writing a one to bit 8 sets the TIM0EN bit; writing a one to bit 9 clears it. Writing a one to both bit 8 and bit 9 clears TIM0EN. Reading the status register returns the TIM0EN state on both bit 8 and bit 9. The remaining TIMxEN bits operate similarly.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12

11 10

TIM1DIS Timer 1 Disable TIM1EN Timer 1 Enable TIM0DIS Timer 0 Disable TIM0EN Timer 0 Enable

TIM0IRQ Timer 0 Interrupt TIM1IRQ Timer 1 Interrupt TIM0OVF Timer 0 Counter Overflow Error TIM1OVF Timer 1 Counter Overflow Error

Figure A-156. TMSTAT Register Table A-140. TMSTAT Register Bit Descriptions (RW)
Bit 0 (RW1C) 1 (RW1C) Name TIM0IRQ Timer 0 Interrupt Latch TIM1IRQ Timer 1 Interrupt Latch Description Also an output Also an output

A-262

ADSP-214xx SHARC Processor Hardware Reference

Register Reference

Table A-140. TMSTAT Register Bit Descriptions (RW) (Contd)

Bit 32 4 (RO) 5 (RO) 76 8 9 (RW1C) 10 10 Name Reserved TIM0OVF Timer 0 Overflow/Error TIM1OVF Timer 1 Overflow/Error Reserved TIM0EN Timer 0 Enable TIM0DIS Timer 0 Disable TIM1EN Timer 1 Enable TIM1EN Timer 1 Disable Enable timer 0 Disable timer 0 Enable timer 1 Enable timer 1 Also an output Also an output Description

ADSP-214xx SHARC Processor Hardware Reference

A-263

Peripherals Routed Through the DPI

A-264

ADSP-214xx SHARC Processor Hardware Reference

B REGISTER LISTING

This section lists all available memory mapped IOP registers including the address and reset values. Power Management and Miscellaneous Registers
Register Mnemonic Address Description Reset

Power Management Register PMCTL PMCTL1 Miscellaneous Registers SYSCTL RUNRSTCTL REVPID ROMID 0x30024 0x2100 0x30026 0x20FF System Control Running Reset Control Silicon revision and processor Identification register ROM Identification 0x0 0x0 Hardware dependent Hardware dependent 0x2000 0x2001 Power Management Control Power Management Control 1 Hardware dependent 0

External Port Registers

Register Mnemonic External Port Register EPCTL 0x1801 External Port Global Control 0xF0 Address Description Reset

Asynchronous Memory Interface Registers AMICTL0 AMICTL1 0x1804 0x1805 AMI Control Register for Bank 1 AMI Control Register for Bank 2 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-1

Register Mnemonic AMICTL2 AMICTL3 AMISTAT

Address 0x1806 0x1807 0x180A

Description AMI Control Register for Bank 3 AMI Control Register for Bank 4 AMI Status

Reset 0x0 0x0 0x1

External Port Direct Memory Access (DMA) Registers DMAC0 EIEP0 EMEP0 ECEP0 IIEP0 IMEP0 ICEP0 CPEP0 EBEP0 TPEP0 ELEP0 TCEP0 DFEP0 DMAC1 EIEP1 EMEP1 ECEP1 IIEP1 IMEP1 ICEP1 CPEP1 EBEP1 TPEP1 0x180B 0x1820 0x1821 0x1822 0x1823 0x1824 0x1825 0x1826 0x1827 0x1828 0x1829 0x182B 0x182C 0x180C 0x1830 0x1831 0x1832 0x1833 0x1834 0x1835 0x1836 0x1837 0x1838 External Port DMA CH 0 Control External Port CH 0 DMA External Index Address External Port CH 0 DMA External Modifier External Port CH 0 DMA External Count External Port CH 0 DMA Internal Index Address External Port CH 0 DMA Internal Modifier External Port CH 0 DMA Internal Count External Port CH 0 DMA Chain Pointer External Port CH 0 DMA External Base Address External Port CH 0 DMA TAP Pointer External Port CH 0 DMA External Length External Port CH 0 DMA Delay Line TAP Count External Port CH 0 DMA Data FIFO External Port DMA CH 1 Control External Port CH 1 DMA External Index Address External Port CH 1 DMA External Modifier External Port CH 1 DMA External Count External Port CH 1 DMA Internal Index Address External Port CH 1 DMA Internal Modifier External Port CH 1 DMA Internal Count External Port CH 1 DMA Chain Pointer External Port CH 1 DMA External Base Address External Port CH 1 DMA TAP Pointer 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

B-2

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic ELEP1 TCEP1 DFEP1 DDR2 Registers DDR2CTL0 DDR2CTL1 DDR2CTL2 DDR2CTL3 DDR2CTL4 DDR2CTL5 DDR2RRC DDR2STAT0 DDR2STAT1 DDR2PADCTL0 DDR2PADCTL1 DLL0CTL1 DLL0STAT0 DLL1CTL1 DLL1STAT0

Address 0x1839 0x183B 0x183C

Description External Port CH 1 DMA External Length External Port CH 1 DMA Delay Line TAP Count External Port CH 1 DMA Data FIFO

Reset 0x0 0x0 0x0

0x1812 0x1813 0x1814 0x1815 0x1816 0x1817 0x181D 0x181E 0x1840 0x1841 0x1842 0x1851 0x1853 0x1856 0x1858

DDR2 Control 0 DDR2 Control 1 DDR2 Control 2 DDR2 Control 3 DDR2 Control 4 DDR2 Control 5 DDR2 Refresh Rate DDR2 Status 0 DDR2 Status 1 DDR2 Pad Control 0 DDR2 Pad Control 1 DLL0 Control Register 1 DLL0 Status Register 1 DLL1 Control Register 1 DLL1 Status Register 1

0x1800 0018 0x9452 3466 0x422 0x4780 0x8000 0xC000 0x2800614 0x9 0x0 0x200 0000 0x8020 0x0 0x0 0x0 0x0

Shared Memory DDR2 Registers BMAX BCOUNT SYSTAT SDRAM Registers SDCTL SDRRC 0x1800 0x1802 SDRAM Control SDRAM Refresh Count 0x0102000A 0x3081A 0x180D 0x180E 0x180F Bus Maximum Timeout Count Bus Current Timeout Count Shared Memory Status 0x0 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-3

Register Mnemonic SDSTAT0 SDSTAT1

Address 0x1803 0x1843

Description SDRAM Status SDRAM Status

Reset 0x8 0x0

Serial Port Registers

Register Mnemonic Address Global Serial Port Register SPERRSTAT 0x2300 Global SPORT Error Status 0x0 Description Reset

Serial Port Error Control Registers SPERRCTL0 SPERRCTL1 SPERRCTL2 SPERRCTL3 SPERRCTL4 SPERRCTL5 SPERRCTL6 SPERRCTL7 SPCTL0 SPCTLN0 DIV0 SPMCTL0 SP0CS0 SP0CS1 SP0CS2 SP0CS3 SP0CCS0 SP0CCS1 0xC18 0xC19 0x418 0x419 0x818 0x819 0x4818 0x4819 0xC00 0xC1A 0xC02 0xC04 0xC05 0xC06 0xC07 0xC08 0xC0D 0xC0E SPORT0 Error Control SPORT1 Error Control SPORT2 Error Control SPORT3 Error Control SPORT4 Error Control SPORT5 Error Control SPORT6 Error Control SPORT7 Error Control SPORT 0 Control Register SPORT 0 Control Register 2 SPORT 0 Divisor for TX/RX SCLK0 and FS0 SPORT 0 TDM Control Register SPORT 0 TDM Select, CH310 SPORT 0 TDM TX Select, CH6332 SPORT 0 TDM TX Select, CH9564 SPORT 0 TDM TX Select, CH12796 SPORT 0 TDM TX Compand Select, CH310 SPORT 0 TDM TX Compand Select, CH6332 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0000 0000 0x0000 0000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

B-4

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic Address SP0CCS2 SP0CCS3 TXSP0A RXSP0A TXSP0B RXSP0B SPCTL1 SPCTLN1 DIV1 SPMCTL1 SP1CS0 SP1CS1 SP1CS2 SP1CS3 SP1CCS0 SP1CCS1 SP1CCS2 SP1CCS3 IISP0A IMSP0A CSP0A CPSP0A IISP0B IMSP0B CSP0B CPSP0B IISP1A 0xC0F 0xC10 0xC60 0xC61 0xC62 0xC63 0xC01 0xC1B 0xC03 0xC17 0xC09 0xC0A 0xC0B 0xC0C 0xC11 0xC12 0xC13 0xC14 0xC40 0xC41 0xC42 0xC43 0xC44 0xC45 0xC46 0xC47 0xC48

Description SPORT 0 TDM TX Compand Select, CH9564 SPORT 0 TDM TX Compand Select, CH12796 SPORT 0A Transmit Data SPORT 0A Receive Data SPORT 0B Transmit Data SPORT 0B Receive Data SPORT 1 Control Register SPORT 1 Control Register 2 SPORT 1 Divisor for TX/RX SCLK1 and FS1 SPORT 1 TDM Control Register SPORT 1 TDM Select, CH310 SPORT 1 TDM RX Select, CH6332 SPORT 1 TDM RX Select, CH9564 SPORT 1 TDM RX Select, CH12796 SPORT 1 TDM RX Compand Select, CH310 SPORT 1 TDM RX Compand Select, CH6332 SPORT 1 TDM RX Compand Select, CH9564 SPORT 1 TDM RX Compand Select, CH12796 Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0000 0000 0x0000 0000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-5

Register Mnemonic Address IMSP1A CSP1A CPSP1A IISP1B IMSP1B CSP1B CPSP1B TXSP1A RXSP1A TXSP1B RXSP1B SPCTL2 SPCTL3 SPCTLN2 SPCTLN3 DIV2 DIV3 SPMCTL2 SP2CS0 SP2CS1 SP2CS2 SP2CS3 SP3CS0 SP3CS1 SP3CS2 SP3CS3 SP2CCS0 0xC49 0xC4A 0xC4B 0xC4C 0xC4D 0xC4E 0xC4F 0xC64 0xC65 0xC66 0xC67 0x400 0x401 0x41A 0x41B 0x402 0x403 0x404 0x405 0x406 0x407 0x408 0x409 0x40A 0x40B 0x40C 0x40D

Description Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters SPORT 1A Transmit Data SPORT 1A Receive Data SPORT 1B Transmit Data SPORT 1B Receive Data SPORT 2 Control SPORT 3 Control SPORT 2 Control Register 2 SPORT 3 Control Register 2 SPORT 2 Divisor for TX/RX SCLK2 and FS2 SPORT 3 Divisor for TX/RX SCLK3 and FS3 SPORTs 2 TDM Control SPORT 2 TDM TX Select, CH310 SPORT 2 TDM TX Select, CH6332 SPORT 2 TDM TX Select, CH9564 SPORT 2 TDM TX Select, CH12796 SPORT 3 TDM RX Select, CH310 SPORT 3 TDM RX Select, CH6332 SPORT 3 TDM RX Select, CH9564 SPORT 3 TDM RX Select, CH12796 SPORT 2 TDM TX Compand Select, CH310

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

B-6

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic Address SP2CCS1 SP2CCS2 SP2CCS3 SP3CCS0 SP3CCS1 SP3CCS2 SP3CCS3 SPMCTL3 IISP2A IMSP2A CSP2A CPSP2A IISP2B IMSP2B CSP2B CPSP2B IISP3A IMSP3A CSP3A CPSP3A IISP3B IMSP3B CSP3B CPSP3B TXSP2A RXSP2A TXSP2B 0x40E 0x40F 0x410 0x411 0x412 0x413 0x414 0x417 0x440 0x441 0x442 0x443 0x444 0x445 0x446 0x447 0x448 0x449 0x44A 0x44B 0x44C 0x44D 0x44E 0x44F 0x460 0x461 0x462

Description SPORT 2 TDM TX Compand Select, CH6332 SPORT 2 TDM TX Compand Select, CH9564 SPORT 2 TDM TX Compand Select, CH12796 SPORT 3 TDM RX Compand Select, CH310 SPORT 3 TDM RX Compand Select, CH6332 SPORT 3 TDM RX Compand Select, CH9564 SPORT 3 TDM RX Compand Select, CH12796 SPORT 3 TDM Control Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters SPORT 2A Transmit Data SPORT 2A Receive Data SPORT 2B Transmit Data

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-7

Register Mnemonic Address RXSP2B TXSP3A RXSP3A TXSP3B RXSP3B SPCTL4 SPCTL5 SPCTLN4 SPCTLN5 DIV4 DIV5 SPMCTL4 SP4CS0 SP4CS1 SP4CS2 SP4CS3 SP5CS0 SP5CS1 SP5CS2 SP5CS3 SP4CCS0 SP4CCS1 SP4CCS2 SP4CCS3 SP5CCS0 SP5CCS1 SP5CCS2 0x463 0x464 0x465 0x466 0x467 0x800 0x801 0x81A 0x819 0x802 0x803 0x804 0x805 0x806 0x807 0x808 0x809 0x80A 0x80B 0x80C 0x80D 0x80E 0x80F 0x810 0x811 0x812 0x813

Description SPORT 2B Receive Data SPORT 3A Transmit Data SPORT 3A Receive Data SPORT 3B Transmit Data SPORT 3B Receive Data SPORT 4 Control SPORT 5 Control SPORT 4 Control Register 2 SPORT 5 Control Register 2 SPORT 4 Divisor for TX/RX SCLK4 and FS4 SPORT 5 Divisor for TX/RX SCLK5 and FS5 SPORT 4 TDM Control SPORT 4 TDM TX Select, CH310 SPORT 4 TDM TX Select, CH6332 SPORT 4 TDM TX Select, CH9564 SPORT 4 TDM TX Select, CH12796 SPORT 5 TDM RX Select, CH310 SPORT 5 TDM RX Select, CH6332 SPORT 5 TDM RX Select, CH9564 SPORT 5 TDM RX Select, CH12796 SPORT 4 TDM TX Compand Select, CH310 SPORT 4 TDM TX Compand Select, CH6332 SPORT 4 TDM TX Compand Select, CH9564 SPORT 4 TDM TX Compand Select, CH12796 SPORT 5 TDM RX Compand Select, CH310 SPORT 5 TDM RX Compand Select, CH6332 SPORT 5 TDM RX Compand Select, CH9564

Reset 0x0 0x0 0x0 0x0 0x0 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

B-8

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic Address SP5CCS3 SPMCTL5 IISP4A IMSP4A CSP4A CPSP4A IISP4B IMSP4B CSP4B CPSP4B IISP5A IMSP5A CSP5A CPSP5A IISP5B IMSP5B CSP5B CPSP5B TXSP4A RXSP4A TXSP4B RXSP4B TXSP5A RXSP5A TXSP5B 0x814 0x817 0x840 0x841 0x842 0x843 0x844 0x845 0x846 0x847 0x848 0x849 0x84A 0x84B 0x84C 0x84D 0x84E 0x84F 0x860 0x861 0x862 0x863 0x864 0x865 0x866

Description SPORT 5 TDM RX Compand Select, CH12796 SPORT 5 TDM Control Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters SPORT 4A Transmit Data SPORT 4A Receive Data SPORT 4B Transmit Data SPORT 4B Receive Data SPORT 5A Transmit Data SPORT 5A Receive Data SPORT 5B Transmit Data

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-9

Register Mnemonic Address RXSP5B SPCTL6 SPCTL7 SPCTLN6 SPCTLN7 DIV6 DIV7 SPMCTL6 SP6CS0 SP6CS1 SP6CS2 SP6CS3 SP7CS0 SP7CS1 SP7CS2 SP7CS3 SP6CCS0 SP6CCS1 SP6CCS2 SP6CCS3 SP7CCS0 SP7CCS1 SP7CCS2 SP7CCS3 SPMCTL7 IISP6A IMSP6A 0x867 0x4800 0x4801 0x481A 0x481B 0x4802 0x4803 0x4804 0x4805 0x4806 0x4807 0x4808 0x4809 0x480A 0x480B 0x480C 0x480D 0x480E 0x480F 0x4810 0x4811 0x4812 0x4813 0x4814 0x4817 0x4840 0x4841

Description SPORT 5B Receive Data SPORT 6 Control SPORT 7 Control SPORT 6 Control Register 2 SPORT 7 Control Register 2 SPORT 6 Divisor for TX/RX SCLK6 and FS6 SPORT 7 Divisor for TX/RX SCLK7 and FS7 SPORT 6 TDM Control SPORT 6 TDM TX Select, CH310 SPORT 6 TDM TX Select, CH6332 SPORT 6 TDM TX Select, CH9564 SPORT 6 TDM TX Select, CH12796 SPORT 7 TDM RX Select, CH310 SPORT 7 TDM RX Select, CH6332 SPORT 7 TDM RX Select, CH9564 SPORT 7 TDM RX Select, CH12796 SPORT 6 TDM TX Compand Select, CH310 SPORT 6 TDM TX Compand Select, CH6332 SPORT 6 TDM TX Compand Select, CH9564 SPORT 6 TDM TX Compand Select, CH12796 SPORT 7 TDM RX Compand Select, CH310 SPORT 7 TDM RX Compand Select, CH6332 SPORT 7 TDM RX Compand Select, CH9564 SPORT 7 TDM RX Compand Select, CH12796 SPORT 7 TDM Control Internal Memory DMA Address Internal Memory DMA Access Modifier

Reset 0x0 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

B-10

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic Address CSP6A CPSP6A IISP6B IMSP6B CSP6B CPSP6B IISP7A IMSP7A CSP7A CPSP7A IISP7B IMSP7B CSP7B CPSP7B TXSP6A RXSP6A TXSP6B RXSP6B TXSP7A RXSP7A TXSP7B RXSP7B 0x4842 0x4843 0x4844 0x4845 0x4846 0x4847 0x4848 0x4849 0x484A 0x484B 0x484C 0x484D 0x484E 0x484F 0x4860 0x4861 0x4862 0x4863 0x4864 0x4865 0x4866 0x4867

Description Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters SPORT 6A Transmit Data SPORT 6A Receive Data SPORT 6B Transmit Data SPORT 6B Receive Data SPORT 7A Transmit Data SPORT 7A Receive Data SPORT 7B Transmit Data SPORT 7B Receive Data

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-11

Serial Peripheral Interface Registers

Register Mnemonic SPI Registers SPICTL SPIFLG SPISTAT TXSPI RXSPI SPIBAUD RXSPI_SHADOW IISPI IMSPI CSPI CPSPI SPIDMAC SPIB Registers SPICTLB SPIFLGB SPISTATB TXSPIB RXSPIB SPIBAUDB RXSPIB_SHADOW IISPIB IMSPIB CSPIB 0x2800 0x2801 0x2802 0x2803 0x2804 0x2805 0x2806 0x2880 0x2881 0x2882 SPIB Control SPIB Flag SPIB Status SPIB Transmit Data SPIB Receive Data SPIB Baud Setup SPIB Receive Data Shadow Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining 0x0400 0x0F00 0x01 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1000 0x1001 0x1002 0x1003 0x1004 0x1005 0x1006 0x1080 0x1081 0x1082 0x1083 0x1084 SPI Control SPI Flag SPI Status SPI Transmit Data SPI Receive Data SPI Baud Setup SPI Receive Data Shadow Internal Memory DMA Address Internal Memory DMA Access Modifier Contains Number of DMA Transfers Remaining Points to Next DMA Parameters SPI DMA Control 0x0400 0x0F80 0x01 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Address Description Reset

B-12

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic CPSPIB SPIDMACB

Address 0x2883 0x2884

Description Points to Next DMA Parameters SPIB DMA Control

Reset 0x0 0x0

Peripheral Timer Registers

Register Mnemonic TMSTAT TM0STAT TM0CTL TM0CNT TM0PRD TM0W TM1STAT TM1CTL TM1CNT TM1PRD TM1W Address 0x1400 0x1400 0x1401 0x1402 0x1403 0x1404 0x1408 0x1409 0x140A 0x140B 0x140C Description GP Timer 0/1 Status GP Timer 0 Status (Alias of TMSTAT) GP Timer 0 Control GP Timer 0 Count GP Timer 0 Period GP Timer 0 Width GP Timer 1 Status (Alias of TMSTAT) GP Timer 1 Control GP Timer 1 Count GP Timer 1 Period GP Timer 1 Width Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

DAI/DPI Signal Routing Control Registers

Register Mnemonic Address Description Reset

SRU DAI Routing Registers SRU_CLK0 SRU_CLK1 SRU_CLK2 SRU_CLK3 SRU_CLK4 SRU_CLK5 0x2430 0x2431 0x2432 0x2433 0x2434 0x2435 SRU Clock Control 0 SRU Clock Control 1 SRU Clock Control 2 SRU Clock Control 3 SRU Clock Control 4 SRU Clock Control 5 0x2526 30C2 0x3DEF 7BDE 0x3DEF 7BDE 0x3DEF 7BDE 0x3DEF 7BDE 0x3DEF 7BDE

ADSP-214xx SHARC Processor Hardware Reference

B-13

Register Mnemonic SRU_DAT0 SRU_DAT1 SRU_DAT2 SRU_DAT3 SRU_DAT4 SRU_DAT5 SRU_DAT6 SRU_FS0 SRU_FS1 SRU_FS2 SRU_FS3 SRU_FS4 SRU_PIN0 SRU_PIN1 SRU_PIN2 SRU_PIN3 SRU_PIN4 SRU_EXT_MISCA SRU_EXT_MISCB SRU_PBEN0 SRU_PBEN1 SRU_PBEN2 SRU_PBEN3 SRU_CLK_SHREG SRU_DAT_SHREG

Address 0x2440 0x2441 0x2442 0x2443 0x2444 0x2445 0x2446 0x2450 0x2451 0x2452 0x2453 0x2454 0x2460 0x2461 0x2462 0x2463 0x2464 0x2470 0x2471 0x2478 0x2479 0x247A 0x247B 0x24F1 0x24F2

Description SRU Data Control 0 SRU Data Control 1 SRU Data Control 2 SRU Data Control 3 SRU Data Control 4 SRU Data Control 5 SRU Data Control 6 SRU FS Control 0 SRU FS Control 1 SRU FS Control 2 SRU FS Control 3 SRU FS Control 4 SRU Pin Control 0 SRU Pin Control 1 SRU Pin Control 2 SRU Pin Control 3 SRU Pin Control 4 SRU External Misc. A Control SRU External Misc. B Control SRU Pin Enable 0 SRU Pin Enable 1 SRU Pin Enable 2 SRU Pin Enable 3 SRU Shift Register Clock Control SRU Shift Register Data Control

Reset 0x0814 4040 0x0F38 B289 0x0000 0450 0x0 0x0 0x0 0x00FB EFBE 0x2736 B4E3 0x3DEF 7BDE 0x3DEF 7BDE 0x1EF7BDE 0x3DE 0x04C8 0A94 0x04E8 4B96 0x0366 8C98 0x03A7 14A3 0x0569 4F9E 0x3DEF 7BDE 0x3DEF 7BDE 0x0E24 82CA 0x1348 D30F 0x1A55 45D6 0x1D71 F79B 0x0000 0272 0x0000 0012

SRU2 DPI Routing Registers SRU2_INPUT0 0x1C00 SRU2 Input Signal Routing 0 0x0002 1462

B-14

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic SRU2_INPUT1 SRU2_INPUT2 SRU2_INPUT3 SRU2_INPUT4 SRU2_INPUT5 SRU2_PIN0 SRU2_PIN1 SRU2_PIN2 SRU2_PBEN0 SRU2_PBEN1 SRU2_PBEN2 DAI Interrupt Registers DAI_IMASK_FE DAI_IMASK_RE DAI_IRPTL_PRI DAI_IRPTL_H DAI_IRPTL_L DAI_IRPTL_HS DAI_IRPTL_LS DPI Interrupt Registers DPI_IRPTL DPI_IRPTL_SH DPI_IMASK_FE DPI_IMASK_RE

Address 0x1C01 0x1C02 0x1C03 0x1C04 0x1C05 0x1C10 0x1C11 0x1C12 0x1C20 0x1C21 0x1C22

Description SRU2 Input Signal Routing 1 SRU2 Input Signal Routing 2 SRU2 Input Signal Routing 3 SRU2 Input Signal Routing 4 SRU2 Input Signal Routing 5 SRU2 Pin Assignment 0 SRU2 Pin Assignment 1 SRU2 Pin Assignment 2 SRU2 Pin Enable 0 SRU2 Pin Enable 1 SRU2 Pin Enable 2

Reset 0x1AC0 2C00 0x0 0x0 0x0 0x0 0x1801 7556 0x004D B699 0x0045 0000 0x0D00 C28B 0x0021 03CE 0x0018 5964

0x2480 0x2481 0x2484 0x2488 0x2489 0x248C 0x248D

DAI Falling Edge Interrupt Mask DAI Rising Edge Interrupt Mask DAI Interrupt Latch Priority DAI High Priority Interrupt Latch DAI Low Priority Interrupt Latch Shadow DAI High Priority Interrupt Latch Shadow DAI Low Priority Interrupt Latch

0x0 0x0 0x0 0x0 0x0 0x0 0x0

0x1C32 0x1C33 0x1C34 0x1C35

DPI Interrupt Latch DPI Shadow Priority Latch DPI Falling Edge Interrupt Mask DPI Rising Edge Interrupt Mask

0x0 0x0 0x0 0x0

DAI/DPI Pin Buffer Status Registers DAI_PIN_STAT DPI_PIN_STAT 0x24B9 0x1C31 DAI Pin Status DPI Pin Status 0x000F FFFF 0x0000 3FFF

ADSP-214xx SHARC Processor Hardware Reference

B-15

DAI/DPI Interrupt Control Registers

Register Mnemonic DAI Interrupt Registers DAI_IMASK_FE DAI_IMASK_RE DAI_IRPTL_PRI DAI_IRPTL_H DAI_IRPTL_L DAI_IRPTL_HS DAI_IRPTL_LS DPI Interrupt Registers DPI_IRPTL DPI_IRPTL_SH DPI_IMASK_FE DPI_IMASK_RE 0x1C32 0x1C33 0x1C34 0x1C35 DPI Interrupt Latch DPI Shadow Priority Latch DPI Falling Edge Interrupt Mask DPI Rising Edge Interrupt Mask 0x0 0x0 0x0 0x0 0x2480 0x2481 0x2484 0x2488 0x2489 0x248C 0x248D DAI Falling Edge Interrupt Mask DAI Rising Edge Interrupt Mask DAI Interrupt Latch Priority DAI High Priority Interrupt Latch DAI Low Priority Interrupt Latch Shadow DAI High Priority Interrupt Latch Shadow DAI Low Priority Interrupt Latch 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Address Description Reset

Programmable Interrupt Priority Control Registers

Register Mnemonic PICR0 PICR1 PICR2 PICR3 Address 0x2200 0x2201 0x2202 0x2203 Description Programmable Interrupt Priority Control 0 Programmable Interrupt Priority Control 1 Programmable Interrupt Priority Control 2 Programmable Interrupt Priority Control 3 Reset 0x0A41 8820 0x16A4 A0E6 0x2307 B9AC 0x0000 0012

B-16

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

DAI/DPI Pin Buffer Status Registers

Register Mnemonic Address Description Reset

DAI/DPI Pin Buffer Status Registers DAI_PIN_STAT DPI_PIN_STAT 0x24B9 0x1C31 DAI Pin Status DPI Pin Status 0x000F FFFF 0x0000 3FFF

Input Data Port Registers

Register Mnemonic IDP_CTL0 IDP_CTL1 IDP_CTL2 IDP_PP_CTL IDP_FIFO DAI_STAT0 DAI_STAT1 Address 0x24B0 0x24B2 0x24B3 0x24B1 0x24D0 0x24B8 0x24BA Description IDP Control 0 IDP Control 1 IDP Control 2 Parallel Data Acquisition Port Control Register IDP FIFO Packing Mode IDP Status IDP Status Reset 0x0 0x0000 FFFF 0x0 0x0 0x0 0x0 0x0

Input Data Port DMA Parameter Registers IDP_DMA_I0 IDP_DMA_I1 IDP_DMA_I2 IDP_DMA_I3 IDP_DMA_I4 IDP_DMA_I5 IDP_DMA_I6 IDP_DMA_I7 IDP_DMA_I0A IDP_DMA_I1A IDP_DMA_I2A 0x2400 0x2401 0x2402 0x2403 0x2404 0x2405 0x2406 0x2407 0x2408 0x2409 0x240A IDP DMA Channel 0 Index IDP DMA Channel 1 Index IDP DMA Channel 2 Index IDP DMA Channel 3 Index IDP DMA Channel 4 Index IDP DMA Channel 5 Index IDP DMA Channel 6 Index IDP DMA Channel 7 Index IDP DMA Channel 0 Index A for Ping Pong DMA IDP DMA Channel 1 Index A for Ping Pong DMA IDP DMA Channel 2 Index A for Ping Pong DMA 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-17

Register Mnemonic IDP_DMA_I3A IDP_DMA_I4A IDP_DMA_I5A IDP_DMA_I6A IDP_DMA_I7A IDP_DMA_I0B IDP_DMA_I1B IDP_DMA_I2B IDP_DMA_I3B IDP_DMA_I4B IDP_DMA_I5B IDP_DMA_I6B IDP_DMA_I7B IDP_DMA_M0 IDP_DMA_M1 IDP_DMA_M2 IDP_DMA_M3 IDP_DMA_M4 IDP_DMA_M5 IDP_DMA_M6 IDP_DMA_M7 IDP_DMA_C0 IDP_DMA_C1 IDP_DMA_C2 IDP_DMA_C3 IDP_DMA_C4 IDP_DMA_C5

Address 0x240B 0x240C 0x240D 0x240E 0x240F 0x2418 0x2419 0x241A 0x241B 0x241C 0x241D 0x241E 0x241F 0x2410 0x2411 0x2412 0x2413 0x2414 0x2415 0x2416 0x2417 0x2420 0x2421 0x2422 0x2423 0x2424 0x2425

Description IDP DMA Channel 3 Index A for Ping Pong DMA IDP DMA Channel 4 Index A for Ping Pong DMA IDP DMA Channel 5 Index A for Ping Pong DMA IDP DMA Channel 6 Index A for Ping Pong DMA IDP DMA Channel 7 Index A for Ping Pong DMA IDP DMA Channel 0 Index B for Ping Pong DMA IDP DMA Channel 1 Index B for Ping Pong DMA IDP DMA Channel 2 Index B for Ping Pong DMA IDP DMA Channel 3 Index B for Ping Pong DMA IDP DMA Channel 4 Index B for Ping Pong DMA IDP DMA Channel 5 Index B for Ping Pong DMA IDP DMA Channel 6 Index B for Ping Pong DMA IDP DMA Channel 7 Index B for Ping Pong DMA IDP DMA Channel 0 Modify IDP DMA Channel 1 Modify IDP DMA Channel 2 Modify IDP DMA Channel 3 Modify IDP DMA Channel 4 Modify IDP DMA Channel 5 Modify IDP DMA Channel 6 Modify IDP DMA Channel 7 Modify IDP DMA Channel 0 Count IDP DMA Channel 1 Count IDP DMA Channel 2 Count IDP DMA Channel 3 Count IDP DMA Channel 4 Count IDP DMA Channel 5 Count

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

B-18

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic IDP_DMA_C6 IDP_DMA_C7 IDP_DMA_PC0 IDP_DMA_PC1 IDP_DMA_PC2 IDP_DMA_PC3 IDP_DMA_PC4 IDP_DMA_PC5 IDP_DMA_PC6 IDP_DMA_PC7

Address 0x2426 0x2427 0x2428 0x2429 0x242A 0x242B 0x242C 0x242D 0x242E 0x242F

Description IDP DMA Channel 6 Count IDP DMA Channel 7 Count IDP DMA Channel 0 Ping Pong Count IDP DMA Channel 1 Ping Pong Count IDP DMA Channel 2 Ping Pong Count IDP DMA Channel 3 Ping Pong Count IDP DMA Channel 4 Ping Pong Count IDP DMA Channel 5 Ping Pong Count IDP DMA Channel 6 Ping Pong Count IDP DMA Channel 7 Ping Pong Count

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Precision Clock Generator Registers

Register Mnemonic PCG_CTLA0 PCG_CTLA1 PCG_CTLB0 PCG_CTLB1 PCG_CTLC0 PCG_CTLC1 PCG_CTLD0 PCG_CTLD1 PCG_PW1 PCG_PW2 PCG_SYNC1 PCG_SYNC2 Address 0x24C0 0x24C1 0x24C2 0x24C3 0x24C6 0x24C7 0x24C8 0x24C9 0x24C4 0x24CA 0x24C5 0x24CB Description Precision Clock A Control 0 Precision Clock A Control 1 Precision Clock B Control 0 Precision Clock B Control 1 Precision Clock C Control 0 Precision Clock C Control 1 Precision Clock D Control 0 Precision Clock D Control 1 Precision Clock Pulse Width Control 1 Precision Clock Pulse Width Control 2 Precision Clock Frame Sync Synchronization 1 Precision Clock Frame Sync Synchronization 2 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-19

Pulse Width Modulation Registers

Register Mnemonic PWMGCTL PWMGSTAT PWMCTL0 PWMSTAT0 PWMPERIOD0 PWMDT0 PWMA0 PWMB0 PWMSEG0 PWMAL0 PWMBL0 PWMDBG0 PWMPOL0 PWMCTL1 PWMSTAT1 PWMPERIOD1 PWMDT1 PWMA1 PWMB1 PWMSEG1 PWMAL1 PWMBL1 PWMDBG1 PWMPOL1 PWMCTL2 Address 0x3800 0x3801 0x3000 0x3001 0x3002 0x3003 0x3005 0x3006 0x3008 0x300A 0x300B 0x300E 0x300F 0x3010 0x3011 0x3012 0x3013 0x3015 0x3016 0x3018 0x301A 0x301B 0x301E 0x301F 0x3400 Description PWM Global Control PWM Global Status PWM Control 0 PWM Status 0 PWM Period 0 PWM Dead Time 0 PWM Channel A Duty Control 0 PWM Channel B Duty Control 0 PWM Output Enable 0 PWM Channel AL Duty Control 0 PWM Channel BL Duty Control 0 PWM Debug Status 0 PWM Output Polarity Select 0 PWM Control 1 PWM Status 1 PWM Period 1 PWM Dead Time 1 PWM Channel A Duty Control 1 PWM Channel B Duty Control 1 PWM Output Enable 1 PWM Channel AL Duty Control 1 PWM Channel BL Duty Control 1 PWM Debug Status 1 PWM Output Polarity Select 1 PWM Control 2 Reset 0x0 0x0 0x0 0x0009 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x00FF 0x0 0x0009 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x00FF 0x0

B-20

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic PWMSTAT2 PWMPERIOD2 PWMDT2 PWMA2 PWMB2 PWMSEG2 PWMAL2 PWMBL2 PWMDBG2 PWMPOL2 PWMCTL3 PWMSTAT3 PWMPERIOD3 PWMDT3 PWMA3 PWMB3 PWMSEG3 PWMAL3 PWMBL3 PWMDBG3 PWMPOL3

Address 0x3401 0x3402 0x3403 0x3405 0x3406 0x3408 0x340A 0x340B 0x340E 0x340F 0x3410 0x3411 0x3412 0x3413 0x3415 0x3416 0x3418 0x341A 0x341B 0x341E 0x341F

Description PWM Status 2 PWM Period 2 PWM Dead Time 2 PWM Channel A Duty Control 2 PWM Channel B Duty Control 2 PWM Output Enable 2 PWM Channel AL Duty Control 2 PWM Channel BL Duty Control 2 PWM Debug Status 2 PWM Output Polarity Select 2 PWM Control 3 PWM Status 3 PWM Period 3 PWM Dead Time 3 PWM Channel A Duty Control 3 PWM Channel B Duty Control 3 PWM Output Enable 3 PWM Channel AL Duty Control 3 PWM Channel BL Duty Control 3 PWM Debug Status 3 PWM Output Polarity Select 3

Reset 0x0009 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x00FF 0x0 0x0009 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x00FF

Memory-to-Memory DMA Registers

Register Mnemonic MTMCTL IIMTMW Address 0x2C01 0x2C10 Description Memory-to-Memory DMA Control MTM DMA Destination Index Reset 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-21

Register Mnemonic IIMTMR IMMTMW IMMTMR CMTMW CMTMR

Address 0x2C11 0x2C0E 0x2C0F 0x2C16 0x2C17

Description MTM DMA Source Index MTM DMA Destination Modify MTM DMA Source Modify MTM DMA Destination Count MTM DMA Source Count

Reset 0x0 0x0 0x0 0x0 0x0

Hardware Accelerator Registers (FFT/FIR/IIR)

Register Mnemonic FFT Accelerator Registers FFTCTL1 FFTCTL2 FFTMACSTAT FFTDADDR FFTDDATA IIFFT IMFFT ICFFT ILFFT IBFFT CPIFFT OIFFT OMFFT OCFFT OLFFT OBFFT CPOFFT 0x5300 0x530C 0x5302 0x5303 0x5304 0x5310 0x5311 0x5312 0x5313 0x5314 0x5315 0x5318 0x5319 0x531A 0x531B 0x531C 0x531D FFT Global Control Channel Control MAC Status Debug Address Debug Data Input Index Input Modifier Input Count Input Length Input Base Input Chain Pointer Output Index Output Modifier Output Count Output Length Output Base Output Chain Pointer 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Address Description Reset

B-22

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic FFTDMASTAT FFTSHDMASTAT FIR Accelerator Registers FIRCTL1 FIRDMASTAT FIRMACSTAT FIRDEBUGCTL FIRDBGADDR FIRDBGWRDATA FIRDBGRDDATA FIRCTL2 IIFIR IMFIR ICFIR IBFIR OIFIR OMFIR OCFIR OBFIR CIFIR CMFIR CCFIR CPFIR IIR Accelerator Registers IIRCTL1 IIRDMASTAT IIRMACSTAT

Address 0x5320 0x5321

Description DMA Status DMA Shadow Status

Reset 0x0 0x0

0x5000 0x5001 0x5002 0x5004 0x5005 0x5006 0x5007 0x5010 0x5011 0x5012 0x5013 0x5014 0x5015 0x5016 0x5017 0x5018 0x5019 0x501A 0x501B 0x501C

FIR Global Control DMA Status Reg MAC Status Debug Control Debug Address Debug Data Write Debug Data Read Channel Control Input Data Index Input Data Modifier Input Data Count Input Data Base Output Data Index Output Data Modifier Output Data Count Output Data Base Coefficient Index Coefficient Modifier Coefficient Count Chain Pointer

0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

0x5200 0x5201 0x5202

IIR Global Control DMA Status Reg MAC Status

0x0 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-23

Register Mnemonic IIRDEBUGCTL IIRDBGADDR IIRDBGWRDATA_L IIRDBGWRDATA_H IIRDBGRDDATA_L IIRDBGRDDATA_H IIRCTL2 IIIIR IMIIR ICIIR IBIIR OIIIR OMIIR OCIIR OBIIR CIIIR CMIIR CCIIR CPIIR

Address 0x5203 0x5204 0x5205 0x5206 0x5207 0x5208 0x5210 0x5211 0x5212 0x5213 0x5214 0x5215 0x5216 0x5217 0x5218 0x5219 0x521A 0x521B 0x521C

Description Debug Control Debug Address Debug Data Write LS 32 Bits Debug Data Write MS 8 Bits Debug Data Read LS 32 Bits Debug Data Read MS 8 Bits Channel Control Input Data Index Input Data Modifier Input Data Count Input Data Base Output Data Index Output Data Modifier Output Data Count Output Data Base Coefficient Index Coefficient Modifier Coefficient Count Chain Pointer

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

S/PDIF Interface Registers

Register Mnemonic Address Description Reset

S/PDIF Transmit Registers DITCTL 0x24A0 Digital Interface Transmit Control 0x0

S/PDIF Channel Status Registers DITCHANA0 0x24A1 Transmit CH0 Subframe A 0x0

B-24

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic DITCHANA1 DITCHANA2 DITCHANA3 DITCHANA4 DITCHANA5 DITCHANB0 DITCHANB1 DITCHANB2 DITCHANB3 DITCHANB4 DITCHANB5

Address 0x24D4 0x24D5 0x24D6 0x24D7 0x24D8 0x24A2 0x24DA 0x24DB 0x24DC 0x24DD 0x24DE

Description Transmit CH1 Subframe A Transmit CH2 Subframe A Transmit CH3 Subframe A Transmit CH4 Subframe A Transmit CH5 Subframe A Transmit CH0 Subframe B Transmit CH1 Subframe B Transmit CH2 Subframe B Transmit CH3 Subframe B Transmit CH4 Subframe B Transmit CH5 Subframe B

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

S/PDIF User Bit Status Registers DITUSRBITA0 DITUSRBITA1 DITUSRBITA2 DITUSRBITA3 DITUSRBITA4 DITUSRBITA5 DITUSRBITB0 DITUSRBITB1 DITUSRBITB2 DITUSRBITB3 DITUSRBITB4 DITUSRBITB5 DITUSRUPD 0x24E0 0x24E1 0x24E2 0x24E3 0x24E4 0x24E5 0x24E8 0x24E9 0x24EA 0x24EB 0x24EC 0x24ED 0x24EF Transmit User Bit CH0 Subframe A Transmit User Bit CH1 Subframe A Transmit User Bit CH2 Subframe A Transmit User Bit CH3 Subframe A Transmit User Bit CH4 Subframe A Transmit User Bit CH5 Subframe A Transmit User Bit CH0 Subframe B Transmit User Bit CH1 Subframe B Transmit User Bit CH2 Subframe B Transmit User Bit CH3 Subframe B Transmit User Bit CH4 Subframe B Transmit User Bit CH5 Subframe B Transmit User Bit Update 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

S/PDIF Receiver Registers DIRCTL 0x24A8 Receiver Control 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-25

Register Mnemonic DIRSTAT DIRCHANL DIRCHANR

Address 0x24A9 0x24AA 0x24AB

Description Receiver Status Receiver Left Channel Status Receiver Right Channel Status

Reset 0x20 0x0 0x0

Sample Rate Converter Registers

Register Mnemonic SRCCTL0 SRCCTL1 SRCMUTE SRCRAT0 SRCRAT1 Address 0x2490 0x2491 0x2492 0x2498 0x2499 Description SRC0 Control SRC1 Control SRC Mute SRC0 Output to Input Ratio SRC1 Output to Input Ratio Reset 0x0 0x0 0x0 0x8000 8000 0x8000 8000

UART Registers
Register Mnemonic UART0THR UART0RBR UART0DLL UART0IER UART0DLH UART0IIR UART0LCR UART0MODE UART0LSR UART0SCR UART0IIRSH UART0LSRSH Address 0x3C00 0x3C00 0x3C00 0x3C01 0x3C01 0x3C02 0x3C03 0x3C04 0x3C05 0x3C07 0x3C09 0x3C0A Description UART0 Transmit Hold UART0 Receive Buffer UART0 Divisor Latch Low UART0 Interrupt Enable UART0 Divisor Latch High UART0 Interrupt ID UART0 Line Control UART0 Mode UART0 Line Status UART0 Scratch UART0 Interrupt ID Shadow UART0 Line Status Shadow Reset 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x60 Undefined 0x1 0x60

B-26

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic RXI_UAC0 RXM_UAC0 RXC_UAC0 RXCP_UAC0 TXI_UAC0 TXM_UAC0 TXC_UAC0 TXCP_UAC0 UART0TXCTL UART0RXCTL UART0TXSTAT UART0RXSTAT

Address 0x3E00 0x3E01 0x3E02 0x3E03 0x3F00 0x3F01 0x3F02 0x3F03 0x3F04 0x3E04 0x3F05 0x3E05

Description UART Receive Index Register UART Receive Modifier Register UART Receive Count Register UART Receive Chain Pointer Register UART Transmit Index Register UART Transmit Modifier Register UART Receive Count Register UART Transmit Chain Pointer Register UART0 DMA TX Control UART0 DMA RX Control UART0 DMA TX Status UART0 DMA RX Status

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Two Wire Interface Registers

Register Mnemonic TWIDIV TWIMITR TWISCTL TWISSTAT TWISADDR TWIMCTL TWIMSTAT TWIMADDR TWIIRPTL TWIIMASK TWIFIFOCTL Address 0x4400 0x4404 0x4408 0x440C 0x4410 0x4414 0x4418 0x441C 0x4420 0x4424 0x4428 Description SCL Clock Divider Master Internal Time Reference Slave Mode Control Slave Mode Status Slave Mode Address Master Mode Control Master Mode Status Master Mode Address Interrupt Latch Interrupt Mask FIFO Control Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-27

Register Mnemonic TWIFIFOSTAT TXTWI 8 TXTWI 16 RXTWI8 RXTWI16

Address 0x442C 0x4480 0x4484 0x4488 0x448C

Description FIFO Status 8-bit FIFO Transmit 16-bit FIFO Transmit 8-Bit FIFO Receive 16-Bit FIFO Receive

Reset 0x0 0x0 0x0 0x0 0x0

Link Port Registers

Register Mnemonic LCTL0 LSTAT0 TXLB0 RXLB0 TXLB0_IN_SHADOW TXLB0_OUT_SHADOW RXLB0_IN_SHADOW RXLB0_OUT_SHADOW LSTAT0_SHADOW IILB0 IMLB0 CLB0 CPLB0 LCTL1 LSTAT1 TXLB1 RXLB1 TXLB1_IN_ SHADOW Address 0x4C00 0x4C01 0x4C08 0x4C09 0x4C0D 0x4C0C 0x4C0B 0x4C0A 0x4C03 0x4C18 0x4C19 0x4C1A 0x4C1B 0x4C20 0x4C21 0x4C28 0x4C29 0x4C2D Description Link Port 0 Control Link Port 0 Status Link Port 0 TX Buffer Link Port 0 RX Buffer Link Port 0 Shadow TX Buffer Link Port 0 Shadow Output Pack Link Port 0 Shadow Input RX Buffer Link Port 0 Shadow Output Pack Link Port 0 Shadow Status Link Port 0 Internal Index Link Port 0 Internal Modifier Link Port 0 Internal Count Link Port 0 Chain Pointer Link Port 1 Control Link Port 1 Status Link Port 1 TX Buffer Link Port 1 RX Buffer Link Port 1 Shadow Input TX Buffer Reset 0x0 0x0 Undefined Undefined 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Undefined Undefined 0x0

B-28

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic TXLB1_OUT_SHADOW RXLB1_IN_SHADOW RXLB1_OUT_SHADOW LSTAT1_SHADOW IILB1 IMLB1 CLB1 CPLB1

Address 0x4C2C 0x4C2B 0x4C2A 0x4C23 0x4C38 0x4C39 0x4C3A 0x4C3B

Description Link Port 1 Shadow Output Pack Link Port 1 Shadow Input RX Buffer Link Port 1 Shadow Output Pack Link Port 1 Shadow Status Link Port 1 Internal Index Link Port 1 Internal Modifier Link Port 1 Internal Count Link Port 1 Chain Pointer

Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Shift Register Register

Register Mnemonic SR_CTL Address 0x24F0 Description Shift Register Control Reset 0x0

Watchdog Timer Registers

Register Mnemonic WDTCTL WDTCURCNT WDTTRIP WDTCNT WDTSTATUS WDTUNLOCK WDTCLKSEL Address 0x5400 0x5401 0x5402 0x5403 0x5404 0x5405 0x5408 Description Watchdog Timer Control Watchdog Timer Current Count Watchdog Timer Trip Watchdog Timer Count Watchdog Timer Status Watchdog Timer Unlock Watchdog Timer Clock Select Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-29

Real-Time Clock Registers

Register Mnemonic RTC_CLOCK RTC_ALARM RTC_CTL RTC_STAT RTC_STPWTCH RTC_INIT RTC_INITSTAT Address 0x4CA0 0x4CA1 0x4CA2 0x4CA3 0x4CA4 0x4CA6 0x4CA7 Description Real-Time Clock Clock (1Hz Register) Real-Time Clock Alarm (1Hz Register) Real-Time Clock Control Real-Time Clock Status Real-Time Clock Stopwatch (1Hz Register) Real-Time Clock Initialization (1Hz Register) Real-Time Clock Initialization Status Reset Undefined Undefined 0x0 0x0 Undefined 0x0 Undefined

Media Local Bus Registers

Register Mnemonic MLB_DCCR MLB_SSCR MLB_SDCR MLB_SMCR MLB_VCCR MLB_SBCR MLB_ABCR MLB_CBCR MLB_CICR MLB_CECR0 MLB_CSCR0 MLB_CCBCR0 MLB_CNBCR0 MLB_LCBCR0 MLB_CECR1 Address 0x4100 0x4101 0x4102 0x4103 0x4107 0x4108 0x4109 0x410A 0x410C 0x4110 0x4111 0x4112 0x4113 0x41A0 0x4114 Description MLB Device Control MLB System Status Configuration System Data Configuration System Interrupt Mask Version Control Config (Contains the IP Version) Synchronous Base Address Asynchronous Base Address Control Base Address Channel Interrupt Status Channel 0 Control Channel 0 Status Channel 0 Current Buffer (RX Buffer in I/O Mode) Channel 0 Next Buffer (TX Buffer in I/O Mode) Channel 0 Local Channel Buffer Control Channel 1 Control Reset 0x0 0x0 0x0 0x00000060 0x202 0x0 0x0 0x0 0x0 0x0 0x8000 0000 0x0 0x0 0x0040 0000 0x0

B-30

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic MLB_CSCR1 MLB_CCBCR1 MLB_CNBCR1 MLB_LCBCR1 MLB_CECR2 MLB_CSCR2 MLB_CCBCR2 MLB_CNBCR2 MLB_LCBCR2 MLB_CECR3 MLB_CSCR3 MLB_CCBCR3 MLB_CNBCR3 MLB_LCBCR3 MLB_CECR4 MLB_CSCR4 MLB_CCBCR4 MLB_CNBCR4 MLB_LCBCR4 MLB_CECR5 MLB_CSCR5 MLB_CCBCR5 MLB_CNBCR5 MLB_LCBCR5 MLB_CECR6 MLB_CSCR6 MLB_CCBCR6

Address 0x4115 0x4116 0x4117 0x41A1 0x4118 0x4119 0x411A 0x411B 0x41A2 0x411C 0x411D 0x411E 0x411F 0x41A3 0x4120 0x4121 0x4122 0x4123 0x41A4 0x4124 0x4125 0x4126 0x4127 0x41A5 0x4128 0x4129 0x412A

Description Channel 1 Status Channel 1 Current Buffer (RX Buffer in I/O Mode) Channel 1 Next Buffer (TX Buffer in I/O Mode) Channel 1 Local Channel Buffer Control Channel 2 Control Channel 2 Status Channel 2 Current Buffer (RX Buffer in I/O Mode) Channel 2 Next Buffer (TX Buffer in I/O Mode) Channel 2 Local Channel Buffer Control Channel 3 Control Channel 3 Status Channel 3 Current Buffer (RX Buffer in I/O Mode) Channel 3 Next Buffer (TX Buffer in I/O Mode) Channel 3 Local Channel Buffer Control Channel 4 Control Channel 4 Status Channel 4 Current Buffer (RX Buffer in I/O Mode) Channel 4 Next Buffer (TX Buffer in I/O Mode) Channel 4 Local Channel Buffer Control Channel 5 Control Channel 5 Status Channel 5 Current Buffer (RX Buffer in I/O Mode) Channel 5 Next Buffer (TX Buffer in I/O Mode) Channel 5 Local Channel Buffer Control Channel 6 Control Channel 6 Status Channel 6 Current Buffer (RX Buffer in I/O Mode)

Reset 0x8000 0000 0x0 0x0 0x0040 0001 0x0 0x8000 0000 0x0 0x0 0x0040 0002 0x0 0x8000 0000 0x0 0x0 0x0040 0003 0x0 0x8000 0000 0x0 0x0 0x0040 0004 0x0 0x8000 0000 0x0 0x0 0x0040 0005 0x0 0x8000 0000 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-31

Register Mnemonic MLB_CNBCR6 MLB_LCBCR6 MLB_CECR7 MLB_CSCR7 MLB_CCBCR7 MLB_CNBCR7 MLB_LCBCR7 MLB_CECR8 MLB_CSCR8 MLB_CCBCR8 MLB_CNBCR8 MLB_LCBCR8 MLB_CECR9 MLB_CSCR9 MLB_CCBCR9 MLB_CNBCR9 MLB_LCBCR9 MLB_CECR10 MLB_CSCR10 MLB_CCBCR10 MLB_CNBCR10 MLB_LCBCR10 MLB_CECR11 MLB_CSCR11 MLB_CCBCR11 MLB_CNBCR11 MLB_LCBCR11

Address 0x412B 0x41A6 0x412C 0x412D 0x412E 0x412F 0x41A7 0x4130 0x4131 0x4132 0x4133 0x41A8 0x4134 0x4135 0x4136 0x4137 0x41A9 0x4138 0x4139 0x413A 0x413B 0x41AA 0x413C 0x413D 0x413E 0x413F 0x41AB

Description Channel 6 Next Buffer (TX Buffer in I/O Mode) Channel 6 Local Channel Buffer Control Channel 7 Control Channel 7 Status Channel 7 Current Buffer (RX Buffer in I/O Mode) Channel 7 Next Buffer (TX Buffer in I/O Mode) Channel 7 Local Channel Buffer Control Channel 8 Control Channel 8 Status Channel 8 Current Buffer (RX Buffer in I/O Mode) Channel 8 Next Buffer (TX Buffer in I/O Mode) Channel 8 Local Channel Buffer Control Channel 9 Control Channel 9 Status Channel 9 Current Buffer (RX Buffer in I/O Mode) Channel 9 Next Buffer (TX Buffer in I/O Mode) Channel 9 Local Channel Buffer Control Channel 10 Control Channel 10 Status

Reset 0x0 0x0040 0006 0x0 0x8000 0000 0x0 0x0 0x0040 0007 0x0 0x8000 0000 0x0 0x0 0x0040 0008 0x0 0x8000 0000 0x0 0x0 0x0040 0009 0x0 0x8000 0000

Channel 10 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 10 Next Buffer (TX Buffer in I/O Mode) Channel 10 Local Channel Buffer Control Channel 11 Control Channel 11 Status 0x0 0x0040 000A 0x0 0x8000 0000

Channel 11 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 11 Next Buffer (TX Buffer in I/O Mode) Channel 11 Local Channel Buffer Control 0x0 0x0040 000B

B-32

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic MLB_CECR12 MLB_CSCR12 MLB_CCBCR12 MLB_CNBCR12 MLB_LCBCR12 MLB_CECR13 MLB_CSCR13 MLB_CCBCR13 MLB_CNBCR13 MLB_LCBCR13 MLB_CECR14 MLB_CSCR14 MLB_CCBCR14 MLB_CNBCR14 MLB_LCBCR14 MLB_CECR15 MLB_CSCR15 MLB_CCBCR15 MLB_CNBCR15 MLB_LCBCR15 MLB_CECR16 MLB_CSCR16 MLB_CCBCR16 MLB_CNBCR16 MLB_LCBCR16 MLB_CECR17 MLB_CSCR17

Address 0x4140 0x4141 0x4142 0x4143 0x41AC 0x4144 0x4145 0x4146 0x4147 0x41AD 0x4148 0x4149 0x414A 0x414B 0x41AE 0x414C 0x414D 0x414E 0x414F 0x41AF 0x4150 0x4151 0x4152 0x4153 0x41B0 0x4154 0x4155

Description Channel 12 Control Channel 12 Status

Reset 0x0 0x8000 0000

Channel 12 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 12 Next Buffer (TX Buffer in I/O Mode) Channel 12 Local Channel Buffer Control Channel 13 Control Channel 13 Status 0x0 0x0040 000C 0x0 0x8000 0000

Channel 13 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 13 Next Buffer (TX Buffer in I/O Mode) Channel 13 Local Channel Buffer Control Channel 14 Control Channel 14 Status 0x0 0x0040 000D 0x0 0x8000 0000

Channel 14 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 14 Next Buffer (TX Buffer in I/O Mode) Channel 14 Local Channel Buffer Control Channel 15 Control Channel 15 Status 0x0 0x0040 000E 0x0 0x8000 0000

Channel 15 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 15 Next Buffer (TX Buffer in I/O Mode) Channel 15 Local Channel Buffer Control Channel 16 Control Channel 16 Status 0x0 0x0040 000F 0x0 0x8000 0000

Channel 16 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 16 Next Buffer (TX Buffer in I/O Mode) Channel 16 Local Channel Buffer Control Channel 17 Control Channel 17 Status 0x0 0x0040 0010 0x0 0x8000 0000

ADSP-214xx SHARC Processor Hardware Reference

B-33

Register Mnemonic MLB_CCBCR17 MLB_CNBCR17 MLB_LCBCR17 MLB_CECR18 MLB_CSCR18 MLB_CCBCR18 MLB_CNBCR18 MLB_LCBCR18 MLB_CECR19 MLB_CSCR19 MLB_CCBCR19 MLB_CNBCR19 MLB_LCBCR19 MLB_CECR20 MLB_CSCR20 MLB_CCBCR20 MLB_CNBCR20 MLB_LCBCR20 MLB_CECR21 MLB_CSCR21 MLB_CCBCR21 MLB_CNBCR21 MLB_LCBCR21 MLB_CECR22 MLB_CSCR22 MLB_CCBCR22 MLB_CNBCR22

Address 0x4156 0x4157 0x41B1 0x4158 0x4159 0x415A 0x415B 0x41B2 0x415C 0x415D 0x415E 0x415F 0x41B3 0x4160 0x4161 0x4162 0x4163 0x41B4 0x4164 0x4165 0x4166 0x4167 0x41B5 0x4168 0x4169 0x416A 0x416B

Description

Reset

Channel 17 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 17 Next Buffer (TX Buffer in I/O Mode) Channel 17 Local Channel Buffer Control Channel 18 Control Channel 18 Status 0x0 0x0040 0011 0x0 0x8000 0000

Channel 18 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 18 Next Buffer (TX Buffer in I/O Mode) Channel 18 Local Channel Buffer Control Channel 19 Control Channel 19 Status 0x0 0x0040 0012 0x0 0x8000 0000

Channel 19 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 19 Next Buffer (TX Buffer in I/O Mode) Channel 19 Local Channel Buffer Control Channel 20 Control Channel 20 Status 0x0 0x0040 0013 0x0 0x8000 0000

Channel 20 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 20 Next Buffer (TX Buffer in I/O Mode) Channel 20 Local Channel Buffer Control Channel 21 Control Channel 21 Status 0x0 0x0040 0014 0x0 0x8000 0000

Channel 21 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 21 Next Buffer (TX Buffer in I/O Mode) Channel 21 Local Channel Buffer Control Channel 22 Control Channel 22 Status 0x0 0x0040 0015 0x0 0x8000 0000

Channel 22 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 22 Next Buffer (TX Buffer in I/O Mode) 0x0

B-34

ADSP-214xx SHARC Processor Hardware Reference

Register Listing

Register Mnemonic MLB_LCBCR22 MLB_CECR23 MLB_CSCR23 MLB_CCBCR23 MLB_CNBCR23 MLB_LCBCR23 MLB_CECR24 MLB_CSCR24 MLB_CCBCR24 MLB_CNBCR24 MLB_LCBCR24 MLB_CECR25 MLB_CSCR25 MLB_CCBCR25 MLB_CNBCR25 MLB_LCBCR25 MLB_CECR26 MLB_CSCR26 MLB_CCBCR26 MLB_CNBCR26 MLB_LCBCR26 MLB_CECR27 MLB_CSCR27 MLB_CCBCR27 MLB_CNBCR27 MLB_LCBCR27 MLB_CECR28

Address 0x41B6 0x416C 0x416D 0x416E 0x416F 0x41B7 0x4170 0x4171 0x4172 0x4173 0x41B8 0x4174 0x4175 0x4176 0x4177 0x41B9 0x4178 0x4179 0x417A 0x417B 0x41BA 0x417C 0x417D 0x417E 0x417F 0x41BB 0x4180

Description Channel 22 Local Channel Buffer Control Channel 23 Control Channel 23 Status

Reset 0x0040 0016 0x0 0x8000 0000

Channel 23 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 23 Next Buffer (TX Buffer in I/O Mode) Channel 23 Local Channel Buffer Control Channel 24 Control Channel 24 Status 0x0 0x0040 0017 0x0 0x8000 0000

Channel 24 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 24 Next Buffer (TX Buffer in I/O Mode) Channel 24 Local Channel Buffer Control Channel 25 Control Channel 25 Status 0x0 0x0040 0018 0x0 0x8000 0000

Channel 25 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 25 Next Buffer (TX Buffer in I/O Mode) Channel 25 Local Channel Buffer Control Channel 26 Control Channel 26 Status 0x0 0x0040 0019 0x0 0x8000 0000

Channel 26 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 26 Next Buffer (TX Buffer in I/O Mode) Channel 26 Local Channel Buffer Control Channel 27 Control Channel 27 Status 0x0 0x0040 001A 0x0 0x8000 0000

Channel 27 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 27 Next Buffer (TX Buffer in I/O Mode) Channel 27 Local Channel Buffer Control Channel 28 Control 0x0 0x0040 001B 0x0

ADSP-214xx SHARC Processor Hardware Reference

B-35

Register Mnemonic MLB_CSCR28 MLB_CCBCR28 MLB_CNBCR28 MLB_LCBCR28 MLB_CECR29 MLB_CSCR29 MLB_CCBCR29 MLB_CNBCR29 MLB_LCBCR29 MLB_CECR30 MLB_CSCR30 MLB_CCBCR30 MLB_CNBCR30 MLB_LCBCR30

Address 0x4181 0x4182 0x4183 0x41BC 0x4184 0x4185 0x4186 0x4187 0x41BD 0x4188 0x4189 0x418A 0x418B 0x41BE

Description Channel 28 Status

Reset 0x8000 0000

Channel 28 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 28 Next Buffer (TX Buffer in I/O Mode) Channel 28 Local Channel Buffer Control Channel 29 Control Channel 29 Status 0x0 0x0040 001C 0x0 0x8000 0000

Channel 29 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 29 Next Buffer (TX Buffer in I/O Mode) Channel 29 Local Channel Buffer Control Channel 30 Control Channel 30 Status 0x0 0x0040 001D 0x0 0x8000 0000

Channel 30 Current Buffer (RX Buffer in I/O Mode) 0x0 Channel 30 Next Buffer (TX Buffer in I/O Mode) Channel 30 Local Channel Buffer Control 0x0 0x0040 001E

B-36

ADSP-214xx SHARC Processor Hardware Reference

C AUDIO FRAME FORMATS

This appendix introduces all the serial timing protocols used for audio inter-chip communications. These formats are listed and their availability in the various peripherals noted in Table C-1. Table C-1. Audio Format Availability
Frame Format Serial I 2S Left-justified Right-justified, 24-bit Right-justified, 20-bit Right-justified, 18-bit Right-justified, 16-bit TDM, 128 channel Yes SPORTs Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes IDP/SIP ASRC Input ASRC Output S/PDIF Tx S/PDIF Rx PCG Yes Yes Yes Yes Yes Yes Yes Yes

ADSP-214xx SHARC Processor Hardware Reference

C-1

Overview

Overview
The following protocols are available in the SHARC processor and are briefly described in this appendix. For complete information on the industry standard protocols, see the specification listings in each section. Standard Serial Mode Left-justified Mode (Sony format) I2S Mode (Sony/Philips format) Time Division Multiplex (TDM) Mode MOST Mode Right-justified Mode S/PDIF (consumer mode) EBU/AES3 (professional mode)

Standard Serial Mode

Most processors allow word lengths of 4 to 32 bits to be transmitted or received through their serial ports. For convenience, most AFE (analog front-end) devices operate with 16-bit word lengths for both data and status transfer between the AFE and processor. The serial ports (SPORTs) of most DSPs are designed for full-duplex operation. They differ from the typical serial interface of micro controllers in that they use a frame sync pulse to indicate the start of the data frame. In the case of full duplex asynchronous transfers, two separate FS pulses are used for transmit and receive. The typical micro controller serial interfaces use the serial clock (SCLK) as an indicator of serial data, meaning that the SCLK is only active when data is valid. The DSP serial interface can operate with a continuous

C-2

ADSP-214xx SHARC Processor Hardware Reference

Audio Frame Formats

SCLK,

in which the frame synchronization (FS) pulse indicates the start of valid data. Serial mode allows a flexible timing which can be used in unframed mode or framed mode. In framed mode the user can select between timing for early and late frame sync. Moreover the word order can be selected as LSB or MSB first.

I 2 S Mode
The Inter-IC-Sound (I2S) bus protocol is a popular 3 wire serial bus standard that was developed to standardize communication across a wide range of peripheral devices. Today the I2S protocol has become the standard method of communicating with consumer and professional audio products. The I2S protocol provides transmission of 2 channel (stereo) Pulse Code Modulation digital data, where each audio sample is sent MSB first. The following list shows applications that use this format. Audio D/A and A/D converters PC multimedia audio controllers Digital audio transmitters and receivers that support serial digital audio transmission standards, such as AES/EBU, S/PDIF, IEC958, CP-340, and CP-1201 Digital audio signal processors Dedicated digital filter chips Sample rate converters diagrams for I S, right-justified Timingfound in the product specific dataand left-justified formats can be sheet.
2

ADSP-214xx SHARC Processor Hardware Reference

C-3

I2S Mode

The I2S bus transmits audio data from 832 bits and control signals over separate lines. The data line carries two multiplexed data channelsthe left channel and the right channel. In I2S mode, if both channels on a SPORT are set up to transmit, then the SPORT transmits left and right I2S channels simultaneously. If both channels on a SPORT are set up to receive, the SPORT receives left and right I2S channels simultaneously. Data is transmitted in MSB-first format. I2S consists, as stated above, of a bit clock, a word select and the data line. The bit clock pulses once for each discrete bit of data on the data lines. The bit clock operates at a frequency which is a multiple of the sample rate. The bit clock frequency multiplier depends on number of bits per channel, times the number of channels. For example, CD Audio with a sample frequency of 44.1 kHz and 32 bits of precision per (2) stereo channels has a bit clock frequency of 2.8224 MHz. The word select clock lets the device know whether channel 1 or channel 2 is currently being sent, since I2S allows two channels to be sent on the same data line. Transitions on the word select clock also serve as a start-of-word indicator. The word clock line pulses once per sample, so while the bit clock runs at some multiple of the sample frequency, the word clock always matches the sample frequency. For a two channel (stereo) system, the word clock is a square wave, with an equal number of bit clock pulses clocking the data to each channel. In a mono system, the word clock pulses one bit clock length to signal the start of the next word, but is no longer be square. Instead, bit clocking transitions occur with the word clock either high or low. Note the major difference between I2S and left/right justified modes is a left MSB data shift by one SCLK cycle in relation to the frame. Standard I2S data is sent from MSB to LSB, starting at the left edge of the word select clock, with one bit clock delay. This allows both the transmitting and receiving devices to ignore the audio precision of the remote device. If the transmitter is sending 32 bits per channel to a device with

C-4

ADSP-214xx SHARC Processor Hardware Reference

Audio Frame Formats

only 24 bits of internal precision, the receiver ignores the extra bits of precision by not storing the bits past the 24th bit. Likewise, if the transmitter is sending 16 bits per channel to a receiving device with 24 bits of precision, the receiver zero-fills the missing bits. This feature makes it possible to mix and match components of varying precision without re configuration.

Left-Justified Mode
Left-justified mode (also known as SONY Format) is a mode where in each frame sync cycle two samples of data are transmitted/receivedone sample on the high segment of the frame sync, the other on the low segment of the frame sync. Prior to development of the I2S standard, many manufacturers used a variety of non-standard stereo modes. Some companies continue to use this mode, which is supported by many of todays audio front-end devices. Programs have control over various attributes of this mode. One attribute is the number of bits (8- to 32-bit word lengths). However, each sample of the pair that occurs on each frame sync must be the same length.

Right-Justified Mode
Right-justified mode is a mode where in each frame sync cycle two samples of data are transmitted/receivedone sample on the high segment of the frame sync, the other on the low segment of the frame sync. Prior to development of the I2S standard, many manufacturers used a variety of non-standard stereo modes. Some companies continue to use this mode, which is supported by many of todays audio front-end devices. Programs have control over various attributes of this mode. One attribute is the number of bits (8- to 32-bit word lengths). However, each sample of the pair that occurs on each frame sync must be the same length.

ADSP-214xx SHARC Processor Hardware Reference

C-5

TDM Mode

TDM Mode
Many applications require multiple I/O channels to implement the desired system functions (such as telephone line and acoustic interfaces). Because most DSPs provide one, or at most two SPORTs, and one of these may be required for interfacing to the host or supervisory processor, it may be impractical, if not impossible, to dedicate a separate SPORT interface to each AFE connection. The solution is to devise a way to connect a series of serial devices to one SPORT. Different converter manufacturers have approached this task in different ways. In essence, though, there are only two choices; either a time division multiplexing (TDM) approach, where each device is active on the SPORT in a particular time slot, or a cascading approach, where all devices are daisy chained together and data is transferred by shifting it through the chain and then following with a latching signal or a serial protocol. Figure C-1 illustrates a pulsed frame clock for the TDM operation.
FSTDM

BCLKTDM

INTERNAL DAC L0

INTERNAL DAC L1

INTERNAL DAC L2

AUXILIARY DAC L0

INTERNAL DAC R0

INTERNAL DAC R1

INTERNAL DAC R2

AUXILIARY DAC R0

BCLKTDM

24-BIT DATA

MSB

MSB 1

MSB 2

MSB 3

MSB 4

LSB +8

LSB +7

LSB +6

LSB +5

LSB +4

LSB +3

LSB +2

LSB +1

LSB

20-BIT DATA

MSB

MSB 1

MSB 2

MSB 3

MSB 4

LSB +4

LSB +3

LSB +2

LSB +1

LSB

16-BIT DATA

MSB

MSB 1

MSB 2

MSB 3

MSB 4

LSB

Figure C-1. TDM Mode Timing

C-6

ADSP-214xx SHARC Processor Hardware Reference

Audio Frame Formats

Packed I 2 S Mode
This mode allows applications to send more than the standard 32 bits per channel normally available through standard I2S mode. Packed mode is implemented using standard TDM mode. Packed mode supports up to 128 channels (as does TDM mode) as well as the maximum of (128 x 32) bits per left or right channel. As shown in Figure C-2, packed I2S waveforms are the same as the wave forms used in TDM mode, except that the frame sync is toggled for every frame, and therefore emulates I 2S mode. In other words, packed I2S mode is a hybrid between TDM and I2S mode.
L/RCLK

BCLK

DATA

SLOT 1 RIGHT 0

SLOT 2 RIGHT 1

SLOT 3 RIGHT 2

BLANK SLOT 4 SCLK

SLOT 4 LEFT 0

SLOT 5 LEFT 1

SLOT 6 LEFT 2

BLANK SLOT 4 SCLK

BCLK

20-BIT DATA

MSB MSB MSB MSB MSB 2 3 4 5 MSB MSB MSB MSB MSB 2 4 4 5

LSB +5

LSB +4

LSB +3

LSB +2

LSB

16-BIT DATA

LSB

Figure C-2. Packed I2S Mode

MOST Mode
A special packed TDM mode is available that allows four channels to be fit into a space of 64-bit clock cycles. This mode is called packed TDM4 mode, or MOST mode. MOST (Media Oriented Systems Transport) is a networking standard intended for interconnecting multimedia components in automobiles and other vehicles. Many integrated circuits intended to interface with a MOST bus use a packed TDM4 data format.

ADSP-214xx SHARC Processor Hardware Reference

C-7

AES/EBU/SPDIF Formats

Figure C-3 shows a word length of 16 bits for packed TDM4 mode. This figure is shown with a negative BCLK polarity, a negative LRCLK polarity, and an MSB delay of 1. The MSB position of the serial data must be delayed by one bit clock from the start of the frame (I2S position).

LRCLKx (1 PERIOD) BCLKx (64 PERIODS) SDATA_INx, SDATA_OUTx (4 CHANNELS) 16 BITS 16 BITS 16 BITS 16 BITS

Figure C-3. Packed TDM4 Mode Timing

AES/EBU/SPDIF Formats
For this section, it is important to be familiar with serial digital application interface standards IEC-60958, EIAJ CP-340, AES3 and AES11. S/PDIF data is transmitted as a stream of 32-bit data words. A data frame consists of 384 words in total, with 192 data words transmitted for the A stereo channel, and 192 data words transmitted for the B stereo channel. The difference between the AES/EBU and S/PDIF protocol is the channel status bit. If the channel status bit is not set, then: 0 = Consumer/professional 1 = Normal/compressed data 2 = Copy prohibit/copy permit 3 = 2 channels/4 channels 4 = n/a 5 = No pre-emphasis/pre-emphasis

C-8

ADSP-214xx SHARC Processor Hardware Reference

Audio Frame Formats

There is one channel status bit in each sub-frame, (comprising of 192 bits per audio block). This translates to 192/8 = 24 bytes available (per audio block). The meaning of the channel status bits are as follows. The biphase encoded AES3 stream is composed of subframes (Figure C-5 on page C-11). Subframes consist of a preamble, four auxiliary bits, a 20-bit audio word, a validity bit, a user bit, a channel status bit, and a parity bit. The preamble indicates the start of the subframe. The four auxiliary bits normally are the least significant bits of the 24-bit audio word when pasted to the 20-bit audio word. In some cases, the auxiliary bits are used to convey some kind of other data indicated by the channel status bits. The validity bit (if cleared, =0) indicates the audio sample word is suitable for direct analog conversion. User data bits may be used in any way desired by the program. The channel status bit conveys information about the status of the channel. Examples of status are length of audio sample words, number of audio channels, sampling frequency, sample address code, alphanumeric source, and destination codes and emphasis. The parity bit is set or cleared to provide an even number of ones and of zeros for time slots 4-31. Each frame in the AES3 stream is made up of two subframes. The first subframe is channel A, and the second subframe is channel B. A block is comprised of 192 frames. The channel status is organized into two 192 bit blocks, one for channel A and one for channel B. Normally, the channel status of channel A is equal to channel B. It is extremely rare that they are ever different. Three different preambles are used to indicate the start of a block and the start of channel A or B. 1. Preamble Z indicates the start of a block and the start of subframe channel A

ADSP-214xx SHARC Processor Hardware Reference

C-9

AES/EBU/SPDIF Formats

2. Preamble X indicates the start of a channel A subframe when not at the start of a block. 3. Preamble Y indicates the start of a channel B subframe. The user bits from the channel A and B subframes are simply strung together. For more information, please refer to the AES3 standard.

CHANNEL 1

CHANNEL 2

CHANNEL 1 SUBFRAME 1

CHANNEL 2 SUBFRAME 2

CHANNEL 1

CHANNEL 2

FRAME 191

FRAME 0 START OF BLOCK

FRAME 1

Figure C-4. S/PDIF Block Structure The data carried by the S/PDIF interface is transmitted serially. In order to identify the assorted bits of information the data stream is divided into frames, each of which are 64 time slots (or 128 unit intervals1) in length (Figure C-4). Since the time slots correspond with the data bits, the frame is often described as being 64 bits in length. A frame is uniquely composed of two subframes. The first subframe normally starts with preamble X. However, the preamble changes to preamble Z once every 192 frames. This defines the block of frames structure used to organize the channel status information. The second subframe always starts with preamble Y.

The unit interval is the minimum time interval between condition changes of a data transmission signal.

C-10

ADSP-214xx SHARC Processor Hardware Reference

Audio Frame Formats

Subframe Format
Each frame consists of two subframes. Figure C-5 shows an illustration of a subframe, which consists of 32 time slots numbered 0 to 31. A subframe is 64 unit intervals in length. The first four time slots of each subframe carry the preamble information. The preamble marks the subframe start and identifies the subframe type. The next 24 time slots carry the audio sample data, which is transmitted in a 24-bit word with the least significant bit (LSB) first. When a 20-bit coding range is sufficient, time slots 8 to 27 carry the audio sample word with the LSB in time slot 8. Time slots 4 to 7 may be used for other applications. Under these circumstances, the bits in time slots 4 to 7 are designated auxiliary sample bits. If the source provides fewer bits than the interface allows (either 20 or 24), the unused LSBs are set to logic 0.

PREAMBLE

USER DATA

CHANNEL STATUS
30

VALIDITY

24-BIT AUDIO WORD

27

28

29

31

PREAMBLE

USER DATA

AUXILIARY SAMPLE BITS

CHANNEL STATUS
30

VALIDITY

20-BIT AUDIO WORD

27

28

29

31

Figure C-5. Subframe Format This functionality is important when using the S/PDIF receiver in common applications where there are multiple types of data to handle. If there are PCM audio data streams as well as encoded data streams, for example a CD audio stream and a DVD audio stream with encoded data, there is a danger of incorrectly passing the encoded data directly to the DAC. This

ADSP-214xx SHARC Processor Hardware Reference

C-11

PARITY

MSB

LSB

PARITY

LSB

MSB

AES/EBU/SPDIF Formats

results in the playing of encoded data as audio, causing loud odd noises to be played. The non-audio flag provides an easy method to mark the this type of data. After the audio sample word, there are four final time slots which carry: 1. Validity bit (time slot 28). The validity bit is logic 0 if the audio sample word is suitable for conversion to an analog audio signal, and logic 1 if it is not. This bit is set if the CHST_BUF_ENABLE bit and the VALIDITY_A (VALIDITY_B for channel 2) bit is set in the SPDIF_TX_CTL register. This bit is also set if the corresponding bit given with the sample is set. 2. User data bit (time slot 29). This bit carries user-specified information that may be used in any way. This bit is set if the corresponding bit given with the left/right sample is set. 3. Channel status bit (time slot 30). The channel status for each audio signal carries information associated with that audio signal, making it possible for different channel status data to be carried in the two subframes of the digital audio signal. Examples of information to be carried in the channel status are: length of audio sample words, number of audio channels, sampling frequency, sample address code, alphanumeric source and destination codes, and emphasis. Channel status information is organized in 192-bit blocks, subdivided into 24 bytes. The first bit of each block is carried in the frame with preamble Z. 4. Parity bit (time slot 31). The parity bit indicates that time slots 4 to 31 inclusive will carry an even number of ones and an even number of zeros (even parity). The parity bit is automatically generated for each subframe and inserted into the encoded data. The two subframes in a frame can be used to transmit two channels of data (channel 1 in subframe 1, channel 2 in subframe 2) with a sample

C-12

ADSP-214xx SHARC Processor Hardware Reference

Audio Frame Formats

rate equal to the frame rate. Alternatively, the two subframes can carry successive samples of the same channel of data, but at a sample rate that is twice the frame rate. This is called single-channel, double-frequency (SCDF). For more information, see Data Output Mode on page 14-12.

Channel Coding
To minimize the direct-current (dc) component on the transmission line, to facilitate clock recovery from the data stream, and to make the interface insensitive to the polarity of connections, time slots 4 to 31 are encoded in bi-phase mark. Each bit to be transmitted is represented by a symbol comprising two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. The second state of the symbol is identical to the first if the bit to be transmitted is logic 0. However, it is different if the bit is logic 1. Figure C-6 shows that the ones in the original data end up with mid cell transitions in the bi-phase mark encoded data, while zeros in the original data do not. Note that the bi-phase mark encoded data always has a transition between bit boundaries.
CLOCK (2 X BIT RATE)

DATA

BI-PHASE MARK DATA

Figure C-6. Bi-phase Mark Encoding

ADSP-214xx SHARC Processor Hardware Reference

C-13

AES/EBU/SPDIF Formats

Preambles
Preambles are specific patterns that provide synchronization and identify the subframes and blocks. To achieve synchronization within one sampling period and to make this process completely reliable, these patterns violate the bi-phase mark code rules, thereby avoiding the possibility of data imitating the preambles. A set of three preambles, shown in Table C-2, are used. These preambles are transmitted in the time allocated to four time slots at the start of each subframe (time slots 0 to 3) and are represented by eight successive states. The first state of the preamble is always different from the second state of the previous symbol (representing the parity bit). Table C-2. Preambles
Preamble X Y Z Preceding state 0 11100010 11100100 11101000 Preceding state 1 00011101 00011011 00010111 Description Subframe 1 Subframe 2 Subframe 1 and block start

Like bi-phase code, the preambles are dc free and provide clock recovery. They differ in at least two states from any valid bi-phase sequence.

C-14

ADSP-214xx SHARC Processor Hardware Reference

INDEX

Numerics
128-channel TDM, 11-3 16-bit DDR2 address map, 4-91 16-bit packed word, 4-25 16-bit SDRAM address map, 4-53 16-bit word, boot packing, 24-19 32/40-bit floating-point mode, IIR accelerator, 7-65 32-bit packed word, 4-25 32-bit word, 4-42, 4-143, 11-42, 11-45, 12-6, 12-10, 12-12, 12-20 32-bit word, boot packing, 24-17, 24-18 32- to 40-bit packing, IIR, 7-66 48-bit word, 4-18 48-bit word, boot packing, 24-15 8-bit boot (SPI), 24-16 8-bit word, 4-16, 12-13 8-bit word, boot packing, 24-20

A
AAC compressed format, 14-17 AC-3 format, 14-17 accelerator See FFT, FIR, IIR accelerator accuracy (PWM), 8-23 acknowledging interrupts, 2-11 active low frame sync select for frame sync (INVFSx) bit, 15-13 active state multichannel receive frame sync select (LMFS) bit, 11-37 AD1855 stereo DAC, use with SPI, 16-10

address AMI, 4-115 AMI address map, 4-16 chain pointer, 3-32 column address width (DDR2CAW), 4-90 core to external memory, 4-52 decoding address bank, 4-52, 4-90 destination, 3-23 instruction execution from external memory, 4-42 logical vs. physical, 4-18, 4-43 map, 16-bit DDR2, 4-91 mapping, DDR2, 4-91 mapping, SDRAM, 4-53 predictive, 4-16 row address width (DDR2RAW), 4-90 SDRAM, 4-32, 4-34 SDRAM read, 4-57 width settings, DDR2, 4-90 addressing 7-bit in TWI, 22-2 AMI, external, 4-16, 4-25, 4-41, 4-87 byte in SDRAM, 4-80 DMA controller, 3-26 general call in TWI, 22-11 internal index, 3-28 IOP, 3-26 mixing instructions and data, 4-21, 4-46 AES audio standard, C-8 alarm clock, RTC, 19-9

ADSP-214xx SHARC Processor Hardware Reference

I-1

Index

AMI See also external port, SDRAM, shared memory ADDR23-0 bits, 4-16, 4-41, 4-87 address map, 4-16 control (AMICTLx) register, A-27 to A-30 data buffer, 4-115 DMA, 4-12 external memory addressing, 4-16, 4-25, 4-41, 4-87 flush buffer, 4-116 memory bank support, 4-16, 4-41, 4-87 non predictive reads, 4-26 predictive reads, 4-26 reading external memory, 4-115 read/write throughput, 4-141 reducing time delay, 4-26 status (AMISTAT) register, A-30, A-31 timing, 4-8 AMI bits ACK pin enable (ACKEN), A-29 buffer flush (FLSH), A-29 bus hold cycle (HC), A-29 bus idle cycle (HC), A-29 most significant word first (MSWF), A-28 packing disable (PKDIS), A-28 predictive read disable (NO_OPT), A-30 read hold cycle (RHC), A-30 wait state enable (WS), A-29 AMIEN, A-28 arbitration, fixed/floating, 3-38 architecture TWI controller, 22-7 array, hold TCB, 3-35 asynchronous memory interface. See AMI asynchronous serial communications (UART), 21-7 audience, intended, lxxi

audio biphase encoded in S/PDIF, 14-3 bi-phase mark encoding, C-14 channel coding, C-13 channel status bits, C-9 data formats, IDP, 12-16 formats, C-1 to C-8 formats, IDP, 12-6 formats, S/PDIF, 14-7, 14-15 frames and subframes, C-9, C-12 modes, C-2 to C-8 non-linear data, S/PDIF, 14-16 PCM, C-12 preambles, C-14 transmission standards, C-3 audio serial timing protocols, C-1 autobaud detection, 21-6 automotive products, 1-2

B
bank DDR2 address mapping, 4-93, 4-94 SDRAM address mapping, 4-50 to 4-55 bank interleaving, external port, 4-89 base registers, 3-9 baud rate, 24-14 setting, 16-33 UART, 21-5 BHD (buffer hang disable) bit, 11-64 bidirectional connections through the signal routing unit, 10-14 bidirectional functions (transmit, receive), 11-3 biphase encoded audio stream, 14-4, 14-14 routing data, 14-5 bi-phase mark encoding, C-14 bits See peripheral specific bits, bits by name or acronym

I-2

ADSP-214xx SHARC Processor Hardware Reference

Index

block diagram FFT accelerator, 7-6 IDP, 12-7 IDP channel 0, 12-9 I/O processor, 3-30 PWM, 8-3 shift register, 18-6 S/PDIF transmitter, 14-8 SPI, 16-9 SPORTs, 11-15 SRC, 13-6 TWI controller, 22-7 block diagrams RTC, 19-10 boolean operator OR, 12-33 booting, 24-7 to 24-27 bootstrap loading, 24-7 DMA use in, 3-23 link port, 24-21 SPI master mode, 24-12 SPI packing, 24-16 SPI slave, 24-15 SPI slave mode, 24-15 bridge, FPGA, 5-9 buffer addressing, 3-26 AMI, 4-115 configuring, 3-4 DAI (miscellaneous polarity, 10-29 data, 3-10 data, listed, 3-10 DMA use in, 3-25 error, SPORTs, 11-45 external port, 4-115 external port DMA, 4-116 FFT, 7-15 flush, AMI, 4-116 flush, external port, 4-116 flush, MLB, 9-13

buffer (continued) flush SPI, 16-22 flush SPORT, 11-45 flush TWI, 22-16 IDP, 12-14 to 12-15 link port transmit and receive, 5-14 local buffer threshold, MLB, 9-12 memory-to-memory, 6-4 pack and unpack, AMI, 4-115 shift register, 18-5 SPI, 16-19 to 16-23 SPORT data, 11-1 SPORTs, 11-41 to 11-45 start address for circular, 3-8 tap list, 3-10 TCB allocation, 3-32 TWI, 22-13 to 22-16 UART, 21-9 buffer, pin, 10-9 buffer hang disable (BHD) bit, 11-64, A-163 buffering controller for multiple DDR2s, 4-95 buffering SDRAM reads and writes, 4-57 buses arbitration, 4-105, 4-106 errors in, 4-62, 4-100 external bus data width (BW) bit, A-28 external port, 3-38 hold cycle bit, A-29 I2S and, C-3 idle cycle bit, A-29 I/O address (IOA), 3-26 IO data (IOD), 3-30 master, 4-108 master timeout, 4-112 peripheral, 3-44 shared memory bus arbitration, 4-105 slave, 4-108 synchronization, 4-110

ADSP-214xx SHARC Processor Hardware Reference

I-3

Index

bus lock (BUSLK) bit, 4-113 bus master count (BCNT) register, 4-112 bus master max time-out (BMAX) register, 4-112 bus request BRx signal, 4-108 bus synchronized (BSYN) bit, 4-111 bus transition cycle (BTC), 4-106 bypass as a one-shot (strobe pulse), 15-14

C
cache, throughput, 4-22, 4-47 capacitors bypass, 24-38 decoupling, 24-38 CAS latency bit (SDCL), A-33 cautions and warnings DMA transfers, 3-28 I/O processor, 3-28 SPORTs, 11-44 center-aligned paired PWM double-update mode, 8-10 single-update mode, 8-9 chain assignment, I/O processor, 3-33 chained DMA, 3-24, 3-31, 3-34 chained DMA enable (SCHEN_A and SCHEN_B) bit, A-162 chained DMA sequences, 3-12 chain pointer (CPSPI) registers, SPI, 16-35 chain pointer (CPSPx) registers, SPORTs, 3-13, 11-49 chain pointer (CPx) registers, 3-32 chain pointer registers (general), 3-12 enable (SCHEN_A and SCHEN_B) bit, 11-49 FFT accelerator, 3-19 FIR accelerator, 3-17 IIR accelerator, 3-18 link ports, 3-16

chained DMA (continued) SPI, 3-15 SPORTs, 3-15, 11-49, A-162 UART, 3-16, 21-15 chaining enable bit (CHEN), 3-34 chain insertion mode, SPORT, 11-50 chain pointer registers, 3-8, 3-12 changing SPI configuration, 16-33 channel allocation for DMA, 3-4 arbitration, fixed/floating, 3-38 coding, audio, C-13 defined, 3-3 DMA, 3-24 interrupt, 3-44, 3-47 priority for DMA, 3-30 registers, listed, 3-39, 3-43 status bits, C-9 channel B transmit status register (SPDIF_TX_CHSTB), A-199, A-200 channel selection registers, 11-24 clearing interrupts, latches, 2-12 CLKOUTEN (clockout enable) bit, A-12 clock A source (CLKASOURCE) bit, A-189 clocks and system clocking, 23-2 clock and frame sync frequencies (DIVx) registers, 11-8 clock distribution, 24-35 clock polarity (CLKPL) bit, A-222 clock rising edge select (CKRE) bit, A-160 core clock, 23-6 disabling the clock, 23-6 hardware control, 23-4 IIR, 7-60 internal clock select (ICLK) bit, A-160 MTM DMA, 6-2 output divider, 23-4 peripheral clock, 23-6

I-4

ADSP-214xx SHARC Processor Hardware Reference

Index

clocks and system clocking (continued) PWM, 8-6 restriction on SPORTs, 11-12 RTC, 19-3 SDRAM controller, 4-7 selecting clock ratios, 23-4 shift register, 18-4 software control, 23-4 source select (MSTR) bit, A-160 SPI clock phase select (CPHASE) bit, A-222 SPORTs, 11-9 VCO clock change (runtime), 4-155 VCO encodings, 23-5 coefficient memory, FIR, 7-33 commands auto-refresh, 4-34 bank activate, 4-31 load mode register, 4-30 precharge, 4-31 read/write, 4-32 self-refresh, 4-61, 4-99 compand data in place, 11-4 companding (compressing/expanding), 11-4 companding limitations, SPORTs, 11-25 compatibility, SPORTs models, 11-26 complete single block DMA, 3-45 compute block, FFT, 7-5 conditioning input signals, 24-35 configuring frame sync signals, 11-14 connecting peripherals through DAI, 10-16 connecting signal routing unit, 10-34 connections group A, clock signals, 10-22 group A, DPI, input routing signals, A-207 group B, DPI, pin assignment signals, A-211 group C, DPI, pin enable signals, A-218

continuous mode, See SPORTs, framed and unframed data controller, SDRAM, 4-27 conventions, lxxx core access read optimization, 4-59, 4-97 address mapping, 4-52 data transfers, IDP, 12-16 data transfers, link port, 5-15 data transfers, PDAP, 12-16 data transfers, SPORTs, 11-45 data transfers, UART, 21-13, 21-23 transmit/receive operations, SPI, 16-23 core, multiplexing FLAG pins, 24-28 count (CSPx) DMA registers, 3-7 count (CSPx) registers, 3-28 counters ASRC resolution, 13-14 RTC, 19-6 count (IDP_DMA_Cx) registers, 12-21, 12-22 crosstalk, reducing, 24-39 CSPx (peripheral DMA counter) registers, 3-7, 3-28 customer support, lxxvi

D
DAI buffer polarity, 10-29 clock routing control registers (group A), 10-22 configuration macro, 10-33 connecting peripherals with, 10-16 control registers, clock routing control registers (Group A), A-123 DAI interrupt falling edge (DAI_IRPTL_FE) register, 12-28 DAI interrupt rising edge (DAI_IRPTL_RE) register, 12-28 DAI_IRPTL_H register, 12-24

ADSP-214xx SHARC Processor Hardware Reference

I-5

Index

DAI (continued) DAI_IRPTL_PRI register, 12-28 DAI_PIN_STAT register, A-153 DAI_STAT register, 12-23, A-178, A-180 debugging, 10-39 edge-related interrupts, 10-31 examples, 10-36 interrupt controller registers, A-18 interrupt event masking, 2-10 interrupts, 10-30 interrupt sources, 2-7 latching interrupts, 2-8 loopback routing, 10-39 miscellaneous buffer polarity, 10-29 miscellaneous functions, 10-19 miscellaneous interrupts, 10-30 pin buffer polarity, 10-29 ping-pong DMA status (SRU_PINGx_STAT) register, A-179, A-180 pin status (DAI_PIN_STAT) register, A-153 routing, 10-19 routing, default, 10-24 rules for routing, 10-19 selection group E (miscellaneous signals), A-144 servicing interrupts, 2-10 specifications, 10-1 SPORT SRU signal connections, 11-6 status (DAI_STAT) register, A-178, A-180 system configuration, sample, 10-32 system design, 10-5 system example, 10-38 unused pin example, 10-28 DAI interrupt controller registers, A-18 DAI registers pin status (DAI_PIN_STAT), A-219

data buffer, FIR, 7-33 direction control (SPTRAN) bit, A-163 type select (DTYPE) bit, A-159 data-independent frame sync, 11-37 (DIFS) mode, 11-37 data memory, FFT, 7-6 data type and companding, 11-14 data words single word transfers, 11-45 transferring, 11-23, 11-34 DDR2, 4-63 to 4-104 16-bit address mapping, 4-91 to 4-94 addressing (16-bit, interleaving), 4-93 automated initialization sequence, 4-80 bank address, 4-52, 4-90 buffering controller for multiple devices, 4-95 clocking (ADSP-2146x AMI), 4-7 commands, 4-71 to 4-78 DDR2 DLL description, 4-65 decoding address bank, 4-52, 4-90 delay generation, 4-67 disabling, 4-80 interleaving, 4-88 latency, 4-72, 4-73, 4-157 memory chip select pins (DDR2_CSx), 4-63 resetting, 4-80 throughput, 4-11 width address setting, 4-90 DDR2 bits address mode (ADDRMODE), 4-89 auto refresh (DDR2ORF), A-44, A-61 bank count, 4 or 8 (DDR2BC, A-42, A-58, A-59, A-60 column address width (DDR2CAW), 4-90, A-42 disable access (DIS_DDCTL), A-42

I-6

ADSP-214xx SHARC Processor Hardware Reference

Index

DDR2 bits (continued) disable clock and control (DIS_DDCLK1), A-42 disable DDCKE signal (DIS_DDCKE), A-42 disable SHARC DLL (SH_DLL_DIS), A-42 exit self refresh (SREF_EXIT), A-44 external data path width (X16DE), A-43, A-58, A-59, A-60, A-61, A-62 force auto refresh (FARF), A-44 force DLL calibration (ForceDLLcal), A-43 force EMR2 register write (FEMR2), A-43 force EMR3 register write (FEMR3), A-43 force EMR register write (FEMR), A-44 force MR register write (FLMR), A-44 force precharge (Force PC), A-44 pipeline enable (DDR2BUF), A-44 power-up sequence start (DDR2PSS), A-43 read modify (DDR2MODIFY), A-45 read optimization enable (DDR2OPT), A-45 row address width (DDR2RAW), 4-90, A-43, A-61 self refresh mode (DDR2SRF), A-44 DDR2 registers control (DDR2CTL0), 4-75, 4-88, A-40 control register 2 (DDR2CTL2), A-47 control register 3 (DDR2CTL3), A-49 DLL 0 control 1 (DLL0CTL1), A-58 DLL 1 control 1 (DLL1CTL1), A-59 DLL status (DLLxSTAT0), A-60 pad control 0 (DDR2PADCTL0), A-60 pad control 1 (DDR2PADCTL1), A-61 refresh rate control (DDR2RRC), A-53 status 0 (DDR2STAT0), A-54

DDR2 registers (continued) status 1 (DDR2STAT1), A-56 timing control 1 (DDR2CTL1), A-45 dead time example (PWM), 8-16 debug, 11-43, 11-62, 24-35 DAI use in, 10-39 data buffer use in, 3-12 FIR, 7-58 SPI, 5-22, 16-42 SPORT, 11-63 decimation, FIR, 7-39 de-emphasis mode SRC, 13-15 destination address, 3-23 DIFS (data independent frame sync select) bit, A-161 digital applications interface. See DAI digital loopback mode, See peripheral specific loopback mode DIVEN (PLL divider enable) bit, 23-14, A-9, A-12 divisor, UART, 21-4, A-234 divisor (DIVx) registers, 11-8, 11-13 DIVx (divisor) registers, A-154 DLAB (divisor latch access) bit, A-236 DMA arbitration, 3-44 base registers, 3-9 booting, 3-23 buffer, external port, 4-116 buffer status, SPI, 16-23 chained, FFT, 3-19 chained, FIR, 3-17 chained, IIR, 3-18 chained, link ports, 3-16 chained, SPI, 3-15 chained, SPORT, 3-15 chained, UART, 3-16, 21-15 chained interrupts, 3-46 chaining, 3-24, 3-31 to 3-36

ADSP-214xx SHARC Processor Hardware Reference

I-7

Index

DMA (continued) chaining enable bit (CHEN), 3-34 chain insertion mode, 3-36 chain loading priority, 3-35 chain pointer registers, 3-8, 3-12 channel, buffer registers, listed, 3-39, 3-43 channel, parameter registers, 3-39, 3-43 channel allocation, 3-4 channel paths, 3-25 channel priority, 3-30 channel priority, external port, A-22 channels, 3-3 channel status, 3-29 circular buffered, 3-9, 3-25 configuring in the I/O processor, 3-50 control/status registers, 3-39, 3-43 data buffer, 3-32, 3-39, 3-43 direction change (external port), 3-24 extended parameter registers, 3-9 external port bus priority, A-22 FFT chaining, 3-19 FIFO, PDAP, 12-22 handshake, 3-30 IIR chaining, 3-18 index addresses, 3-28 index registers, 3-4 interrputs, 3-44 to 3-47 loading chain, 3-34 miscellaneous external port parameter registers, 3-10 multichannel (PDAP), 12-22 operation, master mode, 16-35, 16-36 parameter registers, 3-39, 3-43 ping-pong, 3-24 ping-pong, IDP, 12-21 ping-pong enable (IDP_PING) bits, A-175

DMA (continued) program controlled interrupt (PCI) bit, 3-13, 3-15, 11-50, 16-13, 21-22, A-165 read optimization example, 4-60, 4-98 rotating peripheral priority, 3-44 single block complete, 3-45 SPI slave mode, 16-34, 16-35 SPORT chain status bits (DMACHSxy), A-169 SPORT status bit (DMASxy), A-168 standard, IDP, 12-20 standard (non chained), 3-23 switching from receive to transmit mode, 16-39 switching from transmit to receive mode, 16-37 TCB, 3-22 TCB allocation, 3-32 TCB size, 3-32 transfer control block See DMA TCB transfer direction, external port, 3-25 unchained, 3-45 DMA completion access complete, 3-45 internal transfer complete, 3-45 DMACx (external port DMA registers), A-23 DMA example, chain assignment, 3-34 Dolby, DTS audio standards (S/PDIF), 14-13 DPI connections, group A, A-207 to A-208 connections, group B, A-211 to A-213 connections, group C, A-215 to A-217 interrupt controller registers, A-18 interrupt event masking, 2-10 interrupt sources, 2-7 latching interrupts, 2-8

I-8

ADSP-214xx SHARC Processor Hardware Reference

Index

DPI (continued) loopback routing, 10-39 miscellaneous functions, 10-19 miscellaneous interrupts, 10-30 pin assignment (group B) signals, A-211 pin enable (group C) signals, A-215 routing, default, 10-27 servicing interrupts, 2-10 specifications, 10-1 unused pin example, 10-28 DSP, architectural overview, 1-2 DSxEN (SPI device select) bits, 16-35, 16-36, A-231 DTS format, 14-17 DTYPE (data type) bits, A-159 DXS_B, DSX_A (data buffer channel A/B status) bit, A-163, A-164

E
early vs. late frame syncs, 11-35 EBU audio standard, C-8 edge-related interrupts, 10-31 ELSI (enable RX status interrupt) bit, A-240 emergency dead time example, 8-16 enable EXT_CLK mode, 17-15 external cock synchronization, PCG, 15-21 external port (asynchronous memory interface), A-28 multichannel mode in SPORTs, A-167 PCGs, 15-19 peripheral timer, 17-4, 17-21 pin buffer, timer, 17-3 pulse width modulation groups, 8-20 PWM_OUT mode, 17-8 synchronize (counter) bits, PWM, 8-24 WDTH_CAP mode, 17-12

enable receive buffer full interrupt (ERBFI) bit, A-239 enable transmit buffer empty interrupt (ETBEI) bit, A-239 endian format, 16-2, A-159 equation duty cycles in PWM, 8-10 FIR throughput, 7-49 frame sync frequency, 11-10 frame sync pulse (SPORT), 11-10 peripheral timer period, 17-11 pulse width modulation switching frequency, 8-6 SDRAM clock, 4-37 SDRAM refresh rate, 4-36 serial clock frequency, 11-10 serial port clock divisor, 11-10 SPI clock baud rate, A-228 errors internal bus (SDRAM), 4-62, 4-100 SPORT error control register, A-170 TWI master mode, 22-23, 22-24 TWI repeat start, 22-25 TWI slave transfer, 22-11, 22-21 UART baud rate, 21-5 event flags, RTC, 19-18 examples bypass mode (PLL), 23-17 capacitor placement, 24-38 chain assignment, DMA, 3-34 clock post divider, 23-13 DAI, 10-36, 10-38 DAI, unused pins, 10-28 DPI, unused pins, 10-28 edge-aligned PWM, 8-18 external port DMA read, 4-60, 4-98 FIR filter loop, 4-24, 4-49 interrupt assignment, 2-5 interrupt latency, 2-13

ADSP-214xx SHARC Processor Hardware Reference

I-9

Index

examples (continued) multi-bank SDRAM with data packing, 4-39, 4-84 multiple processor system, 4-57, 4-95 pin buffer, 10-9 PWM deadtime, 8-12 PWM emergency dead time, 8-16 PWM switching frequencies, 8-7 read optimization, 4-59, 4-97 reset generator, 24-44 SDRAM clock, 4-36 single processor system, 4-56, 4-95 software based interrupt, 2-5 SPI interface with AD1855 DAC, 16-10 SRU connections, 10-34 to 10-37 SRU to DAI connections, 10-34 timing for a SPORT multichannel transfer, 11-22 token passing, 5-12 VCO, 23-14 examples, timing link port handshake, 5-6 SPI clock, 16-17 SPI transfer protocol, 16-15 SPORT framed vs. unframed data, 11-36 SPORT normal vs. alternate framing, 11-36 execution stalls, bus transition, 4-107 EXT_CLK (external event watchdog) mode, 17-6 extended parameter registers, DMA, 3-9 external event watchdog (EXT_CLK) mode, 17-2, 17-15 external memory access restrictions, 4-165 access timing, 4-6 address bank decoding, 4-52, 4-90 addressing, AMI, 4-16, 4-25, 4-41, 4-87 banks, 4-27, 4-38

external memory (continued) boot-up code for interrupt vector tables, 4-17, 4-42 executing instructions from, 4-42 external physical address, 4-16, 4-41, 4-87 interface, 4-12 most significant word first (MSWF) bit, A-28 packing and unpacking data (PKDIS) bits, A-28 pin descriptions, 4-28, 4-64 reads, 4-115 restrictions, access, 4-165 SDRAM, 4-38 select signals (MSx), 4-38 SPORT data transfers, 11-41 writes, 4-115 external memory DMA transfers, SPORTs, 11-51 external port buffer status, 4-116 bus hold cycle bit, A-29 bus idle cycle bit, A-29 bus priority, A-22 cache throughput, 4-22 channel freezing, 4-11 channel priority, A-22 clock frequencies, 4-7 core address mapping, 4-52 data pin mode select (EPDATA) bits, A-6 DMA bus, 3-38 DMA read optimization, 4-60, 4-98 DMA registers, 3-29, A-23 to A-26 external code throughput, 4-149 external index addressing, 3-29 feature summary, 5-2 flush buffer, 4-116 instruction packing, 4-18, 4-43

I-10

ADSP-214xx SHARC Processor Hardware Reference

Index

external port (continued) multiplexing, 24-30 read hold cycle (RHC) bits, A-30 SPORT bus interface, 11-51 TCB, 3-20 transfer direction, DMA, 3-25 external port bits bank select (BxSD), A-21 bus priority (EPBR), A-22 data enable (DATA), A-23 delay line write pointer write back status (WBS), A-26 DMA chaining enable (CHEN), A-24 DMA chain status (CHS), A-26 DMA circular buffer enable (CBEN), A-25 DMA delay-line enable (DLEN), A-25 DMA direction (TRAN), A-24 DMA enable (DMAEN), A-24 DMA external interface status (EXTS), A-26 DMA FIFO status (DFS), A-26 DMA flush FIFO (DFLSH), 4-123 DMA transfer direction status (DIRS), A-26 DMA transfer status (DMAS), A-26 freeze length core (FRZCR), A-22, A-23 freeze length (FRZDMA), A-22 freeze (NOFRZDMA, NOFRZCR), 4-11 internal DMA complete interrupt (INIRT), 4-123, A-25 on the fly control loading enable (OFCEN), A-25 tap list DMA enable (TLEN), A-25 write back of EPEI after reads/writes (WRBEN), A-25 external port DMA direction change, 3-24

external port registers, A-20 to A-26 AMI control (AMICTLx), A-27 control (EPCTL), 4-157

F
FE, format extension, See SPORTs, word length FFT buffers, 7-15 FFT accelerator, 7-3 to 7-20 block diagram, 7-6 chained DMA, 3-19 chain pointer register (FFTICP), 7-15 circular buffer addressing, 7-16 circular buffer chained DMA, 7-15 compute block, 7-5 data transfer types, 7-14 debug feature and strategy description, 7-28, 7-83 debugging, 7-27, 7-53 enable (ENABLE) bit, 7-7 horizontal, 7-13 H point coefficient buffer, 7-9 idle state, 7-7 interrupts, 7-17, 7-45 interrupt sources, DMA, 7-18 inverse, 7-14 large, 7-26 large, computation, 7-10 memory, coefficients, 7-6 memory, data, 7-6 memory, twiddle coefficients, 7-6 packed and unpacked date, 7-8 packing bits (FFT_CPACKIN, FFT_CPACKOUT), 7-14 processing state, 7-7 programming, 7-26 read state, 7-7 registers, 7-5 repeat (FFT_RPT) bit, 7-7

ADSP-214xx SHARC Processor Hardware Reference

I-11

Index

FFT accelerator (continued) repeat mode, 7-13 reset (FFT_RST) bit, 7-7 reset state, 7-7 small, computation, 7-10 special coefficient buffer, 7-10 special product, 7-11 start (START) bit, 7-7 storing small FFTs, 7-8 TCB structure, 7-18 throughput, 7-79 vertical FFT example, 7-11 V point coefficient buffer, 7-9 write state, 7-7 FIFO see also buffer data packing in IDP, 12-19 IDP, 12-6 IDP modes use, 12-10 SPI, 16-9 SPI DMA, 16-25 to memory data transfer, 12-14 transmit, SPORT, 11-42 FIG, frame ignore, See SPORTs, framed and unframed data FIR channel control register (FIRCTL2), A-82 control register 1 (FIRCTL1), A-80 DMA status register (FIRDMASTAT), A-85 MAC status register (FIRMACSTAT), A-83 FIR accelerator, 7-28 to 7-55 block diagram, 7-31 buffer, data, 7-33 chained DMA, 3-17 coefficient memory, 7-32 debug, 7-58 decimation, 7-39

FIR accelerator (continued) delay line (TAP), 7-32 DMA transfers, 7-43 FIR_UPSAMP bit, 7-40 formats, fixed-point, 7-43 formats, floating-point, 7-41 input sample, 7-33 interpolation, 7-40 MAC unit, 7-32, 7-33 multiply accumulators, 7-32 pre-fetch data, 7-33 registers, 7-29, 7-32 sample ratio (FIR_RATIO) bit, 7-40 single rate operations, 7-39 TAP delay line, 7-33 throughput, 7-79 window size (WINDOW) bit, 7-40 FIR bits channel auto iterate (FIR_CAI), A-80 channel complete interrupt (FIR_CCINTR), A-81 channel number select (FIR_CH321), A-80 DMA enable (FIR_DMAEN), A-80 rounding mode select (FIR_RND), A-81 tap length (TAPLEN), A-82 window size (WINDOW), A-82 FIR filter inner loop, 4-24, 4-49 FLAG pin multiplexing, 24-28 flags flag interrupt mode (IRQxEN) bits, A-6 input/output (FLAGx) pins, 11-15, 16-9 SPORT pins, 11-15 FLAGx pins, 11-15, 16-9 floating-point, 1-1 40-bit, IIR, 7-65 FIR data format, 7-41 FIR multiplier, 7-30 format select bit, IIR (IIR_FORTYBIT), A-89

I-12

ADSP-214xx SHARC Processor Hardware Reference

Index

floating-point (continued) IIR accelerator, 7-63 multipliers and adders, FFT, 7-5 radix-2 complex FFT, 7-3 rounding bit, FIR (FIR_RND), A-81 framed versus unframed data, 11-34 frame sync A source (FSASOURCE) bit, A-189 early vs. late, 11-35 frequencies, 11-8 internal vs. external, 11-36 output, synchronizing, 15-21 PCG B source (FSBSOURCE) bit, 15-14 routing control (SRU_FS0) registers (group C), A-133 signals, configuring, 11-14 frame sync delay (MFD), 11-22 frame sync required (FSR) bit, A-161 FS_BOTH (frame sync both) bit, A-162 FSM, frame synchronization mode, See SPORTs, framed and unframed data FSP, frame synchronization polarity, See SPORTs, framed and unframed data FSR (frame sync required) bit, A-161 full-duplex operation, specifications, 11-13 full-duplex operation, SPORTs, 11-21

hold cycle (external bus) bit, A-29 hold off, processor bus transition, 4-107 hold time inputs, 24-38 recognition of asynchronous input, 24-38 host processor, 24-7 hysteresis on RESET pin, 24-35

I
I2C port. See TWI controller I2S (Tx/Rx on left channel first), 11-29 ICLK (internal clock select) bit, A-160 identifying processor model, silicon revision, 24-34 idle cycle (external bus) bit, A-29 IDP address, DMA, 12-21 address, ping-pong DMA, 12-21 buffer, 3-10, 12-14 buffer flush, 12-15 channel 0 diagram, 12-9 control (IDP_CTL0) register, A-172 control (IDP_CTL1) register, 12-29, A-174, A-176 (DAI) interrupt service routine steps, 12-24 DMA count (IDP_DMA_Cx) register, 12-21, 12-22 DMA index (IDP_DMA_Ix) register, 12-21 DMA modify (IDP_DMA_Mx) register, 12-21, 12-22 FIFO (IDP_FIFO) register, 12-14, 12-16, 12-25 FIFO memory data transfer, 12-14 FIFO register (IDP_FIFO register), 12-14 illustrated, 12-2

G
generators, optional reset, 24-44 GM (get more data) bit, A-221 ground plane, in PCB design, 24-39 group descriptions, signal routing unit, 10-16

H
handshake, DMA, 3-30 handshaking, external port, 4-104 hardware reset, 24-3

ADSP-214xx SHARC Processor Hardware Reference

I-13

Index

IDP (continued) interrupt driven transfers, 12-16 interrupts, 12-16, 12-28 memory data transfer, 12-14 packing modes, 12-10, 12-13 PDAP control (IDP_PDAP_CTL) register, A-176 PDAP control (IDP_PP_CTL) register, A-176 ping-pong DMA, 12-21 polarity of left-right encoding, 12-19 serial inputs, 12-6 specifications, 12-1 IDP bits bus hang disable (IDP_BHD), 12-33, A-173 clear buffer overflow (IDP_CLROVR), A-173 DMA enable (IDP_DMA_EN), 12-30, A-173 DMA status (IDP_DMAx_STAT), 12-23, A-180 enable (IDP_ENABLE), 12-30, A-173 FIFO number of samples (IDP_FIFOSZ), A-180 FIFO samples exceed interrupt (IDP_FIFO_GTN_INT), 12-28 frame sync format (IDP_SMODEx), 12-15, 12-17, 12-27, A-174 IDP_DMA_EN bit do not set, 12-16 monitor number of samples (IDP_NSET), A-173 PDAP clock edge (IDP_PDAP_CLKEDGE), 12-28, A-178 PDAP enable (IDP_PDAP_EN), 12-30, A-178 PDAP input mask bits, 12-27

IDP bits (continued) PDAP packing mode (IDP_PDAP_PACKING), A-178 PDAP reset (IDP_PDAP_RESET), A-178 ping-pong DMA enable (IDP_PING) bits, A-175 port select (IDP_PORT_SELECT), A-177 port select (IDP_PP_SELECT), 12-28 reset (IDP_PDAP_RESET) bit, A-178 IDP_CTL0 (input data port control) register, A-172 IDP_CTL1 (input data port control) register, 12-29, A-174, A-176 IFS (internal frame sync select) bit, A-161 IIR global control register (IIRCTL1), A-87 IIR accelerator 32- to 40-bit packing, 7-66 chained DMA, 3-18 chain pointer DMA, 7-67 coefficient memory, 7-64 control (IIRCTLx) register, 7-60 data memory, 7-64 debugging, 7-83 DMA status (IIRDMASTAT) register, 7-60 DMA transfers, 7-66 floating-point operations, 7-63 internal memory, 7-64 MAC unit, 7-63 operating modes, 7-65 single step, 7-83 throughput, 7-72, 7-81 transposed form 2 biquad, 7-62 IIR accelerator registers debug mode control (IIRDEBUGCTL), 7-60, A-92

I-14

ADSP-214xx SHARC Processor Hardware Reference

Index

IIR accelerator registers (continued) DMA status (IIRDMASTAT), 7-60, A-91 global control (IIRCTLx), 7-60, A-87 MAC status (IIRMACSTAT), 7-60, A-90 IIR bits 40-bit floating-point select (IIR_FORTYBIT), A-89 all channels done (IIR_DMAACDONE), A-92 channel auto iterate (IIR_CAI), A-88 channel complete interrupt (IIR_CCINTR), A-89 coefficient and Dk load status (IIR_DMACnDkLD), A-91 DMA chain pointer loading status (IIR_DMACPL), A-91 DMA enable (IIR_DMAEN), A-88 DMA status processing of current channel done (IIR_DMAWDONE), A-91 enable (IIR_EN), A-87 IIR enable (IIR_EN), A-88 number of biquads (IIR_NBIQUADS), A-90 number of channels (IIR_NCH), A-88 rounding mode select for floating-point mode (IIR_RND), A-89 save state (IIR_SS), A-88 status (MRZ, MRI, MINV, ARZ, ARI, AINV), A-90 window size (IIR_WINDOW), A-90 IISPx (serial port DMA internal index) registers, 3-4, 3-26 IMSPI (serial peripheral interface address modify) register, 16-35 IMSPx (SPORT DMA address modifier) registers, 3-6, 3-26 index registers, 3-28

INDIV (input divisor) bit, A-9 initializing DDR2, 4-80 input setup and hold time, 24-38 input signal conditioning, 24-35 input slave select enable (ISSEN) bit, A-221 input synchronization delay, 24-31 instruction cache, throughput, 4-22, 4-47 interconnections, master-slave, 16-3 interleaving 16-bit addressing, DDR2, 4-93 internal index, 3-28 internal memory DMA index (IDP_DMA_Ix) registers, 12-21 DMA index (IISPx) registers, 3-4, 3-26 DMA modifier (IDP_DMA_Mx) registers, 12-21, 12-22 DMA modifier (IMSPx) registers, 3-6, 3-26 internal vs. external frame syncs, 11-36 interpolation, FIR filter, 7-40 interrupt and timer pins, 24-31 interrupt controller, DAI, 10-30 interrupts acknowledge mechanisms, 2-11 audio events, 2-6 buffer status and, 2-12 channel priority, 3-47 conditions for generating interrupts, 11-48 DAI, 10-30 DAI/DPI controller, 2-6 DAI/DPI controller registers, A-18 DAI/DPI sources, 2-7 data transfer, starting, 12-31 default routing, A-14 destinations, A-14 DPI, 10-30 (enable RX status interrupt) bit, A-240 event masking, 2-10

ADSP-214xx SHARC Processor Hardware Reference

I-15

Index

interrupts (continued) example, assigning, 2-5 external memory booting, 4-17, 4-42 FFT, 7-18 FIFO to memory, 12-30 latching, 2-8 latency, 2-12 latency, managing, 2-13 link ports, 5-17 masking, 3-44 multiple request signals, 2-5 polling, 3-44 priority, 3-47 priority control, 2-3, A-16 registers (PICRx), A-16 response to, 2-12 restrictions, 2-12 servicing, 2-10, 2-11 software based, 2-5 sources, A-14 system interrupt controller, 2-6 TWI, 2-5 UART, 2-5 INVFSx (active low frame sync select for frame sync) bits, 15-13 I/O interface to peripheral devices, 11-1 I/O processor, 3-25 address bus (IOA), 3-26 and addressing, 3-26 buffer, 3-39, 3-43 DMA data, 3-32 bus priority, external port, A-22 bus structure, 3-30 chain assignment, 3-33 chained DMA, 3-12 chain pointer (CPSPI) register, 3-12 chain pointer registers, 3-8 configuring DMA, 3-50 count registers, 3-7, 3-28 DMA channel registers, 3-39, 3-43

I/O processor (continued) IDP buffer, 3-10 miscellaneous external port parameter registers, 3-10 standard (non chained) DMA, 3-23 TCB memory allocation, 3-32 transfer types, 3-1, 3-2 ISSS (input service select) bit, A-232

K
kernel boot timing, 24-23

L
LAFS (late transmit frame sync select) bit, 11-29, 11-35, A-162 latchup, 24-35 latency input synchronization, 24-31 in SPORT registers, 11-57 link ports, 5-15 PCG, 15-19 left-justified mode, C-5 SRC, A-182 SRC timing, 13-11 left-justified sample pair mode Tx/Rx on FS rising edge, 11-29 length registers, DMA, 3-9 life counter, 19-1 link port token passing, 5-10 link port bits buffer hang disable (LP_BHD), A-64 bus status transmit (LPBS), A-66 DMA channel count interrupt (DMACH_IRPT), A-65 DMA channel count mask (DMACH_IRPT_MSK), A-64 external transfer done interrupt (EXTTXFR_DONE), A-66

I-16

ADSP-214xx SHARC Processor Hardware Reference

Index

link port bits (continued) external transfer done mask (EXTTXFR_DONE_MSK), A-64 invalid transmit interrupt (LPIT), A-66 link buffer DMA chaining enable (LCHEN), A-63 link buffer enable (LEN), A-63 link buffer status (FFST), A-66 link buffer transmit/receive (LTRAN), A-63 link port transmitter logic synchronizer enable (LSYNC_EN), A-63 receive request mask (LRRQ_MSK), A-64 receive request status (LTRQ), A-65 transmit request mask (LTRQ_MSK), A-64 transmit request status (LTRQ), A-65 link ports block diagram, 5-5 boot bit settings, 24-22 booting, 24-21 buffer DMA enable (LxDEN) bit, A-63 buffers, 5-14 chained DMA, 3-16 control (LCTL) register, A-63 FPGA bridge, 5-9 handshake timing, 5-5 initialization for boot, 24-22 interrupts, 5-17 to 5-19 masking interrupt, 5-19 protocol, 5-5 receive DMA, 5-21 servicing interrupts, 5-19 token passing, 5-10 transmit DMA, 5-22 logical vs. physical address, 4-18, 4-43 loopback mode timers, 17-25, 19-20, 20-9 loopback mode, SPI, 16-43

loopback routing, DAI, DPI, 10-39 loop-back test, MLB, 9-23 low active transmit frame sync (LFS, LTFS and LTDV) bits, A-192 LRFS (SPORT logic level) bit, 11-37 LSBF (least significant bit first) bit, A-159

M
MAC status (IIRMACSTAT) register, 7-60 manual contents, lxxii conventions, lxxx new in this edition, lxxv manual revisions, lxxv mapping addresses, DDR2, 4-93 mask bits, interrupt, 3-44 master input slave output (MISOx) pins, 16-8, 16-14 slave output, 16-14 master mode operation, SPI, 16-33 master out slave in (MOSIx) pin, 16-8, 16-14 master-slave interconnections, 16-3 MCM, multichannel mode, See SPORTs modes, multichannel mode media local bus See MLB media oriented systems transport (MOST) protocol, C-7 memory coefficient, 7-33 data transfer, FIFO, 12-14 FFT data, 7-6 IIR related, 7-64 memory-mapped registers, A-2 TCB allocation for DMA, 3-32 transfer types, 3-2 memory select (flags) programming (MSEN) bit, A-6 memory-to-memory DMA. See MTM DMA

ADSP-214xx SHARC Processor Hardware Reference

I-17

Index

memory transfer types, 3-1 microcontroller, host, 24-7 MISCAx_I (signal routing unit external miscellaneous) register, 15-14 miscellaneous external port parameter registers, 3-10 miscellaneous signal routing (SRU_EXT_MISCx) registers (Group E), A-143 MISOx pins, 16-8, 16-14 MLB buffer local channel, 9-12 buffer threshold, 9-12 channel address, 9-7 clock rate, 9-3 configuring circular buffered DMA, 9-22 configuring I/O mode using interrupts, 9-20 configuring ping-pong DMA, 9-22 data transfer, core, 9-11 DMA transfers, 9-14 features, 9-3 flush buffer, 9-13 frame synchronization, 9-10 Generic Synchronous Packet Format (GSPF), 9-9 I/O service requests, 9-13 logical channel, 9-7 MLBCLK pin, 9-4 MLBDAT pin, 9-4 MLBSIG pin, 9-4 MOST25 and MOST50, 9-2 multi-packet buffering, 9-16 ping-pong DMA, 9-15 register descriptions, 9-4, 9-5 registers, A-93 to A-111 RxStatus byte, 9-7 single-packet buffering, 9-16 specifications, 9-1

MLB bits buffer current address (BCA), 9-14, A-109 buffer depth (BD), A-111 buffer final address (BFA), 9-14, A-109 buffer ready, DMA (RDY), A-108 buffer threshold (TH), 9-13, A-111 channel enable (CE), A-105 channel type select (CTYPE), A-105 frame synchronization channel disable (FSCD), 9-10, A-104 frame synchronization enable (FSE), 9-10, A-105 frame synchronization physical channel count (FSPC), A-104 little-endian mode (MLE), A-95 loop-back mode (LBM), 9-23 MASK, 9-10 next buffer end address (BEA), A-110 next buffer start address (BEA), A-110 MLB registers buffer, 9-5, 9-11, A-109 to A-111 channel control (MLB_CECRx), 8-24, 9-10, 9-15, 9-16, 9-18, 9-20, 13-17, 14-19, 16-28, 17-17, 21-16, 22-17, A-101 channel interrupt status (MLB_CICR), 9-20, A-99 channel status configuration (MLB_CSCRx), 8-24, 9-10, 9-16, 9-17, 9-18, 13-17, 14-19, 16-28, 17-17, 21-16, 22-17 device control and configuration (MLB_DCCR), 9-4, 9-23, A-94 status, channel (MLB_CSCRx), A-106 system data configuration (MLB_SDCR), A-97 system mask configuration (MLB_SMCR), A-98

I-18

ADSP-214xx SHARC Processor Hardware Reference

Index

MLB registers (continued) system status (MLB_SSCR), 9-4, 9-21, A-96 mode left-justified (IDP), 12-6 left-justified (SPORT), C-5 loopback (SPORT), A-168 right-justified (IDP), 12-6 serial mode settings (IDP), 12-17 single channel double frequency (SPDIF), 14-12 standard serial, C-2 timer, A-261 two channel (SPDIF), 14-12 modes, audio, C-2 to C-8 MOSIx pins, 16-8, 16-14 MOST (media oriented systems transport), C-7 most significant byte first (MSBF) bit, A-222 MPEG-2 format, 14-17 MSBF (most significant byte first) bit, A-222 MTM DMA 32-bit word, 6-4 buffers, 6-4 clocking, 6-2 data types, 6-3 FIFOs, 6-4 interrupts, 6-4 latency, 6-6 programming, 6-7 resetting, 6-4 specifications, 6-1 throughput, 6-6 MTxCCSx (serial port transmit compand) registers, A-169

MTxCSx (serial port transmit select) registers, A-169 multi-bank operation with data packing, 4-39, 4-84 multichannel filtering, FIR, 7-51 multiple processor system example, 4-57, 4-95 multiplexing clockout enable (CLKOUTEN), A-12 external port pins, 24-30 pins, 24-28 to 24-32 PWM pins, 8-4, A-6 RESETOUT, A-12 multiplexing FLAG pins, 24-28 multiprocessing. See shared memory

N
n greater than or equal to 512, repeat, 7-26 no operation command (NOP), 4-34 normal frame sync, 11-35

O
one shot frame sync A or B (STROBEx) bits, 15-13 one shot option (STROBEB) bit, 15-14 optimization core read, 4-59, 4-97 DDR2 reads, 4-96 to 4-99 SDRAM reads, 4-57 SDRAM reads, example, 4-60 SDRAM reads, external port DMA example, 4-60 SDRAM throughput, 4-141, 4-142 OR, logical, 12-33

ADSP-214xx SHARC Processor Hardware Reference

I-19

Index

P
package availability, 1-2 packing 16 to 32-bit packing (PACK) bit, A-160 modes in IDP_PP_CTL, illustrated, 12-10 serial peripheral interface (PACKEN) bit, A-224 packing instructions, 4-18, 4-43 page size (SDRAM), A-35 parallel data acquisition port control (IDP_PP_CTL) register, A-176 parallel data acquisition port (PDAP), 12-33 parameter registers, DMA, 3-39, 3-43 PCG active low frame sync select for frame sync (INVFSx) bits, 15-13 block diagram, 15-6 bypass mode, 15-13 clock A source (CLKASOURCE) bit, A-189 clocking (CLKDIV bit), 15-6 clocking (serial clock), 15-6 clock input source enable (CLKx_SOURCE_IOP) bit, A-193 clock with external frame sync enable (FSx_SYNC) bit, A-193 control (PCG_CTL_Ax) registers, 15-14, A-187, A-188 divider mode, setting, 15-8 division ratios, 15-18 enable clock (ENCLKx) bit, A-187, A-188 enable frame sync (ENFSx) bit, A-187, A-188 frame sync, 15-7 to 15-12 frame sync, setting, 15-21 frame sync A source (FSASOURCE) bit, 15-14, A-189

PCG (continued) frame sync B source (FSBSOURCE) bit, 15-14, A-189 frame sync input source enable (CLKx_SOURCE_IOP) bit, A-193 frame sync with external frame sync enable (FSx_SYNC) bit, A-193, A-194 I2S timing, 15-11 latency, 15-19 one shot frame sync A or B (STROBEx) bits, 15-13 one shot option, 15-14 PCG_CTLA0 (control) register, A-187, A-188 phase shift, 15-8 phase shift of frame sync, 15-16 pins, 15-3 pulse width for frame sync (PWFSx) bit, A-190 pulse width (PCG_PW) register, 15-14 specifications, 15-1 SRU latency, 15-20 SRU programming, 15-4 STROBEA (one shot frame sync A) bit, 15-14 STROBEB (one shot frame sync B) bit, 15-14 synchronization with the external clock, 15-21 PCI (program control interrupt) bit, 3-14 PDAP 32-bit word packed, 12-12 8-bit word packed, 12-13 channel priority, 12-6 control (IDP_PDAP_CTL) register, A-176 data format, 12-6 enable (IDP_PDAP_EN) bit, A-178 mode configuration, 12-8

I-20

ADSP-214xx SHARC Processor Hardware Reference

Index

PDAP (continued) operating modes, 12-7 packed data, 12-9, 12-10 packing by 2 (two cycle data move), 12-11 packing by 3 (three cycle data move), 12-12 packing by 4 (four cycle data move), 12-13 packing mode (IDP_PDAP_PACKING) bit, A-178 pin descriptions, 12-3 port mask bits (IDP_Pxx_PDAPMASK), A-177 port select (IDP_PORT_SELECT) bit, A-177 port selection, 12-8 reset (IDP_PDAP_RESET) bit, A-178 (rising or falling) clock edge (IDP_PDAP_CLKEDGE) bit, A-178 transferring data, 12-6 peripheral devices, I/O interface to, 11-1 peripherals memory mapped, 4-12 peripheral timers external event watchdog (EXT_CLK) mode, 17-6, 17-15 input/output (TMRx) pin, 17-5 invalid conditions, 17-8 modes, 17-5 period, configuring, 17-5 period equation, 17-11 pulse width count and capture (WDTH_CAP) mode, 17-12 pulse width modulation (PWMOUT) mode, 17-8 rectangular signals, 17-10 single pulse generation, 17-11

peripheral timers registers, 17-4 period (TMxPRD) registers, 17-4 pulse width (TMxW) registers, 17-4 timer count (TMxCNT), 17-4 timer global status and control (TMSTAT), 17-4 timer width (TMxW), 17-4 timer word period (TMxPRD), 17-4 word count (TMxCNT) registers, 17-4 phase shift of frame sync, 15-16 physical vs. logical address, 4-18, 4-43 PICR register, 3-48 pin buffer example, 10-9 input hysteresis, 24-35 ping-pong DMA, 3-24 ping-pong DMA, IDP, 12-21 pins ACK, enabling, A-29 descriptions, 23-17, 24-2 external memory, 4-28, 4-64 FLAGx, 11-15 PCG, 15-3 pin states during SDRAM commands, 4-35 RESET, 24-35 timer (through SRU), 17-5 plane, ground, 24-39 PLLBP (PLL bypass bit), 23-7, A-12 PLLBP (PLL bypass mode) bit, 23-8, 23-14 PLLDx (PLL divider) bits, A-9, A-11, A-12 PLLM (PLL multiplier) bit, A-8, A-11 PLL start-up, 23-9 PMCTL (power management control) register, 23-4, A-7, A-8, A-11 polarity IDP left-right encoding, 12-19 PWM double-update mode, 8-10 PWM single update mode, 8-9 SPDIF connections, C-13

ADSP-214xx SHARC Processor Hardware Reference

I-21

Index

polarity (continued) SPI clock, 16-14, 16-33 power management bypass mode (PLL) example, 23-17 clocking system, 23-2 clock system, 23-2 phase-locked loop (PLL), 23-2 PLL, 23-9 post divider example, 23-13 registers (PMCTLx), 23-1 VCO programming example, 23-14 power management control (PMCTL) register, A-7 power management control register (PMCTL), 23-4, A-8 power management register, A-12 power savings, 23-6 power supply, monitor and reset generator, 24-44 power-up, SDRAM (SDPM) bit, A-33 power-up, See system design power-up reset circuit, 24-44, 24-45 preambles, audio applications, C-14 preambles, S/PDIF, C-14 precision clock generators. See PCG predictive address vs. real address, 4-16 predictive reads, disable bit (NO_OPT), A-30 printed circuit board design, 24-39 priority, interrupt, 3-47 processor core, overview, 1-2 core access to link buffers, 5-15 core multiplexing, 24-28 host, 24-7 identification, 24-34 resetting, 24-3 product details, 1-2 program control interrupt (PCI) bit, 3-14

program controlled interrupt bit (PCI), 3-13, 3-15, 11-50, 16-13, 21-22, A-165 programmable interrupt priority control, 2-3, A-16 programmable interrupt registers (PICRx), A-16 programmable interrupts, listed, 3-48 programming example, 7-77 protocol mode, changing, 11-29 pulse, clock, in serial ports, 11-13 pulse, frame sync delay in serial ports, 11-22 pulse, frame sync formula, 11-10 pulse width count and capture (WDTH_CAP) mode, 17-12 pulse width modulation (PWMOUT) mode, 17-8 PWM 16-bit read/write duty cycle registers, 8-7 accuracy in, 8-23 block diagram, 8-3 center-aligned paired PWM double-update mode, 8-10 channel duty control (PWMA, PWMB) registers, A-74 crossover mode, 8-14 double update mode, 8-22 double-update mode, 8-10 enable pulse width modulation groups, 8-20 equation, duty cycles, 8-10 equations, 8-8 to 8-12 example, edge-aligned, 8-18 global control (PWMGCTL) register, A-67 global status (PWMGSTAT) register, A-69 multiplexing, 8-4

I-22

ADSP-214xx SHARC Processor Hardware Reference

Index

PWM (continued) output disable (PWMSEG) register, 8-13, A-71 paired mode status (PWM_PAIRSTAT) bit, A-71 phase (PWM_PHASE) bit, 8-8 polarity single update mode, 8-9 resetting, 8-13 single update mode, 8-22 specifications, 8-1 status (PWMSTAT) register, 8-8, A-71 switching frequency equation, 8-6 switching signals, 8-8 synchronization (PWM_SYNCENx) bits, 8-24 timing, 8-8, 8-9 two-phase generator, 8-6 PWM bits crossover (PWM_AXOV, PWM_BXOV), 8-14 PWM clock, 8-6 PWM example, deadtime, 8-12 PWMGCTL (pulse width modulation global control) register, A-67 PWMGSTAT (pulse width modulation global status) register, A-69 PWMOUT (pulse width modulation) mode, 17-8

R
read-only-to-clear bit type description, A-4 read time delay, AMI, 4-26 read-write-1-to-clear bit type description (RW1C), A-4 read-write-1-to-set bit type description (RW1S), A-4 real time clock see RTC real-time clock. See RTC

receive busy (overflow error) SPI DMA status (SPIOVF) bit, A-227 receive data, serial port (RXSPx) registers, 3-10 receive data (RXSPI) buffer, 16-8 receive overflow error (SPIOVF) bit, 16-40, 16-41 receive shift (RXSR) register, 16-8 refresh rate control, DDR2, A-53 refresh rate control (SDRRC) register, A-36 refresh rate in SDRAM, 4-36 register drawings, reading, A-2 registers, See peripheral specific registers register writes and effect latency, SPORTs, 11-42 reset accelerator state, 7-6 bus synchronization, 4-110, 4-111 clock change during runtime, 4-155 DAI state, 10-24 data mask, 4-40 DDR2 controller, 4-80 DPI state, 10-27 flush data in PDAP FIFO, 12-22 generators, 24-43 halting ping-pong DMA, 3-24, 12-22 MTM DMA, 6-4 PLL, 14-23, 14-24 power-up RTC, 19-16 PWM enable bits, 8-13 RESET after power-up, 24-3 RESETOUT, 24-35 RESET pin, 24-35 SDRAM controller, 4-41 shift register, 18-5 timer state, 17-8 time state, 17-14 UART, 21-4, 21-14 UART DMAUART reset, DMA, 21-23

ADSP-214xx SHARC Processor Hardware Reference

I-23

Index

RESET pin, 24-35 resolution (PWM), 8-23 responding to interrupts, 2-12 restrictions clock rate, SPORTs, 11-12 external memory access, 4-165 interrupts, 2-12 SDRAM, 4-52 SPORTs, 11-22 right justified mode, C-5 right-justified mode SRC, 13-11 SRC, timing, 13-11 rotating DMA priority, 3-44 routing, DAI, 10-24 routing, DPI, 10-27 ROVF_A or TUVF_A (channel A error status) bit, A-164 ROVF_A or TUVF_A (serial port error status) bits, A-164 ROVF_B or TUVF_B (channel B error status) bit, A-163 RS-232 device, restrictions, 11-15 RTC alarm, 19-9 alarm clock features, 19-9 alarm (RTC_ALARM) register, 19-9 block diagram, 19-10 calibration, 19-2, 19-10 clocking, 19-3 clock register (RTC_CLOCK), 19-4 clock requirements, 19-3 counters, 19-6 day alarm, 19-9 digital watch, 19-7 digital watch features, 19-1 error, 19-10 event flags, 19-18 flags (list), 19-18 initialization register (RTC_INIT), 19-4

RTC (continued) pin descriptions, 19-3 pins, 19-3 power-down, 19-16 power-up, 19-16 programming, 19-15 registers, 19-3 reset, 19-16 specifications, 19-1 status register (RTC_STAT), 19-4 status (RRTC_STAT) register, 19-18 stopwatch, 19-10 stopwatch count (RTC_SWCNT) register, 19-10 stopwatch function, 19-10 running reset, 24-4 RXFLSH (flush receive buffer) bit, 16-38, 16-40, 16-41 RXS_A (data buffer channel B status) bit, A-164 RXSPI, RXSPIB (SPI receive buffer) registers, 16-23 RXSPx (serial port receive buffer) registers, 3-10 RXSR (SPI receive shift) register, 16-8 RXS (SPI data buffer status) bit, A-230 RX_UACEN (DMA receive buffer enable) bit, 21-4

S
sample/window based processing mode, IIR, 7-39, 7-65 saving power, 23-6 SCHEN_A and SCHEN_B (serial port chaining enable) bit, A-162 SDEN (serial port DMA enable) bit, A-162 SDRAM, 4-39, 4-84 bank status, external, A-39 bus errors, 4-62, 4-100 changing SDCLK, 4-155

I-24

ADSP-214xx SHARC Processor Hardware Reference

Index

SDRAM (continued) clock equation, 4-36 core address mapping, 4-52 multi-bank operation, 4-37, 4-82 refresh rate, 4-36 refresh rate control register (SDRRC), A-36 registers, A-31 to A-39 resetting, 4-41 restrictions, 4-52 status register (SDSTAT), A-37 throughput, 4-28, 4-57, 4-59, 4-61 SDRAM bits CAS latency (SDCL), A-33 column address width (SDCAW), A-34 disable clock and control (DSDCTL), A-33 external data path width (X16DE), A-34 force auto refresh (Force AR), A-34 force load mode register write (Force LMR), A-35 force precharge (Force PC), A-35 optional refresh (SDORF), A-34 page size is 128 words (PGSZ 128), A-35 pipeline option with external register buffer (SDBUF), A-35 power-up mode (SDPM), A-33 power-up sequence start (SDPSS), A-34 RAS setting (SDTRAS), A-33 RDC setting (SDTRCD), A-35 read optimization (SDROPT), 4-57, 4-97, A-36 refresh delay (RDIV), A-36 row address width (SDRAW), A-35 RP setting (SDTRP), A-33 self-refresh enable (SDSRF), A-34 status, external bank, A-39 WR setting (SDTWR), A-34

SDRAM controller, 4-27 addressing (16-bit), 4-54 to 4-55 calculating refresh rate, 4-36 clock frequencies, 4-7 external memory access timing, 4-6 power-up sequence, A-34, A-35 read optimization, 4-57 read/write command, 4-32 refresh rate (SDRRC) register, 4-35 setting bank column address width, A-35 SDRAM controller commands auto-refresh, 4-34 bank activate, 4-31 command pin states, 4-35 load mode register, 4-30 NOP/command inhibit, 4-34 self-refresh, 4-61, 4-99 single precharge, 4-31 SENDZ (send zeros) bit, A-221 serial clock (SPORTx_CLK) pins, 11-13 serial communications, 21-7 serial inputs, 12-6 serial peripheral interface, See SPI serial timing protocol, audio, C-1 servicing interrupts, 2-11 setting up DMA on SPORT channels, 11-48 setup time, inputs, 24-38 shared memory see also external port bus arbitration, 4-105 system design diagram, 4-104 shift register block diagram, 18-6 buffers, 18-5 clocking, 18-4 clock routing (DAI), A-150 control (SRC_CTL), A-206 data routing (DAI), A-152 effect latency, 18-7

ADSP-214xx SHARC Processor Hardware Reference

I-25

Index

shift register (continued) parallel data, 18-7 programming, 18-8 reset signal, 18-5 serial data, 18-6 signal routing unit external miscellaneous (MISCAx) registers, 15-14 signal routing unit See SRU, DAI signal routing unit (SRU), 17-5 signals bus grant HBG, 4-111 bus request BRx, 4-105, 4-108, 4-111 memory select MSx, 4-111 PWM waveform generation and, 17-10 sensitivity in SPORTs, 11-7 serial port, 11-9, 11-13 SPORT, 11-6 timer, 17-5 silicon revision, 24-34 single channel double frequencey mode, 14-12 single processor system example, 4-56, 4-95 single rate operations FIR, 7-39 software based interrupts, 2-5 software reset, 24-4 SP1PDN (SPORT1 clock enable) bit, A-12 SP3PDN (SPORT3 clock enable) bit, A-13 SPCTLx control bit comparison in four SPORT operation modes, 11-30, 11-31 SPCTLx (serial port control) registers, 11-13, 11-15, 11-30 S/PDIF See also S/PDIF bits; S/PDIF registers AAC compressed format, 14-17 AC-3 format, 14-17 audio standards, 14-13 biphase encoding, 14-5 block structure, C-10 clock (SCLK) input, 14-5

S/PDIF (continued) compressed audio data, 14-16 DTS format, 14-17 frame sync (LRCLK) input, 14-5 MPEG-2 format, 14-17 non-linear audio data, 14-16 output routing, 14-7 pin descriptions, receiver, 14-4 pin descriptions, transmitter, 12-3, 14-3 preambles, C-14 programming guidelines, 14-6 serial clock input, 14-6 serial data (SDATA) input, 14-5 single-channel, double-frequencey format, 14-12 subframe format, C-11 two channel mode, 14-12 S/PDIF bits biphase error (DIR_BIPHASEERROR), A-204 channel status buffer enable (DIT_CHANBUF), A-197 channel status byte 0 A (DIT_B0CHANL), A-197 channel status byte 0 B (DIT_B0CHANR), A-197 channel status byte 0 for subframe A (DIR_B0CHANL), A-204 channel status byte 0 for subframe B (DIR_B0CHANR), A-204 disable PLL (DIR_PLLDIS), A-202 frequency multiplier (DIT_FREQ), A-196 lock error (DIR_LOCK), A-201 lock receiver status (DIR_LOCK), A-204 mute receiver (DIR_MUTE), A-202 mute transmitter (DIT_MUTE), A-196 non-audio frame mode channel 1 and 2 (DIR_NOAUDIOLR), A-203

I-26

ADSP-214xx SHARC Processor Hardware Reference

Index

S/PDIF bits (continued) non-audio subframe mode channel 1 (DIR_NOAUDIOL), A-203 parity biphase error (DIR_BIPHASE), A-201 parity (DIR_PARITYERROR), A-204 select single channel double frequency mode channel (DIT_SCDF_LR), A-196 serial data input format (DIT_SMODEIN), A-197 single channel double frequency channel select (DIR_SCDF_LR), A-201 stream disconnected (DIR_NOSTREAM), A-204 transmit single channel double frequency enable (DIT_SCDF), A-196, A-201, A-202 transmitter enable (DIT_EN), A-196 validity bit A (DIT_VALIDL), A-197 validity bit B (DIT_VALIDR), A-197 validity (DIR_VALID), A-203 S/PDIF registers channel A transmit status (SPDIF_TX_CHSTA), A-198, A-199 channel B transmit status (SPDIF_TX_CHSTB), A-199, A-200 left channel status for sub-frame A (DIRCHANL), A-205 receiver status (DIRSTAT), A-202 SRU control, 14-5, 14-7 transmit control (DITCTL), 14-6, A-195 SPDIF_TX_CHSTA (Sony/Philips digital interface channel status) register, A-198, A-199 special IDP registers, A-153 SPEN_A (serial port channel A enable) bit, A-158

SPI See also SPI bits; SPI registers AD1855 DAC and, 16-10 address, TCB, 16-37 block diagram, 16-8 booting, 24-12, 24-15 boot packing, 24-16 buffer errors, 16-21 buffer packing, 16-20 buffers, 16-19 to 16-23 chained DMA, 3-15 chaining, DMA, 16-13, 16-24, 16-26, 16-35 change clock polarity, 16-33 changing configuration, 16-33 clock phase, 16-15 clock (SPICLK) pin, 16-14 clock (SPICLK) signal, 16-8 configuring and enabling, 16-35, 16-36 core transfers, 16-34, 16-35 DMA, switching from transmit to receive mode, 16-37 examples, timing, 16-17 examples, transfer protocol, 16-15 features, 16-2 flush buffer, 16-22 functional description, 16-8 interconnections, master-slave, 16-3 interface signals, 16-3 loopback mode, 16-43 master boot mode, 24-12 master input slave output (MISOx) pins, 16-8 master mode, 16-33 master mode operation, configuring for, 16-33 master out slave in (MOSIx) pins, 16-8 master-slave interconnections, 16-3 operation, master mode, 16-35, 16-36 operations, 16-33

ADSP-214xx SHARC Processor Hardware Reference

I-27

Index

SPI (continued) polarity, clock, 16-14, 16-33 receive data (RXSPI) buffer, 16-8, 16-34 registers, A-219 shift registers (input, output), 16-18 slave boot mode, 24-15 SPI_DS_I pin, 16-35, A-221 switching from receive to transmit mode, 16-37, 16-39 system, configuring and enabling bits, A-220 transfer formats, 16-14 transmit data (TXSPI) buffer, 16-8 transmit underrun error (SPIUNF) bit, 16-40, 16-41, A-227 TXFLSH (flush transmit buffer) bit, 16-38, A-224 SPI bits chained DMA enable (SPICHEN_A and SPICHEN_B), A-227 chain loading status (SPICHS), A-228 clock phase (CPHASE), A-222 clock polarity (CLKPL), A-222 device select enable (DSxEN), 16-35, 16-36 enable (SPIEN), A-223 FIFO clear (FIFOFLSH), A-227 flush receive buffer (RXFLSH), 16-38, 16-40, A-224 flush transmit buffer (TXFLSH), A-224 get more data (GM), A-221 input slave select (ISSEN), A-221 internal loopback (ILPBK), A-225 master select (SPIMS), A-222 MISO disable (DMISO), A-221 most significant byte first (MSBF), A-222 open drain output select (OPD), A-223 packing enable (PACKEN), A-224

SPI bits (continued) program controlled interrupt bit (PCI), 16-13 receive overflow error (SPIOVF), 16-40, 16-41 seamless transfer (SMLS), A-224 send zero (SENDZ), A-221 sign extend (SGN), A-224 word length (WL), A-222 SPICHEN_A and SPICHEN_B (SPI DMA chaining enable) bits, A-162 SPICLK (SPI clock) pins, 16-14 SPICLK (SPI clock) signal, 16-8 SPICTL (SPI port control) registers, A-220 SPIDMAC (SPI DMA control) register, 16-24, A-225 SPI_DS_I (SPI device select) pin, 16-14 SPIDS status signal, A-232 SPI general operations, 16-4, 16-5 SPI master mode operation, 16-33 SPIOVF (SPI receive overflow error) bit, 16-40, 16-41 SPIPDN (SPI clock enable) bit, A-13 SPI registers DMA configuration (SPIDMAC), 16-24, 16-35, 16-38, A-225 flag (SPIFLGx), A-231 receive buffer (RXSPI), 3-10 receive control (SPICTL, SPICTLB), A-220 RXSR (SPI receive shift), 16-8 serial shift, 16-18 SPIBAUD (baud rate) register, A-228 status (SPISTAT), 16-40, A-229 status (SPISTAT, SPISTATB), A-229 transmit buffer (TXSPI), 16-34, A-228 TXSR (SPI transmit shift), 16-8 SPISTAT, SPISTATB (SPI status) registers, A-229

I-28

ADSP-214xx SHARC Processor Hardware Reference

Index

SPIUNF (SPI transmit underrun error) bit, 16-40, 16-41 SPORT bits, 11-22 B channels enable (MCEB), A-168 chained DMA enable (SCHEN), 11-48, 11-49, 11-59 chained DMA enable (SPICHEN), A-162 channel A enable (SPEN_A), A-158 channel error status (ROVF_A or TUVF_A), A-164 clock, internal clock (ICLK), MSTR (I2S mode only), A-160 clock rising edge select (CKRE), 11-9 control bit comparison, 11-30, 11-31 current channel selected (CHNL), A-168 data independent transmit/receive frame sync (DIFS), A-161 DMA chaining status (DMACHSxy), A-169 DMA enable (SDEN), A-162 DMA status (DMASxy), A-168 DXS_B (data buffer status), A-163 FS both enable (FS_BOTH), A-162 internal frame sync select (IFS), A-161 internal serial clock (ICLK), 11-9 late frame sync (LAFS), A-162 loopback mode (SPL), A-168 multichannel frame delay (MFD), A-167 multichannel mode enable (MCEA), A-167 number of channels (NCH), 11-23 number of multichannel slots (NCH), A-168 operation mode (OPMODE), 11-28 program controlled interrupt bit (PCI), 11-50, A-165 receive underflow status (ROVF_A or TUVF_A), A-164

SPORT modes (I2S), 11-28 I2S (Tx/Rx on left channel first), 11-29 left-justified, 11-29, C-5 loopback, 11-64 standard DSP, 11-29, C-2 SPORT registers channel selection, active (SPxCSx), 11-23 control (SPCTLx), 11-13, 11-15, 11-30, 11-31 divisor (DIVx), 11-13 multichannel control (SPMCTLxy), 11-22, 11-28 receive buffer (RXSPx), 11-41, 11-44, C-4 SPCTLx (serial port control), A-155 transmit buffer (TXSPx), 11-41, 11-42, C-4 transmit compand (SPxCCSy), A-169 SPORTs, 11-43, 11-62 128-channel TDM, 11-3, 11-20 See also SPORT bits, modes, registers 128-channel TDM, 11-3 access complete interrupt, 11-52 address, DMA, 11-48 address, TCB and, 11-58 buffer errors, 11-45 buffer flush, 11-45 buffer hang disable (BHD) bit, 11-64 buffers, data, 11-42 chained DMA, 3-15 chain insertion (DMA), 3-36 chain insertion mode (DMA), 11-50 channel number (quantity) select (NCH bit), 11-23 clock divisor equation, 11-10 clock frequency equation, 11-10 clock rate restrictions, 11-12 clock (SCLKx) pins, 11-13

ADSP-214xx SHARC Processor Hardware Reference

I-29

Index

SPORTs (continued) clock signal options, 11-9 companding and data type bit (DTYPE), 11-14 companding (compressing/expanding), 11-4 companding limitations (ADSP-2146x), 11-25 compatibility with previous models, 11-26 configuring frame sync signals, 11-14 control bit comparison, 11-30, 11-31 data type, sign-extend, 11-33 data type, zero-fill, 11-33 debugging, A-168 divisor (DIVx) register, 11-8, 11-36 DMA chaining, 11-49 DMA channels, 11-47 DMA complete interrupt, 11-52 duplex, full, 11-13 enabling B channels, A-168 equation frame sync frequency, 11-10 examples, normal vs. alternate framing, 11-36 external memory DMA transfers, 11-51 external port bus interface, 11-51 features, 11-2 finding currently selected channel, A-168 flag pins, 11-15 FLAGx pins, 11-15 framed and unframed data, 11-34 framed vs. unframed data example, 11-36 frame sync delay, 11-22 full-duplex operation, 11-21 input/output (FLAGx) pins, 11-15 internal clock selection, 11-9 internal transfer complete interrupt, 11-52

SPORTs (continued) interrupts, 11-51 to 11-56 interrupt sources, 11-52 latency in writes, 11-57 loopback mode, 11-64 masking interrupts, 11-54 operation modes, changing, 11-30 operation modes, listed, 11-28 operation modes, standard DSP serial, C-2 pairing, 11-22 polarity change, 11-26 protocol mode, changing, 11-29 receive buffers, 11-42 serial clock pins, 11-13 servicing interrupts, 11-55 signal sensitivity, 11-7 SPORTx_DA and SPORTx_DB channel data signal, 11-13 SPORTx_FS (serial port frame sync) pins, 11-14 SRU routing, 11-7 time division multiplexed (TDM) mode, 11-20 transmit buffers, 11-42 transmit data valid signal (SPORTx_TDV_O), 11-25 transmit underflow status (TUVF_A) bit, A-164 transmit valid data signal (SPORTx_TDV_0), 11-25 Tx/Rx on FS rising edge, 11-29 using with SRU, 11-6 warnings and cautions, 11-44 SPTRAN (serial port data direction control) bit, A-163 SRC block diagram, 13-6 clocking, 13-12, C-7 control (SRCCTLx) register, A-182

I-30

ADSP-214xx SHARC Processor Hardware Reference

Index

SRC (continued) frame sync signal, 13-4 mute (SRCMUTE) register, A-185 ratio (SRCRAT) register, A-186 right-justified mode, 13-11 right-justified mode, timing, 13-11 time division multiplexing mode, 13-12, C-7, C-8 SRC bits auto mute (SRC0_AUTO_MUTE), A-182 bypass (SRC0_BYPASS), A-182 de-emphasis (SRC0_DEEMPHASIS), A-182 dither select (SRC0_DITHER), A-182 enable (SRC0_ENABLE), A-183 hard mute (SRC0_HARD_MUTE), A-182 matched phase select (SRC0_MPHASE), A-183, A-185 serial input format (SRC0_SMODEIN), A-182 serial output format (SRC0_SMODEOUT), A-183 soft mute (SRC0_SOFTMUTE), A-182 word length, output (SRC0_LENOUT), A-183 SRU bidirectional pin buffer, 10-14 buffers, 10-14 connecting, 10-34 connecting peripherals with, 10-16 connecting through, 10-34 default routing, SPORT, 11-7 frame sync routing control (SRU_FSx) registers, A-133 group A (clock) signals, 10-22, A-207 group E (miscellaneous) signals, A-143 to A-144 inputs, 10-16

SRU (continued) outputs, 10-16 register use of, 10-34 serial ports and, 11-6 signal groups, 10-17 to 10-19 signal groups, defined, 10-16 signal sources, clock, A-123 signal sources, frame sync, A-133 signal sources, miscellaneous, A-143 signal sources, pin signal, A-137 SPORT signal connections, 11-6 SRU2 group B (pin assignment) signals, A-211 group C (pin enable) signals, A-215 SRU registers clock (SRU_CLKx), A-123 frame sync (SRU_FSx), A-133 miscellaneous (SRU_EXT_MISCx), A-143 pin assignment (SRU_PINx) registers (group D), A-137 pin enable (SRU_PINENx) registers, A-146, A-150 pin signal (SRU_PINx), A-137 SRU_DATx (SRU data) registers, A-128 SRU_EXT_MISCx (SRU external miscellaneous) registers, A-143 SRU_FSx (SRU frame sync routing control) registers, A-133 SRU_PINENx (SRU pin buffer enable) registers, A-146, A-150 SRU_PINGx_STAT (ping-pong DMA status) register, A-179, A-180 SRU_PINx (pin signal assignment) registers, A-137 standard DSP serial mode, C-2 starting an interrupt driven transfer, 12-30, 12-31 status, DMA channel, 3-29 status registers, DMA, 3-39, 3-43

ADSP-214xx SHARC Processor Hardware Reference

I-31

Index

stopwatch function, RTC, 19-10 STROBEA (one shot frame sync A) bit, 15-14, A-191 STROBEB (one shot frame sync B) bit, 15-14, A-191 strobe period, 15-14 supervisory circuits, 24-44 support, technical or customer, -lxxvi switching from receive to transmit DMA, 16-39 synchronization with the external clock, 15-21 synchronizing frame sync output, 15-21 SYSCTL register external port data pin mode select (EPDATA) bits, A-6 interrupt request enable (IRQxEN) bits, A-6 memory select (MSEN) bit, A-6 pulse width modulation select (PWMx) bits, A-6 timer (flag) expired mode (TMREXPEN) bit, A-6 SYSCTL (system control) register, A-5 system, 24-35 system control register. See SYSCTL register system design baud rate, init value, 24-14 boot times, kernel, 24-22 bypass capacitors, 24-38 clock distribution, 24-35 conditioning input signals, 24-35 crosstalk, 24-39 decoupling capacitors, 24-38 designing for high frequency operation, 24-34 generators, reset, 24-44 ground plane, 24-39 hold time, inputs, 24-38

system design (continued) input setup and hold time, 24-38 input signal conditioning, 24-35 kernel, boot, 24-22 latchup, 24-35 latency, input synchronization, 24-31 link port booting, 24-21 pin descriptions, 24-2 plane, ground, 24-39 PLL start-up, 23-3 power options, 23-6 power supply, monitor and reset generator, 24-44 power-up, 23-3 recommendations and suggestions, 24-39 RESET pin, 24-35 resetting the processor, 24-3 shared memory system diagram, 4-104 VCO encodings, 23-5

T
tap list buffer, 3-10 TCB, 3-15 to 3-22, 3-31 to 3-35 TCB chain loading, 3-12 TCB throughput, 3-49 technical or customer support, lxxvi technical support, lxxvi test mode DAI use in, 10-39 data buffer use in, 3-12 loopback, SPI, 16-43, A-225 SPI, 5-22, 16-42 SPORT, 11-43, 11-62, 11-63, 17-25, 19-19, 20-9, 22-27 system, 24-35 throughput AMI, 4-141 arbitration freezing and, 4-11 DDR2, 4-11, 4-95, 4-97, 4-119

I-32

ADSP-214xx SHARC Processor Hardware Reference

Index

throughput (continued) external port, 4-149 external port DMA writes, 3-49 FIR accelerator, 7-49 freeze bits (FRZDMA, FRZCR, FRZSP), 4-11 IIR, 7-72 IIR accelerator, 7-72 instruction cache, 4-22, 4-47 I/O processor, 3-49 MTM DMA, 6-6 SDRAM, 4-141, 4-142 sequential reads in SDRAM, 4-59 THR register empty (THRE) flag, 21-13 time division multiplexed (TDM) mode, 11-20, 13-12, C-7 timeout, bus mastership, 4-112 timer, configuring, A-261 timer registers, A-260 timer control (TMxCTL), A-261 timer status (TMxSTAT), A-262 timers, UART, 21-6 timer See peripheral timers, core timer timing external memory accesses, 4-6 kernel boot, 24-23 link port handshake, 5-5 PWM, 8-8, 8-9 SPI clock, 16-17 SPI slave, 16-17 SPI transfer protocol, 16-15 SPORT framed vs. unframed data, 11-36 SPORT normal vs. alternate framing, 11-36 TIMOD (transfer initiation mode) bit, 16-34 TMRPDN (timer clock enable) bit, A-12, A-13

TMSTAT (peripheral timer global status and control) register, 17-4 TMxCNT (peripheral timer word count) registers, 17-4 TMxCTL (timer control) registers, A-261 TMxPRD (peripheral timer period) registers, 17-4 TMxSTAT (timer global status and control) register, A-262 TMxW (peripheral timer width) registers, 17-4 token passing, link ports, 5-10 T_PRDHx (timer period) registers, 17-4 transfer control block, See DMA TCB transfer control block See DMA TCB transfer direction, external port, 3-25 transmit and receive data buffers (TXSPxA/B, RXSPxA/B), 11-42 transmit and receive SPORT data buffers (TXSPxA/B, RXSPxA/B), 11-42 transmit data (TXSPI) buffer, 16-8 transmit shift (TXSR) register, 16-8 TUVF_A (channel error status) bit, A-164 TWI buffers, 22-13 to 22-16 flush buffer, 22-16 specifications, 22-1 TWI controller architecture, 22-6 block diagram, 22-7 bus arbitration, 22-9 call address, 22-11 clocking, 22-8 error, 22-11, 22-21, 22-25 fast mode, setting, 22-12 programming model, 22-19 start and stop conditions, 22-11 transferring data, 22-8

ADSP-214xx SHARC Processor Hardware Reference

I-33

Index

TWI controller bits address not acknowledged (TWIANAK), A-249 buffer write error (TWIWERR), A-249 clock high (TWICLKHI), A-113, A-114, A-245 clock low (TWICLKLOW), A-112, A-113, A-245 data not acknowledged (TWIDNAK), A-249 data transfer count (TWIDCNT), A-246 enable (TWIEN), A-244 fast mode (TWIFAST), A-246 general call enable (TWIGCE), A-251 issue stop condition (TWISTOP), A-246 lost arbitration (TWILOST), A-248 master address length (TWIMLEN), A-246 master mode enable (TWIMEN), A-246 master transfer direction (TWIMDIR), A-246 master transfer in progress (TWIMPROG), A-248 not acknowledged (TWINAK), A-251 repeat START (TWIRSTART), A-246 serial clock override (TWISCLOVR), A-247 serial clock sense (TWISCLSEN), A-250 serial data override (TWISDAOVR), A-247 serial data sense (TWISDASEN), A-249 slave address length (TWISLEN), A-251 slave enable (TWISEN), A-251 slave transmit data valid (TWIDVAL), A-251 TWI controller registers clock divider (TWIDIV), A-244 RXTWI16 (16-bit receive FIFO) register, 22-16 RXTWI8 (8-bit receive FIFO), 22-15

TWI controller registers (continued) TWIMADDR (master mode address), A-247 TWIMCTL (master mode control), A-245 TWIMSTAT (master mode status), A-248 TWISADDR (slave mode address), A-251 TWISCTL (slave mode control), A-250 TWISSTAT (slave mode status), A-252 TXTWI16 (16-bit transmit FIFO), 22-14 TXTWI8 (8-bit transmit FIFO), 22-13 two channel mode (S/PDIF), 14-12 TXFLSH (flush transmit buffer) bit, 16-38, A-224 TXS_A (data buffer channel B status) bit, A-164 TXSPI, TXSPIB (SPI transmit buffer) registers, A-228 TXSPI (SPI transmit buffer) register, 3-10, 16-23, 16-34 TXSPx (serial port transmit buffer) registers, 3-10 TXSR (SPI transmit shift) register, 16-8 TX_UACEN (DMA transmit buffer enable) bit, 21-4

U
UART, 21-1 baud rate examples, 21-5 bock diagram, 21-7 buffers, 21-9 chained DMA, 3-16, 21-15 core transfers, 21-13 data ready flag, 21-13 divisor, 21-4, A-234 divisor reset, 21-4 DMA transfers, 21-14

I-34

ADSP-214xx SHARC Processor Hardware Reference

Index

UART (continued) reset, 21-4, 21-14 shift registers, 21-9 standard, 21-1 timers, 21-6 UART bits 9-bit RX enable (RX9), A-235 9-bit TX enable (TX9), A-235 address detect enable (UARTAEN), A-235 DMA TX/RX control, A-233 DMA TX/RX status, A-242 enable receive buffer full interrupt (UARTRBFIE), A-239 enable transmit buffer empty interrupt (UARTTBEIE), A-239 interrupt enable, A-240 pack data, 21-8 packing enable (PACK), A-235 pin status (UARTPSTx), A-235 program controlled interrupt bit (PCI), 21-22 synch data packing in RX (UARTPKSYN), A-235 THR register empty (UARTTHRE), A-238 UARTNOINT (pending interrupt), A-241 UARTSTAT (interrupt), A-241 UART registers divisor latch register (UARTxDLL), 21-4, A-234 divisor latch (UARTxDLH), 21-4, A-234 interrupt enable register (UARTxIER), A-239 interrupt identification register (UARTxIIR), A-241 line control register (UARTxLCR), A-236

UART registers (continued) line status register (UARTxLSR), A-238 shift, 21-9 UARTxDLH (divisor latch register), 21-4, A-234 UARTxDLL (divisor latch register), 21-4, A-234 UARTxIER (interrupt enable register), A-239 UARTxIIR (interrupt identification register), A-241 UARTxLCR (line control register), A-236 UARTxLSR (line status register), A-238 unchained (single block) DMA complete, 3-45

V
VCO bypass clock, 23-7 clock, 23-5 examples, clock management, 23-14 output clock, 23-5

W
wait states, enabling (WS bit), A-29 warnings and cautions DMA transfers, 3-28 I/O processor, 3-28 SPORTs, 11-44 watchdog timer block diagram, 20-6 clocking, 20-4 clock pin (WDT_CLKIN), 20-4 pin descriptions, 20-3 register descriptions, 20-3 specifications, 20-1 starting, 20-7 trip count mode, 20-6

ADSP-214xx SHARC Processor Hardware Reference

I-35

Index

WDTH_CAP (width capture) mode, 17-2, 17-12, 20-2 window processing, IIR, 7-65 window size (IIR), A-90 word packing enable (packing 16-bit to 32-bit words), A-160

write-1-to-clear bit description (W1C), A-4 write-only bit description (WO), A-4 write-only-to-clear bit description (WOC), A-4 write-only-to-clear bit type description (WOC), A-4

I-36

ADSP-214xx SHARC Processor Hardware Reference