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Rfic Asignment

This document contains an assignment description for an RF integrated circuit design course. It includes 6 practice problems related to topics of units, linearity, and noise in RF circuit design. Problem 1 involves calculating the output swing required to deliver a specified power level to an antenna. Problem 2 examines the gain and filtering required for a desired signal in the presence of a blocking signal at the input of an LNA. Problem 3 derives an expression for the input amplitude where second order intermodulation products equal the fundamental. Problem 6 calculates the noise factor of a circuit and how a parasitic capacitance affects it.

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Kunal Khandelwal
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141 views

Rfic Asignment

This document contains an assignment description for an RF integrated circuit design course. It includes 6 practice problems related to topics of units, linearity, and noise in RF circuit design. Problem 1 involves calculating the output swing required to deliver a specified power level to an antenna. Problem 2 examines the gain and filtering required for a desired signal in the presence of a blocking signal at the input of an LNA. Problem 3 derives an expression for the input amplitude where second order intermodulation products equal the fundamental. Problem 6 calculates the noise factor of a circuit and how a parasitic capacitance affects it.

Uploaded by

Kunal Khandelwal
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE 6730: RF Integrated Circuit Design

Spring 2009

Assignment #1 Topics: Units, Linearity, Noise Due Date: Jan. 29, 2009

Problem 1: Suppose we wish to deliver 14.3 dBm of power to a 50 antenna at 1.9 GHz. (a) What is the peak-to-peak output swing required of the power amplier, assuming a sinusoidal output? (b) Repeat part (a), but this time assume that the output is a triangle wave. Problem 2: We are designing a system with an LNA whose behavior can be modeled as: y(t) = 1 x(t) + 2 x2 (t) + 3 x3 (t) (1) where 1 = 10, 2 = 2, and 3 = 0.5. The inputs to the LNA are a desired signal at 1 with a peak amplitude of 1 mV, and a blocking signal at 2 with a peak amplitude of 2 V. (a) Assuming that no ltering takes place before the LNA, what is the gain (in dB) for the desired signal? (b) If we plan on inserting a SAW (surface acoustic wave) lter before the LNA, and the minimum gain for the desired signal is 19.5 dB, by how many dB must the lter attenuate the blocking signal at 2 ? Problem 3: In class we discussed the IP3 for a system, which quantied the size of the third order intermodulation products (output components at 21 2 , 22 1 ) relative to the fundamental. In some systems we are more interested in the size of the second order intermodulation products (output components at 1 2 , 2 1 ) relative to the fundamental. (a) Assuming that the system can be modeled as in (1) from the previous question, derive an expression for the AIP 2 point (the input amplitude for which the second order IM products are equal to the fundamental). (b) Suppose we know that for an input power of -40 dBm, the power of the fundamental components at the output is -10 dBm and the power of the IM2 components is -50 dBm. What is the IIP2 (input second intercept point) of the system?

ECE 6730: RF Integrated Circuit Design

Spring 2009

Figure 1: Schematic for noise factor calculation. Problem 4: Suppose we have a system that is composed of two blocks, with the rst block having a gain of 1 = 10 and an input IP3 of AIP 3,1 = 1, and the second block having a gain of 1 = 2 and an input IP3 of AIP 3,2 = 1. (a) What is the input IP3 of the system as a whole? (b) What does the system input IP3 become if the order of the blocks is reversed? (c) What does this tell us about how we should distribute the gain in a system if we want to try and maximize the linearity? Problem 5: Lee: Chapter 11, Problem 6. Problem 6: Consider the circuit in Fig. 1. Ignore CGD , rO , body eect, and induced gate noise. Assume all transistors are biased in the saturation region. (a) Calculate the noise factor of the circuit. (b) Cp is a parasitic capacitance that is inuenced by the physical layout of the circuit. How does its presence aect the overall noise factor, and should it be minimized or maximized?

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