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Practical

This document contains 16 figures showing various digital logic circuits including NMOS pass transistor logic, inverters, NAND gates, NOR gates, XOR gates, XNOR gates, buffers, D flip-flops, D latches. For each figure, there is a brief description of the circuit elements and its input-output logic functionality. The document also calculates the Vinv voltage of an inverter and defines the setup time of a D flip-flop using CMOS as the time before clock arrival that the input must be stable to ensure the correct output.

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Sumeet Saurav
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© Attribution Non-Commercial (BY-NC)
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Download as DOCX, PDF, TXT or read online on Scribd
19 views

Practical

This document contains 16 figures showing various digital logic circuits including NMOS pass transistor logic, inverters, NAND gates, NOR gates, XOR gates, XNOR gates, buffers, D flip-flops, D latches. For each figure, there is a brief description of the circuit elements and its input-output logic functionality. The document also calculates the Vinv voltage of an inverter and defines the setup time of a D flip-flop using CMOS as the time before clock arrival that the input must be stable to ensure the correct output.

Uploaded by

Sumeet Saurav
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Practical List

Figure 1 NMOS DC characteristic (Id v/s Vds at Vgs=1v) .............................................................................. 2


Figure 2: - NMOS Pass Transistor logic ......................................................................................................... 2
Figure 3: - Inverter DC Characteristic ............................................................................................................ 3
Figure 4: - Inverter DC characteristic with calculation of Vinv ..................................................................... 3
Figure 5: - Inverter output ............................................................................................................................ 4
Figure 6: - Two input NAND gate .................................................................................................................. 4
Figure 7: - Three input NAND gate ................................................................................................................ 5
Figure 8: - Nor gate ....................................................................................................................................... 5
Figure 9: - Xor gate using cmos ..................................................................................................................... 6
Figure 10: - Xor using transmission gate ....................................................................................................... 6
Figure 11: - Xor using 5 transistors ............................................................................................................... 7
Figure 12: - Xnor using 4 transistors ............................................................................................................. 7
Figure 13: - Buffer output ............................................................................................................................. 8
Figure 14: - D Flip Flop using CMOS .............................................................................................................. 8
Figure 15: - D Latch ....................................................................................................................................... 9
Figure 16: - DFF Setup time........................................................................................................................... 9

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Figure 1 NMOS DC characteristic (Id v/s Vds at Vgs=1v)

Figure 2: - NMOS Pass Transistor logic


Here green plot is showing input and red plot is showing output. From here it is evident
that NMOS can pass logic zero effectively but it passes degraded high logic that is with
threshold drop.

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Figure 3: - Inverter DC Characteristic

Figure 4: - Inverter DC characteristic with calculation of Vinv


Vinv of inverter is the voltage when input voltage and output voltage is equal so from
above figure it is 1.266v.

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Figure 5: - Inverter output


In above figure input is a, and output is q which are inverse of each other.

Figure 6: - Two input NAND gate


In above figure input is a, b and output is q which is showing NAND relationship (q = ab).
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Figure 7: - Three input NAND gate


In above figure input is a, b, c and output is q which is showing NAND relationship (q =
abc).

Figure 8: - Nor gate


In above figure input is a, b and output is q which is showing NOR relationship ( q = a+b).

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Figure 9: - Xor gate using cmos


In above figure input is a, b and output is q which is showing XOR relationship (q = a b).

Figure 10: - Xor using transmission gate


In above figure input is a, b and output is vout which is showing XOR relationship
(vout = a b).
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Figure 11: - Xor using 5 transistors


In above figure input is a, b and output is vout which is showing XOR relationship
(vout= a b). This circuit is implemented by using minimum number of transistor (5
Transistor) and it is working perfectly.

Figure 12: - Xnor using 4 transistors


In above figure input is a, b and output is vout which is showing XNOR relationship
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(vout =a b). This circuit is implemented by using minimum number of transistor (4


Transistor) and it is working perfectly, only a threshold drop in output comes when both
inputs are high as shown above.

Figure 13: - Buffer output


This buffer is implemented by using back to back inverter, where output q is perfectly
replica of input a.

Figure 14: - D Flip Flop using CMOS


From above figure it can be seen that output q is changing its value at rising edge of
clock pulse and qbar is just opposite of output q.
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Figure 15: - D Latch


Above figure is showing output of a D Latch. Where output Qn is changing according to
input D only at the high level of clock pulse.

Figure 16: - DFF Setup time


Set up time is the time before the arrival of clock for which input should be at proper
level to get desired output. As in above figure clock (50%) is coming at time 1.53ns and if
input D (50%) is coming after 1.43ns then we will get low output but to get high output
input D (50%) should come before or at 1.43ns. So set up time for above circuit is 10ns.
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