Scribd
Upload
85 views

Static Random Access Memory

This document discusses random access memory (RAM) and static RAM (SRAM). It provides an overview of RAM, explaining that RAM contains words of information that can be read and written using addresses. It describes SRAM and dynamic RAM (DRAM), noting that SRAM uses latches to store data permanently while DRAM requires refreshing. The document discusses RAM timing and interfaces, addressing in RAM, and the internal components of RAM like decoders that select individual words.

Uploaded by

Palash Swarnakar
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
85 views

Static Random Access Memory

This document discusses random access memory (RAM) and static RAM (SRAM). It provides an overview of RAM, explaining that RAM contains words of information that can be read and written using addresses. It describes SRAM and dynamic RAM (DRAM), noting that SRAM uses latches to store data permanently while DRAM requires refreshing. The document discusses RAM timing and interfaces, addressing in RAM, and the internal components of RAM like decoders that select individual words.

Uploaded by

Palash Swarnakar
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 19

1/23/2006 HY220: Iukeo Muupocioq 1

HY220
Static Random Access Memory
1/23/2006 HY220: Iukeo Muupocioq 2
Overview
Memory is a collection of storage cells with associated input
and output circuitry
Possible to read and write cells
Random access memory (RAM) contains words of
information
Data accessed using a sequence of signals
Leads to timing waveforms
Decoders are an important part of memories
Selects specific data in the RAM
Static RAM loses values when circuit power is removed.
1/23/2006 HY220: Iukeo Muupocioq 3
Comments about Memory Access and Timing
Most computers have a central processing unit (CPU)
Processor generates control signals, address, and data
Values stored and then read from RAM
The timing of
the system is
very
important.
Processor
provides data
for the cycle
time on writes
Processor
waits for the
access time
for reads
1/23/2006 HY220: Iukeo Muupocioq 4
Memory Arrays
1/23/2006 HY220: Iukeo Muupocioq 5
Types of Random Access Memories
Static random access memory (SRAM)
Operates like a collection of latches
Once value is written, it is guaranteed to remain in the memory as
long as power is applied
Generally expensive
Used inside processors (like the Pentium)
Dynamic random access memory (DRAM)
Generally, simpler internal design than SRAM
Requires data to be rewritten (refreshed), otherwise data is lost
Often hold larger amount of data than SRAM
Longer access times than SRAM
Used as main memory in computer systems
1/23/2006 HY220: Iukeo Muupocioq 6
Ao Kotqyopr Mvqq
Static RAM (SRAM)
Arovo ono0qkrovto or Latch.
+Totrpq npoonKooq vqq.
+Arv pr(rto refreshing.
+KoKq ounrppo otov 0puo.
-MryoKtrpo yr0o on DRAM.
Dynamic RAM (DRAM)
Arovo ono0qkrovto or
opto dynamic node.
+Mkp yr0o vqq.
-Xpr(rto refreshing Kym
leakage. Ho opyq on SRAM.
-HpoKqoto r 0puo (noise).
data
write/read
data
write/read
C
storage cell
storage cell
1/23/2006 HY220: Iukeo Muupocioq 7
RAM Interface Signals
Data input and output
lines carry data
Memory contains 2
k
words
k address lines select
one word out of 2
k
Read asserted when data
to be transferred to
output
Write asserted when data
input to be stored
1/23/2006 HY220: Iukeo Muupocioq 8
Random Access Memory Fundamentals
Lets consider a simple RAM chip
8 words of 2 bytes each (each word is 16 bits)
How many address bits do we need?
01010000 11100110
11001100 11111111
00000000 10101010
01010110 00111111
11111111 00000000
00000001 10000000
01010101 11001100
00000000 11111111
word
Pick one of 8 locations
Dec Binary
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
16 Data and Input signals
____ address signals
Each bit stored in a binary cell
1/23/2006 HY220: Iukeo Muupocioq 9
Apiskovikq
Apiskovikq
Mvqq
Mvqq
R
o
w

D
e
c
o
d
e
r
Row Address
Storage cell
Word line
Bit line
Sense amplifiers(read)/
Drivers (write)
Column decoder
Column Address
Data I/O
Read: select desired bits
Write: do not write unwanted bits
1/23/2006 HY220: Iukeo Muupocioq 10
Inside the RAM Device
Address inputs go
into decoder
Only one
output active
Word line selects a
row of bits (word)
Data passes
through OR gate
Each binary cell
(BC) stores one bit
Input data stored if
Read/Write is 0
Output data driven
if Read/Write is 1
1/23/2006 HY220: Iukeo Muupocioq 11
Inside the SRAM Device
Note: delay primarily
depends on the number
of words
Delay not effected by
size of words
How many address
bits would I need for
16 words?
Word
1/23/2006 HY220: Iukeo Muupocioq 12
Array Architecture
1/23/2006 HY220: Iukeo Muupocioq 13
Six transistor CMOS SRAM cell.
Six transistor CMOS SRAM cell.
word
line
bit
bit
Otov q word line rvrpyonorto (V
DD
) ttr q tq tou Latch
o(rto oto bit ko bit kot to ooo tq vqq q q tq tou
Latch yprto on to bit ko bit kot tqv ryypoq tq vqq.
1/23/2006 HY220: Iukeo Muupocioq 14
SRAM Banks
SRAM Banks
1/23/2006 HY220: Iukeo Muupocioq 15
Read Operation
Read Operation
1/23/2006 HY220: Iukeo Muupocioq 16
Write Operation
1/23/2006 HY220: Iukeo Muupocioq 17
Example 1 : Combination of Read/Write
1/23/2006 HY220: Iukeo Muupocioq 18
Example 2: Combination of Read/Write
1/23/2006 HY220: Iukeo Muupocioq 19
Summary
Memories provide storage for computers
Memories are organized in words
Selected by addresses
SRAMs store data in latches
Accessed by surrounding circuitry
RAM waveforms indicate the control signals needed for
access
Words in SRAMs are accessed with decoders
Only one word selected at a time

You might also like