Digital Network Synchronization

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Digital Network Synchronization By Jorge E. Rodriguez

9. - Conclusion. Appendix A. References.

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I. Abstract: The digital network synchronization topic is one of the fascinating areas in telecommunication today. With the new technologies like SONET and ISDN, synchronization plays a major role. The goal of having one single source of clock in the whole network has been something that almost every network designer has wanted. The impairments such as jitter, wander and slips make it difficult to achieve the synchronization with the synchronous mode implemented today. Synchronous mode is based on the master-slave method. The master-slave method uses a PRS (Primary Reference Source) clock, known some times as stratum level 1, from where the rest of the switches are synchronized. Depending on the performance required, four stratum levels were approved based on their characteristics of accuracy and stability. There are two types of technology used for the stratum clocks nowadays: the atomic clocks and the quartz clocks. The difference is based on accuracy, stability and cost. The synchronous mode represents too many challenges in order to accomplish synchronization in the network; but thanks to the improvements in the technology and the reduced cost in the atomic clocks technology, the plesichronous mode could be the direction that need to be implemented in the future. The plesichronous mode means that each node's clock runs independently of each other.Because they use very high frequency accuracy, the slip rate is diminished, resulting in a better-synchronized digital network.

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1. Introduction: The concept of timing is central to the operation of a digital telecommunications network. A digital network consists of digital switches interconnected by digital transmission facilities. Every switch has its own clock that determines the bit rate on the digital links emanating from it. Digital Networks are based on hierarchical bit rates of 1,544 kbit/s and 2,048 kbit/s. Pulse code modulation (PCM) information is organized in frames that in turn consist of several timeslots or channels. The 8-bit time slot repeated 8000 times per second, gives the 64 kbit/s capacity per channel. For a common connection, the timeslots are switched through several offices and transported over the transmission links. All the timeslots are grouped together in order to form a frame, which could have 24 channels for a digital network of 1,544 kbit/s or 30 channels for a digital network of 2,048 kbit/s. Each frame has a framing bit or bits, which are used to perform frame alignment. Frame alignment is performed by identifying the beginning of a frame in the incoming bit stream. Once we have achieved the alignment, the timeslots are identified and switched by virtue of their position in time with respect to the beginning of the frame. To receive and switch timeslots arriving on the incoming link correctly, the digital switches in the network must maintain the same clock rate. The goal of synchronization is to achieve a common clock rate for the digital switches. For synchronizing the switches, timing has to be transported on digital links. The timing conveyed on the link is in terms of frequency and not as date, hours, minutes and seconds. To resolve timing issues, we need to do two things: first, to achieve synchronization for the digital switches and second, to minimize the presence of transmission impairments such as jitter and wander. Digital switches via Time Slot Interchange (TSI) are accomplished by the rearrangement of timeslots of digitized information. These timeslots need to occur at the same rate. If all the time slots were created at one switch, there would be no need for network synchronization [1]. When digital switches are connected by digital transmissions systems, time slots created in one office will be switched at another office, so these offices need to be synchronized in order to be able to receive the correct bits in the correct time in the correct timeslot. The technologies like ISDN (Integrated Services Digital Network) and SONET (Synchronous Optical Network), as well as the growth in data services, have been pushing for a better and accurate synchronization network and a better synchronization architecture too. Timing issues assume enhanced significance in an integrated services digital network (ISDN) that aims at supporting a wide range of services, both voice and data (nonvoice). To ensure satisfactory provisioning of ISDN services, one requirement is to minimize the occurrence of events called slips. Jitter, wander, slips and other concepts will be explained in more detail in this document.

2. Frame Formats _____________________________________________________________________________________

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_____________________________________________________________________________________ There are several frame structures depending the speed we need to achieve; the different synchronous frame structures used today according to the ITU-T G.704 are: 1,544, 6,312, 2,048, 8,488 and 44,736 kbit/s hierarchical levels [2]. This document will explain the 1,544 and the 2,048 kbit/s only, for better understanding of how and where the framing bit or bits are located, and the impact of loosing or not recognize these F (framing) bits due jitter or wander. 2.1.- Basic frame structure at 1,544 kbit/s: This frame structure known as DS-1 has 193 bits, numbered 1 to 193. One frame consists of 193 bits and is repeated 8000 times per second to form a 1.544 Mbit/s signal rate. The frame consists of 24 channels or timeslots of 8 bits in each one. The F-bit, or frame bit, is the first bit (bit number 1) of the frame and is used for the frame alignment process [2]. Not being able to identify this F-bit will cause the loss of synchronization. In order to achieve synchronization on the DS-1, two methods were designed for the allocations of the F-bits. Method 1: The use of a multiframe of 24 frames, where the F-bit in the frames 4, 8, 12, 16, 20 and 24 is used for the synchronization with the pattern 001011 [2]. This multiframe alignment pattern is used to identify where the multiframe begins and where it ends. Knowing the beginning and end of each frame, the timeslots can be extracted from the frames and retransmitted towards their final destination. A more detailed representation of the bit number one besides the use of farming is explained in table A-1. Method 2: The use of a multiframe of 12 frames, where the F-bit in the odd frames (1,3,5,7, etc.) is alternated from 1 to 0, so the pattern will be 101010 in the frames 1,3,5,7,9,11 respectively [2]. A more detail representation of the bit number one besides the use of framing is explained in table A-2. 2.2. - Basic frame structure at 2,048 kbit/s: This frame structure known as E-1 has 256 bits, numbered 1 to 256. One frame consists of 256 bits and is repeated 8000 times per second to form a 2.048 Mbit/s signal rate. Unlike DS-1, the E-1 has 32 channels numbered 0 to 31, but only 30 are used to transmit information (voice or nonvoice), the other 2 channels are used for synchronization and signaling. The synchronization bits are located in channel zero whereas several bits are used [2]. The E-1 uses a multiframe of two sub-multiframes. Each sub-multiframe consists of 8 frames [2]. Because E-1 uses a complete channel of 8 bits for synchronization, there is no one single bit for framing. There are several bits for framing spread among the 8 bits in conjunction with the multiframe. A more detail description of the use of these 8 bits is explained in table A-3. 2.3. - Basic frame structure of SONET: The basic building block of the SONET digital transmission hierarchy is called the STS level one (STS-1) frame. The basic STS-1 SONET frame consists of 810 bytes, transmitted 8000 times per second to from a 51.840 Mbit/s signal rate. The STS-1 unlike DS-1 or E-1 uses a different way to synchronize, so the frame has three different areas, which are used for that purpose called: Path, Line and Section.

3. - The Impact of Jitter and Wander on Digital Network Synchronization. Jitter and wander are impairments of digital signals caused by clocks that generate those digital signals and multiplexers that transport those digital signals. 3.1. - Jitter: _____________________________________________________________________________________
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Jitter is the short-term variations of the significant instants of a digital signal from their ideal position in time. Figure 3.1 represents a jitter-free signal; the digital pulses are perfectly aligned with their ideal position. Figure 3.2 represents a digital signal by the presence of jitter, the digital pulses are distributed from their ideal position, and the intervals between the pulses are no longer uniform. The displacement of the digital pulse with respect to its ideal position represents the jitter amplitude or phase variation. Jitter amplitude is specified in terms of the unit interval (UI). A UI is the interval t between the pulses of the jitter-free signal. The value of one UI for 1.5444 Mbit/s is 648 ns, and for 2.048 Mbit/s is 488 ns. Jitter amplitude may also be specified in degrees or radians, where one UI is taken as 360 or 2 respectively.

1t Unit Interval t

2t

3t Time

Figure 3.1 digital bit stream spaced uniformly in time

1t Unit Interval t

2t

3t Time

Figure 3.2 digital bit stream impaired by the presence of jitter. Several sources of jitter exist in a digital network. Regenerators and multiplexers on the transmission link are sources of jitter. The clock that generates the digital signal itself introduces jitter. Regenerators are required over long transmission links. The incoming bit stream of weak and noise-laden pulses is regenerated into a new bit stream. For this purpose, timing information is extracted from the incoming pulses. The imperfection associated with the time extraction process contributes to jitter in the regenerated bit stream. Digital multiplexers and demultiplexers also introduce jitter. Digital multiplexers combine several low-rate bit streams (input tributaries) to form a single higher-rate time division multiplexed (TDM) bit stream. The reverse function is performed by demultiplexers. During the process of multiplexing and demultipexing is where the jitter is added. This could be because the clock rate at the input signal of the multiplexer is not the same as the clock rate of the other multiplexer at the other end. This is known as stuffing bits. Multiplexers use stuffing bits to accommodate frequency differences between lower rate payload signals. The removal of these stuffing bits in the demultiplexing process also produces jitter. Jitter can affect digital signals in two ways: First, high-speed jitter may lead to errors due the inability of equipment to sample the incoming bit-stream correctly. Second, jitter may lead to overflow or underflow of synchronizer and desynchronizer buffers (elastic buffers). These buffers are in multiplexers, providing the interface to the lower speed systems, and are usually only several bits long. Jitter can be controlled in synchronization distribution network by requiring stratum clocks to be able to accept inputs with high level of jitter and to be able to generate outputs with low levels of jitter. _____________________________________________________________________________________
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_____________________________________________________________________________________ 3.2. - Wander: Wander is the long-term variation of the significant instants of a digital signal from their ideal position in time. Wander is generally cyclic in its incidence and is introduced largely by environmental factors, such as temperature differences over the length of a transmission link [3]. In a synchronized network, clocks are locked to a timing reference. Because the locking mechanism is imperfect, wander is introduced. Wander can affect service in the following two ways: DS-1 slips performance and jitter caused by pointer adjustments for DSn signals carrier on SONET. The main source of wander is synchronized clocks. Synchronized clocks use some control mechanisms to maintain lock with their reference. This control mechanism leads to wander, sometimes referred to as clock breathing. A Bellcore study showed that 3.5 microseconds (5.4 UI) of wander occurred on a DS-1 signal carried over 150 miles of aerial copper cable that experienced a 36 degree Fahrenheit change in temperature. While this is an extreme case, it illustrates that temperature variation can affect wander. 4. - Slips. Slips occur at the memory buffers terminating the incoming link, and they arise due to frequency inequalities of the clocks in the network. Without the buffers, any small change in the clocks frequency between the incoming bit stream and the switching end office clock, the slips would occur in an uncontrolled manner. Under normal operation of a switch or repeater, the bits arrived at frequency x and are written into the buffer from where they are read and transmitted at frequency y. If frequency x and frequency y are equal, as soon as one bit is written into the buffer, the same bit is read it from it, so the system runs evenly, in a perfect harmony (synchronized). That is not always the case. As we explained before, there is jitter and wander that slow down the transmission and there are some other factor that increase the speed on the clocks in the network. When we have some changes in the network, we have to adjust the system in order to overcome the effects. We call elastic buffers or slip buffers. Lets assume the incoming bit rate stays normal, but the outgoing bit rate for some reason accelerates. In this case, the outgoing rate is going to read the buffer faster that the incoming bit is written, so the switch is going to send a duplicate bit (the same bit that just sent) and is going to cause a slip. But what happens if now the incoming bits are getting faster and are written into the buffer as soon as they arrive, but the outgoing rate stays normal, eventually the outgoing clock is going to miss a bit or frames. At that time, we have an other type of a slip. Slips occur because the rate of the incoming bits is different of the outgoing bits rate causing sometimes overflow or underflow to the buffers, which is translated to send a repeated bit or frame, or the loss of a bit or frame. Figure 4.1 shows a digital switch B receiving a 24-channel DS-1 bit stream from two other switches, A and C. The switches have local clocks with the same nominal frequency, but due to differing departures from the ideal value, their actual frequencies may be different. Each digital link in the switch is terminated in a memory buffer. The frames are transmitted from switch A at the bit rate determined by frequency a of the switch A clock. At switch B, the clock is extracted from the incoming bit stream and the time slots are written in the memory buffer at the clock frequency a. The memory buffer is read, at the frequency b of the switch B clock. Because a and b are not identical, the read and write rates differ and buffer M1 would eventually overflow or underflow, resulting in a slip. Overflow arises when writing is faster than reading (a >b) and a block of bits sent from switch A to Switch B are lost at switch B. The underflow situation is when reading is faster than writing (b > a) and a block of bits is read it twice. The same effect is shown between exchange C and B. _____________________________________________________________________________________
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Buffers

Exchange

Write fa Bit Stream at frequency fa

M1 Read

Exchange

M2 Read

Write fc Bit Stream at frequency fc

Exchange

Read frequency fb Figure 4.1. Controlled Slips on memory buffers.

Slips occurring at the memory buffers are called controlled slips. The buffers in the switch are called aligners. The size of the aligners determines the amount of bit skipped or repeated during a slip. The aligners sizes are normally one or two frames [1,3]. Aligners are used to absorb a certain amount of transmission impairments such as jitter and wander. The use of buffers will introduce propagation delay time, so the correct size of the buffers (how many frames it should hold) is based on a trade-off between delay and clock stability. The propose of digital network synchronization is to minimize slips caused by network impairments. One solution is to operate the network at a common clock rate. This buffer is often called an elastic store or buffer, because it is used to accommodate the different frequencies of the read and write operations. To handle this potential problem, a common practice is to read from the buffer at a slightly higher rate than the maximum expected write rate (which is the maximum rate sent from a transmitting machine). With this approach, the write operation cannot overtake the read. Periodically, the read is halted, and a bit is stuffed in the stream to handle the timing difference between the read and write operations. Al inputs are read by the same clock and their streams are bit-stuffed to equal a common rate, so they are synchronized together [4].

Slips are either controlled or uncontrolled. The controlled slips do not affect the framing bit (Fbit) and therefore do not propagate to any subsequent back-to-back frames. This is done by extracting the framing information before the slip buffer. Slip buffers are also used to retime a signal at points where the DS-1 or E-1 path are not terminated and the framing information cannot be extracted before the buffer. When these buffers overflow or underflow, the framing information is lost and this is called uncontrolled slips. The uncontrolled slips may cause loss of alignment and sometimes desynchronization in the network. The effect of a slip depends on the type of service being carried by the digital line. For voice conversations, a slip may be unnoticeable or may create a pop. In order to be noticeable, the slip rate has to be very high. During the transmission of digital data, a slip will cause that the information be delivered with errors and it must be retransmitted. If the slips rate is too high, this will cause degradation in the throughput. _____________________________________________________________________________________
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_____________________________________________________________________________________ Slips have a very serious effect on data that is transmitted over analog circuits via modems. Most modems use the phase of a carrier signal to send data. A slip looks like a 45 degrees shift on a 1 kHz carrier. Studies have shown that analog modems make take up to 6 seconds to recover from a slip [1]. Other work has shown that slips can lead to 0.08 inches of vertical space being missed in a fax transmission [1]. 4.1 Network performance objectives for slip control. Slips cannot be entirely eliminated in practical network. Therefore is necessary to specify the maximum permissible slip rate that would permit satisfactory provisioning of services in an ISDN. ITU-T recommendation G.822 specifies the end-to-end controlled slip-rate for international digital connections. With plesiochronous operation, the number of slips on the international links will be governed by the size of buffer stores, the accuracy, and the stability of the interconnecting national clocks [5]. Some considerations under ITU-T G.822 are: The end-to-end sip rate performance should satisfy the service requirements for telephone and non-telephone services on a 64-kbit/s digital connection in an ISDN. The slip rate objectives for and international end-to-end connection are stated with reference to the standard digital Hypothetical Reference Connection (HRC) of 27,500 km in length. It is recognized that one slip in 70 days per plesiochronous interexchange link is the resulting maximum theoretical slip rate. For 64 kbit/s end-to-end connections, controlled slips rates are defined in three categories. The slip rate may significantly exceed the value above due to variations design, environmental and operational conditions in international and national sections. Table 4.1 Controlled Slip rate performance on a 64 kbit/s international connection (ITU-T G.822) [5]. Performance Category (a) (b) (c) Mean Slip Rate 5 slips in 24 hours > 5 slips in 24 hours and 30 slips in 1 hour > 30 slips in 1 hour Proportion of time (Total Time 1 Year) > 98.9% < 1.0 % < 0.1 %

For most of the time (98.9%), no more than 5 controlled slips per day are allowed, this is indicated by category (a). Slips rates within this threshold satisfy performance requirements for ISDN services. In addition to the mean slip rate for end-to-end international connection, a breakup of slip rates for the national and international portions of the connection is useful, so that the national synchronization network may be planned to meet these standards. ITU-T G.822 specifies the allocation for the national and international portions of a connection. Table 4.2 specifies the allocation of controlled slips performance. To the national network section was allocated 46% (40% for the local portion and 6% for the national transit portion). The national transit portion of the national network carries a high volume of traffic, and any degradation of performance will have networkwide (national) impact, so 6% is very well understandable. On the other hand, 40% of the slips are permitted into the local portion of the network, so the quality of the clocks used in the digital switches can be chosen based on their hierarchical level in the network. _____________________________________________________________________________________
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Table 4.2 Allocation of controlled slip rates (ITU-T G.822) [5] Portion of HRX International transit Each national transit portion Each local portion Allowed Percentage of Permissible Slip Rates 8.0 % 6% 40%

By combining tables 4.1 and 4.2, it can be seen that for performance category (a), not more than two slips every 24 hours are allowed for the local portion of the national network, one slip every 80 hours is allowed for the national transit portion and one slips every 60 hours is allowed for the international transit. 5. - Description of commercial available clocks to time a Digital Network The clock in network synchronization plays a very important role, because the accuracy or inaccuracy of it will impact the behavior of the network; like not be able to identify the framing information bits resulting of loss of synchronization. There are two categories of digital clocks: atomic clock and quartz clocks. Three types of atomic clocks are available commercially: cesium beam clock, rubidium clocks, and hydrogen master clocks. Cesium beam clock are of prime interest for telecommunications applications due to their excellent longterm frequency accuracy and stability (of the order of 1 x 10 -11 or better) [3]. Cesium beam clocks are primary frequency standards. They do not require frequency calibration from other source, and they maintain their frequency accuracy and stability throughout their operating life. The cesium beam tube is the main component of a cesium clock. The life expectancy of the tube is about 5 years [3]. The rubidium clocks are particularly suitable for calibrations and testing applications because of their excellent short-term stability and retrace capability (that is, rubidium clocks are able to reach their nominal frequency quite rapidly after a cold restart). The long-term stability of rubidium clocks is limited to 1 x 10-11 / month [3], therefore, this makes their use inappropriate as a primary standard for network synchronization in which better long-term stability is needed. The hydrogen master frequency standard, which is among the most expensive atomic clocks available; despite having the best short-term and long-term frequency stability, it suffer on account of limited frequency accuracy. Therefore, the hydrogen master is not used for network synchronization. A quartz clock uses a quartz crystal unit in an oscillator circuit. The frequency of quartz clocks varies with time due to both internal and external environmental factors. Aging rates vary from 1 x 10-4 / day to 1 x 10-11 / day [3]. Changes in external factors such as temperatures, pressure, magnetic field, and acceleration also contribute to frequency departure of quartz clocks. The frequency departure with time due to the combined effect of aging and environmental factors is called drift. Quartz clocks are used widely in the synchronization of the digital network nodes. 6. - Synchronization methods. There are two types of clock operations in the digital synchronization networks: Plesiochronous mode and synchronous mode. The plesiochronous mode is applied to international networks connections and the synchronous mode is used for the national synchronization network. 6.1 Plesiochronous mode. In the plesiochronous method high-quality clocks are used in the switch, and allowed to run independent of each other. Clocks operating autonomously in this manner are said to be free running, as _____________________________________________________________________________________
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_____________________________________________________________________________________ no external timing control is applied to them. To meet the slip-rate parameters while operating in this mode, the clock should have very high frequency accuracy. Using the plesiochronous mode means that the switches do not have to be synchronized with each others. Because of that, the slip rate between the nodes is very low. This mode of operation is one of the simplest to implement, since it avoids distributing time throughout the network. In actual practice, the clock used for plesiochronous operations is based on cesium beam technology. At present, plesiochronous operations are used for international links [5]. However, the use of this mode in the national network in the future is a possibility. 6.2 Synchronous mode. The use of the synchronous mode leads to network synchronization. To force the various network clocks to operate on the same frequency, each clock in the network must be able to receive an external reference frequency. Two techniques are used to achieve the synchronization in the digital networks today: master-slave method and mutual synchronization method. 6.2.1 Master-slave method. As the name implies, the various network clocks are locked to a master frequency source. The master clock is the primary reference source (PRS). It delivers a frequency output called primary reference frequency or timing. The primary reference timing is therefore supplied to a limited number of nodes, because it is not possible to deliver the timing to all the nodes from just one PRS [1]. The hierarchical method of synchronization in the master-slave method is based on stratum levels (performance levels). The stratum levels for synchronization clocks are based on three parameters. 1. - Free-run accuracy: Is the maximum fractional frequency offset that a clock may have when it has never had a reference or has been in holdover for an extended period greater than several days or weeks that there is no influence of synchronized operation on its frequency accuracy. 2. - Holdover stability: Is the amount of frequency offset that a clock experiences after it has lost its synchronization reference. Although such an event is rare, holdover stability is an important parameter since slip rate depends on the holdover stability of the slave clock until reference timing is restored. 3. - Pull-in/Hold-in: Is a clocks ability to achieve or maintain synchronization with a reference that may be off-frequency. A slave clock receives timing reference from the same or higher stratum level. Table 6.1 shows the stratum levels specifications according to Bellcore GR-436-CORE Digital Network Synchronization Plan [1]. Table 6.1 Stratum Level Specifications Stratum Level 1 2 3E 3 4 Stratum 1: Stratum 1 is the highest level clock; its clock is required to have a long-term accuracy of better than 1x10-11 completely autonomous of other frequencies. Currently, cesium beam references are the only _____________________________________________________________________________________
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Free-Run Accuracy 10-11 1.6 x 10-8 4.6 x 10-6 4.6 x 10-6 32 x 10-6

Holdover Stability N/A 1 x 10-10 per day 1 x 10-8 day 1 < 255 slips during first day of holdover No Holdover

Pull-in/Hold-in N/A 1.6 x 10-8 4.6 x 10-6 4.6 x 10-6 32 x 10-6

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_____________________________________________________________________________________ technology deployed in the network that are true stratum 1 clock in the sense that they achieve the required frequency accuracy autonomously. Therefore, all stratum 1 clocks can be use as PRSs, but not all PRS are stratum 1 clocks. Two technologies being used for PRSs that are not autonomous stratum 1 clocks are LORAN-C and Global Positioning System (GPS) navigational systems. LORAN-C and GPS are both being used in some telecommunications networks, as PRSS. LORAN-C is a land-based system that was developed for maritime navigation and is operated by the Coast Guard. GPS is a satellite-base system that was developed for the Department of Defense navigational needs and operated by the Air Force. The LORAN-C and GPS signals themselves are controlled by cesium standards that are not a part of the PRS. Bellcores GR-2830-CORE define two classes of PRS [7]: Network PRS - This class is for applications that are synchronization distribution hubs and has tighter requirements for redundancy and allowable periods of degraded performance. Office PRS - This class is for applications with limited synchronization distribution and relaxed requirements for redundancy and allowable periods of degraded performance. LORAN-C (Long Range Navigation, version C) is a terrestrial radionavigation system whose origins date back to the 1940s. To determine position on the earths surface, a receiver measures the time difference between the receipt of pulse signal from two pairs of transmitting stations. Each time difference corresponds to a hyperbolic line-of-position and the receiver position is at the intersection of the two resulting lines. According to the 1994 U.S. Federal Radionavigation Plan, the LORAN-C system is expected to remain part of the radionavigation mix until the year 2000, to accommodate the transition to GPS [7].

GPS (Global Positioning System) is a satellite radionavigation system that provides, among other services, very accurate position-determining information signals all over the world (earth). Highly accurate frequency as well as time-of -the day information is also available from the received signals. The GPS system consists of 24 satellites in six different circular orbits at an altitude of 20,180 kms [7]. The signals transmitted from all GPS satellites are at the same two navigation frequencies in the L-band: L1 at 1575.42 MHz and L2 at 1227.6 MHz. Civilian users make use of only the L1 frequency signal since L2 signal is encrypted [7]. Stratum 2: Stratum 2 clocks are based on either double oven crystal oscillators or rubidium atomic oscillators. Stratum 2 clocks have long time constants for averaging their input frequency reference. These types of clocks were historically deployed as part of tandem switches. Some standards for stratum 2 clocks do not require the use of two inputs reference or automatic protection switching when two references were provided. This is because of the quality of the stratum 2 holdover. Stratum 3 and 3E: Stratum 3 represents a large step down from stratum 2 clocks in terms of holdover performance. Stratum 3 clocks are based on temperature compensated crystal oscillators. Stratum 3 clocks are normally deployed in end offices and as slave clocks in offices with stratum 2 BITS. Stratum 3E is a new classification defined by GR-1244-CORE [8]. Stratum 3E requirements are a direct studies on network wander. The stratum 3E is required to filter a reference timing input with large amount of wander (up to the network limits) and to create a clean timing output with low levels of _____________________________________________________________________________________
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_____________________________________________________________________________________ wander. To achieve this filtering, a stable oscillator is necessary. This stable oscillator allows the stratum 3E to provide significantly better holdover performance. It is expected that stratum 3E requirements will necessitate the use of oven controlled crystal oscillator and digital filtering. Stratum 4 and 4E: Stratum 4 clocks are not used in the interoffice synchronization distribution network. Stratum 4 clocks no not provide holdover and enter free-run when they lose their reference. The application for stratum 4E clocks is normally in CPE, such as a digital PBX. Table 6.2. Slip rate in Holdover mode [1,3,8]. Stratum Level 2 3E 3 Slips on First Day of Holdover 1 or less 1 48 Slips in First Week of Holdover 2 22 919

PRS Primary reference timing Strarum 2 Reference timing Stratum 3 Reference timing Stratum 4
Figure 6.1. Principle of master-slave synchronization. The reference timing between network nodes is carried on existing digital links and the trafficcarrying capacity of the link is not affected. 6.2.2 Mutual synchronization method. In mutual synchronization, the nodal clocks synchronize each other. Each network nodes receives the reference frequency from all other nodes and operates at a frequency that is the mean of the frequencies of all the nodes in the network. Mutual synchronization it is not recommendable for large networks. _____________________________________________________________________________________
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Figure 6.2. Principle of a mutually synchronized network.

7. - Transport of timing. So far, the synchronization methods described above are used to transport timing across interoffice, but there is also a method to synchronize network nodes inside the offices which is called: BITS (Building Integrated Timing Supply). Intraoffice synchronization distribution is based on BITS. BITS use the master-slave model where its clock is chosen to be the master and from where the rest of the clocks inside the building are time locked. The BITS is the only clock that has a reference from another office. The BITS should be of the same or higher stratum level than all the other clocks in the office. The concept of BITS has three major advantages: Performance, use of resources and operations. Performance is one of the advantages because having a BITS inside each office improves reliability and availability of timing distribution. The use of resources is the second advantage because BITS allows shared use of equipment among services within the office. In addition, an operation is the third advantage because the BITS is location-dependent instead of service-dependent. All signals leaving the building are considered being of the stratum quality of the BITS clock, because failures of the BITS or its wiring to salved network elements are rare. During interoffice fault conditions the BITS is the only clock that should enter holdover, and all signals leaving the building should have frequency offsets no greater than that of the BITS clock.

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DS-1

BITS
DS-1 DS-1 DS-1 CC

Digital Switch

DCS

SONET

Channel Banks

Figure 7.1. Recommended BITS Implementation.

8. - Timing in SONET and SDH Abstract: This section describes the timing aspects in synchronous optical network (SONET) and synchronous digital hierarchy (SDH). The main points considered are: Frame format for SONET and SDH networks Pointer adjustments mechanism Clock requirements in SONET/SDH Timing distribution in SONET/SDH Introduction: SONET, which stands for synchronous optical network, is a standard developed in North America to support broadband transmission based on optical-fiber technology. The complementary international standard finalized by the International Telecommunications Union-Telecommunications Standardization Sector (ITU-T) is synchronous digital hierarchy, or SDH. SONET and SDH, which are compatible to each other, are a result of an intensive standardization process. The synchronization of networks has been on the basis of a plesiochronous digital hierarchy (PDH), but the introduction of SONET and SDH, has created renewed interest in network synchronization and has raised several new timing issues. _____________________________________________________________________________________
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The basic building block of SONET is a 51.84 Mbit/s signal referred to as synchronous transport signal level-1 (STS-1). The corresponding building block for SDH is synchronous transport module level 1 (STM-1), which has a bit rate of 155.52 Mbit/s. Both STS-1 and STM-1 can be synchronously multiplexed to create higher rate signals. During multiplexing, several low-rate signals are combined to form a higher rate bit stream. Each low-rate signal is called tributary of the higher-rate multiplexed signal. SONET STS-1 STS-3 STS-9 STS-12 STS-18 STS-24 STS-36 STS-48 STS-192 SDH STM-1 STM-3 STM-4 STM-6 STM-8 STM-12 STM-16 STM-64 Bit Rate (Mbit/s) 51.84 155.52 466.52 622.08 933.12 1244.16 1866.24 2488.32 9953.28 Optical Carrier Level (OC-n) OC-1 OC-3 OC-9 OC-12 OC-18 OC-24 OC-36 OC-48 OC-192

Table 8.1. Signal Hierarchy in SONET and SDH The key feature of SONET and SDH is the synchronous multiplexing of signals, wherein the position of a tributary is fixed in the higher-order multiplexed signal. This is in contrast to the PDH, where multiplexing is performed asynchronously. For example, to obtain a particular DS1 signal from a DS3 signal, the DS3 signal must be demultiplexed to DS2 and then to DS1. Synchronous multiplexing permits direct access to the required lower-order signal since its position in the higher-order signal is visible due to the absence of stuff bits. Another feature of SONET/SDH is that the PDH signals of both the North American and European hierarchies can be multiplexed in a SONET or SDH frame.

North America
Signal DS1 DS2 DS3 DS4 Bit Rate (Mbit/s) 1.544 6.312 44.736 274.176 Signal E1 E2 E3 E4

European
Bit Rate (Mbit/s) 2.048 8.448 34.368 139.264

Table 8.2. North America and European signals in the PDH SONET and SDH Frame structure: SONET Frame Structure: The STS-1 frame structure can be visualized as a table of bytes consisting of 9 rows and 90 columns. The 810 (9 X 90) bytes frame is transmitted in 125 s, yielding a bit rate of 51.84 Mbit/s. A SONET frame consists of two parts: 1. - A line and section overhead part consisting of 27 bytes of the first three columns. 2. - An STS-1 synchronous payload envelop (SPE) composed of the remaining 783 bytes from columns 4 to 90. _____________________________________________________________________________________
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In addition to the line and section overheads, the payload also contains a 9-byte path overhead. The basic building block of a SONET network is a section that consists of two NEs directly connected by optical fiber. Examples of NEs are regenerators, add/drop multiplexers (ADM), synchronous multiplexers and cross connects. A line consists of several sections. The signal structure remains unaltered during its transport through a line. A path is simply an end-to-end connection between terminals. PATH LINE SECTION SECTION LINE

OC-n

OC-n

TM

RGTR

ADM or DCS

OC-n

OC-n

RGTR

TM

SECTION DCS ADM RGTR TM

SECTION Figure 8.1 SONET Section, Line and Path definitions

= Digital Cross-Connect System = Add-Drop Multiplex = STE Regenerator = Terminal Multiplex SDH Frame Structure:

An STM-1 frame is the modular unit for SDH. The frame format of and STM-1 frame has been specified in ITU-T recommendations G.708 and G.709. It consists of 270 columns and nine rows. With the frame periodicity of 125 s, a 155.52 Mbit/s bit rate is achieved. The frame can therefore readily carry a 139.264 Mbit/s E4 signal. An examination of the STM-1 frame reveals that it can be considered to consist of three STS-1 signal structures. Thus, an STM-1 signal is equivalent to three STS-1 concatenated signals (STS-3c). Network Synchronization in SONET and SDH: The nodes of SONET/SDH are supplied with timing traceable to a primary reference clock (PRS). The PRS may be common to the digital switched and all other NEs of the SONET/SDH network. When several network operators operate the SONET/SDH network, different operators may use different PRSs. Regardless of the single or multi-operator character of the network, through, the basic requirements remains that all nodes receive reference timing traceable to a PRS. Although SONET/SDH NEs are synchronized to reference timing traceable to a PRS, events causing timing impairments may result in frequency differences between NEs. The pointer mechanism in SONET/SDH has been designed to take care of these situations. The fact that the position of the payload is not rigidly fixed inside the frame, rather, it floats in the frame within a small tolerance. This is achieved by means of a pointer that points to the beginning of the SPE in a frame. Thus, the position of the SPE inside the frame can be adjusted by changing the value of the pointer. The pointer adjustment is performed to accommodate frequency differences at a SONET NE. Two cases may arise, as follows: _____________________________________________________________________________________
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_____________________________________________________________________________________ 1. The sending NE clock is faster than the receiving NE clock. Thus, the received STS-1 payload rate will be higher than the frame rate of the receiving NE. In this case, the receiving NE introduces a negative pointer adjustment, that is, the pointer is decremented by 1. This pointer is named H3, and is used to carry 1 byte of payload data by the time this is happening. This is called negative stuff byte. The sending NE clock is slower than the receiving NE clock, and therefore the received STS-1 payload rate is slower than the frame rate of the receiving NE. In this case, the receiving NE introduces a positive pointer adjustment by incrementing the pointer by 1. The byte position immediately follows the H3 byte is nulls (positive byte stuffing).

2.

A similar mechanism of pointer adjustment exists in SDH NEs. In this case, a byte named AU3 is the pointer that needs to be adjusted by incrementing or decrementing by 3 bytes. The pointer adjustment is accompanied by stuffing (positive or negative) of 3 bytes. The pointer adjustment mechanism eliminates the need for slip buffers. This is an advantage, because buffers introduce signal delay. When all the NE is SONET-SDH network receive timing from a reference traceable to a PRS, there is very little offset between the NEs.

Two principal methods for synchronization of digital switches were discussed: master-salve and mutual synchronization. The master-slave technique has emerged as a method of choice for network synchronization in PDH environments. For SONET/SDH also, the master-slave method is recommended by the ITU-T. BELLCORE and European Telecommunications Standards Institute (ETSI) standards also stipulate the use of the master-slave method. Planning the interoffice synchronization network and avoiding timing loops is much more challenging with the deployment of SONET. Furthermore, DS1s carried on SONET are not recommended for network synchronization distribution to BITS clocks, because these signals will not meet ANSI T1.101 synchronization interfaces specifications [9]. SONET NEs are required to have internal clocks of 20-ppm minimum free-run accuracy. Based on the work done in T1X1 on ANSI T1.105.09, SONET: network Element timing and Synchronization, clocks that are contained in NEs that support SONET Line terminating functions, and that meet only this minimum accuracy requirements are called SONET Minimum Clocks (SMCs). The following general statements describe conditions necessary for synchronization and SONET networks to be compatible [9]: Where BITS timing is available, SONET NEs are externally timed from the BITS clock. Where no BITS timing is available, SONET NEs are timed from a received OC-N (or OC-M) signal quality. External-timing references to a SONET NE are from a BITS clock of stratum 3 or better Timing signals delivered to the synchronization network from a SONET NE are derived directly from a terminating OC-N (or OC-M). Synchronization status messages have been defined as a nibble (bits 5 to 8) in the S1 byte of the SONET line overhead and as a bit-oriented message in the Extended Superframe Format (ESF) data link of DS1 signals. These messages contain clock quality information that allows SONET NEs to select the _____________________________________________________________________________________
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_____________________________________________________________________________________ most suitable synchronization reference from the set of available references. The purpose of these messages is to allow SONET NEs to reconfigure their synchronization references autonomously while avoiding the creation of timing loops. However, it is critical to realize that the use of synchronization status messages alone will not preclude the creation of timing loops. Synchronization engineering follows the guidelines in GR-486-CORE is still required [9]. Table 8.3 list the synchronization status messages that have been defined at this time for the S1 byte and the ESF DS1 format.

Description

Acronym

Quality Level

Stratum 1 Traceable PRS 1 Synchronized - STU 2 Traceable Unknown Stratum 2 Traceable ST2 3 00001100 11111111 Stratum 3 Traceable ST3 4 00010000 11111111 SONET Minimum SMC 5 00100010 11111111 Clock Traceable Stratum 4 Traceable ST4 6 00101000 11111111 DON'T USE for DUS 7 00110000 11111111 Synchronization Reserved for Network RES User assignable 01000000 11111111 Synchronization USE. Notes: a = The ESF synchronization status messages are transmitted rightmost bit first. b = The S1 bits are transmitted leftmost bit first. Table 8.2 Synchronization Status Messages Definitions

DS1 ESF Data Link Code Worda 00000100 11111111 00001000 11111111

S1 bits 5678b 0001 0000 0111 1010 1100 N/A 1111 1110

Synchronization status messages in the S1 byte can provide the following benefits: Automatic reconfiguration of line-timed rings. Improved reliability of the interoffice timing distribution. Trouble-shooting of synchronization-related problems. Therefore, support for synchronization status messages is required for (almost) all line-side SONET signals. In a line-timed ring where some NEs support synchronization messaging and others do not, a timing loop may be created if the NEs are allowed to reconfigured their timing sources autonomously. This is mainly due to the fact that equipment that does not support S1 messages will generate an all-zeros code in the S1 nibble, which correspond to the "Synchronized-Traceability Unknown" message. It is important to note that the benefit of preventing timing loops for interoffice synchronization distribution (particularly for SONET rings) can only be realized if synchronization status messaging is supported by all TSGs and SONET Nes. Additionally, even if synchronization status messaging is implemented for all _____________________________________________________________________________________
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_____________________________________________________________________________________ SONET signals and ESF DS1s, the creation of timing loops could occur in certain configurations or situations. Correct use of the synchronization status message will keep the SONET ring in synch for much longer time.

9. - Conclusions. In order to achieve a fully synchronized network, the resources and the technical considerations are a major concern. Jitter, wander and slips impairments will always be there, and the failure of any equipment is also a possibility that needs to be put into the table of impairments. If the network synchronization model is still master-slave, the administration and operation cost could be very high considering that the technology of atomic clocks is getting cheaper. On the other hand, it is almost impossible to replace all the stratum 2, 3 and 4 clocks with Cesium clocks fast enough in order to avoid excessive amount of time and money in maintaining the master-slave model plus there is no need to have stratum 1 inside a PBX also. So there are several cases where the master-salve model will be maintained as the primary source of getting timing synchronization. As more and more stratum 1 clocks are implemented, the less and less network synchronization issues will be in the network. Moving away from synchronous mode and moving into plesiochronous mode is one of several possibilities in order to get a better synchronized network in the future; plus with the help of GPS technology we are moving in the right direction.

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Appendix A
Table A-1: DS-1 Multiframe structure for the 24 frame multiframe from G.704 ESF [2]. Multiframe structure for the 24 frame multiframe
F-bit Assignments Bit number(s) in each channel time slot

Frame number Within multiframe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Bit number within multiframe

FAS 1 194 387 580 773 966 1159 1352 1545 1738 1931 2124 2317 2510 2703 2896 3089 3282 3475 3668 3861 4054 4247 4440 0 0 1 0 1 1

DL m m m m m m m m m m m m

CRC e1 e2 e3 e4 e5 e6

For character signal a) 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7

For signallinga) 8 8 8 8

Signalling channel designationa)

Table A-2: DS-1 Allocation of the F-bits for the 12-frame multiframe from G.704 SF [2]. Allocation of F-bits for the 12-frame multiframe

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Multiframe alignment signal or signalling S S

Frame number 1 2 3 4

Frame alignment signal 1 0

NOTE For multiframe structure, see 3.1.3.2.2.

Table A-3: E-1 Multiframe structure from G.704 [2]. multiframe structure
Sub-multiframe (SMF) Frame number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bits 1 to 8 of the frame 1 C1 0 C2 0 C3 1 C4 0 C1 1 C2 1 C3 E C4 E 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A 4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1
Sa8

Multiframe

II

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References:
1.- GR-436-CORE, Digital Network Synchronization Plan, Revision 1 (Bellcore, June 1996). 2.- ITU-T G.704, Synchronous frame structures used at 1544, 6312, 2048, 8488 and 44 736 kbit/s hierarchical levels. (07/95). 3.- P.K. Bhatnag, Engineering Networks for Synchronization, CCS7, and Telecommunications handbook series. IEEE Press, 1997, 488 pp. ISBN 0-7803-1158-2. ISDN. IEEE

4.- Uyless Black & Sharleen Waters, SONET & T1: Architecture for Digital Transport Networks. Pretince Hall Series in Advance Communications Technologies. Pretince Hall, 1997, 332 pp. ISBN 0-13-447590-9 5.- ITU-T G.822, Controlled slip rate objetives on an international digital connection. (Extract from the Blue Book). 6.- ITU-T G.801, Digital transmission models. (Extract from the Blue Book). 7.- GR-2830-CORE, Primary Reference Sources: Generic Criteria., Issue 2 (Bellcore, December 1995). 8.- GR-1244-CORE, Clocks for the synchronized network: Common generic criteria. Issue 1 (Bellcore, June 1995). 9.- GR-253-CORE, Synchronous Oprical Network (SONET) Transport Systems: Common Generic Criteria. (Revision 1, December 1997) GR-1244-ILR, Clocks for the Synchronized Network: Common Generic Criteria. Issue 1A (Bellcore, December 1996). GR-378-CORE, Generic Requirements for Timming Signal Generators. Issue 1 (Bellcore, June 1995). ITU-T G.811, Timing Requirements at the outputs of primary reference clocks suitable fro plesiochronous operations of internationals digital links. (Extract from the Blue Book). ITU-T G.823, The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy. (03/93). ITU-T G.824, The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy. (03/93). ITU-T G.825, The control of jitter and wander within digital networks which are based on the synchronous digital hierarchy (SDH). (03/93). ITU-T G.813, Timing characteristics of SDH equipment slave clocks (SEC). (08/96). ITU-T G.810, Definitions and terminology for synchronization networks. (08/96).

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