REDUCED COMPLEXITY FILTERING TECHNIQUE FOR TIME DOMAIN EQUALIZERS

BACKGROUND Technical Field [0001] The embodiments herein generally relate to Digital broadcasting systems, and, more particularly, to reduced complexity filtering techniques for time domain equalizers.

Description of the Related Art [0002] In a Digital broadcasting system, perfect reconstruction of video signals is possible as long as the distortion is so small that it does not lead to incorrect decision of signals. Large distortion, however, leads to false decisions, resulting in fatal effects on visibility of reconstructed video signals. In such a system, the presence of echoes has a very undesirable impact on the performance of the demodulation system. The presence of echoes, directly affect the Bit Error Rate (BER) of the data received. Hence, it becomes essential to minimize the effect of these echoes and multi-path propagations. Intersymbol interference (ISI) is a form of distortion of a signal in which one symbol interferes with subsequent symbols. This is an unwanted phenomenon as the previous symbols have similar effect as noise, thus making the communication less reliable. [0003] ISI is usually caused by multipath propagation or the inherent non-linear frequency response of a channel causing successive symbols to "blur" together. The

presence of ISI in the system introduces errors in the decision device at the receiver output. Therefore, in the design of the transmitting and receiving filters, the objective is to minimize

the effects of ISI, and thereby deliver the digital data to its destination with the smallest error rate possible. Inter symbol interference is reduced using equalizers such as linear equalizers, adaptive equalizers, and Decision Feedback Equalizers (DFEs). An adaptive filter updates the equalizer parameters (such as the filter coefficients or taps) as it processes the data. Hence the updated filter coefficients also need to be stored. Digital TV broadcasting

techniques typically use a Decision Feedback Equalizer (DFE) that augments a linear equalizer by adding a filtered version of previous symbol estimates to the original filter output. [0004] FIG. 1 illustrates a time domain equalizer 100 used in an ATSC demodulation system. The domain equalizer 100 includes a feed-forward filter section (FFE) 102, a feedback filter section 104 (DFE) and a decision feedback error e[n] 106. Both filter sections are Finite Impulse Response (FIR) structures and the number of taps is decided based on the channel estimation results. To meet the A/53 requirements of the ATSC Standard, the maximum number of taps for the FFE section 102 and the DFE section 104 can be 384 and 448 respectively but the total number of taps does not exceed 768. FIR filtering techniques used to implement these sections (Feedback and Feed-forward) require large number of taps, thus resulting in large area. The large area contribution leads to a larger die-size and

consequently a higher cost of the DTV receiver of which this equalizer is a component. [0005] FIG. 2 illustrates an exploded view of the feed-forward filter 102 of adaptive coefficients of FIG. 1. The feed-forward filter 102 includes several tap values as input 202, a filter input 204, multipliers 206, and rounder blocks 208. The individual multiplier outputs filtered value corresponding to each tap which can be optionally rounded before summing up. The final summation result can be saturated and rounded before generating the final output.

Usage of a large number of Taps leads to higher power dissipation in the equalizer throughout the entire duration of demodulation. The feed-forward filter transversal equation is as
follows

[0006] FIG. 3 illustrates a feed-forward tap adaptation 300 used in equalization of input signal. The feed-forward tap adaptation 300 includes an equalizer error input signal in logarithmic form 302, a shifter 304, a saturation block 306, an accumulator 308 and truncation logic 310. The complex input signal is right shifted with sign extension by the amount of N, corresponding to logarithm of equalizer error input and subsequently subtracted from the previous tap coefficient. The new tap coefficient could be optionally passed

through saturation logic 306 to be stored in a tap accumulator 308. The tap coefficient is truncated using truncation logic 310, to generate a complex tap coefficient with a predefined fixed point format. equations. The Feed-forward tap adaptation is expressed using the following

[0007] FIG. 4 illustrates an exploded view of the feedback filter 104 a possible fixed point implementation of the feedback filter. The feedback filter 104 includes several

adaptive coefficients 402, a filter input 404, a multiplier 406, a rounder 408, saturation logic 410. The adaptive coefficient as tap value of j, index j ranges from 0 to Nc-1. The multiplier outputs the filtered value of j. The final summation result can be saturated by saturation logic 410 and rounded by rounder 408 before generating the final output from the filter named as filterout. The feedback filter equation is as follows.

[0008] FIG. 5 illustrates a feedback tap adaptation 500 to generate a real tap coefficient with a predefined fixed point format. The feedback tap adaptation 500 includes a real input signal 502, a shifter 504, saturation logic 506, an accumulator 508 and a truncation 510. The real input is right shifted with sign extension by the amount of N, corresponding to logarithm of error input and subsequently subtracted from the previous tap coefficient FFTapAcc(j) to get the new tap coefficient. The new tap coefficient could be optionally passed through saturation logic 506 to be stored in a tap accumulator 508. 4 The tap

coefficient is truncated 510 to generate a real tap coefficient with a predefined fixed point format. The Feedback tap adaptation is expressed using the following equations.

[0009] FIG. 6 illustrates a functional diagram of a FIR filtering structure. The FIR adaptive filtering technique used for both Feed Forward (FFE) and Decision Feedback sections (DFE) is as mentioned in the equation

N 1

y[n ]=

k= 0

w[k ] . x [n k ]

In the equation shown above, y(n) 602 is an output of the FFE/DFE filtering process, w(k) represents adaptation coefficients w[0] 604A, w[1] 604B, w[2] 604C, and w[N-1] 604D. x[n-k] represents input regressors x[n] 606, x[n-1], x[n-2], and x[1], as shown in FIG. 6. [0001] The time domain decision feedback equalizers used in current DTV and over the air or cable broadcast systems need to take care of several conditions. These typically consist of different multi-path scenarios, micro reflections, and a wide range of post and pre-echoes depending upon the channel conditions. Supporting a large range of such conditions

necessitates the need of a huge number of taps (e.g., filter coefficients or adaptation coefficients w[k]) in the feedback and the feed-forward filter sections. For example, to support the worst case requirement of 768 taps for ATSC, 768 multiply-and-accumulate (MAC) operations are required per symbol duration. 5

[0010] FIR filtering techniques used to implement these sections (e.g., feedback section 106 and feed-forward section102) require a large number of taps, thus resulting in large area. The large area contribution leads to a larger die-size and consequently a higher cost of the DTV receiver of which this equalizer is a component. In addition, usage of a large number of taps leads to higher power dissipation in the equalizer throughout the entire duration of demodulation. Conversely, if a limited number of arithmetic resources like only adders and shifters are available then the amount of time taken to complete the filter operations is significantly high. This can result in not being able to meet the real time deadlines, thus leading to inability of the TV receiver to demodulate the signals. [0011] One approach to reduce filter areas is to design an adaptive filtering implementation using a completely log-log based equalizer. Another approach involves having a completely sparse equalizer which has a lesser number of effective taps. A log-log based equalizer can have a higher residue mean square error (MSE) as compared to a floating-point implementation thus making it unsuitable for difficult channel conditions. The log-log based equalizer also takes a larger amount of time to converge to an equivalent error value compared to a floating point, implementation. On the other hand, the completely sparse equalizer has different gradients for different taps. This complicates the filtering operations since a lot of control operations needs to be performed in addition to filtering, which in some cases may also lead to increased area.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The embodiments herein will be better understood from the following detailed description with reference to the drawings, in which: [0013] FIG. 1 illustrates a time domain equalizer used in an ATSC demodulation system; [0014] FIG. 2 illustrates an exploded view of the feed-forward filter of FIG. 1; [0002] FIG. 3 illustrates a feed-forward tap adaptation in the time domain equalizer of FIG. 1; [0015] FIG. 4 illustrates an exploded view of feedback filter of FIG. 1; [0016] FIG. 5 illustrates a feedback tap adaptation in the time domain equalizer of FIG. 1; [0017] FIG. 6 illustrates a functional diagram of a FIR filtering structure implemented in the time domain equalizer of FIG. 1; [0018] FIG. 7 illustrates a process flow of a reduced complexity filtering operation according to an embodiment herein; [0019] FIG. 8A is a table view of a reduced complexity multiplier structure illustrating input tap bits in Q.15 format{ h[k] } converted to a sign, an exponent using a leading zero (positive number), and extracted reduced tap bits { h'[k] }according to an embodiment herein; [0020] FIG. 8B is a table view of a reduced complexity multiplier structure illustrating input tap bits in Q.15 format{ h[k] } converted to a sign, an exponent using a leading one (negative number) position detector, and extracted reduced tap bits { h'[k]

}according to an embodiment herein; [0021] FIG. 9 illustrates a reduced complexity multiplier cell to implement the reduced complexity filtering operation of FIG.7 according to an embodiment herein; [0022] FIG. 10 illustrates a pipelined implementation of the reduced complexity multiplier cell of FIG. 9 according to an embodiment herein; [0023] FIG. 11 illustrates a feed-forward tap adaptation using reduced complexity according to an embodiment herein; [0024] FIG. 12 illustrates a feed-forward filter using reduced complexity according to an embodiment herein; [0025] FIG. 13 illustrates a feedback tap adaptation using reduced complexity according to an embodiment herein; [0026] FIG. 14 illustrates a feedback filtering using reduced complexity according to an embodiment herein; and [0027] FIG. 15 illustrates a Mean Square Error (MSE) of a Decision Feedback Equalizer (DFE) adaptation error plotted against a number of symbol blocks at an SNR of 30 dB according to an embodiment herein;

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0028] The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not

unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein. [0029] As mentioned, there remains a need for reducing the filter areas while meeting real time deadlines for demodulating signals in a TV receiver. The embodiments herein achieve this by providing a reduced complexity filtering technique for time-domain equalizers. Referring now to the drawings, and more particularly to FIGS.7 through 15, where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments. [0030] FIG. 7 illustrates a process flow 700 of a reduced complexity filtering operation according to an embodiment herein. At step 702, an accumulator is initialized with a zero value and a number of taps is initialized with a zero value. At step 704, a decision box is made and a number of taps is compared with value equal to N signifying the completion of generation of all products for each of the input taps. If YES, at step 706, an accumulator is initialized of a Y[n] value and a Y[n] is equals to a summation of PROD[n]. This branch will typically be taken when all the coefficients and corresponding input samples are multiplied to generate individual product PROD[n] and ready for final accumulation. If all the products corresponding to N taps are not computed, the branch NO is taken. At step 708, an adaptive filter coefficient for each tap {h[k]} is taken in Q.J format. [0031] At step 710, an exponent is extracted for each filter coefficient using a leading zero (Positive number) or leading one position detector (Negative number). If the position

detected is lesser than or equal to J, we get SGN (sign bit) and EXP (exponent) bits. At step 712, a M+1 significant bits are extracted after the leading zero or leading one position, and to obtain a h[k] containing M significant bits, convergent rounding is performed on M+1 bits. At step 714, the extracted tap h[k] is segregated to L groups where L is equal to ceil[M/2] and modified booth recording of the input samples of x [n-k] is performed. At step 716, the recoded inputs are used to obtain INTMUL which is equals to SGN (sign bit) multiplied with h[k] multiplied with x[n-k]. This requires (L-1) adders per operation, of width of J+1, where J is equals to bit width of input samples of x[n-k] decremented by one. [0032] At step 718, the intermediate value of INTMUL obtained in Step 716, is right shifted with sign extension by EXP (exponent) amount to get the value of the product. The intermediate product of this step PROD is assigned the value of INTMUL right shifted EXP. This is equal to SGN* h[k]*x[n-k]* two to the power of negative EXP. At step 720, an accumulator is assigned to add the previous accumulator value with intermediate product PROD, and the number of taps is incremented by one. [0033] FIG. 8A is a table view 800 of how a full precision Q.15 input tap h[k] 802, where h[k] is a positive number, is extracted to get a sign bit 804, an exponent value 806 (using leading zero count) and 5bit extracted reduced tap positive coefficient 808. In a generic case the extracted bit can be any number other than 5 also. [0034] FIG. 8B is a table view 810 of how a full precision Q.15 input tap h[k] 812, where h[k] is a negative number, is extracted to get a sign bit 814, an exponent value 816 (using leading ones count) and 5 bit extracted reduced tap negative coefficient 818. In a generic case the extracted bit can be any number other than 5 also. [0035] FIG. 9 illustrates a reduced complexity multiplier cell 900 consisting of a

10

leading zero or one detector for exponent computation according to an embodiment herein. The leading zero/leading one detector 902 converts the input tap bits value to sign and exponent. The exponent computation is done by splitting the J+1 bit wide Coefficient Tap to 4 bit groups, each 4 bit group of J+1 bits is indexed from msb to lsb using index k, where k ranges from ([J+1]/4 1) down to zero. If the number of bits in inputs is 16 bits, they are grouped as 4 bits grp3, grp2, grp1 and grp0, the number of leading zeros or leading ones is generated as a gray coded intermediate output. The outputs from this transformation are exp_gp2, exp_gp1 and exp_gp0 respectively. The final gray-coded exponent value (gray_coded_expval) is generated using the following pseudo code. if (grp3 != 4d0 ) gray_coded_expval = exp_gp3, elseif (grp2 ! = 4d0) gray_coded_expval = exp_gp2 ^ 4b0110,// Gray addition of 4 elseif (grp1 ! = 4d0) gray_coded_expval = exp_gp1 ^ 4b1100,// Gray addition of 8 elseif (grp0 ! = 4d0) gray_coded_expval = exp_gp0 ^ 4b1010,// Gray addition of 12 [0036] The final gray coded exponent value is converted to binary value using the known transformation as shown below. exp_result_msb = gray_coded_expval[3]; exp_result_msbminus1 = gray_coded_expval[2] ^ exp_result_msb; exp_result_msbminus2 = gray_coded_expval[1] ^ exp_result_msbminus1; exp_result_msbminus3 = gray_coded_expval[0] ^ exp_result_msbminus2 Where exponent value = { exp_result_msb, exp_result_msbminus1, exp_result_msbminus2, exp_result_msbminus3} and the reduced precision Tap Coefficient value is given as

11

Reduced precision tap value (h[k]) = Slice of M most significant bits from [msb to msb-M] {Input_Tap_Coefficient <<< exponent value}; where <<< means signed right shift operation. [0037] Based on the discarded bits, one can optionally perform convergent rounding of the extracted bit slices to get the M-bit Tap Value (Extracted Tap coefficient h[k]) which will be provided to the Multiplier Input. Additional exponent threshold logic is provided to signal is the exponent is greater than a programmed threshold exponent value. This exponent threshold value (exp_threshold) is provided as one of the control registers of the Equalizer. To generate signal, exp_threshold_true is computed with exponent result which is greater than the exp_threshold. exp_threshold_true = if (exponent value > exp_threshold) TRUE else FALSE [0038] The convergent rounding extracted bit is done in 904 to generate h[k] reduced precision tap value. The modified booth recorder and adder 906 consists of two sources x[nk] which is the input sample (J+1 bits) and h[k] which is the reduced precision tap Coefficient (M bits). In addition, the inputs exp_threshold_true is provided as inputs. The Modified Booth Recorder 906 is implemented as a Radix-4 type. Typically M-bit coefficient is divided into pairs and partial products are generated. The modified Booth algorithm requires at most M/2+1 partial products and the algorithm used is as follows. Step1: If the exp_threshold_true is set to TRUE for the computed h[k] then h[k] is forced to a zero M bit value and we directly go to Step6. This gating function is also performed as a part of the coefficient extractor block 904. Step2: Pad the LSB with one zero. Step3: If M is even dont pad the MSB (M/2 Partial Productss) and if n is odd sign extend the MSB by 1 bit (M+1/2 Partial Productss). 12

Step4: Divide the multiplier into overlapping groups of 3-bits. Step5: Determine partial product scale factor from modified booth 2 encoding table. Step6: if exp_threshold_true is TRUE then compute the Multiplicand Multiples else force the result to all zeros. Step7: Sum the gated Partial Products to obtain the Multiplied Value which is passed to the Sign Extended Right Shifter. [0039] A sign extended right shifter 908 is typically implemented using known techniques where the MSB is replicated to fill in the right shifted out places. In this case, the value to be shifted is the output from the Multiplier and the control input is the exponent value. The added extensions occupy minimal area compared to adding a full precision multiplier. [0040] FIG. 10 illustrates a pipelined implementation of the reduced complexity multiplier cell 1000 which can be used as an extension of the ALU of any processor for performing equalization function according to an embodiment herein. The pipelined

implementation consists of several intermediate registers which helps in operating this circuit at much higher speeds. In this figure 1002 is identical in functionality to 902 shown in Figure 9, 1004 is identical in functionality to 904 shown in FIG. 9, 1006 is identical in functionality to 906 and 1008 is identical in functionality to 908 as shown in FIG. 9. [0041] FIG. 11 illustrates a feed-forward tap adaptation using reduced complexity 1100 of tap coefficients from the truncation block operation according to an embodiment herein. It includes shifters 1102, truncate blocks 1104, accumulators 1106, rounder blocks 1108 and TQL blocks 1110. The shifter 1102 right shifts the tap coefficients. The truncate logic 1104 truncates the tap coefficient. The accumulator 1106 stores the truncated tap coefficients. The rounder 1108 performs rounding of the tap coefficients. The TQL block 13

1110 converts the full precision tap bits to generate an exponent value and reduced precision tap. [0042] FIG. 12 illustrates a feed-forward filtering using reduced complexity 1200 using reduced precision tap coefficient operation according to an embodiment herein. It includes multipliers 1202, shifters 1204, saturation blocks 1206 and rounder blocks 1208. The multiplier 1202 multiplies the reduced tap coefficients with input samples. The shifter 1204 shifts the filtered value and the individual results are summed up. The saturation block 1206 received the final summation result. The rounding blocks 1208 to finally generate the FilterOut. [0043] FIG. 13 illustrates a feedback tap adaptation using reduced complexity 1300 of coefficient adaptation operation according to an embodiment herein. It includes shifters 1302, adders 1304, truncate blocks 1306, accumulators 1308, rounder blocks 1310 and TQL blocks 1312. The shifter 1302 right shifts the input tap value. The adder 1304 adds the previously accumulated tap value with the right shifted value to get the new tap bits. The truncate block 1306 generates the full precision tap coefficients. The accumulator 1308 stores the full precision tap coefficients. The rounding logic 1310 performs rounding of the tap coefficients values. The TQL block 1312 converts the full precision tap bits to generate exponent value and reduced precision tap. [0044] FIG. 14 illustrates a feedback filtering using reduced complexity 1400 using reduced precision tap coefficient according to an embodiment herein. It includes multiplier 1402, rounder block 1404 and shifters 1406. The multiplier 1402 multiplies the reduced precision tap coefficients with incoming input samples. The rounder block 1404 performs rounding of the multiplier output. The shifter 1406 right shifts the rounded multiplier output

14

and is summed up and rounded to generate a FilterOutput. [0045] FIG. 15 illustrates a Mean Square Error (MSE) 1500 of a Decision Feedback Equalizer (DFE) adaptation error plotted against a number of symbol blocks at an SNR of 30 dB according to an embodiment herein. The mean square error of equalizer 1502 adaptation error in the Y axis. The number of symbol blocks 1504 in the X axis. As per the graph 1506 shown, the mean square error for cases when M (effective precision of filter taps) is greater than or equals to 4 the equalizer performs as good as the one which implements multiplication using a full precision or floating point arithmetic. Results obtained with other Time Domain Equalizers show similar results as well to confirm that this scheme is effective.

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