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The document describes the Advanced Encryption Standard algorithm. It explains the cipher, key expansion, implementation, and provides simulation results. Tables and figures are included to illustrate transformations in the cipher and decryption processes.

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muzammil shadab
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50 views

Table of Contents

The document describes the Advanced Encryption Standard algorithm. It explains the cipher, key expansion, implementation, and provides simulation results. Tables and figures are included to illustrate transformations in the cipher and decryption processes.

Uploaded by

muzammil shadab
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Advanced Encryption Standard

Table of Contents CERTIFICATE ACKNOWLEDGEMENT ABSTRACT TABLE OF CONTENTS CHAPTERS


1.0.

Page No 01
01 03

INTRODUCTION
1.1 Introduction to Cryptography 1.2 Description of the Advanced Encryption Standard Algorithm

2.0. VLSI DESIGN FLOW


2.1 Introduction 2.2 Conventional Approach to Digital Design

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06 06 09 09

2.3. VLSI DESIGN


2.3.1 Abstraction Model

2.4. ASIC DESIGN FLOW


2.4.1 Design Description 2.4.2 Optimization 2.4.3 Simulation 2.4.4 Synthesis 2.4.5 Physical Design 2.4.6 Post Layout Simulation 2.4.7 Critical Subsystems

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11 13 13 13 14 15 15

2.4.8 Role of HDL 3.0. ALGORITHM SPECIFICATION 3.1. CIPHER


3.1.1 Sub Bytes () Transformation 3.1.2 ShiftRows () Transformation 3.1.3 MixColumns () Transformation

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18 19 21 22

Advanced Encryption Standard 3.1.4 AddRoundKey () transformation 23

3.2. KEY EXPANSION 3.3.0. INVERSE CIPHER


3.3.1 Invshiftrows () Transformation 3.3.2 InvsubBytes () Transformation 3.3.3 InvMixColumns () Transformation 3.3.4 Inverse of the AddRoundKey () Transformation 3.3.5 Equivalent Inverse Cipher

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26 27 28 29 29

3.4.0. IMPLEMENTATION ISSUES


3.4.1 Key Length Requirements 3.4.2 Keying Restrictions 3.4.3 Parameterization of Key Length, Block Size and Round Number 3.4.4 Parameterization Suggestions Regarding Various Platforms

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31 31 31 32

4.0. DESIGN IMPLEMENTATION 4.1.0. TOP BLOCK DIAGRAM


4.4.1 Encryption Top Block 4.4.2 Round Encryption Block 4.4.3 Control FSM 4.4.4 Decryption Top Block

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35 36 36 39

4.2 THE ADDROUNDKEY OPERATION 4.3 THE SHIFT ROW OPERATION 4.4 THE SUBBYTES OPERATION 4.5 THE MIXCOLUMN OPERATION 4.6.0. THE RIJNDAEL KEY SCHEDULE
4.6.1 Rotate 4.6.2 Rcon 4.6.3 S-Box 4.6.4 The Key Expansion

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46 46 46 46

Advanced Encryption Standard

4.7. THE KEY SCHEDULE 4.8. GENERAL COMMENTS 4.9.0. IMPLEMENTATION


4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.9.8 4.9.9 S-BOX Rotate Rcon Key Schedule Core Key Expansion AES Encryption Sub Bytes Shift Rows AddRoundKey

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50 50 50 50 51 51 51 51 51 52 52 52 52

4.9.10 Mix Columns 4.9.11 The Main AES body 4.9.12 AES Encryption 4.9.13 AES Decryption

5.0. SIMULATION RESULTS 6.0. SYNTHESIS REPORT CONCLUSIONS AND FUTURE WORK BIBLIOGRAPHY/ REFERENCES Appendix A: VHDL LANGUAGE OVERVIEW

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Advanced Encryption Standard

List of Tables
Table 3.0. Key blocked round combinations Table 3.1.1 S-box substitution values for the byte XY. Table 3.3.2 Inv-Sbox substitution values for the byte xy.

Page No
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List of Figures
Figure 2.1 A simple digital circuit Figure 2.2 Sequence of steps in conventional electronic circuit design Figure 2.3 Design domains and levels of abstraction Figure 2.4 Major activities in ASIC design Figure 2.5 ASIC design and development flow Figure 3.1 Sub bytes applies the S box to each byte of the state Figure 3.2 Shift rows cyclically shifts the last three rows in the state Figure 3.3 Mix columns operates on the state column-by-column Figure 3.4 Addroundkey Xor each column of the state with a word from the key schedule. Figure 3.5. InvshiftRows cyclically shifts the last three rows in the state Figure 4.1. Advanced Encryption Standard. Figure 4.2. Top Block Diagram Figure 4.3. Encryption Top Block Figure 4.4 Round encryption block diagram Figure 4.5 Control FSM Figure 4.6 Decryption Top Block Figure 4.7 Addroundkey Figure 4.8 Shift operation Figure 4.9 Byte substitution Figure 4.10 Mix Column operations Figure 4.11 key generation block 27 33 34 35 36 37 39 40 41 42 43 45 07 08 10 11 12 20 21 23 24

Advanced Encryption Standard Figure 5.0 Simulation Results 54

List of Abbreviations AES : Advanced Encryption Standard DES : Data Encryption Standard XTEA: Extended Tiny Encryption Algorithm SPN: Substitution Permutation Network CLB: Configuration Logic Block DLL: Delay Lock Loop NIST: National Institute of standards and Technology NBS: National Bureau of Standards PDA: Personal Digital Assistance FPGA: Field programmable Gate Array VHDL: Very High Speed Integrated Circuit Hardware Description Language ASIP : Application Specific Instruction Processor

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