Scribd
Upload
72 views

Lect 02 MOS1

The document discusses the MOS transistor and its operation. It begins by describing the basic operation of the MOS transistor in cut-off, inversion, and saturation modes. It then presents the standard MOS current equation and discusses effects like channel length modulation. The document finds discrepancies between the standard model and simulations due to velocity saturation effects. It proposes a unified MOS model that incorporates velocity saturation through a variable mobility term and matches simulations better. The document concludes by introducing the alpha power law model for more accurately modeling short channel MOS transistors.

Uploaded by

Rahul Charan
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
72 views

Lect 02 MOS1

The document discusses the MOS transistor and its operation. It begins by describing the basic operation of the MOS transistor in cut-off, inversion, and saturation modes. It then presents the standard MOS current equation and discusses effects like channel length modulation. The document finds discrepancies between the standard model and simulations due to velocity saturation effects. It proposes a unified MOS model that incorporates velocity saturation through a variable mobility term and matches simulations better. The document concludes by introducing the alpha power law model for more accurately modeling short channel MOS transistors.

Uploaded by

Rahul Charan
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

MOS Transistor

MOS Transistor

Professor Chris H. Kim


University of Minnesota Dept. of ECE [email protected] www.umn.edu/~chriskim/ Source Body Gate

Drain
Kuroda, IEDM panel
2

Basic Operation (1)

MOS Transistor Current Equation

Device is in cut-off region Simply, two back-to-back reverse biased pn diodes.


4

Basic Operation (2)

Basic Operation (3)

With a positive gate bias, electrons are pulled toward the positive gate electrode Given a large enough bias, the electrons start to invert the surface (p n type), a conductive channel forms Threshold voltage Vt
5

Current flows from drain to source with a positive drain voltage What is current in terms of Vgs, Vds, Vbs?
6

MOS Current

Channel Length Modulation

Ids = 0 : cut-off Vgs< Vt Ids = eCoxW/L ((Vgs-Vt) Vds-0.5Vds2) : triode (linear) mode 0 < Vds < Vgs- Vt 2 Ids = eCoxW/(2L) (Vgs-Vt) 0 < Vgs- Vt < Vds : saturation mode
7

Pinch-off depletion layer width increases as the drain voltage increases Extreme case of this is punch-through

L = Lo Vds

I ds = I dsat

Lo = I dsat (1 + Vds ) Lo Vds


8

Simulation versus Model (NMOS)

Simulation versus Model (PMOS)

The square-law model doesnt match well with simulations Only fits for low Vgs, low Vds (low E-field) conditions
9

Not as bad as the NMOS device Still large discrepancies at high E-field conditions
10

Simulation versus Model (Ids vs. Vgs)

Velocity Saturation

Saturation current does not increase quadratically The simulated curves looks like a straight line Main reason for discrepancy: velocity saturation
11

E-fields have gone up as dimensions scale Unfortunately, carrier velocity in silicon is limited Electron velocity saturates at a lower E-field than holes Mobility (e=v/E) degrades at higher E-fields Simple piecewise linear model can be used
12

Velocity Saturation
v =

Velocity Saturation
Plug it into the original current equation

e E
n 1 n

E 1 + Ec = vsat for E > Ec

for E < Ec

Ec =

2vsat

[Toh, Ko, Meyer, JSSC, 8/1988]

2 W Vds 1 eCox (Vgs Vt )Vds L 2 1 + Vds I ds = Ec L CoxWvsat (Vgs Vt Vdsat )

(Vds < Vdsat ) (Vds > Vdsat )

Equate the two expressions to get

Modeled through a variable mobility n=1 for PMOS, n=2 for NMOS To get an analytical expression, lets assume n=1
13

Vdsat =

(Vgs Vt ) Ec L (Vgs Vt ) + Ec L

14

Simulation versus Model


700 600 500 IDS [V] 400 300 200 100 0

Unified MOS Model


unified model simulation
1.2V

linear

1.0V

vel. saturation

0.8V

0.6V

saturation
0.2

0.4V 1.2

Model incorporating velocity saturation matches fairly well with simulation


15

Vdsat0.4

0.6 VDS [V]

0.8

16

Unified MOS Model Equations


I ds =

Alpha Power Law


Simple empirical model for short channel MOS

W eCox (Vgs Vt ) 2L

[Sakurai and Newton, JSSC 1990]

- body effect parameter

Model presented is compact and suitable for hand analysis. Still have to keep in mind the main approximation: that VDSat is constant. But the model still works fairly well.
17

Parameter is between 1 and 2 =1-1.2 for short channel devices Parameters and Vt are fitted to measured data for minimum square error fitted Vt can be different from physical Vt

18

You might also like