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Chap 6

The document describes algorithms for VLSI layout compaction. It discusses design rules, symbolic layout representation, and applications of compaction such as area minimization. Compaction can be 1D or 2D, with 1D being more efficient. Various algorithms are presented for solving the longest path problem on constraint graphs modeling the compaction problem, including for cyclic graphs.

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Sangeeth Kumar
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Download as PDF, TXT or read online on Scribd
230 views

Chap 6

The document describes algorithms for VLSI layout compaction. It discusses design rules, symbolic layout representation, and applications of compaction such as area minimization. Compaction can be 1D or 2D, with 1D being more efficient. Various algorithms are presented for solving the longest path problem on constraint graphs modeling the compaction problem, including for cyclic graphs.

Uploaded by

Sangeeth Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

DESIGN RULES
Design rules: restrictions on the mask patterns to increase the probability of successful fabrication.
Patterns and design rules are expressed in l. The types of the most common design rules: * minimum-width rules (valid for a mask pattern of a specific layer): (a). * minimum-separation rules (between mask patterns of the same layer or different layers): (b) resp. (c). * minimum-overlap rules (mask patterns in different layers): (d).

(a) (b)

(c) (d)

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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

SYMBOLIC LAYOUT
A layout is symbolic when not all mask patterns have full specification: * Single symbols are used to represent elements located in several layers, e.g. transistors, contact cuts. * The length, width or layer of a wire or other layout element might be left unspecified. * Mask layers not directly related to the functionality of the circuit do not need to be specified, e.g. n-well, p-well.

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In

LAYOUT COMPACTION

ALGORITHMS FOR VLSI DESIGN AUTOMATION

p/n diffusion polysilicon contact cut V ss V ss metal Symbolic and geometric layout of a CMOS inverter. Out V dd In

EXAMPLE

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V dd

Out 3

ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

COMPACTION AND ITS APPLICATIONS


A compaction program or compactor generates layout at the mask level. It attempts to make the layout as dense as possible. Applications of compaction: * Area minimization: removing redundant space in layout at the mask level. * Layout compilation: generation of mask-level layout from symbolic layout. * Redesign: automatic removal of design-rule violations. * Rescaling: converting mask-level layout from one technology to another.
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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

ASPECTS OF COMPACTION
Dimension: * 1-dimensional (1D): layout elements only move or shrink in one dimension (x or y). Often sequentially performed first in the x-dimension and then in the y-dimension (or vice versa). * 2-dimensional (2D): layout elements move and shrink simultaneously in two dimensions. Complexity: * 1D-compaction can be done efficiently; 2D-compaction is NP-hard.

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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

1D COMPACTION: X FOLLOWED BY Y
C D I E F H G E B A C D I F H G E B A C B D I F H G A

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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

1D COMPACTION: Y FOLLOWED BY X
C D I E F H G B A C B D I E F G E F H D I G A C B H A

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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

2D COMPACTION
C D I E F H G B A C D E B I F A H G

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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

INEQUALITIES FOR DISTANCE CONSTRAINTS


Minimum-distance design rules For example: can be expressed as inequalities. x2 * x1 w a x3 * x2 w b x3 * x6 w b x1 x2

x5 x6

x3


x4

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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

10

THE CONSTRAINT GRAPH


The inequalities can be used to construct a constraint graph G(V, E): * There is a vertex v i for each variable x i. * For each inequality of the form x j * x i w d ij, there is an edge (v i, v j) with weight d ij. * There is an extra source vertex, v 0; it is located at x + 0; all other vertices are at its right. * If all the inequalities express minimum-distance constraints, the graph is acyclic. It is a DAG, a directed acyclic graph.
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0 v0 0

v1 a v2 v5 a

b v3

a v4

v6 b

ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

11

MAXIMUM-DISTANCE CONSTRAINTS
Sometimes the distance of layout elements is bounded by a maximum, e.g. when the user wants a maximum wire width. * A maximum distance constraint gives an inequality of the or form: x j * x i v c ij x i * x j w * c ij. * Consequence for the constraint graph: backward edge
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(v j, v i) with weight d ji + * c ij. The graph is not acyclic anymore. x1 x2 v1 a v2

a b

b min. distance max. distance

ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

12

LONGEST-PATH ALGORITHM FOR DAGS


longest-path(G)

main ()

for (i 1; i  n; i i + 1) pi in-degree of vi ; Q fv0 g; while (Q 6= ;) f any element from Q; vi Q Q nfvi g; for each vj such that vi ; vj  2 E f xj maxxj ; xi + dij; pj pj - 1; if (pj  0) Q Q fvj g;

 

f g

for (i 0; i  n; i xi 0; longest-path(G);

 

 i + 1)

    

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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

13

LONGEST-PATHS IN CYCLIC GRAPHS


Constraint-graph compaction with maximum-distance constraints requires solving the longest-path problem in cyclic graphs. Two cases are distinguished: * There are positive cycles the +2 problem is NP-hard; however, v2 v3 a positive cycle corresponds to +2 +1 v 1 +1 v4 a set of conflicting constraints. x2 x3 The best to be done is to detect -3 x1 x4 the cycles. * All cycles are negative: polynomial-time algorithms exist.

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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

14

THE LIAO-WONG ALGORITHM (1)


Main ideas: * Split the edge set E of the constraint graph into two subsets: + forward edges E f: related to minimum-distance constraints, and + backward edges E b: related to maximum-distance constraints. * The graph G(V, E f) is acyclic; the minimum distance for each vertex can be computed with the procedure longest-path. * Repeat : + update minimum distances by processing the edges from E b. + call longest-path for G(V, E f). * The worst-case time complexity is: O(|E b|
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|E|).

ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

15

THE LIAO-WONG ALGORITHM (2)


count 0; 1; i  n; i for (i xi - ; x0 0;

   1  do f ag  0;

 i + 1)

if (count jEb j && ag) error(positive cycle)

  g count  count +1;

longest-path(Gf ); for each vi ; vj  2 Eb if (xj xi + dij ) f xj xi + dij ; 1; ag

while (ag);
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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

16

THE BELLMAN-FORD ALGORITHM (1)


for (i 1; i  n; i i + 1) xi - ; x0 0; count 0; S1 fv0 g; S2 ;; while (count  n && S1 6= ;) f for each vi 2 S1 for each vj such that vi ; vj  2 E if (xj xi + dij ) f xj xi + dij ; S2 S2 fvj g
S1 S2 ; S2 ;; count + 1; count

   1      

 

if (count n) error(positive cycle);


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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

17

THE BELLMAN-FORD ALGORITHM (2)


* Worst-case time complexity: O(n |E|). * However, average time complexity reported by Schiele: O(n 1.5).

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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

18

LONGEST AND SHORTEST PATHS


* Longest paths become shortest paths and vice versa when edge weights are multiplied by 1. * Situation in DAGs: both the longest and shortest path problems can be solved in linear time. * Situation in cyclic directed graphs: + All weights are positive: shortest-path problem in P (Dijkstra), longest-path problem is NP-complete. + All weights are negative: longest-path problem in P (Dijkstra), shortest-path problem is NP-complete. + No positive cycles: longest-path problem is in P. + No negative cycles: shortest-path problem is in P. + Otherwise: problem is NP-complete.
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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

19

REMARKS CONSTRAINT-GRAPH COMPACTION


* The algorithms mentioned only compute the left-most position for each layout element. All elements outside the critical paths also have a right-most position. It is interesting to find the best position within this interval with respect to some cost function. * The quality of the layout can further be improved by automatic jog insertion.

* A method to reduce complexity is hierarchical compaction.


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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

20

CONSTRAINT GENERATION
* The constraint graph is not directly available after layout design. It must be computed. * The set of constraints should be irredundant and generated efficiently.
B A C

* Doenhardt and Lengauer have proposed a method for irredundant constraint generation with complexity O(n log n).
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ALGORITHMS FOR VLSI DESIGN AUTOMATION LAYOUT COMPACTION

21

VIRTUAL GRID COMPACTION


Features: * 1D method. * All layout elements are associated to horizontal and vertical grid lines. * Initially the distance between grid lines is unspecified. * The distance between two subsequent grid lines is computed by taking the maximum separation imposed by pairs of elements on different grid lines. * Disadvantage: rigid as elements initially located on one line always remain aligned.

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