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User Defined Primitives in Verilog - ElectroSofts3

User Defined Primitives in Verilog _ElectroSofts3

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Miguel Bruno
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247 views

User Defined Primitives in Verilog - ElectroSofts3

User Defined Primitives in Verilog _ElectroSofts3

Uploaded by

Miguel Bruno
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog Tutorial: Harsha Perla

User defined primitives


User can define set of gate primitives by designing and specifying new primitive elements called user-defined primitives (UDPs). Instances of these new UDPs can then be used in exactly the same manner as the gate primitives to represent the circuit being modeled. User Defined Primitives can describe both combinational (Example 1) and sequential (Example 2) circuits. The behavioral description is provided as a truth table. Rules: UDP can have only one output. Inout ports are illegal. Combinational UDP should not have more than 10 inputs. Sequential UDP should not have more than 9 inputs. Vector declaration for UDP ports is illegal. The UDP declaration starts with the keyword primitive and ends with the keyword endprimitive. A port list, an output port declaration and input ports declaration are similar to their equivalents in a module declaration. Port list The port list contains a comma-separated list of primitive ports. There can be only one output port and several input ports. The inout ports are illegal. The first port on the list should be the output port. There are some restrictions concerning the number of input ports. The combinational UDPs list of ports should not contain more than 10 inputs, and the sequential UDPs port list should not contain more than 9 inputs. If the port list contains more inputs, then a warning will be issued. These restrictions are caused by illegibility of written UDPs.

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Port declaration Input and output port declarations should match the port list of the UDP they are enclosed in. If the described UDP is sequential, then reg declaration for output port should be provided. All ports of the UDP should be of scalar type (1-bit wide). Vectors are illegal.
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Initial statement Sequential UDPs can contain an initial statement for an output port. This statement begins with the keyword initial, followed by an assignment to the output port. Assigned values should be 1-bit wide and there must not be any delays. State table The state table starts with the keyword table and ends with the keyword endtable. The state tables for combinational and sequential UDPs are different. The state table is comprised of rows each of which ended with a the semicolon. Table row describes the behavior of UDP for a particular combination of inputs. The combinational UDPs have two fields separated by a colon. One field is for the inputs and one for the outputs. The sequential UDPs have three fields: one for the inputs, one for the current output state, and one for the next output state. If any combination of input signals, is not explicitly specified in the UDP declaration, the output value will be unknown (x). A particular combination of inputs can be specified only one time.

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