The Programmable Logic Data Book April 1998

, XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc. , all XC-prex product designations, XACTstep, XACTstep Advanced, XACTstep Foundry, XACT-Floorplanner, XACT-Performance, XAPP, XAM, X-BLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, XPP, XSI, Foundation Series, BITA, Congurable Logic Cell, CLC, Dual Block, FastCLK, FastCONNECT, FastFLASH, FastMap, HardWire, LCA, Logic Cell, LogiCore, LogicProfessor, MicroVia, PLUSASM, PowerGuide, PowerMaze, Select-RAM, SMARTswitch, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Spartan, Spartan-XL and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company and The Programmable Gate Array Company are service marks of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx devices and products are protected under one or more of the following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822;

4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418; 4,853,626; 4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377; 5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,466,117; 5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196; 5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; RE 34,363, RE 34,444, and RE 34,808. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx ofcer is prohibited. Copyright 1998 Xilinx, Inc. All Rights Reserved.

The Programmable Logic Data Book

Xilinx Home Page (WWW): XDOCS E-mail Document Server: Application Service Centers North America Hotline: http://www.xilinx.com/ (Answers Database, File Download) [email protected] send E-mail with help in the header 1-408-879-5199 (USA, Xilinx headquarters) 1-800-255-7778 (North America) 1-408-879-4442 (FAX) [email protected] (44) 1932-820821 (44) 1932-828522 [email protected] (33) 1-3463-0100 (33) 1-3463-0959 [email protected] (49) 89-93088-130 (49) 89-93088-188 [email protected] (81) 3-3297-9163 (81) 3-3297-0067 [email protected] (82) 2-761-4277 (82) 2-761-4278 [email protected] (85) 2-2424-5200 (85) 2-2424-7159 [email protected] 1-800-624-4782 www.xilinx.com

Email: United Kingdom Hotline: Fax: Email: France Hotline: Fax: Email: Germany Hotline: Fax: Email: Japan Hotline: Fax: Email: Korea Hotline: Fax: Email: Hong Kong Hotline: Fax: Email: Software Authorization and Licensing: On-Line Authorization:

2100 Logic Drive San Jose, California 95124 United States of America Telephone: (408) 559-7778 Fax: (408) 559-7114

On behalf of the employees of Xilinx, our sales representatives, our distributors, and our manufacturing partners, welcome to our 1998 Data Book, and thank you for your interest in Xilinx products and services. As the inventor of Field Programmable Gate Array technology and the worlds leading supplier of programmable logic, we would like to pledge our continuing commitment to providing you, our users, with the best possible integrated circuit components, development systems, and technical and sales support. Over the past year, we have substantially enhanced our product line with the introduction of the XC4000XL, XC4000XV, and Spartan series of FPGAs, as well as XH3 FpgASIC Hardwire technology. We have continued to enhance our leading-edge products with new speed grades and improved pricing. The Alliance and Foundation series products have set a new standard for functionality and ease-of-use in programmable logic development systems. You can expect this pace of innovation to continue, and even increase, as we maintain our leadership role in bringing leading-edge programmable logic solutions to the market. We look forward to satisfying all of your programmable logic needs.

Sincerely,

Wim Roelandts Chief Executive Ofcer

Section Titles

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Table of Contents

Introduction
An Introduction to Xilinx Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Development System Products and CORE Solutions Products

Development Systems: Products Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Development Systems: Product Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 CORE Solutions Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

CPLD Products
XC9500 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 XC9500 In-System Programmable CPLD Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 XC9536 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 XC9572 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 XC95108 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 XC95144 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 XC95216 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 XC95288 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65

FPGA Products
XC4000E and XC4000X Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 XC4000E and XC4000X Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . 4-5 XC4000XV Family Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-155 XC4000XLT Family Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-175 Spartan and Spartan-XL Families Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187 Spartan and Spartan-XL Families Field Programmable Gate Arrays . . . . . . . . . . . . . . . 4-189 XC5200 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-243 XC5200 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-247

XC3000 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-319 XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L). . . . . . . . . . 4-321

SPROM Products
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs . . . 5-1 XC1700E Family of Serial Configuration PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Spartan and Spartan-XL Families of Serial Configuration PROMs . . . . . . . . . . . . . . . . . 5-23

3V Products
3.3 V and Mixed Voltage Compatible Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

HardWire FpgASIC Products

Xilinx HardWire FpgASIC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

High-Reliability and QML Military Products

High-Reliability and QML Military Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 XC4000X Series High-Reliability Field Programmable Gate Arrays . . . . . . . . . . . . . . . . 8-7 XC4000E High-Reliability Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 XC4000E High-Reliability Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . 8-11

Programming Support
HW-130 Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

Packages and Thermal Characteristics

Packages and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21

Testing, Quality, and Reliability

Quality Assurance and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

Technical Support and Services

Technical Support And Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

Product Technical Information

XC3000, XC4000, and XC5200: A Technical Overview for the First-Time User . . . . . . . 13-5 Choosing a Xilinx Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 I/O Characteristics of the XL FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 XC4000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 XC3000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 FPGA Configuration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 Configuring Mixed FPGA Daisy Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39 Configuration Issues: Power-up, Volatility, Security, Battery Back-up . . . . . . . . . . . . . 13-41 Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-45 Metastable Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-47 Set-up and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-50 Overshoot and Undershoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-51 Boundary Scan in XC4000 and XC5200 Series Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 13-52

Index
Book Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

Introduction

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Introduction Table of Contents

An Introduction to Xilinx Products

About this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Book Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About the Company . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Logic vs. Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Faster Design and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Changes without Penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shortest Time-to-Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Programmable Gate Arrays (FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complex Programmable Logic Devices (CPLDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HardWire devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Reliability Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development System Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9500 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-1 1-1 1-2 1-2 1-3 1-3 1-3 1-3 1-3 1-4 1-4 1-4 1-4 1-5 1-5 1-5 1-6 1-6 1-7 1-7 1-8

An Introduction to Xilinx Products

1 1*

November 10, 1997

About this Book

This Data Book provides a snapshot in time in its listing of IC devices and development system software available from Xilinx as of late 1997. New devices, speed grades, package types and development system products are continually being added to the Xilinx product portfolio. Users are encouraged to contact their local Xilinx sales representative and consult the WebLINX World Wide Web site and the quarterly XCELL newsletter for the latest information regarding new product availability. This book covers the current XC4000E/EX/XL, XC4000XV, XC4000XLT, Spartan, XC5200, XC3000A/L, XC3100A/L, XC9500, XC1700D/L and XC1701L. The product specications for several older Xilinx FPGA families are not included in this Data Book. This does not imply that these products are no longer available. However, for new designs, users are encouraged to use the newer products described in this book, which offer better performance at lower cost than the older technologies. Product specications for the older products are available at WebLINX, the Xilinx site on the World Wide Web, or through your local Xilinx sales representative.

Chapter 2 contains a discussion of the overall design methodology when using Xilinx programmable logic and descriptions of Xilinx development system products. This chapter is placed at the beginning of the book since these development tools are needed to design with any of the Xilinx programmable logic devices. Chapter 3 contains the product descriptions for the Xilinx Complex Programmable Logic Device (CPLD) products, including the XC9000 series. Chapter 4 includes the product descriptions for the Xilinx static-memory-based Field Programmable Gate Array (FPGA) products, including the XC3000, XC4000, XC5000, and Spartan series. Chapter 5 holds the product descriptions for the XC1701L and XC1700D families of Serial PROM devices. These Serial PROMs provide a convenient, low-cost means of storing conguration programs for the SRAM-based FPGAs described in Chapter 4. Chapter 6 is an overview of Xilinx components appropriate for 3.3 V and mixed-voltage systems. This chapter will refer you back to the appropriate product descriptions in the earlier chapters. Chapter 7 contains a brief overview of the HardWire product line. Detailed product specications are available in separate Xilinx data sheets. Chapter 8 is an overview of Xilinx High-Reliability/Military products. Detailed product specications are available in separate Xilinx data sheets. Chapter 9 describes the HW130 device programmer for the XC170X series of Serial PROMs and the XC9500 series of CPLDs. Chapter 10 contains a description of all the physical packages for the various IC products, including information about the thermal characteristics of those packages. Chapter 11 discusses the testing, quality, and reliability of Xilinx component products. Chapter 12 includes a listing of all the technical support facilities provided by Xilinx. Chapter 13 contains additional information about Xilinx components that is not provided in the product specications of the earlier chapters. This includes some additional electrical parameters that are not in the product specications because they are not part of the manufacturing test program for the particular device, but may be of interest to the user. Also included in this chapter is a discussion of the 1-1

Data Sheet Categories

In order to provide the most up-to-date information, some component products included in this book may not have been fully characterized at the time of publication. In these cases, the AC and DC characteristics included in the data sheets will be marked as Advance or Preliminary information. (Not withstanding the denitions of such terms, all specications are subject to change without notice.) These designations have the following meaning: Advance Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, but not for nal production. Preliminary Based on preliminary characterization. Changes are possible, but not expected. Final (unmarked) Specications not identied as either Advance or Preliminary are to be considered nal.

Data Book Contents

Chapter 1 is a general overview of the Xilinx product line, and is recommended reading for designers who are new to the eld of high-density programmable logic.

November 10, 1997

An Introduction to Xilinx Products

JTAG boundary test scan logic found in several Xilinx component families. The nal two sections contain an index to the topics included in this Data Book and a listing of Xilinx sales ofces, sales representatives, and distributors.

About the Company

Xilinx, Inc., offers the industrys broadest selection of programmable logic devices. With 1997 revenues of over $560 million, Xilinx is the worlds largest supplier of programmable logic, and the market leader in Field Programmable Gate Arrays (FPGAs). Xilinx was founded in 1984, based on the revolutionary idea of combining the logic density and versatility of gate arrays with the time-to-market advantages and convenience of user-programmable standard parts. One year later, Xilinx introduced the worlds rst Field Programmable Gate Array. Since then, through a combination of architectural and manufacturing process improvements, the company has continually increased device performance, in terms of capacity, speed, and ease-of-use, while lowering costs. In 1992, Xilinx expanded its product line to include advanced Complex Programmable Logic Devices (CPLDs). For the user, CPLDs are an attractive complement to FPGAs, offering simpler design software and more predictable timing.

As the market leader in one of the fastest growing segments of the semiconductor industry, Xilinx strategy is to focus its resources on creating new ICs and development system software, providing world-class technical support, developing markets, and building a diverse customer base across a broad range of geographic and end-use application segments. The company has avoided the large capital commitment and overhead burden associated with sole ownership and operation of a wafer fabrication facility. Instead, Xilinx has established alliances with several high-volume, state-of-the-art CMOS IC manufacturers. Using standard, high-volume processes assures low manufacturing costs, produces programmable logic devices with well-established reliability, and provides for early access to advances in CMOS processing technology. Xilinx headquarters are located in San Jose, California. The company markets its products worldwide through a network of direct sales ofces, manufacturers representatives, and distributors (as listed in the back of this book). The company has representatives and distributors in over 38 countries.

Product Line Overview

Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) can be used in virtually any digital logic system. Over 50 million Xilinx components have been used in a wide variety of end-equipment applications, ranging from supercomputers to hand-held

1-2

November 10, 1997

instruments, from central ofce switches to centrifuges, and from missile guidance systems to guitar synthesizers. Xilinx achieved its leading position through a continuing commitment to provide a complete product solution. This encompasses a focus on all three critical areas of the high-density programmable solution triangle: components (silicon), software, and service (Figure 2).

one-third of its lifetime potential prot. With mask-programmed gate arrays, design iterations can easily add that much time, and more, to a product schedule. Once the decision has been made to use Xilinx programmable logic, a choice must be made from a number of product families, device options, and product types. The information in the product selection matrices that follow can help guide that selection; detailed product specications are available in subsequent chapters of this book. Since many component products are available in common packages with common footprints, designs often can be migrated to higher or lower density devices, or even across some product families, without any printed circuit board changes. Design ideas, represented in text or schematic format, are converted into a conguration data le for an FPGA or CPLD device using the Xilinx XACTstep development software running on a PC or workstation.

Programmable Logic vs. Gate Arrays

Xilinx programmable logic devices provide the benets of high integration levels without the risks or expenses of semi-custom and custom IC development. Some of the benets of programmable logic versus mask-programmed gate arrays are briey discussed below.

Faster Design and Verication

Xilinx FPGAs and CPLDs can be designed and veried quickly while the same process requires several weeks with gate arrays. There are no non-recurring engineering (NRE) costs, no test vectors to generate, and no delay while waiting for prototypes to be manufactured.

Component Products
Xilinx offers the broadest line of programmable logic devices available today, with hundreds of products featuring various combinations of architectures, logic densities, package types, and speed grades in commercial, industrial, and military grades. This breadth of product offerings allows the selection of the programmable logic device that is best suited for the target application. Xilinx programmable logic offerings include several families of reprogrammable FPGAs and FLASH-memory-based CPLDs (Figure 3). HardWire devices are mask-programmed versions of the reprogrammable FPGAs, and provide a transparent, no-risk migration path to lower-cost devices for high-volume, stable designs. Additionally, a family of Serial PROM devices is available to store conguration programs for the reprogrammable FPGA devices. Many devices are available in military temperature range

Design Changes without Penalty

Because the devices are software-congured and user-programmed, modications are much less risky and can be made anytime - in a manner of minutes or hours, as opposed to the weeks it would take with a gate array. This results in signicant cost savings in design and production.

Shortest Time-to-Market
When designing with Xilinx programmable logic, time-to-market is measured in days or a few weeks, not the months often required when using gate arrays. A study by market research rm McKinsey & Co. concluded that a six-month delay in getting to market can cost a product

Optimized circuits/architectures
SO

Powerful but easy

N

Highest performance/densities
LI

Integrated across families Seamless integration into customer CAE system

WA

FT

Deep submicron processes Unmatched quality and reliability

SI

CO

RE

S E RV I C E Global world class sales/distribution support Global world class technical support: FAEs/support center/on-line/internet Global world class manufacturing: quality/capacity/delivery
X5955

Figure 2: The Xilinx Programmable Solution Triangle

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and/or MIL-STD-883B versions, for high-reliability and military applications.

Complex Programmable Logic Devices (CPLDs)

Designers more comfortable with the speed, design simplicity, and predictability of PALs may prefer CPLD devices. Conceptually, CPLDs consist of multiple PAL-like function blocks that can be interconnected through a switch matrix (Figure 5). The XC9000 CPLD series features 5V in-system programmable FLASH technology, and, like most of the FPGA families, includes built-in JTAG boundary scan test logic.

Field Programmable Gate Arrays (FPGAs)

FPGA devices feature a gate-array-like architecture, with a matrix of logic cells surrounded by a periphery of I/O cells, as diagrammed in Figure 4. Segments of metal interconnect can be linked in an arbitrary manner by programmable switches to form the desired signal nets between the cells. FPGAs combine an abundance of logic gates, registers, and I/Os with fast system speed. Xilinx offers several families of reprogrammable, static-memory-based (SRAM-based) FPGAs, including the XC3000, XC4000, XC5000, and XC6000 series.
ASIC Alternatives
Gate Arrays Custom Highest Density ASIC Tools

HardWire devices
HardWire devices are masked-programmed versions of the SRAM-based FPGAs. The HardWire products provide an easy, transparent migration path to a cost-reduced device without the engineering burden associated with conventional gate array re-design. The HardWire gate array is architecturally identical to its FPGA counterpart, but the programmable elements in the FPGA are replaced with xed metal connections. The resulting die is considerably smaller, with a correspondingly lower cost. Using proprietary automatic test vector generation software and patented test logic, Xilinx guarantees over 95% fault coverage, while eliminating the need for user-generated test vectors. The mask and test programs are generated automatically by Xilinx from the users existing FPGA design le.

Xilinx Product Line

CPLD ISP PAL Architecture Medium Density Simple Tools

FPGA Programmable Gate Array Architecture High Density ASIC Tools

HardWire Custom Transparent Conversion 100% Tested

Serial PROMs
The XC1700 family features one-time programmable serial PROMs ranging in density from about 18,000 bits to over 260,000 bits. These serial PROMs are an easy-to-use, cost-effective method for storing conguration data for the SRAM-based FPGAs.

PAL Devices Programmable AND/OR Architecture Low Density Simple Tools

X5957

Figure 3: Application-Specic IC Products

PROGRAMMABLE INTERCONNECT

I/O BLOCKS

X1153

LOGIC BLOCKS

Figure 4: FPGA Architecture

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FB

FB

FB

FB

I/O

Interconnect Matrix FB FB

I/O

FB

FB

X5956

Figure 5: CPLD Architecture

High-Reliability Devices
Xilinx was the rst company to offer high-reliability FPGAs by introducing MIL-STD-883B qualied XC2000 and XC3000 series devices in 1989. MIL-STD-883B members of the XC4000 FPGA series are currently available, and qualied versions of additional Xilinx families are in development. The product line also includes Standard Microcircuit Drawing (SMD) versions of several families. Some Xilinx devices are available in tested die form through arrangements with manufacturing partners.

forms include the ubiquitous PC and several popular workstations.

Technical Support and Service

Providing global, world-class manufacturing, technical support, and sales/distribution support is an essential foundation of the Xilinx product strategy. Xilinx manufacturing facilities have earned ISO9002 certication, and Xilinx quality and reliability achievements are among the worlds best - not just for programmable logic suppliers, but among all semiconductor companies. Comprehensive technical support facilities include training courses, extensive product documentation and application notes, a quarterly technical newsletter, the WebLINX World Wide Web site, technical support hotlines, and a cadre of Field Application Engineers. Sales support is provided by a worldwide network of representatives and distributors.

Development System Products

Xilinx offers a complete software environment for the implementation of logic designs in Xilinx programmable logic devices. This environment combines powerful technology with a exible, easy-to-use graphical interface to help users achieve the best possible designs, regardless of experience level. The user has a wide range of choices between a fully-automatic implementation and detailed involvement in the layout process. The development system provides all the implementation tools required to design with Xilinx logic devices, including the following: libraries and interfaces for popular schematic editors, logic synthesis tools, and simulators design manager/ow engine module generator map, place, and route compilation software static timing analyzer hardware debugger

Xilinx is committed to an open system approach to front-end design creation, synthesis, and verication. Xilinx devices are supported by the broadest number of EDA vendors and synthesis vendors in the industry. Supported plat-

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An Introduction to Xilinx Products

XC3000 Series Product Selection Matrix

XC3020A/L XC3030A/L XC3042A/L XC3064A/L XC3090A/L XC3120A XC3130A XC3142A XC3164A XC3190A XC3195A XC3142L
3 N/A 2-3 144 480 4 N N 1.5 -2

XC3000 Series

KEY FEATURES

Low Cost/ Low Power

Max Logic Gates (K) 1.5 N/A 1-1.5 64 256 4 N N -6/-8 2 N/A 1.5-2 100 360 4 N N -6/-8 3 N/A 2-3 144 480 4 N N -6/-8 4.5 N/A 3.5-4.5 224 688 4 N N -6/-8 6 N/A 5-6 320 928 4 N N -6/-8 1.5 N/A 1-1.5 64 256 8 N N 8 -09 2 N/A

High Performance

Low Voltage (3.3 V) High Performance

6 7.5 N/A 6.5-7.5 484 1320 8 N N 8 -09 6 N/A 5-6 320 928 4 N N 1.5 -2

3 N/A 2-3 144 480 8 N N 8 -09

4.5 N/A 3.5-4.5 224 688 8 N N 8 -09

DENSITY

Max RAM Bits Typical Gate Range (K) CLBs Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade

N/A 5-6 320 928 8 N N 8 -09

1.5-2 100 360 8 N N 8 -09

FEATURES

0.5/0.02 0.5/0.02 0.5/0.02 0.5/0.02 0.5/0.02

XC4000 Series Product Selection Matrix

XC4028EX/XL XC4036EX/XL XC4005E/XL XC4010E/XL XC4013E/XL XC4020E/XL XC4044XL XC4052XL XC4062XL XC4085XL XC4003E XC4006E XC4008E XC4025E
DEVICES

XC4000 Series

KEY FEATURES

High Density High Performance Select-RAM Memory

System Gate Range* (Logic and RAM) (K) Logic Cells Max Logic Gates, (no RAM) (K) Max RAM Bits (no Logic) CLBs Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 2-5 238 3 3200 100 360 12 Y Y 10 -1 3-9 466 5 6272 196 616 12 Y Y 10 -09 4-12 6-15 7-20 608 770 950 6 8 10 8192 10368 12800 256 324 400 768 936 1120 12 12 12 Y Y Y Y Y Y 10 10 10 -1 -1 -09 10-30 1368 13 18432 576 1536 12 Y Y 10 -09 13-40 1862 20 25088 784 2016 12 Y Y 10 -09 15-45 2432 25 32768 1024 2560 12 Y Y 10 -1 18-50 2432 28 32768 1024 2560 12 Y Y 10 -09 22-65 3078 36 41472 1296 3168 12 Y Y 10 -09 27-80 33-100 40-130 55-180 3800 4598 5472 7448 44 52 62 85 51200 61952 73728 100352 1600 1936 2304 3136 3840 4576 5376 7168 12 12 12 12 Y Y Y Y Y Y Y Y 10 10 10 10 -09 -09 -09 -09

FEATURES

DENSITY

*Maximum System gates assume 20% of CLBs used as RAM

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XC3190L

DEVICES

Spartan Series Product Selection Matrix

KEY FEATURES DEVICES

Spartan Series

XCS05 XCS05-XL

XCS10 XCS10-XL

XCS20 XCS20-XL

XCS30 XCS30-XL

XCS40 XCS40-XL

High Density High Performance Select-RAM Memory Low Cost

System Gate Range* (Logic and RAM) (K) Logic Cells Max Logic Gates, (no RAM) (K) Max RAM Bits (no Logic) CLBs Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 2-5 238 3 3200 100 360 12 Y Y 3 -4 3-10 466 5 6272 196 616 12 Y Y 3 -4 7-20 950 10 12800 400 1120 12 Y Y 3 -4 10-30 1368 13 18432 576 1536 12 Y Y 3 -4 13-40 1862 20 25088 784 2016 12 Y Y 3 -4

FEATURES

DENSITY

*Maximum System gates assume 20% of CLBs used as RAM

XC5200 Series Product Selection Matrix

KEY FEATURES DEVICES

XC5200 Series

XC5202

XC5204

XC5206

XC5210

XC5215

High Density Low Cost Max Logic Gates (K) Max RAM Bits Typical Gate Range (K) CLBs/Logic Cells Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 3 N/A 2-3 64 256 8 Y Y 15 -3 6 N/A 4-6 120 480 8 Y Y 15 -3 10 N/A 6-10 196 784 8 Y Y 15 -3 16 N/A 10-16 324 1296 8 Y Y 15 -3 23 N/A 15-23 484 1936 8 Y Y 15 -3

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FEATURES

DENSITY

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XC9500 Series Product Selection Matrix

KEY DENSITY FEATURES DEVICES

CPLD Families

XC9536

XC9572

XC95108

XC95144

XC95216

XC95288

JTAG 5 V ISP 3 V or 5 V I/O Gates (K) Macrocells Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 0.8 36 36 24 Y N -5 1.6 72 72 24 Y N -7 2.4 108 108 24 Y N 140 -7 3.2 144 144 24 Y N -7 4.8 216 216 24 Y N -10 6.4 288 288 24 Y N -10

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FEATURES

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Development System Products and CORE Solutions Products

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Development System Products Table of Contents

Development System Products and CORE Solutions Products

Development Systems: Products Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flexible Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx M1 Software Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increased Design Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M1 Technical Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-1 2-1 2-1 2-1 2-2 2-2 2-2 2-2

Development Systems: Product Descriptions

Development Systems Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Base-Express System with VHDL/Verilog Synthesis (PC) . . . . . . . . . . Foundation Series: Foundation Standard System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Express System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Alliance Base (PC or Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Alliance Standard (PC or Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series Options (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-4 2-5 2-6 2-7 2-8 2-10 2-12

CORE Solutions Overview

Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORE Solutions Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORE Solutions Data Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LogiCORE Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx CORE Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx PCI Solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx DSP Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquiring LogiCORE Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AllianceCORE Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AllianceCORE Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquiring AllianceCORE Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2-13 2-13 2-13 2-13 2-14 2-14 2-14 2-14 2-14 2-15 2-15

Development Systems: Products Overview

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Product Overview all Xilinx programmable logic devices, featuring the industrys largest FPGA devices.

Introduction
Leading-edge silicon products, state-of-the art software solutions and world-class technical support make up the total solution delivered by Xilinx. The software component of this solution is critical to the success of every design project. Xilinx Software Solutions provide powerful tools which make designing with programmable logic simple. Push button design ows, integrated on-line help, multimedia tutorials, plus high performance automatic and autointeractive tools, help designers achieve optimum results. And the industrys broadest array of programmable logic technology and EDA integration options deliver unparalleled design exibility.

Foundation Series
The Xilinx Foundation Series provides everything required to design a programmable logic device in an easy-to-use environment. This fully integrated tool set allows users to access design entry, synthesis, implementation and simulation tools in a ready-to-use package. Every step in the design process is accomplished using graphical tool bars, icons and pop-up menus supported by interactive tutorials and comprehensive on-line help. The Xilinx Foundation Series features support for standards based HDL design. All congurations support the popular ABEL language, with integrated compilers optimized for each target architecture. HDL congurations include integrated VHDL/Verilog synthesis from Synopsys with tutorials and graphical HDL design entry tools to turn new users into experts quickly and easily.

Product Overview
Xilinx Software Solutions are available in two different product series making it easy for designers to choose the right system for their needs. These two series support the industrys broadest array of programmable logic IC families. This allows users to standardize their design tools for all programmable logic applications and use these tools to realize the benets of the industrys highest performance and density FPGAs and CPLDs. It also makes it easy to migrate designs to new technologies and re-use existing designs in new applications. The Xilinx Foundation Series provides designers with a complete, ready-to-use solution for programmable logic design. The Xilinx Alliance Series provides designers powerful integration of Xilinx design tools with their existing EDA environment.

HDL Congurations
HDL congurations of the Foundation Series contain integrated VHDL/Verilog synthesis and graphical interactive HDL entry tools with the following features: On-line tutorial teaches the art of VHDL design. Xilinx HDL Editor provides color coding, syntax checking and single click error navigation making it easy to create and debug VHDL, Verilog and ABEL designs. Graphical State Machine editor makes the design of simple or complex state machines simple and intuitive. HDL Language Assistant provides libraries of common functions with optimized VHDL, Verilog and ABEL code. FPGA and CPLD specic synthesis and optimization from Synopsys tools produce high-utilization, highperformance results

Flexible Congurations
Xilinx Software Solutions are available in two device congurations giving designers a cost-effective way to match their tools to the design methodologies they require. These congurations are available for both the Foundation and Alliance Series. Base congurations provide push button design ows and support a broad array of FPGA and CPLD devices targeted for low density and high volume applications. Standard congurations combine push button ows with powerful auto-interactive tools. These tools give designers more inuence and control over implementation while maintaining the benets of design automation. Standard congurations include support for

Alliance Series
The Alliance Series provides powerful and integrated design tools for users who require a quality solution for their chosen EDA design solution. With the Alliance Series, users can choose from a wide range of design techniques including schematic capture, module-based design and HDL design solutions. With standard based design interfaces including EDIF, VITAL, VHDL, Verilog and SDF, this series provides maximum exibility, portability, mixed vendor support, and design reuse.

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Development Systems: Products Overview

Quality integration with leading EDA vendors such as ALDEC, Exemplar, Cadence, Mentor Graphics, Model Technology, OrCAD, Synopsys, Synplicity, Veribest and VIEWlogic provide tightly-coupled environments that make it easy to move through the design process and through a mixed EDA vendor ow. The EDA vendors are supported through the Xilinx Alliance Program, insuring high quality tools and accuracy of results. Information on Xilinx Alliance Program vendors can be found on the Xilinx WEB page www.xilinx.com. The Alliance Series includes an enhanced set of easy-touse features including, design manager, ow engine, installation, on-line documentation, and answer database. In addition, the Alliance Series includes a powerful and complete implementation toolset, LogiBLOX (next generation module generation), fully integrated EDA vendor support, and a powerful gate-level optimizer. Also included are new advanced place and route software that has incremental design capabilities and SMARTspecs (a robust timing constraint language). Users can achieve up to 25% performance improvements with no additional elapse time through the use of the Alliance Series Turns Engine. The Turns Engine uses networked workstations to run multiple place and route passes for a single design. This feature is included with the Alliance Series BASE and Standard workstation development systems. The libraries and interface provide Xilinx Unied Library schematic symbols, HDL synthesis libraries, VITAL(VHDL) and Verilog simulation models with timing information and translators through a standard netlist format. All of these tools provide a complete spectrum of high density design methodologies from fully-automatic to hand-crafted and close integration with Xilinx LogiCores and AllianceCore partners.

which delivers push-button design ows and incremental design capabilities. These Xilinx-exclusive capabilities leverage results from previous design iterations to reduce runtimes and shorter design iterations to less than ten minutes. As engineers design complex circuits incrementally, this technology allows them to work in their preferred methodology. M1 Technology also delivers advanced timing driven placeand route capabilities to deliver maximum design performance through push-button ows.

M1 Technical Benets
Maximum Design Performance
M1 technology enables the user to achieve maximum design performance by providing a unique combination of advanced algorithms and interactive tools. Designer productivity is greatly enhanced through use of simple, pushbutton ows and optional auto-interactive tools. Customer testing has shown that M1 technology used with XC4000XL/XV devices results in 70 percent shorter run times, up to a 25 percent performance improvement, and the ability to place and route devices with up to 100 percent utilization with a push-button ow.

Modular Software System

The modular architecture of the Xilinx M1 technology allows rapid delivery of incremental technologies, new features, device support, and versions of its leading software product families. New feature sets can now be released independently resulting in users ability to quickly complete designs without having to re-learn new tools as enhancements are made. The investment Xilinx has made in the M1 technology ensures that the continuous delivery of innovative device architectures and improved software solutions can be done more rapidly, and predictably than previous software versions.

Alliance Series Options

VIEWlogic Workview Ofce Development System options as part of the Alliance Series are intended for users who want the integration of a complete solution with the power to access board and system level design tools. These products include VIEWlogic Workview Ofce schematic capture and simulation tools.

Methodology Flexibility
High-level design methodologies are becoming the methodology choice for the design of complex programmable logic. M1 technology delivers programmable logic specic high-level ows. The ows provide high-quality, high performance optimized results, and afford fast, exible design changes and iterations to match the way engineers design. Designers employ a mixture of graphical and languagebased design entry methods while providing an easy-tolearn environment for Hardware Description Language (HDL) based design. Xilinx recognizes that design environments are variant and, therefore, has created a exible system enabling the customer to choose the best methodology for their environment or design challenge.

Xilinx M1 Software Technology

M1 technology represents Xilinxs next generation software technology. This advanced technology developed as a result of the Xilinx merger with NeoCAD Inc., enables digital system designers to increase design performance, leverage standards-based, high-level design methodologies and quickly receive new software features and device support through Xilinx Foundation Series and Alliance Series software solutions.

Increased Design Performance

The M1 technology provides dramatically improved design performance through advanced place-and-route software

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Development Systems: Product Descriptions

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Development Systems Descriptions

Its simple to order a Xilinx Development System. Just choose a Foundation or Alliance Series and a few options. Give your local Xilinx Sales Office a call for information about our evaluation kits.

Foundation Series
Foundation Base System (PC) Foundation Base-Express System (PC) Foundation Standard System (PC) Foundation Express System (PC)

Alliance Series
Alliance Base (PC or Workstation) Alliance Standard (PC or Workstation)

Alliance Series Options

VIEWlogic Workview Ofce Standard Development System Options (PC)

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Development Systems: Product Descriptions

Foundation Series: Foundation Base System (PC)

Overview
The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Base System provides design entry (schematic and Abel HDL), simulation, and device implementation tools for a broad array of FPGA and CPLD devices targeted for low density and high volume applications.

Package Features - Foundation Base System

Feature CPLD Devices FPGA Devices Libraries and Interface Schematic Editor HDL Editor Graphical State Editor ABEL 6 Entry / Synthesis VHDL Entry / Synthesis Verilog Entry / Synthesis Schematic-centric Synthesis HDL-centric Synthesis Simulator Device Implementation Maintenance2
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System Features
Project manager Schematic editor Integrated HDL editor with support for the Abel 6 HDL Functional and timing simulator EDIF, VHDL (VITAL compliant), and Verilog / SDF design interfaces Device implementation software for Xilinx CPLDs and FPGAs Comprehensive on-line help, on-line documentation, and software tutorials Software maintenance, including hotline support and software updates

FND FND FND FND BAS STD BSX EXP 1 1

Device Support
CPLDs: - XC9500 FPGAs: - XC4000E/X Up to XC4010E/X - Spartan - XC3x00A/L - XC5200 Up to XC5210 FPGAs

Notes: 1. Spartan, XC3x00A/X, XC4000E/X up to XC4010E/X, and XC5200 up to XC5210. 2. A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information.

Required Hardware Environment

Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements: 32 MB RAM, 32-64 MB Virtual Memory CD-ROM drive

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Foundation Series: Foundation Base-Express System with VHDL/Verilog Synthesis (PC)

Overview
The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Express System incorporates advanced synthesis technology from Synopsys, and provides design entry (schematic and HDL), VHDL and Verilog synthesis, simulation, and device implementation tools for a broad array of FPGA and CPLD devices targeted for low density and high volume applications.

Package Features - Foundation Base-Express System

Feature CPLD Devices FPGA Devices Libraries and Interface Schematic Editor HDL Editor Graphical State Editor ABEL 6 Entry / Synthesis VHDL Entry / Synthesis Verilog Entry / Synthesis Schematic-centric Synthesis HDL-centric Synthesis Simulator Device Implementation Maintenance2
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System Features
Project manager Schematic editor Integrated HDL editor with support for VHDL, Verilog, and Abel 6 HDL VHDL and Verilog synthesis, including compilation and optimization Functional and timing simulator EDIF, VHDL (VITAL compliant), and Verilog / SDF design interfaces Device implementation software for Xilinx CPLDs and FPGAs Comprehensive on-line help, on-line documentation, and software tutorials Software maintenance, including hotline support and software updates

FND FND FND FND BAS STD BSX EXP 1 1

Device Support
CPLDs: - XC9500 FPGAs: - XC4000E/X Up to XC4010E/X - Spartan - XC3x00A/L - XC5200 Up to XC5210 FPGAs

Notes: 1. Spartan, XC3x00A/L, XC4000E/X up to XC4010E/X, and XC5200 up to XC5210. 2. A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information.

Required Hardware Environment

Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements: 32 MB RAM, 32-64 MB Virtual Memory CD-ROM drive

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Development Systems: Product Descriptions

Foundation Series: Foundation Standard System (PC)

Overview
The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Standard System provides design entry (schematic and Abel HDL), simulation, and device implementation tools for all Xilinx CPLDs and Xilinx FPGAs.

Package Features - Foundation Base System

Feature CPLD Devices FPGA Devices Libraries and Interface Schematic Editor HDL Editor Graphical State Editor ABEL 6 Entry / Synthesis VHDL Entry / Synthesis Verilog Entry / Synthesis Schematic-centric Synthesis HDL-centric Synthesis Simulator Device Implementation Maintenance2
11/12/97

System Features
Project manager Schematic editor Integrated HDL editor with support for the Abel 6 HDL Functional and timing simulator EDIF, VHDL (VITAL compliant), and Verilog / SDF design interfaces Device implementation software for Xilinx CPLDs and FPGAs Comprehensive on-line help, on-line documentation, and software tutorials Software maintenance, including hotline support and software updates

FND FND FND FND BAS STD BSX EXP 1 1

Device Support
CPLDs: - XC9500 FPGAs: - XC4000E/X - Spartan - XC3x00A/L - XC5200

Notes: 1. Spartan, XC3x00A/L, XC4000E/X up to XC4010E/X, and XC5200 up to XC5210. 2. A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information.

Required Hardware Environment

Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements - Small Devices (< 10K gates): 32 MB RAM, 32-64 MB Virtual Memory - Medium Devices (10K to 30K gates): 64 MB RAM, 64-128 MB Virtual Memory - Large Devices (> 30K gates): 128 MB RAM, 128-256 MB Virtual Memory CD-ROM drive

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Foundation Series: Foundation Express System (PC)

Overview
The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Express System incorporates advanced synthesis technology from Synopsys, and provides design entry (schematic and HDL), VHDL and Verilog synthesis, simulation, and device implementation tools for all Xilinx CPLDs and Xilinx FPGAs.

Package Features - Foundation Base System

Feature CPLD Devices FPGA Devices Libraries and Interface Schematic Editor HDL Editor Graphical State Editor ABEL 6 Entry / Synthesis VHDL Entry / Synthesis Verilog Entry / Synthesis Schematic-centric Synthesis HDL-centric Synthesis Simulator Device Implementation Maintenance2
11/12/97

System Features
Project manager Schematic editor Integrated HDL editor with support for VHDL, Verilog, and Abel 6 HDL VHDL and Verilog synthesis, including compilation and optimization Functional and timing simulator EDIF, VHDL (VITAL compliant), and Verilog / SDF design interfaces Device implementation software for Xilinx CPLDs and FPGAs Comprehensive on-line help, on-line documentation, and software tutorials Software maintenance, including hotline support and software updates

FND FND FND FND BAS STD BSX EXP 1 1

Device Support
CPLDs: - XC9500 FPGAs: - XC4000E/X - Spartan - XC3x00A/L - XC5200

Notes: 1. Spartan, XC3x00A/L, XC4000E/X up to XC4010E/X, and XC5200 up to XC5210. 2. A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information.

Required Hardware Environment

Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements - Small Devices (< 10K gates): 32 MB RAM, 32-64 MB Virtual Memory - Medium Devices (10K to 30K gates): 64 MB RAM, 64-128 MB Virtual Memory - Large Devices (> 30K gates): 128 MB RAM, 128-256 MB Virtual Memory CD-ROM drive

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Development Systems: Product Descriptions

Alliance Series: Alliance Base (PC or Workstation)

Overview
Next generation FPGA/CPLD design solutions leveraging Open Systems integration with premier EDA partners for devices up to 10,000 gates.

Libraries and Interfaces

Cadence
Concept schematic libraries and Verilog-XL simulation models Falcon Framework schematic capture library and ModelSim simulation models Leonardo synthesis libraries and interfaces are available from Mentor or Exemplar Logic HDL Design Solutions (VHDL and Verilog) Design Compiler, FPGA Compiler II, FPGA Express, VSS Vital Simulation models DesignWare arithmetic modules

Base System Features:

EDA Libraries & Interfaces Design Manager and Flow Engine LogiBLOX Module Generator Gate Optimizer Complete HDL design methodology support Incremental design capabilities Place and route utilizing SMARTspecs Re-entrant router Multi-pass PAR Timing Analyzer Standard netlist and backannotation (EDIF, SDF, VITAL VHDL and Verilog) Xchecker Hardware Debugger (workstation only)

Mentor

Synopsys

* No libraries required to support FPGA Express

VIEWlogic
Workview Ofce schematic capture library and functional and timing simulation interface Leonardo and Galileo synthesis libraries and interfaces are available from Exemplar Logic Synplify synthesis libraries and interfaces are available from Synplicity ModelSim, V-System HDL simulation libraries and interface

Package Includes:
Alliance Quick Start Guide Alliance Release Document Answer Database Core Technology CD CAE Libraries CD On-line Documentation CD with DynaText browser Hardware Cable Demoboard

Exemplar

Synplicity

Device Support:
CPLDs: - XC9500 FPGAs: - XC4000E/X Up to XC4010E/X - Spartan - XC3x00A/L - XC5200 Up to XC5210 FPGAs

Model Technology

Contact your local EDA sales ofce to purchase these EDA tools.

Support and Updates Include:

Answers Database - http://www.xilinx.com or Answers electronic book included. Hotline Telephone Support Apps FAX and E-Mail Online Documentation World Wide Web Access Technical Newletter Extensive Application Notes Software Updates (for in-maintenance customers) - A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information

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Required Hardware Environment (PC)

Fully IBM compatible PC486/Pentium - NEC98 supported Windows 95, Windows NT 4.0 - Chinese, Korean and Japanese versions Minimum 300 Mbytes hard-disk space CD-ROM drive VGA display Serial port mouse One parallel and two serial ports 32 MB RAM (Use additional RAM to increase performance) 32 MB - 64 MB Virtual Memory

Required Hardware Environment (Workstation)

Ultra Sparc (or equivalent) - Sun OS 4.1.3 and 4.1.4 - Solaris 2.5 HP715 (or equivalent) - HP-UX 10.2 RS6000 - AIX 4.1.5 (no GUIs) 64 MB RAM (Use additional to increase performance) 64MB min Swap Space Color Monitor

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Development Systems: Product Descriptions

Alliance Series: Alliance Standard (PC or Workstation)

Overview
Next generation FPGA/CPLD design solutions leveraging Open Systems integration with premier EDA partners for unlimited gate capacity.

Libraries and Interfaces

Cadence
Concept schematic libraries and Verilog-XL simulation models Falcon Framework schematic capture library and ModelSim simulation models Leonardo synthesis libraries and interfaces are available from Mentor or Exemplar Logic HDL Design Solutions (VHDL and Verilog) Design Compiler, FPGA Compiler II, FPGA Express, VSS Vital Simulation models DesignWare arithmetic modules

Base System Features:

EDA Libraries & Interfaces Design Manager and Flow Engine LogiBLOX Module Generator Gate Optimizer Full HDL design methodology support Incremental design capabilities Place and route utilizing SMARTspecs Re-entrant router Multi-pass PAR Timing Analyzer Standard netlist and backannotation (EDIF, SDF, VITAL VHDL and Verilog) Xchecker Hardware Debugger (workstation only)

Mentor

Synopsys

* No libraries required to support FPGA Express

VIEWlogic
Workview Ofce schematic capture library and functional and timing simulation interface Leonardo and Galileo synthesis libraries and interfaces are available from Exemplar Logic Synplify synthesis libraries and interfaces are available from Synplicity ModelSim, V-System HDL simulation libraries and interface

Package Includes:
Alliance Quick Start Guide Alliance Release Document Answer Database Core Technology CD CAE Libraries CD On-line Documentation CD with DynaText browser Hardware Cable Demoboard

Exemplar

Synplicity

Model Technology

Device Support:
CPLDs: - XC9500 FPGAs: - XC4000E/X - Spartan - XC3x00A/L - XC5200

Contact your local EDA sales ofce to purchase these EDA tools.

Support and Updates Include:

Answers Database - http://www.xilinx.com or Answers electronic book included. Hotline Telephone Support Apps FAX and E-Mail Online Documentation World Wide Web Access Technical Newletter Extensive Application Notes Software Updates (for in-maintenance customers) - A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information

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Required Hardware Environment (PC)

Fully IBM compatible PC486/Pentium - NEC98 supported Windows 95, Windows NT 4.0 - Chinese, Korean and Japanese versions Minimum 300 Mbytes hard-disk space CD-ROM drive VGA display Serial port mouse One parallel and two serial ports Small Devices: (8K or <) XC9536 - XC95108; XC4003E - XC4008E; XC4005XL - XC4008XL - 32 MB RAM (Use additional RAM to increase performance) - 32 -64 MB Virtual Memory Medium Devices: (10K- 28K) XC95144 - XC95216; XC4010E - XC4025E; XC4028EX - XC4036EX; XC4010XL - XC4028XL - 64 MB RAM (Use additional RAM to increase performance) - 64-128 MB Virtual Memory Large Devices: (36K or >) XC4036XL - XC4062XL - 128K RAM (Use additional RAM to increase performance) - 128 - 256 MB Virtual Memory

Required Hardware Environment (Workstation)

Ultra Sparc (or equivalent) - Sun OS 4.1.3 and 4.1.4 - Solaris 2.5 HP715 (or equivalent) - HP-UX 10.2 RS6000 - AIX 4.1.5 (no GUIs) Small Devices: (28K or <) XC4000E; XC4028EX - XC4036EX; XC4005XL - XC4028XL - 64 MB RAM (Use additional RAM to increase performance) - 64MB min Swap Space Large Devices (36K or >) XC4036XL - XC4062XL - 128 MB RAM (Use additional RAM to increase performance) - 128 MB min Swap Space Color Monitor

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Development Systems: Product Descriptions

Alliance Series Options (PC)

Overview
VIEWlogic Workview Ofce schematic capture and gate simulator development system with libraries and interfaces for Xilinx FPGAs and CPLDs.

Support and Updates Include:

Answers Database - http://www.xilinx.com or Answers electronic book included. Hotline Telephone Support Apps FAX and E-Mail Software Updates (for in-maintenance customers) Online Documentation World Wide Web Access Technical Newletter Extensive Application Notes

Workview Ofce Standard Features:

Workview Ofce schematic editor Workview Ofce gate simulator Libraries and interfaces Hotline support Software maintenance for 90-days

Required Hardware Environment:

Fully IBM compatible PC486/Pentium Windows 95, Windows NT 4.0 - Chinese, Korean and Japanese versions Minimum 500 Mbytes hard-disk space CD-ROM drive VGA display Serial port mouse One parallel and two serial ports 64 Mbytes RAM recommended (increase to improve performance)

Libraries Support:
CPLDs: - XC9500 FPGAs: - XC4000E/X - Spartan - XC3x00A/L - XC5200

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CORE Solutions Overview

0 2*

September 5, 1997 (Version 1.0)

Product Overview view) which lists all of the functions available today. This table will be your best guide to locating a specic product. If you don't see what you need, check the AllianceCORE Partner Proles, Areas of Expertise section, for each of our AllianceCORE partners. Our partners will be more than willing to discuss the possibility of producing a core specifically for your needs.

Background
The ASIC core industry has been developing for over a decade. Today there exists a wealth of intellectual property (IP) that is readily available from numerous sources. During this time, however, programmable logic did not have the density or the performance needed to accommodate large IP cores. Today, things have changed considerably. Xilinx is shipping FPGAs like the XL family that have usable densities up to 125,000 gates. Now, not only is the use of pre-dened logic functions in programmable logic a possibility, it is becoming a requirement to meet ever-shrinking product development cycles. As a result, many ASIC core vendors and system designers are beginning to look at using cores for their programmable logic designs. It is for this reason that Xilinx created the CORE Solutions portfolio of products.

Data Book Contents

The contents of the data book are as follows: Introduction - Program Overview - Product Listing by Application Segment LogiCORE Products, sold and supported by Xilinx - Product Overview - PCI - DSP - CORE Generator products AllianceCORE Products, sold and supported by Xilinx' Partners - Program Overview - Products - AllianceCORE Partner Proles LogiBLOX, GUI-based small function generator Reference Designs Sales Ofces, Representatives and Distributors

CORE Solutions Products

CORE Solutions products support four application areas. The application areas are as follows: Standard Bus Interfaces - such as PCI, PCMCIA, USB and Plug-and-Play ISA. DSP Functions - These range from small building blocks such adders, registers and multipliers, to larger system-level functions such as FIR lters and ReedSolomon coders. Telecom and Networking - building blocks for popular communications standards. Base-Level Functions - a broad category of functions used across many application segments. These include the every small parameterizable LogiBLOX macros up through larger functions such as UARTs and DMA controllers.

Ordering Information
To order a copy, request the CORE Solutions Data Book from the Xilinx Literature Department. In the US call 1-800231-3386. For international locations call 1-408-879-5017 or you can send an E-mail request to: [email protected]. An electronic version of the CORE Solutions Data Book (1.2M Adobe Acrobat .pdf format) can also be downloaded from: www.xilinx.com/products/logicore/core_sol.pdf

CORE Solutions Data Book

The goal of the CORE Solutions portfolio of products is to provide cores with the shortest time-to-market and best possible device utilization the programmable logic industry has to offer. Xilinx has published a brand new data book focused entirely on programmable logic cores and related products. Now there is one denitive sourcebook with detailed descriptions of all Xilinx CORE Solutions. When you receive your copy of the CORE Solutions Data Book, become familiar with the Product Listing by Application Segment Table, (reproduced at the end of this over-

LogiCORE Products
LogiCORE products are sold, licensed and supported by Xilinx. They are developed internally by Xilinx or jointly with a partner. The cores that Xilinx provides as LogiCORE products typically fall into one of two categories.The rst are high-performance interface cores that require a thorough understanding and control of the FPGA technology and

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CORE Solutions Overview

implementation software in order to achieve the desired performance and complexity. An example of a core in this category is the LogiCORE PCI interface. The second category are cores that benet from a very specialized implementation in the FPGA. An example is the LogiCORE DSP modules that are implemented using a unique algorithm, Distributed Arithmetic. This algorithm ts the lookup-table-based architecture of the FPGA. The result is outstanding performance and device utilization, often more than 10 times better than generic HDL descriptions.

PCI is an extremely high-performance and complex specication that is challenging to meet in any technology. To meet the stringent PCI specication the core is carefully hand-tuned for the targeted architecture. Placement and routing for the critical parts of the core is locked down to ensure that timing can be met every time the core is used. To achieve our goals, the LogiCORE development team is working closely with both the IC and Software teams. As an example of this teamwork, new methodologies for characterizing and modeling our FPGAs have been developed. The result is access to state of the art technology and expertise, that allows you to complete your PCI application in record time. Xilinx has sold over 250 licenses of the LogiCORE PCI interface and has built up solid knowledge about PCI. We are committed, and will continuously develop our PCI products to remain state of the art.

Xilinx CORE Generator

In addition to actual cores, Xilinx is committed to develop enabling design tools and methodologies to facilitate usage of cores with FPGAs. The rst products available in this category are the web-based CORE Generator for PCI and the CORE Generator for DSP (available on CD). This innovative methodology for acquiring and using cores combines the benets of a rm core with predictable performance, and the exibility of system level design, facilitated by behavioral languages such as VHDL and Verilog.

Xilinx DSP Solutions

Using an FPGA to implement high performance DSP functions often allows a radical performance advantage over xed processors while maintaining maximum exibility and the shortest time-to-market. Until now, tools to automate the design process have been lacking and most designs have been completed manually by experienced FPGA designers. With the introduction of Xilinx CORE Generator for DSP, complex parameterized DSP building blocks can be implemented automatically with performance and density equal to or better than a hand-tuned implementation. LogiCORE DSP modules can be used with VHDL-, Verilog- or schematic based design methodologies. Higher level DSP cores are available from our AllianceCORE partners.

In addition, because Xilinx is using the web as a distribution mechanism, you always have access to the latest versions and enhancements of the cores at: www.xilinx.com/products/logicore/logicore.htm The LogiCORE products are customized to t your specic application using an intuitive graphical user interface. Based on your inputs, the tool then generates a proven core with highly predictable timing that can be integrated using any VHDL-, Verilog- or schematic-based design ow. As a result, you can integrate several individually proven cores with given performance into one system on a single FPGA. Because each core is already veried, the time-tomarket benets are maintained for high-complexity FPGAs.

Acquiring LogiCORE Products

LogiCORE products are available from your local Xilinx sales representative similar to other Xilinx software products. Xilinx and your local sales representative will also be your primary source for support of the core, the devices and the design tools. You can also send email questions to: [email protected].

Xilinx PCI Solutions

Xilinx PCI solution includes devices, tools and cores needed to build a cost-effective single-chip PCI system in record time. LogiCORE PCI - the only proven PCI core with predictable timing XC4000E/XL - the industrys fastest FPGAs that allow you to integrate the PCI interface plus 5 to 60 thousand gates of user designed logic HardWire - an automatic migration path to a low-cost chip for volume production CORE Generator - for easy conguration and integration of the LogiCORE PCI module 3rd party Design Centers - with PCI expertise available for special applications and customization of the core

AllianceCORE Overview
The AllianceCORE program is a cooperative effort between Xilinx and independent third-party core developers. It is designed to produce a broad selection of industry-standard solutions dedicated for use in Xilinx programmable logic. Xilinx takes an active role with its partners in the process of productizing AllianceCOREs. This is unique to the AllianceCORE program. Because the process is so involved,

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we work closely with our partners to select the right cores rst. This naturally limits the number of partners we can work with at any one time and subsequently the number of available cores. At the same time it raises the quality and usability of the cores that are offered.

tee functionality and compliance. AllianceCOREs originated from either schematic or HDL entry tools.

Core Integration
AllianceCOREs are not just cores, they are complete solutions for system designs. While cores by themselves have value, in many cases it is often not enough to just supply a generic core. You may need additional tools such as system software and prototyping equipment to help you rapidly integrate the core into your design, perform system debug in a real-world environment, and then quickly convert the prototype to a production unit. This is particularly true of complex functions. Many AllianceCORE functions are supported by Xilinxbased demonstration or prototyping boards. Some also have system simulation models or debug software. All of this allows you to evaluate and work with the function before you have to layout your board. These tools are provided by the AllianceCORE partner, usually at additional cost. Descriptions of the support tools available for each core are included in the CORE Solutions Data Book. Complete solutions like these help preserve the value of using programmable logic while minimizing the support burden for the core provider.

AllianceCORE Criteria
A core must meet a minimum set of criteria before it can receive the AllianceCORE label.

Core Selection
The AllianceCORE program looks at cores from a practical point of view. A programmable logic version of a core must have value over an ASIC or standard product version of the same function. It must be cost effective and make sense for use in a programmable device in a production system. If a candidate core does not pass these simple tests, then it does not make sense to invest the effort to convert it to an AllianceCORE module.

Core Qualication
Generic, synthesizable cores offer maximum exibility for users with unique requirements. This is typically the format for cores provided to the ASIC market. With programmable logic, however, this exibility can come at the expense of efciency and performance. It can take a considerable amount of effort to get a specic core to synthesize in a way that meets density and timing requirements. Time spent trying to accomplish this can quickly reduce the time-tomarket advantage of using programmable logic and cores in the rst place. Xilinx is not interested in promoting generic, synthesizable functions as AllianceCOREs. Instead, AllianceCOREs are generally provided as parameterizable black-boxes that allow customization in critical areas. This guarantees that the implementation is optimized for density while still meeting performance, preserving the time-to-market value of programmable logic. Flexibility is provided by allowing you to quickly implement your unique logic on the same device. Source code versions of the cores are also available from the partners at additional cost for those who need ultimate exibility. Announced AllianceCOREs have been implemented and veried in a Xilinx device. They are available immediately for purchase in a Xilinx-specic format. Timing-critical cores designed to adhere to an industry standard also come with appropriate constraints les in order to guaran-

Acquiring AllianceCORE Products

AllianceCORE products are sold and serviced directly by the AllianceCORE partners since they are the experts for their particular products. They are responsible for pricing, licensing terms, delivery and technical support. Contact information for each partner is included in the AllianceCORE Partner Proles section of the CORE Solutions Data Book. If you want additional information about the AllianceCORE program or are interested in becoming a partner, contact Xilinx directly. Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Attn: Mark Bowlby, AllianceCORE Product Manager Phone: +1 408-879-5381 Fax: +1 408-879-4780 E-mail: [email protected] URL: www.xilinx.com/products/logicore /alliance/tblpart.htm

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CORE Solutions Overview

Table 1: Product Listing by Application Segment

Check www.xilinx.com/products/logicore/tbls_cores.htm for the latest listing of available Cores

Function Standard Bus Interfaces IIC Two-Wire Serial Interface ISA Plug and Play Interface ISA Interface for JPEG Motion Codec PCI Master/Slave Interfaces 1.2.0 PCI Master/Slave Interfaces 2.0.0 PCMCIA Fax/Modem PCMCIA Library USB - Low-Speed Function Controller USB - Full-Speed Function Controller USB - 3-Port Hub Controller DSP Functions 1s Complement Accumulator, Scaled by 1/2 Adder, Registered Adder, Registered Loadable Adder, Registered Scaled Adder, Registered Serial Adders, Subtractors, Accumulators Comb Filter Correlator, 1-D RAM Based Correlator, 1-D ROM Based Delay Element FIR Filter, 16-Tap, 8-Bit FIR Filter - Serial Distributed Arithmetic FIR Filter - Dual Channel Serial Distributor Arithmetic Integrator Memory - 16-Word Deep Register Look-up Table Memory - 32-Word Deep Register Look-up Table Memory - 16-Word Deep Registered RAM Memory - 32-Word Deep Registered RAM Memory - Registered Synchronous RAM Memory - Registered ROM Multiplier, Constant Coefficient Multiplier, Constant Coefficient (pipelined) Multipliers, Parallel - Area Optimized Multipliers, Parallel - Performance Optimized Parallel to Serial Converter Reed-Solomon Decoder Reed-Solomon Encoder SDA FIR Control Logic Sine/Cosine Square Root Subtracter, Registered Subtracter, Registered Loadable CORE Solution AllianceCORE Reference Design Reference Design LogiCORE LogiCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE Reference Design LogiCORE LogiCORE LogiCORE LogiCORE Reference Design LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE AllianceCORE AllianceCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE

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Table 1: Product Listing by Application Segment (Continued)

Check www.xilinx.com/products/logicore/tbls_cores.htm for the latest listing of available Cores

Function Time Skew Buffer - Non-Symmetric 16-Deep Time Skew Buffer - Non-Symmetric 32-Deep Time Skew Buffer - Symmetric 16-Deep Transform, DFT Transform, FFT Base-Level Functions 16450 UART 16550A UART with RAM 8250 Asynchronous Communications 8254 Programmable Timer M8255 Programmable Peripheral Interface XF8255 Programmable Peripheral Interface Accumulator Adder/Subtracter Clock Divider Comparator Constant Constant Counter Counter, Loadable Binary Counter, Ultra-Fast Synchronous Counter, Accelerating Loadable Data Register Decoder FIFOs in XC4000 RAM FIFO, High-Performance RAM-Based FIFO, Register-Based Frequency/Phase Comparator for PLL Gates, Simple Harmonic Frequency Synthesizer and FSK Modulator Input/Output Microcontroller, Dynamic Memory (ROM, RAM, Synch-RAM, Dual Port RAM) Multiplexer Multiplexers, Barrel Shifters Multiplexer, Two Input Multiplexer, Three Input Multiplexer, Four Input Pad Pulse-Width Modulation Register Serial Code Conversion between BCD and Binary Shift Register Tristate CORE Solution LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE LogiBLOX LogiBLOX LogiBLOX LogiBLOX LogiCORE LogiBLOX LogiBLOX Reference Design Reference Design Reference Design LogiBLOX LogiBLOX Reference Design Reference Design Reference Design Reference Design LogiBLOX Reference Design LogiBLOX Reference Design LogiBLOX LogiBLOX Reference Design LogiCORE LogiCORE LogiCORE LogiBLOX Reference Design LogiCORE Reference Design LogiBLOX LogiBLOX

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CORE Solutions Overview

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CPLD Products

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

CPLD Products Table of Contents

CPLD Products
XC9500 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 XC9500 In-System Programmable CPLD Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 XC9536 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 XC9572 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 XC95108 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 XC95144 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 XC95216 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 XC95288 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65

XC9500 Series Table of Contents

1 3*

XC9500 In-System Programmable CPLD Family

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FastCONNECT Switch Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin-Locking Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 Boundary-Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development System Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FastFLASH Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-5 3-5 3-7 3-8 3-10 3-13 3-14 3-15 3-16 3-16 3-16 3-16 3-16 3-17 3-17 3-18 3-19 3-19

XC9536 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9536 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9536 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3-21 3-21 3-23 3-23 3-23 3-24 3-24 3-25 3-26 3-26 3-27 3-27

XC9572 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9572 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9572 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3-29 3-29 3-31 3-31 3-31 3-32 3-32 3-33 3-34 3-35 3-36 3-1

XC9500 Series Table of Contents

Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

XC95108 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3-37 3-37 3-39 3-39 3-39 3-40 3-40 3-41 3-42 3-43 3-43 3-44 3-44

XC95144 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3-45 3-45 3-47 3-47 3-47 3-48 3-48 3-49 3-50 3-51 3-52 3-53 3-53

XC95216 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 3-55 3-55 3-57 3-57 3-57 3-58 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-64

XC95288 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65

3-2

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-67 3-67 3-67 3-68 3-68 3-69 3-70 3-71 3-72 3-73 3-74 3-75 3-75

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XC9500 Series Table of Contents

3-4

XC9500 In-System Programmable CPLD Family

0 3*

November 10, 1997 (Version 2.0)

Product Information

Features
High-performance - 5 ns pin-to-pin logic delays on all pins - fCNT to 125 MHz Large density range - 36 to 288 macrocells with 800 to 6,400 usable gates 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-5, -7, -10 speed grades) Advanced CMOS 5V FastFLASH technology Supports parallel programming of multiple XC9500 devices

Family Overview
The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members. As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 to 288 registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in a given package footprint. The XC9500 architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. An expanded JTAG instruction set allows version control of programming patterns and in-system debugging. In-system programming throughout the full device operating range and a minimum of 10,000 program/erase cycles provide worry-free recongurations and system eld upgrades. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. I/Os may be congured for 3.3 V or 5 V operation. All outputs provide 24 mA drive.

Architecture Description
Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the FastCONNECT switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with 36 inputs and 18 outputs. The FastCONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs. See Figure 1.

November 10, 1997 (Version 2.0)

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XC9500 In-System Programmable CPLD Family

3 JTAG Port

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18

Function Block 1 Macrocells 1 to 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2 or 4

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block N Macrocells 1 to 18

X5877

Figure 1: XC9500 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

Table 1: XC9500 Device Family XC9536 36 800 36 5 4.5 4.5 100 100 XC9572 72 1,600 72 7.5 5.5 5.5 125 83 XC95108 108 2,400 108 7.5 5.5 5.5 125 83 XC95144 144 3,200 144 7.5 5.5 5.5 125 83 XC95216 216 4,800 216 10 6.5 6.5 111 67 XC95288 288 6,400 288 15 8.0 8.0 95 56

Macrocells Usable Gates Registers tPD (ns) tSU (ns) tCO (ns) fCNT (MHz) fSYSTEM (MHz)

Note: fCNT = Operating frequency for 16-bit counters

fSYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs.

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November 10, 1997 (Version 2.0)

Figure 2: Available Packages and Device I/O Pins (not including dedicated JTAG pins) XC9536 34 34 XC9572 34 69 72 72 XC95108 XC95144 XC95216 XC95288

44-Pin VQFP 44-Pin PLCC 84-Pin PLCC 100-Pin TQFP 100-Pin PQFP 160-Pin PQFP 208-Pin HQFP 352-Pin BGA

69 81 81 108

81 81 133

133 166 166

168 192

Function Block
Each Function Block, as shown in Figure 3, is comprised of 18 independent macrocells, each capable of implementing a combinatorial or registered function. The FB also receives global clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the FastCONNECT switch matrix. These 18 outputs and their corresponding output enable signals also drive the IOB. Logic within the FB is implemented using a sum-of-products representation. Thirty-six inputs provide 72 true and complement signals into the programmable AND-array to form 90 product terms. Any number of these product terms, up to the 90 available, can be allocated to each macrocell by the product term allocator. Each FB (except for the XC9536) supports local feedback paths that allow any number of FB outputs to drive into its own programmable AND-array without going outside the FB. These paths are used for creating very fast counters and state machines where all state registers are within the same FB.

Macrocell 1

Programmable AND-Array From FastCONNECT Switch Matrix

Product Term Allocators

18

36 18 18 OUT PTOE

To FastCONNECT Switch Matrix

To I/O Blocks

Macrocell 18 1 Global Set/Reset 3 Global Clocks

X5878

Figure 3: XC9500 Function Block

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XC9500 In-System Programmable CPLD Family

Macrocell
Each XC9500 macrocell may be individually congured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Figure 4. Five direct product terms from the AND-array are available for use as primary data inputs (to the OR and XOR gates) to implement combinatorial functions, or as control inputs including clock, set/reset, and output enable. The product term allocator associated with each macrocell selects how the ve direct terms are used. The macrocell register can be congured as a D-type or Ttype ip-op, or it may be bypassed for combinatorial operation. Each register supports both asynchronous set and reset operations. During power-up, all user registers are initialized to the user-dened preload state (default to 0 if unspecied).
Global Set/Reset Global Clocks

36

Additional Product Terms (from other macrocells)

Product Term Set 1 0 S D/T Q Product Term Allocator

To FastCONNECT Switch Matrix

Product Term Clock Product Term Reset

OUT Product Term OE PTOE To I/O Blocks

Additional Product Terms (from other macrocells)

X5879

Figure 4: XC9500 Macrocell Within Function Block

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November 10, 1997 (Version 2.0)

All global control signals are available to each individual macrocell, including clock, set/reset, and output enable signals. As shown in Figure 5, the macrocell register clock originates from either of three global clocks or a product

term clock. Both true and complement polarities of a GCK pin can be used within the device. A GSR input is also provided to allow user registers to be set to a user-dened state.

Macrocell Product Term Set

Product Term Clock

S D/T

R Product Term Reset

I/O/GSR

Global Set/Reset

I/O/GCK1 Global Clock 1

I/O/GCK2

Global Clock 2

I/O/GCK3

Global Clock 3

X5880

Figure 5: Macrocell Clock and Set/Reset Capability

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XC9500 In-System Programmable CPLD Family

Product Term Allocator

The product term allocator controls how the ve direct product terms are assigned to each macrocell. For example, all ve direct terms can drive the OR function as shown in Figure 6.
Product Term Allocator

Note that the incremental delay affects only the product terms in other macrocells. The timing of the direct product terms is not changed.
Product Term Allocator

Macrocell Product Term Logic

Product Term Allocator

X5894

Figure 6: Macrocell Logic Using Direct Product Term The product term allocator can re-assign other product terms within the FB to increase the logic capacity of a macrocell beyond ve direct terms. Any macrocell requiring additional product terms can access uncommitted product terms in other macrocells within the FB. Up to 15 product terms can be available to a single macrocell with only a small incremental delay of tPTA, as shown in Figure 7.
Product Term Allocator

Macrocell Logic With 15 P-Terms

X5895

Figure 7: Product Term Allocation With 15 Product Terms

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November 10, 1997 (Version 2.0)

The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in Figure 8.
Product Term Allocator

In this example, the incremental delay is only 2*tPTA. All 90 product terms are available to any macrocell, with a maximum incremental delay of 8*tPTA.

Macrocell Logic With 2 Product Terms Product Term Allocator

Product Term Allocator

Macrocell Logic With 18 Product Terms

Product Term Allocator

X5896

Figure 8: Product Term Allocation Over Several Macrocells

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XC9500 In-System Programmable CPLD Family

The internal logic of the product term allocator is shown in Figure 9.

From Upper Macrocell To Upper Macrocell

Product Term Allocator

Product Term Set

Global Set/Reset

1 0

S D/T Q Global Clocks Product Term Clock R

Product Term Reset

Global Set/Reset Product Term OE

From Lower Macrocell

To Lower Macrocell

X5881

Figure 9: Product Term Allocator Logic

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November 10, 1997 (Version 2.0)

FastCONNECT Switch Matrix

The FastCONNECT switch matrix connects signals to the FB inputs, as shown in Figure 10. All IOB outputs (corresponding to user pin inputs) and all FB outputs drive the FastCONNECT matrix. Any of these (up to a FB fan-in limit of 36) may be selected, through user programming, to drive each FB with a uniform delay. The FastCONNECT switch matrix is capable of combining multiple internal connections into a single wired-AND output before driving the destination FB. This provides additional logic capability and increases the effective logic fanin of the destination FB without any additional timing delay. This capability is available for internal connections originating from FB outputs only. It is automatically invoked by the development software where applicable.

FastCONNECT Switch Matrix

Function Block

I/O Block (36) D/T Q 18 I/O

Function Block

I/O Block (36) D/T Q I/O 18

Wired-AND Capability

X5882

Figure 10: FastCONNECT Switch Matrix

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XC9500 In-System Programmable CPLD Family

I/O Block
The I/O Block (IOB) interfaces between the internal logic and the device user I/O pins. Each IOB includes an input buffer, output driver, output enable selection multiplexer, and user programmable ground control. See Figure 11 for details. The input buffer is compatible with standard 5 V CMOS, 5 V TTL and 3.3 V signal levels. The input buffer uses the internal 5 V voltage supply (VCCINT) to ensure that the input thresholds are constant and do not vary with the VCCIO voltage. The output enable may be generated from one of four options: a product term signal from the macrocell, any of the global OE signals, always 1, or always 0. There are two global output enables for devices with up to 144 macrocells, and four global output enables for devices with 180 or more macrocells. Both polarities of any of the global 3-state control (GTS) pins may be used within the device.

To other Macrocells

VCCINT

I/O Block

To FastCONNECT Switch Matrix

Macrocell

Pull-up Resistor OUT I/O

(Inversion in AND-array) Product Term OE PTOE

UserProgrammable Ground

0 Slew Rate Control

I/O/GTS1 Global OE 1

I/O/GTS2

Global OE 2

I/O/GTS3

Global OE 3

Available in XC95180, XC95216 and XC95288

I/O/GTS3

Global OE 4

X5899

Figure 11: I/O Block and Output Enable Capability

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November 10, 1997 (Version 2.0)

Each output has independent slew rate control. Output edge rates may be slowed down to reduce system noise (with an additional time delay of tSLEW) through programming. See Figure 12. Each IOB provides user programmable ground pin capability. This allows device I/O pins to be congured as additional ground pins. By tying strategically located programmable ground pins to the external ground connection, system noise generated from large numbers of simultaneous switching outputs may be reduced. A control pull-up resistor (typically 10K ohms) is attached to each device I/O pin to prevent them from oating when the device is not in normal user operation. This resistor is active during device programming mode and system power-up. It is also activated for an erased device. The resistor is deactivated during normal operation. The output driver is capable of supplying 24 mA output drive. All output drivers in the device may be congured for either 5 V TTL levels or 3.3 V levels by connecting the device output voltage supply (VCCIO) to a 5 V or 3.3 V
Output Voltage

voltage supply. Figure 13 shows how the XC9500 device can be used in 5 V only and mixed 3.3 V/5 V systems.

Pin-Locking Capability
The capability to lock the user dened pin assignments during design changes depends on the ability of the architecture to adapt to unexpected changes. The XC9500 devices have architectural features that enhance the ability to accept design changes while maintaining the same pinout. The XC9500 architecture provides maximum routing within the FastCONNECT switch matrix, and incorporates a exible Function Block that allows block-wide allocation of available product terms. This provides a high level of condence of maintaining both input and output pin assignments for unexpected design changes. For extensive design changes requiring higher logic capacity than is available in the initially chosen device, the new design may be able to t into a larger pin-compatible device using the same pin assignments. The same board may be used with a higher density device without the expense of board rework.
Output Voltage

Standard Slew-Rated Limited tSLEW 1.5 V Standard

Slew-Rated Limited tSLEW 1.5 V

Time

Time

(a)

(b)

X5900

Figure 12: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs

5 V CMOS 5V 0V 5 V TTL or 3.6 V IN 0V 3.3 V or 3.3 V 0V

5V

5 V CMOS 5V

5V

3.3 V

VCCINT

VCCIO 5 V TTL

0V 5 V TTL or 3.6 V

VCCINT

VCCIO 3.3 V

XC9500 CPLD

~4V OUT 0V 3.3 V

IN 0V or 3.3 V 0V

XC9500 CPLD

3.3 V OUT 0V

GND

GND

(a)

(b)

X5901

Figure 13: XC9500 Devices in (a) 5 V Systems and (b) Mixed 3.3 V/5 V Systems

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XC9500 In-System Programmable CPLD Family

In-System Programming
XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol, as shown in Figure 14. In-system programming offers quick and efcient design iterations and eliminates package handling. The Xilinx development system provides the programming data sequence using a Xilinx download cable, a third-party JTAG development system, JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. All I/Os are 3-stated and pulled high by the IOB resistors during in-system programming. If a particular signal must remain low during this time, then a pulldown resistor may be added to the pin.

The TMS and TCK pins have dedicated pull-up resistors as specied by the IEEE 1149.1 standard. Boundary Scan Description Language (BSDL) les for the XC9500 are included in the development system and are avalable on the Xilinx FTP site.

Design Security
XC9500 devices incorporate advanced data security features which fully protect the programming data against unauthorized reading or inadvertent device erasure/reprogramming. Table 2 shows the four different security settings available. The read security bits can be set by the user to prevent the internal programming pattern from being read or copied. Erasing the entire device is the only way to reset the read security bit. The write security bits provide added protection against accidental device erasure or reprogramming when the JTAG pins are subject to noise, such as during system power-up. Once set, the write-protection may be deactivated when the device needs to be reprogrammed with a valid pattern. Table 2: Data Security Options
Read Security Default Read Allowed
Write Security

External Programming
XC9500 devices can also be programmed by the Xilinx HW130 device programmer as well as third-party programmers. This provides the added exibility of using pre-programmed devices during manufacturing, with an in-system programmable option for future enhancements.

Endurance
All XC9500 CPLDs provide a minimum endurance level of 10,000 in-system program/erase cycles. Each device meets all functional, performance, and data retention specications within this endurance limit.

Set Read Inhibited Program/Erase Allowed Read Inhibited Program/Erase Inhibited

X5905

Default Program/Erase Allowed Read Allowed Set Program/Erase Inhibited

IEEE 1149.1 Boundary-Scan (JTAG)

XC9500 devices fully support IEEE 1149.1 boundary-scan (JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS, USERCODE, INTEST, IDCODE, and HIGHZ instructions are supported in each device. For ISP operations, ve additional instructions are added; the ISPEN, FERASE, FPGM, FVFY, and ISPEX instructions are fully compliant extensions of the 1149.1 instruction set.

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November 10, 1997 (Version 2.0)

V CC

GND

(a)

(b)

X5902

Figure 14: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable

Low Power Mode

All XC9500 devices offer a low-power mode for individual macrocells or across all macrocells. This feature allows the device power to be signicantly reduced. Each individual macrocell may be programmed in lowpower mode by the user. Performance-critical parts of the application can remain in standard power mode, while other parts of the application may be programmed for lowpower operation to reduce the overall power dissipation. Macrocells programmed for low-power mode incur additional delay (tLP) in pin-to-pin combinatorial delay as well as register setup time. Product term clock to output and product term output enable delays are unaffected by the macrocell power-setting.

Timing Model
The uniformity of the XC9500 architecture allows a simplied timing model for the entire device. The basic timing model, shown in Figure 15, is valid for macrocell functions that use the direct product terms only, with standard power setting, and standard slew rate setting. Table 3 shows how each of the key timing parameters is affected by the product term allocator (if needed), low-power setting, and slew-limited setting. The product term allocation time depends on the logic span of the macrocell function, which is dened as one less than the maximum number of allocators in the product term path. If only direct product terms are used, then the logic span is 0. The example in Figure 6 shows that up to 15 product terms are available with a span of 1. In the case of Figure 8, the 18 product term function has a span of 2. Detailed timing information may be derived from the full timing model shown in Figure 16. The values and explanations for each parameter are given in the individual device data sheets.

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XC9500 In-System Programmable CPLD Family

tSU Combinatorial Logic Combinatorial Logic D/T Q

tCO Propagation Delay = tPD (a) tPSU Combinatorial Logic P-Term Clock Path tPCO Setup Time = tPSU Clock to Out Time = tPCO Internal System Cycle Time = tSYSTEM (d) D/T Q Combinatorial Logic Setup Time = tSU (b) Clock to Out Time = tCO

D/T

(c) All resources within FB using local Feedback

Combinatorial Logic

Combinatorial Logic

D/T

Q Combinatorial Logic

Internal Cycle Time = tCNT (e) Setup Time Propagation Delay = tPD + tFBK With Feedback (f)

Figure 15: Basic Timing Model

tF tLF tLOGILP tIN tLOGI tPTCK tGCK tPTSR tGSR tPTTS tGTS Figure 16: Detailed Timing Model S*tPTA tPDI tSLEW

D/T

tOUT

tSUI tCOI tHI

>

tAOI tRAI

tEN

SR

Power-Up Characteristics
The XC9500 devices are well behaved under all operating conditions. During power-up each XC9500 device employs internal circuitry which keeps the device in the quiescent state until the VCCINT supply voltage is at a safe level (approximately 3.8 V). During this time, all device pins and JTAG pins are disabled and all device outputs are disabled with the IOB pull-up resistors (~ 10K ohms) enabled, as shown in Table 4. When the supply voltage reaches a safe 3-18

level, all user registers become initialized (typically within 100 s for 9536 - 95144, 200 s for 95216 and 300 s for 95288), and the device is immediately available for operation, as shown in Figure 17. If the device is in the erased state (before any user pattern is programmed), the device outputs remain disabled with the IOB pull-up resistors enabled. The JTAG pins are enabled to allow the device to be programmed at any time.

November 10, 1997 (Version 2.0)

If the device is programmed, the device inputs and outputs take on their congured states for normal operation. The JTAG pins are enabled to allow device erasure or boundary-scan tests at any time.

FastFLASH Technology
An advanced CMOS Flash process is used to fabricate all XC9500 devices. Specically developed for Xilinx in-system programmable CPLDs, the FastFLASH process provides high performance logic capability, fast programming times, and endurance of 10,000 program/erase cycles.
VCCINT

Development System Support

The XC9500 CPLD family is fully supported by the development systems available from Xilinx and the Xilinx Alliance Program vendors. The designer can create the design using ABEL, schematics, equations, VHDL, or Verilog in a variety of software front-end tools. The development system can be used to implement the design and generate a JEDEC bitmap which can be used to program the XC9500 device. Each development system includes JTAG download software that can be used to program the devices via the standard JTAG interface and a download cable.

3.8 V (Typ)

0V No Power Quiescent State User Operation Quiescent State No Power

X5904

Initialization of User Registers

Figure 17: Device Behavior During Power-up Table 3: Timing Model Parameters Description Propagation Delay Global Clock Setup Time Global Clock-to-output Product Term Clock Setup Time Product Term Clock-to-output Internal System Cycle Period Parameter tPD tSU tCO tPSU tPCO tSYSTEM Product Term Allocator1 + tPTA * S + tPTA * S + tPTA * S + tPTA * S Macrocell Low-Power Setting + tLP + tLP + tLP + tLP Output Slew-Limited Setting + tSLEW + tSLEW + tSLEW

Note: 1. S = the logic span of the function, as dened in the text. Table 4: XC9500 Device Characteristics Device Circuitry IOB Pull-up Resistors Device Outputs Device Inputs and Clocks Function Block JTAG Controller Quiescent State Enabled Disabled Disabled Disabled Disabled Erased Device Operation Enabled Disabled Disabled Disabled Enabled Valid User Operation Disabled As Configured As Configured As Configured Enabled

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XC9500 In-System Programmable CPLD Family

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XC9536 In-System Programmable CPLD

0 3*

November 10, 1997 (Version 2.0)

Product Specification

Features
5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-5, -6, -7, -10 speed grades) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC and 44-pin VQFP packages

Power Management
Power dissipation can be reduced in the XC9536 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC9536 device.

High P
Typical ICC (mA) (50)

erform

ance

(83)

(50)

ower Low P
(30)

Description
The XC9536 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of two 36V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure 2 for the architecture overview.
0 50 Clock Frequency (MHz) 100
X5920

Figure 1: Typical ICC vs. Frequency For XC9536

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XC9536 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18

Function Block 1 Macrocells 1 to 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

X5919

Figure 2: XC9536 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

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November 10, 1997 (Version 2.0)

Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL
Warning:

Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm)

Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260

Units V V V C C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operating Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage

Note 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

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XC9536 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol VOH Parameter Output high voltage for 5 V operation Test Conditions IOH = -4.0 mA VCC = Min Output high voltage for 3.3 V operation IOH = -3.2 mA VCC = Min Output low voltage for 5 V operation IOL = 24 mA VCC = Min Output low voltage for 3.3 V operation IOL = 10 mA VCC = Min Input leakage current VCC = Max VIN = GND or VCC I/O high-Z leakage current VCC = Max VIN = GND or VCC I/O capacitance VIN = GND f = 1.0 MHz Operating Supply Current VI = GND, No load (low power mode, active) f = 1.0 MHz Min 2.4 2.4 0.5 0.4 10.0 10.0 10.0 30 (Typ) Max Units V V V V A A pF mA

VOL

IIL IIH CIN ICC

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15 Units Min Max Min Max Min Max Min Max Min Max 5.0 6.0 7.5 10.0 15.0 ns 4.5 4.5 5.5 6.5 8.0 ns 0.0 0.0 0.0 0.0 0.0 ns 4.5 4.5 5.5 6.5 8.0 ns 100 100 83 67 56 MHz 100 100 83 67 56 MHz 0.5 0.5 1.5 2.5 4.0 ns 4.0 4.0 4.0 4.0 4.0 ns 8.5 8.5 9.5 10.5 12.0 ns 6.0 6.0 7.0 10.0 15.0 ns 6.0 6.0 7.0 10.0 15.0 ns 10.5 10.5 13.0 15.5 18.0 ns 10.5 10.5 13.0 15.5 18.0 ns 4.0 4.0 4.0 4.5 5.5 ns

Note: 1. fCNT is the fastest 16-bit counter frequency available.

fCNT is also the Export Control Maximum ip-op toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

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November 10, 1997 (Version 2.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15 Min Max Min Max Min Max Min Max Min Max 1.5 2.0 4.0 6.0 2.0 0.0 4.5 1.0 9.0 0.5 4.0 0.5 0.5 6.0 5.0 1.0 9.0 4.5 4.5 1.0 3.5 5.0 1.0 9.0 4.5 4.5 1.0 3.5 4.0 0.5 0.5 6.0 7.5 2.0 10.0 6.0 6.0 1.0 4.0 1.5 2.0 4.0 6.0 2.0 0.0 4.5 1.0 9.0 1.5 3.5 2.0 0.5 6.5 10.0 2.5 11.0 8.5 8.5 1.0 4.5 2.5 2.5 4.5 7.0 2.5 0.0 4.0 2.0 10.5 0.5 3.5 3.0 0.5 7.0 15.0 3.0 11.5 11.0 11.0 1.5 5.0 3.5 3.0 6.0 10.0 3.0 0.0 3.5 2.5 12.0 1.0 3.5 4.5 0.5 8.0 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 Units

Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feeback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

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XC9536 In-System Programmable CPLD

XC9536 I/O Pins

Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note: Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PC44 2 3 5 4 6 8 7 9 11 12 13 14 18 19 20 22 24 VQ44 40 41 43 42 44 2 1 3 5 6 7 8 12 13 14 16 18 BScan Notes Order 105 102 99 [1] 96 93 [1] 90 87 [1] 84 81 78 75 72 69 66 63 60 57 54 Function Block 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PC44 1 44 42 43 40 39 38 37 36 35 34 33 29 28 27 26 25 VQ44 39 38 36 37 34 33 32 31 30 29 28 27 23 22 21 20 19 BScan Notes Order 51 48 45 [1] 42 39 [1] 36 [1] 33 30 27 24 21 18 15 12 9 6 3 0

[1] Global control pin

XC9536 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND No Connects PC44 5 6 7 42 40 39 17 15 30 16 21,41 32 23,10,31 VQ44 43 44 1 36 34 33 11 9 24 10 15,35 26 17,4,25

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November 10, 1997 (Version 2.0)

Ordering Information XC9536 -5 PC 44 C

Device Type Speed Temperature Range Number of Pins Package Type
Speed Options -15 -10 -7 -6 -5 15 ns 10 ns 7.5 ns 6 ns 5 ns pin-to-pin delay pin-to-pin delay pin-to-pin delay pin-to-pin delay pin-to-pin delay Packaging Options PC44 44-Pin Plastic Leaded Chip Carrier (PLCC) VQ44 44-Pin Thin Quad Pack (VQFP) Temperature Options C I Commercial Industrial 0C to 70C 40C to 85C

Component Availability
Pins Type Code 15 10 7 6 5 Plastic PLCC PC44 C,I C,I C,I C C1 44 Plastic VQFP VQ44 C,I C,I C,I C C

XC9536

C = Commercial = 0 to +70C, I = Industrial = 40 to 85C Note: 1.Contact factory for availability

November 10, 1997 (Version 2.0)

3-27

XC9536 In-System Programmable CPLD

3-28

November 10, 1997 (Version 2.0)

XC9572 In-System Programmable CPLD

0 3*

October 28, 1997 (Version 2.0)

Product Specification Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz)

Features
7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-7, -10 speed grades) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages

200

erform High P
Typical Icc (ma)

ance

(160)

(125) 100
ower Low P

(100)

(65)

50
Clock Frequency (MHz)

100

Description
The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

Figure 1: Typical ICC vs. Frequency for XC9572

Power Management
Power dissipation can be reduced in the XC9572 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.

October 28, 1997 (Version 2.0)

3-29

XC9572 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18

Function Block 1 Macrocells 1 to 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block 4 Macrocells 1 to 18

X5921

Figure 2: XC9572 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

3-30

October 28, 1997 (Version 2.0)

Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage

Note: 1. Numbers in parenthesis are for industrial temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

October 28, 1997 (Version 2.0)

3-31

XC9572 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol VOH Parameter Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL IIH CIN ICC Input leakage current I/O high-Z leakage current I/O capacitance Operating Supply Current (low power mode, active) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 Max Units V V 2.4 0.5 0.4 10.0 10.0 10.0 65 (Typ) V V A A pF ma

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC9572-7 Min 5.5 0.0 5.5 125 83 1.5 4.0 9.5 7.0 7.0 13.0 13.0 4.0 111 67 2.5 4.0 10.5 10.0 10.0 15.5 15.5 4.5 Max 7.5 XC9572-10 Min 6.5 0.0 6.5 95 56 4.0 4.0 12.0 15.0 15.0 18.0 18.0 5.5 Max 10.0 XC9572-15 Min 8.0 0.0 8.0 Max 15.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

Note: 1. fCNT is the fastst 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum ip-op toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

3-32

October 28, 1997 (Version 2.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC9572-7 Min Max 2.5 2.5 4.5 7.0 2.5 0.0 4.0 2.0 10.5 0.5 3.5 2.0 0.5 6.5 7.5 2.0 10.0 6.0 2.0 1.0 4.0 10.0 2.5 11.0 8.5 2.5 1.0 4.5 3.5 3.0 0.5 7.0 15.0 3.0 11.5 11.0 3.5 1.5 5.0 XC9572-10 Min Max 3.5 3.0 6.0 10.0 3.0 0.0 3.5 2.5 12.0 1.0 3.5 4.5 0.5 8.0 XC9572-15 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 Units

Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feeback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

October 28, 1997 (Version 2.0)

3-33

XC9572 In-System Programmable CPLD

XC9572 I/O Pins

Function Macrocell Block PC 44 PC 84 PQ 100 TQ 100 BScan Notes Order Function Macrocell Block PC 44 PC 84 PQ 100 TQ 100 BScan Notes Order

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

1 2 3 4 5 6 7 8 9 35 36 37 38 39 40 42 43 44

4 1 6 7 2 3 11 5 9 13 10 18 20 12 14 23 15 24 63 69 67 68 70 71 76 72 74 75 77 79 80 81 83 82 84

18 15 20 22 16 17 27 19 24 30 25 35 38 29 31 41 32 42 89 96 93 95 97 98 5 99 1 3 6 8 10 11 13 12 14 94

16 13 18 20 14 15 25 17 22 28 23 33 36 27 29 39 30 40 87 94 91 93 95 96 3 97 99 1 4 6 8 9 11 10 12 92

213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108

[1] [1]

[1]

[2] [1] [1]

[3]

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

11 12 13 14 18 19 20 22 24 25 26 27 28 29 33 34

25 17 31 32 19 34 35 21 26 40 33 41 43 36 37 45 39 46 44 51 52 47 54 55 48 50 57 53 58 61 56 65 62 66

43 34 51 52 37 55 56 39 44 62 54 63 65 57 58 67 60 61 68 66 73 74 69 78 79 70 72 83 76 84 87 80 91 88 92 81

41 32 49 50 35 53 54 37 42 60 52 61 63 55 56 65 58 59 66 64 71 72 67 76 77 68 70 81 74 82 85 78 89 86 90 79

105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

Notes: [1] Global control pin

[2] Global control pin GTS1 for PC84, PQ100, and TQ100 [3] Global control pin GTS1 for PC44

3-34

October 28, 1997 (Version 2.0)

XC9572 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND No Connects PC44 5 6 7 42 40 39 17 15 30 16 21,41 32 10,23,31

PC84 9 10 12 76 77 74 30 28 59 29 38,73,78 22,64 8,16,27,42, 49,60

PQ100 24 25 29 5 6 1 50 47 85 49 7,59,100 28,40,53,90 2,23,33,46,64,71, 77,86 4,9,21,26,36,45,48, 75, 82

TQ100 22 23 27 3 4 99 48 45 83 47 5,57,98 26,38,51,88 100,21,31,44,62,69, 75, 84 2,7,19,24,34,43,46, 73, 80

October 28, 1997 (Version 2.0)

3-35

XC9572 In-System Programmable CPLD

Ordering Information XC9572 -7 PQ 100 C

Device Type Speed Temperature Range Number of Pins Package Type

Speed Options -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay -7 7.5 ns pin-to-pin delay

Packaging Options PC44 PC84 PQ100 TQ100 44-Pin Plastic Leaded Chip Carrier (PLCC) 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 100-Pin Very Thin Quad Flat Pack (TQFP) 0C to 70C 40C to 85C

Temperature Options C I Commercial Industrial

Component Availability
Pins Type Code XC9572 15 10 7 44 Plastic PLCC PC44 C,I C,I C 84 Plastic PLCC PC84 C,I C,I C 100 Plastic PQFP PQ100 C,I C,I C Plastic TQFP TQ100 C,I C,I C

C = Commercial = 0 to +70C

I = Industrial = 40 to 85C

3-36

October 28, 1997 (Version 2.0)

XC95108 In-System Programmable CPLD

0 3*

October 28, 1997 (Version 2.0)

Product Specification

Features
7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-7, -10 speed grades) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP and 160-pin PQFP packages

Power Management
Power dissipation can be reduced in the XC95108 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95108 device.

300

H
Typical ICC (mA)

rform igh Pe

ance

(250)

200 (180)
Low Power

(170)

Description
The XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of six 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

100

50 Clock Frequency (MHz)

100
X5898

Figure 1: Typical ICC vs. Frequency for XC95108

October 28, 1997 (Version 2.0)

3-37

XC95108 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O

FastCONNECT Switch Matrix

18

Function Block 1 Macrocells 1 to 18

36 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block 4 Macrocells 1 to 18

36 18

Function Block 5 Macrocells 1 to 18

36 18

Function Block 6 Macrocells 1 to 18

X5897

Figure 2: XC95108 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

3-38

October 28, 1997 (Version 2.0)

Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

October 28, 1997 (Version 2.0)

3-39

XC95108 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol VOH Parameter Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL IIH CIN ICC Input leakage current I/O high-Z leakage current I/O capacitance Operating Supply Current (low power mode, active) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 Max Units V V 2.4 0.5 0.4 10.0 10.0 10.0 100 (Typ) V V A A pF ma

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95108-7 Min 5.5 0.0 5.5 125 83 1.5 4.0 9.5 7.0 7.0 13.0 13.0 4.0 111 67 2.5 4.0 10.5 10.0 10.0 15.5 15.5 4.5 Max 7.5 XC95108-10 XC95108-15 XC95108-20 Min 6.5 0.0 6.5 95 56 4.0 4.0 12.0 15.0 15.0 18.0 18.0 5.5 Max 10.0 Min 8.0 0.0 8.0 83 50 4.0 6.0 16.0 20.0 20.0 22.0 22.0 5.5 Max 15.0 Min 10.0 0.0 10.0 Max 20.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum ip-op toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

3-40

October 28, 1997 (Version 2.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC95108-7 Min Max 2.5 2.5 4.5 7.0 2.5 0.0 4.0 2.0 10.5 0.5 3.5 2.0 0.5 6.5 7.5 2.0 10.0 6.0 2.0 1.0 4.0 10.0 2.5 11.0 8.5 2.5 1.0 4.5 3.5 3.0 0.5 7.0 15.0 3.0 11.5 11.0 3.5 1.5 5.0 XC95108-10 XC95108-15 XC95108-20 Min Max 3.5 3.0 6.0 10.0 3.0 0.0 3.5 2.5 12.0 1.0 3.5 4.5 0.5 8.0 20.0 3.0 11.5 13.0 5.0 1.5 5.5 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 3.5 6.5 0.5 9.0 Min Max 6.5 3.0 9.5 20.0 6.5 0.0 2.5 3.0 15.5 4.0 Units

Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feeback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

October 28, 1997 (Version 2.0)

3-41

XC95108 In-System Programmable CPLD

XC95108 I/O Pins

Function Function BScan BScan Macrocell PC84 PQ100 TQ100 PQ160 Macrocell PC84 PQ100 TQ100 PQ160 Notes Notes Block Block Order Order

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

1 2 3 4 5 6 7 9 10 11 12 13 71 72 74 75 76 77 79 80 81 82 83 84

15 16 21 17 18 19 20 26 22 24 25 27 29 30 98 99 4 1 3 5 6 9 8 10 11 12 13 14

13 14 19 15 16 17 18 24 20 22 23 25 27 28 96 97 2 99 1 3 4 7 6 8 9 10 11 12

25 21 22 29 23 24 27 26 28 36 30 33 34 35 37 42 44 43 158 154 156 4 159 2 9 6 8 12 11 13 14 15 17 18 19 16

321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216

[1] [1] [1]

[1]

[1] [1]

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

14 15 17 18 19 20 21 23 24 25 26 31 57 58 61 62 63 65 66 67 68 69 70

31 32 36 34 35 37 38 45 39 41 42 43 44 51 83 84 82 87 88 89 91 92 93 95 96 94 97

29 30 34 32 33 35 36 43 37 39 40 41 42 49 81 82 80 85 86 87 89 90 91 93 94 92 95

45 47 49 57 54 56 50 58 59 69 60 62 52 63 64 68 77 74 123 134 135 133 138 139 128 140 142 147 143 144 153 146 148 145 152 155

213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108

Notes: [1] Global control pin

3-42

October 28, 1997 (Version 2.0)

XC95108 I/O Pins (continued)

Function Function BScan BScan Macrocell PC84 PQ100 TQ100 PQ160 Macrocell PC84 PQ100 TQ100 PQ160 Notes Notes Block Block Order Order

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

32 33 34 35 36 37 39 40 41 43 44

52 54 48 55 56 57 58 60 62 63 65 61 66

50 52 46 53 54 55 56 58 60 61 63 59 64

76 79 82 72 86 88 78 90 92 84 95 97 87 98 101 96 102 89

105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

45 46 47 48 50 51 52 53 54 55 56

67 68 75 69 70 72 73 74 76 78 79 81 80

65 66 73 67 68 70 71 72 74 76 77 79 78

91 103 104 116 106 108 105 111 113 107 115 117 112 122 124 129 126 114

51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

XC95108 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND GND GND No connects PC84 9 10 12 76 77 74 30 28 59 29 38,73,78 22,64 8,16,27,42,49,60 PQ100 24 25 29 5 6 1 50 47 85 49 7,59,100 28,40,53,90 2,23,33,46,64,71,77,86 TQ100 PQ160 22 33 23 35 27 42 3 6 4 8 99 159 48 75 45 71 83 136 47 73 5,57,98 10,46,94,157 26,38,51,88 1,41,61,81,121,141 100,21,31,44,62,69,75,84 20,31,40,51,70,80,99 100,110,120,127,137 160 3,5,7,32,38,39,48,53,55,6 5,66,67,83,85,93,109, 118,119,125,130,131, 132,149,150,151

October 28, 1997 (Version 2.0)

3-43

XC95108 In-System Programmable CPLD

Ordering Information XC95108 -7 PQ 160 C

Device Type Temperature Range Number of Pins Speed Package Type

Speed Options - 20 -15 -10 -7 20 ns pin-to-pin delay 15 ns pin-to-pin delay 10 ns pin-to-pin delay 7 ns pin-to-pin delay

Packaging Options PC84 PQ100 TQ100 PQ160 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 100-Pin Very Thin Quad Flat Pack (TQFP) 160-Pin Plastic Quad Flat Pack (PQFP) 0C to 70C 40C to 85C

Temperature Options C I Commercial Industrial

Component Availability
Pins Type Code 20 15 10 7 84 Plastic PLCC PC84 C,I C,I C,I C 100 Plastic PQFP PQ100 C,I C,I C,I C Plastic TQFP TQ100 C,I C,I C,I C 160 Plastic PQFP PQ160 C,I C,I C,I C

XC95108

C = Commercial = 0 to +70C

I = Industrial = 40 to 85C

3-44

October 28, 1997 (Version 2.0)

XC95144 In-System Programmable CPLD

0 3*

November 21, 1997 (Version 3.0)

Preliminary Product Specification Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95144 device.

Features
7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 100-pin PQFP, 100-pin TQFP, and 160-pin PQFP packages

600

(480)

Typical ICC (mA)

400

High

man erfor

ce

(320) (300) 200 (160)

er Pow Low

Description
The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

50 Clock Frequency (MHz)

100
X5898B

Figure 1: Typical Icc vs. Frequency for XC95144

Power Management
Power dissipation can be reduced in the XC95144 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.

November 21, 1997 (Version 3.0)

3-45

XC95144 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O

FastCONNECT Switch Matrix

18

Function Block 1 Macrocells 1 to 18

36 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block 4 Macrocells 1 to 18

36 18

Function Block 8 Macrocells 1 to 18

X5922

Figure 2: XC95144 Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

3-46

November 21, 1997 (Version 3.0)

Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

November 21, 1997 (Version 3.0)

3-47

XC95144 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol VOH Parameter Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL IIH CIN ICC Input leakage current I/O high-Z leakage current I/O capacitance Operating Supply Current (low power mode, active) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 Max Units V V 2.4 0.5 0.4 10.0 10.0 10.0 160 (Typ) V V A A pF ma

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95144-7 Min 5.5 0.0 5.5 125 83 1.5 4.0 9.5 7.0 7.0 13.0 13.0 4.0 111 67 2.5 4.0 10.5 10.0 10.0 15.5 15.5 4.5 Preliminary Max 7.5 XC95144-10 XC95144-15 Min 6.5 0.0 6.5 95 56 4.0 4.0 12.0 15.0 15.0 18.0 18.0 5.5 Max 10.0 Min 8.0 0.0 8.0 Max 15.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum ip-op toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

3-48

November 21, 1997 (Version 3.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC95144-7 Min Max 2.5 2.5 4.5 7.0 2.5 0.0 4.0 2.0 10.5 0.5 3.5 2.0 0.5 6.5 7.5 2.0 10.0 6.0 2.0 1.0 4.0 10.0 2.5 11.0 8.5 2.5 1.0 4.5 Preliminary 3.5 3.0 0.5 7.0 15.0 3.0 11.5 11.0 3.5 1.5 5.0 XC95144-10 XC95144-15 Min Max 3.5 3.0 6.0 10.0 3.0 0.0 3.5 2.5 12.0 1.0 3.5 4.5 0.5 8.0 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 Units

Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feedback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

November 21, 1997 (Version 3.0)

3-49

XC95144 In-System Programmable CPLD

XC95144 I/O Pins

Function Macrocell Block 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 1 15 1 16 1 17 1 18 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 TQ 100 11 12 13 14 15 16 17 18 19 20 22 99 1 2 3 4 6 7 8 9 10 PQ 100 13 14 15 16 17 18 19 20 21 22 24 1 3 4 5 6 8 9 10 11 12 PQ BScan Notes 160 Order 25 429 18 426 19 423 27 420 21 417 22 414 32 411 23 408 24 405 34 402 26 399 28 396 38 393 29 390 30 387 39 384 33 381 [1] 378 158 375 159 372 [1] 3 369 5 366 2 363 [1] 4 360 [1] 7 357 6 354 [1] 8 351 [1] 9 348 11 345 12 342 14 339 13 336 15 333 16 330 17 327 324 Function Macrocell Block 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 3 15 3 16 3 17 3 18 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 TQ 100 23 24 25 27 28 29 30 32 33 34 87 89 90 91 92 93 94 95 96 97 PQ 100 25 26 27 29 30 31 32 34 35 36 89 91 92 93 94 95 96 97 98 99 PQ 160 43 35 45 48 36 37 50 42 44 52 47 49 53 54 56 55 57 132 140 147 149 142 143 150 144 145 151 146 148 153 152 154 155 156 BScan Notes Order 321 318 [1] 315 312 309 306 303 300 [1] 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216

Notes: [1] Global control pin.

Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are xed.

3-50

November 21, 1997 (Version 3.0)

XC95144 I/O Pins (continued)

Function TQ Macrocell Block 100 5 1 5 2 35 5 3 5 4 5 5 36 5 6 37 5 7 5 8 39 5 9 40 5 10 5 11 41 5 12 42 5 13 5 14 43 5 15 46 5 16 5 17 49 5 18 6 1 6 2 74 6 3 6 4 6 5 76 6 6 77 6 7 6 8 78 6 9 79 6 10 6 11 80 6 12 81 6 13 6 14 82 6 15 85 6 16 6 17 86 6 18 PQ 100 37 38 39 41 42 43 44 45 48 51 76 78 79 80 81 82 83 84 87 88 PQ 160 65 58 66 67 59 60 74 62 63 76 64 68 78 69 72 83 77 117 119 123 122 124 125 126 129 128 133 134 130 135 138 131 139 BScan Notes Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Function Macrocell Block 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 7 10 7 11 7 12 7 13 7 14 7 15 7 16 7 17 7 18 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 10 8 11 8 12 8 13 8 14 8 15 8 16 8 17 8 18 TQ 100 50 52 53 54 55 56 58 59 60 61 63 64 65 66 67 68 70 71 72 73 PQ 100 52 54 55 56 57 58 60 61 62 63 65 66 67 68 69 70 72 73 74 75 PQ 160 79 84 85 82 86 87 88 90 89 92 95 91 96 97 93 98 101 105 107 102 103 109 104 106 112 108 111 114 113 115 118 116 BScan Notes Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

November 21, 1997 (Version 3.0)

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XC95144 In-System Programmable CPLD

XC95144 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND TQ100 22 23 27 3 4 1 2 99 48 45 83 47 5, 57, 98 26, 38, 51, 88 100, 21, 31, 44, 62, 69, 75, 84 PQ100 24 25 29 5 6 3 4 1 50 47 85 49 7, 59, 100 28, 40, 53, 90 2, 23, 33, 46, 64, 71, 77, 86 PQ160 33 35 42 6 8 2 4 159 75 71 136 73 10, 46, 94, 157 1, 41, 61, 81, 121, 141 20, 31, 40, 51, 70, 80, 99, 100, 110, 120, 127, 137, 160

No Connects

3-52

November 21, 1997 (Version 3.0)

Ordering Information XC95144 -7 PQ 160 C

Device Type Temperature Range Number of Pins Speed Package Type

Speed Options -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay -7 7 ns pin-to-pin delay

Packaging Options PQ100 100-Pin Plastic Quad Flat Pack (PQFP) TQ100 100-Pin Very Thin Quad Flat Pack (TQFP) PQ160 160-Pin Plastic Quad Flat Pack (PQFP) Temperature Options C I Commercial Industrial 0C to 70C 40C to 85C

Component Availability
Pins Type Code XC95144 15 10 7 100 Plastic PQFP PQ100 C,I C,I C Plastic TQFP TQ100 C,I C,I C 160 Plastic PQFP PQ160 C,I C,I C

C = Commercial = 0 to +70C

I = Industrial = 40 to 85C

November 21, 1997 (Version 3.0)

3-53

XC95144 In-System Programmable CPLD

3-54

November 21, 1997 (Version 3.0)

XC95216 In-System Programmable CPLD

0 3*

October 28, 1997 (Version 2.0)

Product Specification

Features
10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 216 macrocells with 4800 usable gates Up to 166 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-10 speed grade) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 160-pin PQFP, 352-pin BGA, and 208-pin HQFP packages

Power Management
Power dissipation can be reduced in the XC95216 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95216 device.

600

High P
Typical ICC (mA)

erform

ance

(500)

400 (360)
ower Low P

(340)

Description
The XC95216 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of twelve 36V18 Function Blocks, providing 4,800 usable gates with propagation delays of 10 ns. See Figure 2 for the architecture overview.

200

50 Clock Frequency (MHz)

100
X5918

Figure 1: Typical ICC vs. Frequency For XC95216

October 28, 1997 (Version 2.0)

3-55

XC95216 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O

FastCONNECT Switch Matrix

18

Function Block 1 Macrocells 1 to 18

36 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block 4 Macrocells 1 to 18

36 18

Function Block 12 Macrocells 1 to 18

X5917

Figure 2: XC95216 Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

3-56

October 28, 1997 (Version 2.0)

Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operating Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

October 28, 1997 (Version 2.0)

3-57

XC95216 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol VOH Parameter Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL IIH CIN ICC Input leakage current I/O high-Z leakage current I/O capacitance Operating Supply Current (low power mode, active) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 Max Units V V 2.4 0.5 0.4 10.0 10.0 10.0 200 (typ) V V A A pF ma

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95216-10 XC95216-15 XC95216-20 Min 6.5 0.0 6.5 111 67 2.5 4.0 10.5 10.0 10.0 15.5 15.5 4.5 95 56 4.0 4.0 12.0 15.0 15.0 18.0 18.0 5.5 Max 10.0 Min 8.0 0.0 8.0 83 50 4.0 6.0 16.0 20.0 20.0 22.0 22.0 5.5 Max 15.0 Min 10.0 0.0 10.0 Max 20.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum ip-op toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

3-58

October 28, 1997 (Version 2.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC95216-10 XC95216-15 XC95216-20 Min Max 3.5 3.0 6.0 10.0 3.0 0.0 3.5 2.5 12.0 1.0 3.5 3.0 0.5 7.0 10.0 2.5 11.0 8.5 2.5 1.0 4.5 15.0 3.0 11.5 11.0 3.5 1.5 5.0 3.5 4.5 0.5 8.0 20.0 3.0 11.5 13.0 5.0 1.5 5.5 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 3.5 6.5 0.5 9.0 Min Max 6.5 3.0 9.5 20.0 6.5 0.0 2.5 3.0 15.5 4.0 Units

Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feeback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

October 28, 1997 (Version 2.0)

3-59

XC95216 In-System Programmable CPLD

XC95216 I/O Pins

Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

18 19 21 22 23 24 25 26 27 28 29 30 6 7 8 9 11 12 13 14 15 16 17

22 23 28 25 30 31 32 12 33 34 35 36 37 38 7 8 29 9 10 15 16 17 18 19 20 14 21

M25 M26 N26 N25 P23 P24 R26 G26 R24 T26 T25 T23 V26 U24 E25 G24 P25 F26 H23 K23 K24 J25 L24 K25 L26 H25 M24

645 642 639 636 633 630 627 624 621 618 615 612 609 606 603 600 597 594 591 588 585 582 579 576 573 570 567 564 561 558 555 552 549 546 543 540

[1]

[1]

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

32 33 34 35 36 37 38 39 42 43 44 152 153 154 155 156 158 159 2 3 4 5

43 44 39 45 46 47 49 67 50 51 55 56 80 57 198 199 196 200 201 202 205 206 3 4 5 203 6

AA26 Y24 U23 AB25 AA24 Y23 AA23 AD18 AB24 AD25 AD23 AF24 AE12 AE23 D18 A21 B19 B20 C20 B22 B24 C23 E23 C26 E24 D20 F24

537 534 531 528 525 522 519 516 513 510 507 504 501 498 495 492 489 486 483 480 477 474 471 468 465 462 459 456 453 450 447 444 441 438 435 432

[1]

[1]

[1]

[1] [1]

[1]

3-60

October 28, 1997 (Version 2.0)

XC95216 I/O Pins (continued)

Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

45 47 48 49 50 52 53 54 55 56 57 140 142 143 144 145 146 147 148 149 150 151

58 60 41 61 63 64 70 109 71 72 73 74 40 75 180 182 208 185 186 187 188 183 191 192 193 194 169 197

AE22 AE21 W25 AF21 AD19 AE20 AF18 AD1 AE17 AE16 AF16 AE14 Y26 AF14 A12 A13 D22 C14 A15 B15 C15 B14 A16 C16 C17 B18 D9 C19

429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324

7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

58 59 60 62 63 64 65 66 67 68 69 126 128 129 130 131 132 133 134 135 138 139

76 77 54 78 82 83 84 91 85 86 87 88 48 89 162 164 143 166 167 170 171 195 173 174 175 178 189 179

AE13 AC13 AE24 AD13 AD12 AC12 AF11 AD8 AE11 AE9 AD9 AC10 AC26 AF7 B5 B6 J1 D8 B7 C10 B9 A20 A9 D11 B11 C12 D15 B12

321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216

October 28, 1997 (Version 2.0)

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XC95216 In-System Programmable CPLD

XC95216 I/O Pins (continued)

Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order

9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

72 74 76 77 78 79 82 83 84 85 86 113 114 115 116 117 118 119 122 123 124 125

95 97 101 99 100 102 103 90 110 111 112 113 62 114 147 148 144 149 150 152 154 168 155 158 159 160 165 161

AD7 AE5 AD4 AC7 AE3 AC5 AD3 AE8 AA4 AB2 AC1 AA2 AC19 AA1 H3 J4 K3 G2 G3 E2 D2 A7 F4 B3 A3 D6 A6 C6

213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108

11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

87 88 89 90 91 92 93 95 96 97 98 101 102 103 104 105 106 107 108 109 111 112

115 116 119 117 118 121 122 107 123 125 126 127 120 128 131 133 106 134 135 136 137 151 138 139 140 145 142 146

Y1 V4 U4 V3 W2 V2 U2 AC3 T2 R4 R3 R2 U3 R1 P1 N2 AD2 N4 N3 M1 M3 F2 M4 L1 L2 G1 L3 H2

105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

3-62

October 28, 1997 (Version 2.0)

XC95216 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V PQ160 33 35 42 6 8 2 4 159 75 71 136 73 10,46,94,157 1,41,61,81,121,141 HQ208 BG352 44 Y24 46 AA24 55 AD23 7 E25 9 F26 3 E23 5 E24 206 C23 98 AD6 94 AF6 176 D12 96 AE6 11, 59, 124, 153, 204 H24, AF23, T1, G4, C22 1, 26, 53, 65, 79, 92, 105, 132, A10, A17, B2, B25, D7, D13, 157, 172, 181, 184 D19, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC8, AC14, AC20, AE25, AF10, AF17 2, 13, 24, 27, 42, 52, 66, 68, 69, A1, A2, A5, A8, A14, A19, A22, 81, 93, 104, 108, 129, 130, 141, A25, A26, B1, B26, C7, E1, E26, 156, 163, 177, 190, 207 H1, H26, N1, P3, P26, V23, W1, W26, AB1, AB4, AB26, AC9, AC17, AE1, AE26, AF1, AF2, AF5, AF8, AF13, AF19, AF20, AF22, AF25, AF26 A4, A11, A18, A23, A24, B4, B8, B10, B13, B16, B17, B21, B23, C1, C2, C3, C4, C5, C8, C9, C11, C13, C18, C21, C24, C25, D1, D3, D4, D5, D10, D14, D16, D17, D21, D23, D24, D25, D26, E3, E4, F1, F3, F23, F25, G25, J2, J3, J23, J24, J26, K2, K4, L4, L23, L25, M2, M23, N24, P2, R23, R25, T3, T4, T24, U25, V1, V24, V25, W3, W4, W24, Y2, Y3, Y25, AA3, AA25, AB3, AB23, AC2, AC4, AC6, AC11, AC15, AC16, AC18, AC21, AC22, AC23, AC24, AC25, AD5, AD10, AD11, AD14, AD15, AD16, AD17, AD20, AD21, AD22, AD24, AD26, AE2, AE4, AE7, AE10, AE15, AE18, AE19, AF3, AF4, AF9, AF12, AF15

GND

20, 31, 40, 51, 70, 80, 99, 100, 110, 120, 127, 137, 160

No Connects

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XC95216 In-System Programmable CPLD

Ordering Information XC95216 -10 HQ 208 C

Device Type Temperature Range Number of Pins Speed Package Type

Speed Options - 20 20 ns pin-to-pin delay -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay

Packaging Options PQ160 160-Pin Plastic Quad Flat Pack (PQFP) HQ208 208-Pin Heat Sink Quad Flat Pack (HQFP) BG352 352-Pin Ball Grid Array (BGA) Temperature Options C I Commercial Industrial 0C to 70C 40C to 85C

Component Availability
Pins Type Code XC95216 20 15 10 160 Plastic PQFP PQ160 C,I C C 160 Power QFP HQ208 C,I C C 352 Plastic BGA BG352 C,I C,I C

C = Commercial = 0 to +70C

I = Industrial = 40 to 85C

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XC95288 In-System Programmable CPLD

0 3*

November 12, 1997 (Version 2.0)

Preliminary Product Specification MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz)
900

Features
15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz 288 macrocells with 6,400 usable gates Up to 192 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant ( -10 speed grade) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 352-pin BGA and 208-pin HQFP packages

Typical ICC (mA)

600 (500)

ance erform High P

(700)

(500)
o Low P w er

300

50 Clock Frequency (MHz)

100
X7131

Figure 1: Typical ICC vs. Frequency For XC95288

Description
The XC95288 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of sixteen 36V18 Function Blocks, providing 6,400 usable gates with propagation delays of 10 ns. See Figure 2 for the architecture overview.

Power Management
Power dissipation can be reduced in the XC95288 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) =

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XC95288 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18

Function Block 1 Macrocells 1 to 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block 4 Macrocells 1 to 18

36 18

Function Block 16 Macrocells 1 to 18

X5924

Figure 2: XC95288 Architecture

Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

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Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

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XC95288 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol VOH Parameter Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL IIH CIN ICC Input leakage current I/O high-Z leakage current I/O capacitance Operating Supply Current (low power mode, active) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 Max Units V V 2.4 0.5 0.4 10.0 10.0 10.0 300 (Typ) V V A A pF ma

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95288-15 XC95288-20 Min 8.0 0.0 8.0 95 56 4.0 4.0 12.0 15.0 15.0 18.0 18.0 5.5 83 50 4.0 6.0 16.0 20.0 20.0 22.0 22.0 5.5 Max 15.0 Min 10.0 0.0 10.0 Max 20.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum ip-op toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

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VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC95288-15 XC95288-20 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 3.5 4.5 0.5 8.0 15.0 3.0 11.5 11.0 3.5 1.5 5.0 20.0 3.0 11.5 13.0 5.0 1.5 5.5 3.5 6.5 0.5 9.0 Min Max 6.5 3.0 9.5 20.0 6.5 0.0 2.5 3.0 15.5 4.0 Units

Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feeback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

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XC95288 In-System Programmable CPLD

XC95288 I/O Pins

Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 32 33 34 35 36 37 15 16 17 18 19 20 21 22 23 25 N26 P25 P23 P24 R26 R25 R24 R23 T26 T25 T23 V26 K23 K24 J25 L24 K25 L25 L26 M23 M24 M25 M26 N25 BScan Notes Order 861 858 855 852 849 846 843 840 837 834 831 828 825 822 819 816 813 810 807 804 801 798 795 792 789 786 783 780 777 774 771 768 765 762 759 756 Function Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 38 39 40 41 43 44 45 46 47 48 3 4 5 6 7 8 9 10 12 14 U24 U23 Y26 W25 AA26 Y25 Y24 AA25 AB25 AA24 Y23 AC26 E23 C26 E24 F24 E25 D26 G24 F25 F26 H23 G26 H25 BScan Notes Order 753 750 747 744 741 738 735 732 729 726 [1] 723 720 717 714 [1] 711 708 705 702 699 696 [1] 693 690 687 [1] 684 681 678 [1] 675 672 669 666 [1] 663 660 657 654 651 648

Notes: [1] Global control pin

Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are xed.

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XC95288 I/O Pins (continued)

Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Note: Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 49 50 51 54 55 56 57 58 60 61 197 198 199 200 201 202 203 205 206 208 AA23 AB24 AD25 AE24 AD23 AC22 AF24 AD22 AE23 AE22 AE21 AF21 C19 D18 A21 B20 C20 B21 B22 C21 D20 B24 C23 D22 BScan Notes Order 645 642 639 636 633 630 627 624 [1] 621 618 615 612 609 606 603 600 597 594 591 588 585 582 579 576 573 570 567 564 561 558 555 552 549 [1] 546 543 540 Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 62 63 64 66 67 69 70 71 72 73 186 187 188 189 191 192 193 194 195 196 AC19 AD19 AE20 AC18 AD18 AE19 AD17 AE18 AF18 AE17 AE16 AF16 A15 B15 C15 D15 A16 B16 C16 B17 C17 B18 A20 B19 BScan Notes Order 537 534 531 528 525 522 519 516 513 510 507 504 501 498 495 492 489 486 483 480 477 474 471 468 465 462 459 456 453 450 447 444 441 438 435 432

[1] Global control pin

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XC95288 In-System Programmable CPLD

XC95288 I/O Pins (continued)

Function Block 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 74 75 76 77 78 80 82 83 84 85 86 170 171 173 174 175 178 179 180 182 183 185 AE14 AF14 AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 AE11 AE9 C10 B9 A9 D11 B11 A11 C12 B12 A12 A13 B14 C14 BScan Notes Order 429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324 Function Block 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 87 88 89 90 91 95 97 99 100 101 102 158 159 160 161 162 164 165 166 167 168 169 BScan Notes Order 321 AD9 318 AC10 315 312 AF7 309 AE8 306 303 AD8 300 AE7 297 AD7 294 AE5 291 AC7 288 285 AE3 282 AD4 279 276 AC5 273 270 267 B3 264 A3 261 258 D6 255 C6 252 249 B5 246 A4 243 B6 240 A6 237 D8 234 231 B7 228 A7 225 222 D9 219 216

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XC95288 I/O Pins (continued)

Function Block 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 103 106 107 109 110 111 112 113 114 115 116 144 145 146 147 148 149 150 151 152 154 155 AD3 AD2 AC3 AD1 AA4 AA3 AB2 AC1 AA2 AA1 Y1 V4 K3 G1 H2 H3 J4 F1 G2 G3 F2 E2 D2 F4 BScan Notes Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Function Block 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 117 118 119 120 121 122 123 125 126 127 128 131 133 134 135 136 137 138 139 140 142 143 V3 W2 U4 U3 V2 V1 U2 T2 R4 R3 R2 R1 P1 N2 N4 N3 M1 M2 M3 M4 L1 L2 L3 J1 BScan Notes Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

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XC95288 In-System Programmable CPLD

XC95288 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V BG352 Y24 AA24 AD23 E25 F26 E23 E24 C23 AD6 AF6 D12 AE6 J23, V24, AF23, AC15, AF15, AD11, AD5, Y3, T1, J3, G4, D5, D10, B13, D17, C22, H24 1, 26, 53, 65, 79, 92, 105, 132, A10, A17, B2, B25, D7, D13, 157, 172, 181, 184 D19, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC8, AC14, AC20, AE25, AF10, AF17 2, 13, 24, 27, 42, 52, 68, 81, 93, A1, A2, A5, A8, A14, A19, A22, 104,108, 129, 130, 141, 156, A25, A26, B1, B26, C7, C9, C13, 163, 177, 190, 207 C18, D24, E1, E26, H1, H26, K4, N1, N24, P3, P26, V23, W1, W4, W26, AB1, AB4, AB26, AC9, AD10, AD14, AD15, AD20, AE1, AE26, AF1, AF2, AF5, AF8, AF13, AF19, AF22, AF25, AF26 A18, A23, A24, B4, B8, B10, B23, C1, C2, C3, C4, C5, C8, C11, C24, C25, D1, D3, D4, D14, D16, D21, D23, D25, E3, E4, F3, F23, G25, J2, J24, J26, K2, L4, L23, P2, T3, T4, T24, U25, V25, W3, W24, Y2, AB3, AB23, AC2, AC4, AC6, AC11, AC16, AC17, AC21, AC23, AC24, AC25, AD16, AD21, AD24, AD26, AE2, AE4, AE10, AE15, AF3, AF4, AF9, AF20 HQ208 44 46 55 7 9 3 5 206 98 94 176 96 11, 59, 124, 153, 204

VCCIO 3.3 V/5 V

GND

No Connects

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November 12, 1997 (Version 2.0)

Ordering Information XC95288 -15 HQ 208 C

Device Type Speed Temperature Range Number of Pins Package Type

Speed Options - 20 20 ns pin-to-pin delay -15 15 ns pin-to-pin delay

Packaging Options HQ208 208-Pin Heat Sink Quad Flat Pack (HQFP) BG352 352-Pin Plastic Ball Grid Array (BGA) Temperature Options C I Commercial Industrial 0C to 70C 40C to 85C

Component Availability
Pins Type Code XC95288 20 15 208 Plastic HQFP HQ C,I C 352 Plastic BGA BG C,I C
I = Industrial = 40 to 85C

C = Commercial = 0 to +70C

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XC95288 In-System Programmable CPLD

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FPGA Products

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

FPGA Products Table of Contents

FPGA Products
XC4000E and XC4000X Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 XC4000E and XC4000X Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . 4-5 XC4000XV Family Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-155 XC4000XLT Family Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-175 Spartan and Spartan-XL Families Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187 Spartan and Spartan-XL Families Field Programmable Gate Arrays . . . . . . . . . . . . . . . 4-189 XC5200 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-243 XC5200 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-247 XC3000 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-319 XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L). . . . . . . . . . 4-321

XC4000E and XC4000X Series Table of Contents

1 4*

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E and XC4000X Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Voltage Versions Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional XC4000X Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Taking Advantage of Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E and XC4000X Series Compared to the XC4000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Improvements in XC4000E and XC4000X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Improvements in XC4000X Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latches (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Set/Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using FPGA Flip-Flops and Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Function Generators as RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Blocks (IOBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other IOB Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffer Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wide Edge Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnect Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLB Routing Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Switch Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-Length Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Lines (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Interconnect (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal I/O Routing (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers (XC4000E only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-5 4-5 4-5 4-6 4-6 4-7 4-7 4-8 4-9 4-9 4-9 4-9 4-10 4-10 4-10 4-10 4-11 4-11 4-11 4-11 4-11 4-11 4-18 4-21 4-21 4-24 4-26 4-27 4-27 4-27 4-28 4-28 4-29 4-29 4-29 4-30 4-30 4-32 4-32 4-32 4-33 4-33 4-33 4-36 4-36 4-38 4-40

4-1

XC4000E and XC4000X Series Table of Contents

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Including Boundary Scan in a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avoiding Inadvertent Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Address lines in XC4000 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting CCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Stream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Redundancy Check (CRC) for Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delaying Configuration After Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Goes High to Signal End of Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of User I/O After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of Global Set/Reset After DONE Goes High. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Complete After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Through the Boundary Scan Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Violating the Maximum High and Low Time Specification for the Readback Clock . . . . . . . . . . Readback with the XChecker Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E/EX/XL Program Readback Switching Characteristic Guidelines . . . . . . . . . . . . . . . . Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Parallel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Address lines in XC4000 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes (XC4000E/EX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes (XC4000XL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave and Peripheral Modes(All) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-40 4-43 4-43 4-45 4-45 4-45 4-46 4-46 4-46 4-47 4-47 4-47 4-47 4-47 4-49 4-49 4-50 4-51 4-51 4-52 4-52 4-52 4-55 4-55 4-55 4-55 4-55 4-56 4-57 4-57 4-57 4-57 4-57 4-57 4-58 4-61 4-61 4-62 4-63 4-63 4-65 4-67 4-67 4-67 4-69 4-69 4-69 4-69 4-70 4-70 4-70 4-70 4-70 4-71 4-72 4-73

4-2

XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . . . . . . . . XC4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . XC4000XL Pin-to-Pin Output Parameter Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitive Load Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL Pin-to-Pin Input Parameter Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL Global Low Skew Clock, Set-Up and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-up and Hold for IFF and FCL . . . . . XC4000XL BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-up and Hold for IFF and FCL . . . . . XC4000XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . XC4000EX Longline and Wide Decoder Timing Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Wide Decoder Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . . . . . . . . XC4000EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . XC4000EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines . XC4000EX CLB RAM Asynchronous (Level-Sensitive) Timing Characteristics . . . . . . . . . . . . . XC4000EX Pin-to-Pin Output Parameter Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Output MUX, Clock to Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Output Level and Slew Rate Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Pin-to-Pin Input Parameter Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Global Early Clock, Set-Up and Hold for IFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Global Early Clock, Set-Up and Hold for FCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Input Threshold Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX IOB Input Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX IOB Input Switching Characteristic Guidelines (Continued) . . . . . . . . . . . . . . . . . . . XC4000EX IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Horizontal Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . XC4000E Wide Decoder Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . XC4000E CLB Level-Sensitive RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) . . . . . . . . . . . . . . . . XC4000E IOB Input Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4003E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4005E/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4006E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4008E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4010E/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-76 4-76 4-77 4-78 4-79 4-79 4-80 4-81 IOB Input 4-82 4-83 4-84 4-84 4-84 4-84 4-85 4-86 4-86 4-87 4-89 4-89 4-90 4-91 4-92 4-92 4-92 4-93 4-93 4-93 4-93 4-94 4-95 4-96 4-97 4-97 4-97 4-97 4-98 4-98 4-99 4-100 4-101 4-104 4-104 4-105 4-106 4-107 4-108 4-110 4-112 4-113 4-113 4-114 4-115 4-117 4-118

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XC4000E and XC4000X Series Table of Contents

Pin Locations for XC4013E/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4020E/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4025E, XC4028EX/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4036EX/XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4044XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4052XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4062XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4085XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Per Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-120 4-123 4-125 4-128 4-131 4-135 4-139 4-143 4-151 4-153 4-154

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XC4000E and XC4000X Series Field Programmable Gate Arrays

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Product Specification

XC4000E and XC4000X Series Features

Note: XC4000 Series devices described in this data sheet include the XC4000E family and XC4000X Series. XC4000X Series devices described in this data sheet include the XC4000EX and XC4000XL families. Separate data sheets are available for two other Families in the XC4000X series, the XC4000XLT and XC4000XV. This information does not apply to the older Xilinx families: XC4000, XC4000A, XC4000D, XC4000H, or XC4000L. For information on these devices, see the Xilinx WEBLINX at http://www.xilinx.com. System featured Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Fully PCI compliant (speed grades -2 and faster) - Abundant ip-ops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks System Performance beyond 80 MHz Flexible Array Architecture Low Power Segmented Routing Architecture Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12-mA sink current per XC4000E output Congured by Loading Binary File - Unlimited reprogrammability Readback Capability - Program verication - Internal node observability Backward Compatible with XC4000 Devices Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization

Low-Voltage Versions Available

Low-Voltage Devices Function at 3.0 - 3.6 Volts XC4000XL: High Performance Low-Voltage Versions of XC4000EX devices

Additional XC4000X Series Features

Highest Performance 3.3 V XC4000XL Highest Capacity Over 180,000 Usable Gates 5V tolerant I/Os on XC4000XL 0.35 SRAM process for XC4000XL Additional Routing Over XC4000E - almost twice the routing capacity for high-density designs Buffered Interconnect for Maximum Speed New Latch Capability in Congurable Logic Blocks Improved VersaRingTM I/O Interconnect for Better Fixed Pinout Flexibility 12-mA Sink Current Per XC4000X Output Flexible New High-Speed Clock Network - 8 additional Early Buffers for shorter clock delays - Virtually unlimited number of clock signals Optional Multiplexer or 2-input Function Generator on Device Outputs 4 Additional Address Bits in Master Parallel Conguration Mode XC4000XLT devices, optimized for PCI applications, are available. The XC4000XV Family offers the highest density with 0.25 micron 2.5 volt technology.

Introduction
XC4000 Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benets of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs. The XC4000E and XC4000X Series currently have 20 members, as shown in Table 2.

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Note: All functionality in low-voltage families is the same as in the corresponding 5-Volt family, except where numerical references are made to timing or power. Table 2: XC4000E and XC4000X Series Field Programmable Gate Arrays Logic Cells 152 238 466 608 770 950 1368 1862 2432 2432 3078 3800 4598 5472 7448 Max Logic Max. RAM Gates Bits (No RAM) (No Logic) 1,600 2,048 3,000 3,200 5,000 6,272 6,000 8,192 8,000 10,368 10,000 12,800 13,000 18,432 20,000 25,088 25,000 32,768 28,000 32,768 36,000 41,472 44,000 51,200 52,000 61,952 62,000 73,728 85,000 100,352 Typical Gate Range (Logic and RAM)* 1,000 - 3,000 2,000 - 5,000 3,000 - 9,000 4,000 - 12,000 6,000 - 15,000 7,000 - 20,000 10,000 - 30,000 13,000 - 40,000 15,000 - 45,000 18,000 - 50,000 22,000 - 65,000 27,000 - 80,000 33,000 - 100,000 40,000 - 130,000 55,000 - 180,000 CLB Matrix 8x8 10 x 10 14 x 14 16 x 16 18 x 18 20 x 20 24 x 24 28 x 28 32 x 32 32 x 32 36 x 36 40 x 40 44 x 44 48 x 48 56 x 56 Total CLBs 64 100 196 256 324 400 576 784 1,024 1,024 1,296 1,600 1,936 2,304 3,136 Number of Max. Flip-Flops User I/O 256 64 360 80 616 112 768 128 936 144 1,120 160 1,536 192 2,016 224 2,560 256 2,560 256 3,168 288 3,840 320 4,576 352 5,376 384 7,168 448

Device XC4002XL XC4003E XC4005E/XL XC4006E XC4008E XC4010E/XL XC4013E/XL XC4020E/XL XC4025E XC4028EX/XL XC4036EX/XL XC4044XL XC4052XL XC4062XL XC4085XL

* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

Description
XC4000 Series devices are implemented with a regular, exible, programmable architecture of Congurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs). They have generous routing resources to accommodate the most complex interconnect patterns. The devices are customized by loading conguration data into internal memory cells. The FPGA can either actively read its conguration data from an external serial or byteparallel PROM (master modes), or the conguration data can be written into the FPGA from an external device (slave and peripheral modes). XC4000 Series FPGAs are supported by powerful and sophisticated software, covering every aspect of design from schematic or behavioral entry, oorplanning, simulation, automatic block placement and routing of interconnects, to the creation, downloading, and readback of the conguration bit stream. Because Xilinx FPGAs can be reprogrammed an unlimited number of times, they can be used in innovative designs where hardware is changed dynamically, or where hardware must be adapted to different user applications.

FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 5,000 systems per month. For lowest high-volume unit cost, a design can rst be implemented in the XC4000E or XC4000X, then migrated to one of Xilinx compatible HardWire mask-programmed devices.

Taking Advantage of Reconguration

FPGA devices can be recongured to change logic function while resident in the system. This capability gives the system designer a new degree of freedom not available with any other type of logic. Hardware can be changed as easily as software. Design updates or modications are easy, and can be made to products already in the eld. An FPGA can even be recongured dynamically to perform different functions at different times. Recongurable logic can be used to implement system self-diagnostics, create systems capable of being recongured for different environments or operations, or implement multi-purpose hardware for a given application. As an added benet, using recongurable FPGA devices simplies hardware design and debugging and shortens product time-to-market.

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XC4000E and XC4000X Series Compared to the XC4000

For readers already familiar with the XC4000 family of Xilinx Field Programmable Gate Arrays, the major new features in the XC4000 Series devices are listed in this section. The biggest advantages of XC4000E and XC4000X devices are signicantly increased system speed, greater capacity, and new architectural features, particularly Select-RAM memory. The XC4000X devices also offer many new routing features, including special high-speed clock buffers that can be used to capture input data with minimal delay. Any XC4000E device is pinout- and bitstream-compatible with the corresponding XC4000 device. An existing XC4000 bitstream can be used to program an XC4000E device. However, since the XC4000E includes many new features, an XC4000E bitstream cannot be loaded into an XC4000 device. XC4000X Series devices are not bitstream-compatible with equivalent array size devices in the XC4000 or XC4000E families. However, equivalent array size devices, such as the XC4025, XC4025E, XC4028EX, and XC4028XL, are pinout-compatible.

much as 50% from XC4000 values. See Fast Carry Logic on page 4-18 for more information. Select-RAM Memory: Edge-Triggered, Synchronous RAM Modes The RAM in any CLB can be congured for synchronous, edge-triggered, write operation. The read operation is not affected by this change to an edge-triggered write. Dual-Port RAM A separate option converts the 16x2 RAM in any CLB into a 16x1 dual-port RAM with simultaneous Read/Write. The function generators in each CLB can be congured as either level-sensitive (asynchronous) single-port RAM, edge-triggered (synchronous) single-port RAM, edge-triggered (synchronous) dual-port RAM, or as combinatorial logic. Congurable RAM Content The RAM content can now be loaded at conguration time, so that the RAM starts up with user-dened data. H Function Generator In current XC4000 Series devices, the H function generator is more versatile than in the original XC4000. Its inputs can come not only from the F and G function generators but also from up to three of the four control input lines. The H function generator can thus be totally or partially independent of the other two function generators, increasing the maximum capacity of the device. IOB Clock Enable The two ip-ops in each IOB have a common clock enable input, which through conguration can be activated individually for the input or output ip-op or both. This clock enable operates exactly like the EC pin on the XC4000 CLB. This new feature makes the IOBs more versatile, and avoids the need for clock gating. Output Drivers The output pull-up structure defaults to a TTL-like totempole. This driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below Vcc, just like the XC4000 family outputs. Alternatively, XC4000 Series devices can be globally congured with CMOS outputs, with p-channel pull-up transistors pulling to Vcc. Also, the congurable pull-up resistor in the XC4000 Series is a pchannel transistor that pulls to Vcc, whereas in the original XC4000 family it is an n-channel transistor that pulls to a voltage one transistor threshold below Vcc.

Improvements in XC4000E and XC4000X

Increased System Speed XC4000E and XC4000X devices can run at synchronous system clock rates of up to 80 MHz, and internal performance can exceed 150 MHz. This increase in performance over the previous families stems from improvements in both device processing and system architecture. XC4000 Series devices use a sub-micron multi-layer metal process. In addition, many architectural improvements have been made, as described below. The XC4000XL family is a high performance 3.3V family based on 0.35 SRAM technology and supports system speeds to 80 MHz. PCI Compliance XC4000 Series -2 and faster speed grades are fully PCI compliant. XC4000E and XC4000X devices can be used to implement a one-chip PCI solution. Carry Logic The speed of the carry logic chain has increased dramatically. Some parameters, such as the delay on the carry chain through a single CLB (TBYP), have improved by as

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Input Thresholds The input thresholds of 5V devices can be globally congured for either TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like XC2000 and XC3000 inputs. The two global adjustments of input threshold and output level are independent of each other. The XC4000XL family has an input threshold of 1.6V, compatible with both 3.3V CMOS and TTL levels. Global Signal Access to Logic There is additional access from global clocks to the F and G function generator inputs. Conguration Pin Pull-Up Resistors During conguration, the three mode pins, M0, M1, and M2, have weak pull-up resistors. For the most popular conguration mode, Slave Serial, the mode pins can thus be left unconnected. The three mode inputs can be individually congured with or without weak pull-up or pull-down resistors after conguration. The PROGRAM input pin has a permanent weak pull-up. Soft Start-up Like the XC3000A, XC4000 Series devices have Soft Start-up. When the conguration process is nished and the device starts up, the rst activation of the outputs is automatically slew-rate limited. This feature avoids potential ground bounce when all outputs are turned on simultaneously. Immediately after start-up, the slew rate of the individual outputs is, as in the XC4000 family, determined by the individual conguration option. XC4000 and XC4000A Compatibility Existing XC4000 bitstreams can be used to congure an XC4000E device. XC4000A bitstreams must be recompiled for use with the XC4000E due to improved routing resources, although the devices are pin-for-pin compatible.

Additional Improvements in XC4000X Only

Increased Routing New interconnect in the XC4000X includes twenty-two additional vertical lines in each column of CLBs and twelve new horizontal lines in each row of CLBs. The twelve Quad Lines in each CLB row and column include optional repowering buffers for maximum speed. Additional highperformance routing near the IOBs enhances pin exibility. Faster Input and Output A fast, dedicated early clock sourced by global clock buffers is available for the IOBs. To ensure synchronization with the regular global clocks, a Fast Capture latch driven by the early clock is available. The input data can be initially loaded into the Fast Capture latch with the early clock, then transferred to the input ip-op or latch with the low-skew global clock. A programmable delay on the input can be used to avoid hold-time requirements. See IOB Input Signals on page 4-21 for more information. Latch Capability in CLBs Storage elements in the XC4000X CLB can be congured as either ip-ops or latches. This capability makes the FPGA highly synthesis-compatible. IOB Output MUX From Output Clock A multiplexer in the IOB allows the output clock to select either the output data or the IOB clock enable as the output to the pad. Thus, two different data signals can share a single output pad, effectively doubling the number of device outputs without requiring a larger, more expensive package. This multiplexer can also be congured as an ANDgate to implement a very fast pin-to-pin path. See IOB Output Signals on page 4-24 for more information. Additional Address Bits Larger devices require more bits of conguration data. A daisy chain of several large XC4000X devices may require a PROM that cannot be addressed by the eighteen address bits supported in the XC4000E. The XC4000X Series therefore extends the addressing in Master Parallel conguration mode to 22 bits.

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Detailed Functional Description

XC4000 Series devices achieve high speed through advanced semiconductor technology and improved architecture. The XC4000E and XC4000X support system clock rates of up to 80 MHz and internal performance in excess of 150 MHz. Compared to older Xilinx FPGA families, XC4000 Series devices are more powerful. They offer onchip edge-triggered and dual-port RAM, clock enables on I/ O ip-ops, and wide-input decoders. They are more versatile in many applications, especially those involving RAM. Design cycles are faster due to a combination of increased routing resources and more sophisticated software.

Each CLB contains two storage elements that can be used to store the function generator outputs. However, the storage elements and function generators can also be used independently. These storage elements can be congured as ip-ops in both XC4000E and XC4000X devices; in the XC4000X they can optionally be congured as latches. DIN can be used as a direct input to either of the two storage elements. H1 can drive the other through the H function generator. Function generator outputs can also drive two outputs independent of the storage element outputs. This versatility increases logic capacity and simplies routing. Thirteen CLB inputs and four CLB outputs provide access to the function generators and storage elements. These inputs and outputs connect to the programmable interconnect resources outside the block.

Basic Building Blocks

Xilinx user-programmable gate arrays include two major congurable elements: congurable logic blocks (CLBs) and input/output blocks (IOBs). CLBs provide the functional elements for constructing the users logic. IOBs provide the interface between the package pins and internal signal lines.

Function Generators
Four independent inputs are provided to each of two function generators (F1 - F4 and G1 - G4). These function generators, with outputs labeled F and G, are each capable of implementing any arbitrarily dened Boolean function of four inputs. The function generators are implemented as memory look-up tables. The propagation delay is therefore independent of the function implemented. A third function generator, labeled H, can implement any Boolean function of its three inputs. Two of these inputs can optionally be the F and G functional generator outputs. Alternatively, one or both of these inputs can come from outside the CLB (H2, H0). The third input must come from outside the block (H1). Signals from the function generators can exit the CLB on two outputs. F or H can be connected to the X output. G or H can be connected to the Y output. A CLB can be used to implement any of the following functions: any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables1 any single function of ve variables any function of four variables together with some functions of six variables some functions of up to nine variables.

Three other types of circuits are also available: 3-State buffers (TBUFs) driving horizontal longlines are associated with each CLB. Wide edge decoders are available around the periphery of each device. An on-chip oscillator is provided.

Programmable interconnect resources provide routing paths to connect the inputs and outputs of these congurable elements to the appropriate networks. The functionality of each circuit block is customized during conguration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA. Each of these available circuits is described in this section.

Congurable Logic Blocks (CLBs)

Congurable Logic Blocks implement most of the logic in an FPGA. The principal CLB elements are shown in Figure 2. Two 4-input function generators (F and G) offer unrestricted versatility. Most combinatorial logic functions need four or fewer inputs. However, a third function generator (H) is provided. The H function generator has three inputs. Either zero, one, or two of these inputs can be the outputs of F and G; the other input(s) are from outside the CLB. The CLB can, therefore, implement certain functions of up to nine variables, like parity check or expandableidentity comparison of two sets of four inputs.

Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators signicantly improves system speed. In addition, the design-software tools can deal with each function generator independently. This exibility improves cell usage.

1. When three separate functions are generated, one of the function outputs must be captured in a ip-op internal to the CLB. Only two unregistered function generator outputs are available from the CLB.

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C1 C4

H1

D IN /H 2

SR/H 0

EC

G4 G3 G2 G1 LOGIC FUNCTION OF H' F', G', AND H1 F4 F3 F2 F1 LOGIC FUNCTION F' OF F1-F4 DIN F' G' H' LOGIC FUNCTION G' OF G1-G4 DIN F' G' H'

S/R CONTROL D SD

Bypass YQ Q

EC G' H' RD 1 Y S/R CONTROL D SD Q Bypass XQ

EC K (CLOCK) H' F' Multiplexer Controlled by Configuration Program RD 1 X

X6692

Figure 2: Simplied Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)

Flip-Flops
The CLB can pass the combinatorial output(s) to the interconnect network, but can also store the combinatorial results or other incoming data in one or two ip-ops, and connect their outputs to the interconnect network as well. The two edge-triggered D-type ip-ops have common clock (K) and clock enable (EC) inputs. Either or both clock inputs can also be permanently enabled. Storage element functionality is described in Table 3.

Clock Enable
The clock enable signal (EC) is active High. The EC pin is shared by both storage elements. If left unconnected for either, the clock enable for that storage element defaults to the active state. EC is not invertible within the CLB. Table 3: CLB Storage Element Functionality (active rising edge is shown) Mode Power-Up or GSR Flip-Flop K X X __/ 0 1 0 X EC X X 1* X 1* 1* 0 SR X 1 0* 0* 0* 0* 0* D X X D X X D X Q SR SR D Q Q D Q

Latches (XC4000X only)

The CLB storage elements can also be congured as latches. The two latches have common clock (K) and clock enable (EC) inputs. Storage element functionality is described in Table 3.

Clock Input
Each ip-op can be triggered on either the rising or falling clock edge. The clock pin is shared by both storage elements. However, the clock is individually invertible for each storage element. Any inverter placed on the clock input is automatically absorbed into the CLB.

Latch Both
Legend: X __/ SR 0* 1*

Dont care Rising edge Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value)

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Set/Reset
An asynchronous storage element input (SR) can be congured as either set or reset. This conguration option determines the state in which each ip-op becomes operational after conguration. It also determines the effect of a Global Set/Reset pulse during normal operation, and the effect of a pulse on the SR pin of the CLB. All three set/ reset functions for any single ip-op are controlled by the same conguration data bit. The set/reset state can be independently specied for each ip-op. This input can also be independently disabled for either ip-op. The set/reset state is specied by using the INIT attribute, or by placing the appropriate set or reset ip-op library symbol. SR is active High. It is not invertible within the CLB.

Two fast feed-through paths are available, as shown in Figure 2. A two-to-one multiplexer on each of the XQ and YQ outputs selects between a storage element output and any of the control inputs. This bypass is sometimes used by the automated router to repower internal signals.

Control Signals
Multiplexers in the CLB map the four control inputs (C1 - C4 in Figure 2) into the four internal control signals (H1, DIN/ H2, SR/H0, and EC). Any of these inputs can drive any of the four internal control signals. When the logic function is enabled, the four inputs are: EC Enable Clock SR/H0 Asynchronous Set/Reset or H function generator Input 0 DIN/H2 Direct In or H function generator Input 2 H1 H function generator Input 1.

Global Set/Reset
A separate Global Set/Reset line (not shown in Figure 2) sets or clears each storage element during power-up, reconguration, or when a dedicated Reset net is driven active. This global net (GSR) does not compete with other routing resources; it uses a dedicated distribution network. Each ip-op is congured as either globally set or reset in the same way that the local set/reset (SR) is specied. Therefore, if a ip-op is set by SR, it is also set by GSR. Similarly, a reset ip-op is reset by both SR and GSR.
STARTUP PAD IBUF GSR GTS Q2 Q3 Q1Q4 CLK DONEIN
X5260

When the memory function is enabled, the four inputs are: EC Enable Clock WE Write Enable D0 Data Input to F and/or G function generator D1 Data input to G function generator (16x1 and 16x2 modes) or 5th Address bit (32x1 mode).

Using FPGA Flip-Flops and Latches

The abundance of ip-ops in the XC4000 Series invites pipelined designs. This is a powerful way of increasing performance by breaking the function into smaller subfunctions and executing them in parallel, passing on the results through pipeline ip-ops. This method should be seriously considered wherever throughput is more important than latency. To include a CLB ip-op, place the appropriate library symbol. For example, FDCE is a D-type ip-op with clock enable and asynchronous clear. The corresponding latch symbol (for the XC4000X only) is called LDCE. In XC4000 Series devices, registers or shift registers generators from performing task. This ability increases devices. the ip ops can be used as without blocking the function a different, perhaps unrelated the functional capacity of the

Figure 3: Schematic Symbols for Global Set/Reset GSR can be driven from any user-programmable pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GSR pin of the STARTUP symbol. (See Figure 3.) A specic pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global Set/Reset signal. Alternatively, GSR can be driven from any internal node.

The CLB setup time is specied between the function generator inputs and the clock input K. Therefore, the specied CLB ip-op setup time includes the delay through the function generator.

Using Function Generators as RAM

Optional modes for each CLB make the memory look-up tables in the F and G function generators usable as an array of Read/Write memory cells. Available modes are level-sensitive (similar to the XC4000/A/H families), edgetriggered, and dual-port edge-triggered. Depending on the

Data Inputs and Outputs

The source of a storage element data input is programmable. It is driven by any of the functions F, G, and H, or by the Direct In (DIN) block input. The ip-ops or latches drive the XQ and YQ CLB outputs.

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selected mode, a single CLB can be congured as either a 16x2, 32x1, or 16x1 bit array. Supported CLB memory congurations and timing modes for single- and dual-port modes are shown in Table 4. XC4000 Series devices are the rst programmable logic devices with edge-triggered (synchronous) and dual-port RAM accessible to the user. Edge-triggered RAM simplies system timing. Dual-port RAM doubles the effective throughput of FIFO applications. These features can be individually programmed in any XC4000 Series CLB. Advantages of On-Chip and Edge-Triggered RAM The on-chip RAM is extremely fast. The read access time is the same as the logic delay. The write access time is slightly slower. Both access times are much faster than any off-chip solution, because they avoid I/O delays. Edge-triggered RAM, also called synchronous RAM, is a feature never before available in a Field Programmable Gate Array. The simplicity of designing with edge-triggered RAM, and the markedly higher achievable performance, add up to a signicant improvement over existing devices with on-chip RAM. Three application notes are available from Xilinx that discuss edge-triggered RAM: XC4000E Edge-Triggered and Dual-Port RAM Capability, Implementing FIFOs in XC4000E RAM, and Synchronous and Asynchronous FIFO Designs. All three application notes apply to both XC4000E and XC4000X RAM. Table 4: Supported RAM Modes 16 x 1 16 x 2 32 x 1 EdgeTriggered Timing LevelSensitive Timing

Level-Sensitive (Asynchronous): an external WE signal acts as the write strobe.

The selected timing mode applies to both function generators within a CLB when both are congured as RAM. The number of read ports is also programmable: Single Port: each function generator has a common read and write port Dual Port: both function generators are congured together as a single 16x1 dual-port RAM with one write port and two read ports. Simultaneous read and write operations to the same or different addresses are supported.

RAM conguration options are selected by placing the appropriate library symbol. Choosing a RAM Conguration Mode The appropriate choice of RAM mode for a given design should be based on timing and resource requirements, desired functionality, and the simplicity of the design process. Recommended usage is shown in Table 5. The difference between level-sensitive, edge-triggered, and dual-port RAM is only in the write operation. Read operation and timing is identical for all modes of operation. Table 5: RAM Mode Selection LevelSensitive Use for New Designs? Size (16x1, Registered) Simultaneous Read/Write Relative Performance No 1/2 CLB No X EdgeTriggered Yes 1/2 CLB No 2X Dual-Port EdgeTriggered Yes 1 CLB Yes 2X (4X effective)

Single-Port Dual-Port

RAM Conguration Options The function generators in any CLB can be congured as RAM arrays in the following sizes: Two 16x1 RAMs: two data inputs and two data outputs with identical or, if preferred, different addressing for each RAM One 32x1 RAM: one data input and one data output.

RAM Inputs and Outputs The F1-F4 and G1-G4 inputs to the function generators act as address lines, selecting a particular memory cell in each look-up table. The functionality of the CLB control signals changes when the function generators are congured as RAM. The DIN/ H2, H1, and SR/H0 lines become the two data inputs (D0, D1) and the Write Enable (WE) input for the 16x2 memory. When the 32x1 conguration is selected, D1 acts as the fth address bit and D0 is the data input. The contents of the memory cell(s) being addressed are available at the F and G function-generator outputs. They can exit the CLB through its X and Y outputs, or can be captured in the CLB ip-op(s).

One F or G function generator can be congured as a 16x1 RAM while the other function generators are used to implement any function of up to 5 inputs. Additionally, the XC4000 Series RAM may have either of two timing modes: Edge-Triggered (Synchronous): data written by the designated edge of the CLB clock. WE acts as a true clock enable.

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Conguring the CLB function generators as Read/Write memory does not affect the functionality of the other portions of the CLB, with the exception of the redenition of the control signals. In 16x2 and 16x1 modes, the H function generator can be used to implement Boolean functions of F, G, and D1, and the D ip-ops can latch the F, G, H, or D0 signals. Single-Port Edge-Triggered Mode Edge-triggered (synchronous) RAM simplies timing requirements. XC4000 Series edge-triggered RAM timing operates like writing to a data register. Data and address are presented. The register is enabled for writing by a logic High on the write enable input, WE. Then a rising or falling clock edge loads the data into the register, as shown in Figure 4.
TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

edge of WCLK latches the address, input data, and WE signals. An internal write pulse is generated that performs the write. See Figure 5 and Figure 6 for block diagrams of a CLB congured as 16x2 and 32x1 edge-triggered, singleport RAM. The relationships between CLB pins and RAM inputs and outputs for single-port, edge-triggered mode are shown in Table 6. The Write Clock input (WCLK) can be congured as active on either the rising edge (default) or the falling edge. It uses the same CLB pin (K) used to clock the CLB ip-ops, but it can be independently inverted. Consequently, the RAM output can optionally be registered within the same CLB either by the same clock edge as the RAM, or by the opposite edge of this clock. The sense of WCLK applies to both function generators in the CLB when both are congured as RAM. The WE pin is active-High and is not invertible within the CLB. Note: The pulse following the active edge of WCLK (TWPS in Figure 4) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive; however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even damage to the larger devices if many CLBs are congured as edge-triggered RAM. Table 6: Single-Port Edge-Triggered RAM Signals

TILO

RAM Signal D A[3:0] A[4] WE WCLK SPO (Data Out)

TWOS OLD

DATA OUT

NEW
X6461

Figure 4:

Edge-Triggered RAM Write Timing

Complex timing relationships between address, data, and write enable signals are not required, and the external write enable pulse becomes a simple clock enable. The active

CLB Pin D0 or D1 (16x2, 16x1), D0 (32x1) F1-F4 or G1-G4 D1 (32x1) WE K F or G

Function Data In Address Address Write Enable Clock Single Port Out (Data Out)

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C1 C4

WE

D1

D0

EC

DIN

WRITE DECODER G1 G4 4 4 1 of 16 LATCH ENABLE

16-LATCH ARRAY

MUX

G'

WRITE PULSE

READ ADDRESS

DIN

WRITE DECODER F1 F4 4 4 1 of 16 LATCH ENABLE

16-LATCH ARRAY

MUX

F'

K (CLOCK)

WRITE PULSE

READ ADDRESS X6752

Figure 5:

16x2 (or 16x1) Edge-Triggered Single-Port RAM

C1 C4

EC WE D1/A4 D0 EC

DIN

WRITE DECODER G1 G 4 F1 F 4 4 4 1 of 16 LATCH ENABLE

16-LATCH ARRAY

MUX

G'

WRITE PULSE

READ ADDRESS H'

DIN

WRITE DECODER 4 4 1 of 16 LATCH ENABLE

16-LATCH ARRAY

MUX

F'

K (CLOCK)

WRITE PULSE

READ ADDRESS X6754

Figure 6: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)

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Dual-Port Edge-Triggered Mode In dual-port mode, both the F and G function generators are used to create a single 16x1 RAM array with one write port and two read ports. The resulting RAM array can be read and written simultaneously at two independent addresses. Simultaneous read and write operations at the same address are also supported. Dual-port mode always has edge-triggered write timing, as shown in Figure 4. Figure 7 shows a simple model of an XC4000 Series CLB congured as dual-port RAM. One address port, labeled A[3:0], supplies both the read and write address for the F function generator. This function generator behaves the same as a 16x1 single-port edge-triggered RAM array. The RAM output, Single Port Out (SPO), appears at the F function generator output. SPO, therefore, reects the data at address A[3:0]. The other address port, labeled DPRA[3:0] for Dual Port Read Address, supplies the read address for the G function generator. The write address for the G function generator, however, comes from the address A[3:0]. The output from this 16x1 RAM array, Dual Port Out (DPO), appears at the G function generator output. DPO, therefore, reects the data at address DPRA[3:0]. Therefore, by using A[3:0] for the write address and DPRA[3:0] for the read address, and reading only the DPO output, a FIFO that can read and write simultaneously is easily generated. Simultaneous access doubles the effective throughput of the FIFO. The relationships between CLB pins and RAM inputs and outputs for dual-port, edge-triggered mode are shown in Table 7. See Figure 8 on page 4-16 for a block diagram of a CLB congured in this mode.
RAM16X1D Primitive DPO (Dual Port Out) WE D DPRA[3:0] WE D AR[3:0] AW[3:0] D Q Registered DPO

Table 7: Dual-Port Edge-Triggered RAM Signals RAM Signal CLB Pin D D0 A[3:0] F1-F4 DPRA[3:0] WE WCLK SPO DPO G1-G4 WE K F G Function Data In Read Address for F, Write Address for F and G Read Address for G Write Enable Clock Single Port Out (addressed by A[3:0]) Dual Port Out (addressed by DPRA[3:0])

Note: The pulse following the active edge of WCLK (TWPS in Figure 4) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive; however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even damage to the larger devices if many CLBs are congured as edge-triggered RAM. Single-Port Level-Sensitive Timing Mode Note: Edge-triggered mode is recommended for all new designs. Level-sensitive mode, also called asynchronous mode, is still supported for XC4000 Series backward-compatibility with the XC4000 family. Level-sensitive RAM timing is simple in concept but can be complicated in execution. Data and address signals are presented, then a positive pulse on the write enable pin (WE) performs a write into the RAM at the designated address. As indicated by the level-sensitive label, this RAM acts like a latch. During the WE High pulse, changing the data lines results in new data written to the old address. Changing the address lines while WE is High results in spurious data written to the new addressand possibly at other addresses as well, as the address lines inevitably do not all change simultaneously. The user must generate a carefully timed WE signal. The delay on the WE signal and the address lines must be carefully veried to ensure that WE does not become active until after the address lines have settled, and that WE goes inactive before the address lines change again. The data must be stable before and after the falling edge of WE. In practical terms, WE is usually generated by a 2X clock. If a 2X clock is not available, the falling edge of the system clock can be used. However, there are inherent risks in this approach, since the WE pulse must be guaranteed inactive before the next rising edge of the system clock. Several older application notes are available from Xilinx that discuss the design of level-sensitive RAMs. These application notes include XAPP031, Using the XC4000 RAM Capability, and XAPP042, High-Speed RAM Design in XC4000. However, the edge-triggered RAM available in the XC4000 Series is superior to level-sensitive RAM for almost every application.

G Function Generator

SPO (Single Port Out) WE D A[3:0] AR[3:0] AW[3:0] D Q Registered SPO

F Function Generator

WCLK
X6755

Figure 7: XC4000 Series Dual-Port RAM, Simple Model

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C1 C4

WE

D1

D0

EC

DIN

WRITE DECODER 4 1 of 16 LATCH ENABLE 4

16-LATCH ARRAY

MUX

G'

G1 G4

WRITE PULSE

READ ADDRESS

DIN

WRITE DECODER

16-LATCH ARRAY

MUX

F'

F1 F4

4 1 of 16 LATCH ENABLE WRITE PULSE READ ADDRESS

K (CLOCK)

X6748

Figure 8: 16x1 Edge-Triggered Dual-Port RAM Figure 9 shows the write timing for level-sensitive, singleport RAM. The relationships between CLB pins and RAM inputs and outputs for single-port level-sensitive mode are shown in Table 8. Figure 10 and Figure 11 show block diagrams of a CLB congured as 16x2 and 32x1 level-sensitive, single-port RAM. Initializing RAM at Conguration Both RAM and ROM implementations of the XC4000 Series devices are initialized during conguration. The initial contents are dened via an INIT attribute or property attached to the RAM or ROM symbol, as described in the schematic library guide. If not dened, all RAM contents are initialized to all zeros, by default. RAM initialization occurs only during conguration. The RAM content is not affected by Global Set/Reset. Table 8: Single-Port Level-Sensitive RAM Signals RAM Signal D A[3:0] WE O CLB Pin D0 or D1 F1-F4 or G1-G4 WE F or G Function Data In Address Write Enable Data Out

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T WC ADDRESS

TAS WRITE ENABLE

T WP

T AH

T DS DATA IN REQUIRED

T DH

X6462

Figure 9: Level-Sensitive RAM Write Timing

C1 C4

WE

D1

D0

EC

Enable

DIN

G1 G 4

WRITE DECODER 1 of 16 4

16-LATCH ARRAY

MUX

G'

READ ADDRESS

Enable

DIN

F1 F 4

WRITE DECODER 1 of 16 4

16-LATCH ARRAY

MUX

F'

X6746

READ ADDRESS

Figure 10: 16x2 (or 16x1) Level-Sensitive Single-Port RAM

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C1 C4

WE

D1/A4

D0

EC

Enable

DIN

G1 G4 F1 F4

WRITE DECODER 1 of 16

16-LATCH ARRAY

MUX

G'

4 READ ADDRESS H'

Enable

DIN

WRITE DECODER 1 of 16

16-LATCH ARRAY

MUX

F'

4 READ ADDRESS X6749

Figure 11: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)

Fast Carry Logic

Each CLB F and G function generator contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is passed on to the function generator in the adjacent CLB. The carry chain is independent of normal routing resources. Dedicated fast carry logic greatly increases the efciency and performance of adders, subtractors, accumulators, comparators and counters. It also opens the door to many new applications involving arithmetic operation, where the previous generations of FPGAs were not fast enough or too inefcient. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addition in digital signal processing are two typical applications. The two 4-input function generators can be congured as a 2-bit adder with built-in hidden carry that can be expanded to any length. This dedicated carry circuitry is so fast and efcient that conventional speed-up methods like carry generate/propagate are meaningless even at the 16-bit level, and of marginal benet at the 32-bit level. This fast carry logic is one of the more signicant features of the XC4000 Series, speeding up arithmetic and counting into the 70 MHz range.

The carry chain in XC4000E devices can run either up or down. At the top and bottom of the columns where there are no CLBs above or below, the carry is propagated to the right. (See Figure 12.) In order to improve speed in the high-capacity XC4000X devices, which can potentially have very long carry chains, the carry chain travels upward only, as shown in Figure 13. Additionally, standard interconnect can be used to route a carry signal in the downward direction. Figure 14 on page 4-20 shows an XC4000E CLB with dedicated fast carry logic. The carry logic in the XC4000X is similar, except that COUT exits at the top only, and the signal CINDOWN does not exist. As shown in Figure 14, the carry logic shares operand and control inputs with the function generators. The carry outputs connect to the function generators, where they are combined with the operands to form the sums. Figure 15 on page 4-21 shows the details of the carry logic for the XC4000E. This diagram shows the contents of the box labeled CARRY LOGIC in Figure 14. The XC4000X carry logic is very similar, but a multiplexer on the passthrough carry chain has been eliminated to reduce delay. Additionally, in the XC4000X the multiplexer on the G4 path has a memory-programmable 0 input, which permits G4 to

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directly connect to COUT. G4 thus becomes an additional high-speed initialization path for carry-in. The dedicated carry logic is discussed in detail in Xilinx document XAPP 013: Using the Dedicated Carry Logic in XC4000. This discussion also applies to XC4000E devices, and to XC4000X devices when the minor logic changes are taken into account. The fast carry logic can be accessed by placing special library symbols, or by using Xilinx Relationally Placed Macros (RPMs) that already include these symbols.

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

X6610

CLB

CLB

CLB

CLB

Figure 13: Available XC4000X Carry Propagation Paths (dotted lines use general interconnect)

CLB

CLB

CLB

CLB
X6687

Figure 12: Available XC4000E Carry Propagation Paths

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XC4000E and XC4000X Series Field Programmable Gate Arrays

CARRY LOGIC

C OUT

C IN DOWN

D IN

G Y

G CARRY

G4

G3 G G2 DIN H G F G1 EC COUT0 D S/R Q YQ

H1

DIN F CARRY H G F D S/R Q XQ

F4

EC

F3 F F2 F1 H X F

CIN UP

C OUT

S/R

EC X6699

Figure 14: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000X)

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C OUT M G1 1 0 I G4 0 1 G2 M

G3 C OUT0 M F2 M 1 F1 0 M M M F3 M 0 1 3 1 0 M 0 1 F4 TO FUNCTION GENERATORS

M M 1 0

X2000

C IN UP C IN DOWN

Figure 15: Detail of XC4000E Dedicated Carry Logic

Input/Output Blocks (IOBs)

User-congurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be congured for input, output, or bidirectional signals. Figure 16 shows a simplied block diagram of the XC4000E IOB. A more complete diagram which includes the boundary scan logic of the XC4000E IOB can be found in Figure 41 on page 4-44, in the Boundary Scan section. The XC4000X IOB contains some special features not included in the XC4000E IOB. These features are highlighted in a simplied block diagram found in Figure 17, and discussed throughout this section. When XC4000X special features are discussed, they are clearly identied in the text. Any feature not so identied is present in both XC4000E and XC4000X devices.

The choice is made by placing the appropriate library symbol. For example, IFD is the basic input ip-op (rising edge triggered), and ILD is the basic input latch (transparentHigh). Variations with inverted clocks are available, and some combinations of latches and ip-ops can be implemented in a single IOB, as described in the XACT Libraries Guide. The XC4000E inputs can be globally congured for either TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in the bitstream generation software. There is a slight input hysteresis of about 300mV. The XC4000E output levels are also congurable; the two global adjustments of input threshold and output level are independent. Inputs on the XC4000XL are TTL compatible and 3.3V CMOS compatible. Outputs on the XC4000XL are pulled to the 3.3V positive supply. The inputs of XC4000 Series 5-Volt devices can be driven by the outputs of any 3.3-Volt device, if the 5-Volt inputs are in TTL mode. Supported sources for XC4000 Series device inputs are shown in Table 9.

IOB Input Signals

Two paths, labeled I1 and I2 in Figure 16 and Figure 17, bring input signals into the array. Inputs also connect to an input register that can be programmed as either an edgetriggered ip-op or a level-sensitive latch.

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Slew Rate Control

Passive Pull-Up/ Pull-Down

T Flip-Flop D Out CE Output Clock I1 FlipFlop/ Latch Q D Delay Input Buffer Q Output Buffer Pad

I2

Clock Enable Input Clock

CE

X6704

Figure 16: Simplied Block Diagram of XC4000E IOB

Slew Rate Control T

Passive Pull-Up/ Pull-Down

Output MUX

0 1 Out Flip-Flop D CE Output Clock I1 Flip-Flop/ Latch Q D

Delay Delay

Q Output Buffer Input Buffer Pad

I2

Clock Enable

CE

Fast Capture Latch

Q D Latch G

Input Clock
X5984

Figure 17: Simplied Block Diagram of XC4000X IOB (shaded areas indicate differences from XC4000E)

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Table 9: Supported Sources for XC4000 Series Device Inputs XC4000E/EX XC4000XL Series Inputs Series Inputs 5 V, 5 V, 3.3 V TTL CMOS CMOS Unreli -able Data

Optional Delay Guarantees Zero Hold Time The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup time of the input ip-op is increased so that normal clock routing does not result in a positive hold-time requirement. A positive hold time requirement can lead to unreliable, temperature- or processing-dependent operation. The input ip-op setup time is dened between the data measured at the device I/O pin and the clock input at the IOB (not at the clock pin). Any routing delay from the device clock pin to the clock input of the IOB must, therefore, be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins. A short specied setup time might, therefore, result in a negative setup time at the device pins, i.e., a positive hold-time requirement. When a delay is inserted on the data line, more clock delay can be tolerated without causing a positive hold-time requirement. Sufcient delay eliminates the possibility of a data hold-time requirement at the external pin. The maximum delay is therefore inserted as the default. The XC4000E IOB has a one-tap delay element: either the delay is inserted (default), or it is not. The delay guarantees a zero hold time with respect to clocks routed through any of the XC4000E global clock buffers. (See Global Nets and Buffers (XC4000E only) on page 4-36 for a description of the global clock buffers in the XC4000E.) For a shorter input register setup time, with non-zero hold, attach a NODELAY attribute or property to the ip-op. The XC4000X IOB has a two-tap delay element, with choices of a full delay, a partial delay, or no delay. The attributes or properties used to select the desired delay are shown in Table 11. The choices are no added attribute, MEDDELAY, and NODELAY. The default setting, with no added attribute, ensures no hold time with respect to any of the XC4000X clock buffers, including the Global Low-Skew buffers. MEDDELAY ensures no hold time with respect to the Global Early buffers. Inputs with NODELAY may have a positive hold time with respect to all clock buffers. For a description of each of these buffers, see Global Nets and Buffers (XC4000X only) on page 4-38. Table 11: XC4000X IOB Input Delay Element Value full delay (default, no attribute added) MEDDELAY NODELAY When to Use Zero Hold with respect to Global LowSkew Buffer, Global Early Buffer Zero Hold with respect to Global Early Buffer Short Setup, positive Hold time

Source Any device, Vcc = 3.3 V, CMOS outputs XC4000 Series, Vcc = 5 V, TTL outputs Any device, Vcc = 5 V, TTL outputs (Voh 3.7 V) Any device, Vcc = 5 V, CMOS outputs

XC4000XL 5-Volt Tolerant I/Os The I/Os on the XC4000XL are fully 5-volt tolerant even though the VCC is 3.3 volts. This allows 5 V signals to directly connect to the XC4000XL inputs without damage, as shown in Table 9. In addition, the 3.3 volt VCC can be applied before or after 5 volt signals are applied to the I/Os. This makes the XC4000XL immune to power supply sequencing problems. Registered Inputs The I1 and I2 signals that exit the block can each carry either the direct or registered input signal. The input and output storage elements in each IOB have a common clock enable input, which, through conguration, can be activated individually for the input or output ip-op, or both. This clock enable operates exactly like the EC pin on the XC4000 Series CLB. It cannot be inverted within the IOB. The storage element behavior is shown in Table 10. Table 10: Input Register Functionality (active rising edge is shown) Mode Power-Up or GSR Flip-Flop Latch Both
Legend: X __/ SR 0* 1*

Clock X __/ 0 1 0 X

Clock Enable X 1* X 1* 1* 0

D X D X X D X

Q SR D Q Q D Q

Dont care Rising edge Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value)

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Additional Input Latch for Fast Capture (XC4000X only) The XC4000X IOB has an additional optional latch on the input. This latch, as shown in Figure 17, is clocked by the output clock the clock used for the output ip-op rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements. This additional latch allows the very fast capture of input data, which is then synchronized to the internal clock by the IOB ip-op or latch. To use this Fast Capture technique, drive the output clock pin (the Fast Capture latching signal) from the output of one of the Global Early buffers supplied in the XC4000X. The second storage element should be clocked by a Global Low-Skew buffer, to synchronize the incoming data to the internal logic. (See Figure 18.) These special buffers are described in Global Nets and Buffers (XC4000X only) on page 4-38. The Fast Capture latch (FCL) is designed primarily for use with a Global Early buffer. For Fast Capture, a single clock signal is routed through both a Global Early buffer and a Global Low-Skew buffer. (The two buffers share an input pad.) The Fast Capture latch is clocked by the Global Early buffer, and the standard IOB ip-op or latch is clocked by the Global Low-Skew buffer. This mode is the safest way to use the Fast Capture latch, because the clock buffers on both storage elements are driven by the same pad. There is no external skew between clock pads to create potential problems. To place the Fast Capture latch in a design, use one of the special library symbols, ILFFX or ILFLX. ILFFX is a transparent-Low Fast Capture latch followed by an active-High input ip-op. ILFLX is a transparent-Low Fast Capture latch followed by a transparent-High input latch. Any of the clock inputs can be inverted before driving the library element, and the inverter is absorbed into the IOB. If a single BUFG output is used to drive both clock inputs, the software automatically runs the clock through both a Global Low-Skew buffer and a Global Early buffer, and clocks the Fast Capture latch appropriately. Figure 17 on page 4-22 also shows a two-tap delay on the input. By default, if the Fast Capture latch is used, the Xilinx software assumes a Global Early buffer is driving the clock, and selects MEDDELAY to ensure a zero hold time. Select

the desired delay based on the discussion in the previous subsection.

IOB Output Signals

Output signals can be optionally inverted within the IOB, and can pass directly to the pad or be stored in an edgetriggered ip-op. The functionality of this ip-op is shown in Table 12. An active-High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under conguration control, the output (OUT) and output 3-state (T) signals can be inverted. The polarity of these signals is independently congured for each IOB. The 4-mA maximum output current specication of many FPGAs often forces the user to add external buffers, which are especially cumbersome on bidirectional I/O lines. The XC4000E and XC4000EX/XL devices solve many of these problems by providing a guaranteed output sink current of 12 mA. Two adjacent outputs can be interconnected externally to sink up to 24 mA. The XC4000E and XC4000EX/XL FPGAs can thus directly drive buses on a printed circuit board. By default, the output pull-up structure is congured as a TTL-like totem-pole. The High driver is an n-channel pullup transistor, pulling to a voltage one transistor threshold below Vcc. Alternatively, the outputs can be globally congured as CMOS drivers, with p-channel pull-up transistors pulling to Vcc. This option, applied using the bitstream generation software, applies to all outputs on the device. It is not individually programmable. In the XC4000XL, all outputs are pulled to the positive supply rail. Table 12: Output Flip-Flop Functionality (active rising edge is shown) Mode Power-Up or GSR Flip-Flop Clock X X __/ X 0 Clock Enable X 0 1* X X T 0* 0* 0* 1 0* D X X D X X Q SR Q D Z Q

ILFFX
IPAD D Q to internal logic

GF BUFGE IPAD BUFGLS

X9013

CE C

Legend: X __/ SR 0* 1* Z

Dont care Rising edge Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value) 3-state

Figure 18: Examples Using XC4000X FCL

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Any XC4000 Series 5-Volt device with its outputs congured in TTL mode can drive the inputs of any typical 3.3Volt device. (For a detailed discussion of how to interface between 5 V and 3.3 V devices, see the 3V Products section of The Programmable Logic Data Book.) Supported destinations for XC4000 Series device outputs are shown in Table 13. An output can be congured as open-drain (open-collector) by placing an OBUFT symbol in a schematic or HDL code, then tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground. (See Figure 19.) Table 13: Supported Destinations for XC4000 Series Outputs XC4000 Series Outputs Destination 3.3 V, 5 V, 5 V, CMOS TTL CMOS Any typical device, Vcc = 3.3 V, some1 CMOS-threshold inputs Any device, Vcc = 5 V, TTL-threshold inputs Any device, Vcc = 5 V, Unreliable CMOS-threshold inputs Data
1. Only if destination device has 5-V tolerant inputs

pin pair. For XC4000X devices, additional internal Power/ Ground pin pairs are connected to special Power and Ground planes within the packages, to reduce ground bounce. Therefore, the maximum total capacitive load is 300 pF between each external Power/Ground pin pair. Maximum loading may vary for the low-voltage devices. For slew-rate limited outputs this total is two times larger for each device type: 400 pF for XC4000E devices and 600 pF for XC4000X devices. This maximum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 V amplitude and more than 5 ns duration. This level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. This restriction is common to all high-speed digital ICs, and is not particular to Xilinx or the XC4000 Series. XC4000 Series devices have a feature called Soft Startup, designed to reduce ground bounce when all outputs are turned on simultaneously at the end of conguration. When the conguration process is nished and the device starts up, the rst activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is determined by the individual conguration option for each IOB. Global Three-State A separate Global 3-State line (not shown in Figure 16 or Figure 17) forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. This global net (GTS) does not compete with other routing resources; it uses a dedicated distribution network. GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. A specic pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3-State signal. Using GTS is similar to GSR. See Figure 3 on page 4-11 for details. Alternatively, GTS can be driven from any internal node.

OPAD OBUFT
X6702

Figure 19: Open-Drain Output Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or property to the output buffer or ip-op. For XC4000E devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pF for all package pins between each Power/Ground

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Output Multiplexer/2-Input Function Generator (XC4000X only) As shown in Figure 17 on page 4-22, the output path in the XC4000X IOB contains an additional multiplexer not available in the XC4000E IOB. The multiplexer can also be congured as a 2-input function generator, implementing a pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2 inverted inputs. The logic used to implement these functions is shown in the upper gray area of Figure 17. When congured as a multiplexer, this feature allows two output signals to time-share the same output pad; effectively doubling the number of device outputs without requiring a larger, more expensive package. When the MUX is congured as a 2-input function generator, logic can be implemented within the IOB itself. Combined with a Global Early buffer, this arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe Driven by a BUFGE buffer, as shown in Figure 20. The critical-path pin-to-pin delay of this circuit is less than 6 nanoseconds. As shown in Figure 17, the IOB input pins Out, Output Clock, and Clock Enable have different delays and different exibilities regarding polarity. Additionally, Output Clock sources are more limited than the other inputs. Therefore, the Xilinx software does not move logic into the IOB function generators unless explicitly directed to do so. The user can specify that the IOB function generator be used, by placing special library symbols beginning with the letter O. For example, a 2-input AND-gate in the IOB function generator is called OAND2. Use the symbol input pin labelled F for the signal on the critical path. This signal is placed on the OK pin the IOB input with the shortest delay to the function generator. Two examples are shown in Figure 21.
IPAD BUFGE F from internal logic OAND2 OPAD FAST
X9019

Other IOB Options

There are a number of other programmable options in the XC4000 Series IOB. Pull-up and Pull-down Resistors Programmable pull-up and pull-down resistors are useful for tying unused pins to Vcc or Ground to minimize power consumption and reduce noise sensitivity. The congurable pull-up resistor is a p-channel transistor that pulls to Vcc. The congurable pull-down resistor is an n-channel transistor that pulls to Ground. The value of these resistors is 50 k 100 k. This high value makes them unsuitable as wired-AND pull-up resistors. The pull-up resistors for most user-programmable IOBs are active during the conguration process. See Table 23 on page 4-59 for a list of pins with pull-ups active before and during conguration. After conguration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are congured with the internal pull-up resistor active. Alternatively, they can be individually congured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pullup, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad. Independent Clocks Separate clock signals are provided for the input and output ip-ops. The clock can be independently inverted for each ip-op within the IOB, generating either falling-edge or rising-edge triggered ip-ops. The clock inputs for each IOB are independent, except that in the XC4000X, the Fast Capture latch shares an IOB input with the output clock pin. Early Clock for IOBs (XC4000X only) Special early clocks are available for IOBs. These clocks are sourced by the same sources as the Global Low-Skew buffers, but are separately buffered. They have fewer loads and therefore less delay. The early clock can drive either the IOB output clock or the IOB input clock, or both. The early clock allows fast capture of input data, and fast clockto-output on output data. The Global Early buffers that drive these clocks are described in Global Nets and Buffers (XC4000X only) on page 4-38. Global Set/Reset As with the CLB registers, the Global Set/Reset signal (GSR) can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two ip-ops can be individually congured to set

Figure 20: Fast Pin-to-Pin Path in XC4000X

F OAND2

D0 D1
X6598

OMUX2 O

S0
X6599

Figure 21: AND & MUX Symbols in XC4000X IOB

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or clear on reset and after conguration. Other than the global GSR net, no user-controlled set/reset signal is available to the I/O ip-ops. The choice of set or clear applies to both the initial state of the ip-op and the response to the Global Set/Reset pulse. See Global Set/Reset on page 411 for a description of how to use GSR. JTAG Support Embedded logic attached to the IOBs contains test structures compatible with IEEE Standard 1149.1 for boundary scan testing, permitting easy chip and board-level testing. More information is provided in Boundary Scan on page 4-43.

Standard 3-State Buffer All three pins are used. Place the library element BUFT. Connect the input to the I pin and the output to the O pin. The T pin is an active-High 3-state (i.e. an active-Low enable). Tie the T pin to Ground to implement a standard buffer. Wired-AND with Input on the I Pin The buffer can be used as a Wired-AND. Use the WAND1 library symbol, which is essentially an open-drain buffer. WAND4, WAND8, and WAND16 are also available. See the XACT Libraries Guide for further information. The T pin is internally tied to the I pin. Connect the input to the I pin and the output to the O pin. Connect the outputs of all the WAND1s together and attach a PULLUP symbol. Wired OR-AND The buffer can be congured as a Wired OR-AND. A High level on either input turns off the output. Use the WOR2AND library symbol, which is essentially an opendrain 2-input OR gate. The two input pins are functionally equivalent. Attach the two inputs to the I0 and I1 pins and tie the output to the O pin. Tie the outputs of all the WOR2ANDs together and attach a PULLUP symbol.

Three-State Buffers
A pair of 3-state buffers is associated with each CLB in the array. (See Figure 28 on page 4-31.) These 3-state buffers can be used to drive signals onto the nearest horizontal longlines above and below the CLB. They can therefore be used to implement multiplexed or bidirectional buses on the horizontal longlines, saving logic resources. Programmable pull-up resistors attached to these longlines help to implement a wide wired-AND function. The buffer enable is an active-High 3-state (i.e. an activeLow enable), as shown in Table 14. Another 3-state buffer with similar access is located near each I/O block along the right and left edges of the array. (See Figure 34 on page 4-35.) The horizontal longlines driven by the 3-state buffers have a weak keeper at each end. This circuit prevents undened oating levels. However, it is overridden by any driver, even a pull-up resistor. Special longlines running along the perimeter of the array can be used to wire-AND signals coming from nearby IOBs or from internal longlines. These longlines form the wide edge decoders discussed in Wide Edge Decoders on page 4-28.

Three-State Buffer Examples

Figure 22 shows how to use the 3-state buffers to implement a wired-AND function. When all the buffer inputs are High, the pull-up resistor(s) provide the High output. Figure 23 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the buffer 3-state signal. Pay particular attention to the polarity of the T pin when using these buffers in a design. Active-High 3-state (T) is identical to an active-Low output enable, as shown in Table 14. Table 14: Three-State Buffer Functionality IN X IN T 1 0 OUT Z IN

Three-State Buffer Modes

The 3-state buffers can be congured in three modes: Standard 3-state buffer Wired-AND with input on the I pin Wired OR-AND

Z=D

qD

q (D

+D ) q (D +D )
D E F

P U L L

U P

D
WAND1

D C D
WAND1
D

D E D
F

WOR2AND

WOR2AND
X6465

Figure 22: Open-Drain Buffers Implement a Wired-AND Function

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XC4000E and XC4000X Series Field Programmable Gate Arrays

~100 k

Z = DA A + DB B + DC C + DN N

DA BUFT A "Weak Keeper"

DB BUFT B

DC BUFT C

DN BUFT N
X6466

Figure 23: 3-State Buffers Implement a Multiplexer

Wide Edge Decoders

Dedicated decoder circuitry boosts the performance of wide decoding functions. When the address or data eld is wider than the function generator inputs, FPGAs need multi-level decoding and are thus slower than PALs. XC4000 Series CLBs have nine inputs. Any decoder of up to nine inputs is, therefore, compact and fast. However, there is also a need for much wider decoders, especially for address decoding in large microprocessor systems. An XC4000 Series FPGA has four programmable decoders located on each edge of the device. The inputs to each decoder are any of the IOB I1 signals on that edge plus one local interconnect per CLB row or column. Each row or column of CLBs provides up to three variables or their compliments., as shown in Figure 24. Each decoder generates a High output (resistor pull-up) when the AND condition of the selected inputs, or their complements, is true. This is analogous to a product term in typical PAL devices. Each of these wired-AND gates is capable of accepting up to 42 inputs on the XC4005E and 72 on the XC4013E. There are up to 96 inputs for each decoder on the XC4028X and 132 on the XC4052X. The decoders may also be split in two when a larger number of narrower decoders are required, for a maximum of 32 decoders per device. The decoder outputs can drive CLB inputs, so they can be combined with other logic to form a PAL-like AND/OR structure. The decoder outputs can also be routed directly to the chip outputs. For fastest speed, the output should be on the same chip edge as the decoder. Very large PALs can be emulated by ORing the decoder outputs in a CLB. This decoding feature covers what has long been considered a weakness of older FPGAs. Users often resorted to external PALs for simple but fast decoding functions. Now, the dedicated decoders in the XC4000 Series device can implement these functions fast and efciently. To use the wide edge decoders, place one or more of the WAND library symbols (WAND1, WAND4, WAND8, WAND16). Attach a DECODE attribute or property to each WAND symbol. Tie the outputs together and attach a PULLUP symbol. Location attributes or properties such as L (left edge) or TR (right half of top edge) should also be used to ensure the correct placement of the decoder inputs.
INTERCONNECT

IOB .I1 A C

IOB .I1 B

C) .....

(A B C) ..... (A B C) ..... (A B C) .....

X2627

Figure 24: XC4000 Series Edge Decoding Example

OSC4
F8M F500K F16K F490 F15
X6703

Figure 25: XC4000 Series Oscillator Symbol

On-Chip Oscillator
XC4000 Series devices include an internal oscillator. This oscillator is used to clock the power-on time-out, for conguration memory clearing, and as the source of CCLK in Master conguration modes. The oscillator runs at a nominal 8 MHz frequency that varies with process, Vcc, and temperature. The output frequency falls between 4 and 10 MHz.

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The oscillator output is optionally available after conguration. Any two of four resynchronized taps of a built-in divider are also available. These taps are at the fourth, ninth, fourteenth and nineteenth bits of the divider. Therefore, if the primary oscillator output is running at the nominal 8 MHz, the user has access to an 8 MHz clock, plus any two of 500 kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-voltage devices). These frequencies can vary by as much as -50% or +25%. These signals can be accessed by placing the OSC4 library element in a schematic or in HDL code (see Figure 25). The oscillator is automatically disabled after conguration if the OSC4 symbol is not used in the design.

Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals.

Five interconnect types are distinguished by the relative length of their segments: single-length lines, double-length lines, quad and octal lines (XC4000X only), and longlines. In the XC4000X, direct connects allow fast data ow between adjacent CLBs, and between IOBs and CLBs. Extra routing is included in the IOB pad ring. The XC4000X also includes a ring of octal interconnect lines near the IOBs to improve pin-swapping and routing to locked pins. XC4000E/X devices include two types of global buffers. These global buffers have different properties, and are intended for different purposes. They are discussed in detail later in this section.

Programmable Interconnect
All internal connections are composed of metal segments with programmable switching points and switching matrices to implement the desired routing. A structured, hierarchical matrix of routing resources is provided to achieve efcient automated routing. The XC4000E and XC4000X share a basic interconnect structure. XC4000X devices, however, have additional routing not available in the XC4000E. The extra routing resources allow high utilization in high-capacity devices. All XC4000X-specic routing resources are clearly identied throughout this section. Any resources not identied as XC4000X-specic are present in all XC4000 Series devices. This section describes the varied routing resources available in XC4000 Series devices. The implementation software automatically assigns the appropriate resources based on the density and timing requirements of the design.

CLB Routing Connections

A high-level diagram of the routing resources associated with one CLB is shown in Figure 26. The shaded arrows represent routing present only in XC4000X devices. Table 15 shows how much routing of each type is available in XC4000E and XC4000X CLB arrays. Clearly, very large designs, or designs with a great deal of interconnect, will route more easily in the XC4000X. Smaller XC4000E designs, typically requiring signicantly less interconnect, do not require the additional routing. Figure 28 on page 4-31 is a detailed diagram of both the XC4000E and the XC4000X CLB, with associated routing. The shaded square is the programmable switch matrix, present in both the XC4000E and the XC4000X. The Lshaped shaded area is present only in XC4000X devices. As shown in the gure, the XC4000X block is essentially an XC4000E block with additional routing. CLB inputs and outputs are distributed on all four sides, providing maximum routing exibility. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algorithms. Inputs, outputs, and function generators can freely swap positions within a CLB to avoid routing congestion during the placement and routing operation.

Interconnect Overview
There are several types of interconnect. CLB routing is associated with each row and column of the CLB array. IOB routing forms a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the internal logic blocks.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Quad Single Double Long

CLB

Direct Connect

Long

Quad

Long

Global Clock

Long

Double Single

Global Clock

Carry Direct Chain Connect x5994

Figure 26: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)

Table 15: Routing per CLB in XC4000 Series Devices

es e bl gl

Singles Doubles Quads Longlines Direct Connects Globals Carry Logic Total

XC4000E XC4000X Vertical Horizontal Vertical Horizontal 8 8 8 8 4 4 4 4 0 0 12 12 6 6 10 6 0 0 2 2 4 2 24 0 0 18 8 1 45 0 0 32

ou

in

Double

Singles Six Pass Transistors Per Switch Matrix Interconnect Point

Double

ou

bl

X6600

Figure 27: Programmable Switch Matrix (PSM)

Programmable Switch Matrices

The horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each switch matrix consists of programmable pass transistors used to establish connections between the lines (see Figure 27). For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a double-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix.

Single-Length Lines
Single-length lines provide the greatest interconnect exibility and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associated with each CLB. These lines connect the switching matrices that are located in every row and a column of CLBs. Single-length lines are connected by way of the programmable switch matrices, as shown in Figure 29. Routing connectivity is shown in Figure 28. Single-length lines incur a delay whenever they go through a switching matrix. Therefore, they are not suitable for routing signals for long distances. They are normally used to conduct signals within a localized area and to provide the branching for nets with fanout greater than one.

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QUAD

DOUBLE

SINGLE

DOUBLE LONG

F4 C4 G4

YQ Y

DIRECT

G1 C1 F1

CLB
K X XQ

G3 C3 F3

FEEDBACK

F2 C2 G2

LONG

Q U AD

LO N G

G LO BA L

LO D N OU G BL E

SI N G LE

LO D O N U G BL E

G D IR LO EC BA T L

FE ED BA C K

Common to XC4000E and XC4000X XC4000X only Programmable Switch Matrix

Figure 28: Detail of Programmable Interconnect Associated with XC4000 Series CLB

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XC4000E and XC4000X Series Field Programmable Gate Arrays

CLB

CLB

CLB

Doubles PSM PSM Singles Doubles

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

PSM

PSM

CLB

CLB

CLB
X6601

CLB

CLB

CLB

Figure 29: Single- and Double-Length Lines, with Programmable Switch Matrices (PSMs)

X9014

Figure 30: Quad Lines (XC4000X only) and up to two independent outputs. Only one of the independent inputs can be buffered. The place and route software automatically uses the timing requirements of the design to determine whether or not a quad line signal should be buffered. A heavily loaded signal is typically buffered, while a lightly loaded one is not. One scenario is to alternate buffers and pass transistors. This allows both vertical and horizontal quad lines to be buffered at alternating buffered switch matrices. Due to the buffered switch matrices, quad lines are very fast. They provide the fastest available method of routing heavily loaded signals for long distances across the device.

Double-Length Lines
The double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two CLBs before entering a switch matrix. Doublelength lines are grouped in pairs with the switch matrices staggered, so that each line goes through a switch matrix at every other row or column of CLBs (see Figure 29). There are four vertical and four horizontal double-length lines associated with each CLB. These lines provide faster signal routing over intermediate distances, while retaining routing exibility. Double-length lines are connected by way of the programmable switch matrices. Routing connectivity is shown in Figure 28.

Quad Lines (XC4000X only)

XC4000X devices also include twelve vertical and twelve horizontal quad lines per CLB row and column. Quad lines are four times as long as the single-length lines. They are interconnected via buffered switch matrices (shown as diamonds in Figure 28 on page 4-31). Quad lines run past four CLBs before entering a buffered switch matrix. They are grouped in fours, with the buffered switch matrices staggered, so that each line goes through a buffered switch matrix at every fourth CLB location in that row or column. (See Figure 30.) The buffered switch matrixes have four pins, one on each edge. All of the pins are bidirectional. Any pin can drive any or all of the other pins. Each buffered switch matrix contains one buffer and six pass transistors. It resembles the programmable switch matrix shown in Figure 27, with the addition of a programmable buffer. There can be up to two independent inputs

Longlines
Longlines form a grid of metal interconnect segments that run the entire length or width of the array. Longlines are intended for high fan-out, time-critical signal nets, or nets that are distributed over long distances. In XC4000X devices, quad lines are preferred for critical nets, because the buffered switch matrices make them faster for high fanout nets. Two horizontal longlines per CLB can be driven by 3-state or open-drain drivers (TBUFs). They can therefore implement unidirectional or bidirectional buses, wide multiplexers, or wired-AND functions. (See Three-State Buffers on page 4-27 for more details.) Each horizontal longline driven by TBUFs has either two (XC4000E) or eight (XC4000X) pull-up resistors. To activate these resistors, attach a PULLUP symbol to the longline net. The software automatically activates the appropriate number of pull-ups. There is also a weak keeper at each end of these two horizontal longlines. This circuit pre-

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vents undened oating levels. However, it is overridden by any driver, even a pull-up resistor. Each XC4000E longline has a programmable splitter switch at its center, as does each XC4000X longline driven by TBUFs. This switch can separate the line into two independent routing channels, each running half the width or height of the array. Each XC4000X longline not driven by TBUFs has a buffered programmable splitter switch at the 1/4, 1/2, and 3/4 points of the array. Due to the buffering, XC4000X longline performance does not deteriorate with the larger array sizes. If the longline is split, the resulting partial longlines are independent. Routing connectivity of the longlines is shown in Figure 28 on page 4-31.

I/O Routing
XC4000 Series devices have additional routing around the IOB ring. This routing is called a VersaRing. The VersaRing facilitates pin-swapping and redesign without affecting board layout. Included are eight double-length lines spanning two CLBs (four IOBs), and four longlines. Global lines and Wide Edge Decoder lines are provided. XC4000X devices also include eight octal lines. A high-level diagram of the VersaRing is shown in Figure 32. The shaded arrows represent routing present only in XC4000X devices. Figure 34 on page 4-35 is a detailed diagram of the XC4000E and XC4000X VersaRing. The area shown includes two IOBs. There are two IOBs per CLB row or column, therefore this diagram corresponds to the CLB routing diagram shown in Figure 28 on page 4-31. The shaded areas represent routing and routing connections present only in XC4000X devices.

Direct Interconnect (XC4000X only)

The XC4000X offers two direct, efcient and fast connections between adjacent CLBs. These nets facilitate a data ow from the left to the right side of the device, or from the top to the bottom, as shown in Figure 31. Signals routed on the direct interconnect exhibit minimum interconnect propagation delay and use no general routing resources. The direct interconnect is also present between CLBs and adjacent IOBs. Each IOB on the left and top device edges has a direct path to the nearest CLB. Each CLB on the right and bottom edges of the array has a direct path to the nearest two IOBs, since there are two IOBs for each row or column of CLBs. The place and route software uses direct interconnect whenever possible, to maximize routing resources and minimize interconnect delays.

Octal I/O Routing (XC4000X only)

Between the XC4000X CLB array and the pad ring, eight interconnect tracks provide for versatility in pin assignment and xed pinout exibility. (See Figure 33 on page 4-34.) These routing tracks are called octals, because they can be broken every eight CLBs (sixteen IOBs) by a programmable buffer that also functions as a splitter switch. The buffers are staggered, so each line goes through a buffer at every eighth CLB location around the device edge. The octal lines bend around the corners of the device. The lines cross at the corners in such a way that the segment most recently buffered before the turn has the farthest distance to travel before the next buffer, as shown in Figure 33.

IOB

IOB

IOB

IOB

IOB

IOB

~ ~ ~ ~

IOB

IOB

CLB
IOB

CLB

CLB
IOB

IOB

CLB
IOB

CLB

Figure 31: XC4000X Direct Interconnect

March 30, 1998 (Version 1.5)

~ ~ ~ ~
IOB

~ ~ ~ ~ ~ ~ ~ ~
IOB IOB

~ ~ ~ ~
IOB IOB

CLB
IOB

IOB

IOB
X6603

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XC4000E and XC4000X Series Field Programmable Gate Arrays

IOB

WED Quad WED Single Double

INTERCONNECT
Long Direct Connect

IOB
WED

Long

Direct Connect

Edge Double Long Global Octal Decode Clock

X5995

Figure 32: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge) WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000X only)

IOB

IOB

IOB

IOB

Segment with nearest buffer connects to segment with furthest buffer

X9015

Figure 33: XC4000X Octal I/O Routing

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QUAD

T O
DOUBLE

SINGLE

C L B A R R A Y

DOUBLE LONG

DECODER

IOB
I1 IK OK T I2 CE O

DIRECT

DECODER

IOB
T OK O CE I2 IK I1

DECODER

LONG
L BA LO G E E G OD ED EC D G N LO

Figure 34: Detail of Programmable Interconnect Associated with XC4000 Series IOB (Left Edge)

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E BL U O D

L TA C O

Common to XC4000E and XC4000X XC4000X only

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XC4000E and XC4000X Series Field Programmable Gate Arrays

IOB inputs and outputs interface with the octal lines via the single-length interconnect lines. Single-length lines are also used for communication between the octals and double-length lines, quads, and longlines within the CLB array. Segmentation into buffered octals was found to be optimal for distributing signals over long distances around the device.

Two different types of clock buffers are available in the XC4000E: Primary Global Buffers (BUFGP) Secondary Global Buffers (BUFGS)

Global Nets and Buffers

Both the XC4000E and the XC4000X have dedicated global networks. These networks are designed to distribute clocks and other high fanout control signals throughout the devices with minimal skew. The global buffers are described in detail in the following sections. The text descriptions and diagrams are summarized in Table 16. The table shows which CLB and IOB clock pins can be sourced by which global buffers. In both XC4000E and XC4000X devices, placement of a library symbol called BUFG results in the software choosing the appropriate clock buffer, based on the timing requirements of the design. The detailed information in these sections is included only for reference.

Four Primary Global buffers offer the shortest delay and negligible skew. Four Secondary Global buffers have slightly longer delay and slightly more skew due to potentially heavier loading, but offer greater exibility when used to drive non-clock CLB inputs. The Primary Global buffers must be driven by the semidedicated pads. The Secondary Global buffers can be sourced by either semi-dedicated pads or internal nets. Each CLB column has four dedicated vertical Global lines. Each of these lines can be accessed by one particular Primary Global buffer, or by any of the Secondary Global buffers, as shown in Figure 35. Each corner of the device has one Primary buffer and one Secondary buffer. IOBs along the left and right edges have four vertical global longlines. Top and bottom IOBs can be clocked from the global lines in the adjacent CLB column. A global buffer should be specied for all timing-sensitive global signal distribution. To use a global buffer, place a BUFGP (primary buffer), BUFGS (secondary buffer), or BUFG (either primary or secondary buffer) element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=L attribute or property to a BUFGS symbol to direct that a buffer be placed in one of the two Secondary Global buffers on the left edge of the device, or a LOC=BL to indicate the Secondary Global buffer on the bottom edge of the device, on the left.

Global Nets and Buffers (XC4000E only)

Four vertical longlines in each CLB column are driven exclusively by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. The four global lines can be driven by either of two types of global buffers. The clock pins of every CLB and IOB can also be sourced from local interconnect.

Table 16: Clock Pin Access XC4000E BUFGP All CLBs in Quadrant All CLBs in Device IOBs on Adjacent Vertical Half Edge IOBs on Adjacent Vertical Full Edge IOBs on Adjacent Horizontal Half Edge (Direct) IOBs on Adjacent Horizontal Half Edge (through CLB globals) IOBs on Adjacent Horizontal Full Edge (through CLB globals)
L = Left, R = Right, T = Top, B = Bottom

BUFGS

BUFGLS

XC4000X L&R BUFGE

T&B BUFGE

Local Interconnect

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March 30, 1998 (Version 1.5)

IOB

IOB

IOB

IOB

locals

locals

locals

BUFGS PGCK1 SGCK1

locals

BUFGP SGCK4 PGCK4

4 BUFGP 4 IOB locals X4 locals IOB Any BUFGS One BUFGP per Global Line locals BUFGS CLB CLB locals CLB CLB

4 BUFGS locals 4

IOB Any BUFGS One BUFGP per Global Line locals BUFGP locals X4 locals IOB

X4

X4

PGCK2 locals locals locals BUFGP locals SGCK2 BUFGS

SGCK3 PGCK3

IOB

IOB

IOB

IOB

X6604

Figure 35: XC4000E Global Net Distribution

BUFGLS

IOB

IOB

IOB

IOB

BUFGLS

GCK1

GCK8 BUFGE BUFGE

GCK7

GCK6

locals

locals

locals

BUFGLS

locals

BUFGE

BUFGE

BUFGLS

CLB

CLB

X4
BUFGLS 8

BUFGLS 8

X8

X8 8

BUFGLS

X8 8 BUFGLS 8

locals
4 8 8
CLB CLOCKS (PER COLUMN)

locals

locals

locals

IOB

locals

IOB CLOCKS

CLB CLOCKS (PER COLUMN)

IOB CLOCKS

IOB

locals

locals
IOB IOB CLOCKS CLB CLOCKS (PER COLUMN) CLB CLOCKS (PER COLUMN) IOB CLOCKS

locals
IOB

8 8

locals
BUFGLS 8

locals
8 BUFGLS X8

locals
X4
BUFGLS 8

locals
8 BUFGLS X8
CLB CLB

X8

locals

locals

locals

BUFGLS

locals

BUFGE BUFGE

BUFGE BUFGE GCK4

BUFGLS

GCK2

GCK3 BUFGLS BUFGLS

GCK5 X9018

IOB

IOB

IOB

IOB

Figure 36: XC4000X Global Net Distribution

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Global Nets and Buffers (XC4000X only)

Eight vertical longlines in each CLB column are driven by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. The global lines are broken in the center of the array, to allow faster distribution and to minimize skew across the whole array. Each half-column global line has its own buffered multiplexer, as shown in Figure 36. The top and bottom global lines cannot be connected across the center of the device, as this connection might introduce unacceptable skew. The top and bottom halves of the global lines must be separately driven although they can be driven by the same global buffer. The eight global lines in each CLB column can be driven by either of two types of global buffers. They can also be driven by internal logic, because they can be accessed by single, double, and quad lines at the top, bottom, half, and quarter points. Consequently, the number of different clocks that can be used simultaneously in an XC4000X device is very large. There are four global lines feeding the IOBs at the left edge of the device. IOBs along the right edge have eight global lines. There is a single global line along the top and bottom edges with access to the IOBs. All IOB global lines are broken at the center. They cannot be connected across the center of the device, as this connection might introduce unacceptable skew. IOB global lines can be driven from two types of global buffers, or from local interconnect. Alternatively, top and bottom IOBs can be clocked from the global lines in the adjacent CLB column. Two different types of clock buffers are available in the XC4000X: Global Low-Skew Buffers (BUFGLS) Global Early Buffers (BUFGE)

Choosing an XC4000X Clock Buffer The clocking structure of the XC4000X provides a large variety of features. However, it can be simple to use, without understanding all the details. The software automatically handles clocks, along with all other routing, when the appropriate clock buffer is placed in the design. In fact, if a buffer symbol called BUFG is placed, rather than a specic type of buffer, the software even chooses the buffer most appropriate for the design. The detailed information in this section is provided for those users who want a ner level of control over their designs. If ne control is desired, use the following summary and Table 16 on page 4-36 to choose an appropriate clock buffer. The simplest thing to do is to use a Global Low-Skew buffer. If a faster clock path is needed, try a BUFG. The software will rst try to use a Global Low-Skew Buffer. If timing requirements are not met, a faster buffer will automatically be used. If a single quadrant of the chip is sufcient for the clocked logic, and the timing requires a faster clock than the Global Low-Skew buffer, use a Global Early buffer.

Global Low-Skew Buffers Each corner of the XC4000X device has two Global LowSkew buffers. Any of the eight Global Low-Skew buffers can drive any of the eight vertical Global lines in a column of CLBs. In addition, any of the buffers can drive any of the four vertical lines accessing the IOBs on the left edge of the device, and any of the eight vertical lines accessing the IOBs on the right edge of the device. (See Figure 37 on page 4-39.) IOBs at the top and bottom edges of the device are accessed through the vertical Global lines in the CLB array, as in the XC4000E. Any Global Low-Skew buffer can, therefore, access every IOB and CLB in the device. The Global Low-Skew buffers can be driven by either semidedicated pads or internal logic. To use a Global Low-Skew buffer, instantiate a BUFGLS element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=T attribute or property to direct that a BUFGLS be placed in one of the two Global Low-Skew buffers on the top edge of the device, or a LOC=TR to indicate the Global Low-Skew buffer on the top edge of the device, on the right.

Global Low-Skew Buffers are the standard clock buffers. They should be used for most internal clocking, whenever a large portion of the device must be driven. Global Early Buffers are designed to provide a faster clock access, but CLB access is limited to one-fourth of the device. They also facilitate a faster I/O interface. Figure 36 is a conceptual diagram of the global net structure in the XC4000X. Global Early buffers and Global Low-Skew buffers share a single pad. Therefore, the same IPAD symbol can drive one buffer of each type, in parallel. This conguration is particularly useful when using the Fast Capture latches, as described in IOB Input Signals on page 4-21. Paired Global Early and Global Low-Skew buffers share a common input; they cannot be driven by two different signals.

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March 30, 1998 (Version 1.5)

8
IOB IOB

7 6
1
I O B

8
IOB IOB

7 6 CLB CLB
I O B

1
I O B

CLB

CLB

I O B

I O B

CLB

CLB

I O B

I O B

CLB

CLB

I O B

2 3

IOB

IOB

5 4
X6753

2 3

IOB

IOB

5 4
X6751

Figure 37: Any BUFGLS (GCK1 - GCK8) Can Drive Any or All Clock Inputs on the Device Global Early Buffers Each corner of the XC4000X device has two Global Early buffers. The primary purpose of the Global Early buffers is to provide an earlier clock access than the potentially heavily-loaded Global Low-Skew buffers. A clock source applied to both buffers will result in the Global Early clock edge occurring several nanoseconds earlier than the Global Low-Skew buffer clock edge, due to the lighter loading. Global Early buffers also facilitate the fast capture of device inputs, using the Fast Capture latches described in IOB Input Signals on page 4-21. For Fast Capture, take a single clock signal, and route it through both a Global Early buffer and a Global Low-Skew buffer. (The two buffers share an input pad.) Use the Global Early buffer to clock the Fast Capture latch, and the Global Low-Skew buffer to clock the normal input ip-op or latch, as shown in Figure 18 on page 4-24. The Global Early buffers can also be used to provide a fast Clock-to-Out on device output pins. However, an early clock in the output ip-op IOB must be taken into consideration when calculating the internal clock speed for the design. The Global Early buffers at the left and right edges of the chip have slightly different capabilities than the ones at the top and bottom. Refer to Figure 38, Figure 39, and Figure 36 on page 4-37 while reading the following explanation. Each Global Early buffer can access the eight vertical Global lines for all CLBs in the quadrant. Therefore, only onefourth of the CLB clock pins can be accessed. This restriction is in large part responsible for the faster speed of the buffers, relative to the Global Low-Skew buffers.

Figure 38: Left and Right BUFGEs Can Drive Any or All Clock Inputs in Same Quadrant or Edge (GCK1 is shown. GCK2, GCK5 and GCK6 are similar.) The left-side Global Early buffers can each drive two of the four vertical lines accessing the IOBs on the entire left edge of the device. The right-side Global Early buffers can each drive two of the eight vertical lines accessing the IOBs on the entire right edge of the device. (See Figure 38.) Each left and right Global Early buffer can also drive half of the IOBs along either the top or bottom edge of the device, using a dedicated line that can only be accessed through the Global Early buffers. The top and bottom Global Early buffers can drive half of the IOBs along either the left or right edge of the device, as shown in Figure 39. They can only access the top and bottom IOBs via the CLB global lines.

8
IOB IOB

7 6

1
I O B

CLB

CLB

I O B

I O B

CLB

CLB

I O B

2 3

IOB

IOB

5 4
X6747

Figure 39: Top and Bottom BUFGEs Can Drive Any or All Clock Inputs in Same Quadrant (GCK8 is shown. GCK3, GCK4 and GCK7 are similar.)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

The top and bottom Global Early buffers are about 1 ns slower clock to out than the left and right Global Early buffers. The Global Early buffers can be driven by either semi-dedicated pads or internal logic. They share pads with the Global Low-Skew buffers, so a single net can drive both global buffers, as described above. To use a Global Early buffer, place a BUFGE element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=T attribute or property to direct that a BUFGE be placed in one of the two Global Early buffers on the top edge of the device, or a LOC=TR to indicate the Global Early buffer on the top edge of the device, on the right.
Vcc

GND Ground and Vcc Ring for I/O Drivers

Vcc

Logic Power Grid

GND

X5422

Power Distribution
Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated Vcc and Ground ring surrounding the logic array provides power to the I/O drivers, as shown in Figure 40. An independent matrix of Vcc and Ground lines supplies the interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically, a 0.1 F capacitor connected between each Vcc pin and the boards Ground plane will provide adequate decoupling. Output buffers capable of driving/sinking the specied 12 mA loads under specied worst-case conditions may be capable of driving/sinking up to 10 times as much current under best case conditions. Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direction. It may also be benecial to locate heavily loaded output buffers near the Ground pads. The I/O Block output buffers have a slew-rate limited mode (default) which should be used where output rise and fall times are not speed-critical.

Figure 40: XC4000 Series Power Distribution

Pin Descriptions
There are three types of pins in the XC4000 Series devices: Permanently dedicated pins User I/O pins that can have special functions Unrestricted user-programmable I/O pins.

Before and during conguration, all outputs not used for the conguration process are 3-stated with a 50 k - 100 k pull-up resistor. After conguration, if an IOB is unused it is congured as an input with a 50 k - 100 k pull-up resistor. XC4000 Series devices have no dedicated Reset input. Any user I/O can be congured to drive the Global Set/ Reset net, GSR. See Global Set/Reset on page 4-11 for more information on GSR. XC4000 Series devices have no Powerdown control input, as the XC3000 and XC2000 families do. The XC3000/ XC2000 Powerdown control also 3-stated all of the device I/O pins. For XC4000 Series devices, use the global 3-state net, GTS, instead. This net 3-states all outputs, but does not place the device in low-power mode. See IOB Output Signals on page 4-24 for more information on GTS. Device pins for XC4000 Series devices are described in Table 17. Pin functions during conguration for each of the seven conguration modes are summarized in Table 23 on page 4-59, in the Conguration Timing section.

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March 30, 1998 (Version 1.5)

Table 17: Pin Descriptions I/O I/O During After Pin Name Cong. Cong. Permanently Dedicated Pins VCC I I

Pin Description

Eight or more (depending on package) connections to the nominal +5 V supply voltage (+3.3 V for low-voltage devices). All must be connected, and each must be decoupled with a 0.01 - 0.1 F capacitor to Ground. Eight or more (depending on package type) connections to Ground. All must be conGND I I nected. During configuration, Configuration Clock (CCLK) is an output in Master modes or Asynchronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheral mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the CCLK I or O I Readback Clock. There is no CCLK High or Low time restriction on XC4000 Series devices, except during Readback. See Violating the Maximum High and Low Time Specification for the Readback Clock on page 4-57 for an explanation of this exception. DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a Low level on DONE DONE I/O O can be configured to delay the global logic initialization and the enabling of outputs. The optional pull-up resistor is selected as an option in the XACTstep program that creates the configuration bitstream. The resistor is included by default. PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA finishes the current clear cycle and executes another complete clear cycle, before it PROGRAM I I goes into a WAIT state and releases INIT. The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled up to Vcc. User I/O Pins That Can Have Special Functions During Peripheral mode configuration, this pin indicates when it is appropriate to write another byte of data into the FPGA. The same status is also available on D7 in AsynRDY/BUSY O I/O chronous Peripheral mode, if a read operation is performed when the device is selected. After configuration, RDY/BUSY is a user-programmable I/O pin. RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High. During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for XC4000X) is preceded by a rising edge on RCLK, a redundant output signal. RCLK is RCLK O I/O useful for clocked PROMs. It is rarely used during configuration. After configuration, RCLK is a user-programmable I/O pin. As Mode inputs, these pins are sampled after INIT goes High to determine the configuration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1 can be used as a 3-state output. These three pins have no associated input or output registers. I (M0), During configuration, these pins have weak pull-up resistors. For the most popular conM0, M1, M2 I O (M1), figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three I (M2) mode inputs can be individually configured with or without weak pull-up or pull-down resistors. A pull-down resistor value of 4.7 k is recommended. These pins can only be used as inputs or outputs when called out by special schematic definitions. To use these pins, place the library components MD0, MD1, and MD2 instead of the usual pad symbols. Input or output buffers must still be used. If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used, this pin is a 3-state output without a register, after configuration is completed. TDO O O This pin can be user output only when called out by special schematic definitions. To use this pin, place the library component TDO instead of the usual pad symbol. An output buffer must still be used.

March 30, 1998 (Version 1.5)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 17: Pin Descriptions (Continued) I/O I/O During After Cong. Cong.

Pin Name

TDI, TCK, TMS

I/O or I (JTAG)

HDC

I/O

LDC

I/O

INIT

I/O

I/O

PGCK1 PGCK4 (XC4000E only)

Weak Pull-up

I or I/O

SGCK1 SGCK4 (XC4000E only)

Weak Pull-up

I or I/O

GCK1 GCK8 (XC4000X only)

Weak Pull-up

I or I/O

CS0, CS1, WS, RS

I/O

A0 - A17

I/O

Pin Description If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. If the BSCAN symbol is not placed in the design, all boundary scan functions are inhibited once configuration is completed, and these pins become user-programmable I/O. In this case, they must be called out by special schematic definitions. To use these pins, place the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used. High During Configuration (HDC) is driven High until the I/O go active. It is available as a control output indicating that configuration is not yet completed. After configuration, HDC is a user-programmable I/O pin. Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a control output indicating that configuration is not yet completed. After configuration, LDC is a user-programmable I/O pin. Before and during configuration, INIT is a bidirectional signal. A 1 k - 10 k external pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used to hold the FPGA in the internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an additional 30 to 300 s after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O go active, INIT is a user-programmable I/O pin. Four Primary Global inputs each drive a dedicated internal global net with short delay and minimal skew. If not used to drive a global buffer, any of these pins is a user-programmable I/O. The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol connected directly to the input of a BUFGP symbol is automatically placed on one of these pins. Four Secondary Global inputs each drive a dedicated internal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If not used to drive a global net, any of these pins is a user-programmable I/O pin. The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol is automatically placed on one of these pins. Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Global Early buffer. Each pair of global buffers can also be driven from internal logic, but must share an input signal. If not used to drive a global buffer, any of these pins is a user-programmable I/O. Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol is automatically placed on one of these pins. These four inputs are used in Asynchronous Peripheral mode. The chip is selected when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe (WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low on Read Strobe (RS) changes D7 into a status output High if Ready, Low if Busy and drives D0 - D6 High. In Express mode, CS1 is used as a serial-enable signal for daisy-chaining. WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write Strobe overrides. After configuration, these are user-programmable I/O pins. During Master Parallel configuration, these 18 output pins address the configuration EPROM. After configuration, they are user-programmable I/O pins.

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March 30, 1998 (Version 1.5)

Table 17: Pin Descriptions (Continued) I/O I/O During After Cong. Cong.

Pin Description During Master Parallel configuration with an XC4000X master, these 4 output pins add O I/O 4 more bits to address the configuration EPROM. After configuration, they are user-programmable I/O pins. (See Master Parallel Configuration section for additional details.) During Master Parallel and Peripheral configuration, these eight input pins receive conD0 - D7 I I/O figuration data. After configuration, they are user-programmable I/O pins. During Slave Serial or Master Serial configuration, DIN is the serial configuration data DIN I I/O input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is the D0 input. After configuration, DIN is a user-programmable I/O pin. During configuration in any mode but Express mode, DOUT is the serial configuration data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the DOUT O I/O DIN input. In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices. After configuration, DOUT is a user-programmable I/O pin. Unrestricted User-Programmable I/O Pins These pins can be configured to be input and/or output after configuration is completed. Weak I/O I/O Before configuration is completed, these pins have an internal high-value pull-up resisPull-up tor (25 k - 100 k) that defines the logic level as High.

Pin Name A18 - A21 (XC4000X only)

Boundary Scan
The bed of nails has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technology and multi-layer boards. The IEEE Boundary Scan Standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for I/O and internal logic. This structure is easily implemented with a four-pin interface on any boundary scan-compatible IC. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two. The XC4000 Series implements IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE and EXTEST boundary scan instructions. When the boundary scan conguration option is selected, three normal user I/O pins become dedicated inputs for these functions. Another user output pin becomes the dedicated boundary scan output. The details of how to enable this circuitry are covered later in this section. By exercising these input signals, the user can serially load commands and data into these devices to control the driving of their outputs and to examine their inputs. This method is an improvement over bed-of-nails testing. It avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fth pin,

a reset for the control logic, is described in the standard but is not implemented in Xilinx devices. The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state machine, an instruction register and a number of data registers. The functional details can be found in the IEEE 1149.1 specication and are also discussed in the Xilinx application note XAPP 017: Boundary Scan in XC4000 Devices. Figure 41 on page 4-44 shows a simplied block diagram of the XC4000E Input/Output Block with boundary scan implemented. XC4000X boundary scan logic is identical. Figure 42 on page 4-45 is a diagram of the XC4000 Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. XC4000 Series devices can also be congured through the boundary scan logic. See Readback on page 4-56.

Data Registers
The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-State Control. Non-IOB pins have appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures all In, Out, and 3-state pins. The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is 4-43

March 30, 1998 (Version 1.5)

XC4000E and XC4000X Series Field Programmable Gate Arrays

always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals. The other standard data register is the single ip-op BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA provides two additional data registers that can be specied using the BSCAN macro. The FPGA provides

two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions. For these instructions, two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE).

EXTEST TS INV TS/OE Boundary Scan OUTPUT INVERT OUTPUT M sd Ouput Data O M Ouput Clock OK rd M M S/R INVERT M OUT SEL D EC Q TS - capture TS - update M

SLEW RATE

PULL DOWN

PULL UP

3-State TS

VCC

PAD

Clock Enable

Boundary Scan

O - capture Q - capture O - update

I - capture Boundary Scan I - update sd D DELAY M FLIP-FLOP/LATCH Input Clock IK M INPUT S/R rd EC M INVERT QL Q M M M M Input Data 2 I2

Input Data 1 I1

GLOBAL S/R

X5792

Figure 41: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown). XC4000X Boundary Scan Logic is Identical.

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March 30, 1998 (Version 1.5)

DATA IN IOB.T 1 0 IOB IOB IOB IOB IOB D Q D sd Q 0 1

LE

IOB

IOB

1 0

sd D Q D Q

IOB

IOB LE

IOB

IOB IOB.I 1 0 1 sd D Q D Q

IOB

IOB

IOB

IOB

IOB

IOB

LE 1 IOB.Q IOB.T 0

IOB

BYPASS REGISTER INSTRUCTION REGISTER

IOB

TDI

M TDO U X

0 1 0 D Q D sd Q 1

LE

1 0 D Q D

sd Q

LE

1 IOB.I 0

DATAOUT SHIFT/ CLOCK DATA CAPTURE REGISTER

UPDATE

EXTEST

X9016

Figure 42: XC4000 Series Boundary Scan Logic

Instruction Set
The XC4000 Series boundary scan instruction set also includes instructions to congure the device and read back the conguration data. The instruction set is coded as shown in Table 18.

Including Boundary Scan in a Schematic

If boundary scan is only to be used during conguration, no special schematic elements need be included in the schematic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user functions after conguration. To indicate that boundary scan remain enabled after conguration, place the BSCAN library symbol and connect the TDI, TMS, TCK and TDO pad symbols to the appropriate pins, as shown in Figure 44. Even if the boundary scan symbol is used in a schematic, the input pins TMS, TCK, and TDI can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDI and TCK.

Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The input-only M0 and M2 mode pins contribute only the In bit to the boundary scan I/O data register, while the outputonly M1 pin contributes all three bits. The rst two bits in the I/O data register are TDO.T and TDO.O, which can be used for the capture of internal signals. The nal bit is BSCANT.UPD, which can be used to drive an internal net. These locations are primarily used by Xilinx for internal testing. From a cavity-up view of the chip (as shown in XDE or Epic), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Figure 43. The device-specic pinout tables for the XC4000 Series include the boundary scan locations for each IOB pin. BSDL (Boundary Scan Description Language) les for XC4000 Series devices are available on the Xilinx FTP site. March 30, 1998 (Version 1.5)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 18: Boundary Scan Instructions Instruction I2 I1 I0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 Test TDO Source Selected EXTEST DR SAMPLE/ DR PRELOAD USER 1 BSCAN. TDO1 USER 2 BSCAN. TDO2 READBACK Readback Data CONFIGURE DOUT Reserved BYPASS Bypass Register I/O Data Source DR Pin/Logic User Logic User Logic Pin/Logic Disabled

Optional IBUF BSCAN TDI TMS TCK From User Logic

TDI TMS TCK TDO1 TDO2 TDO DRCK IDLE SEL1 SEL2

To User Logic

TDO

To User Logic

X2675

Figure 44: Boundary Scan Schematic Example

Conguration
Conguration is the process of loading design-specic programming data into one or more FPGAs to dene the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. XC4000 Series devices use several hundred bits of conguration data per CLB and its associated interconnects. Each conguration bit denes the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The XACTstep development system translates the design into a netlist le. It automatically partitions, places and routes the logic and generates the conguration data in PROM format.

Bit 0 ( TDO end) Bit 1 Bit 2

TDO.T TDO.O Top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom) MD1.T MD1.O MD1.I MD0.I MD2.I Bottom-edge IOBs (Left to Right)

Special Purpose Pins

Three conguration mode pins (M2, M1, M0) are sampled prior to conguration to determine the conguration mode. After conguration, these pins can be used as auxiliary connections. M2 and M0 can be used as inputs, and M1 can be used as an output. The XACTstep development system does not use these resources unless they are explicitly specied in the design entry. This is done by placing a special pad symbol called MD2, MD1, or MD0 instead of the input or output pad symbol. In XC4000 Series devices, the mode pins have weak pullup resistors during conguration. With all three mode pins High, Slave Serial mode is selected, which is the most popular conguration mode. Therefore, for the most common conguration mode, the mode pins can be left unconnected. (Note, however, that the internal pull-up resistor value can be as high as 100 k.) After conguration, these pins can individually have weak pull-up or pull-down resistors, as specied in the design. A pull-down resistor value of 4.7 k is recommended. These pins are located in the lower left chip corner and are near the readback nets. This location allows convenient routing if compatibility with the XC2000 and XC3000 family conventions of M0/RT, M1/RD is desired.

Right-edge IOBs (Bottom to Top) (TDI end) B SCANT.UPD

X6075

Figure 43:

Boundary Scan Bit Sequence

Avoiding Inadvertent Boundary Scan

If TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant during conguration. In some applications, a situation may occur where TMS or TCK is driven during conguration. This may cause the device to go into boundary scan mode and disrupt the conguration process. To prevent activation of boundary scan during conguration, do either of the following: TMS: Tie High to put the Test Access Port controller in a benign RESET state TCK: Tie High or Lowdon't toggle this clock input.

For more information regarding boundary scan, refer to the Xilinx Application Note XAPP 017.001, Boundary Scan in XC4000E Devices.

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Conguration Modes
XC4000E devices have six conguration modes. XC4000X devices have the same six modes, plus an additional conguration mode. These modes are selected by a 3-bit input code applied to the M2, M1, and M0 inputs. There are three self-loading Master modes, two Peripheral modes, and a Serial Slave mode, which is used primarily for daisychained devices. The coding for mode selection is shown in Table 19. Table 19: Conguration Modes Mode Master Serial Slave Serial Master Parallel Up Master Parallel Down Peripheral Synchronous* Peripheral Asynchronous Reserved Reserved
Note:

Additional Address lines in XC4000 devices

The XC4000X devices have additional address lines (A18A21) allowing the additional address space required to daisy-chain several large devices. The extra address lines are programmable in XC4000EX devices. By default these address lines are not activated. In the default mode, the devices are compatible with existing XC4000 and XC4000E products. If desired, the extra address lines can be used by specifying the address lines option in bitgen as 22 (bitgen -g AddressLines:22). The lines (A18-A21) are driven when a master device detects, via the bitstream, that it should be using all 22 address lines. Because these pins will initially be pulled high by internal pull-ups, designers using Master Parallel Up mode should use external pull down resistors on pins A18-A21. If Master Parallel Down mode is used external resistors are not necessary. All 22 address lines are always active in Master Parallel modes with XC4000XL devices. The additional address lines behave identically to the lower order address lines. If the Address Lines option in bitgen is set to 18, it will be ignored by the XC4000XL device. The additional address lines (A18-A21) are not available in the PC84 package.

M2 0 1 1

M1 0 1 0

M0 0 1 0

CCLK output input output

output

0 1 0 0

1 0 1 0

1 1 0 1

input output

Data Bit-Serial Bit-Serial Byte-Wide, increment from 00000 Byte-Wide, decrement from 3FFFF Byte-Wide Byte-Wide

Peripheral Modes
The two Peripheral modes accept byte-wide data from a bus. A RDY/BUSY status is available as a handshake signal. In Asynchronous Peripheral mode, the internal oscillator generates a CCLK burst signal that serializes the bytewide data. CCLK can also drive slave devices. In the synchronous mode, an externally supplied clock input to CCLK serializes the data.

* Peripheral Synchronous can be considered bytewide Slave Parallel

A detailed description of each conguration mode, with timing information, is included later in this data sheet. During conguration, some of the I/O pins are used temporarily for the conguration process. All pins used during conguration are shown in Table 23 on page 4-59.

Master Modes
The three Master modes use an internal oscillator to generate a Conguration Clock (CCLK) for driving potential slave devices. They also generate address and timing for external PROM(s) containing the conguration data. Master Parallel (Up or Down) modes generate the CCLK signal and PROM addresses and receive byte parallel data. The data is internally serialized into the FPGA dataframe format. The up and down selection generates starting addresses at either zero or 3FFFF (3FFFFF when 22 address lines are used), for compatibility with different microprocessor addressing conventions. The Master Serial mode generates CCLK and receives the conguration data in serial form from a Xilinx serial-conguration PROM. CCLK speed is selectable as either 1 MHz (default) or 8 MHz. Conguration always starts at the default slow frequency, then can switch to the higher frequency during the rst frame. Frequency tolerance is -50% to +25%.

Slave Serial Mode

In Slave Serial mode, the FPGA receives serial conguration data on the rising edge of CCLK and, after loading its conguration, passes additional data out, resynchronized on the next falling edge of CCLK. Multiple slave devices with identical congurations can be wired with parallel DIN inputs. In this way, multiple devices can be congured simultaneously. Serial Daisy Chain Multiple devices with different congurations can be connected together in a daisy chain, and a single combined bitstream used to congure the chain of slave devices. To congure a daisy chain of devices, wire the CCLK pins of all devices in parallel, as shown in Figure 52 on page 4-61. Connect the DOUT of each device to the DIN of the next. The lead or master FPGA and following slaves each passes resynchronized conguration data coming from a single source. The header data, including the length count,

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XC4000E and XC4000X Series Field Programmable Gate Arrays

is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames. After an FPGA has received its conguration data, it passes on any additional frame start bits and conguration data on DOUT. When the total number of conguration clocks applied after memory initialization equals the value of the 24-bit length count, the FPGAs begin the start-up sequence and become operational together. FPGA I/O are normally released two CCLK cycles after the last conguration bit is received. Figure 48 on page 4-54 shows the startup timing for an XC4000 Series device. The daisy-chained bitstream is not simply a concatenation of the individual bitstreams. The PROM le formatter must be used to combine the bitstreams for a daisy-chained conguration. Multi-Family Daisy Chain All Xilinx FPGAs of the XC2000, XC3000, and XC4000 Series use a compatible bitstream format and can, therefore, be connected in a daisy chain in an arbitrary sequence. There is, however, one limitation. The lead device must belong to the highest family in the chain. If the chain contains XC4000 Series devices, the master normally cannot be an XC2000 or XC3000 device. The reason for this rule is shown in Figure 48 on page 4-54. Since all devices in the chain store the same length count value and generate or receive one common sequence of CCLK pulses, they all recognize length-count match on the same CCLK edge, as indicated on the left edge of Figure 48. The master device then generates additional CCLK pulses until it reaches its nish point F. The different families generate or require different numbers of additional CCLK pulses until they reach F. Not reaching F means that the device does not really nish its conguration, although DONE may have gone High, the outputs became active, and the internal reset was released. For the XC4000 Series device, not reaching F means that readback cannot be ini-

tiated and most boundary scan instructions cannot be used. The user has some control over the relative timing of these events and can, therefore, make sure that they occur at the proper time and the nish point F is reached. Timing is controlled using options in the bitstream generation software. XC3000 Master with an XC4000 Series Slave Some designers want to use an inexpensive lead device in peripheral mode and have the more precious I/O pins of the XC4000 Series devices all available for user I/O. Figure 45 provides a solution for that case. This solution requires one CLB, one IOB and pin, and an internal oscillator with a frequency of up to 5 MHz as a clock source. The XC3000 master device must be congured with late Internal Reset, which is the default option. One CLB and one IOB in the lead XC3000-family device are used to generate the additional CCLK pulse required by the XC4000 Series devices. When the lead device removes the internal RESET signal, the 2-bit shift register responds to its clock input and generates an active Low output signal for the duration of the subsequent clock period. An external connection between this output and CCLK thus creates the extra CCLK pulse.

OE/T Reset 0 0 1 0 1 1 0 1 0 1 . etc .

Output Connected to CCLK

Active Low Output Active High Output

X5223

Figure 45: CCLK Generation for XC3000 Master Driving an XC4000 Series Slave

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March 30, 1998 (Version 1.5)

Setting CCLK Frequency

For Master modes, CCLK can be generated in either of two frequencies. In the default slow mode, the frequency ranges from 0.5 MHz to 1.25 MHz for XC4000E and XC4000EX devices and from 0.6 MHz to 1.8 MHz for XC4000XL devices. In fast CCLK mode, the frequency ranges from 4 MHz to 10 MHz for XC4000EX devices and from 5 MHz to 15 MHz for XC4000XL devices. The frequency is selected by an option when running the bitstream generation software. If an XC4000 Series Master is driving an XC3000- or XC2000-family slave, slow CCLK mode must be used. In addition, an XC4000XL device driving a XC4000E or XC4000EX should use slow mode. Slow mode is the default. Table 20: XC4000 Series Data Stream Formats Data Type Fill Byte Preamble Code Length Count Fill Bits Start Field Data Frame CRC or Constant Field Check Extend Write Cycle Postamble Start-Up Bytes LEGEND: Unshaded Light Dark Once per bitstream Once per data frame Once per device All Other Modes (D0...) 11111111b 0010b COUNT(23:0) 1111b 0b DATA(n-1:0) xxxx (CRC) or 0110b 01111111b xxh

Data Stream Format

The data stream (bitstream) format is identical for all conguration modes. The data stream formats are shown in Table 20. Bit-serial data is read from left to right, and byte-parallel data is effectively assembled from this serial bitstream, with the rst bit in each byte assigned to D0. The conguration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator eld of ones. This header is followed by the actual conguration data in frames. The length and number of frames depends on the device type (see Table 21 and Table 22). Each frame begins with a start eld and ends with an error check. A postamble code is required to signal the end of data for a single device. In all cases, additional start-up bytes of data are required to provide four clocks for the startup sequence at the end of conguration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are dont-cares; these bytes are not included in bitstreams created by the Xilinx software. A selection of CRC or non-CRC error checking is allowed by the bitstream generation software. The non-CRC error checking tests for a designated end-of-frame eld for each frame. For CRC error checking, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each frame. The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master modes, CCLK and address signals continue to operate externally. The user must detect INIT and initialize a new conguration by pulsing the PROGRAM pin Low or cycling Vcc.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 21: XC4000E Program Data Device Max Logic Gates CLBs (Row x Col.) IOBs Flip-Flops Bits per Frame Frames Program Data PROM Size (bits) XC4003E 3,000 100 (10 x 10) 80 360 126 428 53,936 53,984 XC4005E 5,000 196 (14 x 14) 112 616 166 572 94,960 95,008 XC4006E 6,000 256 (16 x 16) 128 768 186 644 119,792 119,840 XC4008E 8,000 324 (18 x 18) 144 936 206 716 147,504 147,552 XC4010E 10,000 400 (20 x 20) 160 1,120 226 788 178,096 178,144 XC4013E 13,000 576 (24 x 24) 192 1,536 266 932 247,920 247,968 XC4020E 20,000 784 (28 x 28) 224 2,016 306 1,076 329,264 329,312 XC4025E 25,000 1,024 (32 x 32) 256 2,560 346 1,220 422,128 422,176

Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits PROM Size = Program Data + 40 (header) + 8 2. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header.

Table 22: XC4000EX/XL Program Data Device Max Logic Gates CLBs (Row x Column) IOBs Flip-Flops Bits per Frame Frames Program Data PROM Size (bits) XC4005 5,000 196 (14 x 14) 112 616 205 741 151,910 151,960 XC4010 10,000 400 (20 x 20) 160 1,120 277 1,023 283,376 283,424 XC4013 13,000 576 (24 x 24) 192 1,536 325 1,211 393,580 393,632 XC4020 20,000 784 (28 x 28) 224 2,016 373 1,399 521,832 521,880 XC4028 28,000 1,024 (32 x 32) 256 2,560 421 1,587 668,132 668,184 XC4036 36,000 1,296 (36 x 36) 288 3,168 469 1,775 832,480 832,528 XC4044 44,000 1,600 (40 x 40) 320 3,840 517 1,963 1,014,876 1,014,928 XC4052 52,000 1,936 (44 x 44) 352 4,576 565 2,151 1,215,320 1,215,368 XC4062 62,000 2,304 (48 x 48) 384 5,376 613 2,339 1,433,812 1,433,864 XC4085 85,000 3,136 (56 x 56) 448 7,168 709 2,715 1,924,940 1,924,992

Notes: 1. Bits per frame = (12 x number of rows) + 8 for the top + 16 for the bottom + 8 + 1 start bit + 4 error check bits. Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4. Program data = (bits per frame x number of frames) + 5 postamble bits. PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte. 2. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header.t

Cyclic Redundancy Check (CRC) for Conguration and Readback

The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial bitstream. The result of this calculation is tagged onto the data stream as additional check bits. The receiving system

performs an identical calculation on the bitstream and compares the result with the received checksum. Each data frame of the conguration bitstream has four error bits at the end, as shown in Table 20. If a frame data error is detected during the loading of the FPGA, the conguration process with a potentially corrupted bitstream is terminated. The FPGA pulls the INIT pin Low and goes into a Wait state.

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March 30, 1998 (Version 1.5)

During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is computed using the CRC-16 CCITT polynomial, as shown in Figure 46. The checksum consists of the 11 most signicant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLB outputs should not be included (Read Capture option not used), and if RAM is present, the RAM content must be unchanged. Statistically, one error out of 2048 might go undetected.

Boundary Scan Instructions Available:

VCC >3.5 V Yes

No

Test M0 Generate One Time-Out Pulse of 16 or 64 ms

PROGRAM = Low Yes

Keep Clearing Configuration Memory

Conguration Sequence
There are four major steps in the XC4000 Series power-up conguration sequence. Conguration Memory Clear Initialization Conguration Start-Up

EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory CONFIGURE* Once More (* if PROGRAM = High)

~1.3 s per Frame

INIT High? if Master Yes

No

Master Waits 50 to 250 s Before Sampling Mode Lines

The full process is illustrated in Figure 47.

Sample Mode Lines Master CCLK Goes Active Load One Configuration Data Frame LDC Output = L, HDC Output = H
X6076

Conguration Memory Clear

When power is rst applied or is reapplied to an FPGA, an internal circuit forces initialization of the conguration logic. When Vcc reaches an operational level, and the circuit passes the write and read test of a sample pair of conguration bits, a time delay is started. This time delay is nominally 16 ms, and up to 10% longer in the low-voltage devices. The delay is four times as long when in Master Modes (M0 Low), to allow ample time for all slaves to reach a stable Vcc. When all INIT pins are tied together, as recommended, the longest delay takes precedence. Therefore, devices with different time delays can easily be mixed and matched in a daisy chain. This delay is applied only on power-up. It is not applied when reconguring an FPGA by pulsing the PROGRAM pin
X2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X15 X16 15

Frame Error No SAMPLE/PRELOAD BYPASS Configuration memory Full Yes Pass Configuration Data to DOUT

Yes

Pull INIT Low and Stop

No

CCLK Count Equals Length Count Yes

No

SERIAL DATA IN

Polynomial: X16 + X15 + X2 + 1

F

Start-Up Sequence I/O Active

1 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 LAST DATA FRAME CRC CHECKSUM

EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK
START BIT

Operational

If Boundary Scan is Selected

Readback Data Stream

X1789

Figure 46: Circuit for Generating CRC-16 Figure 47: Power-up Conguration Sequence

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Low. During this time delay, or as long as the PROGRAM input is asserted, the conguration logic is held in a Conguration Memory Clear state. The conguration-memory frames are consecutively initialized, using the internal oscillator. At the end of each complete pass through the frame addressing, the power-on time-out delay circuitry and the level of the PROGRAM pin are tested. If neither is asserted, the logic initiates one additional clearing of the conguration frames and then tests the INIT input.

rise time is excessive or poorly dened. As long as PROGRAM is Low, the FPGA keeps clearing its conguration memory. When PROGRAM goes High, the conguration memory is cleared one more time, followed by the beginning of conguration, provided the INIT input is not externally held Low. Note that a Low on the PROGRAM input automatically forces a Low on the INIT output. The XC4000 Series PROGRAM pin has a permanent weak pull-up. Using an open-collector or open-drain driver to hold INIT Low before the beginning of conguration causes the FPGA to wait after completing the conguration memory clear operation. When INIT is no longer held Low externally, the device determines its conguration mode by capturing its mode pins, and is ready to start the conguration process. A master device waits up to an additional 250 s to make sure that any slaves in the optional daisy chain have seen that INIT is High.

Initialization
During initialization and conguration, user pins HDC, LDC, INIT and DONE provide status outputs for the system interface. The outputs LDC, INIT and DONE are held Low and HDC is held High starting at the initial application of power. The open drain INIT pin is released after the nal initialization pass through the frame addresses. There is a deliberate delay of 50 to 250 s (up to 10% longer for low-voltage devices) before a Master-mode device recognizes an inactive INIT. Two internal clocks after the INIT pin is recognized as High, the FPGA samples the three mode lines to determine the conguration mode. The appropriate interface lines become active and the conguration preamble and data can be loaded.Conguration The 0010 preamble code indicates that the following 24 bits represent the length count. The length count is the total number of conguration clocks needed to load the complete conguration data. (Four additional conguration clocks are required to complete the conguration process, as discussed below.) After the preamble and the length count have been passed through to all devices in the daisy chain, DOUT is held High to prevent frame start bits from reaching any daisy-chained devices. A specic conguration bit, early in the rst frame of a master device, controls the conguration-clock rate and can increase it by a factor of eight. Therefore, if a fast conguration clock is selected by the bitstream, the slower clock rate is used until this conguration bit is detected. Each frame has a start eld followed by the frame-conguration data bits and a frame error eld. If a frame data error is detected, the FPGA halts loading, and signals the error by pulling the open-drain INIT pin Low. After all conguration frames have been loaded into an FPGA, DOUT again follows the input data so that the remaining data is passed on to the next device.

Start-Up
Start-up is the transition from the conguration process to the intended user operation. This transition involves a change from one clock source to another, and a change from interfacing parallel or serial conguration data where most outputs are 3-stated, to normal operation with I/O pins active in the user-system. Start-up must make sure that the user-logic wakes up gracefully, that the outputs become active without causing contention with the conguration signals, and that the internal ip-ops are released from the global Reset or Set at the right time. Figure 48 describes start-up timing for the three Xilinx families in detail. The conguration modes can use any of the four timing sequences. To access the internal start-up signals, place the STARTUP library symbol. Start-up Timing Different FPGA families have different start-up sequences. The XC2000 family goes through a xed sequence. DONE goes High and the internal global Reset is de-activated one CCLK period after the I/O become active. The XC3000A family offers some exibility. DONE can be programmed to go High one CCLK period before or after the I/O become active. Independent of DONE, the internal global Reset is de-activated one CCLK period before or after the I/O become active. The XC4000 Series offers additional exibility. The three events DONE going High, the internal Set/Reset being de-activated, and the user I/O going active can all occur in any arbitrary sequence. Each of them can occur one CCLK period before or after, or simultaneous with, any of the others. This relative timing is selected by means of software options in the bitstream generation software.

Delaying Conguration After Power-Up

There are two methods of delaying conguration after power-up: put a logic Low on the PROGRAM input, or pull the bidirectional INIT pin Low, using an open-collector (open-drain) driver. (See Figure 47 on page 4-51.) A Low on the PROGRAM input is the more radical approach, and is recommended when the power-supply 4-52

March 30, 1998 (Version 1.5)

The default option, and the most practical one, is for DONE to go High rst, disconnecting the conguration data source and avoiding any contention when the I/Os become active one clock later. Reset/Set is then released another clock period later to make sure that user-operation starts from stable internal conditions. This is the most common sequence, shown with heavy lines in Figure 48, but the designer can modify it to meet particular requirements. Normally, the start-up sequence is controlled by the internal device oscillator output (CCLK), which is asynchronous to the system clock. XC4000 Series offers another start-up clocking option, UCLK_NOSYNC. The three events described above need not be triggered by CCLK. They can, as a conguration option, be triggered by a user clock. This means that the device can wake up in synchronism with the user system. When the UCLK_SYNC option is enabled, the user can externally hold the open-drain DONE output Low, and thus stall all further progress in the start-up sequence until DONE is released and has gone High. This option can be used to force synchronization of several FPGAs to a common user clock, or to guarantee that all devices are successfully congured before any I/Os go active. If either of these two options is selected, and no user clock is specied in the design or attached to the device, the chip could reach a point where the conguration of the device is complete and the Done pin is asserted, but the outputs do not become active. The solution is either to recreate the bitstream specifying the start-up clock as CCLK, or to supply the appropriate user clock. Start-up Sequence The Start-up sequence begins when the conguration memory is full, and the total number of conguration clocks

received since INIT went High equals the loaded value of the length count. The next rising clock edge sets a ip-op Q0, shown in Figure 49. Q0 is the leading bit of a 5-bit shift register. The outputs of this register can be programmed to control three events. The release of the open-drain DONE output The change of conguration-related pins to the user function, activating all IOBs. The termination of the global Set/Reset initialization of all CLB and IOB storage elements. The DONE pin can also be wire-ANDed with DONE pins of other FPGAs or with other external signals, and can then be used as input to bit Q3 of the start-up register. This is called Start-up Timing Synchronous to Done In and is selected by either CCLK_SYNC or UCLK_SYNC. When DONE is not used as an input, the operation is called Start-up Timing Not Synchronous to DONE In, and is selected by either CCLK_NOSYNC or UCLK_NOSYNC. As a conguration option, the start-up control register beyond Q0 can be clocked either by subsequent CCLK pulses or from an on-chip user net called STARTUP.CLK. These signals can be accessed by placing the STARTUP library symbol. Start-up from CCLK If CCLK is used to drive the start-up, Q0 through Q3 provide the timing. Heavy lines in Figure 48 show the default timing, which is compatible with XC2000 and XC3000 devices using early DONE and late Reset. The thin lines indicate all other possible timing options.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Length Count Match

CCLK Period

CCLK
F DONE

XC2000

I/O

Global Reset F F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing Global Reset F DONE C1 C2 C3 C4 I/O C2 GSR Active C2 DONE IN F DONE C1, C2 or C3 I/O C3 C4 C3 C4

XC3000

DONE I/O

XC4000E/X
CCLK_NOSYNC

XC4000E/X
CCLK_SYNC

Di
GSR Active

Di+1

Di

Di+1
F

DONE C1 U2 U3 U4 I/O U2 GSR Active U2 DONE IN F DONE C1 U2 I/O U3 U4 U3 U4

XC4000E/X
UCLK_NOSYNC

XC4000E/X
UCLK_SYNC

Di
GSR Active

Di+1

Di+2

Synchronization Uncertainty

Di

Di+1

Di+2

UCLK Period
X9024

Figure 48: Start-up Timing

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March 30, 1998 (Version 1.5)

Start-up from a User Clock (STARTUP.CLK) When, instead of CCLK, a user-supplied start-up clock is selected, Q1 is used to bridge the unknown phase relationship between CCLK and the user clock. This arbitration causes an unavoidable one-cycle uncertainty in the timing of the rest of the start-up sequence.

Release of User I/O After DONE Goes High

By default, the user I/O are released one CCLK cycle after the DONE pin goes High. If CCLK is not clocked after DONE goes High, the outputs remain in their initial state 3-stated, with a 50 k - 100 k pull-up. The delay from DONE High to active user I/O is controlled by an option to the bitstream generation software.

DONE Goes High to Signal End of Conguration

XC4000 Series devices read the expected length count from the bitstream and store it in an internal register. The length count varies according to the number of devices and the composition of the daisy chain. Each device also counts the number of CCLKs during conguration. Two conditions have to be met in order for the DONE pin to go high: the chip's internal memory must be full, and the conguration length count must be met, exactly.

Release of Global Set/Reset After DONE Goes High

By default, Global Set/Reset (GSR) is released two CCLK cycles after the DONE pin goes High. If CCLK is not clocked twice after DONE goes High, all ip-ops are held in their initial set or reset state. The delay from DONE High to GSR inactive is controlled by an option to the bitstream generation software.

Conguration Complete After DONE Goes High

Three full CCLK cycles are required after the DONE pin goes High, as shown in Figure 48 on page 4-54. If CCLK is not clocked three times after DONE goes High, readback cannot be initiated and most boundary scan instructions cannot be used.

This is important because the counter that determines when the length count is met begins with the very rst CCLK, not the rst one after the preamble. Therefore, if a stray bit is inserted before the preamble, or the data source is not ready at the time of the rst CCLK, the internal counter that holds the number of CCLKs will be one ahead of the actual number of data bits read. At the end of conguration, the conguration memory will be full, but the number of bits in the internal counter will not match the expected length count. As a consequence, a Master mode device will continue to send out CCLKs until the internal counter turns over to zero, and then reaches the correct length count a second time. This will take several seconds [224 CCLK period] which is sometimes interpreted as the device not conguring at all. If it is not possible to have the data ready at the time of the rst CCLK, the problem can be avoided by increasing the number in the length count by the appropriate value. The XACT User Guide includes detailed information about manually altering the length count. Note that DONE is an open-drain output and does not go High unless an internal pull-up is activated or an external pull-up is attached. The internal pull-up is activated as the default by the bitstream generation software.

Conguration Through the Boundary Scan Pins

XC4000 Series devices can be congured through the boundary scan pins. The basic procedure is as follows: Power up the FPGA with INIT held Low (or drive the PROGRAM pin Low for more than 300 ns followed by a High while holding INIT Low). Holding INIT Low allows enough time to issue the CONFIG command to the FPGA. The pin can be used as I/O after conguration if a resistor is used to hold INIT Low. Issue the CONFIG command to the TMS input Wait for INIT to go High Sequence the boundary scan Test Access Port to the SHIFT-DR state Toggle TCK to clock data into TDI pin.

The user must account for all TCK clock cycles after INIT goes High, as all of these cycles affect the Length Count compare. For more detailed information, refer to the Xilinx application note XAPP017, Boundary Scan in XC4000 Devices. This application note also applies to XC4000E and XC4000X devices.

March 30, 1998 (Version 1.5)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Q3 STARTUP Q2

Q1/Q4 DONE IN

* *
1 0 GSR ENABLE GSR INVERT STARTUP.GSR STARTUP.GTS GTS INVERT GTS ENABLE 0

IOBs OPERATIONAL PER CONFIGURATION

GLOBAL SET/RESET OF ALL CLB AND IOB FLIP-FLOP

CONTROLLED BY STARTUP SYMBOL IN THE USER SCHEMATIC (SEE LIBRARIES GUIDE)

GLOBAL 3-STATE OF ALL IOBs 1

*
1 0 1 0

DONE " FINISHED " ENABLES BOUNDARY SCAN, READBACK AND CONTROLS THE OSCILLATOR

Q0

Q1

Q2

Q3

Q4

FULL LENGTH COUNT

1 S Q D Q D Q 0 M K K K D Q D Q

CLEAR MEMORY CCLK STARTUP.CLK USER NET 0 1

*
Figure 49: Start-up Logic

CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"

X1528

Readback
The user can read back the content of conguration memory and the level of certain internal nodes without interfering with the normal operation of the device. Readback not only reports the downloaded conguration bits, but can also include the present state of the device, represented by the content of all ip-ops and latches in CLBs and IOBs, as well as the content of function generators used as RAMs. Note that in XC4000 Series devices, conguration data is not inverted with respect to conguration as it is in XC2000 and XC3000 families. XC4000 Series Readback does not use any dedicated pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be routed to any IOB. To access the internal Readback sig-

nals, place the READBACK library symbol and attach the appropriate pad symbols, as shown in Figure 50. After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress) output goes High on the next rising edge of RDBK.CLK. Subsequent rising edges of this clock shift out Readback data on the RDBK.DATA net. Readback data does not include the preamble, but starts with ve dummy bits (all High) followed by the Start bit (Low) of the rst frame. The rst two data bits of the rst frame are always High. Each frame ends with four error check bits. They are read back as High. The last seven bits of the last frame are also read back as High. An additional Start bit (Low) and an 11-bit Cyclic Redundancy Check (CRC) signature follow, before RDBK.RIP returns Low.

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March 30, 1998 (Version 1.5)

IF UNCONNECTED, DEFAULT IS CCLK

CLK MD0 READ_TRIGGER IBUF TRIG READBACK

DATA RIP OBUF

READ_DATA

MD1

X1786

Figure 50: Readback Schematic Example

Readback Options
Readback options are: Read Capture, Read Abort, and Clock Select. They are set with the bitstream generation software.
I/O PROGRAMMABLE INTERCONNECT I/O

When the Read Capture option is selected, the readback data stream includes sampled values of CLB and IOB signals. The rising edge of RDBK.TRIG latches the inverted values of the four CLB outputs, the IOB output ip-ops and the input signals I1 and I2. Note that while the bits describing conguration (interconnect, function generators, and RAM content) are not inverted, the CLB and IOB output signals are inverted. When the Read Capture option is not selected, the values of the capture bits reect the conguration data originally written to those memory locations. If the RAM capability of the CLBs is used, RAM data are available in readback, since they directly overwrite the F and G function-table conguration of the CLB. RDBK.TRIG is located in the lower-left corner of the device, as shown in Figure 51.

TRIG DATA RIP

Read Capture

rdbk

I/O

I/O

I/O

rdclk

X1787

Figure 51: READBACK Symbol in Graphical Editor

Violating the Maximum High and Low Time Specication for the Readback Clock
The readback clock has a maximum High and Low time specication. In some cases, this specication cannot be met. For example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. This necessitates stopping the clock, and thus violating the specication. The specication is mandatory only on clocking data at the end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the source of the maximum High and Low time requirements. Therefore, the specication only applies to the six clock cycles prior to and including any start bit, including the clocks before the rst start bit in the readback data stream. At other times, the frame data is already in the register and the register is not dynamic. Thus, it can be shifted out just like a regular shift register. The user must precisely calculate the location of the readback data relative to the frame. The system must keep track of the position within a data frame, and disable interrupts before frame boundaries. Frame lengths and data formats are listed in Table 20, Table 21 and Table 22.

Read Abort
When the Read Abort option is selected, a High-to-Low transition on RDBK.TRIG terminates the readback operation and prepares the logic to accept another trigger. After an aborted readback, additional clocks (up to one readback clock per conguration frame) may be required to re-initialize the control logic. The status of readback is indicated by the output control net RDBK.RIP. RDBK.RIP is High whenever a readback is in progress.

Clock Select
CCLK is the default clock. However, the user can insert another clock on RDBK.CLK. Readback control and data are clocked on rising edges of RDBK.CLK. If readback must be inhibited for security reasons, the readback control nets are simply not connected. RDBK.CLK is located in the lower right chip corner, as shown in Figure 51.

Readback with the XChecker Cable

The XChecker Universal Download/Readback Cable and Logic Probe uses the readback feature for bitstream verication. It can also display selected internal signals on the PC or workstation screen, functioning as a low-cost in-circuit emulator.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E/EX/XL Program Readback Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. The following guidelines reect worst-case values over the recommended operating conditions.

Finished Internal Net

rdbk.TRIG 1 TRTRC rdclk.I 4 TRCL TRCH 5 TRCRT 2 1 TRTRC TRCRT 2

rdbk.RIP TRCRR 6

rdbk.DATA

DUMMY TRCRD 7

DUMMY

VALID

VALID X1790

E/EX rdbk.TRIG rdclk.1 Description rdbk.TRIG setup to initiate and abort Readback rdbk.TRIG hold to initiate and abort Readback rdbk.DATA delay rdbk.RIP delay High time Low time 1 2 7 6 5 4 Symbol TRTRC TRCRT TRCRD TRCRR TRCH TRCL Min 200 50 250 250 Max 250 250 500 500 Units ns ns ns ns ns ns

Note 1: Note 2:

Timing parameters apply to all speed grades. If rdbk.TRIG is High prior to Finished, Finished will trigger the rst Readback.

XL rdbk.TRIG rdclk.1 Description rdbk.TRIG setup to initiate and abort Readback rdbk.TRIG hold to initiate and abort Readback rdbk.DATA delay rdbk.RIP delay High time Low time 1 2 7 6 5 4 Symbol TRTRC TRCRT TRCRD TRCRR TRCH TRCL Min 200 50 250 250 Max 250 250 500 500 Units ns ns ns ns ns ns

Note 1: Note 2:

Timing parameters apply to all speed grades. If rdbk.TRIG is High prior to Finished, Finished will trigger the rst Readback.

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March 30, 1998 (Version 1.5)

Table 23: Pin Functions During Conguration

SLAVE SERIAL <1:1:1> M2(HIGH) (I) M1(HIGH) (I) M0(HIGH) (I) HDC (HIGH) LDC (LOW) INIT DONE PROGRAM (I) CCLK (I) MASTER SERIAL <0:0:0> M2(LOW) (I) M1(LOW) (I) M0(LOW) (I) HDC (HIGH) LDC (LOW) INIT DONE PROGRAM (I) CCLK (O) CONFIGURATION MODE <M2:M1:M0> SYNCH. ASYNCH. MASTER PERIPHERAL PERIPHERAL PARALLEL DOWN <0:1:1> <1:0:1> <1:1:0> M2(LOW) (I) M2(HIGH) (I) M2(HIGH) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M0(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) HDC (HIGH) HDC (HIGH) HDC (HIGH) LDC (LOW) LDC (LOW) LDC (LOW) INIT INIT INIT DONE DONE DONE PROGRAM (I) PROGRAM (I) PROGRAM (I) CCLK (I) CCLK (O) CCLK (O) RDY/BUSY (O) RDY/BUSY (O) RCLK (O) RS (I) CS0 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DOUT DOUT DOUT TDI TDI TDI TCK TCK TCK TMS TMS TMS TDO TDO TDO WS (I) A0 A1 CS1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18* A19* A20* A21* MASTER PARALLEL UP <1:0:0> M2(HIGH) (I) M1(LOW) (I) M0(LOW) (I) HDC (HIGH) LDC (LOW) INIT DONE PROGRAM (I) CCLK (O) RCLK (O)

USER OPERATION (I) (O) (I) I/O I/O I/O DONE PROGRAM CCLK (I) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SGCK4-GCK5-I/O TDI-I/O TCK-I/O TMS-I/O TDO-(O) I/O PGCK4-GCK6-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SGCK1-GCK7-I/O PGCK1-GCK8-I/O I/O I/O I/O I/O I/O ALL OTHERS

DIN (I) DOUT TDI TCK TMS TDO

DIN (I) DOUT TDI TCK TMS TDO

DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) DATA 0 (I) DOUT TDI TCK TMS TDO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18* A19* A20* A21*

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 24: Pin Functions During Conguration

SLAVE SERIAL <1:1:1> M2(HIGH) (I) M1(HIGH) (I) M0(HIGH) (I) HDC (HIGH) LDC (LOW) INIT DONE PROGRAM (I) CCLK (I) MASTER SERIAL <0:0:0> M2(LOW) (I) M1(LOW) (I) M0(LOW) (I) HDC (HIGH) LDC (LOW) INIT DONE PROGRAM (I) CCLK (O) CONFIGURATION MODE <M2:M1:M0> SYNCH. ASYNCH. MASTER PERIPHERAL PERIPHERAL PARALLEL DOWN <0:1:1> <1:0:1> <1:1:0> M2(LOW) (I) M2(HIGH) (I) M2(HIGH) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M0(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) HDC (HIGH) HDC (HIGH) HDC (HIGH) LDC (LOW) LDC (LOW) LDC (LOW) INIT INIT INIT DONE DONE DONE PROGRAM (I) PROGRAM (I) PROGRAM (I) CCLK (I) CCLK (O) CCLK (O) RDY/BUSY (O) RDY/BUSY (O) RCLK (O) RS (I) CS0 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DOUT DOUT DOUT TDI TDI TDI TCK TCK TCK TMS TMS TMS TDO TDO TDO WS (I) A0 A1 CS1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18* A19* A20* A21* MASTER PARALLEL UP <1:0:0> M2(HIGH) (I) M1(LOW) (I) M0(LOW) (I) HDC (HIGH) LDC (LOW) INIT DONE PROGRAM (I) CCLK (O) RCLK (O)

USER OPERATION (I) (O) (I) I/O I/O I/O DONE PROGRAM CCLK (I) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SGCK4-GCK5-I/O TDI-I/O TCK-I/O TMS-I/O TDO-(O) I/O PGCK4-GCK6-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SGCK1-GCK7-I/O PGCK1-GCK8-I/O I/O I/O I/O I/O I/O ALL OTHERS

DIN (I) DOUT TDI TCK TMS TDO

DIN (I) DOUT TDI TCK TMS TDO

DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) DATA 0 (I) DOUT TDI TCK TMS TDO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18* A19* A20* A21*

* XC4000X only Notes 1. A shaded table cell represents a 50 k - 100 k pull-up before and during conguration. 2. (I) represents an input; (O) represents an output. 3. INIT is an open-drain output during conguration.

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March 30, 1998 (Version 1.5)

Conguration Timing
The seven conguration modes are discussed in detail in this section. Timing specications are included.

There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. Figure 52 shows a full master/slave system. An XC4000 Series device in Slave Serial mode should be connected as shown in the third device from the left. Slave Serial mode is selected by a <111> on the mode pins (M2, M1, M0). Slave Serial is the default mode if the mode pins are left unconnected, as they have weak pull-up resistors during conguration.

Slave Serial Mode

In Slave Serial mode, an external signal drives the CCLK input of the FPGA. The serial conguration bitstream must be available at the DIN input of the lead FPGA a short setup time before each rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overows the lead deviceon its DOUT pin.
NOTE: M2, M1, M0 can be shorted to Ground if not used as I/O

NOTE: M2, M1, M0 can be shorted to VCC if not used as I/O

VCC
N/C

4.7 K

4.7 K

4.7 K M0 M1 M2 DIN DOUT

4.7 K

4.7 K

4.7 K

M0 M1 M2 DOUT

N/C

M0 M1 M2 DIN CCLK

PWRDN

DOUT

XC4000E/X

VCC
4.7 K

CCLK

MASTER SERIAL
CCLK DIN PROGRAM DONE LDC INIT

XC1700D
CLK DATA CE RESET/OE CEO VPP

+5 V

XC4000E/X, XC5200

XC3100A

SLAVE

SLAVE
PROGRAM DONE INIT RESET D/P INIT

(Low Reset Option Used)

PROGRAM

X9025

Figure 52: Master/Slave Serial Mode Circuit Diagram

DIN 1 TDCC CCLK

Bit n 2 TCCD

Bit n + 1 5 TCCL

4 TCCH DOUT (Output) Bit n - 1

3 TCCO Bit n
X5379

CCLK

Description DIN setup DIN hold DIN to DOUT High time Low time Frequency

1 2 3 4 5

Symbol TDCC TCCD TCCO TCCH TCCL FCC

Min 20 0 45 45

Max

30

10

Units ns ns ns ns ns MHz

Note:

Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

Figure 53: Slave Serial Mode Programming Switching Characteristics

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Master Serial Mode

In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. The next data bit is put on the SPROM data output, connected to the FPGA DIN pin. The lead FPGA accepts this data on the subsequent rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overows the lead deviceon its DOUT pin. There is an internal pipeline delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In the bitstream generation software, the user can specify Fast CongRate, which, starting several bits into the rst

frame, increases the CCLK frequency by a factor of eight. For actual timing values please refer to Conguration Switching Characteristics on page 4-69. Be sure that the serial PROM and slaves are fast enough to support this data rate. XC2000, XC3000/A, and XC3100A devices do not support the Fast CongRate option. The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is congured as user-I/O, but LDC is then restricted to be a permanently High user output after conguration. Using DONE can also avoid contention on DIN, provided the early DONE option is invoked. Figure 52 on page 4-61 shows a full master/slave system. The leftmost device is in Master Serial mode. Master Serial mode is selected by a <000> on the mode pins (M2, M1, M0).

CCLK (Output) 2 TCKDS 1 Serial Data In TDSCK n n+1 n+2

Serial DOUT (Output)

n3

n2

n1

n
X3223

CCLK

Description DIN setup DIN hold

1 2

Symbol TDSCK TCKDS

Min 20 0

Max

Units ns ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conguration by pulling PROGRAM Low until Vcc is valid. 2. Master Serial mode timing is based on testing in slave mode.

Figure 54: Master Serial Mode Programming Switching Characteristics

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March 30, 1998 (Version 1.5)

Master Parallel Modes

In the two Master Parallel modes, the lead FPGA directly addresses an industry-standard byte-wide EPROM, and accepts eight data bits just before incrementing or decrementing the address outputs. The eight data bits are serialized in the lead FPGA, which then presents the preamble dataand all data that overows the lead deviceon its DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data (and also changes the EPROM address) until the falling CCLK edge that makes the LSB (D0) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. The PROM address pins can be incremented or decremented, depending on the mode pin settings. This option allows the FPGA to share the PROM with a wide variety of microprocessors and microcontrollers. Some processors must boot from the bottom of memory (all zeros) while others must boot from the top. The FPGA is exible and can load its conguration bitstream from either end of the memory. Master Parallel Up mode is selected by a <100> on the mode pins (M2, M1, M0). The EPROM addresses start at 00000 and increment.

Master Parallel Down mode is selected by a <110> on the mode pins. The EPROM addresses start at 3FFFF and decrement.

Additional Address lines in XC4000 devices

The XC4000X devices have additional address lines (A18A21) allowing the additional address space required to daisy-chain several large devices. The extra address lines are programmable in XC4000EX devices. By default these address lines are not activated. In the default mode, the devices are compatible with existing XC4000 and XC4000E products. If desired, the extra address lines can be used by specifying the address lines option in bitgen as 22 (bitgen -g AddressLines:22). The lines (A18-A21) are driven when a master device detects, via the bitstream, that it should be using all 22 address lines. Because these pins will initially be pulled high by internal pull-ups, designers using Master Parallel Up mode should use external pull down resistors on pins A18-A21. If Master Parallel Down mode is used external resistors are not necessary. All 22 address lines are always active in Master Parallel modes with XC4000XL devices. The additional address lines behave identically to the lower order address lines. If the Address Lines option in bitgen is set to 18, it will be ignored by the XC4000XL device. The additional address lines (A18-A21) are not available in the PC84 package.

4.7K

HIGH or LOW

TO DIN OF OPTIONAL DAISY-CHAINED FPGAS N/C N/C TO CCLK OF OPTIONAL DAISY-CHAINED FPGAS

M0

M1

M2 CCLK

NOTE:M0 can be shorted to Ground if not used as I/O. VCC 4.7K

DOUT A17 A16 A15 A14 INIT A13 A12 A11 A10 PROGRAM D7 D6 D5 D4 D3 D2 D1 D0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DONE ... ... ... ... ... A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OE CE D7 D6 D5 D4 D3 D2 D1 D0 DONE INIT EPROM (8K x 8) (OR LARGER) USER CONTROL OF HIGHER ORDER PROM ADDRESS BITS CAN BE USED TO SELECT BETWEEN ALTERNATIVE CONFIGURATIONS M0 DIN M1 M2 DOUT

CCLK XC4000E/X SLAVE

PROGRAM

DATA BUS PROGRAM

X9026

Figure 55: Master Parallel Mode Circuit Diagram

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XC4000E and XC4000X Series Field Programmable Gate Arrays

A0-A17 (output)

Address for Byte n

Address for Byte n + 1 1 TRAC

D0-D7

Byte 2 TDRC 3 TRCD

RCLK (output) 7 CCLKs CCLK

CCLK (output)

DOUT (output)

D6 Byte n - 1

D7
X6078

RCLK

Description Delay to Address valid Data setup time Data hold time

1 2 3

Symbol TRAC TDRC TRCD

Min 0 60 0

Max 200

Units ns ns ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conguration by pulling PROGRAM Low until Vcc is valid. 2. The rst Data byte is loaded and CCLK starts at the end of the rst RCLK active cycle (rising edge).

This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than 500 ns. EPROM data output has no hold-time requirements. Figure 56: Master Parallel Mode Programming Switching Characteristics

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March 30, 1998 (Version 1.5)

Synchronous Peripheral Mode

Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The rst byte of parallel conguration data must be available at the Data inputs of the lead FPGA a short setup time before the rising CCLK edge. Subsequent data bytes are clocked in on every eighth consecutive rising CCLK edge. The same CCLK edge that accepts data, also causes the RDY/BUSY output to go High for one CCLK period. The pin name is a misnomer. In Synchronous Peripheral mode it is really an ACKNOWLEDGE signal. Synchronous operation does not require this response, but it is a meaningful signal for test purposes. Note that RDY/BUSY is pulled High with a high-impedance pullup prior to INIT going High.

The lead FPGA serializes the data and presents the preamble data (and all data that overows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In order to complete the serial shift operation, 10 additional CCLK rising edges are required after the last data byte has been loaded, plus one more CCLK cycle for each daisychained device. Synchronous Peripheral mode is selected by a <011> on the mode pins (M2, M1, M0).

NOTE: M2 can be shorted to Ground if not used as I/O

N/C 4.7 k N/C

M0 M1 CLOCK 8 D0-7 CCLK

M2 OPTIONAL DAISY-CHAINED FPGAs DOUT

M0 M1 CCLK

M2

DATA BUS

DIN

DOUT

VCC
4.7 k

XC4000E/X SYNCHRONOUS PERIPHERAL

XC4000E/X SLAVE

CONTROL SIGNALS 4.7 k PROGRAM

RDY/BUSY INIT DONE INIT DONE

PROGRAM

PROGRAM

X9027

Figure 57: Synchronous Peripheral Mode Circuit Diagram

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XC4000E and XC4000X Series Field Programmable Gate Arrays

CCLK

INIT
BYTE 0 BYTE 1

BYTE 0 OUT DOUT 0 1 2 3 4 5 6 7

BYTE 1 OUT 0 1

RDY/BUSY
X6096

CCLK

Description INIT (High) setup time D0 - D7 setup time D0 - D7 hold time CCLK High time CCLK Low time CCLK Frequency

Symbol TIC TDC TCD TCCH TCCL FCC

Min 5 60 0 50 60

Max

Units s ns ns ns ns MHz

Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the rst data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every eighth consecutive rising edge of CCLK. 2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does not require such a response. 3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal. 4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore, additional CCLK pulses are clearly required after the last byte has been loaded.

Figure 58: Synchronous Peripheral Mode Programming Switching Characteristics

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Asynchronous Peripheral Mode

Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CS0 being Low and RS and CS1 being High to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a double-buffered UART-like parallel-to-serial converter and is serially shifted into the internal logic. The lead FPGA presents the preamble data (and all data that overows the lead device) on its DOUT pin. The RDY/ BUSY output from the lead FPGA acts as a handshake signal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High again when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. A new write may be started immediately, as soon as the RDY/BUSY output has gone Low, acknowledging receipt of the previous data. Write may not be terminated until RDY/BUSY is High again for one CCLK period. Note that RDY/BUSY is pulled High with a high-impedance pullup prior to INIT going High. The length of the BUSY signal depends on the activity in the UART. If the shift register was empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered.
N/C
4.7 k

The READY/BUSY handshake can be ignored if the delay from any one Write to the end of the next Write is guaranteed to be longer than 10 CCLK periods.

Status Read
The logic AND condition of the CS0, CS1and RS inputs puts the device status on the Data bus. D7 High indicates Ready D7 Low indicates Busy D0 through D6 go unconditionally High

It is mandatory that the whole start-up sequence be started and completed by one byte-wide input. Otherwise, the pins used as Write Strobe or Chip Enable might become active outputs and interfere with the nal byte transfer. If this transfer does not occur, the start-up sequence is not completed all the way to the nish (point F in Figure 48 on page 4-54). In this case, at worst, the internal reset is not released. At best, Readback and Boundary Scan are inhibited. The length-count value, as generated by the XACTstep software, ensures that these problems never occur. Although RDY/BUSY is brought out as a separate signal, microprocessors can more easily read this information on one of the data lines. For this purpose, D7 represents the RDY/BUSY status when RS is Low, WS is High, and the two chip select lines are both active. Asynchronous Peripheral mode is selected by a <101> on the mode pins (M2, M1, M0).

N/C N/C

M0

M1

M2

M0

M1

M2

DATA BUS

D07

CCLK OPTIONAL DAISY-CHAINED FPGAs DOUT

CCLK

DIN

DOUT

VCC
ADDRESS BUS

ADDRESS DECODE LOGIC

CS0

4.7 k

4.7 k

XC4000E/X ASYNCHRONOUS PERIPHERAL

...

XC4000E/X SLAVE

CS1 RS WS

CONTROL SIGNALS

RDY/BUSY INIT DONE REPROGRAM

4.7 k

INIT DONE PROGRAM

PROGRAM

X9028

Figure 59:

Asynchronous Peripheral Mode Circuit Diagram

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Write to LCA WS/CS0

Read Status RS, CS0

RS, CS1

WS, CS1

TCA 2 3 TDC TCD 7

READY BUSY

4
D7

D0-D7

CCLK

TWTRB 4
RDY/BUSY

TBUSY

DOUT

Previous Byte D6

D7

D0

D1

D2
X6097

Write

RDY

Description Effective Write time (CS0, WS=Low; RS, CS1=High) DIN setup time DIN hold time RDY/BUSY delay after end of Write or Read RDY/BUSY active after beginning of Read RDY/BUSY Low output (Note 4)

1 2 3 4 7 6

Symbol TCA TDC TCD TWTRB

Min 100 60 0

Max

Units ns ns ns ns ns CCLK periods

60 60

TBUSY

Notes: 1. Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High. 2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing and the phase of the internal timing generator for CCLK. 3. CCLK and DOUT timing is tested in slave mode. 4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data.

This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write may not be terminated until RDY/BUSY has been High for one CCLK period. Figure 60: Asynchronous Peripheral Mode Programming Switching Characteristics

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Conguration Switching Characteristics

Vcc

T POR RE-PROGRAM >300 ns

PROGRAM T PI INIT T ICCK CCLK OUTPUT or INPUT <300 ns M0, M1, M2 (Required) X1532 I/O VALID DONE RESPONSE <300 ns TCCLK

Master Modes (XC4000E/EX)

Description Power-On Reset Program Latency CCLK (output) Delay CCLK (output) Period, slow CCLK (output) Period, fast M0 = High M0 = Low Symbol TPOR TPOR TPI TICCK TCCLK TCCLK Min 10 40 1 40 640 80 Max 40 130 4 250 2000 250 Units ms ms s per CLB column s ns ns

Master Modes (XC4000XL)

Description Power-On Reset Program Latency CCLK (output) Delay CCLK (output) Period, slow CCLK (output) Period, fast M0 = High M0 = Low Symbol TPOR TPOR TPI TICCK TCCLK TCCLK Min 10 40 1 40 540 67 Max 40 130 4 250 1600 200 Units ms ms s per CLB column s ns ns

Slave and Peripheral Modes(All)

Description Power-On Reset Program Latency CCLK (input) Delay (required) CCLK (input) Period (required) Symbol TPOR TPI TICCK TCCLK Min 10 1 4 100 Max 33 4 Units ms s per CLB column s ns

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL Switching Characteristics

Denition of Terms
In the following tables, some specications may be designated as Advance or Preliminary. These terms are dened as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production.

Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specications not identied as either Advance or Preliminary are to be considered nal.

All specications subject to change without notice.

Additional Specications
Except for pin-to-pin input and output parameters, the a.c. parameter delay specications included in this document are derived from measuring internal test patterns. All specications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. For design considerations requiring more detailed timing information, see the appropriate family a.c. supplements available on the Xilinx WEBLINX at http://www.xilinx.com.

Absolute Maximum Ratings

Symbol VCC VIN VTS VCCt TSTG TSOL TJ Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Longest Supply Voltage Rise Time from 1 V to 3V Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic packages Plastic packages Description -0.5 to 4.0 -0.5 to 5.5 -0.5 to 5.5 50 -65 to +150 +260 +150 +125 Units V V V ms C C C C

Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operating Conditions

Symbol Description Supply voltage relative to GND, TJ = 0 C to +85C Commercial VCC VIH VIL TIN Supply voltage relative to GND, TJ = -40C to +100C High-level input voltage Low-level input voltage Input signal transition time Industrial Min 3.0 3.0 50% of VCC 0 Max 3.6 3.6 5.5 30% of VCC 250 Unit s V V V V ns

Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Note 2: Input and output measurement threshold is ~50% of VCC.

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DC Characteristics Over Recommended Operating Conditions

Symbol VOH VOL VDR ICCO IL CIN IRPU IRPD IRLL
Note 1: Note 2:

Description High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL) High-level output voltage @ IOH = -500 A, (LVCMOS) Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1) Low-level output voltage @ IOL = 1500 A, (LVCMOS) Data Retention Supply Voltage (below which conguration data may be lost) Quiescent FPGA supply current (Note 2) Input or output leakage current Input capacitance (sample tested) BGA, SBGA, PQ, HQ, MQ packages PGA packages Pad pull-up (when selected) @ Vin = 0 V (sample tested) Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low

Min 2.4 90% VCC

Max

Units V V

0.4 10% VCC 2.5 5 -10 +10 10 16 0.02 0.02 0.3 0.25 0.15 2.0

V V V mA A pF pF mA mA mA

With up to 64 pins simultaneously sinking 12 mA. With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and oating.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade Description Symbol Device XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL From pad through Global Low Skew buffer, TGLS to any clock K -3 Max 2.7 3.2 3.6 4.0 4.4 4.8 5.3 5.7 6.3 7.2 1.9 2.2 2.4 2.6 2.8 3.1 3.5 4.0 4.9 5.8 -2 Max 2.3 2.8 3.1 3.5 3.8 4.2 4.6 5.0 5.4 6.2 1.8 1.9 2.1 2.2 2.4 2.7 3.0 3.5 4.3 5.1 -1 Max 2.0 2.4 2.7 3.0 3.3 3.6 4.0 4.5 4.7 5.7 1.7 1.7 1.8 2.1 2.1 2.3 2.6 3.0 3.7 4.7 -09 Max 1.9 2.3 2.6 2.9 3.2 3.5 3.9 4.4 4.6 5.5 1.6 1.7 1.7 2.0 2.0 2.2 2.4 3.0 3.4 4.3 Note 1
Note 1: Preliminary specication only.

Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

From pad through Global Early buffer, TGE to any IOB clockK. Values are for BUFGE #s 1, 2, 5 and 6. Add 1 - 2 ns for BUFGE #s 3, 4, 7 and 8 and for all CLB clock Ks driven from any of the 8 BUFGEs, or consult TRCE.

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XC4000XL CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XL devices and expressed in nanoseconds unless otherwise noted.
Speed Grade Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via SR/H0 via H to X/Y outputs C inputs via H1 via H to X/Y outputs C inputs via DIN/H2 via H to X/Y outputs C inputs via EC, DIN/H2 to YQ, XQ output (bypass) CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Carry Net Delay, COUT to CIN Sequential Delays Clock K to Flip-Flop outputs Q Clock K to Latch outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H Hold Time after Clock K F/G inputs F/G inputs via H C inputs via SR/H0 through H C inputs via H1 through H C inputs via DIN/H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Global Set/Reset Symbol TILO TIHO TITO THH0O THH1O THH2O TCBYP TOPCY TASCY TINCY TSUM TBYP TNET TCKO TCKLO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR TCH TCL TRPW TRIO TMRW TMRQ FTOG 1.1 2.2 2.0 1.9 2.0 0.9 1.0 0.6 2.3 3.4 0 0 0 0 0 0 0 0 3.0 3.0 3.0 3.7 19.8 166 Min -3 Max 1.6 2.7 2.9 2.5 2.4 2.5 1.5 2.7 3.3 2.0 2.8 0.26 0.32 2.1 2.1 1.0 1.9 1.7 1.6 1.7 0.8 0.9 0.5 2.1 3.0 0 0 0 0 0 0 0 0 2.8 2.8 2.8 3.2 17.3 179 Min -2 Max 1.5 2.4 2.6 2.2 2.1 2.2 1.3 2.3 2.9 1.8 2.6 0.23 0.28 1.9 1.9 0.9 1.7 1.6 1.4 1.6 0.7 0.8 0.5 1.9 2.7 0 0 0 0 0 0 0 0 2.5 2.5 2.5 2.8 15.0 200 Min -1 Max 1.3 2.2 2.2 2.0 1.9 2.0 1.1 2.0 2.5 1.5 2.4 0.20 0.25 1.6 1.6 0.8 1.6 1.4 1.2 1.4 0.6 0.7 0.4 1.7 2.5 0 0 0 0 0 0 0 0 2.3 2.3 2.3 2.7 14.0 217 Min

-09
Max 1.2 2.0 2.0 1.8 1.6 1.8 1.0 1.6 1.8 1.0 1.7 0.14 0.24 1.5 1.5

Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz

Minimum GSR Pulse Width Delay from GSR input to any Q

Toggle Frequency (MHz) (for export control) Note 1: Preliminary specication only.

See page13 for TRRI values per device.

Note 1

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted.

Single Port RAM

Write Operation

Speed Grade Size

-3 Min

-2 Max Min

-1 Max

-09 Units Min Max

Symbol Min Max

Address write cycle time (clock K period) 16x2 TWCS 32x1 TWCTS Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K Read Operation Address read cycle time Data Valid after address change (no Write Enable) Address setup time before clock K 16x2 TRC 32x1 TRCT 16x2 TILO 32x1 TIHO 16x2 TICK 32x1 TIHCK 16x2 TWPS 32x1 TWPTS 16x2 TASS 32x1 TASTS 16x2 TAHS 32x1 TAHTS 16x2 TDSS 32x1 TDSTS 16x2 TDHS 32x1 TDHTS 16x2 TWSS 32x1 TWSTS 16x2 TWHS 32x1 TWHTS 16x2 TWOS 32x1 TWOTS

9.0 9.0 4.5 4.5 2.2 2.2 0 0 2.0 2.5 0 0 2.0 1.8 0 0 6.8 8.1

8.4 8.4 4.2 4.2 2.0 2.0 0 0 1.9 2.3 0 0 1.8 1.7 0 0 6.3 7.5

7.7 7.7 3.9 3.9 1.7 1.7 0 0 1.7 2.1 0 0 1.6 1.5 0 0 5.8 6.9

7.4 7.4 3.7 3.7 1.7 1.7 0 0 1.7 2.1 0 0 1.6 1.5 0 0 5.8 6.9

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

4.5 6.5 1.6 2.7 1.3 2.3

3.1 5.5 1.5 2.4 1.1 2.0

2.6 3.8 1.3 2.2 1.0 1.8

2.6 3.8 1.2 2.0 0.8 1.6 Note 1

ns ns ns ns ns ns

Note 1: Preliminary specication only.

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XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted.

Dual Port RAM Write Operation

Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

Speed Grade Size Symbol Min

-3 Max Min

-2 Max

--1 Min

-09 Units

Max Min Max

16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1

TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS

9.0 4.5 2.5 0 2.5 0 1.8 0 7.8

8.4 4.2 2.0 0 2.3 0 1.7 0 7.3

7.7 3.9 1.7 0 2.0 0 1.6 0 6.7

7.4 3.7 1.7 0 2.0 0 1.6 0 6.7 Note 2

ns ns ns ns ns ns ns ns ns

Note 1: Timing for16 x1 RAM option is identical to16 x 2 RAM. Note 2: Preliminary specication only.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Timing

TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

TILO

TWOS OLD

DATA OUT

NEW
X6461

XC4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing

TWPDS WCLK (K) TWSDS WE TDSDS DATA IN TASDS ADDRESS TILO TWODS DATA OUT OLD NEW
X6474

TWHDS

TDHDS

TAHDS

TILO

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XC4000XL Pin-to-Pin Output Parameter Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.

XC4000XL Output Flip-Flop, Clock to Out

Speed Grade Description Symbol Device XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL All Devices Global Low Skew Clock to Output using OFF TICKOF -3 Max 7.7 8.3 8.6 9.0 9.4 9.8 10.3 10.7 11.3 12.2 6.9 7.2 7.4 7.6 7.8 8.1 8.5 9.0 9.9 10.8 3.0 -2 Max 6.7 7.2 7.5 7.9 8.2 8.5 9.0 9.3 9.7 10.5 6.1 6.2 6.4 6.5 6.7 7.0 7.3 7.8 8.6 9.4 2.5 -1 Max 5.8 6.2 6.5 6.8 7.1 7.4 7.8 8.3 8.5 9.5 5.5 5.5 5.6 5.9 5.9 6.1 6.4 6.8 7.5 8.5 2.0 -09 Max 5.4 5.8 6.1 6.4 6.7 7.0 7.4 7.9 8.1 9.0 5.1 5.2 5.2 5.5 5.5 5.7 5.9 6.5 6.9 7.8 1.7 Note 3 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Global Early Clock to Output using OFF TICKEOF Values are for BUFGE #s 3, 4, 7, and 8. Add 1.4 ns for BUFGE #s 1, 2, 5, and 6.

For output SLOW option add

OFF = Output Flip Flop

TSLOW

Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see graph below. Note 3: Preliminary specication only.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Capacitive Load Factor

Delta Delay (ns)
Figure 1 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specied output delay if the load capacitance is different than 50 pF. For example, if the actual load capacitance is 120 pF, add 2.5 ns to the specied delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specied output delay. Figure 1 is usable over the specied operating conditions of voltage and temperature and is independent of the output slew rate control.

3 2 1 0 -1 -2 0 20 40 60 80 100 120 140 Capacitance (pF)

X8257

Figure 1: Delay Factor at Various Capacitive Loads

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XC4000XL Pin-to-Pin Input Parameter Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.

XC4000XL Global Low Skew Clock, Set-Up and Hold

Description Input Setup and Hold Times Using Global Low Skew Clock and IFF No Delay Symbol Speed Grade Device -3 Min -2 Min -1 Min -09 Min Units

TPSN/TPHN

Partial Delay

TPSP/TPHP

Full Delay

TPSD/TPHD

XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL

1.2 / 2.6 1.2 / 3.0 1.2 / 3.2 1.2 / 3.7 1.2 / 4.4 1.2 / 5.5 1.2 / 5.8 1.2 / 7.1 1.2 / 7.0 1.2 / 9.4 10. 5 / 0.0 11.1 / 0.0 6.1 / 0.0 11.9 / 0.0 12.3 / 0.0 6.4 / 1.0 13.1 / 0.0 11.9 / 0.0 6.7 / 1.2 12.9 / 0.0

1.1 / 2.2 1.1 / 2.6 1.1 / 2.8 1.1 / 3.2 1.1 / 3.8 1.1 / 4.8 1.1 / 5.0 1.1 / 6.2 1.1 / 6.1 1.1 / 8.2 9.1 / 0.0 9.7 / 0.0 5.3 / 0.0 10.3 / 0.0 10.7 / 0.0 5.6 / 1.0 11.4 / 0.0 10.3 / 0.0 5.8 / 1.2 11.2 / 0.0

0.9 / 2.0 0.9 / 2.3 0.9 / 2.4 0.9 / 2.8 0.9 / 3.3 0.9 / 4.1 0.9 / 4.4 0.9 / 5.4 0.9 / 5.3 0.9 / 7.1 7.9 / 0.0 8.4 / 0.0 4.6 / 0.0 9.0 / 0.0 9.3 / 0.0 4.8 / 1.0 9.9 / 0.0 9.0 / 0.0 5.1 / 1.2 9.8 / 0.0 6.6 / 0.0 6.8 / 0.0 5.6 / 0.0 6.6 / 0.0 7.0 / 0.0 5.8 / 0.0 8.0 / 0.0 8.4 / 0.0 6.0 / 0.0 9.6 / 0.0

0.8 / 1.7 0.8 / 2.0 0.8 / 2.1 0.8 / 2.4 0.8 / 2.9 0.8 / 3.6 0.8 / 3.8 0.8 / 4.7 0.8 / 4.6 0.8 / 6.2 6.9 / 0.0 7.3 / 0.0 4.0 / 0.0 7.8 / 0.0 8.1 / 0.0 4.2 / 1.0 8.6 / 0.0 7.8 / 0.0 4.4 / 1.2 8.5 / 0.0 5.6 / 0.0 5.8 / 0.0 4.8 / 0.0 6.2 / 0.0 6.4 / 0.0 5.3 / 0.0 6.8 / 0.0 7.0 / 0.0 5.5 / 0.0 8.4 / 0.0 Note 3

8.8 / 0.0 7.6 / 0.0 9.0 / 0.0 7.8 / 0.0 6.4 / 0.0 6.0 / 0.0 8.8 / 0.0 7.6 / 0.0 9.3 / 0.0 8.1 / 0.0 6. 6 / 0.0 6.2 / 0.0 10.6 / 0.0 9.2 / 0.0 11.2 / 0.0 9.7 / 0.0 6.8 / 0.0 6.4 / 0.0 12.7 / 0.0 11.0 / 0.0

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

IFF = Input Flip-Flop or Latch

Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions. Note 2: * The XC4013XL, XC4036XL, and 4062XL have signicantly faster partial and full delay setup times than other devices. Note 3: Preliminary specication only.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Description Input Setup and Hold Times No Delay Global Early Clock and IFF Global Early Clock and FCL Symbol Speed Grade Device XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL -3 Min -2 Min -1 Min -09 Min

TPSEN/TPHEN TPFSEN/TPFHEN

1.2 / 4.1 1.2 / 4.4 1.2 / 4.7 1.2 / 4.6 1.2 / 5.3 1.2 / 6.7 1.2 / 6.5 1.2 / 6.7 1.2 / 8.4 1.2 / 8.7 8.4 / 0.0 10.3 / 0.0 5.4 / 0.0 9.8 / 0.0 12.7 / 0.0 6.4 / 0.8 13.8 / 0.0 14.5 / 0.0 8.4 / 1.5 14.5 / 0.0 10.8 / 0.0 10.3 / 0.0 10.0 / 0.0 12.0 / 0.0 12.6 / 0.0 12.2 / 0.0 13.8 / 0.0 14.1 / 0.0 13.1 / 0.0 17.9 / 0.0

1.1 / 3.6 1.1 / 3.8 1.1 / 4.1 1.1 / 4.0 1.1 / 4.6 1.1 / 5.8 1.1 / 5.7 1.1 / 5.8 1.1 / 7.3 1.1 / 7.5

0.9 / 3.1 0.9 / 3.3 0.9 / 3.6 0.9 / 3.5 0.9 / 4.0 0.9 / 5.1 0.9 / 4.9 0.9 / 5.1 0.9 / 6.3 0.9 / 6.6

0.8 / 2.7 0.8 / 2.9 0.8 / 3.1 0.8 / 3.0 0.8 / 3.5 0.8 / 4.4 0.8 / 4.3 0.8 / 4.4 0.8 / 5.5 0.8 / 5.7

Partial Delay Global Early Clock and IFF Global Early Clock and FCL

TPSEP/TPHEP TPFSEP/TPFHEP

7.9 / 0.0 7.4 / 0.0 7.2 / 0.0 9.0 / 0.0 7.8 / 0.0 7.4 / 0.0 4.9 / 0.0 4.4 / 0.0 4.3 / 0.0 9.3 / 0.0 8.8 / 0.0 8.5 / 0.0 11.0 / 0.0 9.6 / 0.0 9.3 / 0.0 5.9 / 0.8 5.4 / 0.8 5.0 / 0.8 12.0 / 0.0 10.4 / 0.0 10.2 / 0.0 12.7 / 0.0 11.0 / 0.0 10.7 / 0.0 7.9 / 1.5 7.4 / 1.5 6.8 / 1.5 12.7 / 0.0 11.0 / 0.0 10.8 / 0.0 9.4 / 0.0 8.2 / 0.0 7.1 / 0.0 9.0 / 0.0 7.8 / 0.0 6.8 / 0.0 8.7 / 0.0 7.6 / 0.0 6.6 / 0.0 10.4 / 0.0 9.1/ 0.0 7.9 / 0.0 11.0/ 0.0 9.5 / 0.0 8.3 / 0.0 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 12.0 / 0.0 10.5/ 0.0 9.1 / 0.0 12.3 / 0.0 10.7/ 0.0 9.3 / 0.0 11.4 / 0.0 9.9 / 0.0 8.6 / 0.0 15.6 / 0.0 13.6 / 0.0 11.8 / 0.0 Note 3

Full Delay Global Early Clock and IFF

TPSED/TPHED

IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch

Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. Note 2: * The XC4013XL, XC4036XL, and 4062XL have signicantly faster partial and full delay setup times than other devices. Note 3: Preliminary specication only.

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XC4000XL BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Description Input Setup and Hold Times No Delay Global Early Clock and IFF Global Early Clock and FCL Symbol Speed Grade Device XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL -3 Min -2 Min -1 Min -09 Min

TPSEN/TPHEN TPFSEN/TPFHEN

1.2 / 4.1 1.2 / 4.4 1.2 / 4.7 1.2 / 4.6 1.2 / 5.3 1.2 / 6.7 1.2 / 6.5 1.2 / 6.7 1.2 / 8.4 1.2 / 8.7 9.0 / 0.0 11.9 / 0.0 6.4 / 0.0 10.8 / 0.0 14.0 / 0.0 7.0 / 0.0 14.6 / 0.0 16.4 / 0.0 9.0 / 0.8 16.7 / 0.0 10.8 / 0.0 10.3 / 0.0 10.0 / 0.0 12.0 / 0.0 12.6 / 0.0 12.2 / 0.0 13.8 / 0.0 14.1 / 0.0 13.1 / 0.0 17.9 / 0.0

1.1 / 3.6 1.1 / 3.8 1.1 / 4.1 1.1 / 4.0 1.1 / 4.6 1.1 / 5.8 1.1 / 5.7 1.1 / 5.8 1.1 / 7.3 1.1 / 7.5 8.5 / 0.0 10.4 / 0.0 5.9 / 0.0 10.3 / 0.0 12.2 / 0.0 6.6 / 0.0 12.7 / 0.0 14.3 / 0.0 8.6 / 0.8 14.5 / 0.0

0.9 / 3.1 0.9 / 3.3 0.9 / 3.6 0.9 / 3.5 0.9 / 4.0 0.9 / 5.1 0.9 / 4.9 0.9 / 5.1 0.9 / 6.3 0.9 / 6.6

0.8 / 2.7 0.8 / 2.9 0.8 / 3.1 0.8 / 3.0 0.8 / 3.5 0.8 / 4.4 0.8 / 4.3 0.8 / 4.4 0.8 / 5.5 0.8 / 5.7

Partial Delay Global Early Clock and IFF Global Early Clock and FCL

TPSEP/TPHEP TPFSEP/TPFHEP

8.0 / 0.0 7.5 / 0.0 9.0 / 0.0 8.0 / 0.0 5.4 / 0.0 4.9 / 0.0 9.8 / 0.0 9.0 / 0.0 10.6 / 0.0 9.8 / 0.0 6.2 / 0.0 5.2 / 0.0 11.0 / 0.0 10.8 / 0.0 12.4 / 0.0 11.4 / 0.0 8.2 / 0.8 7.0 / 0.8 12.6 / 0.0 11.6 / 0.0

Full Delay Global Early Clock and IFF

TPSED/TPHED

IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch

9.4 / 0.0 8.2 / 0.0 7.1 / 0.0 9.0 / 0.0 7.8 / 0.0 6.8 / 0.0 8.7 / 0.0 7.6 / 0.0 6.6 / 0.0 10.4 / 0.0 9.1 / 0.0 7.9 / 0.0 11.0 / 0.0 9.5 / 0.0 8.3 / 0.0 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 12.0 / 0.0 10.5 / 0.0 9.1 / 0.0 12.3 / 0.0 10.7 / 0.0 9.3 / 0.0 11.4 / 0.0 9.9 / 0.0 8.6 / 0.0 15.6 / 0.0 13.6 / 0.0 11.8 / 0.0 Note 3

Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. Note 2: * The XC4013XL, XC4036XL, and 4062XL have signicantly faster partial and full delay setup times than other devices. Note 3: Preliminary specication only.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL IOB Input Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Description Clocks Clock Enable (EC) to Clock (IK) Delay from FCL enable (OK) active edge to IFF clock (IK) active edge Setup Times Pad to Clock (IK), no delay Pad to Clock (IK), via transparent Fast Capture Latch, no delay Pad to Fast Capture Latch Enable (OK), no delay Hold Times All Hold Times Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q Speed Grade Symbol Device TECIK TOKIK All devices All devices -3 Min 0.3 1.7 -2 Min 0.2 1.5 -1 Min 0.2 1.3 -09 Min 0.1 1.2 Units

ns ns

TPICK TPICKF TPOCK

All devices All devices All devices All devices

1.7 2.3 0.7 0 19.8 11.3 13.9 15.9 18.6 20.5 22.5 25.1 27.2 29.1 34.4 Max 1.6 2.6 3.1 1.8 1.9 3.6

1.5 2.1 0.6 0 17.3 9.8 12.1 13.8 16.1 17.9 19.6 21.9 23.6 25.3 29.9 Max 1.4 2.2 2.7 1.5 1.7 3.1

1.3 1.8 0.5 0 15.0 8.5 10.5 12.0 14.0 15.5 17.0 19.0 20.5 22.0 26.0 Max 1.2 1.9 2.4 1.3 1.4 2.7

1.3 1.7 0.5 0 14.0 8.1 10.0 11.4 13.3 14.3 16.2 18.1 19.5 20.9 24.7 Max 1.1 1.8 2.2 1.2 1.3 2.6 Note 1

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

TMRW TRRI

All devices XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL All devices All devices All devices All devices All devices All devices

Propagation Delays Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent FCL and input latch, no delay Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) FCL Enable (OK) active edge to I1, I2 (via transparent standard input latch)
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Note 1: Preliminary specication only.

TPID TPLI TPFLI TIKRI TIKLI TOKLI

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XC4000XL IOB Output Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values are expressed in nanoseconds unless otherwise noted. -3 Description Clocks Clock High Clock Low Propagation Delays Clock (OK) to Pad Output (O) to Pad 3-state to Pad hi-Z (slew-rate independent) 3-state to Pad active and valid Output (O) to Pad via Fast Output MUX Select (OK) to Pad via Fast MUX Setup and Hold Times Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup time Clock Enable (EC) to clock (OK) hold time Global Set/Reset Minimum GSR pulse width Delay from GSR input to any Pad XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL Slew Rate Adjustment For output SLOW option add TSLOW 3.0 2.5 2.0 1.7 Note 2
Note 1: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads. Note 2: Preliminary specication only.

-2 Max Min Max Min

-1 Max

-09 Min Max

Symbol

Min

Units

TCH TCL TOKPOF TOPF TTSHZ TTSONF TOFPF TOKFPF TOOK TOKO TECOK TOKEC TMRW TRPO

3.0 3.0

2.8 2.8

2.5 2.5

2.3 2.3

ns ns

5.0 4.1 4.4 4.1 5.5 5.1

4.4 3.6 3.8 3.6 4.8 4.5

3.8 3.1 3.3 3.1 4.2 3.9

3.5 3.0 3.3 3.0 4.0 3.7

ns ns ns ns ns ns

0.5 0.0 0.0 0.3

0.4 0.0 0.0 0.2

0.3 0.0 0.0 0.1

0.3 0.0 0.0 0.0

ns ns ns ns

19.8

17.3

15.0

14.0

ns ns ns ns ns ns ns ns ns ns ns ns

15.9 18.5 20.5 23.2 25.1 27.1 29.7 31.7 33.7 39.0

13.8 16.1 17.8 20.1 21.9 23.6 25.9 27.6 29.3 33.9

12.0 14.0 15.5 17.5 19.0 20.5 22.5 24.0 25.5 29.5

11.4 13.3 14.7 16.6 17.6 19.4 21.4 22.8 24.2 28.0

ns

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX Switching Characteristics

Denition of Terms
In the following tables, some specications may be designated as Advance or Preliminary. These terms are dened as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specications not identied as either Advance or Preliminary are to be considered Final. All specications subject to change without notice.

XC4000EX Absolute Maximum Ratings

Symbol VCC VIN VTS VCCt TSTG TSOL TJ Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Longest Supply Voltage Rise Time from 1 V to 4 V Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic packages Plastic packages Description Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 50 -65 to +150 +260 +150 +125 Units V V V ms C C C C

Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

XC4000EX Recommended Operating Conditions

Symbol VCC VIH VIL TIN Description Supply voltage relative to GND, TJ = 0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C High-level input voltage Commercial Industrial TTL inputs CMOS inputs Low-level input voltage TTL inputs CMOS inputs Input signal transition time Min 4.75 4.5 2.0 70% 0 0 Max 5.25 5.5 VCC 100% 0.8 20% 250 Units V V V VCC V VCC ns

Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Note 2: Input and output measurement thresholds for TTL are 1.5 V. Input and output measurement thresholds for CMOS are 2.5 V. Note 3: All timing parameters are specied for Commercial temperature range only.

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XC4000EX DC Characteristics Over Recommended Operating Conditions

Symbol VOH VOL VDR ICCO IL CIN IRPU IRPD IRLL Pad pull-up (when selected) @ Vin = 0 V (sample tested) Pad pull-down (when selected) @ Vin = 5.5 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low Description High-level output voltage @ IOH = -4.0 mA, VCC min High-level output voltage @ IOH = -1.0 mA Low-level output voltage @ IOL = 12.0 mA, VCC min (Note 1) TTL outputs CMOS outputs TTL outputs CMOS outputs 3.0 25 -10 BGA, SBGA, PQ, HQ, MQ packages PGA packages 0.02 0.02 0.3 +10 10 16 0.25 0.25 2.0 Min 2.4 VCC-0.5 0.4 0.4 Max Units V V V V V mA A pF pF mA mA mA

Data Retention Supply Voltage (below which conguration data may be lost) Quiescent FPGA supply current (Note 2) Input or output leakage current Input capacitance (sample tested)

Note 1: With up to 64 pins simultaneously sinking 12 mA. Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND.

XC4000EX Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade Description Symbol Device XC4028EX XC4036EX XC4028EX XC4036EX From pad through Global Low Skew buffer, TGLS to any clock K From pad through Global Early buffer, to any clock K in same quadrant TGE -4 Max 9.2 9.8 5.7 5.9 -3 Max 7.5 7.9 4.4 4.6 -2 Max 6.4 7.1 4.2 4.4 Units ns ns ns ns

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX Longline and Wide Decoder Timing Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Fewer than the specied number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.

XC4000EX Horizontal Longline Switching Characteristic Guidelines

Speed Grade Description TBUF driving a Horizontal Longline I going High or Low to Horizontal Longline going High TIO1 or Low, while T is Low. Buffer is constantly active. T going Low to Horizontal Longline going from resis- TON tive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. T going High to Horizontal Longline going from Low to TPU2 High, pulled up by two resistors. (Note 1) TBUF driving Half a Horizontal Longline I going High or Low to half of a Horizontal Longline go- THIO1 ing High or Low, while T is Low. Buffer is constantly active. T going Low to half of a Horizontal Longline going from THON resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. T going High to half of a Horizontal Longline going THPU4 from Low to High, pulled up by four resistors. (Note 1) XC4028EX XC4036EX XC4028EX XC4036EX XC4028EX XC4036EX 6.3 7.3 7.2 8.2 5.6 6.0 6.4 6.8 4.6 5.7 5.4 6.5 ns ns ns ns ns ns XC4028EX XC4036EX XC4028EX XC4036EX XC4028EX XC4036EX 13.7 16.5 14.7 17.4 11.3 13.6 12.1 14.4 10.9 13.2 11.7 14.0 ns ns ns ns ns ns Symbol Device -4 Max -3 Max -2 Max Units

Note 1: These values include a minimum load of one output, spaced as far as possible from the activated pullup(s). Use the statictiming analyzer to determine the delay for each destination.

XC4000EX Wide Decoder Switching Characteristic Guidelines

Speed Grade Description Full length, two pull-ups, inputs from IOB I-pins Full length, two pull-ups, inputs from internal logic Half length, two pull-ups, inputs from IOB I-pins Half length, two pull-ups, inputs from internal logic Symbol TWAF2 TWAF2L TWAO2 TWAO2L Device XC4028EX XC4036EX XC4028EX XC4036EX XC4028EX XC4036EX XC4028EX XC4036EX -4 Max -3 Max -2 Max Units ns ns ns ns ns ns ns ns

Note 1: These delays are specied from the decoder input to the decoder output.

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XC4000EX CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devicees unless otherwise noted.
Speed Grade Description Symbol Combinatorial Delays TILO F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs TIHO F/G inputs via transparent latch to Q outputs TITO C inputs via SR/H0 via H to X/Y outputs THH0O C inputs via H1 via H to X/Y outputs THH1O C inputs via DIN/H2 via H to X/Y outputs THH2O C inputs via EC, DIN/H2 to YQ, XQ output (bypass) TCBYP CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Carry Net Delay, COUT to CIN Sequential Delays Clock K to Flip-Flop outputs Q Clock K to Latch outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H Hold Time after Clock K F/G inputs F/G inputs via H C inputs via SR/H0 through H C inputs via H1 through H C inputs via DIN/H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q (XC4028EX) Delay from GSR input to any Q (XC4036EX) Toggle Frequency ) (for export control purposes) TOPCY TASCY TINCY TSUM TBYP TNET TCKO TCKLO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR TCH TCL TRPW TRIO TMRW TMRQ TMRQ FTOG 1.3 3.0 2.8 2.2 2.8 1.2 1.2 0.8 2.2 3.9 0 0 0 0 0 0 0 0 3.5 3.5 3.5 4.5 13.0 22.8 24.0 143 -4 Min Max 2.2 3.8 3.2 3.6 3.0 3.6 2.0 2.5 4.1 1.9 3.0 0.60 0.18 2.2 2.2 1.1 2.5 2.3 1.8 2.3 0.9 1.0 0.7 1.8 3.2 0 0 0 0 0 0 0 0 3.0 3.0 3.0 3.8 11.5 19.0 21.0 166 Min -3 Max 1.8 3.2 2.7 3.0 2.5 3.0 1.6 2.2 3.6 1.6 2.6 0.50 0.15 1.9 1.9 1.1 2.2 2.0 1.8 2.0 0.9 0.9 0.6 2.1 3.2 0 0 0 0 0 0 0 0 3.0 3.0 3.0 3.6 11.5 19.0 21.0 166 Min -2 Max 1.5 2.7 2.5 2.5 2.3 2.5 1.4 1.9 3.1 1.4 2.2 0.40 0.15 1.7 1.7 Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted.

Single Port RAM

Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

Speed Grade Size Symbol Min

-4 Max Min

-3 Max Min

-2 Units Max

16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1

TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS

11.0 11.0 5.5 5.5 2.7 2.6 0 0 2.4 2.9 0 0 2.3 2.1 0 0 8.2 10.1

9.0 9.0 4.5 4.5 2.3 2.2 0 0 2.0 2.5 0 0 2.0 1.8 0 0 6.8 8.4

9.0 9.0 4.5 4.5 2.2 2.2 0 0 2.0 2.5 0 0 2.0 1.8 0 0 6.8 8.2

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Note 2: Applicable Read timing specications are identical to Level-Sensitive Read timing.

Dual-Port RAM
Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

Speed Grade Size Symbol Min

-4 Max Min

-3 Max

-2 Units Min Max

16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1

TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS

11.0 5.5 3.1 0 2.9 0 2.1 0 9.4

9.0 4.5 2.6 0 2.5 0 1.8 0 7.8

9.0 4.5 2.5 0 2.5 0 1.8 0 7.8

ns ns ns ns ns ns ns ns ns

Note 1: Applicable Read timing specications are identical to Level-Sensitive Read timing.

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XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Timing

TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

TILO

TWOS OLD

DATA OUT

NEW
X6461

XC4000EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing

TWPDS WCLK (K) TWSDS WE TDSDS DATA IN TASDS ADDRESS TILO TWODS DATA OUT OLD NEW
X6474

TWHDS

TDHDS

TAHDS

TILO

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Speed Grade Description Write Operation Address write cycle time Write Enable pulse width (High) Address setup time before WE Address hold time after end of WE DIN setup time before end of WE DIN hold time after end of WE Read Operation Address read cycle time Data valid after address change (no Write Enable) 16x2 32x1 16x2 32x1 TRC TRCT TILO TIHO 4.5 6.5 2.2 3.8 3.1 5.5 1.8 3.2 3.1 5.5 1.5 2.7 ns ns ns ns 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWC TWCT TWP TWPT TAS TAST TAH TAHT TDS TDST TDH TDHT 10.6 10.6 5.3 5.3 2.8 2.9 1.7 1.7 1.1 1.1 6.6 6.6 9.2 9.2 4.6 4.6 2.4 2.5 1.4 1.4 0.9 0.9 5.7 5.7 8.0 8.0 4.0 4.0 2.0 2.0 1.4 1.4 0.8 0.8 5.0 5.0 ns ns ns ns ns ns ns ns ns ns ns ns Size Symbol Min -4 Max Min -3 Max Min -2 Units Max

Read Operation, Clocking Data into Flip-Flop Address setup time before clock K Read During Write Data valid after WE goes active (DIN stable before WE) Data valid after DIN (DIN changes during WE) 16x2 32x1 16x2 32x1 TWO TWOT TDO TDOT 6.5 7.4 7.7 8.2 5.7 6.5 6.7 7.2 4.9 5.6 5.8 6.2 ns ns ns ns 16x2 32x1 TICK TIHCK 1.5 3.2 1.2 2.6 1.2 2.6 ns ns

Read During Write, Clocking Data into Flip-Flop WE setup time before clock K Data setup time before clock K 16x2 32x1 16x2 32x1 TWCK TWCKT TDCK TDCKT 7.1 9.2 5.9 8.4 6.2 8.1 5.2 7.4 5.5 7.0 4.6 6.4 ns ns ns ns

Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.

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XC4000EX CLB RAM Asynchronous (Level-Sensitive) Timing Characteristics

T WC ADDRESS

WRITE
TAS WRITE ENABLE T DS T DH T WP T AH

DATA IN

REQUIRED

READ WITHOUT WRITE

T ILO

X,Y OUTPUTS

VALID

VALID

READ, CLOCKING DATA INTO FLIP-FLOP

T ICK CLOCK T CH

T CKO XQ, YQ OUTPUTS VALID (OLD) VALID (NEW)

READ DURING WRITE

WRITE ENABLE

T WP

T DH DATA IN (stable during WE) T WO X, Y OUTPUTS VALID VALID

DATA IN (changing during WE)

OLD T WO T DO VALID (OLD)

NEW

X, Y OUTPUTS

VALID (PREVIOUS)

VALID (NEW)

READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP

T WP WRITE ENABLE T WCK T DCK DATA IN

CLOCK T CKO

XQ, YQ OUTPUTS
X2640

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX Pin-to-Pin Output Parameter Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000EX devices unless otherwise noted.

XC4000EX Output Flip-Flop, Clock to Out

Speed Grade Description Global Low Skew Clock to TTL Output (fast) using OFF Symbol TICKOF Device XC4028EX XC4036EX XC4028EX XC4036EX -4 Max 16.6 17.2 13.1 13.3 -3 Max 13.7 14.1 10.6 10.8 -2 Max 12.4 13.1 10.2 10.4 Units ns ns ns ns

Global Early Clock to TTL Output (fast) using TICKEOF OFF OFF = Output Flip Flop

XC4000EX Output MUX, Clock to Out

Speed Grade Description Global Low Skew Clock to TTL Output (fast) using OMUX Global Early Clock to TTL Output (fast) using OMUX OMUX = Output MUX
Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. Note 2: Output timing is measured at TTL threshold with 50 pF external capacitive load. Note 3: Set-up time is measured with the fastest route and the lightest load. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions.

-4 Max 15.9 16.5 12.4 12.6

-3 Max 13.1 13.5 10.0 10.2

-2 Max 11.8 12.5 9.6 9.8

Symbol TPFPF TPEFPF

Device XC4028EX XC4036EX XC4028EX XC4036EX

Units ns ns ns ns

XC4000EX Output Level and Slew Rate Adjustments

The following table must be used to adjust output parameters and output switching characteristics. Speed Grade Symbol Device TTTLOF All Devices TTTLO TCMOSOF TCMOSO All Devices All Devices All Devices -4 Max 0 2.9 1.0 3.6 -3 Max 0 2.4 0.8 3.0 -2 Max 0 2.4 0.8 3.0 Units ns ns ns ns

Description For TTL output FAST add For TTL output SLOW add For CMOS FAST output add For CMOS SLOW output add

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XC4000EX Pin-to-Pin Input Parameter Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000EX devices unless otherwise noted

XC4000EX Global Low Skew Clock, Set-Up and Hold

Description Input Setup Time, using Global Low Skew clock and IFF (full delay) Input Hold Time, using Global Low Skew clock and IFF (full delay) IFF = Flip-Flop or Latch Symbol TPSD TPHD Speed Grade Device XC4028EX XC4036EX XC4028EX XC4036EX -4 Min 8.0 8.0 0 0 -3 Min 6.8 6.8 0 0 -2 Min 6.8 6.8 0 0 Units ns ns ns ns

XC4000EX Global Early Clock, Set-Up and Hold for IFF

Description Input Setup Time, using Global Early clock and IFF (partial delay) Input Hold Time, using Global Early clock and IFF (partial delay) IFF = Flip-Flop or Latch Symbol TPSEP TPHEP Speed Grade Device XC4028EX XC4036EX XC4028EX XC4036EX -4 Min 6.5 6.5 0 0 -3 Min 5.4 5.4 0 0 -2 Min 5.4 5.4 0 0 Units ns ns ns ns

Note 1: Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6 ns for BUFGE #s 1, 2, 5 and 6.

XC4000EX Global Early Clock, Set-Up and Hold for FCL

Description Input Setup Time, using Global Early clock and FCL (partial delay) Input Hold Time, using Global Early clock and FCL (partial delay) FCL = Fast Capture Latch Speed Grade Device XC4028EX XC4036EX TPFHEP XC4028EX XC4036EX Symbol TPFSEP -4 Min 3.4 4.4 0 0 -3 Min 3.4 4.2 0 0 -2 Min 3.4 4.2 0 0 Units ns ns ns ns

Note 1: For CMOS input levels, see the XC4000EX Input Threshold Adjustments on page -93. Setup time is measured with the fastest route and the lightest load. Use the static timing analyzer to determine the setup time Note 2: under given design conditions. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions. Note 3: Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2 ns for BUFGE #s 1, 2, 5 and 6.

XC4000EX Input Threshold Adjustments

The following table must be used to adjust input parameters and input switching characteristics. Speed Grade Symbol Device TTTLI All Devices TCMOSI All Devices -4 Max 0 0.3 -3 Max 0 0.2 -2 Max 0 0.2 Units ns ns

Description For TTL input add For CMOS input add

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX IOB Input Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Description Clocks Delay from FCL enable (OK) active edge to IFF clock (IK) active edge Propagation Delays Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent input latch, partial delay Pad to I1, I2 via transparent input latch, full delay Speed Grade Symbol Device TOKIK All devices -4 Min 3.2 Max 2.2 3.8 13.3 14.5 18.2 19.4 5.3 13.6 14.8 3.0 3.2 6.2 -3 Min 2.6 Max 1.9 3.2 11.1 12.1 15.2 16.2 4.4 11.3 12.3 2.5 2.7 5.2 -2 Min 2.6 Max 1.8 3.0 10.9 11.9 14.9 15.9 4.2 11.1 12.1 2.4 2.6 5.0 Units

ns

TPID TPLI TPPLI TPDLI

Pad to I1, I2 via transparent FCL and input latch, TPFLI no delay Pad to I1, I2 via transparent FCL and input latch, TPPFLI partial delay Propagation Delays Clock (IK) to I1, I2 (flip-flop) TIKRI Clock (IK) to I1, I2 (latch enable, active Low) TIKLI FCL Enable (OK) active edge to I1, I2 TOKLI (via transparent standard input latch) Global Set/Reset Minimum GSR Pulse Width TMRW Delay from GSR input to any Q TRRI Delay from GSR input to any Q TRRI FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch

All devices All devices XC4028EX XC4036EX XC4028EX XC4036EX All devices XC4028EX XC4036EX All devices All devices All devices

ns ns ns ns ns ns ns ns ns ns ns ns

All devices XC4028EX XC4036EX

13.0 22.8 24.0

11.5 19.0 21.0

11.5 19.0 21.0

ns ns ns

Note 1: For CMOS input levels, see the XC4000EX Input Threshold Adjustments on page -93. Note 2: For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and Hold tables on page -93. .

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XC4000EX IOB Input Switching Characteristic Guidelines (Continued)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Description Setup Times Pad to Clock (IK), no delay Pad to Clock (IK), partial delay Pad to Clock (IK), full delay Pad to Clock (IK), via transparent Fast Capture Latch, no delay Pad to Clock (IK), via transparent Fast Capture Latch, partial delay Pad to Fast Capture Latch Enable (OK), no delay Pad to Fast Capture Latch Enable (OK), partial delay Setup Times (TTL or CMOS Inputs) Clock Enable (EC) to Clock (IK) Hold Times Pad to Clock (IK), no delay partial delay full delay Pad to Clock (IK) via transparent Fast Capture Latch, no delay partial delay full delay Clock Enable (EC) to Clock (IK), no delay partial delay full delay Pad to Fast Capture Latch Enable (OK), no delay partial delay Symbol TPICK TPICKP TPICKD TPICKF TPICKFP TPOCK TPOCKP Speed Grade Device All devices XC4028EX XC4036EX XC4028EX XC4036EX All devices XC4028EX XC4036EX All devices XC4028EX XC4036EX All devices -4 Min 2.5 10.8 12.0 15.7 16.9 3.9 12.3 13.5 0.8 9.1 10.3 0.3 -3 Min 2.0 9.0 10.0 13.1 14.1 3.3 10.2 11.2 0.7 7.6 8.6 0.2 -2 Min 2.0 9.0 10.0 13.1 14.1 3.3 10.2 11.2 0.7 7.6 8.6 0.2 Units

ns ns ns ns ns ns ns ns ns ns ns ns

TECIK

TIKPI TIKPIP TIKPID

All devices All devices All devices

0 0 0

0 0 0

0 0 0

ns ns ns

TIKFPI TIKFPIP TIKFPID TIKEC TIKECP TIKECD TOKPI TOKPIP

All devices All devices All devices All devices All devices All devices All devices All devices

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

ns ns ns ns ns ns ns ns

Note 1: For CMOS input levels, see the XC4000EX Input Threshold Adjustments on page -93. Note 2: For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and Hold tables on page -93.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX IOB Output Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XC4000EX devices unless otherwise noted. Speed Grade Description Propagation Delays Clock (OK) to Pad Output (O) to Pad 3-state to Pad hi-Z (slew-rate independent) 3-state to Pad active and valid Output MUX Select (OK) to Pad Fast Path Output MUX Input (EC) to Pad Slowest Path Output MUX Input (O) to Pad Setup and Hold Times Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup Clock Enable (EC) to clock (OK) hold Clock Clock High Clock Low Global Set/Reset Minimum GSR pulse width TMRW Delay from GSR input to any Pad (XC4028EX) TRPO Delay from GSR input to any Pad (XC4036EX) TRPO 13.0 30.2 31.4 11.5 25.2 27.2 11.5 25.0 27.0 ns ns ns TCH TCL 3.5 3.5 3.0 3.0 3.0 3.0 ns ns TOOK TOKO TECOK TOKEC 0.6 0 0 0 0.5 0 0 0 0.5 0 0 0 ns ns ns ns TOKPOF TOPF TTSHZ TTSONF TOKFPF TCEFPF TOFPF 7.4 6.2 4.9 6.2 6.7 6.2 7.3 6.2 5.2 4.1 5.2 5.6 5.1 6.0 6.0 5.0 4.1 5.0 5.4 5.0 5.9 ns ns ns ns ns ns ns Symbol Min -4 Max Min -3 Max Min -2 Max Units

Note 1: Output timing is measured at TTL threshold, with 35pF external capacitive loads. Note 2: For CMOS output levels, see the XC4000EX Output Level and Slew Rate Adjustments on page -92.

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XC4000E Switching Characteristics

Denition of Terms
In the following tables, some specications may be designated as Advance or Preliminary. These terms are dened as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, not for production. Specications not identied as either Advance or Preliminary are to be considered Final.1

Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked:

XC4000E Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic packages Plastic packages Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +150 +125 Units V V V C C C C

Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

XC4000E Recommended Operating Conditions

Symbol VCC Description Supply voltage relative to GND, TJ = -0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TC = -55C to +125C High-level input voltage Low-level input voltage Input signal transition time Commercial Industrial Military TTL inputs CMOS inputs TTL inputs CMOS inputs Min 4.75 4.5 4.5 2.0 70% 0 0 Max 5.25 5.5 5.5 VCC 100% 0.8 20% 250 Units V V V V VCC V VCC ns

VIH VIL TIN

Note 1: At junction temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35% per C. Note 2: Input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS.

1. Notwithstanding the denition of the above terms, all specications are subject to change without notice.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E DC Characteristics Over Operating Conditions

Symbol VOH VOL ICCO Description High-level output voltage @ IOH = -4.0mA, VCC min High-level output voltage @ IOH = -1.0mA, VCC min Low-level output voltage @ IOL = 12.0mA, VCC min (Note 1) Quiescent FPGA supply current (Note 2) TTL outputs CMOS outputs TTL outputs CMOS outputs Commercial Industrial Military PQFP and MQFP packages Other packages -0.02 0.2 Min 2.4 VCC-0.5 Max Units V V V V mA mA mA A pF pF mA mA

IL CIN

Input or output leakage current Input capacitance (sample tested)

-10

0.4 0.4 3.0 6.0 6.0 +10 10 16 -0.25 2.5

IRIN* IRLL*

Pad pull-up (when selected) @ VIN = 0V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low

Note 1: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA congured with a Development system Tie option. Note 3: *Characterized Only.

XC4000E Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature) Speed Grade Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E -4 Max 7.0 7.0 7.5 8.0 11.0 11.5 12.0 12.5 7.5 7.5 8.0 8.5 11.5 12.0 12.5 13.0 -3 Max 4.7 4.7 5.3 6.1 6.3 6.8 7.0 7.2 5.2 5.2 5.8 6.6 6.8 7.3 7.5 7.7 -2 Max 4.0 4.3 5.2 5.2 5.4 5.8 6.4 6.9 4.4 4.7 5.6 5.6 5.8 6.2 6.7 7.2 -1 Max 3.5 3.8 4.6 4.6 4.8 5.2 6.0 4.0 4.3 5.1 5.1 5.3 5.7 6.5 Preliminary Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Description From pad through Primary buffer, to any clock K

Symbol TPG

From pad through Secondary buffer, to any clock K

TSG

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XC4000E Horizontal Longline Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. The following guidelines reect worst-case values over the recommended operating conditions. Speed Grade Symbol Device TIO1
XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E All devices XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E

Description
TBUF driving a Horizontal Longline (LL):

-4 Max
5.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 5.0 6.0 7.8 8.1 10.5 11.0 12.0 12.0 5.5 7.0 7.5 8.0 8.5 8.7 11.0 11.0 1.8 20.0 23.0 25.0 27.0 29.0 32.0 35.0 42.0 9.0 10.0 11.5 12.5 13.5 15.0 16.0 18.0

-3 Max
4.2 5.0 5.9 6.3 6.4 7.2 8.2 9.1 4.2 5.3 6.4 6.8 6.9 7.7 8.7 9.6 4.6 6.0 6.7 7.1 7.3 7.5 8.4 8.4 1.5 14.0 16.0 18.0 20.0 22.0 26.0 32.5 39.1 7.0 8.0 9.0 10.0 11.0 13.0 14.8 16.5

-2 Max
3.4 4.0 4.7 5.0 5.1 5.7 7.3 7.3 3.6 4.5 5.4 5.8 5.9 6.5 8.7 9.6 3.9 5.7 5.7 6.0 6.2 7.0 7.1 7.1 1.3 14.0 16.0 18.0 20.0 22.0 26.0 32.5 39.1 6.0 6.8 7.7 8.5 9.4 11.7 14.8 16.5

-1 Max
2.9 3.4 4.0 4.3 4.4 4.9 5.6 3.1 3.8 4.6 4.9 5.0 5.5 7.4 3.5 4.7 4.9 5.2 5.4 6.2 6.3 1.1 12.0 14.0 16.0 16.0 18.0 21.0 26.0 5.4 5.8 6.5 7.5 8.0 9.4 10.5 Preliminary

Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

I going High or Low to LL going High or Low, while T is Low. Buffer is constantly active. (Note1)

I going Low to LL going from resistive pull-up High to active Low. TBUF configured as open-drain. (Note1) T going Low to LL going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. (Note1) T going High to TBUF going inactive, not driving LL T going High to LL going from Low to High, pulled up by a single resistor. (Note 1)

TIO2

TON

TOFF TPUS

T going High to LL going from Low to High, pulled up by two resistors. (Note1)

TPUF

Note 1: These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E Wide Decoder Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. The following guidelines reect worst-case values over the recommended operating conditions. Speed Grade Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E TWAFL XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E TWAO XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E TWAOL XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E -4 Max 9.2 9.5 12.0 12.5 15.0 16.0 17.0 18.0 12.0 12.5 14.0 16.0 18.0 19.0 20.0 21.0 10.5 10.5 13.5 14.0 16.0 17.0 18.0 19.0 12.0 12.5 14.0 16.0 18.0 19.0 20.0 21.0 -3 Max 5.0 6.0 7.0 8.0 9.0 11.0 13.9 16.9 7.0 8.0 9.0 10.0 11.0 13.0 15.5 18.9 6.0 7.0 8.0 9.0 10.0 12.0 15.0 17.6 8.0 9.0 10.0 11.0 12.0 14.0 16.8 19.6 -2 Max 5.0 6.0 7.0 8.0 9.0 11.0 13.9 16.9 7.0 8.0 9.0 10.0 11.0 13.0 15.5 18.9 6.0 7.0 8.0 9.0 10.0 12.0 15.0 17.6 8.0 9.0 10.0 11.0 12.0 14.0 16.8 19.6 -1 Units Max 4.3 ns 5.1 ns 6.0 ns 6.5 ns 7.5 ns 8.6 ns 10.1 ns ns 5.5 ns 6.4 ns 7.0 ns 7.5 ns 8.5 ns 10.0 ns 11.8 ns ns 5.1 ns 6.0 ns 6.5 ns 7.0 ns 7.5 ns 10.0 ns 11.8 ns ns 6.0 ns 7.0 ns 7.6 ns 8.4 ns 9.2 ns 10.8 ns 12.6 ns ns Preliminary

Description Full length, both pull-ups, inputs from IOB I-pins

Symbol TWAF

Full length, both pull-ups, inputs from internal logic

Half length, one pull-up, inputs from IOB I-pins

Half length, one pull-up, inputs from internal logic

Note 1: These delays are specied from the decoder input to the decoder output. Note 2: Fewer than the specied number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.

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XC4000E CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs C inputs via SR through H to X/Y outputs C inputs via H to X/Y outputs C inputs via DIN through H to X/Y outputs CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Sequential Delays Clock K to outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H -4 Symbol TILO TIHO THH0O THH1O THH2O TOPCY TASCY TINCY TSUM TBYP TCKO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK 4.0 6.1 4.5 5.0 4.8 3.0 4.0 4.2 2.5 4.2 Min Max 2.7 4.7 4.1 3.7 4.5 3.2 5.5 1.7 3.8 1.0 3.7 3.0 4.6 3.6 4.1 3.8 2.4 3.0 4.0 2.1 3.5 Min -3 Max 2.0 4.3 3.3 3.6 3.6 2.6 4.4 1.7 3.3 0.7 2.8 2.4 3.9 3.5 3.3 3.7 2.0 2.6 4.0 Min -2 Max 1.6 2.7 2.4 2.2 2.6 2.1 3.7 1.4 2.6 0.6 2.8 1.8 2.8 2.4 2.1 2.5 1.0 2.0 1.5 Min -1 Max 1.3 2.2 1.9 1.6 1.9 1.7 2.5 1.2 1.8 0.5 1.9 Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Preliminary

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E CLB Switching Characteristic Guidelines (continued)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Hold Time after Clock K F/G inputs TCKI F/G inputs via H TCKIH C inputs via H0 through H TCKHH0 C inputs via H1 through H TCKHH1 C inputs via H2 through H TCKHH2 C inputs via DIN TCKDI C inputs via EC TCKEC C inputs via SR, going Low (inactive) TCKR Clock Clock High time TCH Clock Low time TCL Set/Reset Direct Width (High) TRPW Delay from C inputs via S/R, TRIO going High to Q Master Set/Reset (Note 1) Width (High or Low) TMRW Delay from Global Set/Reset net to Q TMRQ Global Set/Reset inactive to first TMRK active clock K edge Toggle Frequency (Note 2) FTOG -4 Min 0 0 0 0 0 0 0 0 4.5 4.5 5.5 6.5 Max Min 0 0 0 0 0 0 0 0 4.0 4.0 4.0 4.0 -3 Max Min 0 0 0 0 0 0 0 0 4.0 4.0 4.0 4.0 -2 Max Min 0 0 0 0 0 0 0 0 3.0 3.0 3.0 3.0 -1 Max Units

ns ns ns ns ns ns ns ns ns ns ns ns

13.0 23.0

11.5 18.7

11.5 17.4

10.0 15.0

ns ns

111

125

125

166 Preliminary

MHz

Note 1: Timing is based on the XC4005E. For other devices see the static timing analyzer. Note 2: Export Control Max. ip-op toggle rate.

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XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted.

Single Port RAM

Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

Speed Grade Size Symbol Min

-4 Max Min

-3 Max Min

-2 Max Min

-1 Units Max

16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1

TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS

15.0 15.0 7.5 7.5 2.8 2.8 0 0 3.5 2.5 0 0 2.2 2.2 0 0 10.3 11.6 1 ms 1 ms

14.4 14.4 7.2 7.2 2.4 2.4 0 0 3.2 1.9 0 0 2.0 2.0 0 0 8.8 10.3 1 ms 1 ms

11.6 11.6 5.8 5.8 2.0 2.0 0 0 2.7 1.7 0 0 1.6 1.6 0 0 7.9 9.3 1 ms 1 ms

8.0 8.0 4.0 4.0 1.5 1.5 0 0 1.5 1.5 0 0 1.5 1.5 0 0 6.5 7.0 Preliminary

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Note 2: Applicable Read timing specications are identical to Level-Sensitive Read timing.

Dual-Port RAM
Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

Speed Grade Size Symbol Min

-4 Max Min

-3 Max Min

-2 Max Min

-1 Units Max

16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1

TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS

15.0 7.5 7.5 2.8 0 2.2 0 2.2 0.3

1 ms

14.4 7.2 2.5 0 2.5 0 1.8 0

1 ms

10.0

7.8

11.6 5.8 1 ms 2.1 0 1.6 0 1.6 0 7.0

8.0 4.0 1.5 0 1.5 0 1.5 0 6.5 Preliminary

ns ns ns ns ns ns ns ns ns

Note 1: Applicable Read timing specications are identical to Level-Sensitive Read timing.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing

TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

TILO

TWOS OLD

DATA OUT

NEW
X6461

XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing

TWPDS WCLK (K) TWSDS WE TDSDS DATA IN TASDS ADDRESS TILO TWODS DATA OUT OLD NEW
X6474

TWHDS

TDHDS

TAHDS

TILO

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XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Description Write Operation Address write cycle time Write Enable pulse width (High) Address setup time before WE Address hold time after end of WE DIN setup time before end of WE DIN hold time after end of WE Read Operation Address read cycle time Data valid after address change (no Write Enable) 16x2 32x1 16x2 32x1 TRC TRCT TILO TIHO 4.5 6.5 2.7 4.7 3.1 5.5 1.8 3.2 2.6 3.8 1.6 2.7 2.6 3.8 1.6 2.7 ns ns ns ns 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWC TWCT TWP TWPT TAS TAST TAH TAHT TDS TDST TDH TDHT 8.0 8.0 4.0 4.0 2.0 2.0 2.5 2.0 4.0 5.0 2.0 2.0 8.0 8.0 4.0 4.0 2.0 2.0 2.0 2.0 2.2 2.2 2.0 2.0 8.0 8.0 4.0 4.0 2.0 2.0 2.0 2.0 0.8 0.8 2.0 2.0 8.0 8.0 4.0 4.0 2.0 2.0 2.0 2.0 0.8 0.8 2.0 2.0 ns ns ns ns ns ns ns ns ns ns ns ns Size Symbol Min -4 Max Min -3 Max Min -2 Max Min -1 Units Max

Read Operation, Clocking Data into Flip-Flop Address setup time before clock K Read During Write Data valid after WE goes active (DIN stable before WE) Data valid after DIN (DIN changes during WE) 16x2 32x1 16x2 32x1 TWO TWOT TDO TDOT 10.0 12.0 9.0 11.0 6.0 7.3 6.6 7.6 4.9 5.6 5.8 6.2 4.9 5.6 5.8 6.2 ns ns ns ns 16x2 32x1 TICK TIHCK 4.0 6.1 3.0 4.6 2.4 3.9 2.4 3.9 ns ns

Read During Write, Clocking Data into Flip-Flop WE setup time before clock K Data setup time before clock K 16x2 32x1 16x2 32x1 TWCK TWCKT TDCK TDCKT 8.0 9.6 7.0 8.0 6.0 6.8 5.2 6.2 5.1 5.8 4.4 5.3 5.1 5.8 4.4 5.3 Preliminary
Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.

ns ns ns ns

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E CLB Level-Sensitive RAM Timing Characteristics

T WC ADDRESS

WRITE
TAS WRITE ENABLE T DS T DH T WP T AH

DATA IN

REQUIRED

READ WITHOUT WRITE

T ILO

X,Y OUTPUTS

VALID

VALID

READ, CLOCKING DATA INTO FLIP-FLOP

T ICK CLOCK T CH

T CKO XQ, YQ OUTPUTS VALID (OLD) VALID (NEW)

READ DURING WRITE

WRITE ENABLE

T WP

T DH DATA IN (stable during WE) T WO X, Y OUTPUTS VALID VALID

DATA IN (changing during WE)

OLD T WO T DO VALID (OLD)

NEW

X, Y OUTPUTS

VALID (PREVIOUS)

VALID (NEW)

READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP

T WP WRITE ENABLE T WCK T DCK DATA IN

CLOCK T CKO

XQ, YQ OUTPUTS
X2640

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XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted. Speed Grade Symbol Device XC4003E TICKOF
XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E

-4
12.5 14.0 14.5 15.0 16.0 16.5 17.0 17.0 16.5 18.0 18.5 19.0 20.0 20.5 21.0 21.0 2.5 2.0 1.9 1.4 1.0 0.5 0 0 4.0 4.6 5.0 6.0 6.0 7.0 7.5 8.0 8.5 8.5 8.5 8.5 8.5 8.5 9.5 9.5 0 0 0 0 0 0 0 0

-3
10.2 10.7 10.7 10.8 10.9 11.0 11.0 12.6 14.0 14.7 14.7 14.8 14.9 15.0 15.1 15.3 2.3 1.2 1.0 0.6 0.2 0 0 0 4.0 4.5 4.7 5.1 5.5 6.5 6.7 7.0 7.0 7.0 7.0 7.0 7.0 7.0 7.0 7.6 0 0 0 0 0 0 0 0

-2
8.7 9.1 9.1 9.2 9.3 9.4 10.2 10.8 11.5 12.0 12.0 12.1 12.2 12.8 12.8 13.0 2.3 1.2 1.0 0.6 0.2 0 0 0 4.0 4.5 4.7 5.1 5.5 5.5 5.7 5.9 6.0 6.0 6.0 6.0 6.0 6.0 6.8 6.8 0 0 0 0 0 0 0 0

-1
5.8 6.2 6.4 6.6 6.8 7.2 7.4 7.8 8.2 8.4 8.6 8.8 9.2 9.4 1.5 0.8 0.6 0.2 0 0 0 1.5 2.0 2.0 2.5 2.5 3.0 3.5 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 0 0 0 0 0 0

Description Global Clock to Output (fast) using OFF

TPG Global Clock-to-Output Delay OFF

Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

. . . . .
X3202

(Max)

Global Clock to Output (slew-limited) using OFF

TPG Global Clock-to-Output Delay OFF

TICKO

. . . . .
X3202

(Max)

Input Setup Time, using IFF (no delay)

D Input Set - Up & Hold Time IFF TPG

TPSUF

(Min)

X3201

Input Hold Time, using IFF (no delay)

D Input Set - Up & Hold Time IFF TPG

TPHF

(Min)

X3201

Input Setup Time, using IFF (with delay)

D Input Set - Up & Hold Time IFF TPG

TPSU

(Min)

X3201

Input Hold Time, using IFF (with delay)

D Input Set - Up & Hold Time IFF TPG

TPH

(Min)

X3201

OFF = Output Flip-Flop

IFF = Input Flip-Flop or Latch

Preliminary

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E IOB Input Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted. Speed Grade Symbol Device -4 Min Max Min -3 Max Min -2 Max Min -1 Max Units

Description
Propagation Delays (TTL Inputs)

Pad to I1, I2 Pad to I1, I2 via transparent latch, no delay with delay

TPID TPLI TPDLI

All devices All devices XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E All devices All devices XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E All devices All devices All devices All devices 0 0 1.5 0

3.0 4.8 10.4 10.8 10.8 10.8 11.0 11.4 13.8 13.8 5.5 8.8 16.5 16.5 16.8 17.3 17.5 18.0 20.8 20.8 5.6 6.2 0 0 1.5 0

2.5 3.6 9.3 9.6 10.2 10.6 10.8 11.2 12.4 13.7 4.1 6.8 12.4 13.2 13.4 13.8 14.0 14.4 15.6 15.6 2.8 4.0 0 0 0.9 0

2.0 3.6 6.9 7.4 8.1 8.2 8.3 9.8 11.5 12.4 3.7 6.2 11.0 11.9 12.1 12.4 12.6 13.0 14.0 14.0 2.8 3.9 0 0

1.4 2.8 6.4 6.5 6.9 7.0 7.3 8.4 9.0 1.9 3.3 6.9 7.0 7.4 7.4 7.8 9.0 9.5 2.7 3.2

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Propagation Delays (CMOS Inputs)

Pad to I1, I2 Pad to I1, I2 via transparent latch, no delay with delay

TPIDC TPLIC TPDLIC

Propagation Delays

Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low)
Hold Times (Note 1)

TIKRI TIKLI TIKPI TIKPID

Pad to Clock (IK), no delay with delay Clock Enable (EC) to Clock (IK), no delay with delay

TIKEC All devices TIKECD All devices

0 0 Preliminary

Note 1: Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.

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XC4000E IOB Input Switching Characteristic Guidelines (continued)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Device Setup Times (TTL Inputs) Pad to Clock (IK), no delay TPICK All devices with delay TPICKD XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E Setup Time (CMOS Inputs) Pad to Clock (IK), no delay TPICKC All devices with delay TPICKDC XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E (TTL or CMOS) Clock Enable (EC) to Clock (IK), no delay TECIK All devices with delay TECIKD XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E Global Set/Reset (Note 3) Delay from GSR net TRRI through Q to I1, I2 GSR width TMRW GSR inactive to first active TMRI Clock (IK) edge -4 Min 4.0 10.9 10.9 10.9 11.1 11.3 11.8 14.0 14.0 6.0 12.0 12.0 12.3 12.8 13.0 13.5 16.0 16.0 Max Min 2.6 8.2 8.7 9.2 9.6 9.8 10.2 11.4 11.4 3.3 8.8 9.7 9.9 10.3 10.5 10.9 12.1 12.1 -3 Max Min 2.0 6.0 6.1 6.2 6.3 6.4 7.9 9.4 10.0 2.4 6.9 8.0 8.1 8.2 8.3 10.0 12.1 12.1 -2 Max Min 1.5 4.8 5.1 5.8 5.8 6.0 7.6 8.2 2.4 5.3 5.6 6.3 6.3 6.5 7.9 8.1 -1 Max Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

3.5 10.4 10.4 10.4 10.4 10.7 11.1 14.0 14.0 12.0 13.0

2.5 8.1 8.5 9.1 9.5 9.7 10.1 11.3 11.3 7.8 11.5

2.1 4.3 5.6 6.7 6.9 7.1 9.0 10.6 11.0 6.8 11.5

1.5 4.3 5.0 6.0 6.0 6.5 8.0 9.0 6.8 10.0

ns ns ns ns ns ns ns ns ns ns ns

Preliminary
Note 1: Note 2: Note 3: Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source. Timing is based on the XC4005E. For other devices see the XACT timing calculator.

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XC4000E IOB Output Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Propagation Delays (TTL Output Levels) Clock (OK) to Pad, fast TOKPOF slew-rate limited TOKPOS Output (O) to Pad, fast TOPF slew-rate limited TOPS 3-state to Pad hi-Z TTSHZ (slew-rate independent) 3-state to Pad active and valid, fast TTSONF slew-rate limited TTSONS Propagation Delays (CMOS Output Levels) Clock (OK) to Pad, fast TOKPOFC slew-rate limited TOKPOSC Output (O) to Pad, fast TOPFC slew-rate limited TOPSC 3-state to Pad hi-Z TTSHZC (slew-rate independent) 3-state to Pad active and valid, fast TTSONFC slew-rate limited TTSONSC
Note 1:

-4 Min Max Min

-3 Max Min

-2 Max Min

-1 Max

Units

7.5 11.5 8.0 12.0 5.0

6.5 9.5 5.5 8.5 4.2

4.5 7.0 4.8 7.3 3.8

3.0 5.0 3.2 5.2 3.0

ns ns ns ns ns

9.7 13.7

8.1 11.1

7.3 9.8

6.8 8.8

ns ns

9.5 13.5 10.0 14.0 5.2

7.8 11.6 9.7 13.4 4.3

7.0 10.4 8.7 12.1 3.9

4.0 7.0 4.0 6.0 3.9

ns ns ns ns ns

9.1 13.1

7.6 11.4

6.8 10.2

6.8 8.8 Preliminary

ns ns

Note 2:

Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.

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XC4000E IOB Output Switching Characteristic Guidelines (continued)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Setup and Hold Output (O) to clock (OK) TOOK setup time Output (O) to clock (OK) TOKO hold time Clock Enable (EC) to TECOK clock (OK) setup Clock Enable (EC) to TOKEC clock (OK) hold Clock Clock High TCH Clock Low TCL Global Set/Reset (Note 3) Delay from GSR net to Pad TRPO GSR width TMRW GSR inactive to first active TMRO clock (OK) edge -4 Min 5.0 0 4.8 1.2 Max Min 4.6 0 3.5 1.2 -3 Max Min 3.8 0 2.7 0.5 -2 Max Min 2.3 0 2.0 0 -1 Max Units

ns ns ns ns

4.5 4.5 15.0 13.0

4.0 4.0 11.8 11.5

4.0 4.0 8.7 11.5

3.0 3.0 7.0

ns ns ns ns

Preliminary
Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source. Timing is based on the XC4005E. For other devices see the XACT timing calculator.

Note 2: Note 3:

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Setup and Hold Input (TDI) to clock (TCK) TTDITCK setup time Input (TDI) to clock (TCK) TTCKTDI hold time Input (TMS) to clock (TCK) TTMSTCK setup time Input (TMS) to clock (TCK) TTCKTMS hold time Propagation Delay Clock (TCK) to Pad (TDO) TTCKPO Clock Clock (TCK) High TTCKH Clock (TCK) Low TTCKL FMAX (MHz) FMAX
Note 1: Note 2:

-4 Min 30.0 0 15.0 0 Max Min 30.0 0 15.0 0

-3 Max Min 30.0 0 15.0 0

-2 Max Min 20.0 0 10.0 0

-1 Max

Units

ns ns ns ns

30.0 5.0 5.0 15.0 5.0 5.0

30.0 5.0 5.0 15.0

30.0 4.0 4.0 15.0

20.0

ns ns ns ns

25.0 Preliminary

Note 3:

Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

March 30, 1998 (Version 1.5)

Device-Specic Pinout Tables

Device-specic tables include all packages for each XC4000 and XC4000X Series device. They follow the pad locations around the die, and include boundary scan register locations..

Pin Locations for XC4003E Devices

XC4003E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O (A12) I/O (A13) I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O, TDI I/O, TCK I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O (LDC) I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O PC84 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 PQ100 P92 P93 P94 P95 P96 P97 P98 P99 P100 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 VQ100 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 PG120 G3 G1 F1 E1 F2 F3 D1 C1 D2 C2 D3 C3 C4 B2 B3 C5 B4 B5 A4 C6 A5 B6 A6 B7 C7 A7 A8 A9 B8 C8 A10 B9 A11 C9 A12 B11 C10 C11 D11 B12 C12 A13 D12 C13 E12 D13 F11 E13 F12 F13 G12 G11 G13 H13 J13 H12 H11 Bndry Scan 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 126 127 130 133 136 139 142 145 148 151 154 157 160 163 166 169 XC4003E Pad Name I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND 5/5/97 PC84 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P1 PQ100 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 VQ100 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 PG120 K13 J12 L13 M13 L12 K11 L11 L10 M12 M11 N13 M10 N11 M9 N10 L8 N9 M8 N8 M7 L7 N7 N6 N5 M6 L6 N4 M5 N3 N2 M3 L4 L3 M2 K3 L2 N1 K2 L1 J2 K1 H3 J1 H2 H1 G2 Bndry Scan 172 175 178 181 184 187 190 193 196 199 202 205 208 211 214 217 220 223 226 229 232 235 238 241 244 0 2 5 8 11 14 17 20 23 26 29 -

Additional XC4003E Package Pins

PG120 A1 E2 L5 5/5/97 A2 E3 L9 Not Connected Pins A3 B1 E11 J3 M1 M4 B10 J11 N12 B13 K12 -

March 30, 1998 (Version 1.5)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Pin Locations for XC4005E/XL Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information.
XC4005E/XL Pad Name VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O (A10) I/O (A11) I/O I/O GND I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 , GCK8 (A15) VCC GND I/O, PGCK1, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK2 , GCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 , GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) PC PQ VQ TQ 84 100 100 144 P2 P92 P89 P128 P3 P93 P90 P129 P4 P94 P91 P130 P95 P92 P131 P96 P93 P132 P5 P97 P94 P133 P6 P98 P95 P134 P135 P136 P137 P7 P99 P96 P138 P8 P100 P97 P139 P140 P141 P9 P1 P98 P142 P10 P2 P99 P143 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P100 P144 P1 P1 P2 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 PG 156 H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 E3 C1 C2 D3 B1 B2 C3 C4 B3 A1 A2 C5 B4 A3 C6 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 C11 B12 A13 A14 C12 B13 B14 A15 C13 A16 C14 B15 B16 D14 C15 D15 E14 C16 PQ 160 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P154 P155 P156 P157 P158 P159 PQ Bndry 208 Scan P183 P184 44 P185 47 P186 50 P187 53 P190 56 P191 59 P192 62 P193 65 P194 P199 68 P200 71 P201 74 P202 77 P203 80 P204 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 174 175 178 181 184 187 190 XC4005E/XL Pad Name GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK3 , GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3, GCK5 I/O I/O I/O (D6) I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O I/O I/O GND I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) PC 84 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 PQ VQ 100 100 P34 P31 P35 P32 P36 P33 P37 P34 P38 P35 P39 P36 P40 P37 P41 P38 P42 P39 P43 P40 P44 P41 P45 P42 P46 P43 P47 P44 P48 P45 P49 P46 P50 P47 P51 P48 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 TQ 144 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 PG 156 F14 F15 E16 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 M16 L15 L14 P16 M14 N15 P15 N14 R16 P14 R15 P13 R14 T16 T15 R13 P12 T14 T13 P11 R11 T11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 P7 T5 R6 T4 P6 T3 P5 R4 R3 P4 PQ 160 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P113 P114 PQ Bndry 208 Scan P67 P68 193 P69 196 P70 199 P71 202 P74 205 P75 208 P76 211 P77 214 P78 P79 P80 217 P81 220 P82 223 P83 226 P86 229 P87 232 P88 235 P89 238 P90 P95 241 P96 244 P97 247 P98 250 P99 253 P100 256 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P119 P120 P121 P122 P123 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P138 P139 P140 P141 P142 P147 P148 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337

P160 P205 P1 P2 P2 P4 P3 P4 P5 P6 P7 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P5 P6 P7 P8 P9 P14 P15 P16 P17 P18 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P33 P34 P35 P36 P37 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 P59 P60 P61 P62

P115 P149 P116 P150 P117 P151

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March 30, 1998 (Version 1.5)

XC4005E/XL Pad Name I/O, SGCK4 , GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 , GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) GND I/O I/O I/O (A4) I/O (A5) I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND 6/10/97

PC 84 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P1

PQ VQ TQ 100 100 144 P76 P73 P106 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127

PG 156 T2 R2 P3 T1 N3 R1 P2 N2 M3 P1 N1 L3 L2 L1 K3 K2 K1 J1 J2 J3 H2

PQ PQ Bndry 160 208 Scan P118 P152 340 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P131 P132 P133 P134 P135 P137 P138 P139 P140 P141 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 P171 P172 P173 P174 P175 P178 P179 P180 P181 P182 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 -

PG156 A4 M1 T12 5/5/97 A12 M2 Not Connected Pins D1 D2 M15 N16 D16 R5 E15 R12 -

PQ160 P8 P71 P129 6/16/97 P9 P72 P130 Not Connected Pins P30 P31 P89 P90 P136 P152 P49 P111 P153 P50 P112 -

PQ208 P1 P19 P40 P63 P84 P102 P117 P143 P157 P176 P197 6/5/97 P3 P20 P41 P64 P85 P104 P118 P144 P158 P177 P198 Not Connected Pins P10 P11 P31 P32 P51 P52 P65 P66 P91 P92 P105 P107 P124 P125 P145 P146 P167 P168 P188 P189 P206 P207 P12 P38 P53 P72 P93 P115 P136 P155 P169 P195 P208 P13 P39 P54 P73 P94 P116 P137 P156 P170 P196 -

= E only = XL only

Additional XC4005E/XL Package Pins

TQ144 P117 5/5/97 Not Connected Pins -

Pin Locations for XC4006E Devices

XC4006E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O GND PC 84 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 TQ 144 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P1 P2 P3 P4 P5 P6 P7 P8 PG 156 H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 D1 D2 E3 C1 C2 D3 B1 B2 C3 C4 B3 A1 A2 C5 B4 A3 A4 C6 PQ 160 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 PQ 208 P183 P184 P185 P186 P187 P190 P191 P192 P193 P194 P197 P198 P199 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P14 Bndry Scan 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 XC4006E Pad Name I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND PC 84 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 TQ 144 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 PG 156 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 C11 A12 B12 A13 A14 C12 B13 B14 A15 C13 PQ 160 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 PQ 208 P15 P16 P17 P18 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 Bndry Scan 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 -

March 30, 1998 (Version 1.5)

4-115

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4006E Pad Name I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) PC 84 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 TQ 144 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 PG 156 A16 C14 B15 B16 D14 C15 D15 E14 C16 E15 D16 F14 F15 E16 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 M16 L15 L14 N16 M15 P16 M14 N15 P15 N14 R16 P14 R15 P13 R14 T16 T15 R13 P12 T14 T13 R12 T12 P11 R11 T11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 PQ 160 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 PQ 208 P50 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P67 P68 P69 P70 P71 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P86 P87 P88 P89 P90 P93 P94 P95 P96 P97 P98 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P119 P120 P121 P122 P123 P126 P127 P128 P129 P130 P131 P132 P133 Bndry Scan 197 198 199 202 205 208 211 214 217 220 223 226 229 232 235 238 241 244 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 346 XC4006E Pad Name I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND 5/5/97 PC 84 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P1 TQ 144 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 PG 156 T6 R7 P7 T5 R6 T4 P6 R5 T3 P5 R4 R3 P4 T2 R2 P3 T1 N3 R1 P2 N2 M3 P1 N1 M2 M1 L3 L2 L1 K3 K2 K1 J1 J2 J3 H2 PQ 160 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P137 P138 P139 P140 P141 PQ 208 P134 P135 P138 P139 P140 P141 P142 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P171 P172 P173 P174 P175 P178 P179 P180 P181 P182 Bndry Scan 349 352 355 358 361 364 367 370 373 376 379 382 385 388 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 -

Additional XC4006E Package Pins

PQ160 P136 5/5/97 PQ208 P1 P20 P51 P66 P91 P107 P136 P156 P176 P196 6/5/97 P3 P31 P52 P72 P92 P117 P137 P157 P177 P206 Not Connected Pins P12 P32 P53 P73 P102 P118 P143 P158 P188 P207 P13 P38 P54 P84 P104 P124 P144 P169 P189 P208 P19 P39 P65 P85 P105 P125 P155 P170 P195 Not Connected Pins -

4-116

March 30, 1998 (Version 1.5)

Pin Locations for XC4008E Devices

XC4008E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 PC84 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 PQ160 PG191 PQ208 Bndry Scan P142 J4 P183 P143 J3 P184 56 P144 J2 P185 59 P145 J1 P186 62 P146 H1 P187 65 H2 P188 68 H3 P189 71 P147 G1 P190 74 P148 G2 P191 77 P149 F1 P192 80 P150 E1 P193 83 P151 G3 P194 P152 C1 P197 86 P153 E2 P198 89 P154 F3 P199 92 P155 D2 P200 95 P156 B1 P201 98 P157 E3 P202 101 P158 C2 P203 104 P159 B2 P204 107 P160 D3 P205 P1 D4 P2 P2 C3 P4 110 P3 C4 P5 113 P4 B3 P6 116 P5 C5 P7 119 P6 A2 P8 122 P7 B4 P9 125 P8 C6 P10 128 P9 A3 P11 131 P10 C7 P14 P11 A4 P15 134 P12 A5 P16 137 P13 B7 P17 140 P14 A6 P18 143 C8 P19 146 A7 P20 149 P15 B8 P21 152 P16 A8 P22 155 P17 B9 P23 158 P18 C9 P24 161 P19 D9 P25 P20 D10 P26 P21 C10 P27 164 P22 B10 P28 167 P23 A9 P29 170 P24 A10 P30 173 A11 P31 176 C11 P32 179 P25 B11 P33 182 P26 A12 P34 185 P27 B12 P35 188 P28 A13 P36 191 P29 C12 P37 P30 A15 P40 194 P31 C13 P41 197 P32 B14 P42 200 P33 A16 P43 203 P34 B15 P44 206 P35 C14 P45 209 P36 A17 P46 212 P37 B16 P47 215 P38 C15 P48 218 P39 D15 P49 P40 A18 P50 221 P41 D16 P55 P42 C16 P56 222 P43 B17 P57 223 XC4008E Pad Name I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O PC84 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 PQ160 PG191 PQ208 Bndry Scan P44 E16 P58 226 P45 C17 P59 229 P46 D17 P60 232 P47 B18 P61 235 P48 E17 P62 238 P49 F16 P63 241 P50 C18 P64 244 P51 G16 P67 P52 E18 P68 247 P53 F18 P69 250 P54 G17 P70 253 P55 G18 P71 256 H16 P72 259 H17 P73 262 P56 H18 P74 265 P57 J18 P75 268 P58 J17 P76 271 P59 J16 P77 274 P60 J15 P78 P61 K15 P79 P62 K16 P80 277 P63 K17 P81 280 P64 K18 P82 283 P65 L18 P83 286 L17 P84 289 L16 P85 292 P66 M18 P86 295 P67 M17 P87 298 P68 N18 P88 301 P69 P18 P89 304 P70 M16 P90 P71 T18 P93 307 P72 P17 P94 310 P73 N16 P95 313 P74 T17 P96 316 P75 R17 P97 319 P76 P16 P98 322 P77 U18 P99 325 P78 T16 P100 328 P79 R16 P101 P80 U17 P103 P81 R15 P106 P82 V18 P108 P83 T15 P109 331 P84 U16 P110 334 P85 T14 P111 337 P86 U15 P112 340 P87 V17 P113 343 P88 V16 P114 346 P89 T13 P115 349 P90 U14 P116 352 P91 T12 P119 P92 U13 P120 355 P93 V13 P121 358 P94 U12 P122 361 P95 V12 P123 364 T11 P124 367 U11 P125 370 P96 V11 P126 373 P97 V10 P127 376 P98 U10 P128 379 P99 T10 P129 382 P100 R10 P130 P101 R9 P131 P102 T9 P132 385 P103 U9 P133 388 P104 V9 P134 391 P105 V8 P135 394 U8 P136 397

March 30, 1998 (Version 1.5)

4-117

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4008E Pad Name I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O GND I/O I/O I/O (A4) I/O (A5) PC84 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 PQ160 PG191 PQ208 Bndry Scan T8 P137 400 P106 V7 P138 403 P107 U7 P139 406 P108 V6 P140 409 P109 U6 P141 412 P110 T7 P142 P111 U5 P145 415 P112 T6 P146 418 P113 V3 P147 421 P114 V2 P148 424 P115 U4 P149 427 P116 T5 P150 430 P117 U3 P151 433 P118 T4 P152 436 P119 V1 P153 P120 R4 P154 P121 U2 P159 0 P122 R3 P160 P123 T3 P161 2 P124 U1 P162 5 P125 P3 P163 8 P126 R2 P164 11 P127 T2 P165 14 P128 N3 P166 17 P129 P2 P167 20 P130 T1 P168 23 P131 M3 P171 P132 P1 P172 26 P133 N1 P173 29 P134 M2 P174 32 P135 M1 P175 35 XC4008E Pad Name I/O I/O I/O I/O I/O (A6) I/O (A7) GND 5/5/97 PC84 P83 P84 P1 PQ160 PG191 PQ208 Bndry Scan L3 P176 38 P136 L2 P177 41 P137 L1 P178 44 P138 K1 P179 47 P139 K2 P180 50 P140 K3 P181 53 P141 K4 P182 -

Additional XC4008E Package Pins

PG191 A14 F2 V4 6/3/97 B5 F17 V5 Not Connected Pins B6 B13 N2 N17 V14 V15 D1 R1 D18 R18 -

PQ208 P1 P51 P91 P117 P157 P206 6/3/97 P3 P52 P92 P118 P158 P207 Not Connected Pins P12 P13 P53 P54 P102 P104 P143 P144 P169 P170 P208 P38 P65 P105 P155 P195 P39 P66 P107 P156 P196 -

Pin Locations for XC4010E/XL Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information.
XC4010E/XL Pad Name PC 84 PQ TQ 100 144 PQ 160 TQ 176 PG 191 PQ/ HQ 208 BG 225 BG 256 Bndry Scan XC4010E/XL Pad Name PC 84 PQ TQ 100 144 PQ 160 TQ 176 PG 191 PQ/ HQ 208 BG 225 BG 256 Bndry Scan

VCC I/O (A8) I/O (A9) I/O (19) I/O (18) I/O I/O I/O (A10) I/O (A11) VCC I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 , GCK8 (A15) VCC GND I/O, PGCK1, GCK1 (A16) I/O (A17)

P2 P92 P128 P142 P155 VCC* P183 VCC* VCC* P3 P93 P129 P143 P156 J3 P184 E8 C10 P4 P94 P130 P144 P157 J2 P185 B7 D10 P95 P131 P145 P158 J1 P186 A7 A9 P96 P132 P146 P159 H1 P187 C7 B9 P160 H2 P188 D7 C9 P161 H3 P189 E7 D9 P5 P97 P133 P147 P162 G1 P190 A6 A8 P6 P98 P134 P148 P163 G2 P191 B6 B8 VCC* VCC* VCC* P135 P149 P164 F1 P192 A5 B6 P136 P150 P165 E1 P193 B5 A5 P137 P151 P166 GND* P194 GND* GND* F2 P195 D6 C6 P167 D1 P196 C5 B5 P152 P168 C1 P197 A4 A4 P153 P169 E2 P198 E6 C5 P7 P99 P138 P154 P170 F3 P199 B4 B4 P8 P100 P139 P155 P171 D2 P200 D5 A3 P140 P156 P172 B1 P201 B3 B3 P141 P157 P173 E3 P202 F6 B2 P9 P1 P142 P158 P174 C2 P203 A2 A2 P10 P2 P143 P159 P175 B2 P204 C3 C3

62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119

P11 P12 P13

P3 P4 P5

P144 P160 P176 VCC* P205 VCC* VCC* P1 P1 P1 GND* P2 GND* GND* P2 P2 P2 C3 P4 D4 B1

122

P14

P6

P3

P3

P3

C4

P5

B1

C2

125

I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O

P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26

P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20

P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24

P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26

P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30

B3 C5 A2 B4 C6 A3 B5 B6 GND* A4 A5 B7 A6 VCC* C8 A7 B8 A8 B9 C9 GND* VCC* C10 B10 A9 A10 A11 C11 VCC* B11 A12

P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34

C2 E5 D3 C1 D2 G6 E4 D1 GND* F5 E1 F4 F3 VCC* G4 G3 G2 G1 G5 H3 GND* VCC* H4 H5 J2 J1 J3 J4 VCC* K2 K3

D2 D3 E4 C1 D1 E3 E2 E1 GND* G3 G2 G1 H3 VCC* J2 J1 K2 K3 K1 L1 GND* VCC* L2 L3 L4 M1 M2 M3 VCC* P1 P2

128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203

4-118

March 30, 1998 (Version 1.5)

XC4010E/XL Pad Name

PC 84

PQ TQ 100 144

PQ 160

TQ 176

PG 191

PQ/ HQ 208

BG 225

BG 256

Bndry Scan

XC4010E/XL Pad Name

PC 84

PQ TQ 100 144

PQ 160

TQ 176

PG 191

PQ/ HQ 208

BG 225

BG 256

Bndry Scan

I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 , GCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 , GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 , GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 , GCK5

P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57

P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57

P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76

P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84

P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47

B12 A13 GND* B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 GND* A18 VCC* C16 B17

P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57

J6 R1 L1 P3 GND* GND* L3 T2 M1 U1 K5 T3 M2 U2 L4 V1 N1 T4 M3 U3 N2 V2 K6 W1 P1 V3 N3 W2 GND* GND* P2 Y1 VCC* VCC* M4 W3 R2 Y2 P3 L5 N4 R3 P4 K7 M5 R4 N5 GND* R5 M6 N6 P6 VCC* R6 M7 R7 L7 N8 P8 VCC* GND* L8 P9 R9 N9 M9 L9 VCC* N10 K9 R11 P11 GND* R12 L10 P12 M11 R13 N12 P13 K10 R14 N13 W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 GND* W7 Y7 V8 W8 VCC* Y8 U9 V10 Y10 Y11 W11 VCC* GND* V11 U11 Y12 W12 V12 U12 VCC* Y15 V14 W15 Y16 GND* Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19

206 209 212 215 218 221 224 227 230 233 236 239 242 245 246 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 346 349 352 355 358 361 364 367 370

P48 E16 P58 P49 C17 P59 P50 D17 P60 P51 B18 P61 P52 E17 P62 P53 F16 P63 P54 C18 P64 D18 P65 F17 P66 P55 GND* P67 P56 E18 P68 P57 F18 P69 P58 G17 P70 P59 G18 P71 VCC* P60 H16 P72 P61 H17 P73 P62 H18 P74 P63 J18 P75 P64 J17 P76 P65 J16 P77 P66 VCC* P78 P67 GND* P79 P68 K16 P80 P69 K17 P81 P70 K18 P82 P71 L18 P83 P72 L17 P84 P73 L16 P85 VCC* P74 M18 P86 P75 M17 P87 P76 N18 P88 P77 P18 P89 P78 GND* P90 N17 P91 R18 P92 P79 T18 P93 P80 P17 P94 P81 N16 P95 P82 T17 P96 P83 R17 P97 P84 P16 P98 P85 U18 P99 P86 T16 P100

P87 GND* P101 GND* GND* P88 U17 P103 P14 Y20 P89 VCC* P106 VCC* VCC* P90 V18 P108 M12 V19 P91 T15 P109 P15 U19 P92 U16 P110 N14 U18

I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O GND I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 , GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 , GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O GND I/O I/O VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7)

P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72

P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76

P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106

P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118

P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130

T14 U15 V17 V16 T13 U14 V15 V14 GND* U13 V13 VCC* U12 V12 T11 U11 V11 V10 U10 T10 VCC* GND* T9 U9 V9 V8 U8 T8 V7 U7 VCC* V6 U6 GND* V5 V4 U5 T6 V3 V2 U4 T5 U3 T4

P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152

L11 M13 J10 L12 M15 L13 L14 K11 GND* K13 K14 VCC* K15 J12 J13 J14 J15 J11 H13 H14 VCC* GND* H12 H11 G14 G15 G13 G12 G11 F15 VCC* F14 F13 GND* E13 D15 F11 D14 E12 C15 D13 C14 F10 B15

T17 V20 T19 T20 R18 R19 R20 P18 GND* N19 N20 VCC* M17 M18 M20 L19 L18 L20 K20 K19 VCC* GND* K18 K17 J20 J19 J18 J17 H19 H18 VCC* G19 F20 GND* D20 E18 D19 C20 E17 D18 C19 B20 C18 B19

373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484

P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84

P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90

P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126

P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140

P131 V1 P153 C13 A20 P132 VCC* P154 VCC* VCC* P133 U2 P159 A15 A19 P134 GND* P160 GND* GND* P135 T3 P161 A14 B18 P136 U1 P162 B13 B17 P137 P3 P163 E11 C17 P138 R2 P164 C12 D16 P139 T2 P165 A13 A18 P140 N3 P166 B12 A17 P141 P2 P167 A12 A16 P142 T1 P168 C11 C15 R1 P169 B11 B15 N2 P170 E10 A15 P143 GND* P171 GND* GND* P144 P1 P172 A11 B14 P145 N1 P173 D10 A14 VCC* VCC* VCC* P146 M2 P174 A10 C12 P147 M1 P175 D9 B12 P148 L3 P176 C9 A12 P149 L2 P177 B9 B11 P150 L1 P178 A9 C11 P151 K1 P179 E9 A11 P152 K2 P180 C8 A10 P153 K3 P181 B8 B10

0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59

March 30, 1998 (Version 1.5)

4-119

XC4000E and XC4000X Series Field Programmable Gate Arrays

PQ/ HQ 208

XC4010E/XL Pad Name

PC 84

PQ TQ 100 144

PQ 160

TQ 176

PG 191

BG 225

BG 256

Bndry Scan

BG225 B2 R15 A1 H2 J8 A3 E3 F12 L6 P5 6/16/97 B14 A8 H6 J9 B10 E14 G10 L15 P7 VCC Pins H1 H15 GND Pins D12 F8 G7 H7 H8 H9 K8 M8 Not Connected Pins C4 C6 C10 E15 F1 F2 J5 K1 K4 M10 M14 N7 P10 R10 D8 R1 G8 H10 D11 F7 K12 N11 R8 G9 J7 E2 F9 L2 N15 -

GND 6/19/97

P1

P91

P127 P141 P154 GND* P182 GND* GND*

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. = E only = XL only

Additional XC4010E/XL Package Pins

PQ/HQ208 P1 P104 P206 5/27/97 P3 P105 P207 Not Connected Pins P51 P52 P53 P107 P155 P156 P208 P54 P157 P102 P158 -

BG256 C14 F1 P4 U7 A1 H4 U13 A6 C8 F3 J3 P20 V15 Y9 5/27/97 D6 F4 P17 U10 B7 H17 U17 A7 C13 F18 J4 R3 W6 Y13 VCC Pins D11 D14 G4 G17 R2 R4 U15 V7 GND Pins D4 D8 D13 N3 N4 N17 W14 Not Connected Pins A13 B13 B16 C16 D5 D12 F19 G18 H1 M4 M19 N1 T1 T18 U20 W9 W10 W13 Y14 D7 F17 P19 U14 D15 K4 R17 W20 D17 U4 C4 E19 H2 N2 V9 W16 E20 L17 U6 G20 U8 C7 F2 H20 N18 V13 Y6 -

PG191 D3 R15 C7 K4 T7 5/27/97 D10 C12 K15 T12 D16 D4 M3 VCC Pins J4 GND Pins D9 M16 J15 D15 R3 R4 G3 R9 R10 G16 R16 -

Pin Locations for XC4013E/XL Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information.
XC4013E HT PQ HT PQ/HQ PG BG /XL 144 160 176 208 223 225 Pad Name VCC P128 P142 P155 P183 VCC* VCC* I/O (A8) P129 P143 P156 P184 J3 E8 I/O (A9) P130 P144 P157 P185 J2 B7 I/O P131 P145 P158 P186 J1 A7 (A19) I/O P132 P146 P159 P187 H1 C7 (A18) I/O P160 P188 H2 D7 I/O P161 P189 H3 E7 I/O (A10) P133 P147 P162 P190 G1 A6 I/O (A11) P134 P148 P163 P191 G2 B6 VCC VCC* VCC* I/O H4 C6 I/O G4 F7 I/O P135 P149 P164 P192 F1 A5 I/O P136 P150 P165 P193 E1 B5 GND P137 P151 P166 P194 GND* GND* I/O P195 F2 D6 I/O P167 P196 D1 C5 I/O P152 P168 P197 C1 A4 I/O P153 P169 P198 E2 E6 I/O (A12) P138 P154 P170 P199 F3 B4 I/O (A13) P139 P155 P171 P200 D2 D5 I/O F4 A3 I/O E4 C4 I/O P140 P156 P172 P201 B1 B3 I/O P141 P157 P173 P202 E3 F6 PQ/ HQ 240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 BG Bndry 256 Scan VCC* C10 D10 A9 B9 C9 D9 A8 B8 VCC* A6 C7 B6 A5 GND* C6 B5 A4 C5 B4 A3 D5 C4 B3 B2 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 XC4013E HT PQ HT PQ/HQ PG BG /XL 144 160 176 208 223 225 Pad Name I/O (A14) P142 P158 P174 P203 C2 A2 P143 P159 P175 P204 B2 C3 I/O, SGCK1 , GCK8 (A15) VCC P144 P160 P176 P205 VCC* VCC* GND P1 P1 P1 P2 GND* GND* P2 P2 P2 P4 C3 D4 I/O, PGCK1 , GCK1 (A16) I/O (A17) P3 P3 P3 P5 C4 B1 I/O P4 P4 P4 P6 B3 C2 I/O P5 P5 P5 P7 C5 E5 I/O, TDI P6 P6 P6 P8 A2 D3 I/O, TCK P7 P7 P7 P9 B4 C1 I/O P8 P8 P10 C6 D2 I/O P9 P9 P11 A3 G6 I/O P12 B5 E4 I/O P13 B6 D1 I/O D5 E3 I/O D6 E2 GND P8 P10 P10 P14 GND* GND* I/O P9 P11 P11 P15 A4 F5 I/O P10 P12 P12 P16 A5 E1 I/O, TMS P11 P13 P13 P17 B7 F4 I/O P12 P14 P14 P18 A6 F3 VCC VCC* VCC* PQ/ HQ 240 P238 P239 BG Bndry 256 Scan A2 C3 140 143

P240 P1 P2

VCC* GND* B1

146

P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19

C2 D2 D3 E4 C1 D1 E3 E2 E1 F3 F2 GND* G3 G2 G1 H3 VCC*

149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 -

4-120

March 30, 1998 (Version 1.5)

XC4013E HT /XL 144 Pad Name I/O I/O I/O I/O I/O P13 I/O P14 I/O P15 I/O P16 GND P17 VCC P18 I/O P19 I/O P20 I/O P21 I/O P22 I/O I/O I/O I/O VCC I/O P23 I/O P24 I/O P25 I/O P26 GND P27 I/O I/O I/O I/O I/O I/O I/O P28 I/O P29 I/O P30 I/O P31 I/O P32 I/O, P33 SGCK2 , GCK2 O (M1) P34 GND P35 I (M0) P36 VCC P37 I (M2) P38 I/O, P39 PGCK2 , GCK3 I/O (HDC) P40 I/O P41 I/O P42 I/O P43 P44 I/O (LDC) I/O I/O I/O I/O I/O I/O GND P45 I/O P46 I/O P47 I/O P48 I/O P49 VCC I/O I/O I/O I/O I/O P50 I/O P51 I/O P52 I/O (INIT) P53 VCC P54 GND P55 I/O P56

PQ 160 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37

HT PQ/HQ PG 176 208 223 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 D7 D8 C8 A7 B8 A8 B9 C9 GND* VCC* C10 B10 A9 A10 A11 C11 D11 D12 VCC* B11 A12 B12 A13 GND* D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16

BG 225 F2 F1 G4 G3 G2 G1 G5 H3 GND* VCC* H4 H5 J2 J1 J3 J4 J5 K1 VCC* K2 K3 J6 L1 GND* L2 K4 L3 M1 K5 M2 L4 N1 M3 N2 K6 P1

PQ/ HQ 240 P20 P21 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57

BG Bndry 256 Scan H2 H1 J2 J1 K2 K3 K1 L1 GND* VCC* L2 L3 L4 M1 M2 M3 N1 N2 VCC* P1 P2 R1 P3 GND* T1 R3 T2 U1 T3 U2 V1 T4 U3 V2 W1 V3 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287

P38 P39 P40 P41 P42 P43

P42 P43 P44 P45 P46 P47

P48 P49 P50 P55 P56 P57

C15 N3 GND* GND* A18 P2 VCC* VCC* C16 M4 B17 R2

P58 P59 P60 P61 P62 P63

W2 GND* Y1 VCC* W3 Y2

290 293 294 295

P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62

P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68

P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80

E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 GND* E18 F18 G17 G18 VCC* H16 H17 G15 H15 H18 J18 J17 J16 VCC* GND* K16

P3 L5 N4 R3 P4 K7 M5 R4 N5 P5 L6 GND* R5 M6 N6 P6 VCC* R6 M7 N7 P7 R7 L7 N8 P8 VCC* GND* L8

P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85 P86 P87 P88 P89 P90 P91 P92

W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 W6 Y6 GND* W7 Y7 V8 W8 VCC* Y8 U9 Y9 W10 V10 Y10 Y11 W11 VCC* GND* V11

298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 346 349 352 355 358 361 364 367

XC4013E HT PQ HT PQ/HQ PG BG /XL 144 160 176 208 223 225 Pad Name I/O P57 P63 P69 P81 K17 P9 I/O P58 P64 P70 P82 K18 R9 I/O P59 P65 P71 P83 L18 N9 I/O P72 P84 L17 M9 I/O P73 P85 L16 L9 I/O L15 R10 I/O M15 P10 VCC VCC* VCC* I/O P60 P66 P74 P86 M18 N10 I/O P61 P67 P75 P87 M17 K9 I/O P62 P68 P76 P88 N18 R11 I/O P63 P69 P77 P89 P18 P11 GND P64 P70 P78 P90 GND* GND* I/O N15 M10 I/O P15 N11 I/O P91 N17 R12 I/O P92 R18 L10 I/O P71 P79 P93 T18 P12 I/O P72 P80 P94 P17 M11 I/O P65 P73 P81 P95 N16 R13 I/O P66 P74 P82 P96 T17 N12 I/O P67 P75 P83 P97 R17 P13 I/O P68 P76 P84 P98 P16 K10 I/O P69 P77 P85 P99 U18 R14 I/O, P70 P78 P86 P100 T16 N13 SGCK3 , GCK4 GND P71 P79 P87 P101 GND* GND* DONE P72 P80 P88 P103 U17 P14 VCC P73 P81 P89 P106 VCC* VCC* PROP74 P82 P90 P108 V18 M12 GRAM I/O (D7) P75 P83 P91 P109 T15 P15 I/O, P76 P84 P92 P110 U16 N14 PGCK3 , GCK5 I/O P77 P85 P93 P111 T14 L11 I/O P78 P86 P94 P112 U15 M13 I/O R14 N15 I/O R13 M14 I/O (D6) P79 P87 P95 P113 V17 J10 I/O P80 P88 P96 P114 V16 L12 I/O P89 P97 P115 T13 M15 I/O P90 P98 P116 U14 L13 I/O P117 V15 L14 I/O P118 V14 K11 GND P81 P91 P99 P119 GND* GND* I/O R12 L15 I/O R11 K12 I/O P82 P92 P100 P120 U13 K13 I/O P83 P93 P101 P121 V13 K14 VCC VCC* VCC* I/O (D5) P84 P94 P102 P122 U12 K15 P85 P95 P103 P123 V12 J12 I/O (CS0) I/O P104 P124 T11 J13 I/O P105 P125 U11 J14 I/O P86 P96 P106 P126 V11 J15 I/O P87 P97 P107 P127 V10 J11 I/O (D4) P88 P98 P108 P128 U10 H13 I/O P89 P99 P109 P129 T10 H14 VCC P90 P100 P110 P130 VCC* VCC* GND P91 P101 P111 P131 GND* GND* I/O (D3) P92 P102 P112 P132 T9 H12 P93 P103 P113 P133 U9 H11 I/O (RS) I/O P94 P104 P114 P134 V9 G14 I/O P95 P105 P115 P135 V8 G15 I/O P116 P136 U8 G13 I/O P117 P137 T8 G12 I/O (D2) P96 P106 P118 P138 V7 G11 I/O P97 P107 P119 P139 U7 F15 VCC VCC* VCC* I/O P98 P108 P120 P140 V6 F14 I/O P99 P109 P121 P141 U6 F13 I/O R8 G10

PQ/ HQ 240 P93 P94 P95 P96 P97 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118

BG Bndry 256 Scan U11 Y12 W12 V12 U12 V13 Y14 VCC* Y15 V14 W15 Y16 GND* V15 W16 Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436

P119 P120 P121 P122 P123 P124

GND* Y20 VCC* V19 U19 U18

439 442

P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P159 P160 P161 P162 P163 P164

T17 V20 U20 T18 T19 T20 R18 R19 R20 P18 GND* P20 N18 N19 N20 VCC* M17 M18 M20 L19 L18 L20 K20 K19 VCC* GND* K18 K17 J20 J19 J18 J17 H19 H18 VCC* G19 F20 G18

445 448 451 454 457 460 463 466 469 472 475 478 481 484 487 490 493 496 499 502 505 508 511 514 517 520 523 526 529 532 535 538 541

March 30, 1998 (Version 1.5)

4-121

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4013E HT PQ HT PQ/HQ PG BG /XL 144 160 176 208 223 225 Pad Name I/O R7 E15 GND P100 P110 P122 P142 GND* GND* I/O R6 E14 I/O R5 F12 I/O P143 V5 E13 I/O P144 V4 D15 I/O P111 P123 P145 U5 F11 I/O P112 P124 P146 T6 D14 I/O (D1) P101 P113 P125 P147 V3 E12 P148 V2 C15 I/O (RCLK, P102 P114 P126 RDY/ BUSY) I/O P103 P115 P127 P149 U4 D13 I/O P104 P116 P128 P150 T5 C14 I/O (D0, P105 P117 P129 P151 U3 F10 DIN) P106 P118 P130 P152 T4 B15 I/O, SGCK4 , GCK6 (DOUT) CCLK P107 P119 P131 P153 V1 C13 VCC P108 P120 P132 P154 VCC* VCC* O, TDO P109 P121 P133 P159 U2 A15 GND P110 P122 P134 P160 GND* GND* P111 P123 P135 P161 T3 A14 I/O (A0, WS) P112 P124 P136 P162 U1 B13 I/O, PGCK4 , GCK7 (A1) I/O P113 P125 P137 P163 P3 E11 I/O P114 P126 P138 P164 R2 C12 I/O (CS1, P115 P127 P139 P165 T2 A13 A2) I/O (A3) P116 P128 P140 P166 N3 B12 I/O P4 F9 I/O N4 D11 I/O P117 P129 P141 P167 P2 A12 I/O P130 P142 P168 T1 C11 I/O P169 R1 B11 I/O P170 N2 E10 GND P118 P131 P143 P171 GND* GND* I/O P119 P132 P144 P172 P1 A11 I/O P120 P133 P145 P173 N1 D10 I/O M4 C10 I/O L4 B10 VCC VCC* VCC* I/O (A4) P121 P134 P146 P174 M2 A10 I/O (A5) P122 P135 P147 P175 M1 D9 I/O P148 P176 L3 C9 I/O P136 P149 P177 L2 B9 I/O P123 P137 P150 P178 L1 A9 (A21) I/O P124 P138 P151 P179 K1 E9 (A20) I/O (A6) P125 P139 P152 P180 K2 C8 I/O (A7) P126 P140 P153 P181 K3 B8 GND P127 P141 P154 P182 GND* GND* PQ/ HQ 240 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174

BG Bndry 256 Scan F19 GND* F18 E19 D20 E18 D19 C20 E17 D18 544 547 550 553 556 559 562 565 568

Additional XC4013E/XL Package Pins

PQ/HQ208 P1 P102 P157 5/5/97 P3 P104 P158 Not Connected Pins P51 P52 P105 P107 P206 P207 P53 P155 P208 P54 P156 -

PG223 D3 R10 C7 G16 R9 5/5/97 D10 R15 C12 K4 R16 VCC Pins D16 J4 GND Pins D4 D9 K15 M3 T7 T12 J15 D15 M16 R4 G3 R3 -

P175 P176 P177 P178

C19 B20 C18 B19

571 574 577 580

P179 P180 P181 P182 P183 P184

A20 VCC* A19 GND* B18 B17

0 2 5

BG225 B2 R1 A1 G8 H8 J9 5/5/97 B14 R8 A8 G9 H9 K8 VCC Pins D8 R15 GND Pins D12 H2 H10 M8 H1 F8 H6 J7 H15 G7 H7 J8 -

P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211

C17 D16 A18 A17 C16 B16 A16 C15 B15 A15 GND* B14 A14 C13 B13 VCC* C12 B12 A12 B11 C11 A11 A10 B10 GND*

8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 -

The BG225 package pins in this table are bonded to an internal Ground plane on the XC4013E die. They must all be externally connected to Ground.
PQ/HQ240 P22 P204 P195 6/9/97 P37 P219 GND Pins P83 P98 Not Connected Pins P143 P158 -

Pins marked with this symbol are used for Ground connections on some revisions of the device. These pins may not physically connect to anything on the current device revision. However, they should be externally connected to Ground, if possible.
BG256 C14 E20 K4 R4 U15 A1 G20 U4 A7 J4 Y13 6/4/97 D6 F1 L17 R17 V7 B7 H4 U8 A13 M4 VCC Pins D7 D11 F4 F17 P4 P17 U6 U7 W20 GND Pins D4 D8 H17 N3 U13 U17 Not Connected Pins C8 D12 M19 V9 D14 G4 P19 U10 D13 N4 W14 H20 W9 D15 G17 R2 U14 D17 N17 J3 W13 -

6/9/97

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. = E only, = XL only

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March 30, 1998 (Version 1.5)

Pin Locations for XC4020E/XL Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information.
XC4020E/XL Pad Name VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O, SGCK1 , GCK8 (A15) VCC GND I/O, PGCK1 , GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O HT 144 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 PQ 160 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 HT 176 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 HQ208 PQ208 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 PG 223 VCC* J3 J2 J1 H1 H2 H3 G1 G2 VCC* H4 G4 F1 E1 GND* F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 VCC* GND* C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 GND* A4 A5 B7 A6 VCC* D7 D8 C8 A7 B8 A8 B9 C9 GND* VCC* C10 B10 A9 A10 A11 C11 D11 D12 VCC* B11 HQ240 PQ240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P38 P39 P40 P41 BG Bndry 256 Scan VCC* C10 86 D10 89 A9 92 B9 95 C9 98 D9 101 A8 104 B8 107 C8 110 A7 113 VCC* A6 116 C7 119 B6 122 A5 125 GND* C6 128 B5 131 A4 134 C5 137 B4 140 A3 143 D5 152 C4 155 B3 158 B2 161 A2 164 C3 167 VCC* GND* B1 C2 D2 D3 E4 C1 D1 E3 E2 E1 F3 F2 GND* G3 G2 G1 H3 VCC* H2 H1 J4 J3 J2 J1 K2 K3 K1 L1 GND* VCC* L2 L3 L4 M1 M2 M3 M4 N1 N2 VCC* P1 170 173 176 179 182 185 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 278 281 284 XC4020E/XL Pad Name I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 , GCK2 O (M1) GND I (M0) VCC I (M2) I/O PGCK2 , GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O HT PQ HT 144 160 176 P24 P26 P30 P25 P27 P31 P26 P28 P32 P27 P29 P33 P30 P34 P31 P35 P28 P32 P36 P29 P33 P37 P30 P34 P38 P31 P35 P39 P32 P36 P40 P33 P37 P41 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 HQ208 PQ208 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 PG 223 A12 B12 A13 GND* D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 GND* A18 VCC* C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 GND* E18 F18 G17 G18 VCC* H16 H17 G15 H15 H18 J18 J17 J16 VCC* GND* K16 K17 K18 L18 L17 L16 L15 M15 VCC* M18 M17 N18 P18 GND* N15 P15 N17 R18 T18 P17 HQ240 PQ240 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 BG Bndry 256 Scan P2 287 R1 290 P3 293 GND* T1 296 R3 299 T2 302 U1 305 T3 308 U2 311 V1 320 T4 323 U3 326 V2 329 W1 332 V3 335 W2 GND* Y1 VCC* W3 Y2 W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 W6 Y6 GND* W7 Y7 V8 W8 VCC* Y8 U9 V9 W9 Y9 W10 V10 Y10 Y11 W11 VCC* GND* V11 U11 Y12 W12 V12 U12 Y13 W13 V13 Y14 VCC* Y15 V14 W15 Y16 GND* V15 W16 Y17 V16 W17 Y18 338 341 342 343 346 349 352 355 358 367 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484

March 30, 1998 (Version 1.5)

4-123

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4020E/XL Pad Name I/O I/O I/O I/O I/O I/O, SGCK3 , GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 , GCK5 I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 , GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 , GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) HT PQ HT 144 160 176 P65 P73 P81 P66 P74 P82 P67 P75 P83 P68 P76 P84 P69 P77 P85 P70 P78 P86 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 HQ208 PQ208 P95 P96 P97 P98 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 PG 223 N16 T17 R17 P16 U18 T16 GND* U17 VCC* V18 T15 U16 T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 GND* R12 R11 U13 V13 VCC* U12 V12 T11 U11 V11 V10 U10 T10 VCC* GND* T9 U9 V9 V8 U8 T8 V7 U7 VCC* V6 U6 R8 R7 GND* R6 R5 V5 V4 U5 T6 V3 V2 U4 T5 U3 T4 V1 VCC* U2 GND* T3 U1 P3 R2 T2 N3 HQ240 PQ240 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 BG Bndry 256 Scan U16 493 V17 496 W18 499 Y19 502 V18 505 W19 508 GND* Y20 VCC* V19 U19 U18 T17 V20 U20 T18 T19 T20 R18 R19 R20 P18 GND* P20 N18 N19 N20 VCC* M17 M18 M19 M20 L19 L18 L20 K20 K19 VCC* GND* K18 K17 J20 J19 J18 J17 H20 H19 H18 VCC* G19 F20 G18 F19 GND* F18 E19 D20 E18 D19 C20 E17 D18 C19 B20 C18 B19 A20 VCC* A19 GND* B18 B17 C17 D16 A18 A17 511 514 517 520 523 526 535 538 541 544 547 550 553 556 559 562 565 568 574 577 580 583 586 589 592 595 598 601 604 607 610 613 619 622 625 628 631 634 637 640 643 646 649 652 655 658 667 670 673 676 0 2 5 8 11 14 17 XC4020E/XL Pad Name I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND HT 144 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 PQ 160 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 HT 176 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 HQ208 PQ208 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 PG 223 P4 N4 P2 T1 R1 N2 GND* P1 N1 M4 L4 VCC* M2 M1 L3 L2 L1 K1 K2 K3 GND* HQ240 PQ240 P189 P190 P191 P192 P193 P194 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211 BG Bndry 256 Scan C16 26 B16 29 A16 32 C15 35 B15 38 A15 41 GND* B14 44 A14 47 C13 50 B13 53 VCC* A13 56 D12 59 C12 62 B12 65 A12 68 B11 71 C11 74 A11 77 A10 80 B10 83 GND* -

6/24/97

= E only = XL only

Additional XC4020E/XL Package Pins

PQ/HQ208 P1 P102 P157 5/5/97 P3 P104 P158 Not Connected Pins P51 P52 P105 P107 P206 P207 P53 P155 P208 P54 P156 -

PG223 D3 R10 C7 G16 R9 5/5/97 D10 R15 C12 K4 R16 VCC Pins D16 J4 GND Pins D4 D9 K15 M3 T7 T12 J15 D15 M16 R4 G3 R3 -

PQ/HQ240 P22 P204 P195 6/9/97 P37 P219 GND Pins P83 P98 Not Connected Pins P143 P158 -

Pins marked with this symbol are used for Ground connections on some revisions of the device. These pins may not physically connect to anything on the current device revision. However, they should be externally connected to Ground, if possible.
BG256 C14 E20 K4 R4 U15 A1 G20 U4 6/17/97 D6 F1 L17 R17 V7 B7 H4 U8 VCC Pins D7 D11 F4 F17 P4 P17 U6 U7 W20 GND Pins D4 D8 H17 N3 U13 U17 D14 G4 P19 U10 D13 N4 W14 D15 G17 R2 U14 D17 N17 -

4-124

March 30, 1998 (Version 1.5)

Pin Locations for XC4025E, XC4028EX/XL Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information.
XC4025E, XC4028 EX/XL Pad Name VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O I/O (A14) I/O, SGCK1 , GCK8 (A15) VCC GND I/O, PGCK1 , GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O HQ HQ PG 160 208 223 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 HQ 240 BG 256 PG 299 HQ 304 P38 P37 P36 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P10 P9 P8 P7 P6 P5 P4 P3 P2 BG Bndry 352 Scan VCC* D14 C14 A15 B15 C15 D15 A16 B16 GND* C16 B17 C17 B18 VCC* C18 D17 A20 B19 GND* C19 D18 A21 B20 C20 B21 B22 C21 GND* VCC* D20 A23 D21 C22 B24 C23 D22 C24 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 XC4025E, XC4028 HQ HQ PG HQ EX/XL 160 208 223 240 Pad Name I/O GND P10 P14 GND* P14 I/O P11 P15 A4 P15 I/O P12 P16 A5 P16 I/O, TMS P13 P17 B7 P17 I/O P14 P18 A6 P18 VCC VCC* P19 I/O D7 P20 I/O D8 P21 I/O I/O GND P22 I/O I/O I/O P19 C8 P23 I/O P20 A7 P24 I/O P15 P21 B8 P25 I/O P16 P22 A8 P26 I/O P17 P23 B9 P27 I/O P18 P24 C9 P28 GND P19 P25 GND* P29 VCC P20 P26 VCC* P30 I/O P21 P27 C10 P31 I/O P22 P28 B10 P32 I/O P23 P29 A9 P33 I/O P24 P30 A10 P34 I/O P31 A11 P35 I/O P32 C11 P36 I/O I/O GND P37 I/O I/O I/O D11 P38 I/O D12 P39 VCC VCC* P40 I/O P25 P33 B11 P41 I/O P26 P34 A12 P42 I/O P27 P35 B12 P43 I/O P28 P36 A13 P44 GND P29 P37 GND* P45 I/O I/O I/O D13 P46 I/O D14 P47 I/O P38 B13 P48 I/O P39 A14 P49 I/O P30 P40 A15 P50 I/O P31 P41 C13 P51 GND VCC I/O I/O I/O P32 P42 B14 P52 I/O P33 P43 A16 P53 I/O P34 P44 B15 P54 I/O P35 P45 C14 P55 I/O P36 P46 A17 P56 I/O, P37 P47 B16 P57 SGCK2 , GCK2 O (M1) P38 P48 C15 P58 GND P39 P49 GND* P59 BG 256 GND* G3 G2 G1 H3 VCC* H2 H1 GND* J4 J3 J2 J1 K2 K3 K1 L1 GND* VCC* L2 L3 L4 M1 M2 M3 M4 GND* N1 N2 VCC* P1 P2 R1 P3 GND* T1 R3 T2 U1 T3 U2 GND* VCC* V1 T4 U3 V2 W1 V3 PG 299 B5 GND* B6 D8 C7 B7 VCC* C8 E9 A7 D9 GND* B8 A8 C9 B9 E10 A9 D10 C10 GND* VCC* B10 B11 C11 E11 D11 A12 B12 A13 GND* C12 D12 E12 B13 VCC* A14 C13 B14 D13 GND* B15 E13 C14 A17 D14 B16 C15 E14 GND* VCC* A18 D15 C16 B17 B18 E15 D16 C17 HQ 304 P288 P287 P286 P285 P284 P283 P282 P280 P279 P278 P277 P276 P275 P274 P273 P272 P271 P270 P269 P268 P267 P266 P265 P264 P263 P262 P261 P260 P259 P258 P257 P256 P255 P253 P252 P251 P250 P249 P248 P247 P246 P245 P244 P243 P242 P241 P240 P239 P238 P237 P236 P235 P234 P233 P232 BG Bndry 352 Scan G26 GND* J23 J24 H25 K23 VCC* K24 J25 L24 K25 GND* L25 L26 M23 M24 M25 M26 N24 N25 GND* VCC* N26 P25 P23 P24 R26 R25 R24 R23 GND* T26 T25 T23 V26 VCC* U24 V25 V24 U23 GND* Y26 W25 W24 V23 AA26 Y25 Y24 AA25 GND* VCC* AB25 AA24 Y23 AC26 AA23 AB24 AD25 AC24 239 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287 290 293 296 299 302 305 308 311 314 317 320 323 326 329 332 335 338 341 344 347 350 353 356 359 362 365 368 371 374 377 380 383

P183 VCC* P212 VCC* VCC* P184 J3 P213 C10 K2 P185 J2 P214 D10 K3 P186 J1 P215 A9 K5 P187 H1 P216 B9 K4 P188 H2 P217 C9 J1 P189 H3 P218 D9 J2 P190 G1 P220 A8 H1 P191 G2 P221 B8 J3 GND* GND* J4 J5 C8 H2 A7 G1 VCC* P222 VCC* VCC* H4 P223 A6 H3 G4 P224 C7 G2 P192 F1 P225 B6 H4 P193 E1 P226 A5 F2 P194 GND* P227 GND* GND* H5 G3 P195 F2 P228 C6 D1 P196 D1 P229 B5 G4 P197 C1 P230 A4 E2 P198 E2 P231 C5 F3 P199 F3 P232 B4 G5 P200 D2 P233 A3 C1 GND* GND* VCC* VCC* F4 E3 F4 P234 D5 D2 E4 P235 C4 C2 P201 B1 P236 B3 F5 P202 E3 P237 B2 E4 P203 C2 P238 A2 D3 P204 B2 P239 C3 C3

P160 P205 VCC* P240 VCC* VCC* P1 VCC* P1 P2 GND* P1 GND* GND* P304 GND* P2 P4 C3 P2 B1 D4 P303 D23

194

P3 P4 P5 P6 P7 P8 P9 -

P5 P6 P7 P8 P9 P10 P11 P12 P13 -

C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 -

P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 -

C2 B2 P302 C25 D2 B3 P301 D24 D3 E6 P300 E23 E4 D5 P299 C26 C1 C4 P298 E24 A3 P297 F24 D6 P296 E25 VCC* VCC* VCC* GND* GND* GND* D1 E7 P295 D26 E3 B4 P294 G24 E2 C5 P293 F25 E1 A4 P292 F26 F3 D7 P291 H23 F2 C6 P290 H24 E8 P289 G25

197 200 203 206 209 212 215 218 221 224 227 230 233 236

W2 A20 P231 AB23 GND* GND* P230 GND*

386 -

March 30, 1998 (Version 1.5)

4-125

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4025E, XC4028 HQ HQ PG HQ EX/XL 160 208 223 240 Pad Name I (M0) P40 P50 A18 P60 VCC P41 P55 VCC* P61 I (M2) P42 P56 C16 P62 I/O, P43 P57 B17 P63 PGCK2 , GCK3 I/O (HDC) P44 P58 E16 P64 I/O P45 P59 C17 P65 I/O P46 P60 D17 P66 I/O P47 P61 B18 P67 I/O (LDC) P48 P62 E17 P68 I/O I/O VCC GND I/O P49 P63 F16 P69 I/O P50 P64 C18 P70 I/O P65 D18 P71 I/O P66 F17 P72 I/O E15 P73 I/O F15 P74 I/O I/O GND P51 P67 GND* P75 I/O P52 P68 E18 P76 I/O P53 P69 F18 P77 I/O P54 P70 G17 P78 I/O P55 P71 G18 P79 VCC VCC* P80 I/O P72 H16 P81 I/O P73 H17 P82 I/O I/O GND P83 I/O I/O I/O G15 P84 I/O H15 P85 I/O P56 P74 H18 P86 I/O P57 P75 J18 P87 I/O P58 P76 J17 P88 I/O (INIT) P59 P77 J16 P89 VCC P60 P78 VCC* P90 GND P61 P79 GND* P91 I/O P62 P80 K16 P92 I/O P63 P81 K17 P93 I/O P64 P82 K18 P94 I/O P65 P83 L18 P95 I/O P84 L17 P96 I/O P85 L16 P97 I/O I/O GND P98 I/O I/O I/O L15 P99 I/O M15 P100 VCC VCC* P101 I/O P66 P86 M18 P102 I/O P67 P87 M17 P103 I/O P68 P88 N18 P104 I/O P69 P89 P18 P105 GND P70 P90 GND* P106 I/O I/O I/O N15 P107 I/O P15 P108 I/O P91 N17 P109 XC4025E, XC4028 EX/XL Pad Name I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 , GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 , GCK5 I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O

BG 256

PG 299

HQ 304

BG Bndry 352 Scan 389 390 391

HQ HQ PG 160 208 223 P71 P72 P73 P74 P75 P76 P77 P78 P92 P93 P94 P95 P96 P97 P98 P99 P100 R18 T18 P17 N16 T17 R17 P16 U18 T16

HQ 240

BG 256

PG 299

HQ 304

BG Bndry 352 Scan 550 553 556 559 562 565 568 571 574 577 580

Y1 C18 P229 AD24 VCC* VCC* P228 VCC* W3 D17 P227 AC23 Y2 B19 P226 AE24

W4 V4 U5 Y3 Y4 VCC* GND* V5 W5 Y5 V6 W6 Y6 GND* W7 Y7 V8 W8 VCC* Y8 U9 GND* V9 W9 Y9 W10 V10 Y10 Y11 W11 VCC* GND* V11 U11 Y12 W12 V12 U12 Y13 W13 GND* V13 Y14 VCC* Y15 V14 W15 Y16 GND* V15 W16 Y17

C19 F16 E17 D18 C20 F17 G16 VCC* GND* D19 E18 D20 G17 F18 H16 E19 F19 GND* H17 G18 G19 H18 VCC* J16 G20 J17 H19 GND* H20 J18 J19 K16 J20 K17 K18 K19 VCC* GND* L19 L18 L16 L17 M20 M19 N20 M18 GND* M17 M16 N19 P20 VCC* N18 P19 N17 R19 GND* N16 P18 U20 P17 T19

P225 P224 P223 P222 P221 P220 P219 P218 P217 P216 P215 P214 P213 P212 P211 P210 P209 P208 P207 P206 P204 P203 P202 P201 P200 P199 P198 P197 P196 P195 P194 P193 P192 P191 P190 P189 P188 P187 P186 P185 P184 P183 P182 P181 P180 P179 P178 P177 P175 P174 P173 P172 P171 P170 P169 P168 P167 P166

AD23 AC22 AF24 AD22 AE23 AE22 AF23 VCC* GND* AD20 AE21 AF21 AC19 AD19 AE20 AF20 AC18 GND* AD18 AE19 AC17 AD17 VCC* AE18 AF18 AE17 AE16 GND* AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 VCC* GND* AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 GND* AE11 AD11 AF9 AD10 VCC* AE9 AD9 AC10 AF7 GND* AE8 AD8 AC9 AF6 AE7

394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484 487 490 493 496 499 502 505 508 511 514 517 520 523 526 529 532 535 538 541 544 547

P110 V16 R18 P165 AD7 P111 W17 P16 P164 AE6 P112 Y18 V20 P163 AE5 GND* GND* GND* VCC* VCC* VCC* R17 P162 AD6 T18 P161 AC7 P113 U16 U19 P160 AF4 P114 V17 V19 P159 AF3 P115 W18 R16 P158 AD5 P116 Y19 T17 P157 AE3 P117 V18 U18 P156 AD4 P118 W19 X20 P155 AC5

P79 P80 P81 P82 P83 P84

P101 GND* P119 GND* GND* P154 GND* P103 U17 P120 Y20 V18 P153 AD3 P106 VCC* P121 VCC* VCC* P152 VCC* P108 V18 P122 V19 U17 P151 AC4 P109 P110 T15 U16 P123 P124 U19 U18 W19 W18 P150 P149 AD2 AC3

583 586

P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 -

P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 -

T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 GND* R12 R11 U13 V13 VCC* U12 V12 T11 U11 V11 V10 U10 T10 VCC* GND* T9 U9 V9 V8 U8 T8 -

P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 -

T17 V20 U20 T18 VCC* GND* T19 T20 R18 R19 R20 P18 GND* P20 N18 N19 N20 VCC* M17 M18 GND* M19 M20 L19 L18 L20 K20 K19 VCC* GND* K18 K17 J20 J19 J18 J17 H20

T15 U16 V17 X18 U15 T14 VCC* GND* W17 V16 X17 U14 V15 T13 W16 W15 GND* U13 V14 W14 V13 VCC* T12 X14 U12 W13 GND* X13 V12 W12 T11 X12 U11 V11 W11 VCC* GND* W10 V10 T10 U10 X9 W9 X8

P148 P147 P146 P145 P144 P143 P142 P141 P140 P139 P138 P137 P136 P135 P134 P133 P132 P131 P130 P129 P127 P126 P125 P124 P123 P122 P121 P120 P119 P118 P117 P116 P115 P114 P113 P112 P111 P110 P109 P108 P107

AB4 AD1 AA4 AA3 AB2 AC1 VCC* GND* Y3 AA2 AA1 W4 W3 Y2 Y1 V4 GND* V3 W2 U4 U3 VCC* V2 V1 U2 T2 GND* T1 R4 R3 R2 R1 P3 P2 P1 VCC* GND* N2 N4 N3 M1 M2 M3 M4

589 592 595 598 601 604 607 610 613 616 619 622 625 628 631 634 637 640 643 646 649 652 655 658 661 664 667 670 673 676 679 682 685 688 691 694 697

4-126

March 30, 1998 (Version 1.5)

XC4025E, XC4028 EX/XL Pad Name I/O GND I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/ BUSY) I/O I/O I/O I/O I/O (D0, DIN) I/O, SGCK4 , GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 , GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC

HQ HQ PG 160 208 223 P106 P107 P108 P109 P110 P111 P112 P113 P114

HQ 240

BG 256

PG 299

HQ 304 P106 P105 P104 P103 P102 P101 P99 P98 P97 P96 P95 P94 P93 P92 P91 P90 P89 P88 P87 P86 P85

BG Bndry 352 Scan L1 GND* L2 L3 J1 K3 VCC* J2 J3 K4 G1 GND* H2 H3 J4 F1 G2 G3 F2 E2 GND* VCC* F3 G4 700 703 706 709 712 715 718 721 724 727 730 733 736 739 742 745 748 751 754

V9 P158 GND* GND* U9 T9 P138 V7 P159 H19 W8 P139 U7 P160 H18 X7 VCC* P161 VCC* VCC* P140 V6 P162 G19 V8 P141 U6 P163 F20 W7 R8 P164 G18 U8 R7 P165 F19 W6 P142 GND* P166 GND* GND* T8 V7 R6 P167 F18 X4 R5 P168 E19 U7 P143 V5 P169 D20 W5 P144 V4 P170 E18 V6 P145 U5 P171 D19 T7 P146 T6 P172 C20 X3 GND* GND* VCC* VCC* P147 V3 P173 E17 U6 P148 V2 P174 D18 V5

XC4025E, XC4028 EX/XL Pad Name I/O I/O I/O I/O GND I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND 6/19/97

HQ HQ PG 160 208 223 P134 P135 P136 P137 P138 P139 P140 P141 P174 M2 P175 M1 P176 L3 P177 L2 P178 L1 P179 K1 P180 K2 P181 K3 P182 GND*

HQ 240

BG 256

PG 299

HQ 304

BG Bndry 352 Scan 62 65 68 71 74 77 80 83 86 89 92 95 -

A13 M5 D12 P1 M4 N2 GND* GND* P202 C12 N1 P203 B12 M3 P205 A12 M2 P206 B11 L5 P207 C11 M1 P208 A11 L4 P209 A10 L3 P210 B10 L2 P211 GND* GND*

P51 A9 P50 D11 P49 B11 P48 A11 GND* P47 D12 P46 C12 P45 B12 P44 A12 P43 C13 P42 B13 P41 A13 P40 B14 P39 GND*

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin. = E only = XL only = EX, XL only

Additional XC4025E, XC4028EX/XL Package Pins

HQ208
Not Connected Pins

P115 P149 P116 P150 P117 P151 P118 P152

U4 T5 U3 T4

P175 P176 P177 P178

C19 B20 C18 B19

W4 W3 T6 U5 V4 X1

P84 P83 P82 P81 P80 P79

D2 F4 E3 C2 D3 E4

757 760 763 766 769 772

P1 P3 P51 5/9/97

P52 P53 P54

P102 P104 P105

P107 P155 P156

P157 P158 P206

P207 P208

PG223 P119 P120 P121 P122 P123 P153 V1 P179 A20 V3 P154 VCC* P180 VCC* VCC* P159 U2 P181 A19 U4 P160 GND* P182 GND* GND* P161 T3 P183 B18 W2 U1 P184 B17 V2 P78 C3 P77 VCC* P76 D4 P75 GND* P74 B3 P73 C4 0 2 5 5/9/97 P125 P163 P126 P164 P127 P165 P128 P129 P130 P131 P132 P133 P3 R2 T2 P185 P186 P187 C17 D16 A18 R5 T4 U3 V1 R4 P5 VCC* GND* U2 T3 U1 P4 R3 N5 T2 R2 GND* N4 P3 P2 N3 VCC* P72 P71 P70 P69 P68 P67 P66 P65 P64 P63 P62 P61 P60 P59 P58 P57 P56 P55 P54 P52 D5 A3 D6 C6 B5 A4 VCC* GND* C7 B6 A6 D8 B7 A7 D9 C9 GND* B8 D10 C10 B9 VCC* 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 VCC Pins

D3 J15 C7 D15 K15 R9

D10 R4 GND Pins C12 G3 M3 R16

D16 R10 D4 G16 M16 T7

J4 R15 D9 K4 R3 T12

P124 P162

HQ240
GND Pins

P166 N3 P188 A17 VCC* GND* P4 P189 C16 N4 P190 B16 P167 P2 P191 A16 P168 T1 P192 C15 P169 R1 P193 B15 P170 N2 P194 A15 P195 P171 GND* P196 GND* P172 P1 P197 B14 P173 N1 P198 A14 M4 P199 C13 L4 P200 B13 VCC* P201 VCC*

P204 5/9/97

P219

Note: These pins may be Not Connected for this device revision, however for compatability with other devices in this package, these pins should be tied to GND.

March 30, 1998 (Version 1.5)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

BG256
VCC Pins

HQ304
Not Connected Pins

C14 D14 F4 K4 P19 U6 U15 A1 D13 H17 U4 W14 5/9/97

D6 D15 F17 L17 R2 U7 V7

GND Pins

D7 E20 G4 P4 R4 U10 W20 D4 G20 N4 U13 -

D11 F1 G17 P17 R17 U14 D8 H4 N17 U17 -

P11 P24 5/15/97

P53 P100

P128 P176

P205 P254

P281 -

Note: In XC4025 (no extension) devices in the HQ304 package, P101 is a No Connect (N.C.) pin. P101 is Vcc in XC4025E and XC4028EX/XL devices. Where necessary for compatibility, this pin can be left unconnected.

B7 D17 N3 U8 -

BG352
VCC Pins

A10 D19 P4 AC14 A1 A22 E26 W26 AF2 AF25 A18 C5 F23 T4 AC11 AD26 5/9/97

A17 G23 U1 AC20 A2 A25 H1 AB1 AF5 AF26 A24 C8 J26 T24 AC16 AE4

PG299
VCC Pins

A2 B20 K1 T20 X15 A5 B1 K20 T5 X11 6/18/97

A6 E1 L20 W1 X19 GND Pins A10 E16 L1 W20 X16

A11 E5 R1 X5 A15 E20 R20 X2 -

A16 F20 T16 X10 A19 F1 T1 X6 -

B2 B25 H4 K1 U26 W23 AE2 AE25 GND Pins A5 A8 A26 B1 H26 N1 AB26 AE1 AF8 AF13 Not Connected Pins B4 B10 C11 D1 K2 L4 U25 AB3 AC21 AC25 AE10 -

D7 K26 Y4 AF10 A14 B26 P26 AE26 AF19 B23 D16 L23 AC2 AD16 -

D13 N23 AC8 AF17 A19 E1 W1 AF1 AF22 C1 D25 T3 AC6 AD21 -

Pin Locations for XC4036EX/XL

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information.
XC4036EX/XL Pad Name VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (A12) PQ 160 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 HQ 208 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 HQ 240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 HQ 304 P38 P37 P36 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 BG 352 VCC* D14 C14 A15 B15 C15 D15 A16 B16 VCC* GND* C16 B17 D16 A18 C17 B18 VCC* C18 D17 A20 B19 GND* C19 D18 A21 B20 C20 B21 B22 PG BG Bndry 411 432 Scan VCC* VCC* W3 D17 110 Y2 A17 113 V4 C18 116 T2 D18 119 U1 B18 122 V6 A19 125 U3 B19 128 R1 C19 131 VCC* VCC* GND* GND* U5 D19 134 T4 A20 137 P2 B20 140 N1 C20 143 R5 C21 146 M2 A22 149 VCC* VCC* L3 B22 152 T6 C22 155 N5 B23 158 M4 A24 161 GND* GND* K2 D22 164 K4 C23 167 P6 B24 170 M6 C24 173 J3 A26 176 H2 C25 179 H4 D24 182 XC4036EX/XL Pad Name I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O VCC GND I/O I/O I/O PQ 160 P155 P156 P157 P158 P159 P160 P1 P2 P3 P4 P5 P6 P7 P8 P9 HQ 208 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 HQ 240 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 HQ 304 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P304 P303 P302 P301 P300 P299 P298 P297 P296 P295 P294 P293 BG 352 C21 GND* VCC* D20 A23 A24 B23 D21 C22 B24 C23 D22 C24 VCC* GND* D23 C25 D24 E23 C26 E24 D25 F23 F24 E25 VCC* GND* D26 G24 F25 PG BG Bndry 411 432 Scan G3 B26 185 GND* GND* VCC* VCC* K6 A27 188 G1 D25 191 E1 C26 194 E3 B27 197 J7 C27 200 H6 B28 203 C3 D27 206 D2 B29 209 E5 C28 212 G7 D28 215 VCC* VCC* GND* GND* H8 D29 218 F6 C30 221 B4 E28 224 D4 E29 227 B2 D30 230 G9 D31 233 F8 E30 236 C5 E31 239 A7 G28 242 A5 G29 245 VCC* VCC* GND* GND* B8 H28 248 C9 H29 251 E9 G30 254

4-128

March 30, 1998 (Version 1.5)

XC4036EX/XL Pad Name I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC

PQ HQ 160 208 P13 P10 P14 P11 P15 P12 P16 P13 P17 P14 P18 P19 P20 P15 P21 P16 P22 P17 P23 P18 P24 P19 P25 P20 P26 P21 P27 P22 P28 P23 P29 P24 P30 P31 P32 P25 P33 P26 P34 P27 P35 P28 P36 P29 P37 P38 P39 P30 P40 P31 P41 P32 P42 P33 P43 P34 P44 P35 P45 P36 P46 P37 P47 P38 P48 P39 P49 P40 P50 P41 P55

HQ 240 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61

HQ 304 P292 P291 P290 P289 P288 P287 P286 P285 P284 P283 P282 P280 P279 P278 P277 P276 P275 P274 P273 P272 P271 P270 P269 P268 P267 P266 P265 P264 P263 P262 P261 P260 P259 P258 P257 P256 P255 P253 P252 P251 P250 P249 P248 P247 P246 P245 P244 P243 P242 P241 P240 P239 P238 P237 P236 P235 P234 P233 P232 P231 P230 P229 P228

BG 352 F26 H23 H24 G25 G26 GND* J23 J24 H25 K23 VCC* K24 J25 J26 L23 L24 K25 GND* VCC* L25 L26 M23 M24 M25 M26 N24 N25 GND* VCC* N26 P25 P23 P24 R26 R25 R24 R23 VCC* GND* T26 T25 T24 U25 T23 V26 VCC* U24 V25 V24 U23 GND* Y26 W25 W24 V23 AA26 Y25 Y24 AA25 GND* VCC* AB25 AA24 Y23 AC26 AD26 AC25 AA23 AB24 AD25 AC24 AB23 GND* AD24 VCC*

PG 411 F12 D10 B10 F10 F14 GND* C11 B12 E11 E15 VCC* F16 C13 B14 E17 E13 A15 GND* VCC* B16 D16 D18 A17 E19 B18 C17 C19 GND* VCC* F20 B20 C21 B22 E21 D22 A23 B24 VCC* GND* A25 D24 B26 A27 C27 F24 VCC* E25 E27 B28 C29 GND* F26 D28 B30 E29 F28 F30 C31 E31 GND* VCC* B32 A33 A35 F32 C35 B38 E33 G31 H32 B36 A39 GND* E35 VCC*

BG Bndry 432 Scan H30 257 J28 260 J29 263 H31 266 J30 269 GND* K28 272 K29 275 K30 278 K31 281 VCC* L29 284 L30 287 M29 290 M31 293 N31 296 N28 299 GND* VCC* P30 302 P28 305 P29 308 R31 311 R30 314 R28 317 R29 320 T31 323 GND* VCC* T30 326 T29 329 U31 332 U30 335 U28 338 U29 341 V30 344 V29 347 VCC* GND* W30 350 W29 353 Y30 356 Y29 359 Y28 362 AA30 365 VCC* AA29 368 AB31 371 AB30 374 AB29 377 GND* AB28 380 AC30 383 AC29 386 AC28 389 AD29 392 AD28 395 AE30 398 AE29 401 GND* VCC* AF31 404 AE28 407 AG31 410 AF28 413 AG30 416 AG29 419 AH31 422 AG28 425 AH30 428 AJ30 431 AH29 434 GND* AH28 437 VCC* -

XC4036EX/XL Pad Name I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O

PQ HQ 160 208 P42 P56 P43 P57 P44 P58 P45 P59 P46 P60 P47 P61 P48 P62 P49 P63 P50 P64 P65 P66 P51 P67 P52 P68 P53 P69 P54 P70 P55 P71 P72 P73 P56 P74 P57 P75 P58 P76 P59 P77 P60 P78 P61 P79 P62 P80 P63 P81 P64 P82 P65 P83 P84 P85 P66 P86 P67 P87 P68 P88 P69 P89 P70 P90 P91 P92 P71 P93 P72 P94

HQ 240 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112

HQ 304 P227 P226 P225 P224 P223 P222 P221 P220 P219 P218 P217 P216 P215 P214 P213 P212 P211 P210 P209 P208 P207 P206 P204 P203 P202 P201 P200 P199 P198 P197 P196 P195 P194 P193 P192 P191 P190 P189 P188 P187 P186 P185 P184 P183 P182 P181 P180 P179 P178 P177 P175 P174 P173 P172 P171 P170 P169 P168 P167 P166 P165 P164 P163

BG 352 AC23 AE24 AD23 AC22 AF24 AD22 AE23 AC21 AD21 AE22 AF23 VCC* GND* AD20 AE21 AF21 AC19 AD19 AE20 AF20 AC18 GND* AD18 AE19 AC17 AD17 VCC* AE18 AF18 AC16 AD16 AE17 AE16 GND* VCC* AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 VCC* GND* AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 VCC* GND* AE11 AD11 AE10 AC11 AF9 AD10 VCC* AE9 AD9 AC10 AF7 GND* AE8 AD8 AC9 AF6 AE7 AD7 AE6 AE5

PG 411 G33 D36 C37 F34 J33 D38 G35 E39 K34 F38 G37 VCC* GND* H38 J37 G39 M34 N35 P34 J35 L37 GND* M38 R35 H36 T34 VCC* N37 N39 U35 R39 M36 V34 GND* VCC* R37 T38 T36 V36 U37 U39 V38 W37 VCC* GND* Y34 AC37 AB38 AD36 AA35 AE37 AB36 AD38 VCC* GND* AB34 AE39 AM36 AC35 AG39 AG37 VCC* AD34 AN39 AE35 AH38 GND* AJ37 AG35 AF34 AH36 AK36 AM34 AH34 AJ35

BG Bndry 432 Scan AJ28 438 AK29 439 AH27 442 AK28 445 AJ27 448 AL28 451 AH26 454 AL27 457 AH25 460 AK26 463 AL26 466 VCC* GND* AH24 469 AJ25 472 AK25 475 AJ24 478 AL24 481 AH22 484 AJ23 487 AK23 490 GND* AJ22 493 AK22 496 AL22 499 AJ21 502 VCC* AH20 505 AK21 508 AK20 511 AJ19 514 AL20 517 AH18 520 GND* VCC* AK19 523 AJ18 526 AL19 529 AK18 532 AH17 535 AJ17 538 AJ16 541 AK16 544 VCC* GND* AL16 547 AH15 550 AK15 553 AJ14 556 AH14 559 AK14 562 AL13 565 AK13 568 VCC* GND* AJ13 571 AH13 574 AL12 577 AK12 580 AH12 583 AJ11 586 VCC* AL10 589 AK10 592 AJ10 595 AK9 598 GND* AL8 601 AH10 604 AJ9 607 AK8 610 AK7 613 AL6 616 AJ7 619 AH8 622

March 30, 1998 (Version 1.5)

4-129

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4036EX/XL Pad Name GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O (D2) PQ 160 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 HQ 208 P95 P96 P97 P98 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 HQ 240 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 HQ 304 P162 P161 P160 P159 P158 P157 P156 P155 P154 P153 P152 P151 P150 P149 P148 P147 P146 P145 P144 P143 P142 P141 P140 P139 P138 P137 P136 P135 P134 P133 P132 P131 P130 P129 P127 P126 P125 P124 P123 P122 P121 P120 P119 P118 P117 P116 P115 P114 P113 P112 P111 P110 P109 P108 P107 P106 P105 P104 P103 BG 352 GND* VCC* AD6 AC7 AF4 AF3 AE4 AC6 AD5 AE3 AD4 AC5 GND* AD3 VCC* AC4 AD2 AC3 AB4 AD1 AB3 AC2 AA4 AA3 AB2 AC1 VCC* GND* Y3 AA2 AA1 W4 W3 Y2 Y1 V4 GND* V3 W2 U4 U3 VCC* V2 V1 T4 T3 U2 T2 GND* VCC* T1 R4 R3 R2 R1 P3 P2 P1 VCC* GND* N2 N4 N3 M1 M2 M3 M4 L1 VCC* GND* L2 L3 K2 L4 J1 PG 411 GND* VCC* AL37 AT38 AM38 AN37 AK34 AR39 AN35 AL33 AV38 AT36 GND* AR35 VCC* AN33 AM32 AP34 AW39 AN31 AV36 AR33 AP32 AU35 AW33 AU33 VCC* GND* AV32 AU31 AR31 AP28 AT32 AV30 AR29 AP26 GND* AU29 AV28 AT28 AR25 VCC* AP24 AU27 AR27 AW27 AT24 AR23 GND* VCC* AP22 AV24 AU23 AT22 AR21 AV22 AP20 AU21 VCC* GND* AU19 AV20 AV18 AR19 AT18 AW17 AV16 AP18 VCC* GND* AR17 AT16 AV14 AW13 AR15 BG Bndry 432 Scan GND* VCC* AK6 625 AL5 628 AH7 631 AJ6 634 AK5 637 AL4 640 AK4 643 AH5 646 AK3 649 AJ4 652 GND* AH4 VCC* AH3 AJ2 655 AG4 658 AG3 661 AH2 664 AH1 667 AF4 670 AF3 673 AG2 676 AE3 679 AF2 682 VCC* GND* AF1 685 AD4 688 AD3 691 AE2 694 AC3 697 AD1 700 AC2 703 AB4 706 GND* AB3 709 AB2 712 AB1 715 AA3 718 VCC* AA2 721 Y2 724 Y4 727 Y3 730 W4 733 W3 736 GND* VCC* V4 739 V3 742 U1 745 U2 748 U4 751 U3 754 T1 757 T2 760 VCC* GND* T3 763 R1 766 R2 769 R4 772 R3 775 P2 778 P3 781 P4 784 VCC* GND* N3 787 N4 790 M1 793 M2 796 L2 799 XC4036EX/XL Pad Name I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/ BUSY) I/O I/O I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) PQ 160 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 HQ 208 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 HQ 240 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 HQ 304 P102 P101 P99 P98 P97 P96 P95 P94 P93 P92 P91 P90 P89 P88 P87 P86 P85 P84 P83 P82 P81 P80 P79 P78 P77 P76 P75 P74 P73 P72 P71 P70 P69 P68 P67 P66 P65 P64 P63 P62 P61 P60 P59 P58 P57 P56 P55 P54 P52 P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 BG 352 K3 VCC* J2 J3 K4 G1 GND* H2 H3 J4 F1 G2 G3 F2 E2 GND* VCC* F3 G4 D1 C1 D2 F4 E3 C2 D3 E4 C3 VCC* D4 GND* B3 C4 D5 A3 C5 B4 D6 C6 B5 A4 VCC* GND* C7 B6 A6 D8 B7 A7 D9 C9 GND* B8 D10 C10 B9 VCC* A9 D11 C11 B10 B11 A11 GND* VCC* D12 C12 B12 A12 C13 B13 A13 B14 PG BG Bndry 411 432 Scan AP16 L3 802 VCC* VCC* AV12 K1 805 AR13 K2 808 AU11 K3 811 AT12 K4 814 GND* GND* AP14 J2 817 AR11 J3 820 AV10 J4 823 AT8 H1 826 AT10 H2 829 AP10 H3 832 AP12 H4 835 AR9 G2 838 GND* GND* VCC* VCC* AU7 G4 841 AW7 F2 844 AW5 AV6 AR7 AV4 AN9 AW1 AP6 AU3 AR5 VCC* AN7 GND* AT4 AV2 AM8 AL7 AR3 AR1 AK6 AN3 AM6 AM2 VCC* GND* AL3 AH6 AP2 AK4 AG5 AF6 AL5 AJ3 GND* AH2 AE5 AM4 AD6 VCC* AG3 AG1 AC5 AE1 AH4 AB6 GND* VCC* AD2 AB4 AE3 AC1 AD4 AA5 AA3 Y6 F3 E1 E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7 B7 D9 D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 B16 A16 847 850 853 856 859 862 865 868 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107

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XC4036EX/XL Pad Name GND 6/17/97

PQ HQ 160 208 P141 P182

HQ 240 P211

HQ 304 P39

BG 352 GND*

PG BG Bndry 411 432 Scan GND* GND* -

PG411
A3 F36 AL39 AW29 A9 D20 P4 AF4 AT14 AW21 A13 C25 E7 G5 L35 W35 AF2 AN1 AT2 AU17 AW15 A11 J1 AP4 AW37 A19 D26 P36 AF36 AT20 AW31 B6 C33 E23 H34 N3 Y38 AF38 AN5 AT30 AU25 AW23 VCC Pins A21 A31 L39 W1 AT34 AU1 GND Pins A29 A37 D34 F4 W39 Y4 AJ39 AL1 AT26 AU39 Not Connected Pins B34 C7 D8 D12 E37 F2 J5 K36 P38 R3 AA37 AB2 AJ5 AK2 AP8 AP30 AU5 AU9 AU37 AV8 AW25 AW35 C39 AA39 AW9 C1 J39 Y36 AP36 AW3 C15 D30 F18 K38 V2 AC3 AK38 AP38 AU13 AV26 D6 AJ1 AW19 D14 L1 AA1 AT6 AW11 C23 D32 F22 L5 W5 AC39 AL35 AR37 AU15 AV34 -

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin.

= XL only

Additional XC4036EX/XL Package Pins

HQ208
P1 P54 P155 P207 P3 P102 P156 P208 Not Connected Pins P51 P104 P157 P52 P105 P158 P53 P107 P206 -

5/15/97

HQ240
P204 P219 GND Pins -

6/17/97

6/16/97

The Ground (GND) package pins in the above table should be externally connected to Ground if possible; however, they can be left unconnected if necessary for compatibility with other devices.

BG432
A1 D11 AA1 AJ3 A11 D21 AA4 AJ29 A3 A25 B31 J1 V1 AH16 AK31 AL18 A8 B21 D13 F4 M3 N29 W28 AD30 AH6 AJ12 AK24 VCC Pins A21 A31 L1 L4 AA28 AA31 AL1 AL11 GND Pins A7 A9 A29 A30 C1 C31 J31 P1 V31 AC1 AJ1 AJ31 AL2 AL3 AL23 AL25 Not Connected Pins A15 A28 B25 C8 D20 D23 F28 F29 M4 M28 N30 V2 W31 Y1 AD31 AE4 AH9 AH19 AJ15 AJ20 AK27 AL15 C3 L28 AH11 AL21 A14 B1 D16 P31 AC31 AK1 AL7 AL29 B8 C16 D26 F30 M30 V28 Y31 AF29 AH23 AJ26 AL17 C29 L31 AH21 AL31 A18 B2 G1 T4 AE1 AK2 AL9 AL30 B12 C17 E2 F31 N1 W1 AC4 AF30 AJ5 AK11 -

HQ304
P11 P176 P24 P205 Not Connected Pins P53 P254 P100 P281 P128 -

5/15/97

BG352
A10 D19 P4 AC14 A1 A22 E26 W26 AF2 AF25 C8 A17 G23 U1 AC20 A2 A25 H1 AB1 AF5 AF26 VCC Pins B2 B25 H4 K1 U26 W23 AE2 AE25 GND Pins A5 A8 A26 B1 H26 N1 AB26 AE1 AF8 AF13 Not Connected Pins D7 K26 Y4 AF10 A14 B26 P26 AE26 AF19 D13 N23 AC8 AF17 A19 E1 W1 AF1 AF22 -

A2 A23 B30 G31 T28 AE31 AK30 AL14 A4 B17 D6 F1 G3 N2 W2 AD2 AG1 AJ8 AK17

6/16/97

5/15/97

Pin Locations for XC4044XL Devices

(Note: XC4044XL is also available in the HQ304 package. The pinout is identical to the XC4036XL in the HQ304. )
XC4044XL Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O (A19) HQ 160 P142 P143 P144 P145 HQ 208 P183 P184 P185 P186 HQ 240 P212 P213 P214 P215 BG 352 VCC* D14 C14 A15 PG 411 VCC* W3 Y2 V2 W5 V4 BG 432 VCC* D17 A17 C17 B17 C18 XC4044XL Pad Name I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND I/O I/O HQ 160 P146 P147 P148 HQ 208 P187 P188 P189 P190 P191 HQ 240 P216 P217 P218 P220 P221 BG 352 B15 C15 D15 A16 B16 VCC* GND* C16 B17 PG 411 T2 U1 V6 U3 R1 VCC* GND* U5 T4 BG 432 D18 B18 A19 B19 C19 VCC* GND* D19 A20

March 30, 1998 (Version 1.5)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4044XL Pad Name I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O HQ 160 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 HQ 208 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 HQ 240 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 BG 352 D16 A18 C17 B18 VCC* C18 D17 A20 B19 GND* C19 D18 A21 B20 C20 B21 B22 C21 GND* VCC* D20 A23 A24 B23 D21 C22 B24 C23 D22 C24 VCC* GND* D23 C25 D24 E23 C26 E24 D25 F23 F24 E25 VCC* GND* D26 G24 F25 F26 H23 H24 G25 G26 GND* J23 J24 H25 K23 VCC* K24 J25 J26 L23 L24 K25 GND* VCC* L25 L26 M23 PG 411 P2 N1 R5 M2 VCC* L3 T6 N5 M4 GND* K2 K4 P6 M6 L5 J5 J3 H2 H4 G3 GND* VCC* K6 G1 E1 E3 J7 H6 C3 D2 E5 G7 VCC* GND* H8 F6 B4 D4 B2 G9 F8 C5 A7 A5 VCC* GND* C7 D8 B8 C9 E9 F12 D10 B10 F10 F14 GND* C11 B12 E11 E15 VCC* F16 C13 B14 E17 E13 A15 GND* VCC* F18 C15 B16 D16 D18 BG 432 B20 C20 C21 A22 VCC* B22 C22 B23 A24 GND* D22 C23 B24 C24 D23 B25 A26 C25 D24 B26 GND* VCC* A27 D25 C26 B27 C27 B28 D27 B29 C28 D28 VCC* GND* D29 C30 E28 E29 D30 D31 E30 E31 G28 G29 VCC* GND* F30 F31 H28 H29 G30 H30 J28 J29 H31 J30 GND* K28 K29 K30 K31 VCC* L29 L30 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 XC4044XL Pad Name I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O HQ 160 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 HQ 208 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 HQ 240 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 BG 352 M24 M25 M26 N24 N25 GND* VCC* N26 P25 P23 P24 R26 R25 R24 R23 VCC* GND* T26 T25 T24 U25 T23 V26 VCC* U24 V25 V24 U23 GND* Y26 W25 W24 V23 AA26 Y25 Y24 AA25 GND* VCC* AB25 AA24 Y23 AC26 AD26 AC25 AA23 AB24 AD25 AC24 AB23 GND* AD24 VCC* AC23 AE24 AD23 AC22 AF24 AD22 AE23 AC21 AD21 AE22 AF23 VCC* GND* AD20 AE21 AF21 AC19 PG 411 A17 E19 B18 C17 C19 GND* VCC* F20 B20 C21 B22 E21 D22 A23 B24 C23 F22 VCC* GND* A25 D24 B26 A27 C27 F24 VCC* E25 E27 B28 C29 GND* F26 D28 B30 E29 D30 D32 F28 F30 C31 E31 GND* VCC* B32 A33 A35 F32 C35 B38 E33 G31 H32 B36 A39 GND* E35 VCC* G33 D36 C37 F34 J33 D38 G35 E39 K34 F38 G37 VCC* GND* H38 J37 G39 M34 K36 BG 432 R31 R30 R28 R29 T31 GND* VCC* T30 T29 U31 U30 U28 U29 V30 V29 V28 W31 VCC* GND* W30 W29 Y30 Y29 Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 AE28 AG31 AF28 AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 AL27 AH25 AK26 AL26 VCC* GND* AH24 AJ25 AK25 AJ24 AH23

4-132

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XC4044XL Pad Name I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O

HQ 160 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76

HQ 208 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98

HQ 240 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116

BG 352 AD19 AE20 AF20 AC18 GND* AD18 AE19 AC17 AD17 VCC* AE18 AF18 AC16 AD16 AE17 AE16 GND* VCC* AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 VCC* GND* AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 VCC* GND* AE11 AD11 AE10 AC11 AF9 AD10 VCC* AE9 AD9 AC10 AF7 GND* AE8 AD8 AC9 AF6 AE7 AD7 AE6 AE5 GND* VCC* AD6 AC7 AF4 AF3 AE4 AC6 AD5 AE3

PG 411 K38 N35 P34 J35 L37 GND* M38 R35 H36 T34 VCC* N37 N39 U35 R39 M36 V34 GND* VCC* R37 T38 T36 V36 U37 U39 W35 AC39 V38 W37 VCC* GND* Y34 AC37 Y38 AA37 AB38 AD36 AA35 AE37 AB36 AD38 VCC* GND* AB34 AE39 AM36 AC35 AG39 AG37 VCC* AD34 AN39 AE35 AH38 GND* AJ37 AG35 AF34 AH36 AK38 AP38 AK36 AM34 AH34 AJ35 GND* VCC* AL37 AT38 AM38 AN37 AK34 AR39 AN35 AL33

BG 432 AK24 AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 AK20 AJ19 AL20 AH18 GND* VCC* AK19 AJ18 AL19 AK18 AH17 AJ17 AK17 AL17 AJ16 AK16 VCC* GND* AL16 AH15 AL15 AJ15 AK15 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AH12 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 AJ8 AH9 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 AK4 AH5

XC4044XL Pad Name I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O

HQ 160 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109

HQ 208 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141

HQ 240 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163

BG 352 AD4 AC5 GND* AD3 VCC* AC4 AD2 AC3 AB4 AD1 AB3 AC2 AA4 AA3 AB2 AC1 VCC* GND* Y3 AA2 AA1 W4 W3 Y2 Y1 V4 GND* V3 W2 U4 U3 VCC* V2 V1 T4 T3 U2 T2 GND* VCC* T1 R4 R3 R2 R1 P3 P2 P1 VCC* GND* N2 N4 N3 M1 M2 M3 M4 L1 VCC* GND* L2 L3 K2 L4 J1 K3 VCC* J2 J3

PG 411 AV38 AT36 GND* AR35 VCC* AN33 AM32 AP34 AW39 AN31 AV36 AR33 AP32 AU35 AW33 AU33 VCC* GND* AV32 AU31 AR31 AP28 AP30 AT30 AT32 AV30 AR29 AP26 GND* AU29 AV28 AT28 AR25 VCC* AP24 AU27 AR27 AW27 AT24 AR23 GND* VCC* AW25 AW23 AP22 AV24 AU23 AT22 AR21 AV22 AP20 AU21 VCC* GND* AU19 AV20 AV18 AR19 AT18 AW17 AV16 AP18 AU17 AW15 VCC* GND* AR17 AT16 AV14 AW13 AR15 AP16 VCC* AV12 AR13

BG 432 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 AF3 AG2 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 AC3 AD1 AC2 AB4 GND* AB3 AB2 AB1 AA3 VCC* AA2 Y2 Y4 Y3 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 R3 P2 P3 P4 N1 N2 VCC* GND* N3 N4 M1 M2 L2 L3 VCC* K1 K2

March 30, 1998 (Version 1.5)

4-133

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4044XL Pad Name I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O I/O (CS1,A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O I/O I/O (A6) I/O (A7) HQ 160 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 HQ 208 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 HQ 240 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 BG 352 K4 G1 GND* H2 H3 J4 F1 G2 G3 F2 E2 GND* VCC* F3 G4 D1 C1 D2 F4 E3 C2 D3 E4 C3 VCC* D4 GND* B3 C4 D5 A3 C5 B4 D6 C6 B5 A4 VCC* GND* C7 B6 A6 D8 C8 B7 A7 D9 C9 GND* B8 D10 C10 B9 VCC* A9 D11 C11 B10 B11 A11 GND* VCC* D12 C12 B12 A12 C13 B13 A13 B14 PG 411 AU11 AT12 GND* AP14 AR11 AV10 AT8 AT10 AP10 AP12 AR9 AU9 AV8 GND* VCC* AU7 AW7 AW5 AV6 AR7 AV4 AN9 AW1 AP6 AU3 AR5 VCC* AN7 GND* AT4 AV2 AM8 AL7 AR3 AR1 AK6 AN3 AM6 AM2 VCC* GND* AL3 AH6 AP2 AK4 AN1 AK2 AG5 AF6 AL5 AJ3 GND* AH2 AE5 AM4 AD6 VCC* AG3 AG1 AC5 AE1 AH4 AB6 GND* VCC* AD2 AB4 AE3 AC1 AD4 AA5 AB2 AC3 AA3 Y6 BG 432 K3 K4 GND* J2 J3 J4 H1 H2 H3 H4 G2 G3 F1 GND* VCC* G4 F2 F3 E1 E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7 B7 D9 B8 A8 D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 A15 C16 B16 A16 XC4044XL Pad Name GND 6/18//97 HQ 160 P141 HQ 208 P182 HQ 240 P211 BG 352 GND* PG 411 GND* BG 432 GND*

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin.

Additional XC4044XL Package Pins

HQ208
P1 P104 P206 P3 P105 P207 Not Connected Pins P51 P52 P53 P107 P155 P156 P208 P54 P157 P102 P158 -

5/29/97

HQ240
P204 P219 GND Pins -

5/29/97

Note: These pins may be Not Connected for this device revision, however for compatability with other devices in this package, these pins should be tied to GND.

BG352
A10 G23 U26 AE25 A1 A25 H26 AE1 AF19 A17 H4 W23 AF10 A2 A26 N1 AE26 AF22 B2 K1 Y4 AF17 A5 B1 P26 AF1 AF25 VCC Pins B25 K26 AC8 GND Pins A8 B26 W1 AF2 AF26 D7 N23 AC14 A14 E1 W26 AF5 D13 P4 AC20 A19 E26 AB1 AF8 D19 U1 AE2 A22 H1 AB26 AF13 -

6/13/97

PG411
A3 J1 AT34 A9 D26 W39 AL1 AW3 A13 E23 P38 AP8 AU37 A11 L39 AU1 A19 D34 Y4 AP36 AW11 B6 E37 R3 AR37 AV26 VCC Pins A31 C39 AA39 AJ1 AW19 AW29 GND Pins A29 A37 C1 F4 J39 L1 Y36 AA1 AF4 AT6 AT14 AT20 AW21 AW31 Not Connected Pins B34 C25 C33 F2 G5 H34 AF2 AF38 AJ5 AT2 AU5 AU13 AV34 AW35 A21 W1 AW9 D6 AL39 AW37 D14 P4 AF36 AT26 D12 L35 AL35 AU15 F36 AP4 D20 P36 AJ39 AU39 E7 N3 AN5 AU25 -

6/2/97

4-134

March 30, 1998 (Version 1.5)

BG432
A1 D21 AA28 AL11 A2 A25 C1 P1 AC31 AK2 AL14 A4 D20 M4 AE4 AJ12 A11 L1 AA31 AL21 A3 A29 C31 P31 AE1 AK30 AL18 A28 D26 M28 AF29 AJ20 A21 L4 AH11 AL31 VCC Pins A31 C3 L28 L31 AH21 AJ3 GND Pins A7 A9 A14 A30 B1 B2 D16 G1 G31 T4 T28 V1 AE31 AH16 AJ1 AK31 AL2 AL3 AL23 AL25 AL29 Not Connected Pins B12 B21 C8 E2 F4 F28 M30 W1 W28 AF30 AG1 AH6 AJ26 AK11 AK27 C29 AA1 AJ29 A18 B30 J1 V31 AJ31 AL7 AL30 D6 F29 Y1 AH19 D11 AA4 AL1 A23 B31 J31 AC1 AK1 AL9 D13 M3 Y31 AJ5 -

5/29/97

Pin Locations for XC4052XL Devices

(Note: XC4052XL is also available in the HQ304 package. The pinout is identical to the XC4036XL in HQ304.)
XC4052XL Pad Name GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O HQ 240 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 PG 411 GND* VCC* K6 G1 E1 E3 F2 G5 GND* J7 H6 C3 D2 E5 G7 VCC* GND* H8 F6 B4 D4 B2 G9 GND* E7 B6 F8 C5 A7 A5 VCC* GND* C7 D8 B8 C9 E9 F12 GND* D10 B10 F10 F14 GND* C11 BG 432 GND* VCC* A27 D25 C26 B27 A28 D26 GND* C27 B28 D27 B29 C28 D28 VCC* GND* D29 C30 E28 E29 D30 D31 GND* F28 F29 E30 E31 G28 G29 VCC* GND* F30 F31 H28 H29 G30 H30 GND* J28 J29 H31 J30 GND* K28 BG 560 GND* VCC* C28 D27 B30 C29 E27 A31 GND* D28 C30 D29 E28 D30 E29 VCC* GND* B33 F29 E30 D31 F30 C33 GND* G29 E31 D32 G30 F31 H29 VCC* GND* H30 G31 J29 F33 G32 J30 GND* K30 H33 L29 K31 GND* L30

XC4052XL Pad Name VCC I/O (A8) I/O (A9) I/O I/O GND I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13)

HQ 240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233

PG 411 VCC* W3 Y2 V2 W5 GND* V4 T2 U1 V6 U3 R1 VCC* GND* U5 T4 P2 N1 R3 N3 GND* R5 M2 VCC* L3 T6 N5 M4 GND* K2 K4 P6 M6 GND* L5 J5 J3 H2 H4 G3

BG 432 VCC* D17 A17 C17 B17 GND* C18 D18 B18 A19 B19 C19 VCC* GND* D19 A20 B20 C20 B21 D20 GND* C21 A22 VCC* B22 C22 B23 A24 GND* D22 C23 B24 C24 GND* D23 B25 A26 C25 D24 B26

BG 560 VCC* A17 B18 C18 E18 GND* C19 D19 E19 B20 C20 D20 VCC* GND* A21 E20 B21 C21 D21 B22 GND* C23 E22 VCC* B24 D23 C24 A25 GND* E23 B25 D24 C25 GND* E25 C27 D26 B28 B29 E26

March 30, 1998 (Version 1.5)

4-135

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4052XL Pad Name I/O I/O, TMS I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O HQ 240 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 PG 411 B12 E11 E15 VCC* F16 C13 GND* A13 D12 B14 E17 E13 A15 GND* VCC* F18 C15 B16 D16 D18 A17 GND* E19 B18 C17 C19 GND* VCC* F20 B20 C21 B22 GND* E21 D22 A23 B24 C23 F22 VCC* GND* A25 D24 E23 C25 B26 A27 GND* C27 F24 VCC* E25 E27 B28 C29 GND* F26 D28 B30 E29 GND* D30 D32 F28 F30 C31 E31 GND* VCC* B32 BG 432 K29 K30 K31 VCC* L29 L30 GND* M30 M28 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 R31 GND* R30 R28 R29 T31 GND* VCC* T30 T29 U31 U30 GND* U28 U29 V30 V29 V28 W31 VCC* GND* W30 W29 W28 Y31 Y30 Y29 GND* Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 GND* AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 BG 560 K32 J33 M29 VCC* L32 M31 GND* N29 L33 M32 P29 P30 N33 GND* VCC* P31 P32 R29 R30 R31 R33 GND* T31 T29 U32 U31 GND* VCC* U29 U30 V31 V29 GND* V30 W33 W31 W30 W29 Y32 VCC* GND* Y31 Y30 AA32 AA31 AA30 AB32 GND* AA29 AB31 VCC* AC31 AB29 AD32 AC30 GND* AD31 AE33 AC29 AE32 GND* AG33 AH33 AE29 AG31 AF30 AH32 GND* VCC* AJ32 XC4052XL Pad Name I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O HQ 240 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 PG 411 A33 C33 B34 A35 F32 GND* C35 B38 E33 G31 H32 B36 A39 GND* E35 VCC* G33 D36 C37 F34 J33 D38 G35 GND* E37 H34 E39 K34 F38 G37 VCC* GND* H38 J37 G39 M34 K36 K38 GND* N35 P34 J35 L37 GND* M38 R35 H36 T34 VCC* N37 N39 GND* P38 L35 U35 R39 M36 V34 GND* VCC* R37 T38 T36 V36 U37 U39 GND* W35 AC39 V38 BG 432 AE28 AF30 AF29 AG31 AF28 GND* AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 GND* AK27 AJ26 AL27 AH25 AK26 AL26 VCC* GND* AH24 AJ25 AK25 AJ24 AH23 AK24 GND* AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 GND* AJ20 AH19 AK20 AJ19 AL20 AH18 GND* VCC* AK19 AJ18 AL19 AK18 AH17 AJ17 GND* AK17 AL17 AJ16 BG 560 AF29 AH31 AG30 AK32 AJ31 GND* AG29 AL33 AH30 AK31 AJ30 AH29 AK30 GND* AJ29 VCC* AN32 AJ28 AK29 AL30 AK28 AM31 AJ27 GND* AN31 AL29 AK27 AL28 AJ26 AM30 VCC* GND* AM29 AK26 AL27 AJ25 AN29 AN28 GND* AL25 AJ23 AN26 AL24 GND* AK23 AN25 AJ22 AL23 VCC* AM24 AK22 GND* AK21 AM22 AJ20 AL21 AN21 AK20 GND* VCC* AL20 AJ19 AM20 AK19 AL19 AN19 GND* AL18 AM18 AK17

4-136

March 30, 1998 (Version 1.5)

XC4052XL Pad Name I/O (INIT) VCC GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O GND I/O I/O

HQ 240 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128

PG 411 W37 VCC* GND* Y34 AC37 Y38 AA37 GND* AB38 AD36 AA35 AE37 AB36 AD38 VCC* GND* AB34 AE39 AM36 AC35 AL35 AF38 GND* AG39 AG37 VCC* AD34 AN39 AE35 AH38 GND* AJ37 AG35 AF34 AH36 GND* AK38 AP38 AK36 AM34 AH34 AJ35 GND* VCC* AL37 AT38 AM38 AN37 AK34 AR39 GND* AR37 AU37 AN35 AL33 AV38 AT36 GND* AR35 VCC* AN33 AM32 AP34 AW39 AN31 AV36 AR33 GND* AP32 AU35

BG 432 AK16 VCC* GND* AL16 AH15 AL15 AJ15 GND* AK15 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AJ12 AK11 GND* AH12 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 GND* AJ8 AH9 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 GND* AH6 AJ5 AK4 AH5 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 GND* AF3 AG2

BG 560 AJ17 VCC* GND* AL17 AM17 AN17 AK16 GND* AM16 AL15 AK15 AJ15 AN15 AM14 VCC* GND* AL14 AK14 AJ14 AN13 AM13 AL13 GND* AK12 AN11 VCC* AJ12 AL11 AK11 AM10 GND* AL10 AJ11 AN9 AK10 GND* AN7 AJ9 AL7 AK8 AN6 AM6 GND* VCC* AJ8 AL6 AK7 AM5 AM4 AJ7 GND* AL5 AK6 AN3 AK5 AJ6 AL4 GND* AJ5 VCC* AM1 AH5 AJ4 AK3 AH4 AL1 AG5 GND* AJ3 AK2

XC4052XL Pad Name I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O (D2) I/O VCC

HQ 240 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161

PG 411 AV34 AW35 AW33 AU33 VCC* GND* AV32 AU31 AR31 AP28 AP30 AT30 GND* AT32 AV30 AR29 AP26 GND* AU29 AV28 AT28 AR25 VCC* AP24 AU27 GND* AR27 AW27 AU25 AV26 AT24 AR23 GND* VCC* AW25 AW23 AP22 AV24 AU23 AT22 GND* AR21 AV22 AP20 AU21 VCC* GND* AU19 AV20 AV18 AR19 GND* AT18 AW17 AV16 AP18 AU17 AW15 VCC* GND* AR17 AT16 AV14 AW13 AU15 AU13 GND* AR15 AP16 VCC*

BG 432 AG1 AE4 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 GND* AC3 AD1 AC2 AB4 GND* AB3 AB2 AB1 AA3 VCC* AA2 Y2 GND* Y4 Y3 Y1 W1 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 GND* U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 GND* R3 P2 P3 P4 N1 N2 VCC* GND* N3 N4 M1 M2 M3 M4 GND* L2 L3 VCC*

BG 560 AG4 AH3 AF5 AJ2 VCC* GND* AJ1 AF4 AG3 AE5 AH1 AF3 GND* AE3 AC5 AE1 AD3 GND* AC4 AD2 AB5 AC3 VCC* AA5 AB3 GND* AB2 AA4 AA3 Y5 Y3 Y2 GND* VCC* W5 W4 W3 W1 V3 V5 GND* V4 V2 U5 U4 VCC* GND* U3 T2 T4 R1 GND* R3 R4 R5 P2 P3 P4 VCC* GND* N1 P5 N2 N3 N5 M3 GND* M4 L1 VCC*

March 30, 1998 (Version 1.5)

4-137

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4052XL Pad Name I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O GND I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O GND HQ 240 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 PG 411 AV12 AR13 AU11 AT12 GND* AP14 AR11 AV10 AT8 GND* AT10 AP10 AP12 AR9 AU9 AV8 GND* VCC* AU7 AW7 AW5 AV6 AU5 AP8 GND* AR7 AV4 AN9 AW1 AP6 AU3 AR5 VCC* AN7 GND* AT4 AV2 AM8 AL7 AT2 AN5 GND* AR3 AR1 AK6 AN3 AM6 AM2 VCC* GND* AL3 AH6 AP2 AK4 AN1 AK2 GND* AG5 AF6 AL5 AJ3 GND* AH2 AE5 AM4 AD6 VCC* AG3 AG1 GND* BG 432 K1 K2 K3 K4 GND* J2 J3 J4 H1 GND* H2 H3 H4 G2 G3 F1 GND* VCC* G4 F2 F3 E1 F4 E2 GND* E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 A4 D6 GND* B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7 B7 D9 B8 A8 GND* D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 GND* BG 560 K2 L4 J1 K3 GND* L5 J2 K4 J3 GND* G1 F1 J5 G3 H4 F2 GND* VCC* F3 G4 D2 E3 G5 C1 GND* F4 D3 B3 F5 E4 D4 C4 VCC* E6 GND* D5 A2 D6 A3 E7 C5 GND* B4 D7 C6 E8 B5 A5 VCC* GND* D8 C7 E9 A6 B7 D9 GND* E11 A9 C10 D11 GND* B10 E12 C11 B11 VCC* D12 A11 GND* XC4052XL Pad Name I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) GND I/O I/O I/O (A6) I/O (A7) GND 6/20/97 HQ 240 P202 P203 P205 P206 P207 P208 P209 P210 P211 PG 411 AF2 AJ5 AC5 AE1 AH4 AB6 GND* VCC* AD2 AB4 AE3 AC1 AD4 AA5 GND* AB2 AC3 AA3 Y6 GND* BG 432 D13 B12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 GND* A15 C16 B16 A16 GND* BG 560 C13 E14 A13 D14 C14 B14 GND* VCC* E15 D15 C15 A15 C16 E16 GND* B17 C17 E17 D17 GND*

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin.

Additional XC4052XL Package Pins

HQ240 GND Pins

P204 6/3/97

P219

Note: These pins may be Not Connected for this device revision, however for compatability with other devices in this package, these pins should be tied to GND.
PG411 VCC Pins

A3 J1 AT34 A9 D26 W39 AL1 AW3 6/3/97

BG432

A11 L39 AU1 A19 D34 Y4 AP36 AW11

A21 W1 AW9 A29 F4 Y36 AT6 AW21

A31 AA39 AW19

GND Pins

C39 AJ1 AW29 C1 LI AF4 AT20 -

D6 AL39 AW37 D14 P4 AF36 AT26 -

F36 AP4 D20 P36 AJ39 AU39 -

A37 J39 AA1 AT14 AW31

VCC Pins

A1 D21 AA28 AL11 A2 A25 C1 P1 AC31 AK2 AL14 C8 6/3/97

A11 L1 AA31 AL21 A3 A29 C31 P31 AE1 AK30 AL18 -

A21 L4 AH11 AL31 A7 A30 D16 T4 AE31 AK31 AL23 -

A31 L28 AH21 GND Pins

C3 L31 AJ3 A14 B2 G31 V1 AJ1 AL3 AL29 -

C29 AA1 AJ29 A18 B30 J1 V31 AJ31 AL7 AL30 -

D11 AA4 AL1 A23 B31 J31 AC1 AK1 AL9 -

A9 B1 G1 T28 AH16 AL2 AL25 -

Not Connected Pins

4-138

March 30, 1998 (Version 1.5)

PG560 VCC Pins

A4 B13 D33 T33 AK1 AM15 AN24 A7 A32 B31 K1 V33 AE2 AM7 AN5 A1 B8 C22 D25 E33 J31 M30 T32 AA1 AD4 AF1 AJ16 AK24 AL26 AN1 6/20/97

A10 B19 E5 V1 AK4 AM21 AN30 A12 B1 C2 L2 W2 AG1 AM11 AN10 A8 B12 C26 E2 H2 K5 N4 U1 AA33 AD5 AF2 AJ18 AK25 AM8 AN23

A16 B32 H1 W32 AK33 AM32 A14 B6 E1 M33 Y1 AG32 AM19 AN14 A19 B16 D10 E10 H3 K29 N30 U2 AB4 AD29 AF31 AJ21 AL8 AM9 AN33

A22 C3 K33 AA2 AL2 AN4 GND Pins

A26 C31 M1 AB33 AL3 AN8 A20 B15 G2 P33 AB1 AJ33 AM28 AN20 A27 C8 D16 E21 H31 L31 T3 V32 AC1 AE4 AG2 AK9 AL12 AM23 -

A30 C32 N32 AD1 AL31 AN12 A24 B23 G33 R32 AC32 AL32 AM33 AN22 A28 C9 D18 E24 H32 M2 T5 Y4 AC2 AE30 AJ10 AK13 AL16 AM26 -

B2 D1 R2 AF33 AM2 AN18 A29 B27 J32 T1 AD33 AM3 AN2 AN27 A33 C12 D22 E32 J4 M5 T30 Y29 AC33 AE31 AJ13 AK18 AL22 AM27 -

A18 B9 F32 P1 Y33 AH2 AM25 AN16 A23 B26 D13 E13 H5 L3 N31 U33 AB30 AD30 AF32 AJ24 AL9 AM12 -

Not Connected Pins

Pin Locations for XC4062XL Devices

(Note: XC4062XL is also available in the HQ304 package. The pinout is identical to the XC4036XL in HQ304.)
XC4062XL Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O GND I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O HQ240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 BG432 VCC* D17 A17 C17 B17 GND* C18 D18 B18 A19 B19 C19 VCC* GND* D19 A20 B20 C20 B21 D20 GND* C21 A22 VCC* B22 PG475 VCC* Y2 Y4 W5 Y6 U3 W3 GND* W1 U5 W7 U7 V2 V4 VCC* GND* V6 R1 T6 R3 R5 T4 GND* P2 N1 VCC* N3 BG560 VCC* A17 B18 C18 E18 D18 A19 GND* C19 D19 E19 B20 C20 D20 VCC* GND* A21 E20 B21 C21 D21 B22 GND* C23 E22 VCC* B24 XC4062XL Pad Name I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O HQ240 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 BG432 C22 B23 A24 GND* D22 C23 B24 C24 GND* D23 B25 A26 C25 D24 B26 GND* VCC* A27 D25 C26 B27 A28 D26 GND* C27 B28 D27 B29 PG475 P4 R7 M2 GND* M4 L3 N5 K2 L5 J1 GND* M6 K4 J3 J5 H2 G1 GND* VCC* L7 K6 E1 H4 G5 F2 GND* H6 C3 F4 C5 BG560 D23 C24 A25 GND* E23 B25 D24 C25 B26 E24 GND* E25 C27 D26 B28 B29 E26 GND* VCC* C28 D27 B30 C29 E27 A31 GND* D28 C30 D29 E28

March 30, 1998 (Version 1.5)

4-139

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4062XL Pad Name I/O (A14) I/O GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O XC4062XL Pad Name GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O

HQ240 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34

BG432 C28 D28 VCC* GND* D29 C30 E28 E29 D30 D31 GND* F28 F29 E30 E31 G28 G29 VCC* GND* F30 F31 H28 H29 G30 H30 GND* J28 J29 H31 J30 GND* K28 K29 K30 K31 VCC* L29 L30 GND* M30 M28 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 R31 GND* R30 R28 R29 T31 GND* VCC* T30 T29 U31 U30

PG475 E3 E5 VCC* GND* G7 D4 A5 B4 D6 F8 GND* B6 E7 D8 G9 E9 A7 VCC* GND* B8 C9 G11 D10 E11 A9 GND* B10 C11 F12 D12 A11 G15 GND* B12 E13 C13 A13 VCC* B14 C15 GND* G17 F14 D16 D14 A15 C17 GND* VCC* D18 B18 F16 G19 E17 E19 GND* A19 F18 C19 D20 F20 B20 GND* VCC* C21 A21 D22 B22 E23 F22

BG560 D30 E29 VCC* GND* B33 F29 E30 D31 F30 C33 GND* G29 E31 D32 G30 F31 H29 VCC* GND* H30 G31 J29 F33 G32 J30 GND* H32 J31 K30 H33 L29 K31 GND* L30 K32 J33 M29 VCC* L32 M31 GND* N29 L33 M32 P29 P30 N33 GND* VCC* P31 P32 R29 R30 R31 R33 GND* T31 T29 T30 T32 U32 U31 GND* VCC* U29 U30 U33 V32 V31 V29

HQ240 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 -

BG432 GND* U28 U29 V30 V29 V28 W31 VCC* GND* W30 W29 W28 Y31 Y30 Y29 GND* Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 GND* AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 AE28 AF30 AF29 AG31 AF28 GND* AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 GND* AK27 AJ26 AL27 AH25 AK26 AL26

PG475 GND* C23 F24 A23 E25 G23 B24 VCC* GND* D24 C25 D28 A27 E29 C27 GND* G25 D26 VCC* F26 B28 D30 A29 GND* C29 G27 F30 B30 E31 C31 GND* F28 D32 B32 G31 A33 C33 GND* VCC* B34 A35 E33 D34 D36 B36 GND* F34 D38 C37 G37 B38 F38 A39 GND* E35 VCC* G33 J37 G35 K36 C39 K38 C41 GND* D40 L37 H36 M36 J35 E41

BG560 GND* V30 W33 W31 W30 W29 Y32 VCC* GND* Y31 Y30 AA32 AA31 AA30 AB32 GND* AA29 AB31 VCC* AC31 AB29 AD32 AC30 GND* AD31 AE33 AC29 AE32 AD30 AE31 GND* AG33 AH33 AE29 AG31 AF30 AH32 GND* VCC* AJ32 AF29 AH31 AG30 AK32 AJ31 GND* AG29 AL33 AH30 AK31 AJ30 AH29 AK30 GND* AJ29 VCC* AN32 AJ28 AK29 AL30 AK28 AM31 AJ27 GND* AN31 AL29 AK27 AL28 AJ26 AM30

4-140

March 30, 1998 (Version 1.5)

XC4062XL Pad Name VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I//O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O

HQ240 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99

BG432 VCC* GND* AH24 AJ25 AK25 AJ24 AH23 AK24 GND* AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 GND* AJ20 AH19 AK20 AJ19 AL20 AH18 GND* VCC* AK19 AJ18 AL19 AK18 AH17 AJ17 GND* AK17 AL17 AJ16 AK16 VCC* GND* AL16 AH15 AL15 AJ15 GND* AK15 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AJ12 AK11 GND* AH12

PG475 VCC* GND* F40 H38 N37 L35 R35 G41 GND* H40 P38 J39 R37 J41 K40 GND* L39 M38 T36 M40 VCC* N39 N41 GND* P40 T38 U35 U37 R39 R41 GND* VCC* V36 U39 V38 V40 W37 W35 GND* W41 Y36 W39 AB36 Y40 Y38 VCC* GND* AA39 AB38 AB40 AC37 AC39 AC41 GND* AD36 AC35 AE37 AD40 AD38 AE39 VCC* GND* AG41 AG39 AG37 AE35 AH38 AF38 GND* AF36

BG560 VCC* GND* AM29 AK26 AL27 AJ25 AN29 AN28 GND* AM26 AK24 AL25 AJ23 AN26 AL24 GND* AK23 AN25 AJ22 AL23 VCC* AM24 AK22 GND* AK21 AM22 AJ20 AL21 AN21 AK20 GND* VCC* AL20 AJ19 AM20 AK19 AL19 AN19 GND* AJ18 AK18 AL18 AM18 AK17 AJ17 VCC* GND* AL17 AM17 AN17 AK16 AJ16 AL16 GND* AM16 AL15 AK15 AJ15 AN15 AM14 VCC* GND* AL14 AK14 AJ14 AN13 AM13 AL13 GND* AK12

XC4062XL Pad Name I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O

HQ240 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137

BG432 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 GND* AJ8 AH9 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 GND* AH6 AJ5 AK4 AH5 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 GND* AF3 AG2 AG1 AE4 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 GND* AC3 AD1 AC2 AB4 GND* AB3 AB2

PG475 AH40 VCC* AJ41 AJ39 AJ37 AG35 GND* AK40 AK38 AL37 AL39 AM38 AM40 GND* AN41 AM36 AK36 AU41 AN39 AP40 GND* VCC* AR41 AL35 AV40 AN37 AT38 AP38 GND* AT40 AW39 AP36 AU37 AR37 AU39 GND* AR35 VCC* AN35 AU35 AV38 AT34 BA39 AU33 AY38 GND* AV36 AR31 AR33 AV32 BA37 AY36 VCC* GND* AV34 BA35 AU31 AY34 AT30 AW33 GND* BA33 AV30 AY32 AU29 AW31 BA31 GND* AR27 AT28

BG560 AN11 VCC* AJ12 AL11 AK11 AM10 GND* AL10 AJ11 AN9 AK10 AM9 AL9 GND* AN7 AJ9 AL7 AK8 AN6 AM6 GND* VCC* AJ8 AL6 AK7 AM5 AM4 AJ7 GND* AL5 AK6 AN3 AK5 AJ6 AL4 GND* AJ5 VCC* AM1 AH5 AJ4 AK3 AH4 AL1 AG5 GND* AJ3 AK2 AG4 AH3 AF5 AJ2 VCC* GND* AJ1 AF4 AG3 AE5 AH1 AF3 GND* AF1 AD4 AE3 AC5 AE1 AD3 GND* AC4 AD2

March 30, 1998 (Version 1.5)

4-141

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4062XL Pad Name I/O I/O VCC I/O (D5) I/O (CS0) GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O XC4062XL Pad Name I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O GND I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O

HQ240 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172

BG432 AB1 AA3 VCC* AA2 Y2 GND* Y4 Y3 Y1 W1 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 GND* U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 GND* R3 P2 P3 P4 N1 N2 VCC* GND* N3 N4 M1 M2 M3 M4 GND* L2 L3 VCC* K1 K2 K3 K4 GND* J2 J3 J4 H1 GND* H2 H3 H4 G2

PG475 AY30 AW29 VCC* BA29 AY28 GND* AR25 AV28 AW27 AT26 AV26 BA27 GND* VCC* AW25 AV24 AU25 AR23 AT24 AY24 GND* BA23 AU23 AW23 AV20 AY22 AV22 VCC* GND* AW21 BA21 AU19 AY20 AU17 AW19 GND* BA19 AT16 AR19 AV14 AY18 AV18 VCC* GND* AT18 AW17 AR15 BA15 AT14 AR17 GND* AW15 AV16 VCC* AY14 BA13 AU13 AW13 GND* AY12 BA11 AV12 AT12 AW11 AY10 GND* BA9 AU11 AW9 AV10

BG560 AB5 AC3 VCC* AA5 AB3 GND* AB2 AA4 AA3 Y5 Y3 Y2 GND* VCC* W5 W4 W3 W1 V3 V5 GND* V4 V2 U2 U1 U5 U4 VCC* GND* U3 T2 T3 T5 T4 R1 GND* R3 R4 R5 P2 P3 P4 VCC* GND* N1 P5 N2 N3 N5 M3 GND* M4 L1 VCC* K2 L4 J1 K3 GND* L5 J2 K4 J3 H2 K5 GND* G1 F1 J5 G3

HQ240 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206

BG432 G3 F1 GND* VCC* G4 F2 F3 E1 F4 E2 GND* E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 A4 D6 GND* B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7 B7 D9 B8 A8 GND* D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 GND* D13 B12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15

PG475 AY8 BA7 GND* VCC* AV8 AY6 AR11 AT8 AU9 AW5 GND* AY4 BA5 AV4 AR9 AU5 AV6 AR5 VCC* AN7 GND* AR7 AW3 AU3 AW1 AP6 AV2 GND* AT4 AN5 AU1 AM6 AT2 AL7 VCC* GND* AR1 AP2 AM4 AN3 AL5 AK6 GND* AN1 AJ5 AM2 AH4 AL3 AK4 GND* AG7 AG5 AK2 AJ3 VCC* AJ1 AF6 GND* AH2 AF4 AE7 AE5 AG3 AG1 GND* VCC* AD6 AD4 AE3 AC5

BG560 H4 F2 GND* VCC* F3 G4 D2 E3 G5 C1 GND* F4 D3 B3 F5 E4 D4 C4 VCC* E6 GND* D5 A2 D6 A3 E7 C5 GND* B4 D7 C6 E8 B5 A5 VCC* GND* D8 C7 E9 A6 B7 D9 GND* D10 C9 E11 A9 C10 D11 GND* B10 E12 C11 B11 VCC* D12 A11 GND* C13 E14 A13 D14 C14 B14 GND* VCC* E15 D15 C15 A15

4-142

March 30, 1998 (Version 1.5)

XC4062XL Pad Name I/O (A21) I/O (A20) GND I/O I/O I/O I/O I/O (A6) I/O (A7) GND 6/16/97

HQ240 P207 P208 P209 P210 P211

BG432 C15 B15 GND* A15 C16 B16 A16 GND*

PG475 AD2 AC7 GND* AC1 AC3 AB6 AB2 AB4 AA3 GND*

BG560 C16 E16 GND* D16 B16 B17 C17 E17 D17 GND*

PG475
VCC Pins

A37 E21 N35 AA41 AR29 AW41 A3 U1 AH6 E15 L41 AL41 AU15 E37 5/5/97

B2 F6 T2 AF2 AT6 AY2 C1 A17 AL1 E27 P36 AR21 AU27 E39

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin.

B16 B26 F36 G13 T40 AA1 AF40 AJ7 AT22 AT36 AY16 AY26 GND Pins C7 G3 A25 A41 AR3 AW7 F10 F32 U41 AA35 AR39 AT10 AW35 BA17 A31 J7

B40 G29 AA5 AJ35 AU21 AY40 L1 AA7 BA1 G21 AE41 AT20 BA25 AP4

D2 N7 AA37 AR13 AW37 BA3 P6 AE1 C35 G39 AH36 AT32 BA41 AU7

Additional XC4062XL Package Pins

HQ240 GND Pins P204 5/5/97 P219 -

BG560
VCC Pins

Note: These pins may be Not Connected for this device revision, however for compatability with other devices in this package, these pins should be tied to GND.

BG432
VCC Pins

A4 B13 D33 T33 AK1 AM15 AN24 A7 A32 B31 K1 V33 AE2 AM11 AN5 A1 B12 D25 H3 M2 Y29 AC33 AF32 AK13 AM12 5/5/97

A10 B19 E5 V1 AK4 AM21 AN30 A12 B1 C2 L2 W2 AG1 AM19 AN10 A8 C8 E2 H5 M5 AA1 AD5 AG2 AK25 AM23

A16 B32 H1 W32 AK33 AM32 -

A1 D21 AA28 AL11 A2 A25 C1 P1 AC31 AK2 AL14 C8 5/5/97

A11 L1 AA31 AL21 A3 A29 C31 P31 AE1 AK30 AL18 -

A21 L4 AH11 AL31

A31 C3 L28 L31 AH21 AJ3 GND Pins A7 A9 A14 A30 B1 B2 D16 G1 G31 T4 T28 V1 AE31 AH16 AJ1 AK31 AL2 AL3 AL23 AL25 AL29 Not Connected Pins -

C29 AA1 AJ29 A18 B30 J1 V31 AJ31 AL7 AL30 -

D11 AA4 AL1 A23 B31 J31 AC1 AK1 AL9 -

A22 A26 C3 C31 K33 M1 AA2 AB33 AL2 AL3 AN4 AN8 GND Pins A14 A18 A20 B6 B9 B15 E1 F32 G2 M33 P1 P33 Y1 Y33 AB1 AG32 AH2 AJ33 AM25 AM28 AM33 AN14 AN16 AN20 Not Connected Pins A23 A27 A28 C12 C22 C26 E10 E13 E21 H31 J4 K29 M30 N4 N30 AA33 AB4 AB30 AD29 AE4 AE30 AJ10 AJ13 AJ21 AL8 AL12 AL22 AM27 AN1 AN23

A30 C32 N32 AD1 AL31 AN12 A24 B23 G33 R32 AC32 AL32 AM7 AN22 A33 D13 E32 L3 N31 AC1 AF2 AJ24 AL26 AN33

B2 D1 R2 AF33 AM2 AN18 A29 B27 J32 T1 AD33 AM3 AN2 AN27 B8 D22 E33 L31 Y4 AC2 AF31 AK9 AM8 -

Pin Locations for XC4085XL Devices

XC4085XL Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O GND I/O (A19) I/O (A18) I/O BG432 VCC D17 A17 C17 B17 GND* C18 D18 B18 BG560 VCC* A17 B18 C18 E18 D18 A19 GND* C19 D19 E19 PG559 VCC* AB6 AB4 AA7 AC1 AA5 AA3 GND* Y8 AB2 Y6 XC4085XL Pad Name I/O I/O (A10) I/O (A11) VCC GND I/O I/O I/O I/O I/O I/O I/O BG432 A19 B19 C19 VCC* GND* D19 A20 B20 C20 B21 D20 BG560 B20 C20 D20 VCC* GND* A21 E20 B21 C21 D21 B22 E21 PG559 AA1 Y4 W7 VCC* GND* W5 V6 V4 Y2 U3 U7 V2

March 30, 1998 (Version 1.5)

4-143

XC4000E and XC4000X Series Field Programmable Gate Arrays XC4085XL Pad Name I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) GND I/O I/O I/O I/O I/O I/O XC4085XL Pad Name VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (TMS) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O

BG432 GND* C21 A22 VCC B22 C22 B23 A24 GND* D22 C23 B24 C24 GND* VCC* D23 B25 A26 C25 D24 B26 GND* VCC* A27 D25 C26 B27 A28 D26 GND* C27 B28 D27 B29 C28 D28 VCC* GND* D29 C30 E28 E29 D30 D31 GND* F28 F29 E30 E31 G28 G29

BG560 C22 GND* D22 A23 C23 E22 VCC* B24 D23 C24 A25 GND* E23 B25 D24 C25 B26 E24 C26 D25 GND* VCC* A27 A28 E25 C27 D26 B28 B29 E26 GND* VCC* C28 D27 B30 C29 E27 A31 GND* D28 C30 D29 E28 D30 E29 VCC* GND* B33 F29 E30 D31 F30 C33 GND* G29 E31 D32 G30 F31 H29

PG559 U5 GND* T4 U1 R3 R5 VCC* T8 T2 P4 R7 GND* N3 R1 N5 P2 M4 L1 L3 P8 GND* VCC* N7 K2 M6 J1 L5 H2 K4 J3 GND* VCC* L7 J5 G1 H4 F2 G5 GND* H6 K8 D2 J7 F4 E3 VCC* GND* C1 C3 F6 A3 H8 D4 GND* D6 C5 E7 B4 H10 G9

BG432 VCC* GND* F30 F31 H28 H29 G30 H30 VCC* GND* J28 J29 H31 J30 GND* K28 K29 K30 K31 VCC* L29 L30 GND* M30 M28 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 R31 GND* R30 R28 R29 T31 GND* VCC* T30 T29 U31

BG560 VCC* GND* E32 E33 H30 G31 J29 F33 G32 J30 VCC* GND* H31 K29 H32 J31 K30 H33 L29 K31 GND* L30 K32 J33 M29 VCC* L31 M30 L32 M31 GND* N29 L33 N30 N31 M32 P29 P30 N33 GND* VCC* P31 P32 R29 R30 R31 R33 GND* T31 T29 T30 T32 U32 U31 GND* VCC* U29 U30 U33 V32 V31

PG559 VCC* GND* F8 D8 B6 E9 A7 G11 H14 F12 VCC* GND* G13 E11 B8 D10 A9 G15 B10 H16 GND* C9 E13 A11 D12 VCC* C11 B14 G17 E15 GND* D14 A15 C13 B16 E17 F18 A17 G19 GND* VCC* D16 C15 B18 H20 B20 E19 GND* D18 F20 G21 C17 D20 E21 GND* VCC* C21 F22 A21 D22 B22

4-144

March 30, 1998 (Version 1.5)

XC4085XL Pad Name I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O

BG432 U30 GND* U28 U29 V30 V29 V28 W31 VCC* GND* W30 W29 W28 Y31 Y30 Y29 GND* Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 GND* VCC* AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 AE28 AF30 AF29 AG31 AF28 GND* AG30 AG29 AH31 AG28 AH30

BG560 V29 GND* V30 W33 W31 W30 W29 Y32 VCC* GND* Y31 Y30 AA33 Y29 AA32 AA31 AA30 AB32 GND* AA29 AB31 AB30 AC33 VCC* AC31 AB29 AD32 AC30 GND* AD31 AE33 AC29 AE32 AD30 AE31 AF32 AD29 GND* VCC* AF31 AE30 AG33 AH33 AE29 AG31 AF30 AH32 GND* VCC* AJ32 AF29 AH31 AG30 AK32 AJ31 GND* AG29 AL33 AH30 AK31 AJ30

PG559 G23 GND* E23 C23 A23 D24 B24 H24 VCC* GND* F24 E25 B26 D26 A27 G25 B28 C27 GND* F26 E27 A29 D28 VCC* G27 B30 C29 E29 GND* D30 A33 C31 B34 H28 A35 G29 E31 GND* VCC* D32 C35 C33 B36 H30 A37 G31 F32 GND* VCC* E33 D34 B38 G33 A41 E35 GND* D36 F36 G35 H34 B40

XC4085XL Pad Name I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O

BG432 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 GND* AK27 AJ26 AL27 AH25 AK26 AL26 VCC* GND* AH24 AJ25 AK25 AJ24 AH23 AK24 VCC* GND* AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 GND* AJ20 AH19 AK20 AJ19 AL20 AH18 GND* VCC* AK19

BG560 AH29 AK30 GND* AJ29 VCC* AN32 AJ28 AK29 AL30 AK28 AM31 AJ27 GND* AN31 AL29 AK27 AL28 AJ26 AM30 VCC* GND* AM29 AK26 AL27 AJ25 AN29 AN28 AK25 AL26 VCC* GND* AJ24 AM27 AM26 AK24 AL25 AJ23 AN26 AL24 GND* AK23 AN25 AJ22 AL23 VCC* AM24 AK22 AM23 AJ21 GND* AL22 AN23 AK21 AM22 AJ20 AL21 AN21 AK20 GND* VCC* AL20

PG559 E37 D38 GND* C39 VCC* H36 F38 C41 D40 B42 J37 K36 GND* H38 D42 G39 C43 F40 E41 VCC* GND* L37 J39 F42 H40 G43 J41 H42 N37 VCC* GND* P36 M38 J43 L39 K42 K40 L43 L41 GND* R37 P42 T36 N39 VCC* M40 R43 N41 R39 GND* U37 T42 P40 U43 R41 V42 U39 V38 GND* VCC* W37

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XC4000E and XC4000X Series Field Programmable Gate Arrays XC4085XL Pad Name I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O XC4085XL Pad Name I/O I/O I/O I/O I/O GND VCC I/O I.O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O

BG432 AJ18 AL19 AK18 AH17 AJ17 GND* AK17 AL17 AJ16 AK16 VCC* GND* AL16 AH15 AL15 AJ15 GND* AK15 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AJ12 AK11 GND* AH12 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 GND* VCC* AJ8

BG560 AJ19 AM20 AK19 AL19 AN19 GND* AJ18 AK18 AL18 AM18 AK17 AJ17 VCC* GND* AL17 AM17 AN17 AK16 AJ16 AL16 GND* AM16 AL15 AK15 AJ15 AN15 AM14 VCC* GND* AL14 AK14 AJ14 AN13 AM13 AL13 AK13 AJ13 GND* AM12 AL12 AK12 AN11 VCC* AJ12 AL11 AK11 AM10 GND* AL10 AJ11 AN9 AK10 AM9 AL9 AJ10 AM8 GND* VCC* AK9 AL8 AN7

PG559 T40 Y42 U41 Y36 V40 GND* W39 AA43 Y38 Y40 AA37 AA39 VCC* GND* AA41 AB38 AB42 AB40 AC37 AC39 GND* AD36 AC41 AD38 AC43 AD40 AE39 VCC* GND* AE37 AF40 AD42 AF42 AF38 AG39 AG43 AG37 GND* AH40 AJ41 AG41 AK40 VCC* AJ39 AH42 AH36 AL39 GND* AJ37 AJ43 AM40 AK42 AN41 AL41 AR41 AK36 GND* VCC* AL37 AN43 AM38

BG432 AH9 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 GND* AH6 AJ5 AK4 AH5 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 GND* AF3 AG2 AG1 AE4 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 VCC* GND* AC3 AD1 AC2 AB4 GND* AB3 AB2 AB1

BG560 AJ9 AL7 AK8 AN6 AM6 GND* VCC* AJ8 AL6 AK7 AM5 AM4 AJ7 GND* AL5 AK6 AN3 AK5 AJ6 AL4 GND* AJ5 VCC* AM1 AH5 AJ4 AK3 AH4 AL1 AG5 GND* AJ3 AK2 AG4 AH3 AF5 AJ2 VCC* GND* AJ1 AF4 AG3 AE5 AH1 AF3 AE4 AG2 VCC* GND* AD5 AF2 AF1 AD4 AE3 AC5 AE1 AD3 GND* AC4 AD2 AB5

PG559 AP42 AN39 AR43 AP40 AT40 GND* VCC* AN37 AR39 AT42 BA43 AU43 AU39 GND* AT38 AP36 AR37 AV42 AV40 AW41 GND* AY42 VCC* BB42 BC41 AV38 BA39 AT36 BB40 AY40 GND* BA41 BB38 AY38 BC37 AW37 AT34 VCC* GND* AU35 AV36 BB36 AY36 BC35 AW35 AU33 AT30 VCC* GND* AV32 AU31 AW33 BB34 AY34 BC33 AU29 AT28 GND* BA35 BB30 AW31

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XC4085XL Pad Name I/O VCC I/O I/O I/O (D5) I/O (CS0) GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O (D2) I/O I/O I/O VCC

BG432 AA3 VCC* AA2 Y2 GND* Y4 Y3 Y1 W1 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 GND* U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 GND* R3 P2 P3 P4 N1 N2 VCC* GND* N3 N4 M1 M2 M3 M4 GND* L2 L3 VCC*

BG560 AC3 VCC* AB4 AC1 AA5 AB3 GND* AB2 AA4 AA3 Y5 AA1 Y4 Y3 Y2 GND* VCC* W5 W4 W3 W1 V3 V5 GND* V4 V2 U2 U1 U5 U4 VCC* GND* U3 T2 T3 T5 T4 R1 GND* R3 R4 R5 P2 P3 P4 VCC* GND* N1 P5 N2 N3 N4 M2 N5 M3 GND* M4 L1 L3 M5 VCC*

PG559 AY32 VCC* BA33 AU27 BC29 AW29 GND* AY30 BA31 BB28 AW27 BC27 AV26 AU25 AY28 GND* VCC* BA29 AT24 BB26 AW25 BB24 AY26 GND* AV24 AU23 BA27 BC23 AY24 AW23 VCC* GND* BA23 AV22 AY22 BB22 AU21 AW21 GND* BA21 BC21 AY20 BB20 AT20 AV20 VCC* GND* AW19 AY18 BB18 AU19 BC17 BA17 AV18 AW17 GND* AY16 BB16 AU17 BA15 VCC*

XC4085XL Pad Name I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK RDY/BUSY) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O GND I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O

BG432 K1 K2 K3 K4 GND* J2 J3 J4 H1 GND* VCC* H2 H3 H4 G2 G3 F1 GND* VCC* G4 F2 F3 E1 F4 E2 GND* E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 A4 D6 GND* B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7

BG560 K2 L4 J1 K3 GND* L5 J2 K4 J3 H2 K5 H3 J4 GND* VCC* G1 F1 J5 G3 H4 F2 E2 H5 GND* VCC* F3 G4 D2 E3 G5 C1 GND* F4 D3 B3 F5 E4 D4 C4 VCC* E6 GND* D5 A2 D6 A3 E7 C5 GND* B4 D7 C6 E8 B5 A5 VCC* GND* D8 C7

PG559 AW15 BC15 AY14 BA13 GND* AT16 BB14 AU15 BC11 AW13 BB10 AY12 BA11 GND* VCC* AT14 AU13 AV12 BC9 AW11 BB8 AY10 AU11 GND* VCC* BA9 AW9 BC7 AY8 AV8 AT10 GND* AU9 BB6 AW7 BC3 AY6 BB4 BA5 VCC* BA3 GND* AT8 AV6 BB2 AY4 AR7 AP8 GND* AT6 AY2 AU5 BA1 AV4 AW3 VCC* GND* AN7 AR5

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XC4000E and XC4000X Series Field Programmable Gate Arrays XC4085XL Pad Name I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) GND I/O I/O I/O I/O I/O (A6) I/O (A7) GND 6/13/97

BG432 B7 D9 B8 A8 VCC* GND* D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 GND* D13 B12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 GND* A15 C16 B16 A16 GND*

BG560 E9 A6 B7 D9 C8 E10 VCC* GND* B8 A8 D10 C9 E11 A9 C10 D11 GND* B10 E12 C11 B11 VCC* D12 A11 E13 C12 GND* B12 D13 C13 E14 A13 D14 C14 B14 GND* VCC* E15 D15 C15 A15 C16 E16 GND* D16 B16 B17 C17 E17 D17 GND*

PG559 AV2 AT4 AU1 AR3 AT2 AL7 VCC* GND* AK8 AM6 AN5 AR1 AP4 AN3 AP2 AJ7 GND* AH8 AL5 AN1 AM4 VCC* AL3 AJ5 AK2 AG7 GND* AK4 AJ3 AG5 AJ1 AF6 AH2 AE7 AH4 GND* VCC* AG3 AD8 AG1 AF4 AE5 AD6 GND* AD4 AF2 AC7 AD2 AC5 AC3 GND*

Additional XC4085XL Package Pins

BG560 A4 B13 D33 T33 AK1 AM15 AN24 A7 A32 B31 K1 V33 AE2 AM11 AN5 A1 6/4/97 A10 B19 E5 V1 AK4 AM21 AN30 A12 B1 C2 L2 W2 AG1 AM19 AN10 A33 VCC Pins A22 A26 C3 C31 K33 M1 AA2 AB33 AL2 AL3 AN4 AN8 GND Pins A14 A18 A20 B6 B9 B15 E1 F32 G2 M33 P1 P33 Y1 Y33 AB1 AG32 AH2 AJ33 AM25 AM28 AM33 AN14 AN16 AN20 Not Connected Pins AC2 AN1 AN33 A16 B32 H1 W32 AK33 AM32 A30 C32 N32 AD1 AL31 AN12 A24 B23 G33 R32 AC32 AL32 AM7 AN22 B2 D1 R2 AF33 AM2 AN18 A29 B27 J32 T1 AD33 AM3 AN2 AN27 -

*Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin.

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PG559 A13 C37 H12 N43 AE3 AL43 AU3 BA19 A5 E5 H22 W1 AH38 AV16 BB12 5/8/97 A31 F14 H18 P6 AE41 AM8 AU7 BA25 A19 E39 K6 W43 AM2 AV28 BB32 A43 F30 H26 P38 AF8 AM36 AU37 BA37 A25 E43 K38 AB8 AM42 AV34 BC5 VCC Pins B2 G3 H32 V8 AF36 AT12 AU41 BC1 GND Pins A39 F10 M2 AB36 AP6 AW1 BC19 C7 G7 M8 V36 AK6 AT18 AV14 BC13 B12 F16 M42 AE1 AP38 AW5 BC25 C19 G37 M36 W3 AK38 AT26 AV30 BC31 B32 F28 T6 AE43 AT22 AW39 BC39 C25 G41 N1 W41 AL1 AT32 BA7 BC43 E1 F34 T38 AH6 AV10 AW43 -

BG432 A1 L4 AH11 C29 A11 L28 AH21 AJ3 A21 L31 AL1 AJ29 VCC Pins A31 D11 AA1 AA4 AL11 AL21 D21 AA28 AL31 L1 AA31 C3

A2 A25 C1 P1 AC31 AK2 AL14 C8 3/3/98

A3 A29 C31 P31 AE1 AK30 AL18

GND Pins A7 A9 A14 A30 B1 B2 D16 G1 G31 T4 T28 V1 AE31 AH16 AJ1 AK31 AL2 AL3 AL23 AL25 AL29 Not Connected Pins

A18 B30 J1 V31 AJ31 AL7 AL30

A23 B31 J31 AC1 AK1 AL9

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XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays

March 30, 1998 (Version 1.5)

Product Availability
Table 25 - Table 27 show the planned packages and speed grades for XC4000-Series devices. Call your local sales ofce for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of the specications. Table 25: Component Availability Chart for XC4000XL FPGAs
PINS 84 Plast. PLCC 100 Plast. PQFP 100 Plast. VQFP 144 Plast. TQFP 144 High-Perf. TQFP 160 High-Perf. QFP 160 Plast. PQFP 176 Plast. TQFP 176 High-Perf. TQFP 208 High-Perf. QFP 208 Plast. PQFP 240 High-Perf. QFP 240 Plast. PQFP 256 Plast. BGA 299 Ceram. PGA 304 High-Perf. QFP 352 Plast. BGA 411 Ceram. PGA 432 Plast. BGA 475 Ceram. PGA 559 Ceram. PGA 560 Plast. BGA

TYPE

HQ160

HQ208

HQ240

HQ304

PQ100

VQ100

PQ160

PQ208

PQ240

BG256

PG299

BG352

PG411

BG432

PG475

PG559
CI C C

CODE

-3

CI C C CI C C

CI C C CI C C

CI C C

CI C C CI C C CI C C CI C C CI C C C CI C CI C C

CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C

CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C

XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL
3/27/98

-2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1

C = Commercial TJ = 0 to +85C I= Industrial TJ = -40C to +100C

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BG560

TQ144

TQ176

HT144

HT176

PC84

XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 26: Component Availability Chart for XC4000E FPGAs

PINS 84 Plast. PLCC 100 Plast. PQFP 100 Plast. VQFP 120 Ceram. PGA 144 Plast. TQFP 156 Ceram. PGA 160 Plast. PQFP 191 Ceram. PGA 208 High-Perf. QFP 208 Plast. PQFP 223 Ceram. PGA 225 Plast. BGA 240 High-Perf. QFP 240 Plast. PQFP 299 Ceram. PGA 304 High-Perf. QF C C

TYPE

HQ208

HQ240

CODE

-4

CI C C C CI C C C CI C C C CI C C C CI C C C

CI C C C CI C C C

CI C C C

CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C CI C C C CI C C C CI C C C CI C C C CI C C CI C C CI C C CI C C C

XC4003E

-3 -2 -1 -4 -3 -2 -1 -4 -3 -2 -1 -4 -3 -2 -1 -4 -3 -2 -1 -4 -3 -2 -1 -4 -3 -2 -1 -4

XC4005E

XC4006E

XC4008E

XC4010E

XC4013E

XC4020E

XC4025E
8/4/97

-3 -2

C = Commercial TJ = 0 to +85C I= Industrial TJ = -40C to +100C

Table 27: Component Availability Chart for XC4000EX FPGAs

PINS TYPE CODE -3 208 High-Perf. QFP 240 High-Perf. QFP 299 Ceram. PGA 304 High-Perf. QFP 352 Plast. BGA 411 Ceram. PGA 432 Plast. BGA

HQ208
CI C C

HQ240
CI C C

PG299
CI C C

HQ304
CI C C CI C C

BG352
CI C C

PG411

BG432

XC4028EX XC4036EX
8/4/97

-2 -1 -3 -2 -1

CI C C

CI

C = Commercial TJ = 0 to +85C I= Industrial TJ = -40C to +100C

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HQ304

PQ100

VQ100

PG120

PG156

PQ160

PG191

PQ208

PG223

BG225

PQ240

PG299

TQ144

PC84

User I/O Per Package

Table 28 - Table 30 show the number of user I/Os available in each package for XC4000-Series devices. Call your local sales ofce for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of the specications. Table 28: User I/O Chart for XC4000XL FPGAs Package Type HQ160 HQ208 HQ240 HQ304 PQ100 VQ100 PQ160 PQ208 PQ240 BG256 PG299 BG352 PG411 BG432 PG475 PG559
448 448 288

Max Device I/O XC4005XL 112 XC4010XL 160 XC4013XL 192 XC4020XL 224 XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL
XC40125XV
3/27/98 256 288 320 352 384 448 448

61 61

77 77

77

112 113 113 113 129 129 129

112 129 129 129 145 145 145 160 160 160

112 160 160 160 193 193 193 193 193 192 193 160 192 205 205 256 256 256 256 256 256 256 288 289 288 320 352 288 320 352 352 384 352 384 448 432

Table 29: User I/O Chart for XC4000E FPGAs Package Type HQ208 HQ240 Max I/O
80 112 128 144 160 192 224 256

Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E

8/5/97

61 61 61 61 61

77 77

77

80 112 113 112 125 112 128 129 129 129 144 160 160 160 160 112 128 144 160 160 192 192 192 160 192 192 193 193 256 256 192

Table 30: User I/O Chart for XC4000EX FPGAs Max Device I/O XC4028EX 256 XC4036EX 288
8/5/97

HQ208
160

HQ240
193 193

PG299
256

Package Type HQ304

256 256

BG352
256 288

PG411
288

BG432

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HQ304

PQ100

VQ100

PG120

PG156

PQ160

PG191

PQ208

PG223

BG225

PQ240

PG299

TQ144

PC84

BG560

TQ144

TQ176

HT144

HT176

PC84

XC4000E and XC4000X Series Field Programmable Gate Arrays

Ordering Information Example:

Device Type Speed Grade -6 -5 -4 -3 -2 -1 Temperature Range C = Commercial (TJ = 0 to +85C) I = Industrial (TJ = -40 to +100C) M = Military (TC = -55 to+125C) Number of Pins Package Type BG = Ball Grid Array PG = Ceramic Pin Grid Array HQ = High Heat Dissipation Quad Flat Pack MQ = Metal Quad Flat Pack CB = Top Brazed Ceramic Quad Flat Pack
X9020

XC4013E-3HQ240C

PC = Plastic Lead Chip Carrier PQ = Plastic Quad Flat Pack VQ = Very Thin Quad Flat Pack TQ = Thin Quad Flat Pack

Table 31: Revisions Version Description March 30, 1998 (1.5) Updated XC4000XL timing and added XC4002XL

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XC4000XV Family Field Programmable Gate Arrays

0 4*

April 2, 1998 (Version 1.0)

Advance Product Specification Backward Compatible with XC4000 Devices Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization

XC4000XV FPGAs
Note: This data sheet describes the XC4000XV devices. This information does not necessarily apply to the other Xilinx families: XC4000, XC4000A, XC4000D, XC4000H, or XC4000L, XC4000E, XC4000EX, XC4000XL. For information on these devices, see the Xilinx WEBLINX at http:// www.xilinx.com. System featured Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Abundant ip-ops - Flexible function generators - Dedicated high-speed carry logic - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks Flexible Array Architecture Low Power Segmented Routing Architecture Systems-Oriented Features - IEEE 1149.1-compatible boundary scan - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors Congured by Loading Binary File - Unlimited reprogrammability Readback Capability - Program verication - Internal node observability

XC4000XV Electrical Features

Low-Voltage Device Functions at 2.3 - 2.7 Volts 5.0 V TTL compatible I/O 3.3 V LVTTL, LVCMOS compatible I/O 12-mA, 24-mA current sink capability 40% lower power than XC4000XL Devices

Additional XC4000XV Features

. Advanced Technology 0.25 m SRAM CMOS process Proven Architecture Industry standard XC4000X architecture Highest Performance Internal performance beyond 100MHz Lowest Power 2.5 V technology plus segmented routing architecture Easy to Use Interfaces to any combination of 3.0 V and 5.0 V TTL-compatible devices Software Compatibility Supported by Alliance/ Foundation Series Software M1.4 Package Compatibility Footprint compatible with XC4000XL devices (except for 2.5 V power pins)

Table 1: The XC4000XV Field Programmable Gate Array Logic Cells 10,982 12,312 16,758 20,102 Max. Logic Max.RAM Typical Gates Bits Gate Range (No RAM) (No Logic) (Logic and RAM)* 125,000 147,968 80,000 - 250,000 150,000 165,888 100,000 - 300,000 200,000 225,792 130,000 - 400,000 250,000 270,848 180,000 - 500,000 CLB Matrix 68 x 68 72 x 72 84 x 84 92 x 92 Number Total of Max. CLBs Flip-Flops User I/O 4,624 10,336 448 5,184 11,520 448 7,056 15,456 448 8,464 18,400 448 PROM Size 2,797,040 3,373,448 4,551,056 5,433,888

Device XC40125XV XC40150XV XC40200XV XC40250XV

* Max values of Typical Gate Range include 20-30% of CLBs used as RAM*

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Introduction
XC4000 Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benets of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs.

Differences between the XC4000XV and XC4000XL FPGAs

VCCINT (2.5 Volt) Power Supply Pins XC4000XV FPGAs are logically identical to XC4000EX and XC4000XL FPGAs. The I/O functionality is identical to XC4000XL FPGAs. The only difference between XV and XL is a separate lower core voltage of 2.5V for XV, which is named VCCINT. The pins assigned to the VCCINT supply are named in the pinout guide for the XC40125XV FPGA Lower Power XC4000XV devices require 40% less power than equivalent XL devices Increased Drive XC4000XV outputs can optionally sink 24-mA each. Increased Routing The XC40150XV, XC40200XV, and XC40250XV have enhanced routing. Eight routing channels of octal length have been added to each row of CLBs.

5.0 V Power 3.3 V Power 2.5 V Power

VCC (5 V) 5 Volt Device TTL LVTTL

VCCIO VCCINT XC4000XV LVTTL

VCC (3.3 V) 3.3 Volt Device

Ground
X7147

VOUT_max TTL LVTTL LVCMOS 5.5 3.6 3.6

VIH 2.0 2.0 50% of VCCIO

VIL 0.8 0.8 30% of VCCIO

VOH 2.4 2.4 90% of VCCIO

VOL 0.4 0.4 10% of VCCIO

Figure 1: XV Power supply and signaling environment

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XC4000XV Switching Characteristics

Denition of Terms
In the following tables, some specications may be designated as Advance or Preliminary. These terms are dened as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production.

Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specications not identied as either Advance or Preliminary are to be considered Final.

All specications subject to change without notice.

Additional Specications
Except for pin-to-pin input and output parameters, the a.c. parameter delay specications included in this document are derived from measuring internal test patterns.All specications are representative of worst- case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. For design considerations requiring more detailed timing information, see the appropriate family a.c. supplements available on the Xilinx WEBLINX at http://www.xilinx.com.

Absolute Maximum Ratings

Symbol VCCINT VCCIO VIN VTS VCC TSTG TSOL TJ Supply voltage relative to GND Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Longest Supply Voltage Rise Time from 1 V to 3V Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic packages Plastic packages Description -0.5 to 3.0 -0.5 to 4.0 -0.5 to 5.5 -0.5 to 5.5 50 -65 to +150 +260 +150 +125 Units V V V V ms C C C C

Notes: 1. Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

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Recommended Operating Conditions

Symbol VCCINT Description Supply voltage relative to GND, TJ = 0 C to +85C Commercial Supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TJ = -40C to +100C High-level input voltage Low-level input voltage Input signal transition time Industrial Min 2.3 2.3 3.0 3.0 50% of VCC 0 Max 2.7 2.7 3.6 3.6 5.5 30% of VCC 250 Units V V V V V V ns

Supply voltage relative to GND, TJ = 0 C to +85C Commercial VCCIO VIH VIL TIN Industrial

Notes: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Input and output measurement threshold is ~50% of VCC.

DC Characteristics Over Recommended Operating Conditions

Symbol VOH VOL VDRINT VDRIO ICCO IL CIN IRPU IRPD IRLL
Note 1: Note 2:

Description High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL) High-level output voltage @ IOH = -500 A, (LVCMOS) Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1) Low-level output voltage @ IOL = 1500 A, (LVCMOS) Data Retention Supply Voltage (below which conguration data may be lost) Data Retention Supply Voltage (below which conguration data may be lost) Quiescent FPGA supply current (Note 2) Input or output leakage current Input capacitance (sample tested) BGA, SBGA, PQ, HQ, MQ packages PGA packages Pad pull-up (when selected) @ Vin = 0 V (sample tested) Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low

Min 2.4 90% VCC

Max

Units V V

0.4 10% VCC 2.1 2.5 5 -10 +10 10 16 0.02 0.02 0.3 0.25 0.15 2.0

V V V V mA A pF pF mA mA mA

With up to 64 pins simultaneously sinking 12 mA. With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and oating.

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XC4000XV Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade Description From pad through Global Low Skew buffer, to any clock K From pad through Global Early buffer, to any IOB clock for BUFGEs # 1, 2, 5, & 6 From pad through Global Early buffer, to any IOB clock for BUFGEs # 3, 4, 7, & 8 Symbol TGLS TGE_1256 TGE_3478 Device XC40125XV XC40125XV XC40125XV -2 Max 6.3 5.4 6.6 -1 Max 5.4 4.7 5.7 Units ns ns

Advance

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XC4000XV CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values are expressed in nanoseconds unless otherwise noted.
Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via SR/H0 via H to X/Y outputs C inputs via H1 via H to X/Y outputs C inputs via DIN/H2 via H to X/Y outputs C inputs via EC, DIN/H2 to YQ, XQ output (bypass) CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Carry Net Delay, COUT to CIN Sequential Delays Clock K to Flip-Flop outputs Q Clock K to Latch outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H Hold Time after Clock K F/G inputs F/G inputs via H C inputs via SR/H0 through H C inputs via H1 through H C inputs via DIN/H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Clocks Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Global Set/Reset Speed Grade Symbol TILO TIHO TITO THH0O THH1O THH2O TCBYP TOPCY TASCY TINCY TSUM TBYP TNET TCKO TCKLO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR TCH TCL TRPW TRIO TMRW TMRQ FTOG 1.1 2.1 1.8 1.6 1.8 0.8 0.9 0.5 2.2 3.2 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 3.0 3.0 2.8 2.8 17.3 32.9 166 Advance -2 Min Max 1.4 2.4 2.1 2.1 1.9 2.1 0.8 1.6 2.9 1.1 2.5 0.3 0.4 1.3 1.3 0.9 1.8 1.5 1.4 1.5 0.7 0.8 0.4 1.9 2.7 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 2.5 2.5 2.5 2.4 15.0 28.6 200 Min -1 Max 1.2 2.1 1.8 1.8 1.7 1.8 0.7 1.4 2.5 0.9 2.2 0.2 0.25 1.2 1.2 Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz

Minimum GSR Pulse Width Delay from GSR input to any Q

Toggle Frequency (MHz) (for export control purposes)

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XC4000XV RAM Synchronous (Edge-Triggered) Write Operation Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan devices and are expressed in nanoseconds unless otherwise noted.

Single Port RAM

Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K Read Operation Address read cycle time Data Valid after address change (no Write Enable) Address setup time before clock K

Speed Grade Size Symbol Min

-2 Max Min

-1 Units Max

16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1

TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS

9 9 4.5 4.5 2.0 2.0 0.0 0.0 2.0 2.5 0.0 0.0 1.9 1.8 0.0 0.0 6.5 7.7

7.7 7.7 3.9 3.9 1.8 1.7 0.0 0.0 1.7 2.1 0.0 0.0 1.6 1.5 0.0 0.0 5.6 6.7

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

16x2 32x1 16x2 32x1 16x2 32x1

TRC TRCT TILO TIHO TICK TIHCK

4.5 6.5 1.4 2.4 1.1 2.1

2.6 3.8 1.3 2.2 0.9 1.8 Advance

ns ns ns ns ns ns

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XC4000XV CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan devices and are expressed in nanoseconds unless otherwise noted.

Dual Port RAM

Speed Grade Size Symbol Min

-2* Max Min

-1 Units Max

Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K
Note: Timing for 16 x1 RAM option is identical to16 x 2 RAM.

16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1

TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS

9 4.5 2.1 0.0 2.3 0.0 1.9 0.0 7.5

7.7 3.9 1.8 0.0 2.0 0.0 1.6 0.0 6.5 Advance

ns ns ns ns ns ns ns ns ns

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TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

TILO

TWOS OLD

DATA OUT

NEW
X6461

XC4000XV CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing

TWPDS WCLK (K) TWSDS WE TDSDS DATA IN TASDS ADDRESS TILO TWODS DATA OUT OLD NEW
X6474

TWHDS

TDHDS

TAHDS

TILO

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Pin-to-Pin Output Parameter Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report.

XC4000XV Output Flip-Flop, Clock to Out

Speed Grade Description Global Low Skew Clock to Output using OFF Symbol TICKOF Device XC40125XV -2 Max 9.0 8.1 9.3 2.3 -1 Max 7.8 7.1 7.1 2.0 Units ns ns ns ns

Global Early Clock to Output using OFF for BUFGEs # 1, 2, 5, & 6 TICKEOF_1256 XC40125XV Global Early Clock to Output using OFF for BUFGEs # 3, 4, 7, & 8 TICKEOF_3478 XC40125XV For output SLOW option add TSLOW All Devices OFF = Output Flip Flop

Advance

Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load.

Capacitive Load Factor

Delta Delay (ns)
Figure 1 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specied output delay if the load capacitance is different than 50 pF. For example, if the actual load capacitance is 120 pF, add 2.5 ns to the specied delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specied output delay. Figure 1 is usable over the specied operating conditions of voltage and temperature and is independent of the output slew rate control.

3 2 1 0 -1 -2 0 20 40 60 80 100 120 140 Capacitance (pF)

X8257

Figure 2: Delay Factor at Various Capacitive Loads

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Pin-to-Pin Input Parameter Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report.

XC4000XV Global Low Skew Clock, Set-Up and Hold

Speed Grade -2 -1 Units Description Symbol Device Min Min Input Setup and Hold Times Using Global Low Skew Clock & IFF No Delay TPSN/TPHN XC40125XV 1.1 / 6.6 0.9 / 5.7 ns Partial Delay TPSP/TPHP XC40125XV 11.3 / 0.0 9.8 / 0.0 ns Full Delay TPSD/TPHD XC40125XV 9.7 / 0.0 8.4 / 0.0 ns IFF = Input Flip-Flop or Latch Advance
Notes: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions.

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XC4000XV BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-Up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Description Input Setup and Hold Times No Delay, Global Early Clock and IFF, Global Early Clock and FCL Partial Delay, Global Early Clock and IFF, Global Early Clock and FCL Full Delay, Global Early Clock and IFF
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch

Symbol

Speed Grade Device

-2 Min 1.1 / 6.6 12.7 / 0.0

-1 Min 0.9 / 5.7 11.0 / 0.0

Units

TPSEN/TPHEN XC40125XV TPFSEN/TPFHEN TPSEP/TPHEP XC40125XV TPFSEP/TPFHEP TPSED/TPHED XC40125XV

ns ns ns

11.1 / 0.0 9.6 / 0.0 Advance

Notes: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions.

XC4000XV BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-Up and Hold for IFF and FCL
Description Input Setup and Hold Times No Delay,Global Early Clock and IFF, Global Early Clock and FCL Partial Delay, Global Early Clock and IFF, Global Early Clock and FCL Full Delay, Global Early Clock and IFF
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch

Symbol

Speed Grade Device

-2 Min

-1 Min

Units

TPSEN/TPHEN XC40125XV 1.4 / 5.5 1.2 / 4.7 TPFSEN/TPFHEN TPSEP/TPHEP XC40125XV 14.5 / 0.0 12.6 / 0.0 TPFSEP/TPFHEP TPSED/TPHED XC40125XV 12.9 / 0.0 11.2 / 0.0 Advance

ns ns ns

Notes: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions.

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XC4000XV IOB Input Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Description Speed Grade Symbol TECIK TOKIK -2 Min 0.0 1.1 Max Min 0.0 0.9 -1 Max Units

Clocks Clock Enable (EC) to Clock (IK) Delay from Fast Capture Latch enable (OK) active edge to IFF clock (IK) active edge Setup Times Pad to Clock (IK), no delay Pad to Clock (IK), via transparent Fast Capture Latch, no delay Pad to Fast Capture Latch Enable (OK), no delay Hold Times All Hold Times Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q - XC40125XV Propagation Delays Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent FCL and input latch, no delay Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) FCL Enable (OK) active edge to I1, I2 (via transparent standard input latch)
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch .

ns ns

TPICK TPICKF TPOCK

1.1 1.3 0.7 0.0

0.9 1.1 0.6 0.0 15.0 28.6 0.6 0.8 1.0 1.3 1.4 2.4 Advance 0.4 0.7 0.8 1.0 1.1 2.0

ns ns ns ns ns ns ns ns ns ns ns ns

TMRW TRRI TPID TPLI TPFLI TIKRI TIKLI TOKLI

17.3 32.9

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XC4000XV IOB Output Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values are expressed in nanoseconds unless otherwise noted. -2 Description Clocks Clock High Clock Low Propagation Delays (See Note 1) Clock (OK) to Pad Output (O) to Pad 3-state to Pad hi-Z (slew-rate independent) 3-state to Pad active and valid Output (O) to Pad via Fast Output MUX Select (OK) to Pad via Fast MUX Setup and Hold Times Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup time Clock Enable (EC) to clock (OK) hold time Global Set/Reset Minimum GSR pulse width Delay from GSR input to any Pad - XC40125XV Slew Rate Adjustment For output SLOW option add TSLOW 2.3 Advance 2.0 ns TMRW TRPO 17.3 35.5 15.0 30.9 ns ns TOOK TOKO TECOK TOKEC 0.2 0.0 0.0 0.3 0.2 0.0 0.0 0.2 ns ns ns ns TOKPOF TOPF TTSHZ TTSONF TOFPF TOKFPF 2.7 2.1 3.8 3.8 2.6 2.4 2.4 1.9 3.3 3.3 2.2 2.1 ns ns ns ns ns ns TCH TCL 3.0 3.0 2.5 2.5 ns ns Symbol Min Max Min -1 Max Units

Note: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads.

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Pin Locations for XC40125XV Devices

XC40125XV Pad Name
VCCIO I/O (A8) I/O (A9) I/O I/O I/O I/O GND I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCCIO GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O I/O VCCINT I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCCIO I/O I/O I/O

BG432
VCCIO D17 A17 C17 B17 GND* C18 D18 B18 A19 B19 C19 VCCIO* GND* D19 A20 B20 C20 B21 D20 GND* C21 A22 VCCIO* B22 C22 B23 A24 GND* D22 C23 B24 C24 GND* VCCIO* D23 B25 A26 C25 D24 B26 GND* VCCIO* A27 D25 C26

BG560
VCCIO* A17 B18 C18 E18 D18 A19 GND* C19 D19 E19 B20 C20 D20 VCCIO* GND* A21 E20 B21 C21 D21 B22 E21 C22 GND* D22 A23 C23 E22 VCCIO* B24 D23 C24 A25 GND* E23 B25 D24 C25 B26 E24 C26 D25 GND* VCCIO* A27 A28 E25 C27 D26 B28 B29 E26 GND* VCCIO* C28 D27 B30

PG559
VCCIO* AB6 AB4 AA7 AC1 AA5 AA3 GND* Y8 AB2 Y6 AA1 Y4 W7 VCCIO* GND* W5 V6 V4 Y2 U3 U7 V2 U5 GND* T4 U1 R3 R5 VCCIO* T8 T2 VCCINT* P4 R7 GND* N3 R1 N5 P2 M4 L1 L3 P8 GND* VCCIO* N7 K2 M6 J1 L5 H2 K4 J3 GND* VCCIO* L7 J5 G1

XC40125XV Pad Name

I/O I/O I/O GND I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCCIO GND I/O, GCK1 (A16) I/O (A17) VCCINT I/O I/O I/O (TDI) I/O (TCK) GND I/O I/O I/O I/O I/O I/O VCCIO GND I/O I/O I/O I/O I/O I/O I/O I/O VCCIO GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O VCCINT I/O (TMS) I/O VCCIO I/O I/O I/O I/O GND I/O

BG432
B27 A28 D26 GND* C27 B28 D27 B29 C28 D28 VCCIO* GND* D29 C30 E28 E29 D30 D31 GND* F28 F29 E30 E31 G28 G29 VCCIO* GND* F30 F31 H28 H29 G30 H30 VCCIO* GND* J28 J29 H31 J30 GND* K28 K29 K30 K31 VCCIO* L29 L30 GND* M30

BG560
C29 E27 A31 GND* D28 C30 D29 E28 D30 E29 VCCIO* GND* B33 F29 E30 D31 F30 C33 GND* G29 E31 D32 G30 F31 H29 VCCIO* GND* E32 E33 H30 G31 J29 F33 G32 J30 VCCIO* GND* H31 K29 H32 J31 K30 H33 L29 K31 GND* L30 K32 J33 M29 VCCIO* L31 M30 L32 M31 GND* N29

PG559
H4 F2 G5 GND* H6 K8 D2 J7 F4 E3 VCCIO* GND* C1 C3 VCCINT* F6 A3 H8 D4 GND* D6 C5 E7 B4 H10 G9 VCCIO* GND* F8 D8 B6 E9 A7 G11 H14 F12 VCCIO* GND* G13 E11 B8 D10 A9 G15 B10 H16 GND* C9 E13 VCCINT* A11 D12 VCCIO* C11 B14 G17 E15 GND* D14

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XC40125XV Pad Name

I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCINT I/O I/O GND VCCIO I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCIO GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O I/O VCCINT I/O I/O GND I/O

BG432
M28 M29 M31 N31 N28 GND* VCCIO* N29 N30 P30 P28 P29 R31 GND* R30 R28 R29 T31 GND* VCCIO* T30 T29 U31 U30 GND* U28 U29 V30 V29 V28 W31 VCCIO* GND* W30 W29 W28 Y31 Y30 Y29 GND* Y28 AA30 VCCIO* AA29 AB31 AB30 AB29 GND* AB28

BG560
L33 N30 N31 M32 P29 P30 N33 GND* VCCIO* P31 P32 R29 R30 R31 R33 GND* T31 T29 T30 T32 U32 U31 GND* VCCIO* U29 U30 U33 V32 V31 V29 GND* V30 W33 W31 W30 W29 Y32 VCCIO* GND* Y31 Y30 AA33 Y29 AA32 AA31 AA30 AB32 GND* AA29 AB31 AB30 AC33 VCCIO* AC31 AB29 AD32 AC30 GND* AD31

PG559
A15 C13 B16 E17 F18 A17 G19 GND* VCCIO* D16 C15 B18 H20 B20 E19 GND* D18 F20 G21 C17 VCCINT* D20 E21 GND* VCCIO* C21 F22 A21 D22 B22 G23 GND* E23 C23 A23 D24 B24 H24 VCCIO* GND* F24 E25 B26 D26 A27 G25 B28 C27 GND* F26 E27 A29 D28 VCCIO* G27 B30 VCCINT* C29 E29 GND* D30

XC40125XV Pad Name

I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCINT I/O I/O, GCK2 O (M1) GND I (M0) VCCIO I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O VCCIO GND I/O I/O I/O I/O I/O I/O I/O I/O

BG432
AC30 AC29 AC28 GND* VCCIO* AD31 AD30 AD29 AD28 AE30 AE29 GND* VCCIO* AF31 AE28 AF30 AF29 AG31 AF28 GND* AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCCIO* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 GND* AK27 AJ26 AL27 AH25 AK26 AL26 VCCIO* GND* AH24 AJ25 AK25 AJ24 AH23 AK24 -

BG560
AE33 AC29 AE32 AD30 AE31 AF32 AD29 GND* VCCIO* AF31 AE30 AG33 AH33 AE29 AG31 AF30 AH32 GND* VCCIO* AJ32 AF29 AH31 AG30 AK32 AJ31 GND* AG29 AL33 AH30 AK31 AJ30 AH29 AK30 GND* AJ29 VCCIO* AN32 AJ28 AK29 AL30 AK28 AM31 AJ27 GND* AN31 AL29 AK27 AL28 AJ26 AM30 VCCIO* GND* AM29 AK26 AL27 AJ25 AN29 AN28 AK25 AL26

PG559
A33 C31 B34 H28 A35 G29 E31 GND* VCCIO* D32 C35 C33 B36 H30 A37 G31 F32 GND* VCCIO* E33 D34 B38 G33 A41 E35 GND* D36 F36 G35 H34 VCCINT* B40 E37 D38 GND* C39 VCCIO* H36 F38 C41 D40 B42 J37 K36 GND* H38 D42 G39 C43 F40 E41 VCCIO* GND* L37 J39 F42 H40 G43 J41 H42 N37

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XC40125XV Pad Name

VCCIO GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O VCCINT I/O I/O VCCIO I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O (INIT) VCCIO GND I/O I/O VCCINT I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O

BG432
VCCIO* GND* AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCCIO* AH20 AK21 GND* AJ20 AH19 AK20 AJ19 AL20 AH18 GND* VCCIO* AK19 AJ18 AL19 AK18 AH17 AJ17 GND* AK17 AL17 AJ16 AK16 VCCIO* GND* AL16 AH15 AL15 AJ15 GND* AK15 AJ14 AH14 AK14 AL13 AK13

BG560
VCCIO* GND* AJ24 AM27 AM26 AK24 AL25 AJ23 AN26 AL24 GND* AK23 AN25 AJ22 AL23 VCCIO* AM24 AK22 AM23 AJ21 GND* AL22 AN23 AK21 AM22 AJ20 AL21 AN21 AK20 GND* VCCIO* AL20 AJ19 AM20 AK19 AL19 AN19 GND* AJ18 AK18 AL18 AM18 AK17 AJ17 VCCIO* GND* AL17 AM17 AN17 AK16 AJ16 AL16 GND* AM16 AL15 AK15 AJ15 AN15 AM14

PG559
VCCIO* GND* P36 M38 J43 L39 K42 K40 L43 L41 GND* R37 P42 VCCINT* T36 N39 VCCIO* M40 R43 N41 R39 GND* U37 T42 P40 U43 R41 V42 U39 V38 GND* VCCIO* W37 T40 Y42 U41 Y36 V40 GND* W39 AA43 Y38 Y40 AA37 AA39 VCCIO* GND* AA41 AB38 VCCINT* AB42 AB40 AC37 AC39 GND* AD36 AC41 AD38 AC43 AD40 AE39

XC40125XV Pad Name

VCCIO GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O I/O VCCINT I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCINT I/O I/O, GCK4 GND DONE VCCIO PROGRAM I/O (D7)

BG432
VCCIO* GND* AJ13 AH13 AL12 AK12 AJ12 AK11 GND* AH12 AJ11 VCCIO* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 GND VCCIO* AJ8 AH9 AK7 AL6 AJ7 AH8 GND* VCCIO* AK6 AL5 AH7 AJ6 AK5 AL4 GND* AH6 AJ5 AK4 AH5 AK3 AJ4 GND* AH4 VCCIO* AH3 AJ2

BG560
VCCIO* GND* AL14 AK14 AJ14 AN13 AM13 AL13 AK13 AJ13 GND* AM12 AL12 AK12 AN11 VCCIO* AJ12 AL11 AK11 AM10 GND* AL10 AJ11 AN9 AK10 AM9 AL9 AJ10 AM8 GND* VCCIO* AK9 AL8 AN7 AJ9 AL7 AK8 AN6 AM6 GND* VCCIO* AJ8 AL6 AK7 AM5 AM4 AJ7 GND* AL5 AK6 AN3 AK5 AJ6 AL4 GND* AJ5 VCCIO* AM1 AH5

PG559
VCCIO* GND* AE37 AF40 AD42 AF42 AF38 AG39 AG43 AG37 GND* AH40 AJ41 AG41 AK40 VCCIO* AJ39 AH42 VCCINT* AH36 AL39 GND* AJ37 AJ43 AM40 AK42 AN41 AL41 AR41 AK36 GND* VCCIO* AL37 AN43 AM38 AP42 AN39 AR43 AP40 AT40 GND* VCCIO* AN37 AR39 AT42 BA43 AU43 AU39 GND* AT38 AP36 AR37 AV42 VCCINT* AV40 AW41 GND* AY42 VCCIO* BB42 BC41

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XC4000XV Family Field Programmable Gate Arrays

XC40125XV Pad Name

I/O, GCK5 I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCIO GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O VCCIO GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O VCCINT I/O I/O VCCIO I/O I/O I/O (D5) I/O (CS0) GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O I/O I/O I/O I/O I/O GND

BG432
AG4 AG3 AH2 AH1 AF4 GND* AF3 AG2 AG1 AE4 AE3 AF2 VCCIO* GND* AF1 AD4 AD3 AE2 AD2 AC4 VCCIO* GND* AC3 AD1 AC2 AB4 GND* AB3 AB2 AB1 AA3 VCCIO* AA2 Y2 GND* Y4 Y3 Y1 W1 W4 W3 GND* VCCIO* W2 V2 V4 V3 U1 U2 GND*

BG560
AJ4 AK3 AH4 AL1 AG5 GND* AJ3 AK2 AG4 AH3 AF5 AJ2 VCCIO* GND* AJ1 AF4 AG3 AE5 AH1 AF3 AE4 AG2 VCCIO* GND* AD5 AF2 AF1 AD4 AE3 AC5 AE1 AD3 GND* AC4 AD2 AB5 AC3 VCCIO* AB4 AC1 AA5 AB3 GND* AB2 AA4 AA3 Y5 AA1 Y4 Y3 Y2 GND* VCCIO* W5 W4 W3 W1 V3 V5 GND*

PG559
AV38 BA39 AT36 BB40 AY40 GND* BA41 BB38 AY38 BC37 AW37 AT34 VCCIO* GND* AU35 AV36 BB36 AY36 BC35 AW35 AU33 AT30 VCCIO* GND* AV32 AU31 AW33 BB34 AY34 BC33 AU29 AT28 GND* BA35 BB30 VCCINT* AW31 AY32 VCCIO* BA33 AU27 BC29 AW29 GND* AY30 BA31 BB28 AW27 BC27 AV26 AU25 AY28 GND* VCCIO* BA29 AT24 BB26 AW25 BB24 AY26 GND*

XC40125XV Pad Name

I/O I/O I/O I/O I/O (D4) I/O VCCIO GND I/O (D3) I/O (RS) VCCINT I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCIO GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O (D2) I/O I/O I/O VCCIO I/O I/O VCCINT I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O I/O I/O I/O I/O I/O I/O

BG432
U4 U3 T1 T2 VCCIO* GND* T3 R1 R2 R4 GND* R3 P2 P3 P4 N1 N2 VCCIO* GND N3 N4 M1 M2 M3 M4 GND* L2 L3 VCCIO* K1 K2 K3 K4 GND* J2 J3 J4 H1 GND* VCCIO* H2 H3 H4 G2 G3 F1 -

BG560
V4 V2 U2 U1 U5 U4 VCCIO* GND* U3 T2 T3 T5 T4 R1 GND* R3 R4 R5 P2 P3 P4 VCCIO* GND* N1 P5 N2 N3 N4 M2 N5 M3 GND* M4 L1 L3 M5 VCCIO* K2 L4 J1 K3 GND* L5 J2 K4 J3 H2 K5 H3 J4 GND* VCCIO* G1 F1 J5 G3 H4 F2 E2

PG559
AV24 AU23 BA27 BC23 AY24 AW23 VCCIO* GND* BA23 AV22 VCCINT* AY22 BB22 AU21 AW21 GND* BA21 BC21 AY20 BB20 AT20 AV20 VCCIO* GND* AW19 AY18 BB18 AU19 BC17 BA17 AV18 AW17 GND* AY16 BB16 AU17 BA15 VCCIO* AW15 BC15 VCCINT* AY14 BA13 GND* AT16 BB14 AU15 BC11 AW13 BB10 AY12 BA11 GND* VCCIO* AT14 AU13 AV12 BC9 AW11 BB8 AY10

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XC40125XV Pad Name

I/O GND VCCIO I/O (D1) I/O (RCLK RDY/BUSY) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCCIO O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) VCCINT I/O I/O I/O I/O GND I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCCIO GND I/O I/O I/O I/O I/O I/O I/O I/O VCCIO GND I/O I/O

BG432
GND* VCCIO* G4 F2 F3 E1 F4 E2 GND* E3 D1 E4 D2 C2 D3 D4 VCCIO* C4 GND* B3 D5 B4 C5 A4 D6 GND* B5 C6 A5 D7 B6 A6 VCCIO* GND* D8 C7 B7 D9 B8 A8 VCCIO* GND* -

BG560
H5 GND* VCCIO* F3 G4 D2 E3 G5 C1 GND* F4 D3 B3 F5 E4 D4 C4 VCCIO* E6 GND* D5 A2 D6 A3 E7 C5 GND* B4 D7 C6 E8 B5 A5 VCCIO* GND* D8 C7 E9 A6 B7 D9 C8 E10 VCCIO* GND* B8 A8

PG559
AU11 GND* VCCIO* BA9 AW9 BC7 AY8 AV8 AT10 GND* AU9 BB6 AW7 BC3 AY6 BB4 BA5 VCCIO* BA3 GND* AT8 AV6 VCCINT* BB2 AY4 AR7 AP8 GND* AT6 AY2 AU5 BA1 AV4 AW3 VCCIO* GND* AN7 AR5 AV2 AT4 AU1 AR3 AT2 AL7 VCCIO* GND* AK8 AM6

XC40125XV Pad Name

I/O I/O I/O I/O I/O I/O GND I/O I/O VCCINT I/O I/O VCCIO I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCCIO I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) GND I/O I/O I/O I/O VCCINT I/O (A6) I/O (A7) GND
1/29/98

BG432
D10 C9 B9 C10 GND* B10 A10 C11 D12 VCCIO* B11 C12 GND* D13 B12 C13 A12 D14 B13 GND* VCCIO* C14 A13 B14 D15 C15 B15 GND* A15 C16 B16 A16 GND*

BG560
D10 C9 E11 A9 C10 D11 GND* B10 E12 C11 B11 VCCIO* D12 A11 E13 C12 GND* B12 D13 C13 E14 A13 D14 C14 B14 GND* VCCIO* E15 D15 C15 A15 C16 E16 GND* D16 B16 B17 C17 E17 D17 GND*

PG559
AN5 AR1 AP4 AN3 AP2 AJ7 GND* AH8 AL5 VCCINT* AN1 AM4 VCCIO* AL3 AJ5 AK2 AG7 GND* AK4 AJ3 AG5 AJ1 AF6 AH2 AE7 AH4 GND* VCCIO* AG3 AD8 AG1 AF4 AE5 AD6 GND* AD4 AF2 AC7 AD2 VCCINT* AC5 AC3 GND*

* Pads labelled GND*, VCCIO*, or VCCINT* are internally bonded to Ground or VCCIO planes within the package. They have no direct connection to any specific package pin.

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Additional XC40125XV Package Pins

PG559 A13 C37 N1 AE41 AU37 BA37 H12 V36 AT26 A5 E5 H22 W1 AH38 AV16 BB12 7/21/97 BG560 A4 B13 D33 T33 AK1 AM15 AN24 A7 A32 B31 A10 B19 E5 V1 AK4 AM21 AN30 A12 B1 C2 A16 B32 H1 W32 AK33 AM32 VCCIO Pins A22 A26 C3 C31 K33 M1 AA2 AB33 AL2 AL3 AN4 AN8 GND Pins A14 A18 A20 B6 B9 B15 E1 F32 G2 A30 C32 N32 AD1 AL31 AN12 A24 B23 G33 B2 D1 R2 AF33 AM2 AN18 A29 B27 J32 A31 F14 N43 AK6 AU41 BC1 H18 AF8 AT32 A19 E39 K6 W43 AM2 AV28 BB32 VCCIO Pins A43 B2 C7 F30 G3 G7 P6 P38 W3 AK38 AL1 AL43 AV14 AV30 BA7 BC13 BC31 BC43 VCCINT Pins** H26 H32 M8 AF36 AM8 AM36 GND Pins A25 A39 B12 E43 F10 F16 K38 M2 M42 AB8 AB36 AE1 AM42 AP6 AP38 AV34 AW1 AW5 BC5 BC19 BC25 C19 G37 W41 AU3 BA19 M36 AT12 B32 F28 T6 AE43 AT22 AW39 BC39 C25 G41 AE3 AU7 BA25 V8 AT18 E1 F34 T38 AH6 AV10 AW43 -

K1 V33 AE2 AM11 AN5 A1 6/4/97

L2 W2 AG1 AM19 AN10 A33

M33 Y1 AG32 AM25 AN14 AC2

P1 Y33 AH2 AM28 AN16 N.C. Pins AN1

P33 AB1 AJ33 AM33 AN20 AN33

R32 AC32 AL32 AM7 AN22 -

T1 AD33 AM3 AN2 AN27 -

BG432 A1 L4 AH11 C29 A11 L28 AH21 AJ3 A21 L31 AL1 AJ29 VCCIO Pins A31 D11 AA1 AA4 AL11 AL21 D21 AA28 AL31 L1 AA31 C3

A2 A25 C1 P1 AC31 AK2 AL14

A3 A29 C31 P31 AE1 AK30 AL18

A7 A30 D16 T4 AE31 AK31 AL23

GND Pins A9 B1 G1 T28 AH16 AL2 AL25 N.C. Pins

A14 B2 G31 V1 AJ1 AL3 AL29

A18 B30 J1 V31 AJ31 AL7 AL30

A23 B31 J31 AC1 AK1 AL9

C8

** VCCINT pins must be connected to VCC in package compatible XC4085XL-PG559

Table 2: Revisions Version 4/98 Description Added timing specifications

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XC4000XLT Family Field Programmable Gate Arrays

0 4*

April 8, 1998 (Version 0.8)

Advance Product Specification

XC4000XLT Features
Note: This data sheet describes the XC4000XLT Family devices. This information does not necessarily apply to the other Xilinx families: XC4000, XC4000A, XC4000D, XC4000H, XC4000L, XC4000E, XC4000EX, XC4000XL or XC4000XV. For information on these devices, or for the most current information regarding the XC4000XLT family, see the Xilinx WEBLINX at http://www.xilinx.com. System featured Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Abundant ip-ops - Flexible function generators - Dedicated high-speed carry logic - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks System performance beyond 80 MHz Low power segmented routing architecture Systems-oriented features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors Congured by loading binary le - Unlimited reprogrammability Readback capability - Program verication - Internal node observability

XC4000XLT Electrical Features

Low-Voltage Device Functions at Vcc=3.0 - 3.6 Volts Vtt supply allows positive signal clamping to Vtt +0.6 V Fully 3.3 V PCI compliant I/O (Vtt connected to 3.3V) 5.0 V PCI compatible I/O for embedded systems with 8 loads or less (Vtt connected to 5.0 V) 5.0 V TTL compatible I/O (Vtt connected to 5.0V) 3.3 V LVTTL, LVCMOS compatible I/O

Additional XC4000XLT Family Features

Highest Performance XC4000XL architecture Highest Capacity Over 130,000 system gates Low Power 3.3 V technology Software Compatibility Bitstream compatible with XC4000XL devices Package Compatibility Footprint compatible with XC4000XL devices (except for Vtt power pins) Advanced Technology 0.35 micron CMOS process Buffered interconnect for maximum speed New latch capability in congurable logic blocks Improved VersaRingTM I/O interconnect for better xed pinout exibility Flexible high-speed clock network - 8 additional Early Buffers for shorter clock delays - Virtually unlimited number of clock signals Optional Multiplexer or 2-input function generator on device outputs 26 Address bits in master parallel conguration mode

PCI Compatible Features

LogiCORE PCI Interface 2.0 available - 33 MHz 32-Bit PCI interface - Master or Target mode - Implemented entirely in programmable logic - Up to 100,000 gates available for user logic Fully compliant 3.3 V PCI I/O - < 7 nsec input setup time - 0 nsec input hold time - < 11 nsec clock to output - Positive and negative input signal clamping - Meets 5.0 V PCI timing for up to 8 loads - 80 mA sink current at minimum AC drive point (2.2V)

XC4000XLT Family FPGAs

3.3V PCI Compliant XC4000XLT devices provide PCI compliant I/O. They differ from XC4000XL devices only in that they enable the positive input signal clamping function required by PCI specications. New Packages enable Positive Signal Clamping The XC4000XLT family of FPGAs is a new packaging option for the XC4000XL FPGAs. For XLT devices, Vtt, the positive clamping supply is made available to device pins. These Vtt pins replace 8 normal I/O pins. By connecting the Vtt pins to a positive power supply, the positive clamping diodes present in the IOBs are enabled.

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XC4000XLT Family Field Programmable Gate Arrays

Vtt

input voltage requirement of 7.0 V (for < 10 nsec). In order to meet the PCI test requirements and provide device protection, it it necessary to connect the Vtt pins to the 5.0 V power supply.

Clamp Diode IBUF

Difference Between the XC4000XLT and XC4000XL FPGAs

The only difference between XLT and XL devices is that in XLT devices, the Vtt supply is connected to package pins. By connecting the Vtt supply pins to a positive voltage, positive input signal clamping is enabled. The Vtt pins assigned to the Vtt supply are named in the pinout guide for the XC4013XLT, XC4028XLT, and XC4062XLT FPGAs. There are 8 Vtt pins in all package options.

Clamp Diode

X7939

Figure 1: Clamp Diodes Present in the XL, XLT IOBs

I/O Signaling Compliance

The I/O signaling compliance is a function of how the Vtt pins are connected. Connecting Vtt to a power supply programs the compliance for all the IOBs on the device. All 8 of the Vtt pins must be connected to the same voltage source. Vtt oating When Vtt is left oating, the I/O characteristics of the XLT devices will be identical to XL devices. I/O will be LVTTL and LVCMOS compatible. Vtt connected to 5.0V power. If Vtt is connected to the 5.0 V power supply, the XLT device will be TTL, LVTTL, LVCMOS and 5V-PCI compatible for up to 8 PCI loads. Vtt connected to 3.3V power If Vtt is connected to 3.3V power, the I/O will be LVTTL, LVCMOS, and 3.3V-PCI compliant. Note that 5V TTL and 5V CMOS is not allowed.

PCI Requirements for Clamp Diodes

Clamp diodes are electrical protection devices placed in the I/O buffer of a chip. Both 5 V PCI and 3.3 V PCI signalling environments require clamp diodes to ground, which all Xilinx 4K family devices have. The 3.3 V PCI specication also requires clamp diodes to 3.3 V. The clamp diode serves two purposes. It offers device protection and it controls the bus waveforms as signals are transitioning on the bus. The latter function is vital to the signal integrity of the bus and is why clamp diodes are mandatory in a 3.3 V PCI system.

5.0 V PCI Requirement for Maximum AC Ratings and Device Protection

The upper clamp diode is optional in 5 V systems. For 5 V signaling, the PCI specication simply requires the devices be able to withstand a maximum overshoot voltage of 11 V for a minimum of 11 nsec through a 55 ohm resistor. See the PCI Specication v2.1, p126 for more details on this particular test. XC4000XL/XLT devices have a maximum

Table 1: XC4000XLT Family Field Programmable Gate Arrays Logic Cells 1368 2432 5472 Max Logic Max. RAM Typical Gates Bits Gate Range (No RAM) (No Logic) (Logic and RAM)* 13,000 18,432 10,000 - 30,000 28,000 32,768 18,000 - 50,000 62,000 73,728 40,000 - 130,000 CLB Matrix 24 x 24 32 x 32 48 x 48 Total CLBs 576 1,024 2,304 Number of Max. Flip-Flops User I/O 1,536 184 2,560 185 5,376 352

Device XC4013XLT XC4028XLT XC4062XLT

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5.0 V Power 3.3 V Power

VCC-5 V 5 Volt Device

5 V PCI TTL LVTTL

VCC

Vtt LVTTL

VCC 3.3 Volt Device

XC4000XLT

Ground
X7145

Figure 2: XLT Power supply and signaling environment with Vtt connected to 5.0 V power supply

3.3 V Power

VCC

Vtt

3.3 V PCI LVTTL

VCC 3.3 Volt Device

XC4000XLT

Ground
X7146

Figure 3: XLT Power supply and signaling environment with Vtt connected to 3.3V power supply

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XC4000XLT Family Field Programmable Gate Arrays

Pin Locations for XC4013XLT Devices

XC4013XLT Pad Name VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC VTT I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS VTT VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC VTT I/O I/O I/O GND I/O PQ208 P183 P184 P185 P186 P187 P188 P189 P190 P191 192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 PQ240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P38 P39 P40 P41 P42 P43 P44 P45 P46 XC4013XLT Pad Name I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VTT VCC I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC VTT I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK4 GND DONE PQ208 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P103 PQ240 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120

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April 8, 1998 (Version 0.8)

XC4013XLT Pad Name VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O VTT VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O VCC VTT I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 , GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O

PQ208 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P159 P160 P161 P162 P163 P164

PQ240 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186

XC4013XLT Pad Name I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VTT VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND

PQ208 P165 P166 P167 P168 P169 P170 P171 P172 173 P174 P175 P176 P177 P178 P179 P180 P181 P182

PQ240 P187 P188 P189 P190 P191 P192 P193 P194 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211

8/21/1997

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin.

Additional XC4013XLT Package Pins

PQ208 P1 P102 P157 5/5/97 PQ240 P22 P204 P195 6/9/97 P37 P219 GND Pins P83 P98 N.C. Pins P143 P158 P3 P104 P158 N.C. Pins P51 P52 P105 P107 P206 P207 P53 P155 P208 P54 P156 -

Pins marked with this symbol are used for Ground connections on some revisions of the device. These pins may not physically connect to anything on the current device revision. However, they should be externally connected to Ground, if possible.

April 8, 1998 (Version 0.8)

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XC4000XLT Family Field Programmable Gate Arrays

Pin Locations for XC4028XLT Devices

XC4028XLT Pad Name VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) GND I/O I/O I/O I/O VCC VTT I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O I/O (A14) I/O, GCK8, (A15) VCC GND I/O, GCK1, (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS VTT VCC I/O I/O HQ 240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 XC4028XLT Pad Name I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC VTT I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O VCC GND I/O HQ 240 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69

4-180

April 8, 1998 (Version 0.8)

XC4028XLT Pad Name I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VTT VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC VTT I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM

HQ 240 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122

XC4028XLT Pad Name I/O (D7) I/O, GCK5 I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VTT VCC I/O (D5) I/O (CS0) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (D2) I/O VCC VTT I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK,RDY/BUSY)

HQ 240 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174

April 8, 1998 (Version 0.8)

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XC4000XLT Family Field Programmable Gate Arrays

XC4028XLT Pad Name I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O HQ 240 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 XC4028XLT Pad Name I/O I/O VTT VCC I/O I/O I/O I/O GND I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND 8/21/1997 HQ 240 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211

Additional XC4028XLT Package Pins

HQ240 GND Pins P204 10/7/97 P219 -

Note: These pins may be N.C. for this device revision, however for compatibility with other devices in this package, these pins should be tied to GND.

4-182

April 8, 1998 (Version 0.8)

Pin Locations for XC4062XLT Devices

XC4062XLT Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O GND I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC VTT I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI HQ240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 BG432 VCC* D17 A17 C17 B17 GND* C18 D18 B18 A19 B19 C19 VCC* GND* D19 A20 B20 C20 B21 D20 GND* C21 A22 VCC* B22 C22 B23 A24 GND* D22 C23 B24 C24 GND* D23 B25 A26 C25 D24 B26 GND* VCC* A27 D25 C26 B27 A28 D26 GND* C27 B28 D27 B29 C28 D28 VCC* GND* D29 C30 E28 E29 D30 XC4062XLT Pad Name I/O, TCK GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS VTT VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O HQ240 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 BG432 D31 GND* F28 F29 E30 E31 G28 G29 VCC* GND* F30 F31 H28 H29 G30 H30 GND* J28 J29 H31 J30 GND* K28 K29 K30 K31 VCC* L29 L30 GND* M30 M28 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 R31 GND* R30 R28 R29 T31 GND* VCC* T30 T29 U31 U30 U28 U29 V30 V29

April 8, 1998 (Version 0.8)

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XC4000XLT Family Field Programmable Gate Arrays

XC4062XLT Pad Name I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC VTT I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O XC4062XLT Pad Name I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VTT VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I//O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC VTT I/O I/O

HQ240 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71

BG432 V28 W31 VCC* GND* W30 W29 W28 Y31 Y30 Y29 GND* Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 GND* AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 AE28 AF30 AF29 AG31 AF28 GND* AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 GND* AK27 AJ26 AL27 AH25 AK26 AL26 VCC* GND* AH24 AJ25 AK25

HQ240 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104

BG432 AJ24 AH23 AK24 GND* AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 GND* AJ20 AH19 AK20 AJ19 AL20 AH18 GND* VCC* AK19 AJ18 AL19 AK18 AH17 AJ17 GND* AK17 AL17 AJ16 AK16 VCC* GND* AL16 AH15 AL15 AJ15 GND* AK15 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AJ12 AK11 GND* AH12 AJ11 VCC* AL10 AK10 AJ10

4-184

April 8, 1998 (Version 0.8)

XC4062XLT Pad Name I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VTT VCC I/O (D5) I/O (CS0)

HQ240 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142

BG432 AK9 GND* AL8 AH10 AJ9 AK8 GND* AJ8 AH9 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 GND* AH6 AJ5 AK4 AH5 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 GND* AF3 AG2 AG1 AE4 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 GND* AC3 AD1 AC2 AB4 GND* AB3 AB2 AB1 AA3 VCC* AA2 Y2

XC4062XLT Pad Name GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O (D2) I/O VCC VTT I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O (D1)

HQ240 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173

BG432 GND* Y4 Y3 Y1 W1 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 GND* U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 GND* R3 P2 P3 P4 N1 N2 VCC* GND* N3 N4 M1 M2 M3 M4 GND* L2 L3 VCC* K1 K2 K3 K4 GND* J2 J3 J4 H1 GND* H2 H3 H4 G2 G3 F1 GND* VCC* G4

April 8, 1998 (Version 0.8)

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XC4000XLT Family Field Programmable Gate Arrays

XC4062XLT Pad Name I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O GND I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VTT VCC I/O I/O GND I/O I/O XC4062XLT Pad Name I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) GND I/O I/O I/O I/O I/O (A6) I/O (A7) GND 8/21/1997

HQ240 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 -

BG432 F2 F3 E1 F4 E2 GND* E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 A4 D6 GND* B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7 B7 D9 B8 A8 GND* D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 GND* D13 B12

HQ240 P202 P203 P205 P206 P207 P208 P209 P210 P211

BG432 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 GND* A15 C16 B16 A16 GND*

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin.

Additional XC4062XLT Package Pins

HQ240 GND Pins P204 5/5/97 P219 -

Note: These pins may be N.C. for this device revision, however for compatibility with other devices in this package, these pins should be tied to GND.

BG432
VCC Pins

A1 D21 AA28 AL11 A2 A25 C1 P1 AC31 AK2 AL14 C8 5/5/97

A11 L1 AA31 AL21 A3 A29 C31 P31 AE1 AK30 AL18 -

A21 L4 AH11 AL31 A7 A30 D16 T4 AE31 AK31 AL23 -

A31 L28 AH21 GND Pins A9 B1 G1 T28 AH16 AL2 AL25 N.C. Pins -

C3 L31 AJ3 A14 B2 G31 V1 AJ1 AL3 AL29 -

C29 AA1 AJ29 A18 B30 J1 V31 AJ31 AL7 AL30 -

D11 AA4 AL1 A23 B31 J31 AC1 AK1 AL9 -

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April 8, 1998 (Version 0.8)

pwd

Spartan and Spartan-XL Families Table of Contents

1 4*

Spartan and Spartan-XL Families Field Programmable Gate Arrays

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLB Signal Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Blocks (IOBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Input Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Output Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing Channel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLB Routing Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Features Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Distributed RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Configuration Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-State Long Line Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Signals: GSR and GTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Set/Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global 3-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Including Boundary Scan in a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avoiding Inadvertent Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Daisy Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting CCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Stream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Redundancy Check (CRC) for Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delaying Configuration After Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Through the Boundary Scan Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Violating the Maximum High and Low Time Specification for the Readback Clock . . . . . . Readback with the XChecker Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-189 4-189 4-190 4-191 4-191 4-191 4-192 4-192 4-193 4-194 4-194 4-196 4-197 4-198 4-199 4-199 4-199 4-202 4-204 4-204 4-205 4-205 4-205 4-205 4-205 4-206 4-206 4-207 4-207 4-207 4-208 4-208 4-208 4-209 4-209 4-210 4-210 4-211 4-212 4-212 4-213 4-213 4-213 4-213 4-213 4-214 4-214 4-215

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Spartan Program Readback Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . Spartan Detailed Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan Horizontal Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . Spartan CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines . . . . . . . . . . . . Spartan CLB RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . . . . . . . . . . . Spartan CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing. . . . . . . . . . . . . . . . Spartan Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O). . . . . . . . . . . . . . . . . . Spartan IOB Input Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-XL Detailed Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-XL Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-XL Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-XL DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . Spartan-XL Guaranteed Input and Output Parameters (Pin-to-Pin) . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XCS05 & XCS05XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XCS10 & XCS10XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XCS20 & XCS20XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XCS30 & XCS30XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XCS40 & XCS40XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-215 4-216 4-216 4-216 4-216 4-217 4-218 4-218 4-219 4-220 4-222 4-222 4-223 4-224 4-225 4-226 4-226 4-226 4-226 4-227 4-228 4-229 4-231 4-231 4-232 4-233 4-235 4-237 4-241 4-242

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Preliminary Product Specification System level features - Available in both 5.0 Volt and 3.3 Volt versions - On-chip Select-RAMTM memory - Fully PCI compliant - Low power segmented routing architecture - Full readback capability for program verication and internal node observability - Dedicated high-speed carry logic - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks - IEEE 1149.1-compatible boundary scan logic support Versatile I/O and packaging - Low cost plastic packages available in all densities - Footprint compatibility in common packages across all Spartan and Spartan-XL devices - Individually programmable output slew-rate control maximizes performance and reduces noise - Hold time of 0.0 ns for input registers simplies system timing - 12-mA sink current per output Fully supported by powerful Xilinx development system - Foundation series: Fully integrated, shrink-wrap software - Alliance series: Over 100 PC and engineering workstation 3RD party development systems supported - Fully automatic mapping, placement and routing - Interactive design editor for design optimization

Introduction
The SpartanTM Series is the rst high-volume production FPGA solution to deliver all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, Core Solutions and prices that, in high volume, approach and in many cases are equivalent to mask programmed ASIC devices. The Spartan series is the result of more than thirteen years of FPGA design experience and feedback from thousands of customers. By streamlining the Spartan feature set, leveraging advanced hybrid process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. The Spartan Series currently has 10 members, as shown in Table 1.

Spartan Series Features

Note: The Spartan series devices described in this data sheet include the 5 V SpartanTM family of devices and the 3.3 V Spartan-XLTM family of devices. Next generation ASIC replacement technology - First ASIC replacement FPGA for high-volume production with on-chip RAM - Advanced 0.35m/0.50m process - Density up to 1862 logic cells or 40,000 system gates - Streamlined feature set based on XC4000 architecture - System performance beyond 80 MHz - Broad set of AllianceCORETM and LogiCORETM solutions available - Unlimited reprogrammability

Table 1: Spartan and Spartan-XL Series Field Programmable Gate Arrays Logic Cells 238 466 950 1368 1862 Max System Gates 5,000 10,000 20,000 30,000 40,000 Typical Gate Range (Logic and RAM)* 2,000 - 5,000 3,000 - 10,000 7,000 - 20,000 10,000 - 30,000 13,000 - 40,000 CLB Matrix 10 x 10 14 x 14 20 x 20 24 x 24 28 x 28 Total CLBs 100 196 400 576 784 Number of Flip-Flops 360 616 1,120 1,536 2,016 Max. Available User I/O 77 112 160 192 205

Device XCS05 & XCS05XL XCS10 & XCS10XL XCS20 & XCS20XL XCS30 & XCS30XL XCS40 & XCS40XL

* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

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General Overview
Spartan Series FPGAs are implemented with a regular, exible, programmable architecture of Congurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and surrounded by a perimeter of programmable Input/Output Blocks (IOBs), as seen in Figure 1. They have generous routing resources to accommodate the most complex interconnect patterns. The devices are customized by loading conguration data into internal static memory cells. Re-programming is possible an unlimited number of times. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA. The FPGA can either actively read its conguration data from an external serial PROM (Master Serial mode), or the conguration data can be written into the FPGA from an external device (Slave Serial mode). Spartan FPGAs can be used where hardware must be adapted to different user applications. FPGAs are ideal for

shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 50,000 systems per month. Spartan Series devices achieve high-performance, lowcost operation through the use of an advanced architecture and semiconductor technology. Spartan and Spartan-XL provide system clock rates exceeding 80 MHz and internal performance in excess of 150 MHz. In contrast to other FPGA devices, Spartan offers the most cost-effective solution while maintaining leading-edge performance. In addition to the conventional benet of high volume programmable logic solutions Spartan also offers on-chip edge-triggered single-port and dual-port RAM, clock enables on all ip-ops, fast carry logic, and many other features. The Spartan Series leverages the highly successful XC4000 architecture with many of that familys features and benets. Technology advancements have been derived from the XC4000XL and XC4000XV process developments.

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB CLB IOB CLB CLB CLB

IOB

BSCAN

OSC

IOB IOB

IOB CLB IOB Routing Channels IOB CLB IOB CLB CLB CLB CLB CLB CLB

IOB IOB

IOB IOB

IOB CLB IOB CLB CLB CLB

IOB IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

RDBK

START -UP
Rev 2.0

VersaRing Routing Channel

Figure 1: Basic FPGA Block Diagram

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Logic Functional Description

The Spartan Series uses a standard FPGA structure as shown in Figure 1. The FPGA consists of an array of congurable logic blocks (CLBs) placed in a matrix of routing channels. The input and output of signals is achieved through a set of input/output blocks (IOBs) forming a ring around the CLBs and routing channels. CLBs provide the functional elements for implementing the users logic. IOBs provide the interface between the package pins and internal signal lines. Routing channels provide paths to interconnect the inputs and outputs of the CLBs and IOBs.

ed block diagram in Figure 2. There are three look-up tables (LUT) which are used as logic function generators, two ip-ops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Description on page 4-199.

Function Generators
Two 16x1 memory look-up tables (F-LUT and G-LUT) are used to implement 4-input function generators, each offering unrestricted logic implementation of any Boolean function of up to four independent input signals (F1 to F4 or G1 to G4). Using memory look-up tables the propagation delay is independent of the function implemented. A third 3-input function generator (H-LUT) can implement any Boolean function of its three inputs. Two of these inputs are controlled by programmable multiplexers (see box A of Figure 2). These inputs can come from the F-LUT or GLUT outputs or from CLB inputs. The third input always comes from a CLB input. The CLB can, therefore, implement certain functions of up to nine inputs, like parity checking. The three LUTs in the CLB can also be combined to do any arbitrarily dened Boolean function of ve inputs.

The functionality of each circuit block is customized during conguration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA.

Congurable Logic Blocks (CLBs)

The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simpli-

B G-LUT
G4 G3 G2 G1 SR H1 DIN F4 F3 F2 F1 F4 Logic F3 Function F of F2 F1-F4 F1 G4 Logic G3 Function G of G2 G1-G4 G1 G D CK EC SR Q YQ

H-LUT
Logic Function H H1 of F,G,H1 F SR Y

D CK EC

XQ

F-LUT
K EC Multiplexer Controlled by Conguration Program

Rev 1.0

Figure 2: Spartan Simplied CLB Logic Diagram (some features not shown)

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A CLB can be used to implement any of the following functions: Any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables1 Any single function of ve variables Any function of four variables together with some functions of six variables Some functions of up to nine variables.
D

SR

GND GSR SD D Q Q

Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators signicantly improves system speed. In addition, the design-software tools can deal with each function generator independently. This exibility improves cell usage.

CK RD EC Vcc
Rev 1.1

Flip-Flops
Each CLB contains two ip-ops that can be used to register (store) the function generator outputs. The ip-ops and function generators can also be used independently (see Figure 2). The CLB input DIN can be used as a direct input to either of the two ip-ops. H1 can also drive either ipop via the H-LUT with a slight additional delay. The two ip-ops have common clock (CK), clock enable (EC) and set/reset (SR) inputs. Internally both ip-ops are also controlled by a global initialization signal (GSR) which is described in detail in Global Signals: GSR and GTS on page 4-205. Functionality of the ip-op is described in Table 2. Table 2: CLB Flip-Flop Functionality Mode Power-Up or GSR Flip-Flop Operation
Legend: X __/ SR 0* 1*

Multiplexer Controlled by Conguration Program

Figure 3: CLB Flip-Flop Functional Block Diagram (see CK path in Figure 3). Any inverter placed on the clock line in the design is automatically absorbed into the CLB. Clock Enable The clock enable line (EC) is active High. The EC line is shared by both ip-ops in a CLB. If either one is left disconnected, the clock enable for that ip-op defaults to the active state. EC is not invertible within the CLB. The clock enable is synchronous to the clock and must satisfy the setup and hold timing specied for the device. Set/Reset The set/reset line (SR) is an asynchronous active High control of the ip-op. SR can be congured as either set or reset at each ip-op. This conguration option determines the state in which each ip-op becomes operational after conguration. It also determines the effect of a GSR pulse during normal operation, and the effect of a pulse on the SR line of the CLB. The SR line is shared by both ip-ops. If SR is not specied for a ip-op the set/reset for that ipop defaults to the inactive state. SR is not invertible within the CLB.

CK X X __/ 0 X

EC X X 1* X 0

SR X 1 0* 0* 0*

D X X D X X

Q SR SR D Q Q

Dont care Rising edge (clock not inverted) Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value)

CLB Signal Flow Control

In addition to the H-LUT input control multiplexers (shown in box A of Figure 2) there are signal ow control multiplexers (shown in box B of Figure 2) which select the signals which drive the ip-op inputs and the combinatorial CLB outputs (X and Y).

Clock Input Each ip-op can be triggered on either the rising or falling clock edge. The CLB clock line is shared by both ip-ops. However, the clock is individually invertible for each ip-op

1. When three separate functions are generated, one of the function outputs must be captured in a ip-op internal to the CLB. Only two unregistered function generator outputs are available from the CLB.

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Each ip-op input is driven from a 4:1 multiplexer which selects among the three LUT outputs and DIN as the data source. Each combinatorial output is driven from a 2:1 multiplexer which selects between two of the LUT outputs. The X output can be driven from the F-LUT or H-LUT, the Y output from G-LUT or H-LUT. Control Signals There are four signal control multiplexers on the input of the CLB. These multiplexers allow the internal CLB control signals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be driven from any of the four general control inputs (C1 - C4 in Figure 4) into the CLB. Any of these inputs can drive any of the four internal control signals. The four internal control signals are: EC - Enable Clock SR - Asynchronous Set/Reset or H function generator Input DIN - Direct In or H function generator Input H1 - H function generator Input 1.
C1 C2 SR C3 C4 EC DIN

H1

Multiplexer Controlled by Conguration Program

Rev 1.1

Input/Output Blocks (IOBs)

User-congurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be con-

Figure 4: CLB Control Signal Interface gured for input, output, or bidirectional signals. Figure 5 shows a simplied functional block diagram of the Spartan IOB.

GTS T

D CK

Q OUTPUT DRIVER Programmable Slew Rate Programmable TTL/CMOS Drive Package Pad INPUT BUFFER

OK EC

I1

I2 D IK EC CK EC Q

Delay

Programmable Pull-Up/ Pull-Down Network Multiplexer Controlled by Conguration Program

Rev 1.1

Figure 5: Simplied Spartan IOB Block Diagram

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IOB Input Signal Path

The input signal to the IOB can be congured to either go directly to the routing channels (via I1 and I2 in Figure 5) or to the input register. The input register can be programmed as either an edge-triggered ip-op or a level-sensitive latch. The functionality of this register is shown in Table 3, and a simplied block diagram of the register can be seen in Figure 6. Table 3: Input Register Functionality Mode Power-Up or GSR Flip-Flop Latch Both
Legend: X __/ SR 0* 1*

The Spartan IOB data input path has a one-tap delay element: either the delay is inserted (default), or it is not. The added delay guarantees a zero hold time with respect to clocks routed through any of the Spartan global clock buffers. (See Global Nets and Buffers on page 4-198 for a description of the global clock buffers in the Spartan Series.) For a shorter input register setup time, with positive hold-time, attach a NODELAY attribute or property to the ip-op. The output of the input register goes to the routing channels (via I1 and I2 in Figure 5). The I1 and I2 signals that exit the IOB can each carry either the direct or registered input signal. The Spartan input buffers can be globally congured for either TTL (1.2 V) or CMOS (0.5 Vcc) thresholds, using an option in the bitstream generation software. The inputs of Spartan devices can be driven by the outputs of any 3.3 V device, if the Spartan inputs are in TTL mode. There is a slight input hysteresis of about 300 mV. Inputs on the Spartan-XL are TTL compatible and 3.3 V CMOS compatible. The Spartan output levels are also congurable; the two global adjustments of input threshold and output level are independent. Supported sources for Spartan Series device inputs are shown in Table 4. Table 4: Supported Sources for Spartan Series Device Inputs Spartan Spartan-XL Inputs Inputs 5.0 V, 5.0 V, 3.3 V TTL CMOS CMOS Unreli -able Data

CK X __/ 0 1 0 X

EC X 1* X 1* 1* 0

D X D X X D X

Q SR D Q Q D Q

Dont care Rising edge (clock not inverted) Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value)

The register choice is made by placing the appropriate library symbol. For example, IFD is the basic input ip-op (rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are also available. The clock signal inverter is also shown in Figure 6 on the CK line.

Source Any device, Vcc = 3.3 V, CMOS outputs Spartan Series, Vcc = 5 V, TTL outputs Any device, Vcc = 5 V, TTL outputs (Voh 3.7 V) Any device, Vcc = 5 V, CMOS outputs

GSR

SD D D Q Q

CK RD EC Vcc
Rev 1.1

Multiplexer Controlled by Conguration Program

The I/Os on the Spartan-XL are fully 5 V tolerant even though the Vcc is 3.3 volts. This allows 5 V signals to directly connect to the Spartan-XL inputs without damage, as shown in Table 4. In addition, the 3.3 volt Vcc can be applied before or after 5 volt signals are applied to the I/Os. This makes the Spartan-XL immune to power supply sequencing problems.

IOB Output Signal Path

Output signals can be optionally inverted within the IOB, and can pass directly to the output buffer or be stored in an

Figure 6: IOB Flip-Flop/Latch Functional Block Diagram

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edge-triggered ip-op and then to the output buffer. The functionality of this ip-op is shown in Table 5. Table 5: Output Flip-Flop Functionality Mode Power-Up or GSR Flip-Flop Clock X X __/ X 0 Clock Enable X 0 1* X X T 0* 0* 0* 1 0* D X X D X X Q SR Q D Z Q

Table 6: Supported Destinations for Spartan Series Outputs Spartan-XL Spartan Outputs Outputs Destination 3.3 V, 5.0 V, 5.0 V, CMOS TTL CMOS Any device, Vcc = 3.3 V, some1 CMOS-threshold inputs Any device, Vcc = 5.0 V, TTL-threshold inputs Any device, Vcc = 5 V, Unreliable CMOS-threshold inputs Data
1. Only if destination device has 5-V tolerant inputs

Legend: X __/ SR 0* 1* Z

Dont care Rising edge (clock not inverted) Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value) 3-state

Output Buffer An active-High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under conguration control, the output (O) and output 3-state (T) signals can be inverted. The polarity of these signals is independently congured for each IOB (see Figure 5). By default, a Spartan device output buffer pull-up structure is congured as a TTL-like totem-pole. The High driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below Vcc. Alternatively, the outputs can be globally congured as CMOS drivers, with additional p-channel pull-up transistors pulling to Vcc. This option, applied using the bitstream generation software, applies to all outputs on the device. It is not individually programmable. In a Spartan-XL device, all outputs are congured as CMOS drivers, therefore driving rail-to-rail. Any Spartan device with its outputs congured in TTL mode can drive the inputs of any typical 3.3 V device. (For a detailed discussion of how to interface between 5.0 V and 3.3 V devices, see the 3V Products section of The Programmable Logic Data Book.) Supported destinations for Spartan Series device outputs are shown in Table 6. Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or property to the output buffer or ip-op.

Spartan Series devices have a feature called Soft Startup, designed to reduce ground bounce when all outputs are turned on simultaneously at the end of conguration. When the conguration process is nished and the device starts up, the rst activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is determined by the individual conguration option for each IOB. Pull-up and Pull-down Network Programmable pull-up and pull-down resistors are used for tying unused pins to Vcc or Ground to minimize power consumption and reduce noise sensitivity. The congurable pull-up resistor is a p-channel transistor that pulls to Vcc. The congurable pull-down resistor is an n-channel transistor that pulls to Ground. The value of these resistors is typically 20 k 100 k (see specications section). This high value makes them unsuitable as wired-AND pull-up resistors. After conguration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are congured with the internal pull-up resistor active. Alternatively, they can be individually congured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pullup, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad. Set/Reset As with the CLB registers, the GSR signal can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two ip-ops can be individually congured to set or clear on reset and after conguration. Other than the global GSR net, no usercontrolled set/reset signal is available to the I/O ip-ops (see Figure 6). The choice of set or reset applies to both

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the initial state of the ip-op and the response to the GSR pulse. Independent Clocks Separate clock signals are provided for the input (IK) and output (OK) ip-ops. The clock can be independently inverted for each ip-op within the IOB, generating either falling-edge or rising-edge triggered ip-ops. The clock inputs for each IOB are independent. Common Clock Enables The input and output ip-ops in each IOB have a common clock enable input (EC), which through conguration, can be activated individually (see EC signal in Figure 6) for the input or output ip-op, or both. This clock enable operates exactly like the EC signal on the Spartan Series CLB. It cannot be inverted within the IOB.

This section describes the routing channels available in Spartan series devices. Figure 7 shows a general block diagram of the CLB routing channels. The implementation software automatically assigns the appropriate resources based on the density and timing requirements of the design. The following description of the routing channels is for information only and is simplied with some minor details omitted. For an exact interconnect description the designer should open a design in the EPIC design editor and review the actual connections in this tool. The routing channels will be discussed as follows; CLB routing channels which run along each row and column of the CLB array. IOB routing channels which form a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the CLB routing channels. Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals.

Routing Channel Description

All internal routing channels are composed of metal segments with programmable switching points and switching matrices to implement the desired routing. A structured, hierarchical matrix of routing channels is provided to achieve efcient automated routing. .

PSM

PSM

PSM

8 Singles

3 Longs

CLB

CLB

2 Doubles

PSM

PSM

PSM

2 Doubles

3 Longs

8 Singles

3 Longs

2 Doubles

Rev 1.1

Figure 7: Spartan Series CLB Routing Channels and Interface Block Diagram

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CLB Routing Channels

The routing channels around the CLB are derived from three types of interconnects; single-length, double-length, and longlines. At the intersection of each vertical and horizontal routing channel is a signal steering matrix called a Programmable Switch Matrix (PSM). Figure 7 shows the basic routing channel conguration showing single-length lines, double-length lines and longlines as well as the CLBs and PSMs. The CLB to routing channel interface is shown as well as how the PSMs interface at the channel intersections. CLB Interface A block diagram of the CLB interface signals is shown in Figure 8. The input signals to the CLB are distributed
YQ C4 G4 F4

evenly on all four sides providing maximum routing exibility. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algorithms. Inputs, outputs, and function generators can freely swap positions within a CLB to avoid routing congestion during the placement and routing operation. The exceptions are the clock (K) input and CIN/COUT signals. The K input is routed to dedicated global vertical lines as well as 4 single-length lines and is on the left side of the CLB. The CIN/COUT signals are routed through dedicated interconnects which do not interfere with the general routing structure. The output signals from the CLB are available to drive both vertical and horizontal channels. Programmable Switch Matrices The horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each PSM consists of programmable pass transistors used to establish connections between the lines (see Figure 9). For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a double-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix. Single-Length Lines Single-length lines provide the greatest interconnect exibility and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associated with each CLB. These lines connect the switching matrices that are located in every row and column of CLBs.

CIN COUT G1

Y G3

C3 C1 K F3 F1 X
Rev 1.1

CLB

XQ

F2

Figure 8: CLB Interconnect Signals

G2

C2

Six Pass Transistors Per Switch Matrix Interconnect Point

Figure 9: Programmable Switch Matrix

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Single-length lines are connected by way of the programmable switch matrices, as shown in Figure 9. Routing connectivity is shown in Figure 7. Single-length lines incur a delay whenever they go through a PSM. Therefore, they are not suitable for routing signals for long distances. They are normally used to conduct signals within a localized area and to provide the branching for nets with fanout greater than one. Double-Length Lines The double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two CLBs before entering a PSM. Double-length lines are grouped in pairs with the PSMs staggered, so that each line goes through a PSM at every other row or column of CLBs (see Figure 7). There are four vertical and four horizontal double-length lines associated with each CLB. These lines provide faster signal routing over intermediate distances, while retaining routing exibility. Longlines Longlines form a grid of metal interconnect segments that run the entire length or width of the array. Longlines are intended for high fan-out, time-critical signal nets, or nets that are distributed over long distances. Each Spartan series longline has a programmable splitter switch at its center. This switch can separate the line into
IOB IOB

two independent routing channels, each running half the width or height of the array. Routing connectivity of the longlines is shown in Figure 7. The longlines also interface to some 3-state buffers which is described later in 3-State Long Line Drivers on page 4-204. I/O Routing Spartan series devices have additional routing around the IOB ring. This routing is called a VersaRing. The VersaRing facilitates pin-swapping and redesign without affecting board layout. Included are eight double-length lines, and four longlines.

Global Nets and Buffers

The Spartan series devices have dedicated global networks. These networks are designed to distribute clocks and other high fanout control signals throughout the devices with minimal skew. Four vertical longlines in each CLB column are driven exclusively by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. The four global lines can be driven by either of two types of global buffers; Primary Global buffers (BUFGP) or Secondary Global buffers (BUFGS). Each of these lines can be accessed by one particular Primary Global buffer, or by any of the Secondary Global buffers, as shown in Figure 10. The clock pins of every CLB and IOB can also be sourced from local interconnect.
IOB IOB

locals

locals

locals

BUFGS PGCK1 SGCK1

locals

BUFGP SGCK4 PGCK4

4 BUFGP 4 IOB locals X4 locals IOB Any BUFGS One BUFGP per Global Line locals BUFGS CLB CLB locals CLB CLB

4 BUFGS locals 4

IOB Any BUFGS One BUFGP per Global Line locals BUFGP locals X4 locals IOB

X4

X4

PGCK2 locals locals locals BUFGP locals SGCK2 BUFGS

SGCK3 PGCK3

IOB

IOB

IOB

IOB

X6604

Figure 10: Spartan Series Global Net Distribution

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The four Primary Global buffers offer the shortest delay and negligible skew. Four Secondary Global buffers have slightly longer delay and slightly more skew due to potentially heavier loading, but offer greater exibility when used to drive non-clock CLB inputs. The Primary Global buffers must be driven by the semidedicated pads (PGCK1-4). The Secondary Global buffers can be sourced by either semi-dedicated pads (SGCK1-4) or internal nets. Each corner of the device has one Primary buffer and one Secondary buffer. Using the library symbol called BUFG results in the software choosing the appropriate clock buffer, based on the timing requirements of the design. A global buffer should be specied for all timing-sensitive global signal distribution. To use a global buffer, place a BUFGP (primary buffer), BUFGS (secondary buffer), or BUFG (either primary or secondary buffer) element in a schematic or in HDL code.

The 32 x 1 Single-Port conguration contains a RAM array with 32 locations, each one-bit wide. There is one data input, one data output, and one 5-bit address decoder. The Dual Port mode 16 x 1 conguration contains a RAM array with 16 locations, each one-bit wide. There are two 4-bit address decoders, one for each port. One port consists of an input for writing and an output for reading, all at a selected address. The other port consists of one output for reading from an independently selected address.

Table 7: CLB Memory Congurations Mode Single-Port Dual-Port 16 x 1 (16 x 1) x 2 32 x 1

Advanced Features Description

Distributed RAM
Optional modes for each CLB allow the function generators (F-LUT and G-LUT) to be used as Random Access Memory (RAM). Read and write operations are signicantly faster for this on-chip RAM than for off-chip implementations. This speed advantage is due to the relatively short signal propagation delays within the FPGA.

Memory Conguration Overview

There are two available memory conguration modes: single-port RAM and dual-port RAM. For both these modes, write operations are synchronous (edge-triggered), while read operations are asynchronous. In the Single-Port Mode, a single CLB can be congured as either a 16 x 1, (16 x 1) x 2 or 32 x 1 RAM array. In the Dual-Port mode, a single CLB can be congured only as one 16 x 1 RAM array. The different CLB memory congurations are summarized in Table 7. Any of these possibilities can be individually programmed into a Spartan Series CLB. The 16 x 1 Single-Port conguration contains a RAM array with 16 locations, each one-bit wide. One 4-bit address decoder determines the RAM location for write and read operations. There is one input for writing data and one output for reading data, all at the selected address. The (16 x 1) x 2 Single-Port conguration combines two 16 x 1 Single Port congurations (each according to the preceding description). There is one data input, one data output and one address decoder for each array. These arrays can be addressed independently.

The appropriate choice of RAM conguration mode for a given design should be based on timing and resource requirements, desired functionality, and the simplicity of the design process. Selection criteria include the following: Whereas the 32 x 1 Single-Port, the (16 x 1) x 2 Single-Port and the 16 x 1 Dual-Port congurations each use one entire CLB, the 16 x 1 Single-Port conguration uses only one half of a CLB. Due to its simultaneous read/write capability, the Dual-Port RAM can transfer twice as much data as the Single-Port RAM, which permits only one data operation at any given time. CLB memory conguration options are selected by using the appropriate library symbol in the design entry. Single-Port Mode There are three CLB memory congurations for the SinglePort RAM: 16 x 1, (16 x 1) x 2, and 32 x 1, the functional organization of which is shown in Figure 11. The Single-Port RAM signals and the CLB signals (Figure 2 on page 4-191) from which they are originally derived are shown in Table 8. Table 8: Single-Port RAM Signals RAM Signal D A[3:0] A4 (32 x 1 only) WE WCLK SPO Function Data In Address Address Write Enable Clock Single Port Out (Data Out) CLB Signal DIN or H1 F1-F4 or G1-G4 H1 SR K FOUT or GOUT

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n WRITE ROW SELECT READ ROW SELECT

q q

A[n-1:0] n INPUT REGISTER

16 x 1 32 x 1 RAM ARRAY q
q

WE D0 or D1

WRITE CONTROL

READ OUT

SPO

WCLK

Figure 11: Logic Diagram for the Single-Port RAM

NOTE: 1. The (16 x 1) x 2 conguration combines two 16 x 1 Single Port RAMs, each with its own independent address bus and data input. The same WE and WCLK signals are connected to both RAMs. 2. n = 4 for the 16 x 1 and (16 x 1) x 2 congurations. n = 5 for the 32 x 1 conguration

Writing data to the Single-Port RAM is essentially the same as writing to a data register. It is an edge-triggered (synchronous) operation performed by applying an address to the A inputs and data to the D input during the active edge of WCLK while WE is High. The timing relationships are shown in Figure 12. The High logic level on WE enables the input data register for writing. The active edge of WCLK latches the address, input data, and WE signals. Then, an internal write pulse is generated that loads the data into the memory cell.
TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

WCLK can be congured as active on either the rising edge (default) or the falling edge. While the WCLK input to the RAM accepts the same signal as the clock input to the associated CLBs ip-ops, the sense of this WCLK input can be inverted with respect to the sense of the ip-op clock inputs. Consequently, within the same CLB, data at the RAMs SPO line can be stored in a ip-op with either the same or the inverse clock polarity used to write data to the RAM. The WE input is active-High and cannot be inverted within the CLB. Allowing for settling time, the data on the SPO output reects the contents of the RAM location currently addressed. When the address changes, following the asynchronous delay TILO, the data stored at the new address location will appear on SPO. If the data at a particular RAM address is overwritten, after the delay TWOS, the new data will appear on SPO. Dual-Port Mode In dual-port mode, the function generators (F-LUT and GLUT) are used to create a 16 x 1 Dual-Port memory. Of the two data ports available, one permits read and write operations at the address specied by A[3:0] while the second provides only for read operations at the address specied independently by DPRA[3:0]. As a result, simultaneous read/write operations at different addresses (or even at the same address) are supported.

TILO

TWOS OLD

DATA OUT

NEW
X6461

The functional organization of the 16 x 1 Dual-Port RAM is shown in Figure 13.

Figure 12: Data Write and Access Timing for RAM

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4 WRITE ROW SELECT READ ROW SELECT

q q

A[3:0] INPUT REGISTER 4 4

16 x 1 RAM
q q

WE D

q q

WRITE CONTROL

READ OUT

SPO

WCLK

WRITE ROW SELECT

16 x 1 RAM
q q

READ ROW SELECT

q q

DPRA[3:0] 4

WRITE CONTROL

READ OUT

DPO

Figure 13: Logic Diagram for the Dual-Port RAM The Dual-Port RAM signals and the CLB signals from which they are originally derived are shown in Table 9. Table 9: Dual-Port RAM Signals RAM Signal D A[3:0] Function Data In Read Address for Single-Port. Write Address for Single-Port and Dual-Port. Read Address for Dual-Port Write Enable Clock Single Port Out (addressed by A[3:0]) Dual Port Out (addressed by DPRA[3:0]) CLB Signal DIN F1-F4 previously. Single Port Out (SPO) serves as the data output for the lower memory. Therefore, SPO reects the data at address A[3:0]. The other address port, labeled DPRA[3:0] for Dual Port Read Address, supplies the read address for the upper memory. The write address for this memory, however, comes from the address A[3:0]. Dual Port Out (DPO) serves as the data output for the upper memory. Therefore, DPO reects the data at address DPRA[3:0]. By using A[3:0] for the write address and DPRA[3:0] for the read address, and reading only the DPO output, a FIFO that can read and write simultaneously is easily generated. The simultaneous read/write capability possible with the Dual-Port RAM can provide twice the effective data throughput of a Single-Port RAM alternating read and write operations. The timing relationships for the Dual-Port RAM mode are shown in Figure 12. Note that write operations to RAM are synchronous (edgetriggered); however, data access is asynchronous.

DPRA[3:0] WE WCLK SPO DPO

G1-G4 SR K FOUT GOUT

The RAM16X1D primitive used to instantiate the Dual-Port consists of an upper and a lower 16 x 1 memory array. The address port labeled A[3:0] supplies both the read and write addresses for the lower memory array, which behaves the same as the 16 x 1 Single-Port RAM array described

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Initializing RAM at FPGA Conguration Both RAM and ROM implementations of the Spartan series are initialized during device conguration. The initial contents are dened via an INIT attribute or property attached to the RAM or ROM symbol, as described in the schematic library guide. If not dened, all RAM contents are initialized to zeros, by default. RAM initialization occurs only during device conguration. The RAM content is not affected by GSR. More Information on using RAM inside CLBs Three application notes are available from Xilinx that discuss synchronous (edge-triggered) RAM: Xilinx Edge-Triggered and Dual-Port RAM Capability, Implementing FIFOs in Xilinx RAM, and Synchronous and Asynchronous FIFO Designs. All three application notes apply to both the Spartan and the Spartan-XL series.

The carry chain in Spartan devices can run either up or down. At the top and bottom of the columns where there are no CLBs above and below, the carry is propagated to the right.

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

Fast Carry Logic

Each CLB F-LUT and G-LUT contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is passed on to the function generator in the adjacent CLB. The carry chain is independent of normal routing resources. (See Figure 14.) Dedicated fast carry logic greatly increases the efciency and performance of adders, subtractors, accumulators, comparators and counters. It also opens the door to many new applications involving arithmetic operation, where the previous generations of FPGAs were not fast enough or too inefcient. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addition in digital signal processing are two typical applications. The two 4-input function generators can be congured as a 2-bit adder with built-in hidden carry that can be expanded to any length. This dedicated carry circuitry is so fast and efcient that conventional speed-up methods like carry generate/propagate are meaningless even at the 16-bit level, and of marginal benet at the 32-bit level. This fast carry logic is one of the more signicant features of the Spartan series, speeding up arithmetic and counting functions.

CLB

CLB

CLB

CLB

X6610

Figure 14: Available Spartan Carry Propagation Paths Figure 15 on page 4-203 shows a Spartan series CLB with dedicated fast carry logic. The carry logic shares operand and control inputs with the function generators. The carry outputs connect to the function generators, where they are combined with the operands to form the sums. Figure 16 on page 4-204 shows the details of the carry logic for the Spartan. This diagram shows the contents of the box labeled CARRY LOGIC in Figure 15. The fast carry logic can be accessed by placing special library symbols, or by using Xilinx Relationally Placed Macros (RPMs) that already include these symbols.

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CARRY LOGIC

C OUT

D IN

G Y

G CARRY

G4

G3 G G2 DIN H G F G1 EC COUT0 D S/R Q YQ

H1

DIN F CARRY H G F D S/R Q XQ

F4

EC

F3 F F2 F1 H X F

CIN

S/R

EC S6699_01

Figure 15: Fast Carry Logic in Spartan CLB

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C OUT M G1 1 0 I G4 0 1 G2 M

G3 C OUT0 M F2 M 1 0 F1 M M M F3 M 0 1 3 1 0 C IN M 0 F4 1 TO FUNCTION GENERATORS

S2000_01

Figure 16: Detail of Spartan Dedicated Carry Logic

3-State Long Line Drivers

A pair of 3-state buffers is associated with each CLB in the array. These 3-state buffers (BUFT) can be used to drive signals onto the nearest horizontal longlines above and below the CLB. They can therefore be used to implement multiplexed or bidirectional buses on the horizontal longlines, saving logic resources. There is a weak keeper at each end of these two horizontal longlines. This circuit prevents undened oating levels. However, it is overridden by any driver. The buffer enable is an active-High 3-state (i.e. an activeLow enable), as shown in Table 10.

Three-State Buffer Examples

Figure 17 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the buffer 3-state signal. Pay particular attention to the polarity of the T pin when using these buffers in a design. Active-High 3-state (T) is identical to an active-Low output enable, as shown in Table 10. Table 10: Three-State Buffer Functionality IN X IN T 1 0 OUT Z IN

~100 k

Z = DA A + DB B + DC C + DN N

DA BUFT A "Weak Keeper"

DB BUFT B

DC BUFT C

DN BUFT N
X6466

Figure 17: 3-State Buffers Implement a Multiplexer

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On-Chip Oscillator
Spartan series devices include an internal oscillator. This oscillator is used to clock the power-on time-out, for conguration memory clearing, and as the source of CCLK in Master conguration mode. The oscillator runs at a nominal 8 MHz frequency that varies with process, Vcc, and temperature. The output frequency falls between 4 MHz and 10 MHz. The oscillator output is optionally available after conguration. Any two of four resynchronized taps of a built-in divider are also available. These taps are at the fourth, ninth, fourteenth and nineteenth bits of the divider. Therefore, if the primary oscillator output is running at the nominal 8 MHz, the user has access to an 8 MHz clock, plus any two of 500 kHz, 16 kHz, 490 Hz and 15 Hz (up to 10% lower for low-voltage devices). These frequencies can vary by as much as -50% or +25%. These signals can be accessed by placing the OSC library element in a schematic or in HDL code. The oscillator is automatically disabled after conguration if the OSC symbol is not used in the design.

Global 3-State
A separate Global 3-State line (GTS) as shown in Figure 5 on page 4-193 forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. GTS does not compete with other routing resources; it uses a dedicated distribution network. GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. This is similar to what is shown in Figure 18 for GSR except the IBUF would be connected to GTS. A specic pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3-State signal. Alternatively, GTS can be driven from any internal node.

Boundary Scan
The bed of nails has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technology and multi-layer boards. The IEEE Boundary Scan Standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for I/O and internal logic. This structure is easily implemented with a four-pin interface on any boundary scan-compatible IC. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two. The Spartan Series implements IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE and EXTEST boundary scan instructions. When the boundary scan conguration option is selected, three normal user I/O pins become dedicated inputs for these functions. Another user output pin becomes the dedicated boundary scan output. The details of how to enable this circuitry are covered later in this section. By exercising these input signals, the user can serially load commands and data into these devices to control the driving of their outputs and to examine their inputs. This method is an improvement over bed-of-nails testing. It avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fth pin, a reset for the control logic, is described in the standard but is not implemented in Xilinx devices. The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state machine, an instruction register and a number of data registers. The functional details can be found in the IEEE 1149.1 specication and are also

Global Signals: GSR and GTS

Global Set/Reset
A separate Global Set/Reset line, as shown in Figure 3 on page 4-192 for the CLB and Figure 6 on page 4-194 for the IOB, sets or clears each ip-op during power-up, reconguration, or when a dedicated Reset net is driven active. This global net (GSR) does not compete with other routing resources; it uses a dedicated distribution network. Each ip-op is congured as either globally set or reset in the same way that the local set/reset (SR) is specied. Therefore, if a ip-op is set by SR, it is also set by GSR. Similarly, if in reset mode, it is reset by both SR and GSR.
STARTUP PAD IBUF GSR GTS Q2 Q3 Q1Q4 CLK DONEIN
X5260

Figure 18: Schematic Symbols for Global Set/Reset GSR can be driven from any user-programmable pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GSR pin of the STARTUP symbol. (See Figure 18.) A specic pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the GSR signal. Alternatively, GSR can be driven from any internal node.

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discussed in the Xilinx application note: Boundary Scan in FPGA Devices. Figure 19 on page 4-206 is a diagram of the Spartan Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. Spartan Series devices can also be congured through the boundary scan logic. See Conguration Through the Boundary Scan Pins on page 4-213.

The other standard data register is the single ip-op BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA provides two additional data registers that can be specied using the BSCAN macro. The FPGA provides two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions. For these instructions, two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE).

Data Registers
The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-State Control. Non-IOB pins have appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures all In, Out, and 3-state pins. The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals.
IOB.T

Instruction Set
The Spartan Series boundary scan instruction set also includes instructions to congure the device and read back the conguration data. The instruction set is coded as shown in Table 11.

DATA IN 0 1 0 IOB IOB IOB IOB IOB D Q D sd Q 1

LE

IOB

IOB

1 0

sd D Q D Q

IOB

IOB LE

IOB

IOB IOB.I 1 0 1 sd D Q D Q

IOB

IOB

IOB

IOB

IOB

IOB

LE 1 IOB.Q IOB.T 0

IOB

BYPASS REGISTER INSTRUCTION REGISTER

IOB

TDI

M TDO U X

0 1 0 D Q D sd Q 1

LE

1 0 D Q D

sd Q

LE

1 IOB.I 0

DATAOUT SHIFT/ CLOCK DATA CAPTURE REGISTER

UPDATE

EXTEST

X9016

Figure 19: Spartan Series Boundary Scan Logic

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Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The input-only pins contribute only the In bit to the boundary scan I/O data register, while the output-only pins contributes all three bits. The rst two bits in the I/O data register are TDO.T and TDO.O, which can be used for the capture of internal signals. The nal bit is BSCANT.UPD, which can be used to drive an internal net. These locations are primarily used by Xilinx for internal testing. From a cavity-up view of the chip (as shown in EPIC), starting in the upper right chip corner, the boundary scan dataregister bits are ordered as shown in Figure 20. The device-specic pinout tables for the Spartan Series include the boundary scan locations for each IOB pin. BSDL (Boundary Scan Description Language) les for Spartan Series devices are available on the Xilinx FTP site.
Bit 0 ( TDO end) Bit 1 Bit 2 TDO.T TDO.O Top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom)

MODE.I

Bottom-edge IOBs (Left to Right)

Right-edge IOBs (Bottom to Top) (TDI end) BSCANT.UPD

S6075_02

Figure 20:

Boundary Scan Bit Sequence

Including Boundary Scan in a Schematic

If boundary scan is only to be used during conguration, no special schematic elements need be included in the schematic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user functions after conguration. To indicate that boundary scan remain enabled after conguration, place the BSCAN library symbol and connect the TDI, TMS, TCK and TDO pad symbols to the appropriate pins, as shown in Figure 21. Even if the boundary scan symbol is used in a schematic, the input pins TMS, TCK, and TDI can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDI and TCK. Table 11: Boundary Scan Instructions Instruction I2 I1 I0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 Test Selected EXTEST SAMPLE/ PRELOAD USER 1 TDO Source DR DR I/O Data Source DR Pin/Logic

Avoiding Inadvertent Boundary Scan

If TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant during conguration. In some applications, a situation may occur where TMS or TCK is driven during conguration. This may cause the device to go into boundary scan mode and disrupt the conguration process. To prevent activation of boundary scan during conguration, do either of the following: TMS: Tie High to put the Test Access Port controller in a benign RESET state TCK: Tie High or Lowdon't toggle this clock input.

For more information regarding boundary scan, refer to the Xilinx Application Note, Boundary Scan in FPGA Devices.

Optional IBUF BSCAN TDI TMS TCK From User Logic

TDI TMS TCK TDO1 TDO2 TDO DRCK IDLE SEL1 SEL2

To User Logic

BSCAN. User Logic TDO1 USER 2 BSCAN. User Logic TDO2 READBACK Readback Data Pin/Logic CONFIGURE DOUT Disabled Reserved BYPASS Bypass Register

TDO

To User Logic

X2675

Figure 21: Boundary Scan Schematic Example

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Conguration and Test

Conguration is the process of loading design-specic programming data into one or more FPGAs to dene the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. Spartan Series devices use several hundred bits of conguration data per CLB and its associated interconnects. Each conguration bit denes the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The Xilinx development system translates the design into a netlist le. It automatically partitions, places and routes the logic and generates the conguration data in PROM format.

Table 12: Pin Functions During Conguration

CONFIGURATION MODE <MODE Pin> SLAVE MASTER SERIAL SERIAL <High> <Low> MODE (I) MODE (I) HDC (HIGH) HDC (HIGH) LDC (LOW) LDC (LOW) INIT INIT DONE DONE PROGRAM (I) PROGRAM (I) CCLK (I) CCLK (O) DIN (I) DIN (I) DOUT DOUT TDI TDI TCK TCK TMS TMS TDO TDO Notes

USER OPERATION

Conguration Mode Control

Spartan series devices have two conguration modes. MODE = 1 sets Slave Serial mode MODE = 0 sets Master Serial mode

The control pin (MODE) is sampled prior to starting conguration to determine the conguration mode. After conguration, this pin is unused. The MODE pin has a weak pullup resistor turned on during conguration. With MODE High, Slave Serial mode is selected, which is the most popular conguration mode used primarily for daisy-chained devices. Therefore, for the most common conguration mode, the MODE pin can be left unconnected. (Note, however, that the internal pull-up resistor value can be as high as 100 k.) If the Master Serial mode is desired, the MODE pin should be connected directly to GND, or through a pulldown resistor of 1 K or less. During conguration, some of the I/O pins are used temporarily for the conguration process. All pins used during conguration are shown in Table 12 on page 4-208.

MODE I/O I/O I/O DONE PROGRAM CCLK (I) I/O SGCK4-I/O TDI-I/O TCK-I/O TMS-I/O TDO-(O) ALL OTHERS 1. A shaded table cell represents the internal pull-up used before and during conguration. 2. (I) represents an input; (O) represents an output. 3. INIT is an open-drain output during conguration.

When used in a daisy-chain conguration the Master Serial FPGA is placed as the rst device in the chain and is referred to as the lead FPGA. The lead FPGA presents the preamble data, and all data that overows the lead device, on its DOUT pin. There is an internal pipeline delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. See the timing diagram in Figure 22. In the bitstream generation software, the user can specify Fast Conguration Rate, which, starting several bits into the rst frame, increases the CCLK frequency by a factor of eight. For actual timing values please refer to the specication section. Be sure that the serial PROM and slaves are fast enough to support this data rate. Devices such as XC3000A and XC3100A do not support the Fast Conguration Rate option. The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is congured as user-I/O, but LDC is then restricted to be a permanently High user output after conguration. Using DONE can also avoid contention on DIN, provided the early DONE option is invoked. Figure 23 shows a full master/slave system. The leftmost device is in Master Serial mode, all other devices in the chain are in Slave Serial mode. Master Serial mode is selected by a Low on the MODE pin.

Master Serial Mode

The Master serial mode uses an internal oscillator to generate a Conguration Clock (CCLK) for driving potential slave devices and the Xilinx serial-conguration PROM (SPROM). The CCLK speed is selectable as either 1 MHz (default) or 8 MHz. Conguration always starts at the default slow frequency, then can switch to the higher frequency during the rst frame. Frequency tolerance is -50% to +25%. In Master Serial mode, the CCLK output of the device drives a Xilinx SPROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. The next data bit is put on the SPROM data output, connected to the FPGA DIN pin. The FPGA accepts this data on the subsequent rising CCLK edge.

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CCLK (Output) 2 TCKDS 1 Serial Data In TDSCK n n+1 n+2

Serial DOUT (Output)

n3

n2

n1

n
X3223

CCLK

Description DIN setup DIN hold

1 2

Symbol TDSCK TCKDS

Min 20 0

Max

Units ns ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conguration by pulling PROGRAM Low until Vcc is valid. 2. Master Serial mode timing is based on testing in slave mode.

Figure 22: Master Serial Mode Programming Switching Characteristics

Slave Serial Mode

In Slave Serial mode, the FPGA receives serial conguration data on the rising edge of CCLK and, after loading its conguration, passes additional data out, resynchronized on the next falling edge of CCLK. In this mode, an external signal drives the CCLK input of the FPGA (most often from a Master Serial device). The serial conguration bitstream must be available at the DIN input of the lead FPGA a short setup time before each rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overows the lead deviceon its DOUT pin. There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. Figure 23 shows a full master/slave system. A Spartan series device in Slave Serial mode should be connected as shown in the third device from the left. Slave Serial mode is selected by a high on the MODE pin. Slave Serial is the default mode if the MODE pin is left unconnected, as it has a weak pull-up resistors during conguration. Multiple slave devices with identical congurations can be wired with parallel DIN inputs. In this way, multiple devices can be congured simultaneously.

Serial Daisy Chain

Multiple devices with different congurations can be connected together in a daisy chain, and a single combined bitstream used to congure the chain of slave devices. To congure a daisy chain of devices, wire the CCLK pins of all devices in parallel, as shown in Figure 23 on page 4-210. Connect the DOUT of each device to the DIN of the next. The lead or master FPGA and following slaves each passes resynchronized conguration data coming from a single source. The header data, including the length count, is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames. After an FPGA has received its conguration data, it passes on any additional frame start bits and conguration data on DOUT. When the total number of conguration clocks applied after memory initialization equals the value of the 24-bit length count, the FPGAs begin the start-up sequence and become operational together. FPGA I/O are normally released two CCLK cycles after the last conguration bit is received. The daisy-chained bitstream is not simply a concatenation of the individual bitstreams. The PROM le formatter must be used to combine the bitstreams for a daisy-chained conguration.

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NOTE: M2, M1, M0 can be shorted to VCC if not used as I/O

VCC
4.7 K 4.7 K 4.7 K

MODE DOUT

N/C

MODE DIN DOUT

M0 M1 M2 DIN CCLK

PWRDN

DOUT

Spartan

VCC

CCLK

MASTER SERIAL
CCLK DIN PROGRAM DONE LDC INIT

XC17S00
4.7 K CLK DATA CE RESET/OE CEO VPP

+5 V

Spartan

FPGA

SLAVE

SLAVE

PROGRAM DONE INIT

RESET D/P INIT

(Low Reset Option Used)

PROGRAM

S9025_02

Figure 23: Master/Slave Serial Mode Circuit Diagram

DIN 1 TDCC CCLK

Bit n 2 TCCD

Bit n + 1 5 TCCL

4 TCCH DOUT (Output) Bit n - 1

3 TCCO Bit n
X5379

CCLK

Description DIN setup DIN hold DIN to DOUT High time Low time Frequency

1 2 3 4 5

Symbol TDCC TCCD TCCO TCCH TCCL FCC

Min 20 0 45 45

Max

30

10

Units ns ns ns ns ns MHz

Note: Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

Figure 24: Slave Serial Mode Programming Switching Characteristics

Setting CCLK Frequency

In Master mode, CCLK can be generated in either of two frequencies. In the default slow mode, the frequency ranges from 0.5 MHz to 1.25 MHz for Spartan series devices. In fast CCLK mode, the frequency ranges from 4 MHz to 10 MHz for Spartan series devices. The frequency is selected by an option when running the bitstream generation software. Slow mode is the default.

Data Stream Format

The data stream (bitstream) format is identical for both conguration modes. The data stream format is shown in Table 13. Bit-serial data is read from left to right. The conguration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator eld of ones. This header is followed by the actual conguration data in frames. The length and number of frames depends on the device type (see Table 14). Each frame begins with a start eld and ends with an error check. A postamble code is required to signal the end of

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data for a single device. In all cases, additional start-up bytes of data are required to provide four clocks for the startup sequence at the end of conguration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are dont-cares; these bytes are not included in bitstreams created by the Xilinx software. Table 13: Spartan Series Data Stream Formats Data Type Fill Byte Preamble Code Length Count Fill Bits Start Field Data Frame CRC or Constant Field Check Extend Write Cycle Postamble Start-Up Bytes LEGEND: Unshaded Light Dark Once per bitstream Once per data frame Once per device

A selection of CRC or non-CRC error checking is allowed by the bitstream generation software. The non-CRC error checking tests for a designated end-of-frame eld for each frame. For CRC error checking, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each frame. The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master serial mode, CCLK and address signals continue to operate externally. The user must detect INIT and initialize a new conguration by pulsing the PROGRAM pin Low or cycling Vcc.

11111111b 0010b COUNT(23:0) 1111b 0b DATA(n-1:0) xxxx (CRC) or 0110b 01111111b xxh

Cyclic Redundancy Check (CRC) for Conguration and Readback

The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial bitstream. The result of this calculation is tagged onto the data stream as additional check bits. The receiving system performs an identical calculation on the bitstream and compares the result with the received checksum. Each data frame of the conguration bitstream has four error bits at the end, as shown in Table 13. If a frame data error is detected during the loading of the FPGA, the conguration process with a potentially corrupted bitstream is terminated. The FPGA pulls the INIT pin Low and goes into a Wait state.

Table 14: Spartan Program Data Device Max System Gates CLBs (Row x Col.) IOBs Flip-Flops Horizontal Longlines TBUFs per Longline Bits per Frame Frames Program Data PROM Size (bits) XCS05 5,000 100 (10 x 10) 80 360 20 12 126 428 53,936 53,984 XCS10 10,000 196 (14 x 14) 112 616 28 16 166 572 94,960 95,008 XCS20 20,000 400 (20 x 20) 160 1,120 40 22 226 788 178,096 178,144 XCS30 30,000 576 (24 x 24) 192 1,536 48 26 266 932 247,920 247,968 XCS40 40,000 784 (28 x 28) 224 2,016 56 30 306 1,076 329,264 329,312

Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits PROM Size = Program Data + 40 (header) + 8 2. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header.

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During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is computed using the CRC-16 CCITT polynomial, as shown in Figure 25. The checksum consists of the 11 most signicant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLB outputs should not be included (Readback Capture option not used), and if RAM is present, the RAM content must be unchanged. Statistically, one error out of 2048 might go undetected.

Boundary Scan Instructions Available:

VCC Valid Yes

No

Test MODE, Generate One Time-Out Pulse of 16 or 64 ms

PROGRAM = Low Yes

Keep Clearing Configuration Memory

Conguration Sequence
There are four major steps in the Spartan Series power-up conguration sequence. Conguration Memory Clear Initialization Conguration Start-Up

EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory CONFIGURE* Once More (* if PROGRAM = High)

~1.3 s per Frame

INIT High? if Master Yes

No

Master Delays Before Sampling Mode Line

The full process is illustrated in Figure 26.

Sample Mode Line Master CCLK Goes Active Load One Configuration Data Frame LDC Output = L, HDC Output = H
s6076_01

Conguration Memory Clear

When power is rst applied or is reapplied to an FPGA, an internal circuit forces initialization of the conguration logic. When Vcc reaches an operational level, and the circuit passes the write and read test of a sample pair of conguration bits, a time delay is started. This time delay is nominally 16 ms, and up to 10% longer in the Spartan-XL devices. The delay is four times as long when in Master Serial Mode (MODE is Low), to allow ample time for all slaves to reach a stable Vcc. When all INIT pins are tied together, as recommended, the longest delay takes precedence. Therefore, devices with different time delays can easily be mixed and matched in a daisy chain. This delay is applied only on power-up. It is not applied when reconguring an FPGA by pulsing the PROGRAM pin

Frame Error No SAMPLE/PRELOAD BYPASS Configuration memory Full Yes Pass Configuration Data to DOUT

Yes

Pull INIT Low and Stop

No

X2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

X15 X16 15

CCLK Count Equals Length Count Yes

No

SERIAL DATA IN

Start-Up Sequence
F

Polynomial: X16 + X15 + X2 + 1

0 15 14 13 12 11 10 9 START BIT

LAST DATA FRAME

CRC CHECKSUM

Readback Data Stream

X1789

EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK

Operational

If Boundary Scan is Selected

Figure 25: Circuit for Generating CRC-16 Figure 26: Power-up Conguration Sequence

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I/O Active

Low. During this time delay, or as long as the PROGRAM input is asserted, the conguration logic is held in a Conguration Memory Clear state. The conguration-memory frames are consecutively initialized, using the internal oscillator. At the end of each complete pass through the frame addressing, the power-on time-out delay circuitry and the level of the PROGRAM pin are tested. If neither is asserted, the logic initiates one additional clearing of the conguration frames and then tests the INIT input.

A Low on the PROGRAM input is the more radical approach, and is recommended when the power-supply rise time is excessive or poorly dened. As long as PROGRAM is Low, the FPGA keeps clearing its conguration memory. When PROGRAM goes High, the conguration memory is cleared one more time, followed by the beginning of conguration, provided the INIT input is not externally held Low. Note that a Low on the PROGRAM input automatically forces a Low on the INIT output. The Spartan Series PROGRAM pin has a permanent weak pull-up. Using an open-collector or open-drain driver to hold INIT Low before the beginning of conguration causes the FPGA to wait after completing the conguration memory clear operation. When INIT is no longer held Low externally, the device determines its conguration mode by capturing the state of the MODE pin, and is ready to start the conguration process. A master device waits up to an additional 300 s to make sure that any slaves in the optional daisy chain have seen that INIT is High.

Initialization
During initialization and conguration, user pins HDC, LDC, INIT and DONE provide status outputs for the system interface. The outputs LDC, INIT and DONE are held Low and HDC is held High starting at the initial application of power. The open drain INIT pin is released after the nal initialization pass through the frame addresses. There is a deliberate delay before a Master-mode device recognizes an inactive INIT. Two internal clocks after the INIT pin is recognized as High, the device samples the MODE pin to determine the conguration mode. The appropriate interface lines become active and the conguration preamble and data can be loaded.

Conguration Through the Boundary Scan Pins

Spartan Series devices can be congured through the boundary scan pins. The basic procedure is as follows: Power up the FPGA with INIT held Low (or drive the PROGRAM pin Low for more than 300 ns followed by a High while holding INIT Low). Holding INIT Low allows enough time to issue the CONFIG command to the FPGA. The pin can be used as I/O after conguration if a resistor is used to hold INIT Low. Issue the CONFIG command to the TMS input Wait for INIT to go High Sequence the boundary scan Test Access Port to the SHIFT-DR state Toggle TCK to clock data into TDI pin.

Conguration
The 0010 preamble code indicates that the following 24 bits represent the length count. The length count is the total number of conguration clocks needed to load the complete conguration data. (Four additional conguration clocks are required to complete the conguration process, as discussed below.) After the preamble and the length count have been passed through to any device in the daisy chain, its DOUT is held High to prevent frame start bits from reaching any daisy-chained devices. A specic conguration bit, early in the rst frame of a master device, controls the conguration-clock rate and can increase it by a factor of eight. Therefore, if a fast conguration clock is selected by the bitstream, the slower clock rate is used until this conguration bit is detected. Each frame has a start eld followed by the frame-conguration data bits and a frame error eld. If a frame data error is detected, the FPGA halts loading, and signals the error by pulling the open-drain INIT pin Low. After all conguration frames have been loaded into an FPGA, DOUT again follows the input data so that the remaining data is passed on to the next device.

The user must account for all TCK clock cycles after INIT goes High, as all of these cycles affect the Length Count compare. For more detailed information, refer to the Xilinx application note, Boundary Scan in FPGA Devices. This application note also applies to Spartan and Spartan-XL devices.

Readback
The user can read back the content of conguration memory and the level of certain internal nodes without interfering with the normal operation of the device. Readback not only reports the downloaded conguration bits, but can also include the present state of the device, represented by the content of all ip-ops and latches in CLBs and IOBs, as well as the content of function generators used as RAMs. 4-213

Delaying Conguration After Power-Up

There are two methods of delaying conguration after power-up: put a logic Low on the PROGRAM input, or pull the bidirectional INIT pin Low, using an open-collector (open-drain) driver. (See Figure 26 on page 4-212.)

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IF UNCONNECTED, DEFAULT IS CCLK

CLK READ_TRIGGER IBUF TRIG READBACK

DATA RIP OBUF

READ_DATA

s1786_01

Figure 27: Readback Schematic Example Spartan Series Readback does not use any dedicated pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be routed to any IOB. To access the internal Readback signals, place the READBACK library symbol and attach the appropriate pad symbols, as shown in Figure 27. After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress) output goes High on the next rising edge of RDBK.CLK. Subsequent rising edges of this clock shift out Readback data on the RDBK.DATA net. Readback data does not include the preamble, but starts with ve dummy bits (all High) followed by the Start bit (Low) of the rst frame. The rst two data bits of the rst frame are always High. Each frame ends with four error check bits. They are read back as High. The last seven bits of the last frame are also read back as High. An additional Start bit (Low) and an 11-bit Cyclic Redundancy Check (CRC) signature follow, before RDBK.RIP returns Low. Readback Abort When the Readback Abort option is selected, a High-toLow transition on RDBK.TRIG terminates the readback operation and prepares the logic to accept another trigger. After an aborted readback, additional clocks (up to one readback clock per conguration frame) may be required to re-initialize the control logic. The status of readback is indicated by the output control net RDBK.RIP. RDBK.RIP is High whenever a readback is in progress. Clock Select CCLK is the default clock. However, the user can insert another clock on RDBK.CLK. Readback control and data are clocked on rising edges of RDBK.CLK. If readback must be inhibited for security reasons, the readback control nets are simply not connected. RDBK.CLK is located in the lower right chip corner.

Violating the Maximum High and Low Time Specication for the Readback Clock
The readback clock has a maximum High and Low time specication. In some cases, this specication cannot be met. For example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. This necessitates stopping the clock, and thus violating the specication. The specication is mandatory only on clocking data at the end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the source of the maximum High and Low time requirements. Therefore, the specication only applies to the six clock cycles prior to and including any start bit, including the clocks before the rst start bit in the readback data stream. At other times, the frame data is already in the register and the register is not dynamic. Thus, it can be shifted out just like a regular shift register. The user must precisely calculate the location of the readback data relative to the frame. The system must keep track of the position within a data frame, and disable interrupts before frame boundaries. Frame lengths and data formats are listed in Table 13 and Table 14.

Readback Options
Readback options are: Readback Capture, Readback Abort, and Clock Select. They are set with the bitstream generation software. Readback Capture When the Readback Capture option is selected, the readback data stream includes sampled values of CLB and IOB signals. The rising edge of RDBK.TRIG latches the inverted values of the four CLB outputs, the IOB output ipops and the input signals I1 and I2. Note that while the bits describing conguration (interconnect, function generators, and RAM content) are not inverted, the CLB and IOB output signals are inverted. When the Readback Capture option is not selected, the values of the capture bits reect the conguration data originally written to those memory locations. If the RAM capability of the CLBs is used, RAM data are available in readback, since they directly overwrite the F and G function-table conguration of the CLB. RDBK.TRIG is located in the lower-left corner of the device.

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Readback with the XChecker Cable

The XChecker Universal Download/Readback Cable and Logic Probe uses the readback feature for bitstream verication. It can also display selected internal signals on the PC or workstation screen, functioning as a low-cost in-circuit emulator.

not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. The following guidelines reect worst-case values over the recommended operating conditions.

Spartan Program Readback Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are

Finished Internal Net

rdbk.TRIG 1 TRTRC rdclk.I 4 TRCL TRCH 5 TRCRT 2 1 TRTRC TRCRT 2

rdbk.RIP TRCRR 6

rdbk.DATA

DUMMY TRCRD 7

DUMMY

VALID

VALID X1790

Spartan and Spartan-XL Description rdbk.TRIG rdbk.TRIG setup to initiate and abort Readback rdbk.TRIG hold to initiate and abort Readback rdclk.1 rdbk.DATA delay rdbk.RIP delay High time Low time
Note 1: Note 2:

1 2 7 6 5 4

Symbol TRTRC TRCRT TRCRD TRCRR TRCH TRCL

Min 200 50 250 250

Max 250 250 500 500

Units ns ns ns ns ns ns

Timing parameters apply to all speed grades. If rdbk.TRIG is High prior to Finished, Finished will trigger the rst Readback.

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Spartan and Spartan-XL Families Field Programmable Gate Arrays

Spartan Detailed Specications

Denition of Terms
In the following tables, some specications may be designated as Advance or Preliminary. These terms are dened as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production. Specications not identied as either Advance or Preliminary are to be considered Final.1

Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked:

All specications subject to change without notice.

Spartan Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL TJ Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Plastic packages Description Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 Units V V V C C C

Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Spartan Recommended Operating Conditions

Symbol VCC VIH VIL TIN Description Supply voltage relative to GND, TJ = -0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C High-level input voltage Low-level input voltage Input signal transition time Commercial Industrial TTL inputs CMOS inputs TTL inputs CMOS inputs Min 4.75 4.5 2.0 70% 0 0 Max 5.25 5.5 VCC 100% 0.8 20% 250 Units V V V VCC V VCC ns

Note 1: At junction temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35% per C. Input and output Measurement thresholds are: 1.5 V for TTL and 2.5 V for CMOS.

1. Notwithstanding the denition of the above terms, all specications are subject to change without notice.

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Spartan DC Characteristics Over Operating Conditions

Symbol VOH VOL ICCO IL CIN IRPU IRPD Description High-level output voltage @ IOH = -4.0mA, VCC min High-level output voltage @ IOH = -1.0mA, VCC min Low-level output voltage @ IOL = 12.0mA, VCC min (Note 1) Quiescent FPGA supply current (Note 2) TTL outputs CMOS outputs TTL outputs CMOS outputs Commercial Industrial Min 2.4 VCC-0.5 Max Units V V V V mA mA A pF mA mA

Input or output leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested) Pad pull-down (when selected) @ VIN = 5 V (sample tested)

-10 0.02 0.02

0.4 0.4 3.0 6.0 +10 10 0.25

Note 1: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. Note 2: With no output current loads, no active input pull-up resistors, all package pins at Vcc or GND, and the FPGA congured with a Tie option.

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Spartan Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade Description From pad through Primary buffer, to any clock K Symbol TPG Device XCS05 XCS10 XCS20 XCS30 XCS40 XCS05 XCS10 XCS20 XCS30 XCS40 -3 Max 4.0 4.3 5.4 5.8 6.4 4.4 4.7 5.8 6.2 6.7 Preliminary Advance -4 Max Units ns ns ns ns ns ns ns ns ns ns

From pad through Secondary buffer, to any clock K

TSG

Spartan Horizontal Longline Switching Characteristic Guidelines

Testing of switching parameters modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed date, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System. and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan devices unless otherwise noted. The following guidelines reect worst-case values over the recommended operating conditions. Speed Grade Description TBUF driving a Horizontal Longline (LL): I going High or Low to LL going High or Low, while T is TIO1 low. Buffer is constantly active. (Note 1) T going Low to LL going from floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. (Note 1) TON XCS05 XCS10 XCS20 XCS30 XCS40 XCS05 XCS10 XCS20 XCS30 XCS40 3.4 4.0 5.1 5.7 7.3 3.9 5.7 6.2 7.0 7.1 Preliminary Advance ns ns ns ns ns ns ns ns ns ns Symbol Device -3 Max -4 Max Units

Note 1: These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.

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Spartan CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan devices and expressed in nanoseconds unless otherwise noted.
Description Clocks Clock High time Clock Low time Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via SR/H0 via H to X/Y outputs C inputs via H1 via H to X/Y outputs C inputs via DIN/H2 via H to X/Y outputs CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Sequential Delays Clock K to Flip-Flop outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) Hold Time after Clock K F/G inputs F/G inputs via H C inputs via SR/H0 through H C inputs via H1 through H C inputs via DIN/H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Global Set/Reset Speed Grade Symbol TCH TCL TILO TIHO TITO THH0O THH1O THH2O TOPCY TASCY TINCY TSUM TBYP TCKO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR TRPW TRIO TMRW TMRQ FTOG 2.4 3.9 3.5 3.3 3.7 2.0 2.6 4.0 0 0 0 0 0 0 0 0 4.0 4.0 11.5 17.4 125 Preliminary MHz Advance -3 Min 4.0 4.0 1.6 2.7 2.4 2.2 2.2 2.6 2.1 3.7 1.4 2.6 0.6 2.8 Max Min -4 Max Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Minimum GSR Pulse Width Delay from GSR net to any Q (Note 1)
Toggle Frequency (MHz) (for export control purposes)

Note 1: Timing is based on the XCS10. For other devices see the static timing analyzer.

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Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan devices and are expressed in nanoseconds unless otherwise noted.

Single Port RAM

Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K Read Operation (Note 2) Address read cycle time Data Valid after address change (no Write Enable) Address setup time before clock K (Clocking data into flip-flop)

Speed Grade Size Symbol Min

-3 Max Min

-4 Units Max

16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1

TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS

11.6 11.6 5.8 5.8 2.0 2.0 0 0 2.7 1.7 0 0 1.6 1.6 0 0 7.9 9.3

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

16x2 32x1 16x2 32x1 16x2 32x1

TRC TRCT TILO TIHO TICK TIHCK

2.6 3.8 1.6 2.7 2.4 3.9 Preliminary Advance

ns ns ns ns ns ns

Note 1: Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing. Note 2: Read Operation timing for 16 x 1 dual port RAM option is identical to 16 x 2 RAM timing

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Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (continued)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan devices and are expressed in nanoseconds unless otherwise noted.

Dual Port RAM

Speed Grade Size Symbol Min

-3 Max Min

-4 Units Max

Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1

TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS

11.6 5.8 2.1 0 1.6 0 1.6 0 7.0 Preliminary Advance

ns ns ns ns ns ns ns ns ns

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Spartan CLB RAM Synchronous (Edge-Triggered) Write Timing

TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

TILO

TWOS OLD

DATA OUT

NEW
X6461

Spartan CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing

TWPDS WCLK (K) TWSDS WE TDSDS DATA IN TASDS ADDRESS TILO TWODS DATA OUT OLD NEW
X6474

TWHDS

TDHDS

TAHDS

TILO

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Spartan Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. Values apply to all Spartan devices unless otherwise noted. Speed Grade Symbol Device XCS05 TICKOF
. . . . .
X3202

Description Global Clock to Output (fast) using OFF

TPG Global Clock-to-Output Delay OFF

-3
8.7 9.1 9.3 9.4 10.2

-4

Units
ns ns ns ns

(Max)

XCS10 XCS20 XCS30 XCS40

Global Clock to Output (slew-limited) using OFF

TPG Global Clock-to-Output Delay OFF

TICKO
. . . . .
X3202

(Max)

XCS05 XCS10 XCS20 XCS30 XCS40

11.5 12.0 12.2 12.8 12.8

ns ns ns ns

Input Setup Time, using Global Clock and IFF (no delay)
D Input Set - Up & Hold Time IFF TPG

TPSUF

(Min)

XCS05 XCS10 XCS20 XCS30 XCS40

2.3 1.2 0.2 0 0

ns ns ns ns

X3201

Input Hold Time, using Global Clock and IFF (no delay)
D Input Set - Up & Hold Time IFF TPG

TPHF

(Min)

XCS05 XCS10 XCS20 XCS30 XCS40

4.0 4.5 5.5 5.5 5.7

ns ns ns ns

X3201

Input Setup Time, using Global Clock and IFF (with delay)
D Input Set - Up & Hold Time IFF TPG

TPSU

(Min)

XCS05 XCS10 XCS20 XCS30 XCS40

6.0 6.0 6.0 6.0 6.8

ns ns ns ns

X3201

Input Hold Time, using Global Clock and IFF (with delay)
D Input Set - Up & Hold Time IFF TPG

TPH

(Min)

XCS05 XCS10 XCS20 XCS30 XCS40

0 0 0 0 0

ns ns ns ns

X3201

OFF = Output Flip-Flop

IFF = Input Flip-Flop/Latch

Preliminary

Advance

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Spartan IOB Input Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Description Clocks Clock Enable (EC) to Clock (IK), no delay Clock Enable (EC) to Clock (IK), with delay (Note 1) Setup Times (TTL Inputs) Pad to Clock (IK), no delay Pad to clock (IK), with delay (Note 1) Setup Times (CMOS Inputs) Pad to Clock (IK), no delay Pad to Clock (IK), with delay (Note 1) Hold Times Clock Enable (EC) to Clock (IK), no delay All Other Hold Times Propagation Delays (TTL Inputs) Pad to I1, I2 Pad to I1, I2, via transparent input latch, no delay Pad to I1, I2 via transparent input latch, with delay (Note 1) Propagation Delays (CMOS Inputs) Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent input latch, with delay (Note1) Propagation Delays Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) Global Set/Reset (Note 1) Minimum GSR Pulse Width Delay from GSR net through Q to I1, I2 Speed Grade Symbol TECIK TECIKD TPICK TPICKD TPICKC TPICKDC TIKEC -3 Min 2.1 5.6 2.0 6.1 2.4 8.0 0.9 0 2.0 3.6 7.4 Max Min -4 Max Units

ns ns ns ns ns ns
ns

ns ns ns ns

TPID TPLI TPDLI

IPIDC TPLIC TPDLIC

3.7 6.2 11.9

ns ns ns

TIKRI TIKLI TMRW TRRI 11.5

2.8 3.9

ns ns ns ns Advance

6.8 Preliminary

Note 1: Timing is based on the XCS10. For other devices see the static timing analyzer. Note 2: Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Note 3: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.

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Spartan IOB Output Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values are expressed in nanoseconds unless otherwise noted. -3 Description Clocks Clock High Clock Low Propagation Delays (TTL Output Levels) Clock (OK) to Pad, fast Clock (OK) to Pad, slew-rate limited Output (O) to Pad, fast Output (O) to Pad, slew-rate limited 3-state to Pad hi-Z (slew-rate independent) 3-state to Pad active and valid, fast 3-state to Pad active and valid, slew-rate limited Propagation Delays (CMOS Output Levels) Clock (OK) to Pad, fast Clock (OK) to Pad, slew-rate limited Output (O) to Pad, fast Output (O) to Pad, slew-rate limited 3-state to Pad hi-Z (slew-rate independent) 3-state to Pad active and valid, fast 3-state to Pad active and valid, slew-rate limited Setup and Hold Times Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup time Clock Enable (EC) to clock (OK) hold time Global Set/Reset Minimum GSR pulse width Delay from GSR Net to Pad TMRW TRPO 11.5 8.7 Preliminary Advance ns ns TOOK TOKO TECOK TOKEC 3.8 0 2.7 0.5 ns ns ns ns TOKPOFC TOPOSC TOPFC TOPSC TTSHZC TTSONFC TTSONSC 7.0 10.4 8.7 12.1 3.9 6.8 10.2 ns ns ns ns ns ns ns TOKPOF TOKPOS TOPF TOPS TTSHZ TTSONF TTSONS 4.5 7.0 4.8 7.3 3.8 7.3 9.8 ns ns ns ns ns ns ns TCH TCL 4.0 4.0 ns ns Symbol Min Max Min -4 Max Units

Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output rise/ fall times are approximately two times longer than fast output rise/fall times. Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.

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Spartan-XL Detailed Specication

Denition of Terms
In the following tables, some specications may be designated as Advance or Preliminary. These terms are dened as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specications not identied as either Advance or Preliminary are to be considered Final. All specications subject to change without notice.

Spartan-XL Absolute Maximum Ratings

Symbol VCC VIN VTS VCCt TSTG TSOL TJ Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Longest Supply Voltage Rise Time from 1V to 3V Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Plastic packages Description Value -0.5 to 4.0 -0.5 to 5.5 -0.5 to 5.5 50 -65 to +150 +260 +125 Units V V V ms C C C

Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Spartan-XL Recommended Operating Conditions

Symbol VCC VIH VIL TIN Description Supply voltage relative to GND, TJ = 0C to +85C Commercial Supply voltage relative to GND, TJ = -40C to +100C High-level input voltage Low-level input voltage Input signal transition time Industrial Min 3.0 3.0 50% of VCC 0 Max 3.6 3.6 5.5 30% of VCC 250 Units V V V V ns

Notes: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Input and output measurement threshold is ~40% of VCC.

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Spartan-XL DC Characteristics Over Recommended Operating Conditions

Symbol VOH VOL VDR ICCO IL CIN IRPU IRPD
Note 1: Note 2:

Description High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL) High-level output voltage @ IOH = -500 A, (LVCMOS) Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1) Low-level output voltage @ IOL = 1500 A, (LVCMOS) Data Retention Supply Voltage (below which conguration data may be lost) Quiescent FPGA supply current (Note 2) Input or output leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ Vin = 0V (sample tested) Pad pull-down (when selected) @ Vin = 3.3V (sample tested)

Min 2.4 90% VCC

Max

Units V V

0.4 10% VCC 2.5 5 -10 +10 10 0.02 0.02 0.25

V V V mA A pF mA mA

With up to 64 pins simultaneously sinking 12 mA. With no output current loads, no active input pull-up resistors, all package pins at Vcc or GND, and the FPGA congured with the Tie option.

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Spartan and Spartan-XL Families Field Programmable Gate Arrays

Spartan-XL Guaranteed Input and Output Parameters (Pin-to-Pin)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all Spartan-XL devices unless otherwise noted. Speed Grade Symbol Device XCS05XL TICKOF
XCS10XL XCS20XL XCS30XL XCS40XL

Description Global Clock to Output (fast) using OFF

TPG Global Clock-to-Output Delay OFF

-3
8.7 9.1 9.3 9.4 10.2

-4

Units
ns ns ns ns ns

. . . . .
X3202

(Max)

Global Clock to Output (slew-limited) using OFF

TPG Global Clock-to-Output Delay OFF

TICKO

. . . . .
X3202

(Max)

XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

11.5 12.0 12.2 12.8 12.8

ns ns ns ns ns

Input Setup Time, using IFF (no delay)

D Input Set - Up & Hold Time IFF TPG

TPSUF

(Min)

XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

2.3 1.2 0.2 0 0

ns ns ns ns ns

X3201

Input Hold Time, using IFF (no delay)

D Input Set - Up & Hold Time IFF TPG

TPHF

(Min)

XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

4.0 4.5 5.5 5.5 5.7

ns ns ns ns ns

X3201

Input Setup Time, using IFF (with delay)

D Input Set - Up & Hold Time IFF TPG

TPSU

(Min)

XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

6.0 6.0 6.0 6.0 6.8

ns ns ns ns ns

X3201

Input Hold Time, using IFF (with delay)

D Input Set - Up & Hold Time IFF TPG

TPH

(Min)

XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

0 0 0 0 0

ns ns ns ns ns

X3201

OFF = Output Flip-Flop

IFF = Input Flip-Flop/Latch

Advance

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Spartan and Spartan-XL Families Field Programmable Gate Arrays

February 13, 1998 (Version 1.0)

Pin Descriptions
There are three types of pins in the Spartan Series devices: Permanently dedicated pins User I/O pins that can have special functions Unrestricted user-programmable I/O pins.

unused it is congured as an input with the I/O pull-up resistor network remaining activated. Any user I/O can be congured to drive the Global Set/ Reset net GSR or the global three-state net, GTS. See Global Signals: GSR and GTS on page 4-205 for more information. Device pins for Spartan Series devices are described in Table 15.

Before and during conguration, all outputs not used for the conguration process are 3-stated with the I/O pull-up resistor network activated. After conguration, if an IOB is Table 15: Pin Descriptions I/O I/O During After Pin Name Cong. Cong. Permanently Dedicated Pins VCC X X

Pin Description

Eight or more (depending on package) connections to the nominal +5 V supply voltage (+3.3 V for Spartan-XL devices). All must be connected, and each must be decoupled with a 0.01 - 0.1 F capacitor to Ground. Eight or more (depending on package type) connections to Ground. All must be conGND X X nected. During configuration, Configuration Clock (CCLK) is an output in Master mode and is an input in Slave mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the Readback Clock. There is no CCLK High or Low time restriction on CCLK I or O I Spartan Series devices, except during Readback. See Violating the Maximum High and Low Time Specification for the Readback Clock on page 4-214 for an explanation of this exception. DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a Low level on DONE DONE I/O O can be configured to delay the global logic initialization and the enabling of outputs. The optional pull-up resistor is selected as an option in the program that creates the configuration bitstream. The resistor is included by default. PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA finishes the current clear cycle and executes another complete clear cycle, before it PROGRAM I I goes into a WAIT state and releases INIT. The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled up to Vcc. The Mode input is sampled after INIT goes High to determine the configuration mode to be used. MODE I X During configuration, this pin has a weak pull-up resistor. For the most popular configuration mode, Slave Serial, the mode pin can be left unconnected. For Master Serial mode, connect the pin directly to system ground. Pins reserved for factory testing and possible future enhancements. Pins must be left Dont Connect X X floating. User I/O Pins That Can Have Special Functions If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used, this pin is a 3-state output without a register, after configuration is completed. TDO O O To use this pin, place the library component TDO instead of the usual pad symbol. An output buffer must still be used.

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Spartan and Spartan-XL Families Field Programmable Gate Arrays

Table 15: Pin Descriptions (Continued) I/O I/O During After Cong. Cong.

Pin Description If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. I/O TDI, TCK, If the BSCAN symbol is not placed in the design, all boundary scan functions are inhibI or I TMS ited once configuration is completed, and these pins become user-programmable I/O. (JTAG) In this case, they must be called out by special library elements. To use these pins, place the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used. High During Configuration (HDC) is driven High until the I/O go active. It is available as HDC O I/O a control output indicating that configuration is not yet completed. After configuration, HDC is a user-programmable I/O pin. Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a control output indicating that configuration is not yet completed. After configuration, LDC O I/O LDC is a user-programmable I/O pin. Before and during configuration, INIT is a bidirectional signal. A 1 k - 10 k external pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used INIT I/O I/O to hold the FPGA in the internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an additional 30 to 300 s after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O go active, INIT is a user-programmable I/O pin. Four Primary Global inputs each drive a dedicated internal global net with short delay and minimal skew. If not used to drive a global buffer, any of these pins is a user-proPGCK1 Weak grammable I/O. I or I/O PGCK4 Pull-up The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol connected directly to the input of a BUFGP symbol is automatically placed on one of these pins. Four Secondary Global inputs each drive a dedicated internal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If SGCK1 Weak not used to drive a global net, any of these pins is a user-programmable I/O pin. I or I/O SGCK4 Pull-up The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol is automatically placed on one of these pins. During configuration, DIN is the serial configuration data input receiving data on the risDIN I I/O ing edge of CCLK. After configuration, DIN is a user-programmable I/O pin. During configuration, DOUT is the serial configuration data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, oneDOUT O I/O and-a-half CCLK periods after it was received at the DIN input. After configuration, DOUT is a user-programmable I/O pin. Unrestricted User-Programmable I/O Pins These pins can be configured to be input and/or output after configuration is completed. Weak I/O I/O Before configuration is completed, these pins have an internal high-value pull-up resisPull-up tor network that defines the logic level as High.

Pin Name

4-230

February 13, 1998 (Version 1.0)

Device-Specic Pinout Tables

Device-specic tables include all packages for each Spartan and Spartan-XL device. They follow the pad locations around the die, and include boundary scan register locations.

Pin Locations for XCS05 & XCS05XL Devices

XCS05 & XCS05XL Pad Name VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK1 VCC GND I/O, PGCK1 I/O I/O, TDI I/O, TCK I/O, TMS I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 Dont Connect GND MODE VCC Dont Connect I/O, PGCK2 I/O (HDC) I/O I/O (LDC) I/O I/O I/O I/O I/O I/O (INIT) VCC PC84 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 VQ100 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 Bndry Scan 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 83 86 89 92 95 98 104 107 110 113 116 119 122 125 126 127 130 133 136 139 142 145 148 151 154 XCS05 & XCS05XL Pad Name GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O I/O, PGCK3 I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O (DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O I/O, PGCK4 I/O I/O I/O I/O I/O I/O I/O PC84 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 VQ100 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 Bndry Scan 157 160 163 166 169 172 175 178 181 184 187 190 193 196 199 202 205 208 211 214 217 220 223 229 232 235 238 241 244 0 2 5 8 11 14 17 20 23 26

February 13, 1998 (Version 1.0)

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Spartan and Spartan-XL Families Field Programmable Gate Arrays

XCS05 & XCS05XL Pad Name I/O GND
9/24/97

PC84 P84 P1

VQ100 P87 P88

Bndry Scan 29 -

Pin Locations for XCS10 & XCS10XL Devices

XCS10 & XCS10XL Pad Name PC84 VQ100 TQ144 Bndry Scan XCS10 & XCS10XL Pad Name PC84 VQ100 TQ144 Bndry Scan

VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK1 VCC GND I/O, PGCK1 I/O I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O

P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 -

P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 -

P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161

I/O I/O, SGCK2 Dont Connect GND MODE VCC Dont Connect I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O I/O, PGCK3 I/O I/O I/O

P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58

P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55

P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79

164 167 170 173 174 175 178 181 184 187 190 193 196 199 202 205 208 211 214 217 220 223 226 229 232 235 238 241 244 247 250 253 256 259 262 265 268 271

4-232

February 13, 1998 (Version 1.0)

XCS10 & XCS10XL Pad Name

PC84

VQ100

TQ144

Bndry Scan

XCS10 & XCS10XL Pad Name

PC84

VQ100

TQ144

Bndry Scan

I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (DIN) I/O, SGCK4 (DOUT)

P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72

P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73

P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106

274 277 280 283 286 289 292 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337 340

CCLK VCC O, TDO GND I/O I/O, PGCK4 I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND
9/24/97

P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P1

P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88

P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127

0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 -

Additional XCS10/XL Package Pins

TQ144 P117
5/5/97

Not Connected Pins -

Pin Locations for XCS20 & XCS20XL Devices

XCS20 & XCS20XL Pad Name VQ100 TQ144 PQ208 Bndry Scan XCS20 & XCS20XL Pad Name VQ100 TQ144 PQ208 Bndry Scan

VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK1

P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99

P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143

P183 P184 P185 P186 P187 P188 P189 P190 P191 P193 P194 P195 P196 P197 P198 P199 P200 P201 P204 P205 P206 P207

62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119

VCC GND I/O, PGCK1 I/O I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O

P100 P1 P2 P3 P4 P5 P6 P7 P8 P9

P144 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15

P208 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P13 P14 P15 P16 P17 P19 P20 P21 P22 P23

122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176

February 13, 1998 (Version 1.0)

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Spartan and Spartan-XL Families Field Programmable Gate Arrays

XCS20 & XCS20XL Pad Name Bndry Scan XCS20 & XCS20XL Pad Name Bndry Scan

VQ100

TQ144

PQ208

VQ100

TQ144

PQ208

I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 Dont Connect GND MODE VCC Dont Connect I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O

P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42

P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59

P24 P25 P26 P27 P28 P29 P30 P31 P32 P34 P35 P36 P37 P38 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P66 P67 P68 P69 P70 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83

179 182 185 188 191 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 246 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 316

I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O I/O, PGCK3 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O

P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 -

P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 -

P84 P85 P87 P88 P89 P90 P91 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P112 P113 P114 P115 P116 P117 P118 P119 P120 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P141 P142 P143 P145

319 322 325 328 331 334 337 340 343 346 349 352 355 358 361 364 367 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457

4-234

February 13, 1998 (Version 1.0)

XCS20 & XCS20XL Pad Name

VQ100

TQ144

PQ208

Bndry Scan

XCS20 & XCS20XL Pad Name

VQ100

TQ144

PQ208

Bndry Scan

I/O I/O I/O I/O I/O I/O I/O I/O (DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O I/O, PGCK4 I/O I/O I/O I/O I/O I/O I/O

P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 -

P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 -

P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P166 P167 P168

460 463 466 469 472 475 478 481 484 0 2 5 8 11 14 17 20 23 26

I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
2/5/98

P82 P83 P84 P85 P86 P87 P88

P118 P119 P120 P121 P122 P123 P124 P125 P126 P127

P169 P170 P171 P172 P174 P175 P176 P177 P178 P179 P180 P181 P182

29 32 35 38 41 44 47 50 53 56 59 -

Additional XCS20/XL Package Pins

PQ208 P12 P86 P165
2/5/98

P18 P92 P173

Not Connected Pins P33 P39 P111 P121 P192 P202

P65 P140 P203

P71 P144 -

Pin Locations for XCS30 & XCS30XL Devices

XCS30 & XCS30XL Pad Name VQ100 TQ144 PQ208 PQ240 BG256 Bndry Scan XCS30 & XCS30XL Pad Name VQ100 TQ144 PQ208 PQ240 BG256 Bndry Scan

VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK1

P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99

P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143

P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P206 P207

P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239

VCC* C10 D10 A9 B9 C9 D9 A8 B8 VCC* A6 C7 B6 A5 GND* C6 B5 A4 C5 B4 A3 D5 C4 B3 B2 A2 C3

74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143

VCC GND I/O, PGCK1 I/O I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O I/O

P100 P1 P2 P3 P4 P5 P6 P7 P8 P9

P144 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15

P208 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23

P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27

VCC* GND* B1 C2 D2 D3 E4 C1 D1 E3 E2 E1 F3 F2 GND* G3 G2 G1 H3 VCC* H2 H1 J2 J1 K2 K3 K1

146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203 206 209 212

February 13, 1998 (Version 1.0)

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XCS30 & XCS30XL Pad Name Bndry Scan XCS30 & XCS30XL Pad Name Bndry Scan

VQ100

TQ144

PQ208

PQ240

BG256

VQ100

TQ144

PQ208

PQ240

BG256

I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 Dont Connect GND MODE VCC Dont Connect I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O

P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 -

P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 -

P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 -

P28 P29 P30 P31 P32 P33 P34 P35 P36 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85

L1 GND* VCC* L2 L3 L4 M1 M2 M3 N1 N2 VCC* P1 P2 R1 P3 GND* T1 R3 T2 U1 T3 U2 V1 T4 U3 V2 W1 V3 W2 GND* Y1 VCC* W3 Y2 W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 W6 Y6 GND* W7 Y7 V8 W8 VCC* Y8 U9 Y9 W10

215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287 290 293 294 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 346 349 352

I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O I/O, PGCK3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O

P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58

P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85

P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123

P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142

V10 Y10 Y11 W11 VCC* GND* V11 U11 Y12 W12 V12 U12 V13 Y14 VCC* Y15 V14 W15 Y16 GND* V15 W16 Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19 GND* Y20 VCC* V19 U19 U18 T17 V20 U20 T18 T19 T20 R18 R19 R20 P18 GND* P20 N18 N19 N20 VCC* M17 M18

355 358 361 364 367 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484 487 490

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XCS30 & XCS30XL Pad Name

VQ100

TQ144

PQ208

PQ240

BG256

Bndry Scan

XCS30 & XCS30XL Pad Name

VQ100

TQ144

PQ208

PQ240

BG256

Bndry Scan

I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O I/O, PGCK4 I/O I/O I/O I/O I/O

P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 -

P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 -

P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165

P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189

M20 L19 L18 L20 K20 K19 VCC* GND* K18 K17 J20 J19 J18 J17 H19 H18 VCC* G19 F20 G18 F19 GND* F18 E19 D20 E18 D19 C20 E17 D18 C19 B20 C18 B19 A20 VCC* A19 GND* B18 B17 C17 D16 A18 A17 C16

493 496 499 502 505 508 511 514 517 520 523 526 529 532 535 538 541 544 547 550 553 556 559 562 565 568 571 574 577 580 0 2 5 8 11 14 17 20

I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O GND
1/30/98

P82 P83 P84 P85 P86 P87 P88

P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127

P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182

P190 P191 P192 P193 P194 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211

B16 A16 C15 B15 A15 GND* B14 A14 C13 B13 VCC* C12 B12 A12 B11 C11 A11 A10 B10 GND*

23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 -

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package.

Additional XCS30/XL Package Pins

PQ240 P22 P204 P195
2/12/98

P37 P219 -

GND Pins P83 P98 Not Connected Pins -

P143 -

P158 -

BG256 C14 E20 K4 R4 U15 A1 G20 U4 A7 J4 Y13

6/4/97

D6 F1 L17 R17 V7 B7 H4 U8 A13 M4 -

VCC Pins D7 D11 F4 F17 P4 P17 U6 U7 W20 GND Pins D4 D8 H17 N3 U13 U17 Not Connected Pins C8 D12 M19 V9 -

D14 G4 P19 U10 D13 N4 W14 H20 W9 -

D15 G17 R2 U14 D17 N17 J3 W13 -

Pin Locations for XCS40 & XCS40XL Devices

XCS40 & XCS40XL Pad Name PQ208 PQ240 BG256 Bndry Scan XCS40 & XCS40XL Pad Name PQ208 PQ240 BG256 Bndry Scan

VCC I/O I/O I/O

P183 P184 P185 P186

P212 P213 P214 P215

VCC* C10 D10 A9

86 89 92

I/O I/O I/O I/O

P187 P188 P189 P190

P216 P217 P218 P220

B9 C9 D9 A8

95 98 101 104

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Spartan and Spartan-XL Families Field Programmable Gate Arrays

XCS40 & XCS40XL Pad Name Bndry Scan XCS40 & XCS40XL Pad Name Bndry Scan

PQ208

PQ240

BG256

PQ208

PQ240

BG256

I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK1 VCC GND I/O, PGCK1 I/O I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O

P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P206 P207 P208 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29

P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33

B8 C8 A7 VCC* A6 C7 B6 A5 GND* C6 B5 A4 C5 B4 A3 D5 C4 B3 B2 A2 C3 VCC* GND* B1 C2 D2 D3 E4 C1 D1 E3 E2 E1 F3 F2 GND* G3 G2 G1 H3 VCC* H2 H1 J4 J3 J2 J1 K2 K3 K1 L1 GND* VCC* L2 L3 L4

107 110 113 116 119 122 125 128 131 134 137 140 143 152 155 158 161 164 167 170 173 176 179 182 185 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260

I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 Dont Connect GND MODE VCC Dont Connect I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O

P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76

P34 P35 P36 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85 P86 P87 P88

M1 M2 M3 M4 N1 N2 VCC* P1 P2 R1 P3 GND* T1 R3 T2 U1 T3 U2 V1 T4 U3 V2 W1 V3 W2 GND* Y1 VCC* W3 Y2 W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 W6 Y6 GND* W7 Y7 V8 W8 VCC* Y8 U9 V9 W9 Y9 W10 V10 Y10 Y11

263 266 269 272 278 281 284 287 290 293 296 299 302 305 308 311 320 323 326 329 332 335 338 341 342 343 346 349 352 355 358 367 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421

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XCS40 & XCS40XL Pad Name

PQ208

PQ240

BG256

Bndry Scan

XCS40 & XCS40XL Pad Name

PQ208

PQ240

BG256

Bndry Scan

I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O I/O, PGCK3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O

P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 -

P89 P90 P91 P92 P93 P94 P95 P96 P97 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 -

W11 VCC* GND* V11 U11 Y12 W12 V12 U12 Y13 W13 V13 Y14 VCC* Y15 V14 W15 Y16 GND* V15 W16 Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19 GND* Y20 VCC* V19 U19 U18 T17 V20 U20 T18 T19 T20 R18 R19 R20 P18 GND* P20 N18 N19 N20 VCC* M17 M18 M19

424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484 493 496 499 502 505 508 511 514 517 520 523 526 535 538 541 544 547 550 553 556 559 562 565 568 574

I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O I/O, PGCK4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O

P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 -

P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P196 P197 P198 P199

M20 L19 L18 L20 K20 K19 VCC* GND* K18 K17 J20 J19 J18 J17 H20 H19 H18 VCC* G19 F20 G18 F19 GND* F18 E19 D20 E18 D19 C20 E17 D18 C19 B20 C18 B19 A20 VCC* A19 GND* B18 B17 C17 D16 A18 A17 C16 B16 A16 C15 B15 A15 GND* B14 A14 C13

577 580 583 586 589 592 595 598 601 604 607 610 613 619 622 625 628 631 634 637 640 643 646 649 652 655 658 667 670 673 676 0 2 5 8 11 14 17 26 29 32 35 38 41 44 47 50

February 13, 1998 (Version 1.0)

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Spartan and Spartan-XL Families Field Programmable Gate Arrays

XCS40 & XCS40XL Pad Name Bndry Scan

PQ208

PQ240

BG256

Additional XCS40/XL Package Pins

PQ240 P22 P204 P195
2/12/98

I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
10/23/97

P173 P174 P175 P176 P177 P178 P179 P180 P181 P182

P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211

B13 VCC* A13 D12 C12 B12 A12 B11 C11 A11 A10 B10 GND*

53 56 59 62 65 68 71 74 77 80 83 -

P37 P219 -

GND Pins P83 P98 Not Connected Pins -

P143 -

P158 -

BG256 C14 E20 K4 R4 U15 A1 G20 U4

6/17/97

D6 F1 L17 R17 V7 B7 H4 U8

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package.

VCC Pins D7 D11 F4 F17 P4 P17 U6 U7 W20 GND Pins D4 D8 H17 N3 U13 U17

D14 G4 P19 U10 D13 N4 W14

D15 G17 R2 U14 D17 N17 -

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Spartan and Spartan-XL Families Field Programmable Gate Arrays

February 13, 1998 (Version 1.0)

Product Availability
Table 16 shows the packages and speed grades for Spartan Series devices. Table 17 shows the number of user IOs avalable for each device/package combination. Table 16: Component Availability Chart for Spartan Series FPGAs PINS 84 TYPE Plast. PLCC CODE PC84 -3 C -4 (C) -3 C -4 (C) -3 -4 -3 -4 -3 -4 -3 (C) -4 (C) -3 (C) -4 (C) -3 -4 -3 -4 -3 -4 100 Plast. VQFP VQ100 C (C) C (C) C (C) C (C) 144 Plast. TQFP TQ144 208 Plast. PQFP PQ208 240 Plast. PQFP PQ240 256 Plast. BGA BG256

Device XCS05 XCS10 XCS20 XCS30 XCS40 XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
2/13/98

C (C) C (C) C (C)

C (C) C (C) C (C)

C (C) C (C)

C (C) C (C)

(C) (C) (C) (C) (C) (C) (C) (C)

(C) (C) (C) (C) (C) (C)

(C) (C) (C) (C) (C) (C)

(C) (C) (C) (C)

(C) (C) (C) (C)

C = Commercial TJ = 0 to +85C

( ) Parentheses indicate future product plans

Table 17: User I/O Chart for Spartan Series FPGAs Max I/O 80 112 160 192 224 80 112 160 192 224 Package Type TQ144 PQ208 112 113 113

Device XCS05 XCS10 XCS20 XCS30 XCS40 XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
9/24/97

PC84 61 61

VQ100 77 77 77 77 77 77 77 77

PQ240

BG256

160 169 169

192 193

192 205

61 61

112 113 113

160 169 169

192 193

192 205

February 13, 1998 (Version 1.0)

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Spartan and Spartan-XL Families Field Programmable Gate Arrays

Ordering Information

Example:
Device Type

XCS20XL-3 PQ208C
Temperature Range C = Commercial (TJ = 0 to +85oC) I = Industrial (TJ = -40 to +100oC) Number of Pins

Speed Grade -3 -4

Package Type BG = Ball Grid Array VQ = Very Thin Quad Flat Pack PC = Plastic Lead Chip Carrier TQ = Thin Quad Flat Pack PQ = Plastic Quad Flat Pack

4-242

February 13, 1998 (Version 1.0)

XC5200 Series Table of Contents

1 4*

XC5200 Series Field Programmable Gate Arrays

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Family Compared to XC4000 and XC3000 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Block (CLB) Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Block (IOB) Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaBlock: Abundant Local Routing Plus Versatile Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaRing I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Routing Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Taking Advantage of Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-Input Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carry Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cascade Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLB Flip-Flops and Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using FPGA Flip-Flops and Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optional Delay Guarantees Zero Hold Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other IOB Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaBlock Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Routing Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single- and Double-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaRing Input/Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Including Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avoiding Inadvertent Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-247 4-247 4-248 4-248 4-248 4-248 4-248 4-249 4-249 4-250 4-250 4-251 4-251 4-251 4-251 4-251 4-252 4-253 4-253 4-253 4-253 4-253 4-253 4-254 4-254 4-254 4-255 4-255 4-255 4-256 4-256 4-257 4-257 4-257 4-258 4-258 4-260 4-260 4-260 4-262 4-262 4-264 4-264 4-264 4-264 4-265 4-265 4-265

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Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Express Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting CCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Stream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Redundancy Check (CRC) for Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delaying Configuration After Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Goes High to Signal End of Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of User I/O After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of Global Reset After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Complete After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Through the Boundary Scan Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Violating the Maximum High and Low Time Specification for the Readback Clock . . . . . . . . . . Readback with the XChecker Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Parallel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Express Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave and Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Program Readback Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . XC5200 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin) . . . . . . . . . . . . . . . . . . . . . . . . XC5200 IOB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5202 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional No Connect (N.C.) Connections on TQ144 Package. . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5204 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-268 4-268 4-268 4-268 4-269 4-269 4-270 4-270 4-271 4-271 4-272 4-272 4-272 4-274 4-274 4-274 4-275 4-275 4-276 4-276 4-276 4-276 4-277 4-277 4-277 4-277 4-277 4-277 4-278 4-278 4-279 4-280 4-282 4-284 4-284 4-284 4-286 4-289 4-289 4-289 4-290 4-291 4-291 4-291 4-291 4-291 4-292 4-292 4-293 4-294 4-295 4-296 4-297 4-297 4-299 4-299

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Additional No Connect (N.C.) Connections for PQ160 Package . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5206 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional No Connect (N.C.) Connections for PQ208 and TQ176 Packages . . . . . . . . . . . . . . Pin Locations for XC5210 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional No Connect (N.C.) Connections for PQ208 and PQ240 Packages . . . . . . . . . . . . . . Pin Locations for XC5215 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional No Connect (N.C.) Connections for HQ208, HQ240, and HQ304 Packages . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Per Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-302 4-303 4-306 4-306 4-311 4-311 4-317 4-318 4-318 4-318

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XC5200 Series Field Programmable Gate Arrays

1 4*

April 8, 1998 (Version 5.0)

Product Specification Fully Supported by XACTstepTM Development System - Automatic place and route software - Wide selection of PC and Workstation platforms - Over 100 3rd-party Alliance interfaces - Supported by shrink-wrap Foundation software

Features
Low-cost, process-optimized, register/latch rich, SRAM based reprogrammable architecture - 0.5m three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 gates) - Price competitive with Gate Arrays System Level Features - System performance beyond 50 MHz - 6 levels of interconnect hierarchy - VersaRingTM I/O Interface for pin-locking - Dedicated carry logic for high-speed arithmetic functions - Cascade chain for wide input functions - Built-in IEEE 1149.1 JTAG boundary scan test circuitry on all I/O pins - Internal 3-state bussing capability - Four dedicated low-skew clock or signal distribution nets Versatile I/O and Packaging - Innovative VersaRingTM I/O interface provides a high logic cell to I/O ratio, with up to 244 I/O signals - Programmable output slew-rate control maximizes performance and reduces noise - Zero Flip-Flop hold time for input registers simplies system timing - Independent Output Enables for external bussing - Footprint compatibility in common packages within the XC5200 Series and with the XC4000 Series - Over 150 device/package combinations, including advanced BGA, TQ, and VQ packaging available

Description
The XC5200 Field-Programmable Gate Array Family is engineered to deliver the lowest cost of any FPGA family. By optimizing the new XC5200 architecture for three-layer metal (TLM) technology and a 0.5-m CMOS SRAM process, dramatic advances have been made in silicon efciency. These advances position the XC5200 family as a cost-effective, high-volume alternative to gate arrays Building on experiences gained with three previous successful SRAM FPGA families, the XC5200 family brings a robust feature set to high-density programmable logic design. The VersaBlockTM logic module, the VersaRing I/O interface, and a rich hierarchy of interconnect resources combine to enhance design exibility and reduce time-tomarket.Complete support for the XC5200 family is delivered through the familiar XACTstep software environment. The XC5200 family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, VHDL, and Verilog HDL synthesis.Designers utilizing logic synthesis can use their existing tools to design with the XC5200 devices.
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Table 2: XC5200 Field-Programmable Gate Array Family Members Device Logic Cells Max Logic Gates Typical Gate Range VersaBlock Array CLBs Flip-Flops I/Os TBUFs per Longline XC5202 256 3,000 2,000 - 3,000 8x8 64 256 84 10 XC5204 480 6,000 4,000 - 6,000 10 x 12 120 480 124 14 XC5206 784 10,000 6,000 - 10,000 14 x 14 196 784 148 16 XC5210 1,296 16,000 XC5215 1,936 23,000

10,000 - 16,000 15,000 - 23,000 18 x 18 324 1,296 196 20 22 x 22 484 1,936 244 24

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XC5200 Family Compared to XC4000 and XC3000 Series

For readers already familiar with the XC4000 and XC3000 FPGA Families, this section describes signicant differences between them and the XC5200 family. Unless otherwise indicated, comparisons refer to both XC4000 and XC3000 devices.

Table 3: Xilinx Field-Programmable Gate Array Families Parameter Function generators per CLB Logic inputs per CLB Logic outputs per CLB XC5200 XC4000 XC3000 4 20 12 4 no no yes yes yes yes yes 3 9 4 8 yes yes no yes yes yes yes 2 5 2 2 no no no no yes no yes

Congurable Logic Block (CLB) Resources

Each XC5200 CLB contains four independent 4-input function generators and four registers, which are congured as four independent Logic Cells (LCs). The registers in each XC5200 LC are optionally congurable as edge-triggered D-type ip-ops or as transparent level-sensitive latches. The XC5200 CLB includes dedicated carry logic that provides fast arithmetic carry capability. The dedicated carry logic may also be used to cascade function generators for implementing wide arithmetic functions. Low-skew global buffers User RAM Dedicated decoders Cascade chain Fast carry logic Internal 3-state drivers IEEE boundary scan Output slew-rate control

XC4000 family: XC5200 devices have no wide edge decoders. Wide decoders are implemented using cascade logic. Although sacricing speed for some designs, lack of wide edge decoders reduces the die area and hence cost of the XC5200. XC4000 family: XC5200 dedicated carry logic differs from that of the XC4000 family in that the sum is generated in an additional function generator in the adjacent column. This design reduces XC5200 die size and hence cost for many applications. Note, however, that a loadable up/down counter requires the same number of function generators in both families. XC3000 has no dedicated carry. XC4000 family: XC5200 lookup tables are optimized for cost and hence cannot implement RAM.

Routing Resources
The XC5200 family provides a exible coupling of logic and local routing resources called the VersaBlock. The XC5200 VersaBlock element includes the CLB, a Local Interconnect Matrix (LIM), and direct connects to neighboring VersaBlocks. The XC5200 provides four global buffers for clocking or high-fanout control signals. Each buffer may be sourced by means of its dedicated pad or from any internal source. Each XC5200 TBUF can drive up to two horizontal and two vertical Longlines. There are no internal pull-ups for XC5200 Longlines.

Input/Output Block (IOB) Resources

The XC5200 family maintains footprint compatibility with the XC4000 family, but not with the XC3000 family. To minimize cost and maximize the number of I/O per Logic Cell, the XC5200 I/O does not include ip-ops or latches. For high performance paths, the XC5200 family provides direct connections from each IOB to the registers in the adjacent CLB in order to emulate IOB registers. Each XC5200 I/O Pin provides a programmable delay element to control input set-up time. This element can be used to avoid potential hold-time problems.Each XC5200 I/O Pin is capable of 8-mA source and sink currents. IEEE 1149.1-type boundary scan is supported in each XC5200 I/O.

Conguration and Readback

The XC5200 supports a new conguration mode called Express mode, not available in XC4000/E or XC3000 Families.

XC4000 family: The XC5200 family provides a global reset but not a global set.
XC5200 devices use a different conguration process than that of the XC3000 family, but use the same process as the XC4000 family.

XC3000 family: Although their conguration processes differ, XC5200 devices may be used in daisy chains with XC3000 devices. XC3000 family: The XC5200 PROGRAM pin is a singlefunction input pin that overrides all other inputs. The program pin does not exist in XC3000.

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XC3000 family: XC5200 devices support an additional programming mode: Peripheral Synchronous. XC3000 family: The XC5200 family does not support Power-down, but offers a Global 3-state input that does not reset any ip-ops. XC3000 family: The XC5200 family does not provide an onchip crystal oscillator amplier, but it does provide an internal oscillator from which a variety of frequencies up to 12 MHz are available.

Input/Output Blocks (IOBs)

VersaRing GRM VersaBlock GRM VersaBlock GRM VersaBlock

VersaRing

Architectural Overview
Figure 2 presents a simplied, conceptual overview of the XC5200 architecture. Similar to conventional FPGAs, the XC5200 family consists of programmable IOBs, programmable logic blocks, and programmable interconnect. Unlike other FPGAs, however, the logic and local routing resources of the XC5200 family are combined in exible VersaBlocks (Figure 3). General-purpose routing connects to the VersaBlock through the General Routing Matrix (GRM).

GRM VersaBlock

GRM VersaBlock

GRM VersaBlock

GRM VersaBlock

GRM VersaBlock

GRM VersaBlock

VersaRing

VersaRing
X4955

Figure 2: XC5200 Architectural Overview

VersaBlock: Abundant Local Routing Plus Versatile Logic

The basic logic element in each VersaBlock structure is the Logic Cell, shown in Figure 4. Each LC contains a 4-input function generator (F), a storage device (FD), and control logic. There are ve independent inputs and three outputs to each LC. The independence of the inputs and outputs allows the software to maximize the resource utilization within each LC. Each Logic Cell also contains a direct feedthrough path that does not sacrice the use of either the function generator or the register; this feature is a rst for FPGAs. The storage device is congurable as either a D ip-op or a latch. The control logic consists of carry logic for fast implementation of arithmetic functions, which can also be congured as a cascade chain allowing decode of very wide input functions.
GRM
24 24
TS
4 4

CLB

LC3
4 4 4

LC2 LC1 LC0

4 4

LIM
4 4

Direct Connects

X5707

Figure 3: VersaBlock

CO DO DI D F4 F3 F2 F1 X CI CE CK CLR
X4956

FD F

Figure 4: XC5200 Logic Cell (Four LCs per CLB)

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XC5200 Series Field Programmable Gate Arrays

The XC5200 CLB consists of four LCs, as shown in Figure 5. Each CLB has 20 independent inputs and 12 independent outputs. The top and bottom pairs of LCs can be congured to implement 5-input functions. The challenge of FPGA implementation software has always been to maximize the usage of logic resources. The XC5200 family addresses this issue by surrounding each CLB with two types of local interconnect the Local Interconnect Matrix (LIM) and direct connects. These two interconnect resources, combined with the CLB, form the VersaBlock, represented in Figure 3.

The LIM provides 100% connectivity of the inputs and outputs of each LC in a given CLB. The benet of the LIM is that no general routing resources are required to connect feedback paths within a CLB. The LIM connects to the GRM via 24 bidirectional nodes. The direct connects allow immediate connections to neighboring CLBs, once again without using any of the general interconnect. These two layers of local routing resource improve the granularity of the architecture, effectively making the XC5200 family a sea of logic cells. Each VersaBlock has four 3-state buffers that share a common enable line and directly drive horizontal and vertical Longlines, creating robust on-chip bussing capability. The VersaBlock allows fast, local implementation of logic functions, effectively implementing user designs in a hierarchical fashion. These resources also minimize local routing congestion and improve the efciency of the general interconnect, which is used for connecting larger groups of logic. It is this combination of both ne-grain and coarse-grain architecture attributes that maximize logic utilization in the XC5200 family. This symmetrical structure takes full advantage of the third metal layer, freeing the placement software to pack user logic optimally with minimal routing restrictions.

LC3
DI

CO DO D Q

F4 F3 F2 F1

FD F
X

LC2
DO DI D F4 F3 F2 F1 X Q

VersaRing I/O Interface

The interface between the IOBs and core logic has been redesigned in the XC5200 family. The IOBs are completely decoupled from the core logic. The XC5200 IOBs contain dedicated boundary-scan logic for added board-level testability, but do not include input or output registers. This approach allows a maximum number of IOBs to be placed around the device, improving the I/O-to-gate ratio and decreasing the cost per I/O. A freeway of interconnect cells surrounding the device forms the VersaRing, which provides connections from the IOBs to the internal logic. These incremental routing resources provide abundant connections from each IOB to the nearest VersaBlock, in addition to Longline connections surrounding the device. The VersaRing eliminates the historic trade-off between high logic utilization and pin placement exibility. These incremental edge resources give users increased exibility in preassigning (i.e., locking) I/O pins before completing their logic designs. This ability accelerates time-to-market, since PCBs and other system components can be manufactured concurrent with the logic design.

FD F

LC1
DO DI D F4 F3 F2 F1 X Q

FD F

LC0
DO DI D F4 F3 F2 F1 X CI CE CK CLR
X4957

General Routing Matrix

The GRM is functionally similar to the switch matrices found in other architectures, but it is novel in its tight coupling to the logic resources contained in the VersaBlocks. Advanced simulation tools were used during the development of the XC5200 architecture to determine the optimal level of routing resources required. The XC5200 family contains six levels of interconnect hierarchy a series of single-length lines, double-length lines, and Longlines all

FD F

Figure 5: Congurable Logic Block

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routed through the GRM. The direct connects, LIM, and logic-cell feedthrough are contained within each VersaBlock. Throughout the XC5200 interconnect, an efcient multiplexing scheme, in combination with three layer metal (TLM), was used to improve the overall efciency of silicon usage.

Detailed Functional Description

Congurable Logic Blocks (CLBs)
Figure 5 shows the logic in the XC5200 CLB, which consists of four Logic Cells (LC[3:0]). Each Logic Cell consists of an independent 4-input Lookup Table (LUT), and a DType ip-op or latch with common clock, clock enable, and clear, but individually selectable clock polarity. Additional logic features provided in the CLB are: An independent 5-input LUT by combining two 4-input LUTs. High-speed carry propagate logic. High-speed pattern decoding. High-speed direct connection to ip-op D-inputs. Individual selection of either a transparent, levelsensitive latch or a D ip-op. Four 3-state buffers with a shared Output Enable.

Performance Overview
The XC5200 family has been benchmarked with many designs running synchronous clock rates beyond 66 MHz. The performance of any design depends on the circuit to be implemented, and the delay through the combinatorial and sequential logic elements, plus the delay in the interconnect routing. A rough estimate of timing can be made by assuming 3-6 ns per logic level, which includes direct-connect routing delays, depending on speed grade. More accurate estimations can be made using the information in the Switching Characteristic Guideline section.

Taking Advantage of Reconguration

FPGA devices can be recongured to change logic function while resident in the system. This capability gives the system designer a new degree of freedom not available with any other type of logic. Hardware can be changed as easily as software. Design updates or modications are easy, and can be made to products already in the eld. An FPGA can even be recongured dynamically to perform different functions at different times. Recongurable logic can be used to implement system self-diagnostics, create systems capable of being recongured for different environments or operations, or implement multi-purpose hardware for a given application. As an added benet, using recongurable FPGA devices simplies hardware design and debugging and shortens product time-to-market.

5-Input Functions
Figure 6 illustrates how the outputs from the LUTs from LC0 and LC1 can be combined with a 2:1 multiplexer (F5_MUX) to provide a 5-input function. The outputs from the LUTs of LC2 and LC3 can be similarly combined.

CO DI D FD I1 I2 I3 I4 F4 F3 F2 F1 DO Q

F
X

LC1
F5_MUX DO I5 DI D FD F4 F3 F2 F1 Q out Qout

F CI CE CK CLR

LC0
X5710

5-Input Function

Figure 6: Two LUTs in Parallel Combined to Create a 5-input Function

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XC5200 Series Field Programmable Gate Arrays

carry out A3 or B3
CO DI

DO D Q
FD

carry3
DI

CO

DO

D
F4 F3 F2 F1

Q
FD

A3 and B3 to any two

F4 F3 F2 F1

CY_MUX
XOR

XOR X sum3

X half sum3

LC3
A2 or B2
DI

LC3
DI DO

DO carry2 D Q
FD

D
F4 F3 F2 F1

Q
FD

A2 and B2 to any two

F4 F3 F2 F1

CY_MUX

XOR

half sum2

XOR X

sum2

LC2
A1 or B1
DI

LC2
DI DO

DO carry1 D Q
FD

D
F4 F3 F2 F1

Q
FD

A1 and B1 to any two

F4 F3 F2 F1

CY_MUX
XOR

half sum1

XOR X

sum1

LC1
A0 or B0 DI

LC1
carry0
DI DO

DO D Q
FD

D
F4 F3 F2 F1

Q
FD

A0 and B0 to any two

F4 F3 F2 F1

CY_MUX
XOR

X CI CE CK CLR

half sum0

XOR X CI CE CK CLR

sum0

LC0

LC0

carry in

CY_MUX F=0
Initialization of carry chain (One Logic Cell)
X5709

Figure 7: XC5200 CY_MUX Used for Adder Carry Propagate

Carry Function
The XC5200 family supports a carry-logic feature that enhances the performance of arithmetic functions such as counters, adders, etc. A carry multiplexer (CY_MUX) symbol is used to indicate the XC5200 carry logic. This symbol represents the dedicated 2:1 multiplexer in each LC that performs the one-bit high-speed carry propagate per logic cell (four bits per CLB). While the carry propagate is performed inside the LC, an adjacent LC must be used to complete the arithmetic function. Figure 7 represents an example of an adder function. The carry propagate is performed on the CLB shown, which also generates the half-sum for the four-bit adder. An adjacent CLB is responsible for XORing the half-sum with the corresponding carry-out. Thus an adder or counter

requires two LCs per bit. Notice that the carry chain requires an initialization stage, which the XC5200 family accomplishes using the carry initialize (CY_INIT) macro and one additional LC. The carry chain can propagate vertically up a column of CLBs. The XC5200 library contains a set of Relationally-Placed Macros (RPMs) and arithmetic functions designed to take advantage of the dedicated carry logic. Using and modifying these macros makes it much easier to implement customized RPMs, freeing the designer from the need to become an expert on architectures.

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cascade out

Table 4: CLB Storage Element Functionality (active rising edge is shown) Mode Power-Up or GR Flip-Flop
X

CO DI DO out

CK X X __/ 0 1 0 X

CE X X 1* X 1* 1* 0

CLR X 1 0* 0* 0* 0* 0*

D X X D X X D X

Q 0 0 D Q Q D Q

D
A15 A14 A13 A12 F4 F3 F2 F1 AND CY_MUX

Q
FD

LC3
DI D
CY_MUX A11 A10 A9 A8 DO

Latch Both
Legend: X __/ 0* 1*

Q
FD

F4 F3 F2 F1

AND X

LC2
DI DO

Dont care Rising edge Input is Low or unconnected (default value) Input is High or unconnected (default value)

D
A7 A6 A5 A4 F4 F3 F2 F1 AND CY_MUX

Q
FD

Data Inputs and Outputs

X

LC1
DI DO

D
A3 A2 A1 A0 F4 F3 F2 F1 CI cascade in CE CK CLR AND CY_MUX

Q
FD

The source of a storage element data input is programmable. It is driven by the function F, or by the Direct In (DI) block input. The ip-ops or latches drive the Q CLB outputs. Four fast feed-through paths from DI to DO are available, as shown in Figure 5. This bypass is sometimes used by the automated router to repower internal signals. In addition to the storage element (Q) and direct (DO) outputs, there is a combinatorial output (X) that is always sourced by the Lookup Table.
X5708

LC0

CY_MUX F=0 Initialization of carry chain (One Logic Cell)

Figure 8: XC5200 CY_MUX Used for Decoder Cascade Logic

The four edge-triggered D-type ip-ops or level-sensitive latches have common clock (CK) and clock enable (CE) inputs. Any of the clock inputs can also be permanently enabled. Storage element functionality is described in Table 4.

Cascade Function
Each CY_MUX can be connected to the CY_MUX in the adjacent LC to provide cascadable decode logic. Figure 8 illustrates how the 4-input function generators can be congured to take advantage of these four cascaded CY_MUXes. Note that AND and OR cascading are specic cases of a general decode. In AND cascading all bits are decoded equal to logic one, while in OR cascading all bits are decoded equal to logic zero. The exibility of the LUT achieves this result. The XC5200 library contains gate macros designed to take advantage of this function.

Clock Input
The ip-ops can be triggered on either the rising or falling clock edge. The clock pin is shared by all four storage elements with individual polarity control. Any inverter placed on the clock input is automatically absorbed into the CLB.

Clock Enable
The clock enable signal (CE) is active High. The CE pin is shared by the four storage elements. If left unconnected for any, the clock enable for that storage element defaults to the active state. CE is not invertible within the CLB.

CLB Flip-Flops and Latches

The CLB can pass the combinatorial output(s) to the interconnect network, but can also store the combinatorial results or other incoming data in ip-ops, and connect their outputs to the interconnect network as well. The CLB storage elements can also be congured as latches. April 8, 1998 (Version 5.0)

Clear
An asynchronous storage element input (CLR) can be used to reset all four ip-ops or latches in the CLB. This input can also be independently disabled for any ip-op. CLR is active High. It is not invertible within the CLB.

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XC5200 Series Field Programmable Gate Arrays

STARTUP PAD IBUF GR GTS Q2 Q3 Q1Q4 CLK DONEIN

X9009

Three-State Buffers
The XC5200 family has four dedicated Three-State Buffers (TBUFs, or BUFTs in the schematic library) per CLB (see Figure 10). The four buffers are individually congurable through four conguration bits to operate as simple noninverting buffers or in 3-state mode. When in 3-state mode the CLB output enable (TS) control signal drives the enable to all four buffers. Each TBUF can drive up to two horizontal and/or two vertical Longlines. These 3-state buffers can be used to implement multiplexed or bidirectional buses on the horizontal or vertical longlines, saving logic resources.
TS

Figure 9: Schematic Symbols for Global Reset

Global Reset
A separate Global Reset line clears each storage element during power-up, reconguration, or when a dedicated Reset net is driven active. This global net (GR) does not compete with other routing resources; it uses a dedicated distribution network. GR can be driven from any user-programmable pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GR pin of the STARTUP symbol. (See Figure 9.) A specic pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global Reset signal. Alternatively, GR can be driven from any internal node.

CLB CLB LC3 LC2 LC1 LC0

Using FPGA Flip-Flops and Latches

The abundance of ip-ops in the XC5200 Series invites pipelined designs. This is a powerful way of increasing performance by breaking the function into smaller subfunctions and executing them in parallel, passing on the results through pipeline ip-ops. This method should be seriously considered wherever throughput is more important than latency. To include a CLB ip-op, place the appropriate library symbol. For example, FDCE is a D-type ip-op with clock enable and asynchronous clear. The corresponding latch symbol is called LDCE. In XC5200-Series devices, the ip-ops can be used as registers or shift registers without blocking the function generators from performing a different, perhaps unrelated task. This ability increases the functional capacity of the devices. The CLB setup time is specied between the function generator inputs and the clock input CK. Therefore, the specied CLB ip-op setup time includes the delay through the function generator.

Horizontal Longlines

X9030

Figure 10: XC5200 3-State Buffers The 3-state buffer enable is an active-High 3-state (i.e. an active-Low enable), as shown in Table 5. Another 3-state buffer with similar access is located near each I/O block along the right and left edges of the array. The longlines driven by the 3-state buffers have a weak keeper at each end. This circuit prevents undened oating levels. However, it is overridden by any driver. To ensure the longline goes high when no buffers are on, add an additional BUFT to drive the output High during all of the previously undened states. Figure 11 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the buffer 3-state signal. Table 5: Three-State Buffer Functionality IN X IN T 1 0 OUT Z IN

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~100 k

Z = DA A + DB B + DC C + DN N

DA BUFT A "Weak Keeper"

DB BUFT B

DC BUFT C

DN BUFT N
X6466

Figure 11: 3-State Buffers Implement a Multiplexer

Input/Output Blocks
User-congurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be congured for input, output, or bidirectional signals. The I/O block, shown in Figure 12, consists of an input buffer and an output buffer. The output driver is an 8-mA full-rail CMOS buffer with 3-state control. Two slew-rate control modes are supported to minimize bus transients. Both the output buffer and the 3-state control are invertible. The input buffer has globally selected CMOS or TTL input thresholds. The input buffer is invertible and also provides a programmable delay line to assure reliable chip-to-chip setup and hold times. Minimum ESD protection is 3 KV using the Human Body Model.
Vcc
Input Buffer Delay

Table 6: Supported Sources for XC5200-Series Device Inputs XC5200 Input Mode 5 V, 5 V, TTL CMOS Unreliable Data

Source Any device, Vcc = 3.3 V, CMOS outputs Any device, Vcc = 5 V, TTL outputs Any device, Vcc = 5 V, CMOS outputs

Optional Delay Guarantees Zero Hold Time

XC5200 devices do not have storage elements in the IOBs. However, XC5200 IOBs can be efciently routed to CLB ip-ops or latches to store the I/O signals. The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup time of the input ip-op is increased so that normal clock routing does not result in a positive hold-time requirement. A positive hold time requirement can lead to unreliable, temperature- or processing-dependent operation. The input ip-op setup time is dened between the data measured at the device I/O pin and the clock input at the CLB (not at the clock pin). Any routing delay from the device clock pin to the clock input of the CLB must, therefore, be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins. A short specied setup time might, therefore, result in a negative setup time at the device pins, i.e., a positive hold-time requirement. When a delay is inserted on the data line, more clock delay can be tolerated without causing a positive hold-time requirement. Sufcient delay eliminates the possibility of a data hold-time requirement at the external pin. The maximum delay is therefore inserted as the software default. The XC5200 IOB has a one-tap delay element: either the delay is inserted (default), or it is not. The delay guarantees a zero hold time with respect to clocks routed through any of the XC5200 global clock buffers. (See Global Lines on page 260 for a description of the global clock buffers in the XC5200.) For a shorter input register setup time, with non-zero hold, attach a NODELAY attribute or property to the ip-op or input buffer.

Pullup

I
Output Buffer

PAD
Pulldown

O T

X9001

Slew Rate Control

Figure 12: XC5200 I/O Block

IOB Input Signals

The XC5200 inputs can be globally congured for either TTL (1.2V) or CMOS thresholds, using an option in the bitstream generation software. There is a slight hysteresis of about 300mV. The inputs of XC5200-Series 5-Volt devices can be driven by the outputs of any 3.3-Volt device, if the 5-Volt inputs are in TTL mode. Supported sources for XC5200-Series device inputs are shown in Table 6.

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IOB Output Signals

Output signals can be optionally inverted within the IOB, and pass directly to the pad. As with the inputs, a CLB ipop or latch can be used to store the output signal. An active-High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under conguration control, the output (OUT) and output 3-state (T) signals can be inverted. The polarity of these signals is independently congured for each IOB. The XC5200 devices provide a guaranteed output sink current of 8 mA. Supported destinations for XC5200-Series device outputs are shown in Table 7.(For a detailed discussion of how to interface between 5 V and 3.3 V devices, see the 3V Products section of The Programmable Logic Data Book.) An output can be congured as open-drain (open-collector) by placing an OBUFT symbol in a schematic or HDL code, then tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground. (See Figure 13.) Table 7: Supported Destinations for XC5200-Series Outputs XC5200 Output Mode 5 V, CMOS some1

200 pF for all package pins between each Power/Ground pin pair. For some XC5200 devices, additional internal Power/Ground pin pairs are connected to special Power and Ground planes within the packages, to reduce ground bounce. For slew-rate limited outputs this total is two times larger for each device type: 400 pF for XC5200 devices. This maximum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 V amplitude and more than 5 ns duration. This level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. This restriction is common to all high-speed digital ICs, and is not particular to Xilinx or the XC5200 Series. XC5200-Series devices have a feature called Soft Startup, designed to reduce ground bounce when all outputs are turned on simultaneously at the end of conguration. When the conguration process is nished and the device starts up, the rst activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is determined by the individual conguration option for each IOB. Global Three-State A separate Global 3-State line (not shown in Figure 12) forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. This global net (GTS) does not compete with other routing resources; it uses a dedicated distribution network. GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. A specic pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3-State signal. Using GTS is similar to Global Reset. See Figure 9 on page 254 for details. Alternatively, GTS can be driven from any internal node.

Destination XC5200 device, VCC=3.3 V, CMOS-threshold inputs Any typical device, VCC = 3.3 V, CMOS-threshold inputs Any device, VCC = 5 V, TTL-threshold inputs Any device, VCC = 5 V, CMOS-threshold inputs

1. Only if destination device has 5-V tolerant inputs

OPAD OBUFT
X6702

Other IOB Options

There are a number of other programmable options in the XC5200-Series IOB. Pull-up and Pull-down Resistors

Figure 13: Open-Drain Output

Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or property to the output buffer or ip-op. For XC5200 devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is

Programmable IOB pull-up and pull-down resistors are useful for tying unused pins to Vcc or Ground to minimize power consumption and reduce noise sensitivity. The congurable pull-up resistor is a p-channel transistor that pulls to Vcc. The congurable pull-down resistor is an n-channel transistor that pulls to Ground.

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The value of these resistors is 20 k 100 k. This high value makes them unsuitable as wired-AND pull-up resistors. The pull-up resistors for most user-programmable IOBs are active during the conguration process. See Table 14 on page 288 for a list of pins with pull-ups active before and during conguration. After conguration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are congured with the internal pull-up resistor active. Alternatively, they can be individually congured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pullup, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad. JTAG Support Embedded logic attached to the IOBs contains test structures compatible with IEEE Standard 1149.1 for boundary scan testing, simplifying board-level testing. More information is provided in Boundary Scan on page 262. CLK

OSC5

OSC1 OSC2 OSC1 OSC2

CK_DIV

Figure 14: XC5200 Oscillator Macros

VersaBlock Routing
The General Routing Matrix (GRM) connects to the VersaBlock via 24 bidirectional ports (M0-M23). Excluding direct connections, global nets, and 3-statable Longlines, all VersaBlock inputs and outputs connect to the GRM via these 24 ports. Four 3-statable unidirectional signals (TQ0-TQ3) drive out of the VersaBlock directly onto the horizontal and vertical Longlines. Two horizontal global nets and two vertical global nets connect directly to every CLB clock pin; they can connect to other CLB inputs via the GRM. Each CLB also has four unidirectional direct connects to each of its four neighboring CLBs. These direct connects can also feed directly back to the CLB (see Figure 15). In addition, each CLB has 16 direct inputs, four direct connections from each of the neighboring CLBs. These direct connections provide high-speed local routing that bypasses the GRM.

Oscillator
XC5200 devices include an internal oscillator. This oscillator is used to clock the power-on time-out, clear conguration memory, and source CCLK in Master conguration modes. The oscillator runs at a nominal 12 MHz frequency that varies with process, Vcc, and temperature. The output CCLK frequency is selectable as 1 MHz (default), 6 MHz, or 12 MHz. The XC5200 oscillator divides the internal 12-MHz clock or a user clock. The user then has the choice of dividing by 4, 16, 64, or 256 for the OSC1 output and dividing by 2, 8, 32, 128, 1024, 4096, 16384, or 65536 for the OSC2 output. The division is specied via a DIVIDEn_BY=x attribute on the symbol, where n=1 for OSC1, or n=2 for OSC2. These frequencies can vary by as much as -50% or + 50%. The OSC5 macro is used where an internal oscillator is required. The CK_DIV macro is applicable when a user clock input is specied (see Figure 14).

Local Interconnect Matrix

The Local Interconnect Matrix (LIM) is built from input and output multiplexers. The 13 CLB outputs (12 LC outputs plus a Vcc/GND signal) connect to the eight VersaBlock outputs via the output multiplexers, which consist of eight fully populated 13-to-1 multiplexers. Of the eight VersaBlock outputs, four signals drive each neighboring CLB directly, and provide a direct feedback path to the input multiplexers. The four remaining multiplexer outputs can drive the GRM through four TBUFs (TQ0-TQ3). All eight multiplexer outputs can connect to the GRM through the bidirectional M0-M23 signals. All eight signals also connect to the input multiplexers and are potential inputs to that CLB.

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XC5200 Series Field Programmable Gate Arrays

To GRM M0-M23

24

Global Nets

TS COUT 4 4 To Longlines and GRM TQ0-TQ3

North South East West

CLB
4 5 4 4

LC3 LC2 LC1 LC0

Input Multiplexers

3 VCC /GND 3

Output Multiplexers

8 4

Direct to East

5 Direct North CLK 4 Feedback 4 CE CLR CIN

Direct West

4 4

Direct South

X5724

Figure 15: VersaBlock Details CLB inputs have several possible sources: the 24 signals from the GRM, 16 direct connections from neighboring VersaBlocks, four signals from global, low-skew buffers, and the four signals from the CLB output multiplexers. Unlike the output multiplexers, the input multiplexers are not fully populated; i.e., only a subset of the available signals can be connected to a given CLB input. The exibility of LUT input swapping and LUT mapping compensates for this limitation. For example, if a 2-input NAND gate is required, it can be mapped into any of the four LUTs, and use any two of the four inputs to the LUT. The direct connects also provide a high-speed path from the edge CLBs to the VersaRing input/output buffers, and thus reduce pin-to-pin set-up time, clock-to-out, and combinational propagation delay. Direct connects from the input buffers to the CLB DI pin (direct ip-op input) are only available on the left and right edges of the device. CLB look-up table inputs and combinatorial/registered outputs have direct connects to input/output buffers on all four sides. The direct connects are ideal for developing customized RPM cells. Using direct connects improves the macro performance, and leaves the other routing channels intact for improved routing. Direct connects can also route through a CLB using one of the four cell-feedthrough paths.

Direct Connects
The unidirectional direct-connect segments are connected to the logic input/output pins through the CLB input and output multiplexer arrays, and thus bypass the general routing matrix altogether. These lines increase the routing channel utilization, while simultaneously reducing the delay incurred in speed-critical connections.

General Routing Matrix

The General Routing Matrix, shown in Figure 16, provides exible bidirectional connections to the Local Interconnect Matrix through a hierarchy of different-length metal segments in both the horizontal and vertical directions. A pro-

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GRM VersaBlock

GRM VersaBlock

GRM VersaBlock

GRM VersaBlock

GRM VersaBlock

GRM VersaBlock

2
GRM VersaBlock GRM VersaBlock GRM VersaBlock

3 4

Six Levels of Routing Hierarchy 1 2 3 4 5 6 LIM

Single-length Lines Double-length Lines

GRM
24 24

TS CLB

LC3
Direct Connects Longlines and Global Lines Local Interconnect Matrix Logic Cell Feedthrough Path (Contained within each Logic Cell)
4 4 4

LC2 LC1

4 4

6 LC0

LIM
4 4

Direct Connects

X4963

Figure 16: XC5200 Interconnect Structure grammable interconnect point (PIP) establishes an electrical connection between two wire segments. The PIP, consisting of a pass transistor switch controlled by a memory element, provides bidirectional (in some cases, unidirectional) connection between two adjoining wires. A collection of PIPs inside the General Routing Matrix and in the Local Interconnect Matrix provides connectivity between various types of metal segments. A hierarchy of PIPs and associated routing segments combine to provide a powerful interconnect hierarchy: Forty bidirectional single-length segments per CLB provide ten routing channels to each of the four neighboring CLBs in four directions. Sixteen bidirectional double-length segments per CLB provide four routing channels to each of four other (nonneighboring) CLBs in four directions. Eight horizontal and eight vertical bidirectional Longline segments span the width and height of the chip, respectively. Two low-skew horizontal and vertical unidirectional globalline segments span each row and column of the chip, respectively.

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Single- and Double-Length Lines

The single- and double-length bidirectional line segments make up the bulk of the routing channels. The doublelength lines hop across every other CLB to reduce the propagation delays in speed-critical nets. Regenerating the signal strength is recommended after traversing three or four such segments. XACTstep place-and-route software automatically connects buffers in the path of the signal as necessary. Single- and double-length lines cannot drive onto Longlines and global lines; Longlines and global lines can, however, drive onto single- and double-length lines. As a general rule, Longline and global-line connections to the general routing matrix are unidirectional, with the signal direction from these lines toward the routing matrix.

simple as adding an additional TBUF to drive the bus High when the previously undened states are activated.

Global Lines
Global buffers in Xilinx FPGAs are special buffers that drive a dedicated routing network called Global Lines, as shown in Figure 17. This network is intended for high-fanout clocks or other control signals, to maximize speed and minimize skewing while distributing the signal to many loads. The XC5200 family has a total of four global buffers (BUFG symbol in the library), each with its own dedicated routing channel. Two are distributed vertically and two horizontally throughout the FPGA. The global lines provide direct input only to the CLB clock pins. The global lines also connect to the General Routing Matrix to provide access from these lines to the function generators and other control signals. Four clock input pads at the corners of the chip, as shown in Figure 17, provide a high-speed, low-skew clock network to each of the four global-line buffers. In addition to the dedicated pad, the global lines can be sourced by internal logic. PIPs from several routing channels within the VersaRing can also be congured to drive the global-line buffers. Details of all the programmable interconnect for a CLB is shown in Figure 18.

Longlines
Longlines are used for high-fan-out signals, 3-state busses, low-skew nets, and faraway destinations. Row and column splitter PIPs in the middle of the array effectively double the total number of Longlines by electrically dividing them into two separated half-lines. Longlines are driven by the 3state buffers in each CLB, and are driven by similar buffers at the periphery of the array from the VersaRing I/O Interface. Bus-oriented designs are easily implemented by using Longlines in conjunction with the 3-state buffers in the CLB and in the VersaRing. Additionally, weak keeper cells at the periphery retain the last valid logic level on the Longlines when all buffers are in 3-state mode. Longlines connect to the single-length or double-length lines, or to the logic inside the CLB, through the General Routing Matrix. The only manner in which a Longline can be driven is through the four 3-state buffers; therefore, a Longline-to-Longline or single-line-to-Longline connection through PIPs in the General Routing Matrix is not possible. Again, as a general rule, long- and global-line connections to the General Routing Matrix are unidirectional, with the signal direction from these lines toward the routing matrix. The XC5200 family has no pull-ups on the ends of the Longlines sourced by TBUFs, unlike the XC4000 Series. Consequently, wired functions (i.e., WAND and WORAND) and wide multiplexing functions requiring pull-ups for undened states (i.e., bus applications) must be implemented in a different way. In the case of the wired functions, the same functionality can be achieved by taking advantage of the carry/cascade logic described above, implementing a wide logic function in place of the wired function. In the case of 3state bus applications, the user must insure that all states of the multiplexing function are dened. This process is as

GCK1

GCK4

GCK2

GCK3
X5704

Figure 17: Global Lines .

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LONG

DIRECT

GLOBAL

CARRY DOUBLE SINGLE

DIRECT

CLB

GLOBAL

DIRECT

Figure 18: Detail of Programmable Interconnect Associated with XC5200 Series CLB

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DOUBLE

SINGLE

LONG

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VersaRing Input/Output Interface

The VersaRing, shown in Figure 19, is positioned between the core logic and the pad ring; it has all the routing resources of a VersaBlock without the CLB logic. The VersaRing decouples the core logic from the I/O pads. Each VersaRing Cell provides up to four pad-cell connections on one side, and connects directly to the CLB ports on the other side.

XC5200 devices support all the mandatory boundary-scan instructions specied in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions. The TAP can also support two USERCODE instructions. When the boundary scan conguration option is selected, three normal user I/O pins become dedicated inputs for these functions. Another user output pin becomes the dedicated boundary scan output. Boundary-scan operation is independent of individual IOB conguration and package type. All IOBs are treated as independently controlled bidirectional pins, including any unbonded IOBs. Retaining the bidirectional test capability after conguration provides exibility for interconnect testing.

VersaRing
8 8 2 2 GRM 10 2 Pad Pad 2 8

Interconnect
4 4 Pad Pad

Also, internal signals can be captured during EXTEST by connecting them to unbonded IOBs, or to the unused outputs in IOBs used as unidirectional input pins. This technique partially compensates for the lack of INTEST support. The user can serially load commands and data into these devices to control the driving of their outputs and to examine their inputs. This method is an improvement over bedof-nails testing. It avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fth pin, a reset for the control logic, is described in the standard but is not implemented in Xilinx devices. The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state machine, an instruction register and a number of data registers. The functional details can be found in the IEEE 1149.1 specication and are also discussed in the Xilinx application note XAPP 017: Boundary Scan in XC4000 and XC5200 Series devices Figure 20 on page 263 is a diagram of the XC5200-Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. The public boundary-scan instructions are always available prior to conguration. After conguration, the public instructions and any USERCODE instructions are only available if specied in the design. While SAMPLE and BYPASS are available during conguration, it is recommended that boundary-scan operations not be performed during this transitory period. In addition to the test instructions outlined above, the boundary-scan circuitry can be used to congure the FPGA device, and to read back the conguration data. All of the XC4000 boundary-scan modes are supported in the XC5200 family. Three additional outputs for the UserRegister are provided (Reset, Update, and Shift), representing the decoding of the corresponding state of the boundary-scan internal state machine.

VersaBlock

8 2 2 GRM 10

Pad Pad

Interconnect
Pad 4 VersaBlock 4 2 8 2 8
X5705

Pad

Figure 19: VersaRing I/O Interface

Boundary Scan
The bed of nails has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technology and multi-layer boards. The IEEE boundary scan standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for I/O and internal logic. This structure is easily implemented with a four-pin interface on any boundary scan-compatible IC. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two.

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DATA IN

1 0 D Q D

sd Q

LE 1 IOB.O IOB.T 1 0 IOB IOB IOB IOB IOB D Q D sd Q 0

0 1

LE

IOB

IOB

1 0

sd D Q D Q

IOB

IOB LE

IOB

IOB IOB.I 1 0 1 sd D Q D Q

IOB

IOB

IOB

IOB

IOB

IOB

LE 1 IOB.O IOB.T 0

IOB

BYPASS REGISTER INSTRUCTION REGISTER

IOB

TDI

M TDO U X

0 1 0 D Q D sd Q 1

LE M U TDO X INSTRUCTION REGISTER BYPASS REGISTER TDI

1 IOB 0 D Q D

sd Q

IOB

IOB

IOB

LE

IOB

IOB

1 IOB.I 0

IOB

IOB

1 0 D Q D

sd Q

IOB

IOB LE

IOB

IOB IOB.O DATAOUT IOB IOB IOB IOB IOB SHIFT/ CAPTURE CLOCK DATA REGISTER UPDATE

0 1

IOB

IOB

EXTEST

X1523

Figure 20: XC5200-Series Boundary Scan Logic

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XC5200-Series devices can also be congured through the boundary scan logic. See XAPP 017 for more information.

Bit Sequence
The bit sequence within each IOB is: 3-State, Out, In. The data-register cells for the TAP pins TMS, TCK, and TDI have an OR-gate that permanently disables the output buffer if boundary-scan operation is selected. Consequently, it is impossible for the outputs in IOBs used by TAP inputs to conict with TAP operation. TAP data is taken directly from the pin, and cannot be overwritten by injected boundary-scan data. The primary global clock inputs (PGCK1-PGCK4) are taken directly from the pins, and cannot be overwritten with boundary-scan data. However, if necessary, it is possible to drive the clock input from boundary scan. The external clock source is 3-stated, and the clock net is driven with boundary scan data through the output driver in the clockpad IOB. If the clock-pad IOBs are used for non-clock signals, the data may be overwritten normally. Pull-up and pull-down resistors remain active during boundary scan. Before and during conguration, all pins are pulled up. After conguration, the choice of internal pull-up or pull-down resistor must be taken into account when designing test vectors to detect open-circuit PC traces. From a cavity-up view of the chip (as shown in XDE or Epic), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Table 9. The device-specic pinout tables for the XC5200 Series include the boundary scan locations for each IOB pin. Table 9: Boundary Scan Bit Sequence Bit Position Bit 0 (TDO) Bit 1 ... ... ... Bit N (TDI) I/O Pad Location Top-edge I/O pads (right to left) ... Left-edge I/O pads (top to bottom) Bottom-edge I/O pads (left to right) Right-edge I/O pads (bottom to top) BSCANT.UPD

Data Registers
The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-State Control. Non-IOB pins have appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures all In, Out, and 3-State pins. The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals. The other standard data register is the single ip-op BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA provides two additional data registers that can be specied using the BSCAN macro. The FPGA provides two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions, USER1 and USER2. For these instructions, two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE).

Instruction Set
The XC5200-Series boundary scan instruction set also includes instructions to congure the device and read back the conguration data. The instruction set is coded as shown in Table 8. Table 8: Boundary Scan Instructions Instruction I2 I1 I0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 Test TDO Source Selected EXTEST DR SAMPLE/ DR PRELOAD USER 1 BSCAN. TDO1 USER 2 BSCAN. TDO2 READBACK Readback Data CONFIGURE DOUT Reserved BYPASS Bypass Register I/O Data Source DR Pin/Logic User Logic User Logic Pin/Logic Disabled

BSDL (Boundary Scan Description Language) les for XC5200-Series devices are available on the Xilinx web site in the File Download area.

Including Boundary Scan

If boundary scan is only to be used during conguration, no special elements need be included in the schematic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user functions after conguration. To indicate that boundary scan remain enabled after conguration, include the BSCAN library symbol and connect pad symbols to the TDI, TMS, TCK and TDO pins, as shown in Figure 21.

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Optional IBUF BSCAN

RESET UPDATE SHIFT TDI TMS TCK TDO DRCK IDLE SEL1 SEL2

Ground pins of the package will provide adequate decoupling.

To User Logic

Output buffers capable of driving/sinking the specied 8 mA loads under specied worst-case conditions may be capable of driving/sinking up to 10 times as much current under best case conditions. Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direction. It may also be benecial to locate heavily loaded output buffers near the Ground pads. The I/O Block output buffers have a slew-rate limited mode (default) which should be used where output rise and fall times are not speed-critical.

From User Logic

TDO1 TDO2

To User Logic

X9000

Figure 21: Boundary Scan Schematic Example Even if the boundary scan symbol is used in a schematic, the input pins TMS, TCK, and TDI can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDI and TCK.

GND Ground and Vcc Ring for I/O Drivers

Vcc

Vcc

Avoiding Inadvertent Boundary Scan

If TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant during conguration. In some applications, a situation may occur where TMS or TCK is driven during conguration. This may cause the device to go into boundary scan mode and disrupt the conguration process. To prevent activation of boundary scan during conguration, do either of the following: TMS: Tie High to put the Test Access Port controller in a benign RESET state TCK: Tie High or Lowdo not toggle this clock input.
Logic Power Grid

GND

X5422

Figure 22: XC5200-Series Power Distribution

Pin Descriptions
There are three types of pins in the XC5200-Series devices: Permanently dedicated pins User I/O pins that can have special functions Unrestricted user-programmable I/O pins.

For more information regarding boundary scan, refer to the Xilinx Application Note XAPP 017, Boundary Scan in XC4000 and XC5200 Devices.

Power Distribution
Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated Vcc and Ground ring surrounding the logic array provides power to the I/O drivers, as shown in Figure 22. An independent matrix of Vcc and Ground lines supplies the interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically, a 0.1 F capacitor connected near the Vcc and

Before and during conguration, all outputs not used for the conguration process are 3-stated and pulled high with a 20 k - 100 k pull-up resistor. After conguration, if an IOB is unused it is congured as an input with a 20 k - 100 k pull-up resistor. Device pins for XC5200-Series devices are described in Table 10. Pin functions during conguration for each of the seven conguration modes are summarized in Pin Functions During Conguration on page 288, in the Conguration Timing section.

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Table 10: Pin Descriptions I/O I/O During After Pin Name Cong. Cong. Permanently Dedicated Pins VCC I I

Pin Description

Five or more (depending on package) connections to the nominal +5 V supply voltage. All must be connected, and each must be decoupled with a 0.01 - 0.1 F capacitor to Ground. Four or more (depending on package type) connections to Ground. All must be conGND I I nected. During configuration, Configuration Clock (CCLK) is an output in Master modes or Asynchronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and CCLK I or O I can be selected as the Readback Clock. There is no CCLK High time restriction on XC5200-Series devices, except during Readback. See Violating the Maximum High and Low Time Specification for the Readback Clock on page 277 for an explanation of this exception. DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a Low level on DONE can be configured to delay the global logic initialization and the enabling of outDONE I/O O puts. The exact timing, the clock source for the Low-to-High transition, and the optional pullup resistor are selected as options in the XACTstep program that creates the configuration bitstream. The resistor is included by default. PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA PROGRAM I I executes a complete clear cycle, before it goes into a WAIT state and releases INIT. The PROGRAM pin has an optional weak pull-up after configuration. User I/O Pins That Can Have Special Functions During Peripheral mode configuration, this pin indicates when it is appropriate to write another byte of data into the FPGA. The same status is also available on D7 in AsynRDY/BUSY O I/O chronous Peripheral mode, if a read operation is performed when the device is selected. After configuration, RDY/BUSY is a user-programmable I/O pin. RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High. During Master Parallel configuration, each change on the A0-A17 outputs is preceded by a rising edge on RCLK, a redundant output signal. RCLK is useful for clocked RCLK O I/O PROMs. It is rarely used during configuration. After configuration, RCLK is a user-programmable I/O pin. As Mode inputs, these pins are sampled before the start of configuration to determine the configuration mode to be used. After configuration, M0, M1, and M2 become userprogrammable I/O. M0, M1, M2 I I/O During configuration, these pins have weak pull-up resistors. For the most popular configuration mode, Slave Serial, the mode pins can thus be left unconnected. A pull-down resistor value of 4.7 k is recommended for other modes. If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used, this pin is a 3-state output, after configuration is completed. TDO O O This pin can be user output only when called out by special schematic definitions. To use this pin, place the library component TDO instead of the usual pad symbol. An output buffer must still be used.

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Table 10: Pin Descriptions (Continued) I/O I/O During After Cong. Cong.

Pin Name

TDI, TCK, TMS

HDC

LDC

INIT

I/O

GCK1 GCK4

Weak Pull-up

CS0, CS1, WS, RS

A0 - A17 D0 - D7 DIN

O I I

DOUT

Pin Description If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. I/O If the BSCAN symbol is not placed in the design, all boundary scan functions are inhibor I ited once configuration is completed, and these pins become user-programmable I/O. (JTAG) In this case, they must be called out by special schematic definitions. To use these pins, place the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used. High During Configuration (HDC) is driven High until the I/O go active. It is available as I/O a control output indicating that configuration is not yet completed. After configuration, HDC is a user-programmable I/O pin. Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a control output indicating that configuration is not yet completed. After configuration, I/O LDC is a user-programmable I/O pin. Before and during configuration, INIT is a bidirectional signal. A 1 k - 10 k external pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used I/O to hold the FPGA in the internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an additional 50 to 250 s after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O go active, INIT is a user-programmable I/O pin. Four Global inputs each drive a dedicated internal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If not used to drive a global net, any of these pins is a user-programmable I/O pin. I or I/O The GCK1-GCK4 pins provide the shortest path to the four Global Buffers. Any input pad symbol connected directly to the input of a BUFG symbol is automatically placed on one of these pins. These four inputs are used in Asynchronous Peripheral mode. The chip is selected when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe (WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low on Read Strobe (RS) changes D7 into a status output High if Ready, Low if Busy I/O and drives D0 - D6 High. In Express mode, CS1 is used as a serial-enable signal for daisy-chaining. WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write Strobe overrides. After configuration, these are user-programmable I/O pins. During Master Parallel configuration, these 18 output pins address the configuration I/O EPROM. After configuration, they are user-programmable I/O pins. During Master Parallel, Peripheral, and Express configuration, these eight input pins reI/O ceive configuration data. After configuration, they are user-programmable I/O pins. During Slave Serial or Master Serial configuration, DIN is the serial configuration data I/O input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is the D0 input. After configuration, DIN is a user-programmable I/O pin. During configuration in any mode but Express mode, DOUT is the serial configuration data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK. I/O In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices. After configuration, DOUT is a user-programmable I/O pin.

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Table 10: Pin Descriptions (Continued) I/O I/O During After Pin Name Cong. Cong. Pin Description Unrestricted User-Programmable I/O Pins These pins can be configured to be input and/or output after configuration is completed. Weak I/O I/O Before configuration is completed, these pins have an internal high-value pull-up resisPull-up tor (20 k - 100 k) that defines the logic level as High.

Conguration
Conguration is the process of loading design-specic programming data into one or more FPGAs to dene the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. XC5200-Series devices use several hundred bits of conguration data per CLB and its associated interconnects. Each conguration bit denes the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The XACTstep development system translates the design into a netlist le. It automatically partitions, places and routes the logic and generates the conguration data in PROM format.

Table 11: Conguration Modes Mode Master Serial Slave Serial Master Parallel Up Master Parallel Down Peripheral Synchronous* Peripheral Asynchronous Express Reserved M2 0 1 1 M1 0 1 0 M0 0 1 0 CCLK output input output Data Bit-Serial Bit-Serial Byte-Wide, increment from 00000 Byte-Wide, decrement from 3FFFF Byte-Wide Byte-Wide Byte-Wide

output

0 1 0 0

1 0 1 0

1 1 0 1

input output input

Special Purpose Pins

Three conguration mode pins (M2, M1, M0) are sampled prior to conguration to determine the conguration mode. After conguration, these pins can be used as auxiliary I/O connections. The XACTstep development system does not use these resources unless they are explicitly specied in the design entry. This is done by placing a special pad symbol called MD2, MD1, or MD0 instead of the input or output pad symbol. In XC5200-Series devices, the mode pins have weak pullup resistors during conguration. With all three mode pins High, Slave Serial mode is selected, which is the most popular conguration mode. Therefore, for the most common conguration mode, the mode pins can be left unconnected. (Note, however, that the internal pull-up resistor value can be as high as 100 k.) After conguration, these pins can individually have weak pull-up or pull-down resistors, as specied in the design. A pull-down resistor value of 4.7 k is recommended. These pins are located in the lower left chip corner and are near the readback nets. This location allows convenient routing if compatibility with the XC2000 and XC3000 family conventions of M0/RT, M1/RD is desired.

Note :*Peripheral Synchronous can be considered byte-wide Slave Parallel

which is used primarily for daisy-chained devices. The seventh mode, called Express mode, is an additional slave mode that allows high-speed parallel conguration. The coding for mode selection is shown in Table 11. Note that the smallest package, VQ64, only supports the Master Serial, Slave Serial, and Express modes.A detailed description of each conguration mode, with timing information, is included later in this data sheet. During conguration, some of the I/O pins are used temporarily for the conguration process. All pins used during conguration are shown in Table 14 on page 288.

Master Modes
The three Master modes use an internal oscillator to generate a Conguration Clock (CCLK) for driving potential slave devices. They also generate address and timing for external PROM(s) containing the conguration data. Master Parallel (Up or Down) modes generate the CCLK signal and PROM addresses and receive byte parallel data. The data is internally serialized into the FPGA data-frame format. The up and down selection generates starting addresses at either zero or 3FFFF, for compatibility with different microprocessor addressing conventions. The Master Serial mode generates CCLK and receives the congura-

Conguration Modes
XC5200 devices have seven conguration modes. These modes are selected by a 3-bit input code applied to the M2, M1, and M0 inputs. There are three self-loading Master modes, two Peripheral modes, and a Serial Slave mode,

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tion data in serial form from a Xilinx serial-conguration PROM. CCLK speed is selectable as 1 MHz (default), 6 MHz, or 12 MHz. Conguration always starts at the default slow frequency, then can switch to the higher frequency during the rst frame. Frequency tolerance is -50% to +50%.

Multi-Family Daisy Chain All Xilinx FPGAs of the XC2000, XC3000, XC4000, and XC5200 Series use a compatible bitstream format and can, therefore, be connected in a daisy chain in an arbitrary sequence. There is, however, one limitation. If the chain contains XC5200-Series devices, the master normally cannot be an XC2000 or XC3000 device. The reason for this rule is shown in Figure 26 on page 273. Since all devices in the chain store the same length count value and generate or receive one common sequence of CCLK pulses, they all recognize length-count match on the same CCLK edge, as indicated on the left edge of Figure 26. The master device then generates additional CCLK pulses until it reaches its nish point F. The different families generate or require different numbers of additional CCLK pulses until they reach F. Not reaching F means that the device does not really nish its conguration, although DONE may have gone High, the outputs became active, and the internal reset was released. For the XC5200Series device, not reaching F means that readback cannot be initiated and most boundary scan instructions cannot be used. The user has some control over the relative timing of these events and can, therefore, make sure that they occur at the proper time and the nish point F is reached. Timing is controlled using options in the bitstream generation software. XC5200 devices always have the same number of CCLKs in the power up delay, independent of the conguration mode, unlike the XC3000/XC4000 Series devices. To guarantee all devices in a daisy chain have nished the powerup delay, tie the INIT pins together, as shown in Figure 28. XC3000 Master with an XC5200-Series Slave Some designers want to use an XC3000 lead device in peripheral mode and have the I/O pins of the XC5200Series devices all available for user I/O. Figure 23 provides a solution for that case. This solution requires one CLB, one IOB and pin, and an internal oscillator with a frequency of up to 5 MHz as a clock source. The XC3000 master device must be congured with late Internal Reset, which is the default option. One CLB and one IOB in the lead XC3000-family device are used to generate the additional CCLK pulse required by the XC5200-Series devices. When the lead device removes the internal RESET signal, the 2-bit shift register responds to its clock input and generates an active Low output signal for the duration of the subsequent clock period. An external connection between this output and CCLK thus creates the extra CCLK pulse.

Peripheral Modes
The two Peripheral modes accept byte-wide data from a bus. A RDY/BUSY status is available as a handshake signal. In Asynchronous Peripheral mode, the internal oscillator generates a CCLK burst signal that serializes the bytewide data. CCLK can also drive slave devices. In the synchronous mode, an externally supplied clock input to CCLK serializes the data.

Slave Serial Mode

In Slave Serial mode, the FPGA receives serial conguration data on the rising edge of CCLK and, after loading its conguration, passes additional data out, resynchronized on the next falling edge of CCLK. Multiple slave devices with identical congurations can be wired with parallel DIN inputs. In this way, multiple devices can be congured simultaneously. Serial Daisy Chain Multiple devices with different congurations can be connected together in a daisy chain, and a single combined bitstream used to congure the chain of slave devices. To congure a daisy chain of devices, wire the CCLK pins of all devices in parallel, as shown in Figure 29 on page 278. Connect the DOUT of each device to the DIN of the next. The lead or master FPGA and following slaves each passes resynchronized conguration data coming from a single source. The header data, including the length count, is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames. After an FPGA has received its conguration data, it passes on any additional frame start bits and conguration data on DOUT. When the total number of conguration clocks applied after memory initialization equals the value of the 24-bit length count, the FPGAs begin the start-up sequence and become operational together. FPGA I/O are normally released two CCLK cycles after the last conguration bit is received. Figure 26 on page 273 shows the startup timing for an XC5200-Series device. The daisy-chained bitstream is not simply a concatenation of the individual bitstreams. The PROM le formatter must be used to combine the bitstreams for a daisy-chained conguration.

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Pseudo Daisy Chain Multiple devices with different congurations can be connected together in a pseudo daisy chain, provided that all of the devices are in Express mode. A single combined bitstream is used to congure the chain of Express mode devices, but the input data bus must drive D0-D7 of each device. Tie High the CS1 pin of the rst device to be congured, or leave it oating in the XC5200 since it has an internal pull-up. Connect the DOUT pin of each FPGA to the CS1 pin of the next device in the chain. The D0-D7 inputs are wired to each device in parallel. The DONE pins are wired together, with one or more internal DONE pullups activated. Alternatively, a 4.7 k external resistor can be used, if desired. (See Figure 38 on page 286.) CCLK pins are tied together. The requirement that all DONE pins in a daisy chain be wired together applies only to Express mode, and only if all devices in the chain are to become active simultaneously. All devices in Express mode are synchronized to the DONE pin. User I/O for each device become active after the DONE pin for that device goes High. (The exact timing is determined by options to the bitstream generation software.) Since the DONE pin is open-drain and does not drive a High value, tying the DONE pins of all devices together prevents all devices in the chain from going High until the last device in the chain has completed its conguration cycle. The status pin DOUT is pulled LOW two internal-oscillator cycles (nominally 1 MHz) after INIT is recognized as High, and remains Low until the devices conguration memory is full. Then DOUT is pulled High to signal the next device in the chain to accept the conguration data on the D7-D0 bus. All devices receive and recognize the six bytes of preamble and length count, irrespective of the level on CS1; but subsequent frame data is accepted only when CS1 is High and the devices conguration memory is not already full.

OE/T Reset 0 0 1 0 1 1 0 1 0 1 . etc .

Output Connected to CCLK

Active Low Output Active High Output

X5223

Figure 23: CCLK Generation for XC3000 Master Driving an XC5200-Series Slave

Express Mode
Express mode is similar to Slave Serial mode, except the data is presented in parallel format, and is clocked into the target device a byte at a time rather than a bit at a time. The data is loaded in parallel into eight different columns: it is not internally serialized. Eight bits of conguration data are loaded with every CCLK cycle, therefore this conguration mode runs at eight times the data rate of the other six modes. In this mode the XC5200 family is capable of supporting a CCLK frequency of 10 MHz, which is equivalent to an 80 MHz serial rate, because eight bits of conguration data are being loaded per CCLK cycle. An XC5210 in the Express mode, for instance, can be congured in about 2 ms. The Express mode does not support CRC error checking, but does support constant-eld error checking. A length count is not used in Express mode. In the Express conguration mode, an external signal drives the CCLK input(s). The rst byte of parallel conguration data must be available at the D inputs of the FPGA devices a short set-up time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge. See Figure 39 on page 287. Bitstream generation currently generates a bitstream sufcient to program in all conguration modes except Express. Extra CCLK cycles are necessary to complete the conguration, since in this mode data is read at a rate of eight bits per CCLK cycle instead of one bit per cycle. Normally the entire start-up sequence requires a number of bits that is equal to the number of CCLK cycles needed. An additional ve CCLKs (equivalent to 40 extra bits) will guarantee completion of conguration, regardless of the start-up options chosen. Multiple slave devices with identical congurations can be wired with parallel D0-D7 inputs. In this way, multiple devices can be congured simultaneously.

Setting CCLK Frequency

For Master modes, CCLK can be generated in one of three frequencies. In the default slow mode, the frequency is nominally 1 MHz. In fast CCLK mode, the frequency is nominally 12 MHz. In medium CCLK mode, the frequency is nominally 6 MHz. The frequency range is -50% to +50%. The frequency is selected by an option when running the bitstream generation software. If an XC5200-Series Master is driving an XC3000- or XC2000-family slave, slow CCLK mode must be used. Slow mode is the default.

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Table 12: XC5200 Bitstream Format

Data Type Fill Byte Preamble Length Counter Fill Byte Start Byte Data Frame * Cyclic Redundancy Check or Constant Field Check Fill Nibble Extend Write Cycle Postamble Fill Bytes (30) Start-Up Byte Value 11111111 11110010 COUNT(23:0) 11111111 11111110 DATA(N-1:0) CRC(3:0) or 0110 1111 FFFFFF 11111110 FFFFFF FF Occurrences Once per bitstream

Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master modes, CCLK and address signals continue to operate externally. The user must detect INIT and initialize a new conguration by pulsing the PROGRAM pin Low or cycling Vcc.

Once per data frame

Table 13: Internal Conguration Data Structure VersaBlock Array 8x8 10 x 12 14 x 14 18 x 18 22 x 22 PROM Size (bits) 42,416 70,704 106,288 165,488 237,744 Xilinx Serial PROM Needed XC1765D XC17128D XC17128D XC17256D XC17256D

Device XC5202 XC5204 XC5206 XC5210 XC5215

Once per device

Once per bitstream *Bits per Frame (N) depends on device size, as described for table 11.

Data Stream Format

The data stream (bitstream) format is identical for all conguration modes, with the exception of Express mode. In Express mode, the device becomes active when DONE goes High, therefore no length count is required. Additionally, CRC error checking is not supported in Express mode. The data stream formats are shown in Table 12. Express mode data is shown with D0 at the left and D7 at the right. For all other modes, bit-serial data is read from left to right, and byte-parallel data is effectively assembled from this serial bitstream, with the rst bit in each byte assigned to D0. The conguration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator eld of ones (or 24 ll bits, in Express mode). This header is followed by the actual conguration data in frames. The length and number of frames depends on the device type (see Table 13). Each frame begins with a start eld and ends with an error check. In all modes except Express mode, a postamble code is required to signal the end of data for a single device. In all cases, additional start-up bytes of data are required to provide four clocks for the startup sequence at the end of conguration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are dontcares; these bytes are not included in bitstreams created by the Xilinx software. In Express mode, only non-CRC error checking is supported. In all other modes, a selection of CRC or non-CRC error checking is allowed by the bitstream generation software. The non-CRC error checking tests for a designated end-of-frame eld for each frame. For CRC error checking, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each frame. The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. April 8, 1998 (Version 5.0)

Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 ll bits * + 24 extended write bits = (34 x number of Rows) + 100 * In the XC5202 (8 x 8), there are 8 ll bits per frame, not 4 Number of Frames = (12 x number of Columns) + 7 for the left edge + 8 for the right edge + 1 splitter bit = (12 x number of Columns) + 16 Program Data = (Bits per Frame x Number of Frames) + 48 header bits + 8 postamble bits + 240 ll bits + 8 start-up bits = (Bits per Frame x Number of Frames) + 304 PROM Size = Program Data

Cyclic Redundancy Check (CRC) for Conguration and Readback

The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial bitstream. The result of this calculation is tagged onto the data stream as additional check bits. The receiving system performs an identical calculation on the bitstream and compares the result with the received checksum. Each data frame of the conguration bitstream has four error bits at the end, as shown in Table 12. If a frame data error is detected during the loading of the FPGA, the conguration process with a potentially corrupted bitstream is terminated. The FPGA pulls the INIT pin Low and goes into a Wait state. During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is computed using the CRC-16 CCITT polynomial, as shown in Figure 24. The checksum consists of the 11 most significant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLB outputs should not be included (Read Capture option not used). Statistically, one error out of 2048 might go undetected.

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Initialization
X2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X15 X16 15

This phase clears the conguration memory and establishes the conguration mode. The conguration memory is cleared at the rate of one frame per internal clock cycle (nominally 1 MHz). An opendrain bidirectional signal, INIT, is released when the conguration memory is completely cleared. The device then tests for the absence of an external active-low level on INIT. The mode lines are sampled two internal clock cycles later (nominally 2 s). The master device waits an additional 32 s to 256 s (nominally 64-128 s) to provide adequate time for all of the slave devices to recognize the release of INIT as well. Then the master device enters the Conguration phase.

SERIAL DATA IN

Polynomial: X16 + X15 + X2 + 1

1 0 15 14 13 12 11 10 9
START BIT

8 7 6 5

LAST DATA FRAME

CRC CHECKSUM

Readback Data Stream

X1789

Figure 24: Circuit for Generating CRC-16

Conguration Sequence
There are four major steps in the XC5200-Series power-up conguration sequence. Power-On Time-Out Initialization Conguration Start-Up

Boundary Scan Instructions Available:

VCC 3V Yes

No

Generate One Time-Out Pulse of 4 ms

PROGRAM = Low Yes

The full process is illustrated in Figure 25.

Power-On Time-Out
An internal power-on reset circuit is triggered when power is applied. When VCC reaches the voltage at which portions of the FPGA begin to operate (i.e., performs a write-andread test of a sample pair of conguration memory bits), the programmable I/O buffers are 3-stated with active highimpedance pull-up resistors. A time-out delay nominally 4 ms is initiated to allow the power-supply voltage to stabilize. For correct operation the power supply must reach VCC(min) by the end of the time-out, and must not dip below it thereafter. There is no distinction between master and slave modes with regard to the time-out delay. Instead, the INIT line is used to ensure that all daisy-chained devices have completed initialization. Since XC2000 devices do not have this signal, extra care must be taken to guarantee proper operation when daisy-chaining them with XC5200 devices. For proper operation with XC3000 devices, the RESET signal, which is used in XC3000 to delay conguration, should be connected to INIT. If the time-out delay is insufcient, conguration should be delayed by holding the INIT pin Low until the power supply has reached operating levels. This delay is applied only on power-up. It is not applied when reconguring an FPGA by pulsing the PROGRAM pin Low. During all three phases Power-on, Initialization, and Conguration DONE is held Low; HDC, LDC, and INIT are active; DOUT is driven; and all I/O buffers are disabled.

EXTEST* SAMPLE/PRELOAD* BYPASS CONFIGURE*

(*only when PROGRAM = High)

Completely Clear Configuration Memory

~1.3 s per Frame

INIT High? if Master Yes Sample Mode Lines Master CCLK Goes Active after 50 to 250 s

No

Load One Configuration Data Frame

Frame Error No

Yes

Pull INIT Low and Stop

SAMPLE/PRELOAD BYPASS

Configuration memory Full Yes Pass Configuration Data to DOUT

No

CCLK Count Equals Length Count Yes Start-Up Sequence

No

F
EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK Operational I/O Active
X9017

If Boundary Scan is Selected

Figure 25: Conguration Sequence

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LDC Output = L, HDC Output = H

Length Count Match

CCLK Period

CCLK
F DONE

XC2000

I/O

Global Reset F F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing Global Reset F DONE C1 C2 C3 C4 I/O C2 GSR Active C2 DONE IN F DONE C1, C2 or C3 I/O C3 C4 C3 C4

XC3000

DONE I/O

XC4000E/EX XC5200/
CCLK_NOSYNC

XC4000E/EX XC5200/
CCLK_SYNC

Di
GSR Active

Di+1

Di

Di+1
F

DONE C1 U2 U3 U4 I/O U2 GSR Active U2 DONE IN F DONE C1 U2 I/O U3 U4 U3 U4

XC4000E/EX XC5200/
UCLK_NOSYNC

XC4000E/EX XC5200/
UCLK_SYNC

Di
GSR Active

Di+1

Di+2

Synchronization Uncertainty

Di

Di+1

Di+2

UCLK Period
X6700

Figure 26: Start-up Timing

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Conguration
The length counter begins counting immediately upon entry into the conguration state. In slave-mode operation it is important to wait at least two cycles of the internal 1-MHz clock oscillator after INIT is recognized before toggling CCLK and feeding the serial bitstream. Conguration will not begin until the internal conguration logic reset is released, which happens two cycles after INIT goes High. A master devices conguration is delayed from 32 to 256 s to ensure proper operation with any slave devices driven by the master device. The 0010 preamble code, included for all modes except Express mode, indicates that the following 24 bits represent the length count. The length count is the total number of conguration clocks needed to load the complete conguration data. (Four additional conguration clocks are required to complete the conguration process, as discussed below.) After the preamble and the length count have been passed through to all devices in the daisy chain, DOUT is held High to prevent frame start bits from reaching any daisy-chained devices. In Express mode, the length count bits are ignored, and DOUT is held Low, to disable the next device in the pseudo daisy chain. A specic conguration bit, early in the rst frame of a master device, controls the conguration-clock rate and can increase it by a factor of eight. Therefore, if a fast conguration clock is selected by the bitstream, the slower clock rate is used until this conguration bit is detected. Each frame has a start eld followed by the frame-conguration data bits and a frame error eld. If a frame data error is detected, the FPGA halts loading, and signals the error by pulling the open-drain INIT pin Low. After all conguration frames have been loaded into an FPGA, DOUT again follows the input data so that the remaining data is passed on to the next device. In Express mode, when the rst device is fully programmed, DOUT goes High to enable the next device in the chain.

Start-Up
Start-up is the transition from the conguration process to the intended user operation. This transition involves a change from one clock source to another, and a change from interfacing parallel or serial conguration data where most outputs are 3-stated, to normal operation with I/O pins active in the user-system. Start-up must make sure that the user-logic wakes up gracefully, that the outputs become active without causing contention with the conguration signals, and that the internal ip-ops are released from the global Reset at the right time. Figure 26 describes start-up timing for the three Xilinx families in detail. Express mode conguration always uses either CCLK_SYNC or UCLK_SYNC timing, the other conguration modes can use any of the four timing sequences. To access the internal start-up signals, place the STARTUP library symbol. Start-up Timing Different FPGA families have different start-up sequences. The XC2000 family goes through a xed sequence. DONE goes High and the internal global Reset is de-activated one CCLK period after the I/O become active. The XC3000A family offers some exibility. DONE can be programmed to go High one CCLK period before or after the I/O become active. Independent of DONE, the internal global Reset is de-activated one CCLK period before or after the I/O become active. The XC4000/XC5200 Series offers additional exibility. The three events DONE going High, the internal Reset being de-activated, and the user I/O going active can all occur in any arbitrary sequence. Each of them can occur one CCLK period before or after, or simultaneous with, any of the others. This relative timing is selected by means of software options in the bitstream generation software. The default option, and the most practical one, is for DONE to go High rst, disconnecting the conguration data source and avoiding any contention when the I/Os become active one clock later. Reset is then released another clock period later to make sure that user-operation starts from stable internal conditions. This is the most common sequence, shown with heavy lines in Figure 26, but the designer can modify it to meet particular requirements. Normally, the start-up sequence is controlled by the internal device oscillator output (CCLK), which is asynchronous to the system clock. XC4000/XC5200 Series offers another start-up clocking option, UCLK_NOSYNC. The three events described above need not be triggered by CCLK. They can, as a conguration option, be triggered by a user clock. This means that the device can wake up in synchronism with the user system.

Delaying Conguration After Power-Up

To delay master mode conguration after power-up, pull the bidirectional INIT pin Low, using an open-collector (opendrain) driver. (See Figure 13.) Using an open-collector or open-drain driver to hold INIT Low before the beginning of master mode conguration causes the FPGA to wait after completing the conguration memory clear operation. When INIT is no longer held Low externally, the device determines its conguration mode by capturing its mode pins, and is ready to start the conguration process. A master device waits up to an additional 250 s to make sure that any slaves in the optional daisy chain have seen that INIT is High.

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When the UCLK_SYNC option is enabled, the user can externally hold the open-drain DONE output Low, and thus stall all further progress in the start-up sequence until DONE is released and has gone High. This option can be used to force synchronization of several FPGAs to a common user clock, or to guarantee that all devices are successfully congured before any I/Os go active. If either of these two options is selected, and no user clock is specied in the design or attached to the device, the chip could reach a point where the conguration of the device is complete and the Done pin is asserted, but the outputs do not become active. The solution is either to recreate the bitstream specifying the start-up clock as CCLK, or to supply the appropriate user clock. Start-up Sequence The Start-up sequence begins when the conguration memory is full, and the total number of conguration clocks received since INIT went High equals the loaded value of the length count. The next rising clock edge sets a ip-op Q0, shown in Figure 27. Q0 is the leading bit of a 5-bit shift register. The outputs of this register can be programmed to control three events. The release of the open-drain DONE output The change of conguration-related pins to the user function, activating all IOBs. The termination of the global Set/Reset initialization of all CLB and IOB storage elements. The DONE pin can also be wire-ANDed with DONE pins of other FPGAs or with other external signals, and can then be used as input to bit Q3 of the start-up register. This is called Start-up Timing Synchronous to Done In and is selected by either CCLK_SYNC or UCLK_SYNC. When DONE is not used as an input, the operation is called Start-up Timing Not Synchronous to DONE In, and is selected by either CCLK_NOSYNC or UCLK_NOSYNC. As a conguration option, the start-up control register beyond Q0 can be clocked either by subsequent CCLK pulses or from an on-chip user net called STARTUP.CLK. These signals can be accessed by placing the STARTUP library symbol. Start-up from CCLK If CCLK is used to drive the start-up, Q0 through Q3 provide the timing. Heavy lines in Figure 26 show the default timing, which is compatible with XC2000 and XC3000 devices using early DONE and late Reset. The thin lines indicate all other possible timing options. Start-up from a User Clock (STARTUP.CLK) When, instead of CCLK, a user-supplied start-up clock is selected, Q1 is used to bridge the unknown phase relation-

ship between CCLK and the user clock. This arbitration causes an unavoidable one-cycle uncertainty in the timing of the rest of the start-up sequence.

DONE Goes High to Signal End of Conguration

In all conguration modes except Express mode, XC5200Series devices read the expected length count from the bitstream and store it in an internal register. The length count varies according to the number of devices and the composition of the daisy chain. Each device also counts the number of CCLKs during conguration. Two conditions have to be met in order for the DONE pin to go high: the chip's internal memory must be full, and the conguration length count must be met, exactly.

This is important because the counter that determines when the length count is met begins with the very rst CCLK, not the rst one after the preamble. Therefore, if a stray bit is inserted before the preamble, or the data source is not ready at the time of the rst CCLK, the internal counter that holds the number of CCLKs will be one ahead of the actual number of data bits read. At the end of conguration, the conguration memory will be full, but the number of bits in the internal counter will not match the expected length count. As a consequence, a Master mode device will continue to send out CCLKs until the internal counter turns over to zero, and then reaches the correct length count a second time. This will take several seconds [224 CCLK period] which is sometimes interpreted as the device not conguring at all. If it is not possible to have the data ready at the time of the rst CCLK, the problem can be avoided by increasing the number in the length count by the appropriate value. In Express mode, there is no length count. The DONE pin for each device goes High when the device has received its quota of conguration data. Wiring the DONE pins of several devices together delays start-up of all devices until all are fully congured. Note that DONE is an open-drain output and does not go High unless an internal pull-up is activated or an external pull-up is attached. The internal pull-up is activated as the default by the bitstream generation software.

Release of User I/O After DONE Goes High

By default, the user I/O are released one CCLK cycle after the DONE pin goes High. If CCLK is not clocked after DONE goes High, the outputs remain in their initial state 3-stated, with a 20 k - 100 k pull-up. The delay from DONE High to active user I/O is controlled by an option to the bitstream generation software.

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Q3 STARTUP Q2

Q1/Q4 DONE IN

* *
1 0 GR ENABLE GR INVERT STARTUP.GR STARTUP.GTS GTS INVERT GTS ENABLE 0

IOBs OPERATIONAL PER CONFIGURATION

GLOBAL RESET OF ALL CLB FLIP-FLOPS/LATCHES

CONTROLLED BY STARTUP SYMBOL IN THE USER SCHEMATIC (SEE LIBRARIES GUIDE)

GLOBAL 3-STATE OF ALL IOBs 1

*
1 0 1 0

DONE " FINISHED " ENABLES BOUNDARY SCAN, READBACK AND CONTROLS THE OSCILLATOR

Q0

Q1

Q2

Q3

Q4

FULL LENGTH COUNT

1 S Q D Q D Q 0 M K K K D Q D Q

CLEAR MEMORY CCLK STARTUP.CLK USER NET 0 1

*
Figure 27: Start-up Logic

CONFIGURATION BIT OPTIONS SELECTED BY USER

X9002

Release of Global Reset After DONE Goes High

By default, Global Reset (GR) is released two CCLK cycles after the DONE pin goes High. If CCLK is not clocked twice after DONE goes High, all ip-ops are held in their initial reset state. The delay from DONE High to GR inactive is controlled by an option to the bitstream generation software.

For detailed information, refer to the Xilinx application note XAPP017, Boundary Scan in XC4000 and XC5200 Devices.

Readback
The user can read back the content of conguration memory and the level of certain internal nodes without interfering with the normal operation of the device. Readback not only reports the downloaded conguration bits, but can also include the present state of the device, represented by the content of all ip-ops and latches in CLBs. Note that in XC5200-Series devices, conguration data is not inverted with respect to conguration as it is in XC2000 and XC3000 families. Readback of Express mode bitstreams results in data that does not resemble the original bitstream, because the bitstream format differs from other modes.

Conguration Complete After DONE Goes High

Three full CCLK cycles are required after the DONE pin goes High, as shown in Figure 26 on page 273. If CCLK is not clocked three times after DONE goes High, readback cannot be initiated and most boundary scan instructions cannot be used.

Conguration Through the Boundary Scan Pins

XC5200-Series devices can be congured through the boundary scan pins.

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XC5200-Series Readback does not use any dedicated pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be routed to any IOB. To access the internal Readback signals, place the READBACK library symbol and attach the appropriate pad symbols, as shown in Figure 28. After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress) output goes High on the next rising edge of RDBK.CLK. Subsequent rising edges of this clock shift out Readback data on the RDBK.DATA net. Readback data does not include the preamble, but starts with ve dummy bits (all High) followed by the Start bit (Low) of the rst frame. The rst two data bits of the rst frame are always High. Each frame ends with four error check bits. They are read back as High. The last seven bits of the last frame are also read back as High. An additional Start bit (Low) and an 11-bit Cyclic Redundancy Check (CRC) signature follow, before RDBK.RIP returns Low.
IF UNCONNECTED, DEFAULT IS CCLK

Read Abort
When the Read Abort option is selected, a High-to-Low transition on RDBK.TRIG terminates the readback operation and prepares the logic to accept another trigger. After an aborted readback, additional clocks (up to one readback clock per conguration frame) may be required to re-initialize the control logic. The status of readback is indicated by the output control net RDBK.RIP. RDBK.RIP is High whenever a readback is in progress.

Clock Select
CCLK is the default clock. However, the user can insert another clock on RDBK.CLK. Readback control and data are clocked on rising edges of RDBK.CLK. If readback must be inhibited for security reasons, the readback control nets are simply not connected.

Violating the Maximum High and Low Time Specication for the Readback Clock
The readback clock has a maximum High and Low time specication. In some cases, this specication cannot be met. For example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. This necessitates stopping the clock, and thus violating the specication. The specication is mandatory only on clocking data at the end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the source of the maximum High and Low time requirements. Therefore, the specication only applies to the six clock cycles prior to and including any start bit, including the clocks before the rst start bit in the readback data stream. At other times, the frame data is already in the register and the register is not dynamic. Thus, it can be shifted out just like a regular shift register. The user must precisely calculate the location of the readback data relative to the frame. The system must keep track of the position within a data frame, and disable interrupts before frame boundaries. Frame lengths and data formats are listed in Table 12 and Table 13.

CLK MD0 READ_TRIGGER IBUF TRIG READBACK

DATA RIP OBUF

READ_DATA

MD1

X1786

Figure 28: Readback Schematic Example

Readback Options
Readback options are: Read Capture, Read Abort, and Clock Select. They are set with the bitstream generation software.

Read Capture
When the Read Capture option is selected, the readback data stream includes sampled values of CLB and IOB signals. The rising edge of RDBK.TRIG latches the inverted values of the CLB outputs and the IOB output and input signals. Note that while the bits describing conguration (interconnect and function generators) are not inverted, the CLB and IOB output signals are inverted. When the Read Capture option is not selected, the values of the capture bits reect the conguration data originally written to those memory locations. The readback signals are located in the lower-left corner of the device.

Readback with the XChecker Cable

The XChecker Universal Download/Readback Cable and Logic Probe uses the readback feature for bitstream verication. It can also display selected internal signals on the PC or workstation screen, functioning as a low-cost in-circuit emulator.

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XC5200 Series Field Programmable Gate Arrays

Conguration Timing
The seven conguration modes are discussed in detail in this section. Timing specications are included.

There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. Figure 29 shows a full master/slave system. An XC5200Series device in Slave Serial mode should be connected as shown in the third device from the left. Slave Serial mode is selected by a <111> on the mode pins (M2, M1, M0). Slave Serial is the default mode if the mode pins are left unconnected, as they have weak pull-up resistors during conguration.

Slave Serial Mode

In Slave Serial mode, an external signal drives the CCLK input of the FPGA. The serial conguration bitstream must be available at the DIN input of the lead FPGA a short setup time before each rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overows the lead deviceon its DOUT pin.

NOTE: M2, M1, M0 can be shorted to Ground if not used as I/O VCC 4.7 K 4.7 K N/C 4.7 K N/C DOUT XC5200 MASTER SERIAL CCLK DIN PROGRAM DONE LDC INIT VCC XC1700D 4.7 K CLK DATA VPP +5 V M0 M1 M2 DIN CCLK XC4000E/EX, XC5200 SLAVE PROGRAM DONE DOUT 4.7 K

NOTE: M2, M1, M0 can be shorted to VCC if not used as I/O

4.7 K

4.7 K

M0 M1 M2

M0 M1 PWRDN M2 DIN CCLK XC3100A SLAVE DOUT

CEO CE RESET/OE (Low Reset Option Used)

INIT

RESET D/P

INIT

PROGRAM

X9003

Figure 29: Master/Slave Serial Mode Circuit Diagram

DIN 1 TDCC CCLK

Bit n 2 TCCD

Bit n + 1 5 TCCL

4 TCCH DOUT (Output) Bit n - 1

3 TCCO Bit n
X5379

CCLK

Description DIN setup DIN hold DIN to DOUT High time Low time Frequency

1 2 3 4 5

Symbol TDCC TCCD TCCO TCCH TCCL FCC

Min 20 0 45 45

Max

30

10

Units ns ns ns ns ns MHz

Note:

Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

Figure 30: Slave Serial Mode Programming Switching Characteristics

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Master Serial Mode

In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. The next data bit is put on the SPROM data output, connected to the FPGA DIN pin. The lead FPGA accepts this data on the subsequent rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overows the lead deviceon its DOUT pin. There is an internal pipeline delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In the bitstream generation software, the user can specify Fast CongRate, which, starting several bits into the rst frame, increases the CCLK frequency by a factor of twelve.

The value increases from a nominal 1 MHz, to a nominal 12 MHz. Be sure that the serial PROM and slaves are fast enough to support this data rate. The Medium CongRate option changes the frequency to a nominal 6 MHz. XC2000, XC3000/A, and XC3100A devices do not support the Fast or Medium CongRate options. The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is congured as user-I/O, but LDC is then restricted to be a permanently High user output after conguration. Using DONE can also avoid contention on DIN, provided the early DONE option is invoked. Figure 29 on page 278 shows a full master/slave system. The leftmost device is in Master Serial mode. Master Serial mode is selected by a <000> on the mode pins (M2, M1, M0).

CCLK (Output) 2 TCKDS 1 Serial Data In TDSCK n n+1 n+2

Serial DOUT (Output)

n3

n2

n1

n
X3223

CCLK

Description DIN setup DIN hold

1 2

Symbol TDSCK TCKDS

Min 20 0

Max

Units ns ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conguration by pulling PROGRAM Low until Vcc is valid. 2. Master Serial mode timing is based on testing in slave mode.

Figure 31: Master Serial Mode Programming Switching Characteristics

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Master Parallel Modes

In the two Master Parallel modes, the lead FPGA directly addresses an industry-standard byte-wide EPROM, and accepts eight data bits just before incrementing or decrementing the address outputs. The eight data bits are serialized in the lead FPGA, which then presents the preamble dataand all data that overows the lead deviceon its DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data (and also changes the EPROM address) until the falling CCLK edge that makes the LSB (D0) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge.

The PROM address pins can be incremented or decremented, depending on the mode pin settings. This option allows the FPGA to share the PROM with a wide variety of microprocessors and microcontrollers. Some processors must boot from the bottom of memory (all zeros) while others must boot from the top. The FPGA is exible and can load its conguration bitstream from either end of the memory. Master Parallel Up mode is selected by a <100> on the mode pins (M2, M1, M0). The EPROM addresses start at 00000 and increment. Master Parallel Down mode is selected by a <110> on the mode pins. The EPROM addresses start at 3FFFF and decrement.

4.7K

HIGH or LOW

TO DIN OF OPTIONAL DAISY-CHAINED FPGAS N/C N/C TO CCLK OF OPTIONAL DAISY-CHAINED FPGAS

M0

M1

M2 CCLK

NOTE:M0 can be shorted to Ground if not used as I/O. VCC 4.7K

DOUT A17 A16 A15 A14 INIT A13 A12 A11 A10 PROGRAM D7 D6 D5 D4 D3 D2 D1 D0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DONE ... ... ... ... ... A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OE CE D7 D6 D5 D4 D3 D2 D1 D0 DONE INIT EPROM (8K x 8) (OR LARGER) USER CONTROL OF HIGHER ORDER PROM ADDRESS BITS CAN BE USED TO SELECT BETWEEN ALTERNATIVE CONFIGURATIONS M0 DIN M1 M2 DOUT

CCLK XC5200/ XC4000E/EX SLAVE PROGRAM

DATA BUS PROGRAM

X9004

Figure 32: Master Parallel Mode Circuit Diagram

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.
A0-A17 (output) Address for Byte n Address for Byte n + 1 1 TRAC D0-D7 Byte 2 TDRC RCLK (output) 7 CCLKs CCLK 3 TRCD

CCLK (output)

DOUT (output)

D6 Byte n - 1

D7
X6078

CCLK
Note:

Description Delay to Address valid Data setup time Data hold time

1 2 3

Symbol TRAC TDRC TRCD

Min 0 60 0

Max 200

Units ns ns ns

1. At power-up, VCC must rise from 2.0 V to VCC min in less then 25 ms, otherwise delay conguration by pulling PROGRAM Low until VCC is Valid. 2. The rst Data byte is loaded and CCLK starts at the end of the rst RCLK active cycle (rising edge).

This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than 500 ns. EPROM data output has no hold-time requirements. Figure 33: Master Parallel Mode Programming Switching Characteristics

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Synchronous Peripheral Mode

Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The rst byte of parallel conguration data must be available at the Data inputs of the lead FPGA a short setup time before the rising CCLK edge. Subsequent data bytes are clocked in on every eighth consecutive rising CCLK edge. The same CCLK edge that accepts data, also causes the RDY/BUSY output to go High for one CCLK period. The pin name is a misnomer. In Synchronous Peripheral mode it is really an ACKNOWLEDGE signal. Synchronous operation does not require this response, but it is a meaningful signal

for test purposes. Note that RDY/BUSY is pulled High with a high-impedance pullup prior to INIT going High. The lead FPGA serializes the data and presents the preamble data (and all data that overows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In order to complete the serial shift operation, 10 additional CCLK rising edges are required after the last data byte has been loaded, plus one more CCLK cycle for each daisychained device. Synchronous Peripheral mode is selected by a <011> on the mode pins (M2, M1, M0).

NOTE: M2 can be shorted to Ground if not used as I/O

N/C 4.7 k N/C

M0 M1
CLOCK CCLK

M2 OPTIONAL DAISY-CHAINED FPGAs DOUT

M0 M1 CCLK

M2

DATA BUS

8 D0-7

DIN

DOUT

VCC
4.7 k

XC5200 SYNCHRONOUS PERIPHERAL

XC5200 SLAVE

CONTROL SIGNALS 4.7 k PROGRAM

RDY/BUSY INIT DONE INIT DONE

PROGRAM

PROGRAM

X9005

Figure 34: Synchronous Peripheral Mode Circuit Diagram

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CCLK

INIT
BYTE 0 BYTE 1

BYTE 0 OUT DOUT 0 1 2 3 4 5 6 7

BYTE 1 OUT 0 1

RDY/BUSY
X6096

CCLK

Description INIT (High) setup time D0 - D7 setup time D0 - D7 hold time CCLK High time CCLK Low time CCLK Frequency

1 2 3

Symbol TIC TDC TCD TCCH TCCL FCC

Min 5 60 0 50 60

Max

Units s ns ns ns ns MHz

Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the rst data byte on the second rising edge of CCLK after INIT goes high. Subsequent data bytes are clocked in on every eighth consecutive rising edge of CCLK. 2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does not require such a response. 3. The pin name RDY/BUSY is a misnomer. In synchronous peripheral mode this is really an ACKNOWLEDGE signal. 4.Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore, additional CCLK pulses are clearly required after the last byte has been loaded.

Figure 35: Synchronous Peripheral Mode Programming Switching Characteristics

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Asynchronous Peripheral Mode

Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CS0 being Low and RS and CS1 being High to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a double-buffered UART-like parallel-to-serial converter and is serially shifted into the internal logic. The lead FPGA presents the preamble data (and all data that overows the lead device) on its DOUT pin. The RDY/ BUSY output from the lead FPGA acts as a handshake signal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High again when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. A new write may be started immediately, as soon as the RDY/BUSY output has gone Low, acknowledging receipt of the previous data. Write may not be terminated until RDY/BUSY is High again for one CCLK period. Note that RDY/BUSY is pulled High with a high-impedance pullup prior to INIT going High. The length of the BUSY signal depends on the activity in the UART. If the shift register was empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered.
N/C
4.7 k

The READY/BUSY handshake can be ignored if the delay from any one Write to the end of the next Write is guaranteed to be longer than 10 CCLK periods.

Status Read
The logic AND condition of the CS0, CS1 and RS inputs puts the device status on the Data bus. D7 High indicates Ready D7 Low indicates Busy D0 through D6 go unconditionally High

It is mandatory that the whole start-up sequence be started and completed by one byte-wide input. Otherwise, the pins used as Write Strobe or Chip Enable might become active outputs and interfere with the nal byte transfer. If this transfer does not occur, the start-up sequence is not completed all the way to the nish (point F in Figure 26 on page 273). In this case, at worst, the internal reset is not released. At best, Readback and Boundary Scan are inhibited. The length-count value, as generated by the XACTstep software, ensures that these problems never occur. Although RDY/BUSY is brought out as a separate signal, microprocessors can more easily read this information on one of the data lines. For this purpose, D7 represents the RDY/BUSY status when RS is Low, WS is High, and the two chip select lines are both active. Asynchronous Peripheral mode is selected by a <101> on the mode pins (M2, M1, M0).

N/C N/C

M0

M1

M2

M0

M1

M2

DATA BUS

D07

CCLK OPTIONAL DAISY-CHAINED FPGAs DOUT

CCLK

DIN

DOUT

VCC
ADDRESS BUS

ADDRESS DECODE LOGIC

CS0

4.7 k

4.7 k

XC5200 ASYNCHRONOUS PERIPHERAL

...

CS1 RS WS

XC5200/ XC4000E/EX SLAVE

CONTROL SIGNALS

RDY/BUSY INIT DONE REPROGRAM

4.7 k

INIT DONE PROGRAM

PROGRAM

X9006

Figure 36:

Asynchronous Peripheral Mode Circuit Diagram

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Write to LCA WS/CS0

Read Status RS, CS0

RS, CS1

WS, CS1

TCA 2 3 TDC TCD 7

READY BUSY

4
D7

D0-D7

CCLK

TWTRB 4
RDY/BUSY

TBUSY

DOUT

Previous Byte D6

D7

D0

D1

D2
X6097

Write

RDY

Description Effective Write time (CSO, WS=Low; RS, CS1=High DIN setup time DIN hold time RDY/BUSY delay after end of Write or Read RDY/BUSY active after beginning of Read RDY/BUSY Low output (Note 4)

1 2 3 4 7 6

Symbol TCA TDC TCD TWTRB

Min 100 60 0

Max

Units ns ns ns ns ns CCLK periods

60 60

TBUSY

Notes: 1. Conguration must be delayed until INIT pins of all daisy-chained FPGAs are high. 2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing and the phase of internal timing generator for CCLK. 3. CCLK and DOUT timing is tested in slave mode. 4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data.

This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write may not be terminated until RDY/BUSY has been High for one CCLK period. Figure 37: Asynchronous Peripheral Mode Programming Switching Characteristics

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XC5200 Series Field Programmable Gate Arrays

Express Mode
Express mode is similar to Slave Serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive CCLK, while byte-wide data is loaded directly into the conguration data shift registers. A CCLK frequency of 10 MHz is equivalent to an 80 MHz serial rate, because eight bits of conguration data are loaded per CCLK cycle. Express mode does not support CRC error checking, but does support constant-eld error checking. In Express mode, an external signal drives the CCLK input of the FPGA device. The rst byte of parallel conguration data must be available at the D inputs of the FPGA a short setup time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge. Express mode is only supported by the XC4000EX and XC5200 families. It may not be used, therefore, when an XC4000EX or XC5200 device is daisy-chained with devices from other Xilinx families. If the rst device is congured in Express mode, additional devices may be daisy-chained only if every device in the chain is also congured in Express mode. CCLK pins are tied together and D0-D7 pins are tied together for all devices along the chain. A status signal is passed from DOUT to CS1 of successive devices along the chain. The lead device in the chain has its CS1 input tied High (or oating, since there is an internal pullup). Frame data is accepted only when CS1 is High and the devices congu-

ration memory is not already full. The status pin DOUT is pulled Low two internal-oscillator cycles after INIT is recognized as High, and remains Low until the devices conguration memory is full. DOUT is then pulled High to signal the next device in the chain to accept the conguration data on the D0-D7 bus. The DONE pins of all devices in the chain should be tied together, with one or more active internal pull-ups. If a large number of devices are included in the chain, deactivate some of the internal pull-ups, since the Low-driving DONE pin of the last device in the chain must sink the current from all pull-ups in the chain. The DONE pull-up is activated by default. It can be deactivated using an option in the bitstream generation software. XC5200 devices in Express mode are always synchronized to DONE. The device becomes active after DONE goes High. DONE is an open-drain output. With the DONE pins tied together, therefore, the external DONE signal stays low until all devices are congured, then all devices in the daisy chain become active simultaneously. If the DONE pin of a device is left unconnected, the device becomes active as soon as that device has been congured. XC4000EX devices in the chain should be congured as synchronized to DONE (either CCLK_SYNC or UCLK_SYNC), and their DONE pins wired together with those of the XC5200 devices. Express mode is selected by a <010> on the mode pins (M2, M1, M0).

VCC NOTE: M2, M1, M0 can be shorted to Ground if not used as I/O 4.7K 8 To Additional Optional Daisy-Chained Devices

M0

M1

M2

M0

M1

M2

CS1 DATA BUS 8 VCC XC4000EX/ XC5200 4.7K PROGRAM INIT PROGRAM INIT CCLK D0-D7

DOUT 8

CS1 D0-D7

DOUT

Optional Daisy-Chained XC4000EX/ XC5200

PROGRAM DONE INIT CCLK DONE

CCLK

To Additional Optional Daisy-Chained Devices

X6611

Figure 38: Express Mode Circuit Diagram

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CCLK 1 TIC

INIT TCD 3 2 T DC D0-D7

BYTE 0 BYTE 1 BYTE 2 BYTE 3

Serial Data Out (DOUT) FPGA Filled Internal INIT

RDY/BUSY

CS1

X5087

CCLK

Description INIT (High) Setup time required DIN Setup time required DIN hold time required CCLK High time CCLK Low time CCLK frequency

1 2 3

Symbol TIC TDC TCD TCCH TCCL FCC

Min 5 30 0 30 30

Max

10

Units s ns ns ns ns MHz

Note: If not driven by the preceding DOUT, CS1 must remain high until the device is fully congured.

Figure 39: Express Mode Programming Switching Characteristics

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XC5200 Series Field Programmable Gate Arrays

Table 14.
SLAVE <1:1:1>

Pin Functions During Conguration

CONFIGURATION MODE: <M2:M1:M0> MASTER-SER <0:0:0> SYN.PERIPH <0:1:1> ASYN.PERIPH MASTER-HIGH MASTER-LOW <1:0:1> <1:1:0> <1:0:0> A16 A17 TDI TCK TMS M1 (HIGH) (I) M0 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK (O) TDO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 TDI TCK TMS M1 (LOW) (I) M0 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK (O) TDO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 EXPRESS <0:1:0> USER OPERATION GCK1-I/O I/O TDI-I/O TCK-I/O TMS-I/O I/O I/O I/O I/O GCK2-I/O I/O I/O I/O I/O DONE PROGRAM I/O GCK3-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CCLK (I) TDO-I/O I/O GCK4-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ALL OTHERS

TDI TCK TMS M1 (HIGH) (I) M0 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I)

TDI TCK TMS M1 (LOW) (I) M0 (LOW) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I)

TDI TCK TMS M1 (HIGH) (I) M0 (HIGH) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) RDY/BUSY DATA 0 (I) DOUT CCLK (I) TDO

TDI TCK TMS M1 (LOW) (I) M0 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) CSO (I) DATA 4 (I) DATA 3 (I) RS (I) DATA 2 (I) DATA 1 (I) RDY/BUSY DATA 0 (I) DOUT CCLK (O) TDO WS (I) CS1 (I)

TDI TCK TMS M1 (HIGH) (I) M0 (LOW) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) DATA 0 (I) DOUT CCLK (I) TDO

DIN (I) DOUT CCLK (I) TDO

DIN (I) DOUT CCLK (O) TDO

CS1 (I)

Notes 1. A shaded table cell represents a 20-k to 100-k pull-up resistor before and during conguration. 2. (I) represents an input (O) represents an output. 3. INIT is an open-drain output during conguration.

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Conguration Switching Characteristics

Vcc T POR RE-PROGRAM >300 ns PROGRAM T PI INIT T ICCK CCLK OUTPUT or INPUT <300 ns M0, M1, M2 (Required) X1532 I/O VALID DONE RESPONSE <300 ns TCCLK

Master Modes
Description Power-On-Reset Program Latency CCLK (output) Delay period (slow) period (fast) Symbol TPOR TPI TICCK TCCLK TCCLK Min 2 6 40 640 100 Max 15 70 375 3000 375 Units ms s per CLB column s ns ns

Slave and Peripheral Modes

Description Symbol Min Max Units Power-On-Reset TPOR 2 15 ms Program Latency TPI 6 70 s per CLB column CCLK (input) Delay (required) TICCK 5 s period (required) TCCLK 100 ns At power-up, VCC must rise from 2.0 to VCC min in less than 15 ms, otherwise delay conguration using PROGRAM until Note:
VCC is valid.

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XC5200 Program Readback Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. The following guidelines reect worst-case values over the recommended operating conditions.

Finished Internal Net

3 T RTL

rdbk.TRIG
T RTRC T RCRT 2

rdclk.I
4 T RCL T RCH 5

rdbk.RIP
6 T RCRR

rdbk.DATA

DUMMY
T RCRD

DUMMY

VALID

VALID

7 X1790

rdbk.TRIG rdclk.1

Description rdbk.TRIG setup to initiate and abort Readback rdbk.TRIG hold to initiate and abort Readback rdbk.DATA delay rdbk.RIP delay High time Low time

1 2 7 6 5 4

Symbol TRTRC TRCRT TRCRD TRCRR TRCH TRCL

Min 200 50 250 250

Max 250 250 500 500

Units ns ns ns ns ns ns

Note 1: Timing parameters apply to all speed grades. Note 2: rdbk.TRIG is High prior to Finished, Finished will trigger the rst Readback

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XC5200 Switching Characteristics

Denition of Terms
In the following tables, some specications may be designated as Advance or Preliminary. These terms are dened as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specications not identied as either Advance or Preliminary are to be considered Final.1

XC5200 Operating Conditions

Symbol Description VCC Supply voltage relative to GND Commercial:0C to 85C junction Supply voltage relative to GND Industrial:-40C to 100C junction VIHT High-level input voltage TTL configuration VILT Low-level input voltage TTL configuration VIHC High-level input voltage CMOS configuration VILC Low-level input voltage CMOS configuration TIN Input signal transition time Min 4.75 4.5 2.0 0 70% 0 Max 5.25 5.5 VCC 0.8 100% 20% 250 Units V V V V VCC VCC ns

XC5200 DC Characteristics Over Operating Conditions

Symbol VOH VOL ICCO IIL CIN IRIN
Note:

Description High-level output voltage @ IOH = -8.0 mA, VCC min Low-level output voltage @ IOL = 8.0 mA, VCC max Quiescent FPGA supply current (Note 1) Leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested)

Min 3.86

Max 0.4 15 +10 15 0.30

-10 0.02

Units V V mA A pF mA

1. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS inputs, and the FPGA congured with a tie option.

XC5200 Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature in plastic packages Junction temperature in ceramic packages -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

1. Notwithstanding the denition of the above terms, all specications are subject to change without notice.

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XC5200 Series Field Programmable Gate Arrays

XC5200 Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Speed Grade Description Global Signal Distribution From pad through global buffer, to any clock (CK) Symbol TBUFG Device XC5202 XC5204 XC5206 XC5210 XC5215 -6 Max (ns) 9.1 9.3 9.4 9.4 10.5 -5 Max (ns) 8.5 8.7 8.8 8.8 9.9 -4 Max (ns) 8.0 8.2 8.3 8.5 9.8 -3 Max (ns) 6.9 7.6 7.7 7.7 9.6

PRELIMINARY

XC5200 Longline Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Speed Grade Description TBUF driving a Longline TS I O TBUF I to Longline, while TS is Low; i.e., buffer is constantly active TS going Low to Longline going from floating High or Low to active Low or High Symbol TIO Device XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC52xx -6 Max (ns) 6.0 6.4 6.6 6.6 7.3 7.8 8.3 8.4 8.4 8.9 3.0 -5 Max (ns) 3.8 4.1 4.2 4.2 4.6 5.6 5.9 6.0 6.0 6.3 2.8 -4 Max (ns) 3.0 3.2 3.3 3.3 3.8 4.7 4.9 5.0 5.0 5.3 2.6 -3 Max (ns) 2.0 2.3 2.7 2.9 3.2 4.0 4.3 4.4 4.4 4.5 2.4

TON

TS going High to TBUF going inactive, not driving Longline

TOFF

PRELIMINARY

Note: 1. Die-size-dependent parameters are based upon XC5215 characterization. Production specications will vary with array
size.

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XC5200 CLB Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Speed Grade Description Combinatorial Delays F inputs to X output F inputs via transparent latch to Q DI inputs to DO output (Logic-Cell Feedthrough) F inputs via F5_MUX to DO output Carry Delays Incremental delay per bit Carry-in overhead from DI Carry-in overhead from F Carry-out overhead to DO Sequential Delays Clock (CK) to out (Q) (Flip-Flop) Gate (Latch enable) going active to out (Q) Set-up Time Before Clock (CK) F inputs F inputs via F5_MUX DI input CE input Hold Times After Clock (CK) F inputs F inputs via F5_MUX DI input CE input Clock Widths Clock High Time Clock Low Time Toggle Frequency (MHz) (Note 3) Reset Delays Width (High) Delay from CLR to Q (Flip-Flop) Delay from CLR to Q (Latch) Global Reset Delays Width (High) Delay from internal GR to Q Symbol Min (ns) -6 Max (ns) 5.6 8.0 4.3 7.2 0.7 1.8 3.7 4.0 5.8 9.2 2.3 3.8 0.8 1.6 0 0 0 0 6.0 6.0 83 6.0 7.7 6.5 6.0 14.7 6.0 12.1 6.0 6.3 5.2 6.0 9.1
PRELIMINARY

-5 Min (ns) Max (ns) 4.6 6.6 3.5 5.8 0.6 1.6 3.2 3.2 4.9 7.4 1.8 3.0 0.5 1.2 0 0 0 0 6.0 6.0 83 6.0 1.4 2.5 0.4 0.9 0 0 0 0 6.0 6.0 Min (ns)

-4 Max (ns) 3.8 5.4 2.8 5.0 0.5 1.5 2.9 2.5 4.0 5.9 1.3 2.4 0.4 0.9 0 0 0 0 6.0 6.0 83 6.0 5.1 4.2 6.0 Min (ns)

-3 Max (ns) 3.0 4.3 2.4 4.3 0.5 1.4 2.4 2.1 4.0 5.5

TILO TITO TIDO TIMO TCY TCYDI TCYL TCYO TCKO TGO TICK TMICK TDICK TEICK TCKI TCKMI TCKDI TCKEI TCH TCL FTOG TCLRW TCLR TCLRL TGCLRW TGCLR

83

4.0 3.0

8.0

Note: 1. The CLB K to Q output delay (TCKO) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold-time requirement (TCKDI) of any CLB on the same die. 2. Timing is based upon the XC5215 device. For other devices, see XACTstep Timing Calculator. 3. Maximum ip-op toggle rate for export control purposes.

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XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin)

All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the Global Buffer specications. The XACTstep delay calculator uses this indirect method, and may overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values listed below should be used, and the derived values should be considered conservative overestimates. Speed Grade Description Global Clock to Output Pad (fast)
BUFG

-6 Max (ns) 16.9 17.1 17.2 17.2 19.0 21.4 21.6 21.7 21.7 24.3 2.5 2.3 2.2 2.2 2.0 3.8 3.9 4.4 5.1 5.8 7.3 7.3 7.2 7.2 6.8 8.8 8.6 8.5 8.5 8.5 0

-5 Max (ns) 15.1 15.3 15.4 15.4 17.0 18.7 18.9 19.0 19.0 21.2 2.0 1.9 1.9 1.9 1.8 3.8 3.9 4.4 5.1 5.8 6.6 6.6 6.5 6.5 5.7 7.7 7.5 7.4 7.4 7.4 0

-4 Max (ns) 10.9 11.3 11.9 12.8 12.8 12.6 13.3 13.6 15.0 15.0 1.9 1.9 1.9 1.9 1.7 3.5 3.8 4.4 4.9 5.7 6.6 6.6 6.4 6.0 5.7 7.5 7.5 7.4 7.4 7.4 0

-3 Max (ns) 9.8 9.9 10.8 11.2 11.7 11.5 11.9 12.5 12.9 13.1 1.9 1.9 1.9 1.8 1.7 3.5 3.6 4.3 4.8 5.6 6.6 6.6 6.3 6.0 5.7 7.5 7.5 7.4 7.3 7.2 0

Symbol TICKOF . . . . (Max)

Device XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC52xx

CLB Q

Direct IOB Connect

FAST
Global Clock-to-Output Delay

Global Clock to Output Pad (slew-limited)

BUFG

TICKO . . . . (Max)

CLB Q

Direct IOB Connect

Global Clock-to-Output Delay

Input Set-up Time (no delay) to CLB Flip-Flop IOB(NODELAY) Direct CLB Connect Input F,DI Set-up
& Hold Time BUFG

TPSUF (Min)

Input Hold Time (no delay) to CLB Flip-Flop IOB(NODELAY) Direct CLB Connect Input F,DI Set-up
& Hold Time BUFG

TPHF (Min)

Input Set-up Time (with delay) to CLB Flip-Flop DI Input Direct IOB Connect CLB Input DI Set-up
& Hold Time BUFG

TPSU

Input Set-up Time (with delay) to CLB Flip-Flop F Input Direct IOB Connect CLB Input F Set-up
& Hold Time BUFG

TPSUL (Min)

Input Hold Time (with delay) to CLB Flip-Flop Direct IOB Connect CLB Input F,DI Set-up
& Hold Time BUFG

TPH (Min)

PRELIMINARY

Note: 1. These measurements assume that the CLB ip-op uses a direct interconnect to or from the IOB. The XACTstep M1
INREG/ OUTREG properties, or XACT-Performance, can be used to assure that direct connects are used. tPSU applies only to the CLB input DI that bypasses the look-up table, which only offers direct connects to IOBs on the left and right edges of the die. tPSUL applies to the CLB inputs F that feed the look-up table, which offers direct connect to IOBs on all four edges, as do the CLB Q outputs. 2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.

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XC5200 IOB Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Speed Grade Description Input Propagation Delays from CMOS or TTL Levels Pad to I (no delay) Pad to I (with delay) Output Propagation Delays to CMOS or TTL Levels Output (O) to Pad (fast) Output (O) to Pad (slew-limited) From clock (CK) to output pad (fast), using direct connect between Q and output (O) From clock (CK) to output pad (slew-limited), using direct connect between Q and output (O) 3-state to Pad active (fast) 3-state to Pad active (slew-limited) Internal GTS to Pad active Symbol -6 Max (ns) -5 Max (ns) -4 Max (ns) -3 Max (ns)

TPI TPID

5.7 11.4

5.0 10.2

4.8 10.2

3.3 9.5

TOPF TOPS TOKPOF TOKPOS TTSONF TTSONS TGTS

4.6 9.5 10.1 14.9 5.6 10.4 17.7

4.5 8.4 9.3 13.1 5.2 9.0 15.9

4.5 8.0 8.3 11.8 4.9 8.3 14.7

3.5 5.0 7.5 10.0 4.6 6.0 13.5

PRELIMINARY

Note: 1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast output rise/fall times. 2. Unused and unbonded IOBs are congured by default as inputs with internal pull-up resistors. 3. Timing is based upon the XC5215 device. For other devices, see XACTstep Timing Calculator.

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XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines

The following guidelines reect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC5200 devices unless otherwise noted. Speed Grade Description Symbol Setup and Hold Input (TDI) to clock (TCK) TTDITCK setup time Input (TDI) to clock (TCK) TTCKTDI hold time Input (TMS) to clock (TCK) TTMSTCK setup time Input (TMS) to clock (TCK) TTCKTMS hold time Propagation Delay Clock (TCK) to Pad (TDO) TTCKPO Clock Clock (TCK) High TTCKH Clock (TCK) Low TTCKL FMAX (MHz) FMAX
Note 1:

-6 Min 30.0 0 15.0 0 Max Min 30.0 0 15.0 0

-5 Max Min 30.0 0 15.0 0

-4 Max Min 30.0 0 15.0 0

-3 Max

30.0 30.0 30.0 10.0 30.0 30.0

30.0 30.0 30.0 10.0

ADVANCE

30.0 30.0 30.0 10.0

30.0

10.0

Input pad setup and hold times are specied with respect to the internal clock.

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Device-Specic Pinout Tables

Device-specic tables include all packages for each XC5200-Series device. They follow the pad locations around the die, and include boundary scan register locations.

Pin Locations for XC5202 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information. Pin
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

Description
VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) GND I/O (A12) I/O (A13) I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) I/O (A17) I/O (TDI) I/O (TCK) GND I/O (TMS) I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O)

VQ64*
57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10

PC84
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

PQ100
92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

VQ100
89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

TQ144
128 129 130 131 132 133 134 137 138 139 142 143 144 1 2 3 6 7 8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 32 33 34 35 36 37 38 39

PG156
H3 H1 G1 G2 G3 F1 F2 F3 E3 C1 B1 B2 C3 C4 B3 A1 B4 A3 C6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 C11 B12 A13 B13 B14 A15 C13 A16 C14 B15 B16

Boundary Scan Order

51 54 57 63 66 69 78 81 90 93 102 105 111 114 117 123 126 129 135 138 141 147 150 153 159 162 165 171 174 177 186 189 192 195

11. 12. 13. 14. 15. 16. 17. 18. 19. 20.

21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34.

11 12 13 14 15 16 17 18

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Pin
35. 36. 37. 38. 39. 40. 41. 42. 43.

Description
I/O (HDC) I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND DONE VCC PROG I/O (D7) GCK3 (I/O) I/O (D6) I/O GND I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O GND I/O (D1) I/O (RCLK-BUSY/ RDY) I/O (D0, DIN) I/O (DOUT)

VQ64*
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

PC84
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

PQ100
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

VQ100
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

TQ144
40 43 44 45 48 49 50 51 52 53 54 55 56 57 58 59 60 61 64 65 66 69 70 71 72 73 74 75 76 79 80 81 84 85 86 87 88 89 90 91 92 93 94 95 96 97 100 101 102 105 106

PG156
D14 E14 C16 F14 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 L14 P16 M14 N14 R16 P14 R15 P13 R14 T16 T15 T14 T13 P11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 P7 T5 P6 T3 P5 P4 T2

Boundary Scan Order

204 207 210 216 219 222 228 231 234 240 243 246 252 255 258 264 267 276 279 288 291 300 303 306 312 315 318 324 327 336 339 342 348 351 360 363 366 372 375

44. 45. 46. 47. 48. 49. 50. 51. 52. 53.

54. 55. 56. 57. 58. 59. 60. 61. 62. 63.

64. 65. 66. 67. 68. 69. 70. 71. 72. 73.

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Pin

Description
CCLK VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O (A2, CS1) I/O (A3) GND I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND

VQ64*
48 49 50 51 52 53 54 55 56

PC84
73 74 75 76 77 78 79 80 81 82 83 84 1

PQ100
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

VQ100
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

TQ144
107 108 109 110 111 112 115 116 118 121 122 123 124 125 126 127

PG156
R2 P3 T1 N3 R1 P2 P1 N1 L3 K3 K2 K1 J1 J2 J3 H2

Boundary Scan Order

0 9 15 18 21 27 30 33 39 42 45 -

74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84.

* VQ64 package supports Master Serial, Slave Serial, and Express conguration modes only.

Additional No Connect (N.C.) Connections on TQ144 Package

TQ144 135 136 140 141 4 5 9 10 25 26 30 31 41 42 46 47 62 63 67 68 77 78 82 83 98 99 103 104 113 114 117 119 120

Notes: Boundary Scan Bit 0 = TDO.T

Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD

Pin Locations for XC5204 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Description VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O PC84 2 3 4 5 6 7 8 PQ100 92 93 94 95 96 97 98 99 100 VQ100 89 90 91 92 93 94 95 96 97 TQ144 128 129 130 131 132 133 134 135 136 137 138 139 140 PG156 H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 D1 D2 E3 C1 C2 PQ160 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Boundary Scan Order 78 81 87 90 93 99 102 105 111 114 117 123 126

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XC5200 Series Field Programmable Gate Arrays

Pin 14. 15. 16.

Description I/O I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) GND I/O I/O I/O (TMS) I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O

PC84 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 -

PQ100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 -

VQ100 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 -

TQ144 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

PG156 D3 B1 B2 C3 C4 B3 A1 A2 C5 B4 A3 C6 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 C11 B12 A13 A14 C12 B13 B14 A15 C13 A16 C14 B15 B16 D14 C15 D15 E14 C16 E15 D16 F14 F15

PQ160 157 158 159 160 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Boundary Scan Order 129 138 141 150 153 159 162 165 171 174 177 180 183 186 189 195 198 201 207 210 213 219 222 225 231 234 237 240 243 246 249 258 261 264 267 276 279 282 288 291 294 300 303

17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30.

31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56.

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Pin 57. 58. 59. 60. 61. 62. 63.

Description I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG I/O (D7) GCK3 (I/O) I/O I/O I/O (D6) I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2)

PC84 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

PQ100 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

VQ100 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

TQ144 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

PG156 E16 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 M16 L15 L14 N16 M15 P16 M14 N15 P15 N14 R16 P14 R15 P13 R14 T16 T15 R13 P12 T14 T13 P11 R11 T11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 P7

PQ160 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106

Boundary Scan Order 306 312 315 318 324 327 330 336 339 348 351 354 360 363 366 372 375 378 384 387 390 396 399 408 411 420 423 426 432 435 438 444 447 450 456 459 462 468 471 474 480 483

64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79.

80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93.

94. 95. 96. 97. 98.

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XC5200 Series Field Programmable Gate Arrays

Pin 99. 100. 101. 102. 103. 104. 105. 106. 107.

Description I/O I/O I/O GND I/O (D1) I/O (RCLK-BUSY/ RDY) I/O I/O I/O (D0, DIN) I/O (DOUT) CCLK VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (A2, CS1) I/O (A3) I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND

PC84 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1

PQ100 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

VQ100 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

TQ144 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127

PG156 T5 R6 T4 P6 T3 P5 R4 R3 P4 T2 R2 P3 T1 N3 R1 P2 N2 M3 P1 N1 M2 M1 L3 L2 L1 K3 K2 K1 J1 J2 J3 H2

PQ160 107 108 109 110 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 137 138 139 140 141

Boundary Scan Order 486 492 495 498 504 507 510 516 519 0 9 15 18 21 27 30 33 39 42 45 51 54 57 63 66 69 -

108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124.

Additional No Connect (N.C.) Connections for PQ160 Package

8 9 30 31 PQ160 89 90 111 112 136

Notes: Boundary Scan Bit 0 = TDO.T

Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD

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Pin Locations for XC5206 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Description VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) I/O I/O GND I/O I/O I/O (TMS) I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O PC84 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PQ100 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VQ100 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TQ144 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PQ160 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TQ176 155 156 157 158 159 160 161 162 163 164 165 166 168 169 170 171 172 173 174 175 176 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PG191 J4 J3 J2 J1 H1 H2 H3 G1 G2 F1 E1 G3 C1 E2 F3 D2 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 C7 A4 A5 B7 A6 C8 A7 B8 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 PQ208 183 184 185 186 187 188 189 190 191 192 193 194 197 198 199 200 201 202 203 204 205 2 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Boundary Scan Order 87 90 93 99 102 105 111 114 117 123 126 129 138 141 150 153 162 165 174 177 183 186 189 195 198 201 207 210 213 219 222 225 234 237 246 249 255 258 261 267 270

19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36.

37. 38. 39. 40. 41.

April 8, 1998 (Version 5.0)

4-303

XC5200 Series Field Programmable Gate Arrays

Pin 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75.

Description I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O

PC84 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 -

PQ100 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 -

VQ100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 -

TQ144 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 -

PQ160 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

TQ176 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

PG191 C11 B11 A12 B12 A13 C12 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 G16 E18 F18 G17 G18 H16 H17 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 M18 M17 N18 P18 M16 T18

PQ208 32 33 34 35 36 37 40 41 42 43 44 45 46 47 48 49 50 55 56 57 58 59 60 61 62 63 64 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 93

Boundary Scan Order 273 279 282 285 291 294 297 303 306 309 315 318 321 330 333 336 339 348 351 354 360 363 372 375 378 384 387 390 396 399 402 408 411 414 420 423 426 432 435 438 444 447 450 456 459

76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86.

4-304

April 8, 1998 (Version 5.0)

Pin 87. 88. 89. 90. 91. 92. 93.

Description I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG I/O (D7) GCK3 (I/O) I/O I/O I/O (D6) I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O (D1) I/O (RCLKBUSY/RDY) I/O I/O I/O (D0, DIN) I/O (DOUT)

PC84 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

PQ100 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

VQ100 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

TQ144 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106

PQ160 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118

TQ176 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130

PG191 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 V17 V16 T13 U14 T12 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 T7 U5 T6 V3 V2 U4 T5 U3 T4

PQ208 94 95 96 97 98 99 100 101 103 106 108 109 110 111 112 113 114 115 116 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 145 146 147 148 149 150 151 152

Boundary Scan Order 468 471 480 483 486 492 495 504 507 516 519 522 528 531 534 540 543 552 555 558 564 567 570 576 579 588 591 600 603 612 615 618 624 627 630 636 639 642 648 651 654 660 663

94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111.

112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. 128. 129.

April 8, 1998 (Version 5.0)

4-305

XC5200 Series Field Programmable Gate Arrays

Pin

Description CCLK VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (A2, CS1) I/O (A3) I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND

PC84 73 74 75 76 77 78 79 80 81 82 83 84 1

PQ100 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

VQ100 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

TQ144 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127

PQ160 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141

TQ176 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154

PG191 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P2 T1 M3 P1 N1 M2 M1 L3 L2 L1 K1 K2 K3 K4

PQ208 153 154 159 160 161 162 163 164 165 166 167 168 171 172 173 174 175 176 177 178 179 180 181 182

Boundary Scan Order 9 15 18 21 27 30 33 42 45 51 54 57 63 66 69 75 78 81 -

130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. 144. 145. 146. 147. 148.

Additional No Connect (N.C.) Connections for PQ208 and TQ176 Packages

195 196 206 207 208 1 3 12 13 38 39 51 52 53 54 PQ208 65 66 91 92 102 104 107 117 118 143 144 155 156 157 158 169 170 TQ176 167

Notes: Boundary Scan Bit 0 = TDO.T

Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD

Pin Locations for XC5210 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin VCC I/O (A8) I/O (A9) I/O I/O I/O I/O Description PC84 2 3 4 TQ144 128 129 130 131 132 PQ160 142 143 144 145 146 TQ176 155 156 157 158 159 160 161 PQ208 183 184 185 186 187 188 189 PG223 J4 J3 J2 J1 H1 H2 H3 BG225 VCC* E8 B7 A7 C7 D7 E7 PQ240 212 213 214 215 216 217 218 Boundary Scan Order 111 114 117 123 126 129

1. 2. 3. 4. 5. 6.

4-306

April 8, 1998 (Version 5.0)

Pin 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24.

Description I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (TMS) I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O

PC84 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

TQ144 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

PQ160 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

TQ176 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

PQ208 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

PG223 G1 G2 H4 G4 F1 E1 G3 F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 C7 A4 A5 B7 A6 D7 D8 C8 A7 B8 A8 B9 C9 D9 D10 C10

BG225 A6 B6 VCC* C6 F7 A5 B5 GND* D6 C5 A4 E6 B4 D5 A3 C4 B3 F6 A2 C3 VCC* GND* D4 B1 C2 E5 D3 C1 D2 G6 E4 D1 E3 E2 GND* F5 E1 F4 F3 VCC* F2 F1 G4 G3 G2 G1 G5 H3 GND* VCC* H4

PQ240 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31

Boundary Scan Order 135 138 141 150 153 162 165 171 174 177 183 186 189 195 198 201 210 213 222 225 231 234 237 243 246 249 255 258 261 267 270 273 279 282 285 291 294 297 306 309 318 321 327

25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48.

49.

April 8, 1998 (Version 5.0)

4-307

XC5200 Series Field Programmable Gate Arrays

Pin 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94.

Description I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O

PC84 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 -

TQ144 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 -

PQ160 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 -

TQ176 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 -

PQ208 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 -

PG223 B10 A9 A10 A11 C11 D11 D12 B11 A12 B12 A13 C12 D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 G16 E18 F18 G17 G18 H16 H17 G15

BG225 H5 J2 J1 J3 J4 J5 K1 VCC* K2 K3 J6 L1 GND* L2 K4 L3 M1 K5 M2 L4 N1 M3 N2 K6 P1 N3 GND* P2 VCC* M4 R2 P3 L5 N4 R3 P4 K7 M5 R4 N5 P5 L6 GND* R5 M6 N6 P6 VCC* R6 M7 N7

PQ240 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 84

Boundary Scan Order 330 333 339 342 345 351 354 357 363 366 369 375 378 381 387 390 393 399 402 405 411 414 417 426 429 432 435 444 447 450 456 459 462 468 471 474 480 483 486 492 495 504 507 510 516

4-308

April 8, 1998 (Version 5.0)

Pin 95. 96. 97. 98. 99.

Description I/O I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG I/O (D7) GCK3 (I/O) I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O

PC84 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 -

TQ144 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 -

PQ160 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 -

TQ176 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 -

PQ208 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 103 106 108 109 110 111 112 113 114 115 116 117 118 119 -

PG223 H15 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 L15 M15 M18 M17 N18 P18 M16 N15 P15 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 T12 R12

BG225 P7 R7 L7 N8 P8 VCC* GND* L8 P9 R9 N9 M9 L9 R10 P10 VCC* N10 K9 R11 P11 GND* M10 N11 R12 L10 P12 M11 R13 N12 P13 K10 R14 N13 GND* P14 VCC* M12 P15 N14 L11 M13 N15 M14 J10 L12 M15 L13 L14 K11 GND* L15

PQ240 85 86 87 88 89 90 91 92 93 94 95 96 97 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136

Boundary Scan Order 519 522 528 531 534 540 543 546 552 555 558 564 567 570 576 579 588 591 600 603 606 612 615 618 624 627 630 636 639 648 651 660 663 666 672 675 678 684 687 690 696 699

100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123.

124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. 136.

April 8, 1998 (Version 5.0)

4-309

XC5200 Series Field Programmable Gate Arrays

Pin 137. 138. 139. 140. 141. 142. 143. 144. 145. 146. 147.

Description I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK-BUSY/RDY) I/O I/O I/O (D0, DIN) I/O (DOUT) CCLK VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (CS1, A2) I/O (A3) I/O

PC84 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 -

TQ144 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 -

PQ160 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 -

TQ176 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 -

PQ208 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 159 160 161 162 163 164 165 166 -

PG223 R11 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 R8 R7 T7 R6 R5 V5 V4 U5 T6 V3 V2 U4 T5 U3 T4 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P4

BG225 K12 K13 K14 VCC* K15 J12 J13 J14 J15 J11 H13 H14 VCC* GND* H12 H11 G14 G15 G13 G12 G11 F15 VCC* F14 F13 G10 E15 GND* E14 F12 E13 D15 F11 D14 E12 C15 D13 C14 F10 B15 C13 VCC* A15 GND* A14 B13 E11 C12 A13 B12 F9

PQ240 137 138 139 140 141 142 144 145 146 147 148 149 150 151 152 153 154 155 156 157 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189

Boundary Scan Order 708 711 714 720 723 726 732 735 738 744 747 756 759 768 771 780 783 786 792 795 798 804 807 810 816 819 822 828 831 834 840 843 846 855 858 9 15 18 21 27 30 33

148. 149. 150. 151. 152. 153. 154. 155. 156. 157. 158. 159. 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171.

172. 173. 174. 175. 176. 177. 178. 179.

4-310

April 8, 1998 (Version 5.0)

Pin 180. 181. 182. 183. 184. I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND

Description

PC84 81 82 83 84 1

TQ144 117 118 119 120 121 122 123 124 125 126 127

PQ160 129 130 131 132 133 134 135 136 137 138 139 140 141

TQ176 141 142 143 144 145 146 147 148 149 150 151 152 153 154

PQ208 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182

PG223 N4 P2 T1 R1 N2 M3 P1 N1 M4 L4 M2 M1 L3 L2 L1 K1 K2 K3 K4

BG225 D11 A12 C11 B11 E10 GND* A11 D10 C10 B10 VCC* A10 D9 C9 B9 A9 E9 C8 B8 GND*

PQ240 190 191 192 193 194 196 197 198 199 200 201 202 203 205 206 207 208 209 210 211

Boundary Scan Order 39 42 45 51 54 57 66 69 75 78 81 87 90 93 99 102 105 -

185. 186. 187. 188. 189. 190. 191. 192. 193. 194. 195. 196.

Additional No Connect (N.C.) Connections for PQ208 and PQ240 Packages

PQ208 1 3 51 52 53 54 102 104 107 155 156 157 158 206 207 208 22 37 83 98 PQ240 143 158 195 204 219

Notes: * Pins labeled VCC* are internally bonded to a VCC plane within the BG225 package. The external pins are: B2, D8, H15, R8,
B14, R1, H1, and R15. Pins labeled GND* are internally bonded to a ground plane within the BG225 package. The external pins are: A1, D12, G7, G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD

Pin Locations for XC5215 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin 1. 2. 3. 4. 5. 6. 7. Description VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) PQ160 142 143 144 145 146 147 HQ208 183 184 185 186 187 188 189 190 HQ240 212 213 214 215 216 217 218 220 PG299 K1 K2 K3 K5 K4 J1 J2 H1 HQ304 38 37 36 35 34 33 32 31 BG225 VCC* E8 B7 A7 C7 D7 E7 A6 BG352 VCC* D14 C14 A15 B15 C15 D15 A16 Boundary Scan Order 138 141 147 150 153 159 162

April 8, 1998 (Version 5.0)

4-311

XC5200 Series Field Programmable Gate Arrays

Pin 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30.

Description I/O (A11) I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O I/O I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (TMS) I/O VCC I/O I/O I/O

PQ160 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -

HQ208 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 -

HQ240 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 -

PG299 J3 H2 G1 E1 H3 G2 H4 F2 F1 H5 G3 D1 G4 E2 F3 G5 C1 F4 E3 D2 C2 F5 E4 D3 C3 A2 B1 D4 B2 B3 E6 D5 C4 A3 D6 E7 B4 C5 A4 D7 C6 E8 B5 A5 B6 D8 C7 B7 A6 C8 E9 B8

HQ304 30 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 10 9 8 7 6 5 4 3 2 1 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 280 279 276

BG225 B6 VCC* C6 F7 A5 B5 GND* D6 C5 A4 E6 B4 D5 A3 C4 B3 F6 A2 C3 VCC* GND* D4 B1 C2 E5 D3 C1 D2 G6 E4 D1 E3 E2 GND* F5 E1 F4 F3 VCC* F2 F1 -

BG352 B16 C17 B18 VCC* C18 D17 A20 B19 GND* C19 D18 A21 B20 C20 B21 B22 C21 D20 A23 D21 C22 B24 C23 D22 C24 VCC* GND* D23 C25 D24 E23 C26 E24 F24 E25 D26 G24 F25 F26 H23 H24 G25 G26 GND* J23 J24 H25 K23 VCC* L24 K25 L25

Boundary Scan Order 165 171 174 177 183 186 189 195 198 201 207 210 213 219 222 225 234 237 243 246 249 258 261 270 273 279 282 285 294 297 303 306 309 315 318 321 327 330 333 339 342 345 351 354 357 363

31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53.

4-312

April 8, 1998 (Version 5.0)

Pin 54. 55. 56. 57. 58. 59. 60.

Description I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC)

PQ160 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

HQ208 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 55 56 57 58 59 60 61 62

HQ240 23 24 25 26 27 28 29 30 31 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

PG299 A8 C9 B9 E10 A9 D10 C10 A10 A11 B10 B11 C11 E11 D11 A12 B12 A13 E12 B13 A16 A14 C13 B14 D13 A15 B15 E13 C14 A17 D14 B16 C15 E14 A18 D15 C16 B17 B18 E15 D16 C17 A20 A19 C18 B20 D17 B19 C19 F16 E17 D18 C20

HQ304 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 256 255 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221

BG225 G4 G3 G2 G1 G5 H3 GND* VCC* H4 H5 J2 J1 J3 J4 J5 K1 VCC* K2 K3 J6 L1 GND* L2 K4 L3 M1 K5 M2 L4 N1 M3 N2 K6 P1 N3 GND* P2 VCC* M4 R2 P3 L5 N4 R3 P4

BG352 L26 M23 M24 M25 M26 N24 N25 GND* VCC* N26 P25 P23 P24 R26 R25 R24 R23 T26 T25 VCC* U24 V25 V24 U23 GND* Y26 W25 W24 V23 AA26 Y25 Y24 AA25 AB25 AA24 Y23 AC26 AA23 AB24 AD25 AC24 AB23 GND* AD24 VCC* AC23 AE24 AD23 AC22 AF24 AD22 AE23

Boundary Scan Order 366 369 375 378 381 390 393 399 402 405 411 414 417 423 426 429 435 438 441 447 450 453 459 462 465 471 474 477 483 486 489 495 498 501 507 510 513 522 525 528 531 540 543 546 552 555

61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99.

April 8, 1998 (Version 5.0)

4-313

XC5200 Series Field Programmable Gate Arrays

Pin 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123.

Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O

PQ160 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

HQ208 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

HQ240 69 70 71 72 73 74 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 91 92 93 94 95 96 97 99 100 101 102 103 104 105 106 107 108 109 110 111 112

PG299 F17 G16 D19 E18 D20 G17 F18 H16 E19 F19 E20 H17 G18 G19 H18 F20 J16 G20 H20 J18 J19 K16 J20 K17 K18 K19 L20 K20 L19 L18 L16 L17 M20 M19 N20 M18 N19 P20 T20 N18 P19 N17 R19 R20 N16 P18 U20 P17 T19 R18 P16 V20

HQ304 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 204 203 202 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 179 178 177 175 174 173 172 171 170 169 168 167 166 165 164 163

BG225 K7 M5 R4 N5 P5 L6 GND* R5 M6 N6 P6 VCC* R6 M7 N7 P7 R7 L7 N8 P8 VCC* GND* L8 P9 R9 N9 M9 L9 R10 P10 VCC* N10 K9 R11 P11 GND* M10 N11 R12 L10 P12 M11

BG352 AE22 AF23 AD20 AE21 AF21 AC19 AD19 AE20 AF20 AC18 GND* AD18 AE19 AC17 AD17 VCC* AE17 AE16 AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 VCC* GND* AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 AE11 AD11 VCC* AE9 AD9 AC10 AF7 GND* AE8 AD8 AC9 AF6 AE7 AD7 AE6 AE5

Boundary Scan Order 558 564 567 570 576 579 582 588 591 594 600 603 606 612 615 618 624 627 630 636 639 642 648 651 660 663 672 675 678 684 687 690 696 699 702 708 711 714 720 723 726 732 735 738 744 747

124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. 144. 145.

4-314

April 8, 1998 (Version 5.0)

Pin 146. 147. 148. 149. 150. 151. 152. 153.

Description I/O I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG I/O (D7) GCK3 (I/O) I/O I/O I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O

PQ160 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -

HQ208 95 96 97 98 99 100 101 103 106 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137

HQ240 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 144 145 146 147 148 149 150 151 152 153 154 155 156 157

PG299 R17 T18 U19 V19 R16 T17 U18 X20 W20 V18 X19 U17 W19 W18 T15 U16 V17 X18 U15 T14 W17 V16 X17 U14 V15 T13 W16 W15 X16 U13 V14 W14 V13 X15 T12 X14 X13 V12 W12 T11 X12 U11 V11 W11 X10 X11 W10 V10 T10 U10 X9 W9

HQ304 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 127 126 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108

BG225 R13 N12 P13 K10 R14 N13 GND* P14 VCC* M12 P15 N14 L11 M13 N15 M14 J10 L12 M15 L13 L14 K11 GND* L15 K12 K13 K14 VCC* K15 J12 J13 J14 J15 J11 H13 H14 VCC* GND* H12 H11 G14 G15 G13 G12

BG352 AD6 AC7 AF4 AF3 AD5 AE3 AD4 AC5 GND* AD3 VCC* AC4 AD2 AC3 AB4 AD1 AA4 AA3 AB2 AC1 Y3 AA2 AA1 W4 W3 Y2 Y1 V4 GND* V3 W2 U4 U3 VCC* V2 V1 T1 R4 R3 R2 R1 P3 P2 P1 VCC* GND* N2 N4 N3 M1 M2 M3

Boundary Scan Order 750 756 759 768 771 774 780 783 792 795 804 807 810 816 819 828 831 834 840 843 846 852 855 858 864 867 870 876 879 882 888 891 894 900 903 906 912 915 924 927 936 939 942 948

154. 155. 156. 157. 158. 159. 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. 175. 176. 177. 178. 179. 180. 181. 182. 183.

184. 185. 186. 187. 188. 189.

April 8, 1998 (Version 5.0)

4-315

XC5200 Series Field Programmable Gate Arrays

Pin 190. 191. 192. 193. 194. 195. 196. 197. 198. 199. 200. 201. 202. 203. 204. 205. 206. 207. 208. 209. 210. 211. 212. 213.

Description I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK-BUSY/RDY) I/O I/O I/O I/O I/O (D0, DIN) I/O (DOUT) CCLK VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (A2, CS1) I/O (A3) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC

PQ160 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 -

HQ208 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 -

HQ240 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201

PG299 X8 V9 W8 X7 X5 V8 W7 U8 W6 X6 T8 V7 X4 U7 W5 V6 T7 X3 U6 V5 W4 W3 T6 U5 V4 X1 V3 W1 U4 X2 W2 V2 R5 T4 U3 V1 R4 P5 U2 T3 U1 P4 R3 N5 T2 R2 T1 N4 P3 P2 N3 R1

HQ304 107 106 103 102 101 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 52

BG225 G11 F15 VCC* F14 F13 G10 E15 GND* E14 F12 E13 D15 F11 D14 E12 C15 D13 C14 F10 B15 C13 VCC* A15 GND* A14 B13 E11 C12 A13 B12 F9 D11 A12 C11 B11 E10 GND* A11 D10 C10 B10 VCC*

BG352 M4 L1 J1 K3 VCC* J2 J3 K4 G1 GND* H2 H3 J4 F1 G2 G3 F2 E2 F3 G4 D2 F4 E3 C2 D3 E4 C3 VCC* D4 GND* B3 C4 D5 A3 D6 C6 B5 A4 C7 B6 A6 D8 B7 A7 D9 C9 GND* B8 D10 C10 B9 VCC*

Boundary Scan Order 951 954 960 963 966 972 975 978 984 987 990 996 999 1002 1008 1011 1014 1020 1023 1032 1035 1038 1044 1047 0 9 15 18 21 27 30 33 39 42 45 51 54 57 63 66 69 75 78 81 87 -

214. 215. 216. 217. 218. 219. 220. 221. 222. 223. 224. 225. 226. 227. 228. 229. 230. 231. 232. 233. 234.

4-316

April 8, 1998 (Version 5.0)

Pin 235. 236. 237. 238. 239. 240. 241. 242. 243. 244.

Description I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND

PQ160 134 135 136 137 138 139 140 141

HQ208 174 175 176 177 178 179 180 181 182

HQ240 202 203 205 206 207 208 209 210 211

PG299 M5 P1 N1 M3 M2 L5 M1 L4 L3 L2 L1

HQ304 51 50 47 46 45 44 43 42 41 40 39

BG225 A10 D9 C9 B9 A9 E9 C8 B8 GND*

BG352 B11 A11 D12 C12 B12 A12 C13 B13 A13 B14 GND*

Boundary Scan Order 90 93 99 102 105 111 114 117 126 129 -

Additional No Connect (N.C.) Connections for HQ208, HQ240, and HQ304 Packages
HQ208 206 207 208 1 3 51 52 53 54 102 104 105 107 155 156 157 158 HQ240 219 22 37 83 98 143 158 204 29 28 24 11 281 278 277 258 257 HQ304 254 205 201 200 181 180 176 128 125 124 105 104 100 53 49 48 -

Notes: * Pins labeled VCC* are internally bonded to a VCC plane within the BG225 and BG352 packages. The external pins for the
BG225 are: B2, D8, H15, R8, B14, R1, H1, and R15. The external pins for the BG352 are: A10, A17, B2, B25, D13, D19, D7, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC14, AC20, AC8, AE2, AE25, AF10, and AF17. Pins labeled GND* are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for the BG225 are: A1, D12, G7, G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. The external pins for the BG352 are: A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1, AF13, AF19, AF2, AF22, AF25, AF26, AF5, AF8. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD

April 8, 1998 (Version 5.0)

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XC5200 Series Field Programmable Gate Arrays

Product Availability
PINS 64 Plast. VQFP 84 Plast. PLCC 100 Plast. PQFP 100 Plast. VQFP 144 Plast. TQFP 156 Ceram. PGA 160 Plast. PQFP 176 Plast. TQFP 191 Ceram. PGA 208 High-Perf. QFP 208 Plast. PQFP 223 Ceram. PGA 225 Plast. BGA 240 High-Perf. QFP 240 Plast. PQFP 299 Ceram. PGA 304 High-Perf. QFP 352 Plast. BGA C(I) 244 TYPE

HQ208

HQ240

HQ304
CI C(I) 244

PQ100

VQ100

PG156

PQ160

PG191

PQ208

PG223

BG225

PQ240

PG299

CODE

-6

CI C(I) C C

CI C(I) C C CI CI C C CI CI C C CI CI C C

CI C(I) C C CI CI C C CI CI C C

CI C(I) C C CI CI C C CI CI C C

CI C(I) C C CI CI C C CI CI C C CI CI C C

CI C(I) C C CI CI C C CI CI C C CI CI C C CI CI C C CI C(I) C C CI CI C C CI CI C C CI C(I) C C CI CI C C CI CI C C CI CI C C CI CI C C CI CI C C CI C(I) C C CI C(I) C C CI CI C C CI C(I) CI

XC5202

-5 -4 -3 -6 -5 -4 -3 -6 -5 -4 -3 -6 -5 -4 -3 -6 -5 -4 -3

XC5204

XC5206

XC5210

XC5215
8/4/97

C = Commercial TJ = 0 to +85C I= Industrial TJ = -40C to +100C

( ) Parentheses indicate future product plans

* VQ64 package supports Master Serial, Slave Serial, and Express conguration modes only.

User I/O Per Package

Device XC5202 XC5204 XC5206 XC5210 XC5215
8/4/97 Max I/O 84 124 148 196 244

Package Type
VQ64 52 PC84 65 65 65 65 PQ100 VQ100 TQ144 PG156 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 PG299 HQ304 BG352 81 81 81 81 81 81 84 117 117 117 84 124 124 133 133 133 148 149 164 148 148 164 196 196 196 197 196 244

Ordering Information
Example: Device Type Speed Grade

XC5210-6PQ208C
Temperature Range Number of Pins Package Type

4-318

April 8, 1998 (Version 5.0)

BG352

TQ144

TQ176

VQ64*

PC84

XC3000 Series Table of Contents

0 4*

XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional XC3100A Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Voltage Versions Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . New XC3000 Series Compared to Original XC3000 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . Improvements in the XC3000A and XC3000L Families . . . . . . . . . . . . . . . . . . . . . . . . . . . Improvements in the XC3100A and XC3100L Families . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of I/O Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Configuration Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reprogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bitstream Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Spike Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Readback Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General XC3000 Series Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-321 4-321 4-321 4-322 4-322 4-322 4-323 4-323 4-324 4-324 4-325 4-326 4-327 4-328 4-329 4-329 4-333 4-335 4-336 4-337 4-337 4-339 4-340 4-340 4-340 4-340 4-340 4-341 4-341 4-341 4-341 4-341 4-341 4-342 4-342 4-342 4-342 4-342 4-343 4-343 4-345 4-347 4-349 4-351 4-352 4-353 4-354 4-354

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XC3000 Series Table of Contents

Dynamic Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Permanently Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Pins That Can Have Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unrestricted User I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions During Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A IOB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L IOB Switching Characteristics Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A IOB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L IOB Switching Characteristics Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 44-Pin PLCC Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 64-Pin Plastic VQFP Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 100-Pin QFP Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 144-Pin Plastic TQFP Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 160-Pin PQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 176-Pin TQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 208-Pin PQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3195A PQ208 and PG223 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Product Description Schematic capture, automatic place and route Logic and timing simulation Interactive design editor for design optimization Timing calculator Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others

Features
Complete line of four related Field Programmable Gate Array product families - XC3000A, XC3000L, XC3100A, XC3100L Ideal for a wide range of custom VLSI design tasks - Replaces TTL, MSI, and other PLD logic - Integrates complete sub-systems into a single package - Avoids the NRE, time delay, and risk of conventional masked gate arrays High-performance CMOS static memory technology - Guaranteed toggle rates of 70 to 370 MHz, logic delays from 9 to 1.5 ns - System clock speeds over 85 MHz - Low quiescent and active power consumption Flexible FPGA architecture - Compatible arrays ranging from 1,000 to 7,500 gate complexity - Extensive register, combinatorial, and I/O capabilities - High fan-out signal distribution, low-skew clock nets - Internal 3-state bus capabilities - TTL or CMOS input thresholds - On-chip crystal oscillator amplier Unlimited reprogrammability - Easy design iteration - In-system logic changes Extensive packaging options - Over 20 different packages - Plastic and ceramic surface-mount and pin-gridarray packages - Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-tested devices - Excellent reliability record Complete XACTstep Development System
Device XC3020A, 3020L, 3120A XC3030A, 3030L, 3130A XC3042A, 3042L, 3142A, 3142L XC3064A, 3064L, 3164A XC3090A, 3090L, 3190A, 3190L XC3195A Max Logic Gates 1,500 2,000 3,000 4,500 6,000 7,500 Typical Gate CLBs Range 1,000 - 1,500 1,500 - 2,000 2,000 - 3,000 3,500 - 4,500 5,000 - 6,000 6,500 - 7,500 64 100 144 224 320 484

Additional XC3100A Features

Ultra-high-speed FPGA family with six members - 50-85 MHz system clock rates - 190 to 370 MHz guaranteed ip-op toggle rates - 1.55 to 4.1 ns logic delays High-end additional family member in the 22 X 22 CLB array-size XC3195A device 8 mA output sink current and 8 mA source current Maximum power-down and quiescent current is 5 mA 100% architecture and pin-out compatible with other XC3000 families Software and bitstream compatible with the XC3000, XC3000A, and XC3000L families PCI complaint (-2, -1, -09 speed grade in plastic quad at pack (PQFP) packaging).

XC3100A combines the features of the XC3000A and XC3100 families: Additional interconnect resources for TBUFs and CE inputs Error checking of the conguration bitstream Soft startup holds all outputs slew-rate limited during initial power-up More adsvanced CMOS process

Low-Voltage Versions Available

Low-voltage devices function at 3.0 - 3.6 V XC3000L - Low-voltage versions of XC3000A devices XC3100L - Low-voltage versions of XC3100A devices

Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 22 x 22

User I/Os Flip-Flops Max 64 80 96 120 144 176 256 360 480 688 928 1,320

Horizontal Longlines 16 20 24 32 40 44

Conguration Data Bits 14,779 22,176 30,784 46,064 64,160 94,984

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Introduction
XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, exible, userprogrammable array architecture is composed of a conguration program store plus three types of congurable elements: a perimeter of I/O Blocks (IOBs), a core array of Congurable Logic Bocks (CLBs) and resources for interconnection. The general structure of an FPGA is shown in Figure 2. The XACTstep development system provides schematic capture and auto place-and-route for design entry. Logic and timing simulation, and in-circuit emulation are available as design verication alternatives. The design editor is used for interactive design optimization, and to compile the data pattern that represents the conguration program. The FPGA user logic functions and interconnections are determined by the conguration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM or ROM on the application circuit board, or on a oppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of program data at power-up. The companion XC17XX Serial Conguration PROMs provide a very simple serial conguration program storage in a one-time programmable package. The XC3000 Field Programmable Gate Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades.

Here is a simple overview of those XC3000 products currently emphasized: XC3000A Family The XC3000A is an enhanced version of the basic XC3000 family, featuring additional interconnect resources and other user-friendly enhancements. The ease-of-use of the XC3000A family makes it the obvious choice for all new designs that do not require the speed of the XC3100A or the 3-V operation of the XC3000L. XC3000L Family The XC3000L is identical in architecture and features to the XC3000A family, but operates at a nominal supply voltage of 3.3 V. The XC3000L is the right solution for battery-operated and low-power applications. XC3100A Family The XC3100A is a performanceoptimized relative of the XC3000A family. While both families are bitstream and footprint compatible, the XC3100A family extends toggle rates to 370 MHz and in-system performance to over 80 MHz. The XC3100A family also offers one additional array size, the XC3195A. The XC3100A is best suited for designs that require the highest clock speed or the shortest net delays. XC3100L Family The XC3100L is identical in architectures and features to the XC3100A family, but operates at a nominal supply voltage of 3.3V. Figure 1 illustrates the relationships between the families. Compared to the original XC3000 family, XC3000A offers additional functionality and, coming soon, increased speed. The XC3000L family offers the same additional functionality, but reduced speed due to its lower supply voltage of 3.3 V. The XC3100A family offers substantially higher speed and higher density with the XC3195A.

XC3000 Series Overview

There are now four distinct family groupings within the XC3000 Series of FPGA devices, with emphasis on those listed below: XC3000A Family XC3000L Family XC3100A Family XC3100L Family

New XC3000 Series Compared to Original XC3000 Family

For readers already familiar with the original XC3000 family of FPGAs, the major new features in the XC3000A, XC3000L, XC3100A, and XC3100L families are listed in this section. All of these new families are upward-compatible extensions of the original XC3000 FPGA architecture. Any bitstream used to congure an XC3000 device will congure the corresponding XC3000A, XC3000L, XC3100A, or XC3100L device exactly the same way. The XC3100A and XC3100L FPGA architectures are upward-compatible extensions of the XC3000A and XC3000L architectures. Any bitstream used to congure an XC3000A or XC3000L device will congure the corresponding XC3100A or XC3100L device exactly the same way.

All four families share a common architecture, development software, design and programming methodology, and also common package pin-outs. An extensive Product Description covers these common aspects. Detailed parametric information for the XC3000A, XC3000L, XC3100A, and XC3100L product families is then provided. (The XC3000 and XC3100 families are not recommended for new designs, and their individual product specications are not included in this book.)

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Improvements in the XC3000A and XC3000L Families

The XC3000A and XC3000L families offer the following enhancements over the popular XC3000 family: The XC3000A and XC3000L families has additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efcient and faster designs when horizontal Longlines are used for data bussing. During conguration, the XC3000A and XC3000L devices check the bit-stream format for stop bits in the appropriate positions. Any error terminates the conguration and pulls INIT Low. When the conguration process is nished and the device starts up in user mode, the rst activation of the outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the XC3000 family, determined by the individual conguration option.
(XC3 195A )

Functio

nality

XC310 00L 0 XC310XC31 XC300 XC300 0L 0A

0A

Speed

city Capa Gate

X7068

Figure 1: XC3000 FPGA Families

Improvements in the XC3100A and XC3100L Families

Based on a more advanced CMOS process, the XC3100A and XC3100L families are architecturally-identical, performance-optimized relatives of the XC3000A and XC3100A families. While all families are footprint compatible, the XC3100A family extends achievable system performance beyond 85 MHz.

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Detailed Functional Description

The perimeter of congurable Input/Output Blocks (IOBs) provides a programmable interface between the internal logic array and the device package pins. The array of Congurable Logic Blocks (CLBs) performs user-specied logic functions. The interconnect resources are programmed to form networks, carrying logic signals among blocks, analogous to printed circuit board traces connecting MSI/SSI packages. The block logic functions are implemented by programmed look-up tables. Functional options are implemented by program-controlled multiplexers. Interconnecting networks between blocks are implemented with metal segments joined by program-controlled pass transistors. These FPGA functions are established by a conguration program which is loaded into an internal, distributed array of conguration memory cells. The conguration program is loaded into the device at power-up and may be reloaded on command. The FPGA includes logic and control signals to implement automatic or passive conguration. Program data may be either bit serial or byte parallel. The XACTstep development system generates the conguration program bitstream used to congure the device. The memory loading process is independent of the user logic functions.

Conguration Memory
The static memory cell used for the conguration memory in the Field Programmable Gate Array has been designed specically for high reliability and noise immunity. Integrity of the device conguration memory based on this design is assured even under adverse conditions. As shown in Figure 3, the basic memory cell consists of two CMOS inverters plus a pass transistor used for writing and reading cell data. The cell is only written during conguration and only read during readback. During normal operation, the cell provides continuous control and the pass transistor is off and does not affect cell stability. This is quite different from the operation of conventional memory devices, in which the cells are frequently read and rewritten.

PWR DN

P9

P8

P7

P6

P5

P4

P3

P2

GND

I/O Blocks
P11

3-State Buffers With Access to Horizontal Long Lines

Configurable Logic Blocks

TCL KIN AA P12 AB AC AD

Interconnect Area

P13 BA U61 BB

Configuration Memory
X3241

Figure 2: Field Programmable Gate Array Structure. It consists of a perimeter of programmable I/O blocks, a core of congurable logic blocks and their interconnect resources. These are all controlled by the distributed array of conguration program memory cells.

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Frame Pointer

Q Read or Write Data Q

testing, no soft errors have been observed even in the presence of very high doses of alpha radiation.
Configuration Control

X5382

Figure 3: Static Conguration Memory Cell. It is loaded with one bit of conguration program and controls one program selection in the Field Programmable Gate Array.

The method of loading the conguration data is selectable. Two methods use serial data, while three use byte-wide data. The internal conguration logic utilizes framing information, embedded in the program data by the XACTstep development system, to direct memory-cell loading. The serial-data framing and length-count preamble provide programming compatibility for mixes of various FPGA device devices in a synchronous, serial, daisy-chain fashion.

I/O Block
Each user-congurable IOB shown in Figure 4, provides an interface between the external package pin of the device and the internal user logic. Each IOB includes both registered and direct input paths. Each IOB provides a programmable 3-state output buffer, which may be driven by a registered or direct output signal. Conguration options allow each IOB an inversion, a controlled slew rate and a high impedance pull-up. Each input circuit also provides input clamping diodes to provide electrostatic protection, and circuits to inhibit latch-up produced by input currents.
Vcc

The memory cell outputs Q and Q use ground and VCC levels and provide continuous, direct control. The additional capacitive load together with the absence of address decoding and sense ampliers provide high stability to the cell. Due to the structure of the conguration memory cells, they are not affected by extreme power-supply excursions or very high levels of alpha particle radiation. In reliability

PROGRAM-CONTROLLED MEMORY CELLS

OUT INVERT

3-STATE INVERT

OUTPUT SELECT

SLEW RATE

PASSIVE PULL UP

3- STATE (OUTPUT ENABLE)

OUT

FLIP FLOP

OUTPUT BUFFER

I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD

CK1

CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP

X3029

Figure 4: Input/Output Block. Each IOB includes input and output storage elements and I/O options selected by conguration memory cells. A choice of two clocks is available on each die edge. The polarity of each clock line (not each ip-op or latch) is programmable. A clock line that triggers the ip-op on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS thresholds.

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The input-buffer portion of each IOB provides threshold detection to translate external signals applied to the package pin to internal logic levels. The global input-buffer threshold of the IOBs can be programmed to be compatible with either TTL or CMOS levels. The buffered input signal drives the data input of a storage element, which may be congured as either a ip-op or a latch. The clocking polarity (rising/falling edge-triggered ip-op, High/Low transparent latch) is programmable for each of the two clock lines on each of the four die edges. Note that a clock line driving a rising edge-triggered ip-op makes any latch driven by the same line on the same edge Low-level transparent and vice versa (falling edge, High transparent). All Xilinx primitives in the supported schematic-entry packages, however, are positive edge-triggered ip-ops or High transparent latches. When one clock line must drive ip-ops as well as latches, it is necessary to compensate for the difference in clocking polarities with an additional inverter either in the ip-op clock input or the latch-enable input. I/O storage elements are reset during conguration or by the active-Low chip RESET input. Both direct input (from IOB pin I) and registered input (from IOB pin Q) signals are available for interconnect. For reliable operation, inputs should have transition times of less than 100 ns and should not be left oating. Floating CMOS input-pin circuits might be at threshold and produce oscillations. This can produce additional power dissipation and system noise. A typical hysteresis of about 300 mV reduces sensitivity to input noise. Each user IOB includes a programmable high-impedance pull-up resistor, which may be selected by the program to provide a constant High for otherwise undriven package pins. Although the Field Programmable Gate Array provides circuitry to provide input protection for electrostatic discharge, normal CMOS handling precautions should be observed. Flip-op loop delays for the IOB and logic-block ip-ops are short, providing good performance under asynchronous clock and data conditions. Short loop delays minimize the probability of a metastable condition that can result from assertion of the clock during data transitions. Because of the short-loop-delay characteristic in the Field Programmable Gate Array, the IOB ip-ops can be used to synchronize external signals applied to the device. Once synchronized in the IOB, the signals can be used internally without further consideration of their clock relative timing, except as it applies to the internal logic and routing-path delays. IOB output buffers provide CMOS-compatible 4-mA source-or-sink drive for high fan-out CMOS or TTL- compatible signal levels (8 mA in the XC3100A family). The network driving IOB pin O becomes the registered or direct data source for the output buffer. The 3-state control signal (IOB) pin T can control output activity. An open-drain output may be obtained by using the same signal for driving the

output and 3-state signal nets so that the buffer output is enabled only for a Low. Conguration program bits for each IOB control features such as optional output register, logic signal inversion, and 3-state and slew-rate control of the output. The program-controlled memory cells of Figure 4 control the following options. Logic inversion of the output is controlled by one conguration program bit per IOB. Logic 3-state control of each IOB output buffer is determined by the states of conguration program bits that turn the buffer on, or off, or select the output buffer 3-state control interconnection (IOB pin T). When this IOB output control signal is High, a logic one, the buffer is disabled and the package pin is high impedance. When this IOB output control signal is Low, a logic zero, the buffer is enabled and the package pin is active. Inversion of the buffer 3-state control-logic sense (output enable) is controlled by an additional conguration program bit. Direct or registered output is selectable for each IOB. The register uses a positive-edge, clocked ip-op. The clock source may be supplied (IOB pin OK) by either of two metal lines available along each die edge. Each of these lines is driven by an invertible buffer. Increased output transition speed can be selected to improve critical timing. Slower transitions reduce capacitive-load peak currents of non-critical outputs and minimize system noise. An internal high-impedance pull-up resistor (active by default) prevents unconnected inputs from oating.

Unlike the original XC3000 series, the XC3000A, XC3000L, XC3100A, and XC3100L families include the Soft Startup feature. When the conguration process is nished and the device starts up in user mode, the rst activation of the outputs is automatically slew-rate limited. This feature avoids potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is determined by the individual conguration option.

Summary of I/O Options

Inputs - Direct - Flip-op/latch - CMOS/TTL threshold (chip inputs) - Pull-up resistor/open circuit Outputs - Direct/registered - Inverted/not - 3-state/on/off - Full speed/slew limited - 3-state/output enable (inverse)

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Congurable Logic Block

The array of CLBs provides the functional elements from which the users logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. For example, the XC3020A has 64 such blocks arranged in 8 rows and 8 columns. The XACTstep development system is used to compile the conguration data which is to be loaded into the internal conguration memory to dene the operation and interconnection of each block. User denition of CLBs and their interconnecting networks may be done by automatic translation from a schematic-capture logic diagram or optionally by installing library or user macros. Each CLB has a combinatorial logic section, two ip-ops, and an internal control section. See Figure 5. There are: ve logic inputs (A, B, C, D and E); a common clock input (K); an asynchronous direct RESET input (RD); and an enable clock (EC). All may be driven from the interconnect

resources adjacent to the blocks. Each CLB also has two outputs (X and Y) which may drive interconnect networks. Data input for either ip-op within a CLB is supplied from the function F or G outputs of the combinatorial logic, or the block input, DI. Both ip-ops in each CLB share the asynchronous RD which, when enabled and High, is dominant over clocked inputs. All ip-ops are reset by the active-Low chip input, RESET, or during the conguration process. The ip-ops share the enable clock (EC) which, when Low, recirculates the ip-ops present states and inhibits response to the data-in or combinatorial function inputs on a CLB. The user may enable these control inputs and select their sources. The user may also select the clock net input (K), as well as its active sense within each CLB. This programmable inversion eliminates the need to route both phases of a clock signal throughout the device. Flexible routing allows use of common or individual CLB clocking.

DI DATA IN 0 MUX F DIN G RD QX A B LOGIC VARIABLES C D E QY F DIN G 0 MUX 1 D Q QY COMBINATORIAL FUNCTION G G Y CLB OUTPUTS F F QX X 1 D Q

EC ENABLE CLOCK 1 (ENABLE) RD

K CLOCK

DIRECT RESET

RD

0 (INHIBIT) (GLOBAL RESET)

X3032

Figure 5: Congurable Logic Block. Each CLB includes a combinatorial logic section, two ip-ops and a program memory controlled multiplexer selection of function. It has the following: - ve logic variable inputs A, B, C, D, and E - a direct data in DI - an enable clock EC - a clock (invertible) K - an asynchronous direct RESET RD - two outputs X and Y

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The combinatorial-logic portion of the CLB uses a 32 by 1 look-up table to implement Boolean functions. Variables selected from the ve logic inputs and two internal block ip-ops are used as table address inputs. The combinatorial propagation delay through the network is independent of the logic function generated and is spike free for single input variable changes. This technique can generate two independent logic functions of up to four variables each as shown in Figure 6a, or a single function of ve variables as shown in Figure 6b, or some functions of seven variables as shown in Figure 6c. Figure 7 shows a modulo-8 binary counter with parallel enable. It uses one CLB of each type. The partial functions of six or seven variables are implemented using the input variable (E) to dynamically select between two functions of four different variables. For the two functions of four variables each, the independent results (F and G) may be used as data inputs to either ipop or either logic block output. For the single function of ve variables and merged functions of six or seven variables, the F and G outputs are identical. Symmetry of the F and G functions and the ip-ops allows the interchange of CLB outputs to optimize routing efciencies of the networks interconnecting the CLBs and IOBs.

A B QX QY C D E A B QX QY C D E Any Function of Up to 4 Variables G Any Function of Up to 4 Variables F

5a

A B QX QY C D E Any Function of 5 Variables G F

5b

Programmable Interconnect
Programmable-interconnection resources in the Field Programmable Gate Array provide routing paths to connect inputs and outputs of the IOBs and CLBs into logic networks. Interconnections between blocks are composed of a two-layer grid of metal segments. Specially designed pass transistors, each controlled by a conguration bit, form programmable interconnect points (PIPs) and switching matrices used to implement the necessary connections between selected metal segments and block pins. Figure 8 is an example of a routed net. The XACTstep development system provides automatic routing of these interconnections. Interactive routing (Editnet) is also available for design optimization. The inputs of the CLBs or IOBs are multiplexers which can be programmed to select an input network from the adjacent interconnect segments. Since the switch connections to block inputs are unidirectional, as are block outputs, they are usable only for block input connection and not for routing. Figure 9 illustrates routing access to logic block input variables, control inputs and block outputs. Three types of metal resources are provided to accommodate various network interconnect requirements. General Purpose Interconnect Direct Connection Longlines (multiplexed busses and wide AND gates

A B QX QY C D M U X QX QY C D E 5c FGM Mode
X5442

Any Function of Up to 4 Variables F

A B Any Function of Up to 4 Variables

Figure 6: Combinational Logic Options 6a. Combinatorial Logic Option FG generates two functions of four variables each. One variable, A, must be common to both functions. The second and third variable can be any choice of B, C, QX and QY. The fourth variable can be any choice of D or E. 6b. Combinatorial Logic Option F generates any function of ve variables: A, D, E and two choices out of B, C, QX, QY. 6c. Combinatorial Logic Option FGM allows variable E to select between two functions of four variables: Both have common inputs A and D and any choice out of B, C, QX and QY for the remaining two variables. Option 3 can then implement some functions of six or seven variables.

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Count Enable Parallel Enable Clock

Terminal Count

Dual Function of 4 Variables

D D0

Q0

FG Mode

D D1 Function of 5 Variables

Q1

F Mode

D D2

Q2

Function of 6 Variables FGM Mode

X5383

Figure 8: An XACT Design Editor view of routing resources used to form a typical interconnection network from CLB GA. and to the right and may be highlighted by the use of the Show BIDI command in the XACT Design Editor. The other PIPs adjacent to the matrices are accessed to or from Longlines. The development system automatically denes the buffer direction based on the location of the interconnection network source. The delay calculator of the XACTstep development system automatically calculates and displays the block, interconnect and buffer delays for any paths selected. Generation of the simulation netlist with a worstcase delay model is provided by an XACT option.

Figure 7: C8BCP Macro. The C8BCP macro (modulo-8 binary counter with parallel enable and clock enable) uses one combinatorial logic block of each option.

General Purpose Interconnect

General purpose interconnect, as shown in Figure 10, consists of a grid of ve horizontal and ve vertical metal segments located between the rows and columns of logic and IOBs. Each segment is the height or width of a logic block. Switching matrices join the ends of these segments and allow programmed interconnections between the metal grid segments of adjoining rows and columns. The switches of an unprogrammed device are all non-conducting. The connections through the switch matrix may be established by the automatic routing or by using Editnet to select the desired pairs of matrix pins to be connected or disconnected. The legitimate switching matrix combinations for each pin are indicated in Figure 11 and may be highlighted by the use of the Show-Matrix command in the XACT Design Editor. Special buffers within the general interconnect areas provide periodic signal isolation and restoration for improved performance of lengthy nets. The interconnect buffers are available to propagate signals in either direction on a given general interconnect segment. These bidirectional (bidi) buffers are found adjacent to the switching matrices, above

Direct Interconnect
Direct interconnect, shown in Figure 12, provides the most efcient implementation of networks between adjacent CLBs or I/O Blocks. Signals routed from block to block using the direct interconnect exhibit minimum interconnect propagation and use no general interconnect resources. For each CLB, the X output may be connected directly to the B input of the CLB immediately to its right and to the C input of the CLB to its left. The Y output can use direct interconnect to drive the D input of the block immediately above and the A input of the block below. Direct interconnect should be used to maximize the speed of high-performance portions of logic. Where logic blocks are adjacent to IOBs, direct connect is provided alternately to the IOB inputs (I) and outputs (O) on all four edges of the die. The right edge provides additional direct connects from CLB outputs to adjacent IOBs. Direct interconnections of IOBs with CLBs are shown in Figure 13.

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Figure 9: XACT Design Editor Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect PIPs are directional. This is indicated on the XACT Design Editor status line: ND is a nondirectional interconnection. D:H->V is a PIP that drives from a horizontal to a vertical line. D:V->H is a PIP that drives from a vertical to a horizontal line. D:C->T is a T PIP that drives from a cross of a T to the tail. D:CW is a corner PIP that drives in the clockwise direction. P0 indicates the PIP is non-conducting, P1 is on.

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Figure 10: FPGA General-Purpose Interconnect. Composed of a grid of metal segments that may be interconnected through switch matrices to form networks for CLB and IOB inputs and outputs.

Figure 12: CLB X and Y Outputs. The X and Y outputs of each CLB have single contact, direct access to inputs of adjacent CLBs

Figure 11: Switch Matrix Interconnection Options for Each Pin. Switch matrices on the edges are different. Use Show Matrix menu option in the XACT Design Editor.

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Global Buffer Direct Input

Global Buffer Inerconnect

* Unbonded IOBs (6 Places)

Figure 13:

Alternate Buffer Direct Input

XC3020A Die-Edge IOBs. The XC3020A die-edge IOBs are provided with direct access to adjacent CLBs.

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Longlines
The Longlines bypass the switch matrices and are intended primarily for signals that must travel a long distance, or must have minimum skew among multiple destinations. Longlines, shown in Figure 14, run vertically and horizontally the height or width of the interconnect area. Each interconnection column has three vertical Longlines, and each interconnection row has two horizontal Longlines. Two additional Longlines are located adjacent to the outer sets of switching matrices. In devices larger than the XC3020A/ L and XC3120A FPGAs, two vertical Longlines in each col-

umn are connectable half-length lines. On the XC3020A/L and XC3120A FPGAs, only the outer Longlines are connectable half-length lines. Longlines can be driven by a logic block or IOB output on a column-by-column basis. This capability provides a common low skew control or clock line within each column of logic blocks. Interconnections of these Longlines are shown in Figure 15. Isolation buffers are provided at each input to a Longline and are enabled automatically by the development system when a connection is made.

Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.

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Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Threestate buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two nonclock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as connectable half-length lines.

VCC Z = DA DB DC ... DN

VCC

(LOW) DA DB DC DN
X3036

Figure 16: 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high impedance), the pull-up resistor(s) provide the High output. The buffer inputs are driven by the control signals or a Low.

Z = DA A + DB B + DC C + + DN N

DA WEAK KEEPER CIRCUIT A

DB B

DC C

DN N
X1741A

Figure 17: 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.

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A buffer in the upper left corner of the FPGA chip drives a global net which is available to all K inputs of logic blocks. Using the global buffer for a clock signal provides a skewfree, high fan-out, synchronized clock for use at any or all of the IOBs and CLBs. Conguration bits for the K input to each logic block can select this global line or another routing resource as the clock source for its ip-ops. This net may also be programmed to drive the die edge clock lines for IOB use. An enhanced speed, CMOS threshold, direct access to this buffer is available at the second pad from the top of the left die edge. A buffer in the lower right corner of the array drives a horizontal Longline that can drive programmed connections to a vertical Longline in each interconnection column. This alternate buffer also has low skew and high fan-out. The network formed by this alternate buffers Longlines can be selected to drive the K inputs of the CLBs. CMOS threshold, high speed access to this buffer is available from the third pad from the bottom of the right die edge.

Internal Busses
A pair of 3-state buffers, located adjacent to each CLB, permits logic to drive the horizontal Longlines. Logic operation

of the 3-state buffer controls allows them to implement wide multiplexing functions. Any 3-state buffer input can be selected as drive for the horizontal long-line bus by applying a Low logic level on its 3-state control line. See Figure 16. The user is required to avoid contention which can result from multiple drivers with opposing logic levels. Control of the 3-state input by the same signal that drives the buffer input, creates an open-drain wired-AND function. A logic High on both buffer inputs creates a high impedance, which represents no contention. A logic Low enables the buffer to drive the Longline Low. See Figure 17. Pull-up resistors are available at each end of the Longline to provide a High output when all connected buffers are non-conducting. This forms fast, wide gating functions. When data drives the inputs, and separate signals drive the 3-state control lines, these buffers form multiplexers (3-state busses). In this case, care must be used to prevent contention through multiple active buffers of conicting levels on a common line. Each horizontal Longline is also driven by a weak keeper circuit that prevents undened oating levels by maintaining the previous logic level when the line is not driven by an active buffer or a pull-up resistor. Figure 18 shows 3-state buffers, Longlines and pull-up resistors.

BIDIRECTIONAL INTERCONNECT BUFFERS

GLOBAL NET

3 VERTICAL LONG LINES PER COLUMN

I/O CLOCKS
GG GH P48

HORIZONTAL LONG LINE PULL-UP RESISTOR

HORIZONTAL LONG LINE

OSCILLATOR AMPLIFIER OUTPUT

P47

DIRECTINPUT OF P47 TO AUXILIARY BUFFER CRYSTAL OSCILLATOR BUFFER 3-STATE INPUT

HG

HH

BCL KIN

OS C

3-STATE CONTROL
.l .lk .q .ck .Q

P46

D P G M

3-STATE BUFFER

ALTERNATE BUFFER
P40 P41 P42 P43 RST
X1245

Figure 18: XACT Design Editor. An extra large view of possible interconnections in the lower right corner of the XC3020A.

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Crystal Oscillator
Figure 18 also shows the location of an internal high speed inverting amplier that may be used to implement an onchip crystal oscillator. It is associated with the auxiliary buffer in the lower right corner of the die. When the oscillator is congured by MakeBits and connected as a signal source, two special user IOBs are also congured to connect the oscillator amplier with external crystal oscillator components as shown in Figure 19. A divide by two option is available to assure symmetry. The oscillator circuit becomes active early in the conguration process to allow the oscillator to stabilize. Actual internal connection is delayed until completion of conguration. In Figure 19 the feedback resistor R1, between the output and input, biases the amplier at threshold. The inversion of the amplier, together with the R-C networks and an AT-cut series resonant crystal, produce the 360-degree phase shift of the

Pierce oscillator. A series resistor R2 may be included to add to the amplier output impedance when needed for phase-shift control, crystal resistance matching, or to limit the amplier input swing to control clipping at large amplitudes. Excess feedback voltage may be corrected by the ratio of C2/C1. The amplier is designed to be used from 1 MHz to about one-half the specied CLB toggle frequency. Use at frequencies below 1 MHz may require individual characterization with respect to a series resistance. Crystal oscillators above 20 MHz generally require a crystal which operates in a third overtone mode, where the fundamental frequency must be suppressed by an inductor across C2, turning this parallel resonant circuit to double the fundamental crystal frequency, i.e., 2/3 of the desired third harmonic frequency network. When the oscillator inverter is not used, these IOBs and their package pins are available for general user I/O.

Q Internal External

Alternate Clock Buffer

XTAL1

XTAL2 (IN) R1 Suggested Component Values R1 0.5 1 M R2 0 1 k (may be required for low frequency, phase shift and/or compensation level for crystal Q) C1, C2 10 40 pF Y1 1 20 MHz AT-cut parallel resonant 44 PIN PLCC 30 26 68 PIN PLCC 47 43 84 PIN PGA PLCC J11 57 L11 53 100 PIN CQFP PQFP 82 67 76 61 R2 Y1 C1 C2

XTAL 1 (OUT) XTAL 2 (IN)

132 PIN PGA P13 M13

160 PIN PQFP 82 76

164 PIN CQFP 105 99

175 PIN 176 PIN 208 PIN PGA TQFP PQFP T14 91 110 P15 85 100
X7064

Figure 19: Crystal Oscillator Inverter. When activated in the MakeBits program and by selecting an output network for its buffer, the crystal oscillator inverter uses two uncongured package pins and external components to implement an oscillator. An optional divide-by-two mode is available to assure symmetry.

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Conguration
Initialization Phase
An internal power-on-reset circuit is triggered when power is applied. When VCC reaches the voltage at which portions of the FPGA device begin to operate (nominally 2.5 to 3 V), the programmable I/O output buffers are 3-stated and a high-impedance pull-up resistor is provided for the user I/O pins. A time-out delay is initiated to allow the power supply voltage to stabilize. During this time the power-down mode is inhibited. The Initialization state time-out (about 11 to 33 ms) is determined by a 14-bit counter driven by a selfgenerated internal timer. This nominal 1-MHz timer is subject to variations with process, temperature and power supply. As shown in Table 1, ve conguration mode choices are available as determined by the input levels of three mode pins; M0, M1 and M2. Table 1: Conguration Mode Choices
M0 M1 M2 CCLK 0 0 0 output 0 0 1 output 0 1 0 0 1 1 output 1 0 0 1 0 1 output 1 1 0 1 1 1 input Mode Master Master reserved Master reserved Peripheral reserved Slave Data Bit Serial Byte Wide Addr. = 0000 up Byte Wide Addr. = FFFF down Byte Wide Bit Serial

In Master conguration modes, the device becomes the source of the Conguration Clock (CCLK). The beginning of conguration of devices using Peripheral or Slave modes must be delayed long enough for their initialization to be completed. An FPGA with mode lines selecting a Master conguration mode extends its initialization state using four times the delay (43 to 130 ms) to assure that all daisychained slave devices, which it may be driving, will be ready even if the master is very fast, and the slave(s) very slow. Figure 20 shows the state sequences. At the end of Initialization, the device enters the Clear state where it clears the conguration memory. The active Low, opendrain initialization signal INIT indicates when the Initialization and Clear states are complete. The FPGA tests for the absence of an external active Low RESET before it makes a nal sample of the mode lines and enters the Conguration state. An external wired-AND of one or more INIT pins can be used to control conguration by the assertion of the active-Low RESET of a master mode device or to signal a processor that the FPGAs are not yet initialized. If a conguration has begun, a re-assertion of RESET for a minimum of three internal timer cycles will be recognized and the FPGA will initiate an abort, returning to the Clear state to clear the partially loaded conguration memory words. The FPGA will then resample RESET and the mode lines before re-entering the Conguration state. During conguration, the XC3000A, XC3000L, XC3100A, and XC3100L devices check the bit-stream format for stop bits in the appropriate positions. Any error terminates the conguration and pulls INIT Low.

All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low

INIT Output = Low PWRDWN Inactive

Power Down No HDC, LDC or Pull-Up

Initialization Power-On Time Delay Active RESET

PWRDWN Active

Clear Configuration Memory

RESET Active

No

Test Mode Pins

Configuration Program Mode

Start-Up

Operational Mode

Low on DONE/PROGRAM and RESET

Active RESET Operates on User Logic Clear Is ~ 200 Cycles for the XC3020A130 to 400 s ~ 250 Cycles for the XC3030A165 to 500 s ~ 290 Cycles for the XC3042A195 to 580 s ~ 330 Cycles for the XC3064A220 to 660 s ~ 375 Cycles for the XC3090A250 to 750 s

Power-On Delay is 214 Cycles for Non-Master Mode11 to 33 ms 216 Cycles for Master Mode43 to 130 ms

X3399

Figure 20: A State Diagram of the Conguration Process for Power-up and Reprogram.

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A re-program is initiated.when a congured XC3000 series device senses a High-to-Low transition and subsequent >6 s Low level on the DONE/PROG package pin, or, if this pin is externally held permanently Low, a High-to-Low transition and subsequent >6 s Low time on the RESET package pin. The device returns to the Clear state where the conguration memory is cleared and mode lines re-sampled, as for an aborted conguration. The complete conguration program is cleared and loaded during each conguration program cycle. Length count control allows a system of multiple Field Programmable Gate Arrays, of assorted sizes, to begin operation in a synchronized fashion. The conguration program
11111111 0010 < 24-Bit Length Count > 1111 0 <Data Frame # 001 > 111 0 <Data Frame # 002 > 111 0 <Data Frame # 003 > 111 . . . . . . . . . 0 <Data Frame # 196 > 111 0 <Data Frame # 197 > 111 1111

generated by the MakePROM program of the XACTstep development system begins with a preamble of 111111110010 followed by a 24-bit length count representing the total number of conguration clocks needed to complete loading of the conguration program(s). The data framing is shown in Figure 21. All FPGAs connected in series read and shift preamble and length count in on positive and out on negative conguration clock edges. A device which has received the preamble and length count then presents a High Data Out until it has intercepted the appropriate number of data frames. When the conguration program memory of an FPGA is full and the length count does not yet compare, the device shifts any additional data through, as it did for preamble and length count. When the F{GA conguration memory is full and the length count

Dummy Bits* Preamble Code Configuration Program Length Dummy Bits (4 Bits Minimum)

Header

For XC3120 197 Configuration Data Frames (Each Frame Consists of: A Start Bit (0) A 71-Bit Data Field Three Stop Bits Postamble Code (4 Bits Minimum)
X5300

Program Data Repeated for Each Logic Cell Array in a Daisy Chain

*The LCA Device Require Four Dummy Bits Min; XACT Software Generates Eight Dummy Bits

Device Gates CLBs Row x Col IOBs Flip-flops Horizontal Longlines TBUFs/Horizontal LL Bits per Frame (including1 start and 3 stop bits) Frames Program Data = Bits x Frames + 4 bits (excludes header) PROM size (bits) = Program Data + 40-bit Header

XC3020A XC3020L XC3120A 1,000 to 1,500 64 (8 x 8) 64 256 16 9 75 197 14,779

XC3030A XC3030L XC3130A 1,500 to 2,000 100 (10 x 10) 80 360 20 11 92 241 22,176

XC3042A XC3042L XC3142A XC3142L 2,000 to 3,000 144 (12 x 12) 96 480 24 13 108 285 30,784

XC3064A XC3064L XC3164A 3,500 to 4,500 224 (16 x 14) 120 688 32 15 140 329 46,064

XC3090A XC3090L XC3190A XC3190L 5,000 to 6,000 320 (20 x 16) 144 928 40 17 172 373 64,160

XC3195A 6,500 to 7,500 484 (22 x 22) 176 1,320 44 23 188 505 94,944

14,819

22,216

30,824

46,104

64,200

94,984

Figure 21: Internal Conguration Data Structure for an FPGA. This shows the preamble, length count and data frames generated by the XACTstep Development System. The Length Count produced by the MakeBits program = [(40-bit preamble + sum of program data + 1 per daisy chain device) rounded up to multiple of 8] (2 K 4) where K is a function of DONE and RESET timing selected. An additional 8 is added if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.

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compares, the device will execute a synchronous start-up sequence and become operational. See Figure 22. Two CCLK cycles after the completion of loading conguration data, the user I/O pins are enabled as congured. As selected in MakeBits, the internal user-logic RESET is released either one clock cycle before or after the I/O pins become active. A similar timing selection is programmable for the DONE/PROG output signal. DONE/PROG may also be programmed to be an open drain or include a pull-up resistor to accommodate wired ANDing. The High During Conguration (HDC) and Low During Conguration (LDC) are two user I/O pins which are driven active while an FPGA is in its Initialization, Clear or Congure states. They and DONE/PROG provide signals for control of external logic signals such as RESET, bus enable or PROM enable during conguration. For parallel Master conguration modes, these signals provide PROM enable control and allow the data pins to be shared with user logic signals. User I/O inputs can be programmed to be either TTL or CMOS compatible thresholds. At power-up, all inputs have TTL thresholds and can change to CMOS thresholds at the completion of conguration if the user has selected CMOS thresholds. The threshold of PWRDWN and the direct clock inputs are xed at a CMOS level. If the crystal oscillator is used, it will begin operation before conguration is complete to allow time for stabilization before it is connected to the internal circuitry.

Conguration Data
Conguration data to dene the function and interconnection within a Field Programmable Gate Array is loaded from an external storage at power-up and after a re-program signal. Several methods of automatic and controlled loading of the required data are available. Logic levels applied to mode selection pins at the start of conguration time determine the method to be used. See Table 1. The data may be either bit-serial or byte-parallel, depending on the conguration mode. The different FPGAs have different sizes and numbers of data frames. To maintain compatibility between various device types, the Xilinx product families use compatible conguration formats. For the XC3020A, conguration requires 14779 bits for each device, arranged in 197 data frames. An additional 40 bits are used in the header. See Figure 22. The specic data format for each device is produced by the MakeBits command of the development system and one or more of these les can then be combined and appended to a length count preamble and be transformed into a PROM format le by the MakePROM command of the XACTstep development system. A compatibility exception precludes the use of an XC2000-series device as the master for XC3000-series devices if their DONE or RESET are programmed to occur after their outputs become active. The Tie Option of the MakeBits program denes output levels of unused blocks of a design and connects these to unused routing resources. This prevents indeterminate levels that might produce parasitic
Postamble Last Frame

Data Frame 12 24 4 3

3 STOP

DIN

Stop

Preamble

Length Count

Data

Start Bit Start Bit The configuration data consists of a composite * 40-bit preamble/length count, followed by one or more concatenated FPGA programs, separated by 4-bit postambles. An additional final postamble bit is added for each slave device and the result rounded up to a byte boundary. The length count is two less than the number of resulting bits. Timing of the assertion of DONE and termination of the INTERNAL RESET may each be programmed to occur one cycle before or after the I/O outputs become active. Heavy lines indicate the default condition

Length Count*

Weak Pull-Up

I/O Active

PROGRAM

DONE

Internal Reset
X5988

Figure 22: Conguration and Start-up of One or More FPGAs.

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supply currents. If unused blocks are not sufcient to complete the tie, the Flagnet command of EditLCA can be used to indicate nets which must not be used to drive the remaining unused routing, as that might affect timing of user nets. Norestore will retain the results of tie for timing analysis with Querynet before Restore returns the design to the untied condition. Tie can be omitted for quick breadboard iterations where a few additional milliamps of Icc are acceptable. The conguration bitstream begins with eight High preamble bits, a 4-bit preamble code and a 24-bit length count. When conguration is initiated, a counter in the FPGA is set to zero and begins to count the total number of conguration clock cycles applied to the device. As each conguration data frame is supplied to the device, it is internally assembled into a data word, which is then loaded in parallel into one word of the internal conguration memory array. The conguration loading process is complete when the current length count equals the loaded length count and the required conguration program data frames have been written. Internal user ip-ops are held Reset during conguration. Two user-programmable pins are dened in the uncongured Field Programmable Gate Array. High During Conguration (HDC) and Low During Conguration (LDC) as well as DONE/PROG may be used as external control signals during conguration. In Master mode congurations it is convenient to use LDC as an active-Low EPROM Chip Enable. After the last conguration data bit is loaded and the length count compares, the user I/O pins become active. Options in the MakeBits program allow timing choices of one clock earlier or later for the timing of the end of the internal logic RESET and the assertion of the DONE signal. The open-drain DONE/PROG output can be ANDtied with multiple devices and used as an active-High READY, an active-Low PROM enable or a RESET to other portions of the system. The state diagram of Figure 20 illustrates the conguration process.

for Master High mode. These two modes provide address compatibility with microprocessors which begin execution from opposite ends of memory.

Peripheral Mode
Peripheral mode provides a simplied interface through which the device may be loaded byte-wide, as a processor peripheral. Figure 27 shows the peripheral mode connections. Processor write cycles are decoded from the common assertion of the active low Write Strobe (WS), and two active low and one active high Chip Selects (CS0, CS1, CS2). The FPGA generates a conguration clock from the internal timing generator and serializes the parallel input data for internal framing or for succeeding slaves on Data Out (DOUT). A output High on READY/BUSY pin indicates the completion of loading for each byte when the input register is ready for a new byte. As with Master modes, Peripheral mode may also be used as a lead device for a daisychain of slave devices.

Slave Serial Mode

Slave Serial mode provides a simple interface for loading the Field Programmable Gate Array conguration as shown in Figure 29. Serial data is supplied in conjunction with a synchronizing input clock. Most Slave mode applications are in daisy-chain congurations in which the data input is driven from the previous FPGAs data out, while the clock is supplied by a lead device in Master or Peripheral mode. Data may also be supplied by a processor or other special circuits.

Daisy Chain
The XACTstep development system is used to create a composite conguration for selected FPGAs including: a preamble, a length count for the total bitstream, multiple concatenated data programs and a postamble plus an additional ll bit per device in the serial chain. After loading and passing-on the preamble and length count to a possible daisy-chain, a lead device will load its conguration data frames while providing a High DOUT to possible down-stream devices as shown in Figure 25. Loading continues while the lead device has received its conguration program and the current length count has not reached the full value. The additional data is passed through the lead device and appears on the Data Out (DOUT) pin in serial form. The lead device also generates the Conguration Clock (CCLK) to synchronize the serial output data and data in of down-stream FPGAs. Data is read in on DIN of slave devices by the positive edge of CCLK and shifted out the DOUT on the negative edge of CCLK. A parallel Master mode device uses its internal timing generator to produce an internal CCLK of 8 times its EPROM address rate, while a Peripheral mode device produces a burst of 8 CCLKs for each chip select and write-strobe cycle. The internal timing generator continues to operate for general timing and synchronization of inputs in all modes.

Conguration Modes
Master Mode
In Master mode, the FPGA automatically loads conguration data from an external memory device. There are three Master modes that use the internal timing source to supply the conguration clock (CCLK) to time the incoming data. Master Serial mode uses serial conguration data supplied to Data-in (DIN) from a synchronous serial source such as the Xilinx Serial Conguration PROM shown in Figure 23. Master Parallel Low and High modes automatically use parallel data supplied to the D0D7 pins in response to the 16-bit address generated by the FPGA. Figure 25 shows an example of the parallel Master mode connections required. The HEX starting address is 0000 and increments for Master Low mode and it is FFFF and decrements

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Special Conguration Functions

The conguration data includes control over several special functions in addition to the normal user logic functions and interconnect. Input thresholds Readback disable DONE pull-up resistor DONE timing RESET timing Oscillator frequency divided by two

tioned above can be considered the Start bit of the rst frame. All data frames must be read back to complete the process and return the Mode Select and CCLK pins to their normal functions. Readback data includes the current state of each CLB ipop, each input ip-op or latch, and each device pad. These data are imbedded into unused conguration bit positions during Readback. This state information is used by the XACTstep development system In-Circuit Verier to provide visibility into the internal operation of the logic while the system is operating. To readback a uniform time-sample of all storage elements, it may be necessary to inhibit the system clock.

Each of these functions is controlled by conguration data bits which are selected as part of the normal XACTstep development system bitstream generation process.

Reprogram
To initiate a re-programming cycle, the dual-function pin DONE/PROG must be given a High-to-Low transition. To reduce sensitivity to noise, the input signal is ltered for two cycles of the FPGA internal timing generator. When reprogram begins, the user-programmable I/O output buffers are disabled and high-impedance pull-ups are provided for the package pins. The device returns to the Clear state and clears the conguration memory before it indicates initialized. Since this Clear operation uses chip-individual internal timing, the master might complete the Clear operation and then start conguration before the slave has completed the Clear operation. To avoid this problem, the slave INIT pins must be AND-wired and used to force a RESET on the master (see Figure 25). Reprogram control is often implemented using an external open-collector driver which pulls DONE/PROG Low. Once a stable request is recognized, the DONE/PROG pin is held Low until the new conguration has been completed. Even if the re-program request is externally held Low beyond the conguration period, the FPGA will begin operation upon completion of conguration.

Input Thresholds
Prior to the completion of conguration all FPGA input thresholds are TTL compatible. Upon completion of conguration, the input thresholds become either TTL or CMOS compatible as programmed. The use of the TTL threshold option requires some additional supply current for threshold shifting. The exception is the threshold of the PWRDWN input and direct clocks which always have a CMOS input. Prior to the completion of conguration the user I/O pins each have a high impedance pull-up. The conguration program can be used to enable the IOB pull-up resistors in the Operational mode to act either as an input load or to avoid a oating input on an otherwise unused pin.

Readback
The contents of a Field Programmable Gate Array may be read back if it has been programmed with a bitstream in which the Readback option has been enabled. Readback may be used for verication of conguration and as a method of determining the state of internal logic nodes during debugging. There are three options in generating the conguration bitstream. Never inhibits the Readback capability. One-time, inhibits Readback after one Readback has been executed to verify the conguration. On-command allows unrestricted use of Readback.

DONE Pull-up
DONE/PROG is an open-drain I/O pin that indicates the FPGA is in the operational state. An optional internal pullup resistor can be enabled by the user of the XACT development system when MakeBits is executed. The DONE/ PROG pins of multiple FPGAs in a daisy-chain may be connected together to indicate all are DONE or to direct them all to reprogram.

Readback is accomplished without the use of any of the user I/O pins; only M0, M1 and CCLK are used. The initiation of Readback is produced by a Low to High transition of the M0/RTRIG (Read Trigger) pin. The CCLK input must then be driven by external logic to read back the conguration data. The rst three Low-to-High CCLK transitions clock out dummy data. The subsequent Low-to-High CCLK transitions shift the data frame information out on the M1/ RDATA (Read Data) pin. Note that the logic polarity is always inverted, a zero in conguration becomes a one in Readback, and vice versa. Note also that each Readback frame has one Start bit (read back as a one) but, unlike in conguration, each Readback frame has only one Stop bit (read back as a zero). The third leading dummy bit men-

DONE Timing
The timing of the DONE status signal can be controlled by a selection in the MakeBits program to occur either a CCLK cycle before, or after, the outputs going active. See Figure 22. This facilitates control of external functions such as a PROM enable or holding a system in a wait state.

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RESET Timing
As with DONE timing, the timing of the release of the internal reset can be controlled by a selection in the MakeBits program to occur either a CCLK cycle before, or after, the outputs going active. See Figure 22. This reset keeps all user programmable ip-ops and latches in a zero state during conguration.

but with incorrect conguration and the possibility of internal contention. An XC3000A/XC3100A/XC3000L/XC3100L device starts any new frame only if the three preceding bits are all ones. If this check fails, it pulls INIT Low and stops the internal conguration, although the Master CCLK keeps running. The user must then start a new conguration by applying a >6 s Low level on RESET. This simple check does not protect against random bit errors, but it offers almost 100 percent protection against erroneous conguration les, defective conguration data sources, synchronization errors between conguration source and FPGA, or PC-board level defects, such as broken lines or solder-bridges.

Crystal Oscillator Division

A selection in the MakeBits program allows the user to incorporate a dedicated divide-by-two ip-op between the crystal oscillator and the alternate clock line. This guarantees a symmetrical clock signal. Although the frequency stability of a crystal oscillator is very good, the symmetry of its waveform can be affected by bias or feedback drive.

Bitstream Error Checking

Bitstream error checking protects against erroneous conguration. Each Xilinx FPGA bitstream consists of a 40-bit preamble, followed by a device-specic number of data frames. The number of bits per frame is also device-specic; however, each frame ends with three stop bits (111) followed by a start bit for the next frame (0). All devices in all XC3000 families start reading in a new frame when they nd the rst 0 after the end of the previous frame. XC3000 device does not check for the correct stop bits, but XC3000A/XC3100A/XC3000L and XC3100L devices check that the last three bits of any frame are actually 111. Under normal circumstances, all these FPGAs behave the same way; however, if the bitstream is corrupted, an XC3000 device will always start a new frame as soon as it nds the rst 0 after the end of the previous frame, even if the data is completely wrong or out-of-sync. Given sufcient zeros in the data stream, the device will also go Done,

Reset Spike Protection

A separate modication slows down the RESET input before conguration by using a two-stage shift register driven from the internal clock. It tolerates submicrosecond High spikes on RESET before conguration. The XC3000 master can be connected like an XC4000 master, but with its RESET input used instead of INIT. (On XC3000, INIT is output only).

Soft Start-up
After conguration, the outputs of all FPGAs in a daisychain become active simultaneously, as a result of the same CCLK edge. In the original XC3000/3100 devices, each output becomes active in either fast or slew-rate limited mode, depending on the way it is congured. This can lead to large ground-bounce signals. In XC3000A/ XC3000L/XC31000A/XC3100L devices, all outputs become active rst in slew-rate limited mode, reducing the ground bounce. After this soft start-up, each individual output slew rate is again controlled by the respective conguration bit.

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Conguration Timing
This section describes the conguration modes in detail.

Master Serial Mode

In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. This puts the next data bit on the SPROM data output, connected to the DIN pin. The lead FPGA accepts this data on the subsequent rising CCLK edge. The lead FPGA then presents the preamble data (and all data that overows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that
* IF READBACK IS ACTIVATED, A 5-k RESISTOR IS REQUIRED IN SERIES WITH M1 DURING CONFIGURATION THE 5 k M2 PULL-DOWN RESISTOR OVERCOMES THE INTERNAL PULL-UP, BUT IT ALLOWS M2 TO BE USER I/O. +5 V

DOUT changes on the falling CCLK edge, and the next device in the daisy-chain accepts data on the subsequent rising CCLK edge. The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is congured as user-I/O, but LDC is then restricted to be a permanently High user output. Using DONE also avoids contention on DIN, provided the early DONE option is invoked.

M0

M1

PWRDWN TO DIN OF OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS TO CCLK OF OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS

DOUT M2 HDC LDC GENERALPURPOSE USER I/O PINS INIT

RESET

Figure 23: Master Serial Mode Circuit Diagram

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OTHER I/O PINS

TO CCLK OF OPTIONAL SLAVE LCAs WITH IDENTICAL CONFIGURATIONS TO DIN OF OPTIONAL SLAVE LCAs WITH IDENTICAL CONFIGURATIONS

XC3000 FPGA DEVICE

+5 V

RESET VCC DIN CCLK D/P

INIT

VPP DATA SCP CEO CLK CE CASCADED SERIAL MEMORY

DATA CLK CE OE/RESET XC17xx

OE/RESET

(LOW RESETS THE XC17xx ADDRESS POINTER)

X5989

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CCLK (Output) 2 TCKDS 1 Serial Data In TDSCK n n+1 n+2

Serial DOUT (Output)

n3

n2

n1

n
X3223

CCLK

Description Data In setup Data In hold

1 2

Symbol TDSCK CKDS

Min 60 0

Max

Units ns ns

Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, conguration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Conguration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is High. 3. Master-serial-mode timing is based on slave-mode testing.

Figure 24: Master Serial Mode Programming Switching Characteristics

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Master Parallel Mode

In Master Parallel mode, the lead FPGA directly addresses an industry-standard byte-wide EPROM and accepts eight data bits right before incrementing (or decrementing) the address outputs. The eight data bits are serialized in the lead FPGA, which then presents the preamble data (and all data that overows the lead device) on the DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data, and also changes the EPROM address, until the falling CCLK edge that makes the LSB (D0) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next device in the daisy chain accepts data on the subsequent rising CCLK edge.

* If Readback is

+5 V

+5 V

+5 V

*
M0 M1PWRDWN CCLK DIN DOUT FPGA Slave #1 5 k

+5 V

*
M0 M1PWRDWN CCLK DIN DOUT FPGA Slave #n 5 k

Activated, a 5-k Resistor is Required in Series With M1 5 k

M0 M1PWRDWN CCLK DOUT M2 HDC RCLK

...
M2 HDC LDC GeneralPurpose User I/O Pins

M2 HDC LDC GeneralPurpose User I/O Pins

GeneralPurpose User I/O Pins

A15 A14 A13

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OE N.C. CE 8 D7 D6 D5 D4 D3 D2 D1 D0 D/P RESET EPROM

Other I/O Pins FPGA Master D7 D6 D5 D4 D3 D2 D1 D0

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D/P

Other I/O Pins INIT

Other I/O Pins INIT D/P Reset

...

...

.....
Reprogram System Reset

Note: XC2000 Devices Do Not Have INIT to Hold Off a Master Device. Reset of a Master Device Should be Asserted by an External Timing Circuit to Allow for LCA CCLK Variations in Clear State Time.

RESET

INIT

+5 V Open Collector 5 k Each

X5990

Figure 25: Master Parallel Mode Circuit Diagram

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A0-A15 (output)

Address for Byte n

Address for Byte n + 1 1 TRAC

D0-D7

Byte 2 TDRC 3 TRCD

RCLK (output) 7 CCLKs CCLK

CCLK (output)

DOUT (output)

D6 Byte n - 1

D7
X5380

RCLK

Description To address valid To data setup To data hold RCLK High RCLK Low

1 2 3

Symbol TRAC TDRC TRCD TRCH TRCL

Min 0 60 0 600 4.0

Max 200

Units ns ns ns ns s

Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, conguration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Conguration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is High.

This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Figure 26: Master Parallel Mode Programming Switching Characteristics

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Peripheral Mode
Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS inputs to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a double-buffered UART-like parallel-to-serial converter and is serially shifted into the internal logic. The lead FPGA presents the preamble data (and all data that overows the lead device) on the DOUT pin. The Ready/Busy output from the lead device acts as a handshake signal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High again
CONTROL SIGNALS ADDRESS BUS DATA BUS 8 M0 D07

when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. The length of the BUSY signal depends on the activity in the UART. If the shift register had been empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered.
+5 V * 5 k * IF READBACK IS ACTIVATED, A 5-k RESISTOR IS REQUIRED IN SERIES WITH M1

M1 PWR DWN CCLK

D07

DOUT ADDRESS DECODE LOGIC CS0 M2 HDC FPGA CS1 CS2 OTHER I/O PINS RDY/BUSY WS INIT REPROGRAM OC D/P RESET LDC

OPTIONAL DAISY-CHAINED FPGAs WITH DIFFERENT CONFIGURATIONS

...

+5 V

GENERALPURPOSE USER I/O PINS

...
X5991

Figure 27: Peripheral Mode Circuit Diagram

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WRITE TO FPGA WS, CS0, CS1

CS2 TCA

2 TDC D0-D7 Valid

TCD

CCLK 4 TWTRB RDY/BUSY TBUSY 6

DOUT

D6

D7
Previous Byte

D0

D1

D2
New Byte
X5992

WRITE

Description Effective Write time required (Assertion of CS0, CS1, CS2, WS) DIN Setup time required DIN Hold time required RDY/BUSY delay after end of WS Earliest next WS after end of BUSY

1 2 3 4 5 6

Symbol TCA TDC TCD TWTRB TRBWT TBUSY

Min 100 60 0

Max

Units ns ns ns ns ns

60 0 2.5 9

RDY

BUSY Low time generated

CCLK periods

Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, conguration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Conguration must be delayed until the INIT of all FPGAs is High. 3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the phase of the internal timing generator for CCLK. 4. CCLK and DOUT timing is tested in slave mode. 5. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data.

Note: This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY will go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted immediately after the end of BUSY. Figure 28: Peripheral Mode Programming Switching Characteristics

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Slave Serial Mode

In Slave Serial mode, an external signal drives the CCLK input(s) of the FPGA(s). The serial conguration bitstream must be available at the DIN input of the lead FPGA a short set-up time before each rising CCLK edge. The lead device then presents the preamble data (and all data that overows the lead device) on its DOUT pin. There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next device in the daisy-chain accepts data on the subsequent rising CCLK edge.
* If Readback is Activated, a 5-k Resistor is Required in Series with M1 5 k Optional Daisy-Chained LCAs with Different Configurations

+5 V

M0 Micro Computer STRB D0 D1 I/O Port D2 D3 D4 D5 D6 D7 RESET INIT RESET +5 V CCLK DIN

M1

PWRDWN

M2 DOUT HDC LDC GeneralPurpose User I/O Pins

FPGA

Other I/O Pins D/P

...
X5993

Figure 29: Slave Serial Mode Circuit Diagram

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DIN 1 TDCC CCLK

Bit n 2 TCCD

Bit n + 1 5 TCCL

4 TCCH DOUT (Output) Bit n - 1

3 TCCO Bit n
X5379

Description To DOUT DIN setup DIN hold High time Low time (Note 1) Frequency

3 1 2 4 5

Symbol TCCO TDCC TCCD TCCH TCCL FCC

Min

Max 100

Units ns ns ns s s MHz

CCLK

60 0 0.05 0.05

5.0 10

Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA. 2. Conguration must be delayed until the INIT of all FPGAs is High. 3. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, conguration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L).

Figure 30: Slave Serial Mode Programming Switching Characteristics

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Program Readback Switching Characteristics

DONE/PROG (OUTPUT) 1 TRTH RTRIG (M0) 2 TRTCC 4 TCCL 4 TCCL

CCLK(1) 5 3 TCCRD M1 Input/ RDATA Output HI-Z VALID READBACK OUTPUT VALID READBACK OUTPUT
X6116

RTRIG CCLK

Description RTRIG High RTRIG setup RDATA delay High time Low time

1 2 3 4 5

Symbol TRTH TRTCC TCCRD TCCHR TCCLR

Min 250 200 0.5 0.5

Max

100 5

Units ns ns ns s s

Notes: 1. 2. 3. 4.

During Readback, CCLK frequency may not exceed 1 MHz. RETRIG (M0 positive transition) shall not be done until after one clock following active I/O pins. Readback should not be initiated until conguration is complete. TCCLR is 5 s min to 15 s max for XC3000L.

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General XC3000 Series Switching Characteristics

4 TMRW RESET 2 TMR 3 TRM M0/M1/M2 5 TPGW DONE/PROG 6 TPGI INIT (Output) User State Clear State Configuration State

PWRDWN Note 3 VCC (Valid) VCCPD

X5387

Description M0, M1, M2 setup time required RESET (2) M0, M1, M2 hold time required RESET Width (Low) req. for Abort Width (Low) required for Re-config. DONE/PROG INIT response after D/P is pulled Low PWRDWN (3) Power Down VCC

2 3 4 5 6

Symbol TMR TRM TMRW TPGW TPGI VCCPD

Min 1 4.5 6 6 2.3

Max

Units s s s s s V

Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, conguration can be delayed by holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a nonmonotonically rising VCC may require a >1-s High level on RESET, followed by a >6-s Low level on RESET and D/P after Vcc has reached 4.0 V (2.5 V for XC3000L). 2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay conguration. The specied hold time is caused by a shift-register lter slowing down the response to RESET during conguration. 3. PWRDWN transitions must occur while VCC >4.0 V(2.5 V for XC3000L).

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Device Performance
The XC3000 families of FPGAs can achieve very high performance. This is the result of A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS SRAMs. Careful optimization of transistor geometries, circuit design, and lay-out, based on years of experience with the XC3000 family. A look-up table based, coarse-grained architecture that can collapse multiple-layer combinatorial logic into a single function generator. One CLB can implement up to four layers of conventional logic in as little as 1.5 ns.

duced by storage elements. Loading of a logic-block output is limited only by the resulting propagation delay of the larger interconnect network. Speed performance of the logic block is a function of supply voltage and temperature. See Figure 32. Interconnect performance depends on the routing resources used to implement the signal path. Direct interconnects to the neighboring CLB provide an extremely fast path. Local interconnects go through switch matrices (magic boxes) and suffer an RC delay, equal to the resistance of the pass transistor multiplied by the capacitance of the driven metal line. Longlines carry the signal across the length or breadth of the chip with only one access delay. Generous on-chip signal buffering makes performance relatively insensitive to signal fan-out; increasing fan-out from 1 to 8 changes the CLB delay by only 10%. Clocks can be distributed with two low-skew clock distribution networks. The tools in the XACTstep Development System used to place and route a design in an XC3000 FPGA automatically calculate the actual maximum worst-case delays along each signal path. This timing information can be back-annotated to the designs netlist for use in timing simulation or examined with X-Delay, a static timing analyzer. Actual system performance is applications dependent. The maximum clock rate that can be used in a system is determined by the critical path delays within that system. These delays are combinations of incremental logic and routing delays, and vary from design to design. In a synchronous system, the maximum clock rate depends on the number of combinatorial logic layers between re-synchronizing ipops. Figure 33 shows the achievable clock rate as a function of the number of CLB layers.

Actual system performance is determined by the timing of critical paths, including the delay through the combinatorial and sequential logic elements within CLBs and IOBs, plus the delay in the interconnect routing. The AC-timing specications state the worst-case timing parameters for the various logic resources available in the XC3000-families architecture. Figure 31 shows a variety of elements involved in determining system performance. Logic block performance is expressed as the propagation time from the interconnect point at the input to the block to the output of the block in the interconnect area. Since combinatorial logic is implemented with a memory lookup table within a CLB, the combinatorial delay through the CLB, called TILO, is always the same, regardless of the function being implemented. For the combinatorial logic function driving the data input of the storage element, the critical timing is data set-up relative to the clock edge provided to the ip-op element. The delay from the clock source to the output of the logic block is critical in the timing signals pro-

Clock to Output TCKO CLB

Combinatorial TILO CLB Logic Logic

Setup TICK CLB IOB TOP

PAD

(K) CLOCK IOB PAD T PID

(K)

TCKO

TOKPO
X3178

Figure 31: Primary Block Speed Factors. Actual timing is a function of various block factors combined with routing. factors. Overall performance can be evaluated with the XDelay timing calculator or by an optional simulation.

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SPECIFIED WORST-CASE VALUES

1.00
C MER IAL (4.7 5 V)

MAX

COM

MAX

MILIT

ARY

(4.5

V)

0.80
NORMALIZED DELAY

0.60

TYPICAL COMMERCIAL (+ 5.0 V, 25C)

TYPICAL MILITARY 0.40

75 V) ERCIAL (4. MIN COMM 25 V) ERCIAL (5. MM CO N MI
MIN MILIT ARY (4.5 V)

(5.5 V) MIN MILITARY

0.20

55

40

20

25

40

70

80

100

125 X6094

TEMPERATURE (C)

Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations

Power
300 250 System Clock (MHz) 200 150 100 50 XC3000A--6 0 CLB Levels: 4 CLBs Gate Levels: (4-16) XC3100A-3

Power Distribution
Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated VCC and ground ring surrounding the logic array provides power to the I/O drivers. An independent matrix of VCC and groundlines supplies the interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically a 0.1-F capacitor connected near the VCC and ground pins will provide adequate decoupling. Output buffers capable of driving the specied 4- or 8-mA loads under worst-case conditions may be capable of driving as much as 25 to 30 times that current in a best case. Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direction. It may also be benecial to locate heavily loaded output buffers near the ground pads. The I/O Block output buffers have a slew-limited mode which should be used where output rise and fall times are not speed critical. Slew-limited outputs maintain their dc drive capability, but generate less external reections and internal noise.

3 CLBs (3-12)

2 CLBs (2-8)

1 CLB (1-4)

Toggle Rate
X7065

Figure 33: Clock Rate as a Function of Logic Complexity (Number of Combinational Levels between Flip-Flops)

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Dynamic Power Consumption

One CLB driving three local interconnects One global clock buffer and clock line One device output with a 50 pF load XC3042A 0.25 2.25 1.25 XC3042L 0.17 1.40 1.25 XC3142A 0.25 1.70 1.25 mW per MHz mW per MHz mW per MHz

Power Consumption
The Field Programmable Gate Array exhibits the low power consumption characteristic of CMOS ICs. For any design, the conguration option of TTL chip input threshold requires power for the threshold reference. The power required by the static memory cells that hold the conguration data is very low and may be maintained in a powerdown mode. Typically, most of power dissipation is produced by external capacitive loads on the output buffers. This load and frequency dependent power is 25 W/pF/MHz per output. Another component of I/O power is the external dc loading on all output pins. Internal power dissipation is a function of the number and size of the nodes, and the frequency at which they change. In an FPGA, the fraction of nodes changing on a given clock is typically low (10-20%). For example, in a long binary counter, the total activity of all counter ip-ops is equivalent to that of only two CLB outputs toggling at the clock frequency. Typical global clock-buffer power is between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz for the XC3090A. The internal capacitive load is more a function of interconnect than fan-out. With a typical load of three general interconnect segments, each CLB output requires about 0.25 mW per MHz of its output frequency. Because the control storage of the FPGA is CMOS static memory, its cells require a very low standby current for data retention. In some systems, this low data retention current characteristic can be used as a method of preserving congurations in the event of a primary power loss. The FPGA has built in powerdown logic which, when activated, will disable normal operation of the device and retain only the conguration data. All internal operation is suspended and output buffers are placed in their high-impedance state with no pull-ups. Different from the XC3000 family which can be powered down to a current consumption of a few microamps, the XC3100A draws 5 mA, even in power-down. This makes power-down operation less meaningful. In contrast, ICCPD for the XC3000L is only 10 A. To force the FPGA into the Powerdown state, the user must pull the PWRDWN pin Low and continue to supply a retention voltage to the VCC pins. When normal power is restored, VCC is elevated to its normal operating voltage and PWRDWN is returned to a High. The FPGA resumes operation with the same internal sequence that occurs at the conclusion of conguration. Internal-I/O and logic-block storage elements will be reset, the outputs will become enabled and the DONE/PROG pin will be released. When VCC is shut down or disconnected, some power might unintentionally be supplied from an incoming signal driving an I/O pin. The conventional electrostatic input protection is implemented with diodes to the supply and ground. A positive voltage applied to an input (or output) will cause the positive protection diode to conduct and drive the VCC connection. This condition can produce invalid power conditions and should be avoided. A large series resistor might be used to limit the current or a bipolar buffer may be used to isolate the input signal.

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Pin Descriptions
Permanently Dedicated Pins
VCC Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight (depending on package type) connections to ground. All must be connected. PWRDWN A Low on this CMOS-compatible input stops all internal activity, but retains conguration. All ip-ops and latches are reset, all outputs are 3-stated, and all inputs are interpreted as High, independent of their actual level. When PWDWN returns High, the FPGA becomes operational with DONE Low for two cycles of the internal 1-MHz clock. Before and during conguration, PWRDWN must be High. If not used, PWRDWN must be tied to VCC. RESET This is an active Low input which has three functions. Prior to the start of conguration, a Low input will delay the start of the conguration process. An internal circuit senses the application of power and begins a minimal time-out cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and conguration begins. If RESET is asserted during a conguration, the FPGA is re-initialized and restarts the conguration at the termination of RESET. If RESET is asserted after conguration is complete, it provides a global asynchronous RESET of all IOB and CLB storage elements of the FPGA. CCLK During conguration, Conguration Clock is an output of an FPGA in Master mode or Peripheral mode, but an input in Slave mode. During Readback, CCLK is a clock input for shifting conguration data out of the FPGA. CCLK drives dynamic circuitry inside the FPGA. The Low time may, therefore, not exceed a few microseconds. When used as an input, CCLK must be parked High. An internal pull-up resistor maintains High when the pin is not being driven. DONE/PROG (D/P) DONE is an open-drain output, congurable with or without an internal pull-up resistor of 2 to 8 k . At the completion of conguration, the FPGA circuitry becomes active in a synchronous order; DONE is programmed to go active High one cycle either before or after the outputs go active.

Once conguration is done, a High-to-Low transition of this pin will cause an initialization of the FPGA and start a reconguration. M0/RTRIG As Mode 0, this input is sampled on power-on to determine the power-on delay (214 cycles if M0 is High, 216 cycles if M0 is Low). Before the start of conguration, this input is again sampled together with M1, M2 to determine the conguration mode to be used. A Low-to-High input transition, after conguration is complete, acts as a Read Trigger and initiates a Readback of conguration and storage-element data clocked by CCLK. By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a single Readback, or be inhibited altogether. M1/RDATA As Mode 1, this input and M0, M2 are sampled before the start of conguration to establish the conguration mode to be used. If Readback is never used, M1 can be tied directly to ground or VCC. If Readback is ever used, M1 must use a 5-k resistor to ground or VCC, to accommodate the RDATA output. As an active-Low Read Data, after conguration is complete, this pin is the output of the Readback data.

User I/O Pins That Can Have Special Functions

M2 During conguration, this input has a weak pull-up resistor. Together with M0 and M1, it is sampled before the start of conguration to establish the conguration mode to be used. After conguration, this pin is a user-programmable I/O pin. HDC During conguration, this output is held at a High level to indicate that conguration is not yet complete. After conguration, this pin is a user-programmable I/O pin. LDC During Conguration, this output is held at a Low level to indicate that the conguration is not yet complete. After conguration, this pin is a user-programmable I/O pin. LDC is particularly useful in Master mode as a Low enable for an EPROM, but it must then be programmed as a High after conguration. INIT This is an active Low open-drain output with a weak pull-up and is held Low during the power stabilization and internal clearing of the conguration memory. It can be used to indicate status to a conguring microprocessor or, as a wired

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AND of several slave mode devices, a hold-off signal for a master mode device. After conguration this pin becomes a user-programmable I/O pin. BCLKIN This is a direct CMOS level input to the alternate clock buffer (Auxiliary Buffer) in the lower right corner. XTL1 This user I/O pin can be used to operate as the output of an amplier driving an external crystal and bias circuitry. XTL2 This user I/O pin can be used as the input of an amplier connected to an external crystal and bias circuitry. The I/O Block is left uncongured. The oscillator conguration is activated by routing a net from the oscillator buffer symbol output and by the MakeBits program. CS0, CS1, CS2, WS These four inputs represent a set of signals, three active Low and one active High, that are used to control conguration-data entry in the Peripheral mode. Simultaneous assertion of all four inputs generates a Write to the internal data buffer. The removal of any assertion clocks in the D0D7 data. In Master-Parallel mode, WS and CS2 are the A0 and A1 outputs. After conguration, these pins are userprogrammable I/O pins. RDY/BUSY During Peripheral Parallel mode conguration this pin indicates when the chip is ready for another byte of data to be written to it. After conguration is complete, this pin becomes a user-programmed I/O pin. RCLK During Master Parallel mode conguration, each change on the A0-15 outputs is preceded by a rising edge on RCLK, a redundant output signal. After conguration is complete, this pin becomes a user-programmed I/O pin.

D0-D7 This set of eight pins represents the parallel conguration byte for the parallel Master and Peripheral modes. After conguration is complete, they are user-programmed I/O pins. A0-A15 During Master Parallel mode, these 16 pins present an address output for a conguration EPROM. After conguration, they are user-programmable I/O pins. DIN During Slave or Master Serial conguration, this pin is used as a serial-data input. In the Master or Peripheral conguration, this is the Data 0 input. After conguration is complete, this pin becomes a user-programmed I/O pin. DOUT During conguration this pin is used to output serial-conguration data to the DIN pin of a daisy-chained slave. After conguration is complete, this pin becomes a user-programmed I/O pin. TCLKIN This is a direct CMOS-level input to the global clock buffer. This pin can also be congured as a user programmable I/O pin. However, since TCLKIN is the preferred input to the global clock net, and the global clock net should be used as the primary clock source, this pin is usually the clock input to the chip.

Unrestricted User I/O Pins

I/O An I/O pin may be programmed by the user to be an Input or an Output pin following conguration. All unrestricted I/O pins, plus the special pins mentioned on the following page, have a weak pull-up resistor of 50 k to 100 k that becomes active as soon as the device powers up, and stays active until the end of conguration.

Note: Before and during conguration, all outputs that are not used for the conguration process are 3-stated with a 50 k to 100 k pull-up resistor.

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Pin Functions During Conguration

Conguration Mode <M2:M1:M0> SLAVE SERIAL <1:1:1> POWR DWN (I) MASTERSERIAL <0:0:0> POWER DWN (I) MASTERHIGH <1:1:0> POWER DWN (I) MASTERLOW <1:0:0> POWER DWN (I)

***

**

****
User Function POWER DWN (1) RDATA RTRIG (I) I/O I/O I/O I/O GND XTL2 OR I/O RESET (I) I/O XTL1 OR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CCLK (I) I/O I/O I/O I/O 5 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O All Others XC3x20A etc. X X X X X X X X X X X X X X XC3x30A etc. XC3x42A etc. XC3x64A etc. XC3x90A etc. XC3195A

PERIPH <1:0:1> POWER DWN (I)

100 44 64 68 84 84 100 VQFP 132 144 160 175 176 208 223 PLCC VQFP PLCC PLCC PGA PQFP TQFP PGA TQFP PQFP PGA TQFP PQFP PGA

7 16 17 18 19 20 22 23 26 27 28 30

17 31 32 33 34 36 40 41 47 48 49 50 51 52 53 54 55 57 58 59 60 61

10 25 26 27 28 30 34 35 43 44 45 46 47 48 49 50 51 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 2 3 4 5 6 7 8 9 X

12 31 32 33 34 36 42 43 53 54 55 56 57 58 60 61 62 65 66 67 70 71 72 73 74 75 76 77 78 81 82 83 84 2 3 4 5 8 9 10 11 X X X X** X**

B2 J2 L1 K2 K3 L3 K6 J6 L11 K10 J10 K11 J11 H10 F10 G10 G11 F11 E11 E10 D10 C11 B11 C10 A11 B10 B9 A10 A9 B6 B7 A7 C7 A6 A5 B5 C5 A3 A2 B3 A1 X X X

29 52 54 56 57 59 65 66 76 78 80 81 82 83 87 88 89 92 93 94 98 99 100 1 2 5 6 8 9 12 13 14 15 17 18 19 20 23 24 25 26 X X X

26 49 51 53 54 56 62 63 73 75 77 78 79 80 84 85 86 89 90 91 95 96 97 98 99 2 3 5 6 9 10 11 12 14 15 16 17 20 21 22 26

A1 B13 A14 C13 B14 D14 G14 H12 M13 P14 N13 M12 P13 N11 M9 N9 N8 N7 P6 M6 M5 N4 N2 M3 P1 M2 N1 L2 L1 K1 J2 H1 H2 G2 G1 F2 E1 D1 D2 B1 C2

1 36 38 40 41 45 53 55 69 71 73 74 75 78 84 85 88 92 93 96 102 103 106 107 108 111 112 115 116 119 120 123 124 128 129 133 134 137 138 141 142

159 40 42 44 45 49 59 61 76 78 80 81 82 86 92 93 96 102 103 106 114 115 119 120 121 124 125 128 129 132 133 136 137 141 142 147 148 151 152 155 156

B2 B14 B15 C15 E14 D16 H15 J14 P15 R15 R14 N13 T14 P12 T11 R10 R9 P8 R8 R7 R5 P5 R3 N4 R2 P2 M3 P1 N1 M1 L2 K2 K1 H2 H1 F2 E1 D1 C1 E3 C2

1 45 47 49 50 54 65 67 85 87 89 90 91 96 102 103 108 112 113 118 124 125 130 131 132 135 136 140 141 146 147 150 151 156 157 164 165 169 170 173 174

3 48 50 56 57 61 77 79 100 102 107 109 110 115 122 123 128 132 133 138 145 146 151 152 153 161 162 165 166 172 173 178 179 184 185 192 193 199 200 203 204

B2 C16 B17 A17 A18 E16 J16 K15 V18 U17 T16 U16 U15 U12 V11 U10 T9 U9 V8 U5 U4 U3 V2 U2 T3 V1 R2 T1 N2 M4 L4 L2 K3 J1 G1 G4 F4 E2 E3 B1

M1 (HIGH) (I) M1 (LOW) (I) M1 (LOW) (I) M1 (HIGH) (I) M1 (LOW) (I) M0 (HIGH) (I) M0 (LOW) (I) M0 (HIGH) (I) M0 (LOW) (I) Mo (LOW) (I) M2 (HIGH) (I) M2 (LOW) (I) M2 (HIGH) (I) M2 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE DATA 7 (I) DATA 6 (I) DATA 5 (I) CS0 (I) DATA 4 (I) DATA 3 (I) CS1 (I) DATA 2 (I) DATA 1 (I) RDY/BUSY DIN (I) DOUT CCLK (I) DIN (I) DOUT CCLK (O) DATA 0 (I) DOUT CCLK (O) WS (I) CS2 (I) DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK (O) A0 A1 A2 A3 A15 A4 A14 A5 A13 A6 A12 A7 A11 A8 A10 A9 DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK (O) A0 A1 A2 A3 A15 A4 A14 A5 A13 A6 A12 A7 A11 A8 A10 A9 DATA 4 (I) DATA 3 (I) DATA 4 (I) DATA 3 (I) HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE DATA 7 (I) DATA 6 (I) DATA 5 (I) HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE DATA 7 (I) DATA 6 (I) DATA 5 (I)

V17 PROGRAM (I)

38 39 40

62 63 64 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16

Notes:

X**

* (I) ** *** ****

Generic I/O pins are not shown. For a detailed description of the configuration modes, see page 343 through page 352. For pinout details, see page 383 through page 394. Represents a 50-k to 100-k pull-up before and during configuration. INIT is an open drain output during configuration. Represents an input. Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown. Peripheral mode and master parallel mode are not supported in the PC44 package. Pin assignments for the XC3195A PQ208 differ from those shown. Pin assignments of PGA Footprint PLCC sockets and PGA packages are not indentical. The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages. Before and during conguration, all outputs that are not used for the conguration process are 3-stated with a 50-kW to 100-kW pull-up resistor.

Note:

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XC3000A Switching Characteristics

Xilinx maintains test specications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specication revision.

XC3000A Operating Conditions

Symbol VCC VIHT VILT VIHC VILC TIN Note: Description Supply voltage relative to GND Commercial 0C to +85C junction Supply voltage relative to GND Industrial -40C to +100C junction High-level input voltage TTL configuration Low-level input voltage TTL configuration High-level input voltage CMOS configuration Low-level input voltage CMOS configuration Input signal transition time Min 4.75 4.5 2.0 0 70% 0 Max 5.25 5.5 VCC 0.8 100% 20% 250 Units V V V V VCC VCC ns

At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C.

XC3000A DC Characteristics Over Operating Conditions

Symbol VOH VOL VOH VOL VCCPD ICCPD Description High-level output voltage (@ IOH = 4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) High-level output voltage (@ IOH = 4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) Power-down supply voltage (PWRDWN must be Low) Power-down supply current (VCC(MAX) @ TMAX) Min 3.86 3.76 0.40 2.30 3020A 3030A 3042A 3064A 3090A 100 160 240 340 500 500 10 +10 Max 0.40 Units V V V V V A A A A A A A A

Commercial Industrial

ICCO IIL

CIN

IRIN IRLL

Quiescent FPGA supply current in addition to ICCPD Chip thresholds programmed as CMOS levels Chip thresholds programmed as TTL levels Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low

10

10 15

pF pF

0.02

16 20 0.17 3.4

pF pF mA mA

Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA
device congured with a MakeBits tie option. 2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed 100 mA per VCC pin. The number of ground pins varies from the XC3020A to the XC3090A.

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XC3000A Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic 0.5 to +7.0 0.5 to VCC +0.5 0.5 to VCC +0.5 65 to +150 +260 +125 +150 Units V V V C C C C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

XC3000A Global Buffer Switching Characteristics Guidelines

Description Global and Alternate Clock Distribution1 Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) T to L.L. active and valid with single pull-up resistor T to L.L. active and valid with pair of pull-up resistors T to L.L. High with single pull-up resistor T to L.L. High with pair of pull-up resistors BIDI Bidirectional buffer delay Speed Grade Symbol -7 Max -6 Max Units

TPID TPIDC TIO TON TON TPUS TPUF TBIDI

7.5 6.0 4.5 9.0 11.0 16.0 10.0 1.7

7.0 5.7 4.0 8.0 10.0 14.0 8.0 1.5

ns ns ns ns ns ns ns ns

Note: 1. Timing is based on the XC3042A, for other devices see XACT timing calculator.

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XC3000A CLB Switching Characteristics Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Symbol -7 Min Max Min -6 Max Units

Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y FG Mode F and FGM Mode

TILO

5.1 5.6 4.5

4.1 4.6 4.0

ns ns ns

Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y FG Mode F and FGM Mode Set-up time before clock K Logic Variables A, B, C, D, E FG Mode F and FGM Mode Data In DI Enable Clock EC Hold Time after clock K Logic Variables A, B, C, D, E Data In DI2 Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad)1 RESET width (Low) delay from RESET pad to outputs X or Y

TCKO

TQLO

9.5 10.0

8.0 8.5

ns ns

2 4 6 3 5 7 11 12

TICK TDICK TECCK TCKI TCKDI TCKEC TCH TCL FCLK TRPW TRIO TMRW TMRQ

4.5 5.0 4.0 4.5 0 1.0 2.0 4.0 4.0 113.0 6.0 6.0 16.0 19.0

3.5 4.0 3.0 4.0 0 1.0 2.0 3.5 3.5 135.0 5.0 5.0 14.0 17.0

ns ns ns ns ns ns ns ns ns MHz ns ns ns ns

13 9

Notes: 1. Timing is based on the XC3042A, for other devices see XACT timing calculator.
2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

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XC3000A CLB Switching Characteristics Guidelines (continued)

CLB Output (X, Y) (Combinatorial) 1 CLB Input (A,B,C,D,E) 2 CLB Clock 12 TCL 4 CLB Input (Direct In) 6 CLB Input (Enable Clock) 8 CLB Output (Flip-Flop) TCKO T ECCK 7 TCKEC TDICK 11 T CH 5 TCKDI T ICK 3 T CKI T ILO

CLB Input (Reset Direct) 13 TRPW 9 T RIO CLB Output (Flip-Flop)

X5424

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XC3000A IOB Switching Characteristics Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Symbol 3 4 1 7 7 10 10 9 9 8 8 5 6 11 12 TPID TPTG TIKRI TPICK TOKPO TOKPO TOPF TOPS TTSHZ TTSHZ TTSON TTSON TOOK TOKO TIOH TIOL FCLK TRRI TRPO TRPO 8.0 0 4.0 4.0 113.0 24.0 33.0 43.0 14.0 8.0 18.0 6.0 16.0 10.0 20.0 11.0 21.0 7.0 0 3.5 3.5 135.0 23.0 29.0 37.0 -7 Min Max 4.0 15.0 3.0 12.0 7.0 15.0 5.0 13.0 9.0 12.0 10.0 18.0 Min -6 Max 3.0 14.0 2.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns

Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays (based on XC3042A) RESET Pad to Registered In (Q) RESET Pad to output pad (fast) (slew-rate limited)

13 15 15

Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test xture). Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be congured with the internal pull-up resistor or alternatively congured as a driven output or driven from an external source. 3. Input pad set-up time is specied with respect to the internal clock (ik). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is congures as a user input.

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XC3000A IOB Switching Characteristics Guidelines (continued)

I/O Block (I) 3 I/O Pad Input 1 I/O Clock (IK/OK) 12 TIOL I/O Block (RI) 4 RESET 5 I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 I/O Pad Output (Registered) TOKPO TOOK 6 TOKO 15 TRPO TIKRI 13 TRRI 11 TIOH T PICK T PID

I/O Pad TS 8 I/O Pad Output

X5425

TTSON

T TSHZ

Vcc PROGRAM-CONTROLLED MEMORY CELLS

OUT INVERT

3-STATE INVERT

OUTPUT SELECT

SLEW RATE

PASSIVE PULL UP

3- STATE (OUTPUT ENABLE)

OUT

FLIP FLOP

OUTPUT BUFFER

I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD

CK1

CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP

X3029

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XC3000L Switching Characteristics

Xilinx maintains test specications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specication revision.

XC3000L Operating Conditions

Symbol VCC VIH VIL TIN Description Supply voltage relative to GND Commercial 0C to +85C junction High-level input voltage TTL configuration Low-level input voltage TTL configuration Input signal transition time Min 3.0 2.0 -0.3 Max 3.6 VCC+0.3 0.8 250 Units V V V ns

Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the right to restrict operation to the 3.0 to 6.0 V range later, when smaller device geometries might preclude operation at 5V. Operating conditions are guaranteed in the 3.0 3.6 V VCC range.

XC3000L DC Characteristics Over Operating Conditions

Symbol VOH VOL VOH VOL VCCPD ICCPD ICCO IIL Description High-level output voltage (@ IOH = 4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) High-level output voltage (@ IOH = 4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) Power-down supply voltage (PWRDWN must be Low) Power-down supply current (VCC(MAX) @ TMAX) Quiescent FPGA supply current in addition to ICCPD1 Chip thresholds programmed as CMOS levels Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low Min 2.40 VCC -0.2 0.2 2.30 10 20 +10 Max 0.40 Units V V V V V A A A

10

CIN

10 15

pF pF

IRIN IRLL

0.02

15 20 0.17 2.50

pF pF mA mA

Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA
device congured with a MakeBits tie option. ICCO is in addition to ICCPD. 2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed 100 mA per VCC pin. The number of ground pins varies from the XC3020L to the XC3090L.

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XC3000L Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic 0.5 to +7.0 0.5 to VCC +0.5 0.5 to VCC +0.5 65 to +150 +260 +125 +150 Units V V V C C C C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

XC3000L Global Buffer Switching Characteristics Guidelines

Description Global and Alternate Clock Distribution1 Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) T to L.L. active and valid with single pull-up resistor T to L.L. High with single pull-up resistor BIDI Bidirectional buffer delay Speed Grade Symbol -8 Max Units

TPID TPIDC TIO TON TPUS TBIDI

9.0 7.0 5.0 12.0 24.0 2.0

ns ns ns ns ns ns

1. Timing is based on the XC3042A, for other devices see XACT timing calculator. 2. The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid option for XC3000L devices.

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XC3000L CLB Switching Characteristics Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Symbol -8 Min Max Units

Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y FG Mode F and FGM Mode

TILO

6.7 7.5 7.5

ns ns ns

Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y FG Mode F and FGM Mode Set-up time before clock K Logic Variables A, B, C, D, E FG Mode F and FGM Mode Data In DI Enable Clock EC Hold Time after clock K Logic Variables A, B, C, D, E Data In DI2 Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad)1 RESET width (Low) delay from RESET pad to outputs X or Y

TCKO

TQLO

14.0 14.8

ns ns

2 4 6 3 5 7 11 12

TICK TDICK TECCK TCKI TCKDI TCKEC TCH TCL FCLK TRPW TRIO TMRW TMRQ

5.0 5.8 5.0 6.0 0 2.0 2.0 5.0 5.0 80.0 7.0 7.0 16.0 23.0

ns ns ns ns ns ns ns ns ns MHz ns ns ns ns

13 9

Notes: 1. Timing is based on the XC3042L, for other devices see XACT timing calculator.
2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

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XC3000L CLB Switching Characteristics Guidelines (continued)

CLB Output (X, Y) (Combinatorial) 1 CLB Input (A,B,C,D,E) 2 CLB Clock 12 TCL 4 CLB Input (Direct In) 6 CLB Input (Enable Clock) 8 CLB Output (Flip-Flop) TCKO T ECCK 7 TCKEC TDICK 11 T CH 5 TCKDI T ICK 3 T CKI T ILO

CLB Input (Reset Direct) 13 TRPW 9 T RIO CLB Output (Flip-Flop)

X5424

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XC3000L IOB Switching Characteristics Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Symbol 3 4 1 7 7 10 10 9 9 8 8 5 6 11 12 TPID TPTG TIKRI TPICK TOKPO TOKPO TOPF TOPS TTSHZ TTSHZ TTSON TTSON TOOK TOKO TIOH TIOL FCLK TRRI TRPO TRPO 12.0 0 5.0 5.0 80.0 25.0 35.0 51.0 22.0 12.0 28.0 9.0 25.0 12.0 28.0 16.0 32.0 -8 Min Max 5.0 24.0 6.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns

Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays (based on XC3042A) RESET Pad to Registered In (Q) RESET Pad to output pad (fast) (slew-rate limited)

13 15 15

Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test xture). Typical slew rate limited output
rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be congured with the internal pull-up resistor or alternatively congured as a driven output or driven from an external source. 3. Input pad set-up time is specied with respect to the internal clock (ik). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is congures as a user input.

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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)

XC3000L IOB Switching Characteristics Guidelines (continued)

I/O Block (I) 3 I/O Pad Input 1 I/O Clock (IK/OK) 12 TIOL I/O Block (RI) 4 RESET 5 I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 I/O Pad Output (Registered) TOKPO TOOK 6 TOKO 15 TRPO TIKRI 13 TRRI 11 TIOH T PICK T PID

I/O Pad TS 8 I/O Pad Output

X5425

TTSON

T TSHZ

Vcc PROGRAM-CONTROLLED MEMORY CELLS

OUT INVERT

3-STATE INVERT

OUTPUT SELECT

SLEW RATE

PASSIVE PULL UP

3- STATE (OUTPUT ENABLE)

OUT

FLIP FLOP

OUTPUT BUFFER

I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD

CK1

CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP

X3029

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XC3100A Switching Characteristics

Xilinx maintains test specications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specication revision.

XC3100A Operating Conditions

Symbol VCC VIHT VILT VIHC VILC TIN Note: Description Supply voltage relative to GND Commercial 0C to +85C junction Supply voltage relative to GND Industrial -40C to +100C junction High-level input voltage TTL configuration Low-level input voltage TTL configuration High-level input voltage CMOS configuration Low-level input voltage CMOS configuration Input signal transition time Min 4.25 4.5 2.0 0 70% 0 Max 5.25 5.5 VCC 0.8 100% 20% 250 Units V V V V VCC VCC ns

At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C.

XC3100A DC Characteristics Over Operating Conditions

Symbol VOH VOL VOH VOL VCCPD ICCO IIL Description High-level output voltage (@ IOH = 8.0 mA, VCC min) Commercial Low-level output voltage (@ IOL = 8.0 mA, VCC min) High-level output voltage (@ IOH = 8.0 mA, VCC min) Industrial Low-level output voltage (@ IOL = 8.0 mA, VCC min) Power-down supply voltage (PWRDWN must be Low) Quiescent LCA supply current in addition to ICCPD1 Chip thresholds programmed as CMOS levels Chip thresholds programmed as TTL levels Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low Min 3.86 3.76 0.40 2.30 8 14 +10 Max 0.40 Units V V V V V mA mA A

10

CIN

10 15

pF pF

IRIN IRLL

0.02 0.20

15 20 0.17 2.80

pF pF mA mA

Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the LCA
device congured with a MakeBits tie option. 2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 or PG223 package.

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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)

XC3100A Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic 0.5 to +7.0 0.5 to VCC +0.5 0.5 to VCC +0.5 65 to +150 +260 +125 +150 Units V V V C C C C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

XC3100A Global Buffer Switching Characteristics Guidelines

Speed Grade -5 Description Symbol Max Global and Alternate Clock Distribution1 Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input TPID 6.8 Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TPIDC 5.4 TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) (XC3100) TIO 4.1 (XC3100A) TIO 3.6 T to L.L. active and valid with single pull-up resistor TON 5.6 T to L.L. active and valid with pair of pull-up resistors TON 7.1 T to L.L. High with single pull-up resistor TPUS 15.6 T to L.L. High with pair of pull-up resistors TPUF 12.0 BIDI Bidirectional buffer delay TBIDI 1.4
Note:

-4 Max

-3 Max

-2 Max

-1 Max

-09 Max Units

6.5 5.1 3.7 3.6 5.0 6.5 13.5 10.5 1.2

5.6 4.3 3.1 3.1 4.2 5.7 11.4 8.8 1.0

4.7 3.7

4.3 3.5

3.9 3.1

ns ns ns ns ns ns ns ns ns

3.1 4.2 5.7 11.4 8.1 0.9

2.9 4.0 5.5 10.4 7.1 0.85

2.1 3.1 4.6 8.9 5.9 0.75

Prelim

1. Timing is based on the XC3142A, for other devices see XACT timing calculator. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid design option for XC3100A devices.

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XC3100A CLB Switching Characteristics Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade -5 -4 -3 -2 -1 -09 Description Symbol Min Max Min Max Min Max Min Max Min Max Min Max Units Combinatorial Delay 4.1 3.3 2.7 2.2 1.75 1.5 ns Logic Variables A, B, C, D, E, 1 TILO to outputs X or Y Sequential delay Clock k to outputs X or Y 8 TCKO 3.1 2.5 2.1 1.7 1.4 1.25 ns Clock k to outputs X or Y when Q is returned through function generators F TQLO or G to drive X or Y 6.3 5.2 4.3 3.5 3.1 2.7 ns Set-up time before clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Reset Direct inactive RD Hold Time after clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad)1 RESET width (Low) (XC3142A) delay from RESET pad to outputs X or Y 2 TICK 3.1 4 TDICK 2.0 6 TECCK 3.8 1.0 0 3 TCKI 5 TCKDI 1.0 7 TCKEC 1.0 11 12 TCH TCL FCLK 2.4 2.4 188 3.8 4.4 2.5 1.6 3.2 1.0 0 1.0 0.8 2.0 2.0 227 3.2 3.7 2.1 1.4 2.7 1.0 0 0.9 0.7 1.6 1.6 270 2.7 3.1 1.8 1.3 2.5 1.0 0 0.9 0.7 1.3 1.3 323 2.3 2.7 1.7 1.2 2.3 1.0 0 0.8 0.6 1.3 1.3 323 2.3 2.4 1.5 1.0 2.05 1.0 0 0.7 0.55 1.3 1.3 370 2.05 2.15 ns ns ns ns ns ns ns ns ns MHz ns ns ns ns

13 TRPW 9 TRIO

TMRW 14.0 14.0 12.0 12.0 12.0 12.0 TMRQ 17.0 14.0 12.0 12.0 12.0 12.0 Prelim

Notes: 1. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die. 2. TILO, TQLO and TICK are specied for 4-input functions. For 5-input functions or base FGM functions, each of these specications for the XC3100A family increases by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and 0.30 ns (-09).

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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)

XC3100A CLB Switching Characteristics Guidelines (continued)

CLB Output (X, Y) (Combinatorial) 1 CLB Input (A,B,C,D,E) 2 CLB Clock 12 TCL 4 CLB Input (Direct In) 6 CLB Input (Enable Clock) 8 CLB Output (Flip-Flop) TCKO T ECCK 7 TCKEC TDICK 11 T CH 5 TCKDI T ICK 3 T CKI T ILO

CLB Input (Reset Direct) 13 TRPW 9 T RIO CLB Output (Flip-Flop)

X5424

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XC3100A IOB Switching Characteristics Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent (XC3100A) Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time XC3120A, XC3130A XC3142A XC3164A XC3190A XC3195A Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) (XC3100A) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) (XC3100A) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time (XC3100A) Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays RESET Pad to Registered In (Q) (XC3142A) (XC3190A) RESET Pad to output pad (fast) (slew-rate limited) Speed Grade -5 -4 -3 -2 -1 -09 Symbol Min Max Min Max Min Max Min Max Min Max Min Max Units 3 TPID TPTG TIKRI 2.8 14.0 2.8 2.5 12.0 2.5 2.2 11.0 2.2 2.0 11.0 1.9 1.7 10.0 1.7 1.55 9.2 1.55 ns ns ns

1 TPICK 10.9 11.0 11.2 11.5 12.0 7 TOKPO 7 TOKPO 10 TOPF 10 TOPS 9 TTSHZ 9 TTSHZ 8 TTSON 8 TTSON 5.5 14.0 4.1 12.1 6.9 6.9 10.0 18.0

10.6 10.7 11.0 11.2 11.6 5.0 12.0 3.7 11.0 6.2 6.2 10.0 17.0

9.4 9.5 9.7 9.9 10.3 4.4 10.0 3.3 9.0 5.5 5.5 9.0 15.0

8.9 9.0 9.2 9.4 9.8 3.7 9.7 3.0 8.7 5.0 5.0 8.5 14.2

8.0 8.1 8.3 8.5 8.9 3.4 8.4 3.0 8.0 4.5 4.5 6.5 11.5

7.2 7.3 7.5 7.7 8.1 3.3 6.9 2.9 6.5 4.05 4.05 5.0 8.6

ns ns ns ns ns ns ns ns ns ns ns ns ns ns

5 TOOK 6 TOKO 11 TIOH 12 TIOL FCLK

5.0 0 2.4 2.4 188

4.5 0 2.0 2.0 227 1.6 1.6 270

3.6 0 1.3 1.3 323

3.2 0 1.3 1.3 323

2.9

ns ns ns ns MHz

1.3 1.3 370

13 TRRI 15 TRPO 15 TRPO

18.0 29.5 24.0 32.0

15.0 25.5 20.0 27.0

13.0 21.0 17.0 23.0

13.0 21.0 17.0 23.0

13.0 21.0 17.0 22.0

14.4 21.0 17.0 21.0 Preliminary

ns ns ns ns

Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test xture). For larger capacitive loads, see
page XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be congured with the internal pull-up resistor or alternatively congured as a driven output or driven from an external source. 3. Input pad set-up time is specied with respect to the internal clock (ik). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is congures as a user input.

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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)

XC3100A IOB Switching Characteristics Guidelines (continued)

I/O Block (I) 3 I/O Pad Input 1 I/O Clock (IK/OK) 12 TIOL I/O Block (RI) 4 RESET 5 I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 I/O Pad Output (Registered) TOKPO TOOK 6 TOKO 15 TRPO TIKRI 13 TRRI 11 TIOH T PICK T PID

I/O Pad TS 8 I/O Pad Output

X5425

TTSON

T TSHZ

Vcc PROGRAM-CONTROLLED MEMORY CELLS

OUT INVERT

3-STATE INVERT

OUTPUT SELECT

SLEW RATE

PASSIVE PULL UP

3- STATE (OUTPUT ENABLE)

OUT

FLIP FLOP

OUTPUT BUFFER

I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD

CK1

CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP

X3029

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XC3100L Switching Characteristics

Xilinx maintains test specications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specication revision.

XC3100L Operating Conditions

Symbol VCC VIH VIL TIN Description Supply voltage relative to GND Commercial 0C to +85C junction High-level input voltage Low-level input voltage Input signal transition time Min 3.0 2.0 -0.3 Max 3.6 VCC + 0.3 0.8 250 Units V V V ns

Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 V to 5.25 V, Xilinx reserves the right to restrict operation to the 3.0 and 3.6 V range later, when smaller device geometries might preclude operation @ 5 V. Operating conditions are guaranteed in the 3.0 3.6 V VCC range.

XC3100L DC Characteristics Over Operating Conditions

Symbol VOH VOL VCCPD ICCO IIL Description High-level output voltage (@ IOH = -4.0 mA, VCC min) High-level output voltage (@ IOH = -100.0 A, VCC min) Low-level output voltage (@ IOH = 4.0 mA, VCC min) Low-level output voltage (@ IOH = +100.0 A, VCC min) Power-down supply voltage (PWRDWN must be Low) Quiescent FPGA supply current Chip thresholds programmed as CMOS levels1 Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA175 (sample tested) All pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V (sample tested) Horizontal long line pull-up (when selected) @ logic Low Min 2.4 VCC -0.2 Max Units V V V V V mA A

0.40 0.2 2.30 1.5 -10 +10

CIN

10 15

pF pF

IRIN

IRLL

0.02 0.20

15 20 0.17 2.80

pF pF mA mA

Notes: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at VCC or GND, and the FPGA

congured with a MakeBits tie option. 2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source current may not exceed 100 mA per VCC pin. The number of ground pins varies from the XC3142L to the XC3190L.

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XC3100L Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic 0.5 to +7.0 0.5 to VCC +0.5 0.5 to VCC +0.5 65 to +150 +260 +125 +150 Units V V V C C C C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

XC3100L Global Buffer Switching Characteristics Guidelines

Description Global and Alternate Clock Distribution1 Either:Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) T to L.L. active and valid with single pull-up resistor T to L.L. High with single pull-up resistor BIDI Bidirectional buffer delay Speed Grade Symbol -3 Max -2 Max Units

TPID TPIDC TIO TON TPUS TBIDI

5.6 4.3 3.1 4.2 11.4 1.0 Advance

4.7 3.7 3.1 4.2 11.4 0.9

ns ns ns ns ns ns

Notes: 1. Timing is based on the XC3142L, for other devices see XACT timing calculator.
2. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid option for XC3100L devices.

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XC3100L CLB Switching Characteristics Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Symbol 1 8 TILO TCKO TQLO 2 4 6 TICK TDICK TECCK 2.1 1.4 2.7 1.0 0 0.9 0.7 1.6 1.6 270 2.7 3.1 -3 Min Max 2.7 2.1 4.3 1.8 1.3 2.5 1.0 0 0.9 0.7 1.3 1.3 325 2.3 2.7 Min -2 Max 2.2 1.7 3.5 Units ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns 12.0

Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y Set-up time before clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Reset Direct Inactive RD Hold Time after clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad) RESET width (Low) (XC3142L) delay from RESET pad to outputs X or Y

3 5 7 11 12

TCKI TCKDI TCKEC TCH TCL FCLK TRPW TRIO

13 9

TMRW TMRQ

12.0

12.0 12.0 Advance

Notes: 1. The CLB K to Q delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die. 2. TILO, TQLO and TICK are specied for 4-input functions. For 5-input functions or base FGM functions, each of these specications for the XC3100L family increase by 0.35 ns (-3) and 0.29 ns (-2).

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XC3100L CLB Switching Characteristics Guidelines (continued)

CLB Output (X, Y) (Combinatorial) 1 CLB Input (A,B,C,D,E) 2 CLB Clock 12 TCL 4 CLB Input (Direct In) 6 CLB Input (Enable Clock) 8 CLB Output (Flip-Flop) TCKO T ECCK 7 TCKEC TDICK 11 T CH 5 TCKDI T ICK 3 T CKI T ILO

CLB Input (Reset Direct) 13 TRPW 9 T RIO CLB Output (Flip-Flop)

X5424

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XC3100L IOB Switching Characteristics Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Symbol 3 TPID TPTG TIKRI TPICK 9.5 9.9 7 7 10 10 9 9 8 8 5 6 11 12 TOKPOTOK
PO

-3 Min Max 2.2 11.0 2.2 Min

-2 Max 2.0 11.0 1.9 Units ns ns ns

Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch (XC3100L) transparent Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time XC3142L XC3190L Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited)(XC3100L) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast)(XC3100L) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time (XC3100L) Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Export Control Maximum flip-flop toggle rate Global Reset Delays RESET Pad to Registered In (Q) (XC3142L) (XC3190L) RESET Pad to output pad (fast) (slew-rate limited)

4 1

9.0 9.4 4.4 10.0 3.3 9.0 5.5 5.5 9.0 15.0 4.0 9.7 3.0 8.7 5.0 5.0 8.5 14.2 3.6 0 1.3 1.3 325

ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz

TOPF TOPF TTSHZ TTSHZ TTSON TTSON TOOK TOKO TIOH TIOL FTOG 4.0 0 1.6 1.6 270

13 15 15

TRRI TRPO TRPO

16.0 21.0 17.0 23.0 Advance

16.0 21.0 17.0 23.0

ns ns ns ns

Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test xture). Typical slew rate limited output
rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be congured with the internal pull-up resistor or alternatively congured as a driven output or driven from an external source. 3. Input pad set-up time is specied with respect to the internal clock (IK). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.

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XC3100L IOB Switching Characteristics Guidelines (continued)

I/O Block (I) 3 I/O Pad Input 1 I/O Clock (IK/OK) 12 TIOL I/O Block (RI) 4 RESET 5 I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 I/O Pad Output (Registered) TOKPO TOOK 6 TOKO 15 TRPO TIKRI 13 TRRI 11 TIOH T PICK T PID

I/O Pad TS 8 I/O Pad Output

X5425

TTSON

T TSHZ

Vcc PROGRAM-CONTROLLED MEMORY CELLS

OUT INVERT

3-STATE INVERT

OUTPUT SELECT

SLEW RATE

PASSIVE PULL UP

3- STATE (OUTPUT ENABLE)

OUT

FLIP FLOP

OUTPUT BUFFER

I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD

CK1

CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP

X3029

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XC3000 Series Pin Assignments

Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 223. Each chip is offered in several package types to accommodate the available PC board space and manufacturing technology. Most package types are also offered with different chips to accommodate design changes without the need for PC board changes. Note that there is no perfect match between the number of bonding pads on the chip and the number of pins on a package. In some cases, the chip has more pads than there are pins on the package, as indicated by the information (unused pads) below the line in the following table. The IOBs of the unconnected pads can still be used as storage elements if the specied propagation delays and set-up times are acceptable. In other cases, the chip has fewer pads than there are pins on the package; therefore, some package pins are connected (n.c.), as shown above the line in the following table. not

XC3000 Series 44-Pin PLCC Pinouts

XC3000A, XC3000L, and XC3100A families have identical pinouts Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 XC3030A GND I/O I/O I/O I/O I/O PWRDWN TCLKIN-I/O I/O I/O I/O VCC I/O I/O I/O M1-RDATA M0-RTRIG M2-I/O HDC-I/O LDC-I/O I/O INIT-I/O Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 XC3030A GND I/O I/O XTL2(IN)-I/O RESET DONE-PGM I/O XTL1(OUT)-BCLK-I/O I/O I/O I/O VCC I/O I/O I/O DIN-I/O DOUT-I/O CCLK I/O I/O I/O I/O

Peripheral mode and Master Parallel mode are not supported in the PC44 package

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XC3000 Series 64-Pin Plastic VQFP Pinouts

XC3000A, XC3000L, and XC3100A families have identical pinouts Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 XC3030A A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A4-I/O A14-I/O A5-I/O GND A13-I/O A6-I/O A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O PWRDN TCLKIN-I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O M1-RDATA M0-RTRIG Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 XC3030A M2-I/O HDC-I/O I/O LDC-I/O I/O I/O I/O INIT-I/O GND I/O I/O I/O I/O I/O XTAL2(IN)-I/O RESET DONE-PG D7-I/O XTAL1(OUT)-BCLKIN-I/O D6-I/O D5-I/O CS0-I/O D4-I/O VCC D3-I/O CS1-I/O D2-I/O D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK

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XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
68 PLCC XC3030A XC3020A 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 42 43 32 33 34 35 36 37 38 39 40 41 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 XC3020A, XC3030A, XC3042A PWRDN TCLKIN-I/O I/O* I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O M1-RDATA M0-RTRIG M2-I/O HDC-I/O I/O LDC-I/O I/O I/O* I/O I/O I/O* INIT-I/O GND I/O I/O I/O I/O I/O I/O I/O* I/O* I/O XTL2(IN)-I/O 68 PLCC 84 PLCC 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 84 PGA B2 C2 B1 C1 D2 D1 E3 E2 E1 F2 F3 G3 G1 G2 F1 H1 H2 J1 K1 J2 L1 K2 K3 L2 L3 K4 L4 J5 K5 L5 K6 J6 J7 L7 K7 L6 L8 K8 L9 L10 K9 L11 XC3030A XC3020A 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 XC3020A, XC3030A, XC3042A RESET DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O D6-I/O I/O D5-I/O CS0-I/O D4-I/O I/O VCC D3-I/O CS1-I/O D2-I/O I/O I/O* D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O I/O* I/O* A15-I/O A4-I/O A14-I/O A5-I/O GND A13-I/O A6-I/O A12-I/O A7-I/O I/O* I/O* A11-I/O A8-I/O A10-I/O A9-I/O

84 PLCC 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11

84 PGA K10 J10 K11 J11 H10 H11 F10 G10 G11 G9 F9 F11 E11 E10 E9 D11 D10 C11 B11 C10 A11 B10 B9 A10 A9 B8 A8 B6 B7 A7 C7 C6 A6 A5 B5 C5 A4 B4 A3 A2 B3 A1

Unprogrammed IOBs have a default pull-up. This prevents an undened pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the 118 pads on the XC3042A (and 84 of the 98 pads on the XC3030A) that are connected to the 84 package pins. Ten pads, indicated by an asterisk, do not exist on the XC3020A, which has 74 pads; therefore the corresponding pins on the 84-pin packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a dash () in the 68 PLCC column, have no connection to the 68 PLCC, but are connected to the 84-pin packages.

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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)

XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PLCC Pin Number 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 XC3064A, XC3090A, XC3195A PWRDN TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O GND* VCC I/O I/O I/O I/O I/O I/O I/O I/O M1-RDATA M0-RTRIG M2-I/O HDC-I/O I/O LDC-I/O I/O I/O I/O I/O INIT/I/O* VCC* GND I/O I/O I/O I/O I/O I/O I/O I/O I/O XTL2(IN)-I/O PLCC Pin Number 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 XC3064A, XC3090A, XC3195A RESET DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O D6-I/O I/O D5-I/O CS0-I/O D4-I/O I/O VCC GND* D3-I/O* CS1-I/O* D2-I/O* I/O D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O A14-I/O A5-I/O GND VCC* A13-I/O* A6-I/O* A12-I/O* A7-I/O* I/O A11-I/O A8-I/O A10-I/O A9-I/O

Unprogrammed IOBs have a default pull-up. This prevents an undened pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * In the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin denition than XC3020A/XC3030A/XC3042A.

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November 20, 1997 (Version 3.0)

XC3000 Series 100-Pin QFP Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin No. TQFP CQFP PQFP VQFP 1 16 13 2 17 14 3 18 15 4 19 16 5 20 17 6 21 18 7 22 19 8 23 20 9 24 21 10 25 22 11 26 23 12 27 24 13 28 25 14 29 26 15 30 27 16 31 28 17 32 29 18 33 30 19 34 31 20 35 32 21 36 33 22 37 34 23 38 35 24 39 36 25 40 37 26 41 38 27 42 39 28 43 40 29 44 41 30 45 42 31 46 43 32 47 44 33 48 45 34 49 46 XC3020A XC3030A XC3042A GND A13-I/O A6-I/O A12-I/O A7-I/O I/O* I/O* A11-I/O A8-I/O A10-I/O A9-I/O VCC* GND* PWRDN TCLKIN-I/O I/O** I/O* I/O* I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O XC3020A TQFP XC3030A CQFP PQFP VQFP XC3042A 35 50 47 I/O* 36 51 48 I/O* 37 52 49 M1-RD 38 53 50 GND* 39 54 51 MO-RT 40 55 52 VCC* 41 56 53 M2-I/O 42 57 54 HDC-I/O 43 58 55 I/O 44 59 56 LDC-I/O 45 60 57 I/O* 46 61 58 I/O* 47 62 59 I/O 48 63 60 I/O 49 64 61 I/O 50 65 62 INIT-I/O 51 66 63 GND 52 67 64 I/O 53 68 65 I/O 54 69 66 I/O 55 70 67 I/O 56 71 68 I/O 57 72 69 I/O 58 73 70 I/O 59 74 71 I/O* 60 75 72 I/O* 61 76 73 XTL2-I/O 62 77 74 GND* 63 78 75 RESET 64 79 76 VCC* 65 80 77 DONE-PG 66 81 78 D7-I/O 67 82 79 BCLKIN-XTL1-I/O 68 83 80 D6-I/O Pin No. Pin No. TQFP CQFP PQFP VQFP 69 84 81 70 85 82 71 86 83 72 87 84 73 88 85 74 89 86 75 90 87 76 91 88 77 92 89 78 93 90 79 94 91 80 95 92 81 96 93 82 97 94 83 98 95 84 99 96 85 100 97 86 1 98 87 2 99 88 3 100 89 4 1 90 5 2 91 6 3 92 7 4 93 8 5 94 9 6 95 10 7 96 11 8 97 12 9 98 13 10 99 14 11 100 15 12 XC3020A XC3030A XC3042A I/O* I/O* I/O D5-I/O CS0-I/O D4-I/O I/O VCC D3-I/O CS1-I/O D2-I/O I/O I/O* I/O* D1-I/O RDY/BUSY-RCLK-I/O DO-DIN-I/O DOUT-I/O CCLK VCC* GND* AO-WS-I/O A1-CS2-I/O I/O** A2-I/O A3-I/O I/O* I/O* A15-I/O A4-I/O A14-I/O A5-I/O

Unprogrammed IOBs have a default pull-up. This prevents an undened pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * This table describes the pinouts of three different chips in three different packages. The pin-description column lists 100 of the 118 pads on the XC3042A that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the XC3030A, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist on the XC3020A, which has 74 pads; therefore, the corresponding pins have no connections. (See table on page 383.)

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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)

XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA Pin Number C4 A1 C3 B2 B3 A2 B4 C5 A3 A4 B5 C6 A5 B6 A6 B7 C7 C8 A7 B8 A8 A9 B9 C9 A10 B10 A11 C10 B11 A12 B12 A13 C12 XC3042A XC3064A GND PWRDN I/O-TCLKIN I/O I/O I/O* I/O I/O I/O* I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O* I/O I/O I/O* I/O I/O* I/O PGA Pin Number B13 C11 A14 D12 C13 B14 C14 E12 D13 D14 E13 F12 E14 F13 F14 G13 G14 G12 H12 H14 H13 J14 J13 K14 J12 K13 L14 L13 K12 M14 N14 M13 L12 XC3042A XC3064A M1-RD GND M0-RT VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O* I/O I/O I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O* I/O I/O I/O I/O XTL2(IN)-I/O GND PGA Pin XC3042A Number XC3064A P14 RESET M11 VCC N13 DONE-PG M12 D7-I/O P13 XTL1-I/O-BCLKIN N12 I/O P12 I/O N11 D6-I/O M10 I/O P11 I/O* N10 I/O P10 I/O M9 D5-I/O N9 CS0-I/O P9 I/O* P8 I/O* N8 D4-I/O P7 I/O M8 VCC M7 GND N7 D3-I/O P6 CS1-I/O N6 I/O* P5 I/O* M6 D2-I/O N5 I/O P4 I/O P3 I/O M5 D1-I/O N4 RDY/BUSY-RCLK-I/O P2 I/O N3 I/O N2 D0-DIN-I/O PGA Pin Number M3 P1 M4 L3 M2 N1 M1 K3 L2 L1 K2 J3 K1 J2 J1 H1 H2 H3 G3 G2 G1 F1 F2 E1 F3 E2 D1 D2 E3 C1 B1 C2 D3 XC3042A XC3064A DOUT-I/O CCLK VCC GND A0-WS-I/O A1-CS2-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O* A14-I/O A5-I/O GND VCC A13-I/O A6-I/O I/O* A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC

Unprogrammed IOBs have a default pull-up. This prevents an undened pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. *Indicates unconnected package pins (14) for the XC3042A.

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XC3000 Series 144-Pin Plastic TQFP Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 XC3042A XC3064A XC3090A PWRDN I/O-TCLKIN I/O* I/O I/O I/O* I/O I/O I/O* I/O I/O I/O I/O I/O I/O* I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O* I/O I/O I/O* I/O* I/O I/O* I/O M1-RD GND MO-RT VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O* I/O I/O Pin Number 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 XC3042A XC3064A XC3090A I/O I/O* I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O* I/O* I/O I/O I/O I/O XTL2(IN)-I/O GND RESET VCC DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O I/O I/O D6-I/O I/O I/O* I/O I/O I/O* D5-I/O CS0-I/O I/O* I/O* D4-I/O I/O VCC GND D3-I/O CS1-I/O I/O* I/O* D2-I/O Pin Number 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 XC3042A XC3064A XC3090A I/O I/O I/O* I/O I/O* D1-I/O RDY/BUSY-RCLK-I/O I/O I/O D0-DIN-I/O DOUT-I/O CCLK VCC GND A0-WSI/O A1-CS2-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O* I/O* A14-I/O A5-I/O I/O (XC3090 only) GND VCC A13-I/O A6-I/O I/O* I/O (XC3090 only) I/O* A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC GND

Unprogrammed IOBs have a default pull-up. This prevents an undened pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * Indicates unconnected package pins (24) for the XC3042A.

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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)

XC3000 Series 160-Pin PQFP Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 XC3064A, XC3090A, XC3195A I/O* I/O* I/O* I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O* I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O* I/O* M1-RDATA PQFP Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 XC3064A, XC3090A, XC3195A GND M0RTRIG VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O* I/O* I/O I/O I/O I/O I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O* XTL2-I/O GND RESET VCC DONE/PG PQFP Pin Number 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 XC3064A, XC3090A, XC3195A D7-I/O XTL1-I/O-BCLKIN I/O* I/O I/O D6-I/O I/O I/O I/O I/O I/O D5-I/O CS0-I/O I/O* I/O* I/O I/O D4-I/O I/O VCC GND D3-I/O CS1-I/O I/O I/O I/O* I/O* D2-I/O I/O I/O I/O I/O I/O D1-I/O RDY/BUSY-RCLK-I/O I/O I/O I/O* D0-DIN-I/O DOUT-I/O PQFP Pin Number 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 XC3064A, XC3090A, XC3195A CCLK VCC GND A0-WS-I/O A1-CS2-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O I/O A14-I/O A5-I/O I/O* GND VCC A13-I/O A6-I/O I/O* I/O* I/O I/O A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC GND PWRDWN TCLKIN-I/O

Unprogrammed IOBs have a default pull-up. This prevents an undened pad level for unbonded or unused IOBs. Programmed IOBs are default slew-rate limited. *Indicates unconnected package pins (18) for the XC3064A.

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XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PGA Pin Number B2 D4 B3 C4 B4 A4 D5 C5 B5 A5 C6 D6 B6 A6 B7 C7 D7 A7 A8 B8 C8 D8 D9 C9 B9 A9 A10 D10 C10 B10 A11 B11 D11 C11 A12 B12 C12 D12 A13 B13 C13 A14 XC3090A, XC3195A PWRDN TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PGA Pin Number D13 B14 C14 B15 D14 C15 E14 B16 D15 C16 D16 F14 E15 E16 F15 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 L15 M16 M15 L14 N16 P16 N15 R16 M14 P15 N14 R15 P14 XC3090A, XC3195A I/O M1-RDATA GND M0-RTRIG VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O XTL2(IN)-I/O GND RESET VCC PGA Pin Number R14 N13 T14 P13 R13 T13 N12 P12 R12 T12 P11 N11 R11 T11 R10 P10 N10 T10 T9 R9 P9 N9 N8 P8 R8 T8 T7 N7 P7 R7 T6 R6 N6 P6 T5 R5 P5 N5 T4 R4 P4 R3 XC3090A, XC3195A DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O I/O I/O I/O I/O D6-I/O I/O I/O I/O I/O I/O D5-I/O CS0-I/O I/O I/O I/O I/O D4-I/O I/O VCC GND D3-I/O CS1-I/O I/O I/O I/O I/O D2-I/O I/O I/O I/O I/O I/O D1-I/O RDY/BUSY-RCLK-I/O I/O I/O I/O I/O D0-DIN-I/O PGA Pin Number N4 R2 P3 N3 P2 M3 R1 N2 P1 N1 L3 M2 M1 L2 L1 K3 K2 K1 J1 J2 J3 H3 H2 H1 G1 G2 G3 F1 F2 E1 E2 F3 D1 C1 D2 B1 E3 C2 D3 C3 XC3090A, XC3195A DOUT-I/O CCLK VCC GND A0-WS-I/O A1-CS2-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O I/O A14-I/O A5-I/O I/O I/O GND VCC A13-I/O A6-I/O I/O I/O I/O I/O A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC GND

Unprogrammed IOBs have a default pull-up. This prevents an undened pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. Pins A2, A3, A15, A16, T1, T2, T3, T15 and T16 are not connected. Pin A1 does not exist.

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XC3000 Series 176-Pin TQFP Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 XC3090A PWRDWN TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 XC3090A M1-RDATA GND M0-RTRIG VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O XTAL2(IN)-I/O GND RESET VCC Pin Number 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 XC3090A DONE-PG D7-I/O XTAL1(OUT)-BCLKIN-I/O I/O I/O I/O I/O D6-I/O I/O I/O I/O I/O I/O D5-I/O CS0-I/O I/O I/O I/O I/O D4-I/O I/O VCC GND D3-I/O CS1-I/O I/O I/O I/O I/O D2-I/O I/O I/O I/O I/O I/O D1-I/O RDY/BUSY-RCLK-I/O I/O I/O I/O I/O D0-DIN-I/O DOUT-I/O CCLK Pin Number 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 XC3090A VCC GND A0-WS-I/O A1-CS2-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O I/O A14-I/O A5-I/O I/O I/O GND VCC A13-I/O A6-I/O I/O I/O I/O I/O A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC GND

Unprogrammed IOBs have a default pull-up. This prevents an undened pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited.

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XC3000 Series 208-Pin PQFP Pinouts

XC3000A, and XC3000L families have identical pinouts
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 XC3090A GND PWRDWN TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M1-RDATA GND M0-RTRIG Pin Number 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 XC3090A VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O XTL2-I/O GND RESET Pin Number XC3090A 105 106 VCC 107 D/P 108 109 D7-I/O 110 XTL1-BCLKIN-I/O 111 I/O 112 I/O 113 I/O 114 I/O 115 D6-I/O 116 I/O 117 I/O 118 I/O 119 120 I/O 121 I/O 122 D5-I/O CS0-I/O 123 124 I/O 125 I/O 126 I/O 127 I/O 128 D4-I/O 129 I/O 130 VCC 131 GND 132 D3-I/O 133 CS1-I/O 134 I/O 135 I/O 136 I/O 137 I/O 138 D2-I/O 139 I/O 140 I/O 141 I/O 142 143 I/O 144 I/O 145 D1-I/O 146 RDY/BUSY-RCLK-I/O 147 I/O 148 I/O 149 I/O 150 I/O 151 DIN-D0-I/O 152 DOUT-I/O 153 CCLK 154 VCC 155 156 Pin Number 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 XC3090A GND WS-A0-I/O CS2-A1-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O I/O A14-I/O A5-I/O I/O I/O GND VCC A13-I/O A6-I/O I/O I/O I/O I/O A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC

Unprogrammed IOBs have a default pull-up. This prevents an undened pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. *In PQ208, XC3090A and XC3195A have different pinouts.

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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)

XC3195A PQ208 and PG223 Pinouts

Pin Description A9-I/O A10-I/O I/O I/O I/O I/O A8-I/O A11-I/O I/O I/O I/O I/O A7-I/O A12-I/O I/O I/O I/O I/O I/O I/O A6-I/O A13-I/O VCC GND I/O I/O A5-I/O A14-I/O I/O I/O I/O I/O A4-I/O A15-I/O I/O I/O I/O I/O A3-I/O A2-I/O I/O I/O I/O I/O A1-CS2-I/O A0-WS-I/O GND VCC CCLK DOUT-I/O

PG223 PQ208 B1 206 E3 205 E4 204 C2 203 C1 202 D2 201 E2 200 F4 199 F3 198 D1 197 F2 196 G2 194 G4 193 G1 192 H2 191 H3 190 H1 189 H4 188 J3 187 J2 186 J1 185 K3 184 J4 183 K4 182 K2 181 K1 180 L2 179 L4 178 L3 177 L1 176 M1 175 M2 174 M4 173 N2 172 N3 171 P2 169 R1 168 N4 167 T1 166 R2 165 P3 164 T2 163 P4 162 U1 161 V1 160 T3 159 R3 158 R4 157 U2 156 V2 155

PG223 PQ208 U3 154 V3 153 R5 152 T4 151 V4 150 RDY/BUSY-RCLK-I/O U4 149 D1-I/O U5 148 I/O R6 147 I/O T5 146 I/O U6 145 I/O T6 144 I/O V7 141 I/O R7 140 I/O U7 139 D2-I/O V8 138 I/O U8 137 I/O T8 136 I/O R8 135 I/O V9 134 CS1-I/O U9 133 D3-I/O T9 132 GND R9 131 VCC R10 130 I/O T10 129 D4-I/O U10 128 I/O V10 127 I/O R11 126 I/O T11 125 I/O U11 124 CS0-I/O V11 123 D5-I/O U12 122 I/O R12 121 I/O V12 120 I/O T13 119 I/O U13 118 I/O T14 117 I/O R13 116 I/O U14 115 D6-I/O U15 114 I/O V15 113 I/O T15 112 I/O R14 111 I/O V16 110 XTLX1(OUT)BCLKN-I/O U16 109 D7-I/O T16 108 D/P V17 107 VCC R15 106 RESET U17 105 GND R16 104 XTL2(IN)-I/O V18 103

Pin Description D0-DIN-I/O I/O I/O I/O I/O

Pin Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC INIT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LDC-I/O I/O I/O I/O HDC-I/O M2-I/O VCC M0-RTIG GND M1/RDATA I/O

PG223 PQ208 U18 102 P15 101 T17 100 T18 99 P16 98 R17 97 N15 96 R18 95 P17 94 N17 93 N16 92 M15 89 M18 88 M17 87 L18 86 L17 85 L15 84 L16 83 K18 82 K17 81 K16 80 K15 79 J15 78 J16 77 J17 76 J18 75 H16 74 H15 73 H17 72 H18 71 G17 70 G18 69 G15 68 F16 67 F17 66 E17 63 C18 62 F15 61 D17 60 E16 59 C17 58 B18 57 E15 56 A18 55 A17 54 D16 53 B17 52 D15 51 C16 50 B16 49

Pin Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCLKIN-I/O PWRDN
GND VCC

PG223 PQ208 A16 48 D14 47 C15 46 B15 45 A15 44 C14 43 D13 42 B14 41 C13 40 B13 39 B12 38 D12 37 A12 36 B11 35 C11 34 A11 33 D11 32 A10 31 B10 30 C10 29 C9 28 D10 27 D9 26 B9 25 A9 24 C8 23 D8 22 B8 21 A8 20 B7 19 A7 18 D7 17 B6 14 C6 13 B5 12 A4 11 D6 10 C5 9 B4 8 B3 7 C4 6 D5 5 C3 4 A3 3 A2 2 B2 1
D4 D3 208 207

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. In the PQ208 package, pins 15, 16, 64, 65, 90, 91, 142, 143, 170 and 195 are not connected. In the PG223 package, the following pins are not connected: A5, A6, A13, A14, D18, E1, E18, F1, F18, N1, N18, P1, P18, V5, V6, V13, and V14. *In PQ208, XC3090A and XC3195A have different pinouts.

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Product Availability
Pins 44 Plast. PLCC PC44 64 Plast. VQFP VQ64 68 Plast. PLCC PC68 Plast. PLCC PC84 84 Cer. PGA PG84 Plast.P QFP PQ100 100 Plast. TQFP Plast. VQFP TopBrazed CQFP 132 Plast. PGA PP132 Cer. PGA 144 Plast. TQFP 160 Plast. PQFP 164 TopBrazed CQFP 175 Plast. PGA PP175 Cer. PGA 176 Plast. TQFP 208 Plast. PQFP 223 Cer. PGA

Type Code

TQ100 VQ100 CB100

PG132 TQ144 PQ160 CB164

PG175 TQ176 PQ208 PG223

XC3020A XC3030A XC3042A XC3064A XC3090A XC3020L XC3030L XC3042L XC3064L XC3090L

XC3120A

XC3130A

XC3142A

XC3164A

XC3190A

XC3195A

-7 -6 -7 -6 -7 -6 -7 -6 -7 -6 -8 -8 -8 -8 -8 -5 -4 -3 -2 -1 -09 -5 -4 -3 -2 -1 -09 -5 -4 -3 -2 -1 -09 -5 -4 -3 -2 -1 -09 -5 -4 -3 -2 -1 -09 -5 -4 -3 -2 -1 -09

CI C

CI C

CI C CI C

CI

CI CI CI CI C C

CI CI CI CI C C

CI CI CI CI C C CI CI CI CI C C

CI C CI C CI C CI C CI C CI CI CI CI CI CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C

CI C CI C CI C

CI C CI C CI C

CI C CI C

CI C CI C

CI C CI C

CI C CI C CI C

CI C CI C

CI C

CI C

CI C

CI C

CI CI

CI CI CI

CI

CI CI CI CI C C CI CI CI CI C C CIMB CI CI CI C C

CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C

CI CI CI CI C C C C CI CI C C

MB

C C CI CI C C CI CI CI CI C C

CIMB CI CI CI C C CI CI CI CI C C

CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C

CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C

MB

MB

CI CI CI CI C C CI CI CI CI C C

CIMB CI CI CI C C CIMB CI CI CI C C

CI CI CI CI C C

CI CI CI CI C C CI CI CI CI C C

CIMB CI CI CI C C

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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)

Pins

44 Plast. PLCC PC44

64 Plast. VQFP VQ64

68 Plast. PLCC PC68 Plast. PLCC PC84

84 Cer. PGA PG84 Plast.P QFP PQ100

100 Plast. TQFP Plast. VQFP TopBrazed CQFP

132 Plast. PGA PP132 Cer. PGA

144 Plast. TQFP

160 Plast. PQFP

164 TopBrazed CQFP

175 Plast. PGA PP175 Cer. PGA

176 Plast. TQFP

208 Plast. PQFP

223 Cer. PGA

Type Code

TQ100 VQ100 CB100

PG132 TQ144 PQ160 CB164

PG175 TQ176 PQ208 PG223

XC3142L XC3190L Notes:

-3* -2* -3* -2* * Advance Information

C C C C

C C

C C C C

C C

C = Commercial, TJ= 0 to +85C M=Military Temp, TC= -55 to +125C

I = Industrial, TJ = -40 to +100C B = MIL-STD-883C Class B

Number of Available I/O Pins

Number of Package Pins Max I/O XC3020A/XC3120A XC3030A/XC3130A XC3042A/XC3142A XC3064A/XC3164A XC3090A/XC3190A XC3195A 64 80 96 120 144 176 44 34 64 54 68 58 58 84 64 74 74 70 70 70 100 120 132 144 156 160 164 175 176 191 196 208 223 240 64 80 82

96 96 110 120 120

120 138 144 144 144 138 144

144 176 176

X7067

Ordering Information

Example: Device Type Speed Grade

XC3030A-3 PC44C Temperature Range Number of Pins Package Type

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SPROM Products

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conguration PROMs
0 5*

December 10, 1997(Version 1.1)

Product Specification

Features
On-chip address counter, incremented by each rising edge on the clock input Simple interface to the FPGA; requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions Supports XC4000EX/XL fast conguration mode (15.0 MHz) Low-power CMOS Floating Gate process Available in 5 V and 3.3 V versions Available in compact plastic packages: 8-pin PDIP, 20-pin SOIC, and 20-pin PLCC. Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages.

Description
The XC1701L, XC1701 and XC17512L serial conguration PROMs (SCPs) provide an easy-to-use, cost-effective method for storing Xilinx FPGA conguration bitstreams. When the FPGA is in master serial mode, it generates a conguration clock that drives the SCP. A short access time after the rising clock edge, data appears on the SCP DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the conguration. Once congured, it disables the SCP. When the FPGA is in slave mode, the SCP and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all SCPs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design le into a standard Hex format, which is then transferred to the programmer.
VCC VPP

GND

CE RESET/ OE or OE/ RESET CLK Address Counter TC

CEO

EPROM Cell Matrix

Output

OE DATA

X3185

Figure 1: Simplied Block Diagram (does not show programming circuit)

December 10, 1997(Version 1.1)

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XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conguration PROMs

Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low.

Serial PROM Pinouts

Pin Name DATA CLK RESET/OE (OE/RESET) CE GND CEO VPP VCC 8-Pin PDIP 1 2 3 4 5 6 7 8 20-Pin SOIC 1 3 8 10 11 13 18 20 20-Pin PLCC 2 4 6 8 10 14 17 20

CLK
Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active.

RESET/OE
When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is 3-stated. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW130 Programmer. Third-party programmers have different methods to invert this pin.

Capacity
Device XC1701L XC1701 XC17512L Conguration Bits 1,048,576 1,048,576 524,288

Number of Conguration Bits, Including Header for all Xilinx FPGAs and Compatible SCP Type
Device XC4010XL XC4013XL XC4020E XC4020XL XC4025E XC4028XL XC4028EX XC4036EX XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL Conguration Bits 283,424 393,623 329,312 521,880 422,176 668,184 668,184 832,528 832,528 1,014,928 1,215,368 1,433,864 1,924,992 SPROM XC17512L XC17512L XC1701 XC17512L XC1701 XC1701L XC1701 XC1701 XC1701L XC1701L XC1701L + XC17256L XC1701L + XC17512L 2 x XC1701L

CE
When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-ICC standby mode.

CEO
Chip Enable output, to be connected to the CE input of the next SCP in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low.

VPP
Programming voltage. No overshoot above the specied max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP oating!

VCC and GND

Positive supply and ground pins.

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December 10, 1997(Version 1.1)

Controlling Serial PROMs

Most connections between the FPGA device and the Serial PROM are simple and self-explanatory. The DATA output(s) of the of the Serial PROM(s) drives the DIN input of the lead FPGA device. The master FPGA CCLK output drives the CLK input(s) of the Serial PROM(s). The CEO output of a Serial PROM drives the CE input of the next Serial PROM in a daisy chain (if any). The RESET/OE input of all Serial PROMs is best driven by the INIT output of the XC3000 or XC4000 lead FPGA device. This connection assures that the Serial PROM address counter is reset before the start of any (re)conguration, even when a reconguration is initiated by a VCC glitch. Other methods such as driving RESET/OE from LDC or system reset assume that the Serial PROM internal power-on-reset is always in step with the FPGAs internal power-on-reset, which may not be a safe assumption. The CE input of the lead (or only) Serial PROM is driven by the DONE/PRGM or DONE output of the lead FPGA device, provided that DONE/PRGM is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum.

internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for conguration, it must still be held at a dened level during normal operation. The XC3000 and XC4000 families take care of this automatically with an onchip default pull-up resistor.

Programming the FPGA With Counters Unchanged Upon Completion

When multiple FPGA-congurations for a single FPGA are stored in a Serial Conguration PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and conguration begins with the rst program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after conguration is complete. Therefore, to reprogram the FPGA with another program, the D/P line is pulled Low and conguration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA conguration process. The FPGA aborts the conguration and then restarts a new conguration, as intended, but the Serial PROM does not reset its address counter, since it never saw a High level on its OE input. The new conguration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (24) and D/P goes High. However, the FPGA conguration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during conguration.

FPGA Master Serial Mode Summary

The I/O and logic functions of the Logic Cell Array and their associated interconnections are established by a conguration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA automatically loads the conguration program from an external memory. The Serial Conguration PROM has been designed for compatibility with the Master Serial Mode. Upon power-up or reconguration, an FPGA enters the Master Serial Mode whenever all three of the FPGA modeselect pins are Low (M0=0, M1=0, M2=0). Data is read from the Serial Conguration PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during conguration. Master Serial Mode provides a simple conguration interface. Only a serial data line and two control lines are required to congure an FPGA. Data from the Serial Conguration PROM is read sequentially, accessed via the

Cascading Serial Conguration PROMs

For multiple FPGAs congured as a daisy-chain, or for future FPGAs requiring larger conguration memories, cascaded SCPs provide additional memory. After the last bit from the rst SCP is read, the next clock signal to the SCP asserts its CEO output Low and disables its DATA line. The second SCP recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After conguration is complete, the address counters of all cascaded SCPs are reset if the FPGA RESET pin goes Low, assuming the SCP reset polarity option has been inverted. To reprogram the FPGA with another program, the D/P line goes Low and conguration begins where the address counters had stopped. In this case, avoid contention between DATA and the congured I/O use of DIN.

December 10, 1997(Version 1.1)

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XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conguration PROMs

* If Readback is Activated, a 3.3-k Resistor is Required in Series With M1 During Configuration the 3.3 k M2 Pull-Down Resistor Overcomes the Internal Pull-Up, but it Allows M2 to be User I/O.

Vcc

M0 M1 PWRDWN DOUT M2 HDC GeneralPurpose User I/O Pins LDC INIT OPTIONAL Daisy-chained FPGAs with Different Configurations

Other I/O Pins OPTIONAL Slave FPGAs with Identical Configurations Vcc

FPGA

RESET

RESET DIN CCLK D/P INIT VCC DATA CLK CE OE/RESET VPP DATA CLK Cascaded Serial CE Memory OE/RESET

SCP CEO

(Low Resets the Address Pointer)

CCLK (OUTPUT)

DIN

DOUT (OUTPUT)

X8256

Figure 2: Master Serial Mode. The one-time-programmable Serial Conguration PROM supports automatic loading of conguration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active.

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Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input.

Programming
The devices can be programmed on programmers supplied by Xilinx or qualied third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device.

Table 1: Truth Table for XC1700 Control Inputs Control Inputs RESET Inactive Active Inactive Active CE Low Low High High Internal Address if address < TC: increment if address > TC: dont change Held reset Not changing Held reset Outputs DATA active 3-state 3-state 3-state 3-state CEO High Low High High High Icc active reduced active standby standby

Notes: 1. The XC1700 RESET input has programmable polarity

2. TC = Terminal Count = highest address value. TC+1 = address 0.

IMPORTANT: Always tie the VPP pin to VCC in your application. Never leave VPP oating.

December 10, 1997(Version 1.1)

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XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conguration PROMs

XC1701 Absolute Maximum Ratings

Symbol VCC VPP VIN VTS TSTG TSOL
Note:

Description Supply voltage relative to GND Supply voltage relative to GND Input voltage relative to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) -0.5 to +7.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260

Units V V V V C C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Operating Conditions
Symbol VCC Description Commercial Industrial Military Supply voltage relative to GND 0C to +70C junction Supply voltage relative to GND -40C to +85C junction Supply voltage relative to GND -55C to +125C case Min 4.75 4.50 4.50 Max 5.25 5.50 5.50 Units V V V

DC Characteristics Over Operating Condition

Symbol VIH VIL VOH VOL VOH VOL ICCA ICCS IL High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode Supply current, standby mode Input or output leakage current -10.0 Industrial 3.76 0.37 10.0 50.0 10.0 Commercial Description Min 2.0 0 3.86 0.32 Max VCC 0.8 Units V V V V V V mA A A

Note: During normal read operation VPP must be connected to VCC

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XC1701L/XC17512L Absolute Maximum Ratings

Symbol VCC VPP VIN VTS TSTG TSOL Description Supply voltage relative to GND Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) -0.5 to +6.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V V C C

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Operating Conditions
Symbol VCC Description Commercial Supply voltage relative to GND 0C to +70C junction Min 3.0 Max 3.6 Units V

DC Characteristics Over Operating Condition

Symbol VIH VIL VOH VOL ICCA ICCS IL High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode Supply current, standby mode Input or output leakage current -10.0 Description Min 2.0 0 2.4 0.4 5.0 50.0 10.0 Max VCC 0.8 Units V V V V mA A A

Note: During normal read operation VPP must be connected to VCC

December 10, 1997(Version 1.1)

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XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conguration PROMs

AC Characteristics Over Operating Condition

CE 9 RESET/OE 11 THOE TLC 7 CLK TOE 2 DATA 4 TOH
X2634

TSCE

9 TSCE

10 THCE

8 THC

6 TCYC

3 TCAC

4 TOH

5 TDF

TCE

Symbol

Description

XC1701 Min Max 25 45 45 50 67 20 20 20 0 20

XC1701L XC17512L Min Max 30 60 60 50 100 25 25 25 0 25

Units ns ns ns ns ns ns ns ns ns ns ns

OE to Data Delay 1 TOE CE to Data Delay 2 TCE 3 TCAC CLK to Data Delay Data Hold From CE, OE, or CLK 4 TOH CE or OE to Data Float Delay2 5 TDF 6 TCYC Clock Periods CLK Low Time3 7 TLC 8 THC CLK High Time3 9 TSCE CE Setup Time to CLK (to guarantee proper counting) CE Hold Time to CLK (to guarantee proper counting) 10 THCE OE Hold Time (guarantees counters are reset) 11 THOE Notes: 1. AC test load = 50 pF

2. Float delays are measured with minimum tester ac load and maximum dc load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.

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AC Characteristics Over Operating Condition (continued)

RESET/OE

CE

CLK 12 TCDF DATA Last Bit 13 TOCK CEO 14 TOCE 14 TOCE

X3183

First Bit 15 TOOE

Symbol 12 13 14 15 TCDF TOCK TOCE TOOE

Description CLK to Data Float Delay2 CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay

XC1701 Min Max 50 30 35 30

XC1701L XC17512L Min Max 50 30 35 30

Units ns ns ns ns

Notes: 1. AC test load = 50 pF

2. Float delays are measured with minimum tester ac load and maximum dc load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.

December 10, 1997(Version 1.1)

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XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conguration PROMs

Ordering Information XC1701L - PC20 C

Device Number
XC1701L XC1701 XC17512L

Operating Range/Processing Package Type

PD8 = 8-Pin Plastic DIP SO20 = 20-Pin Plastic Small-Outline Package PC20 = 20-Pin Plastic Leaded Chip Carrier C = Commercial (0 to +70C) I = Industrial (40 to +85C)

Marking Information
Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package. The XC prex is deleted and the package code is simplied. Device marking is as follows.

1701L
Device Number
XC1701L XC1701 XC17512L

C
Operating Range/Processing
C = Commercial (0 to +70C) I = Industrial (40 to +85C)

Package Type
P S J = 8-Pin Plastic DIP = 20-Pin Plastic Small-Outline Package = 20-Pin Plastic Leaded Chip Carrier

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December 10, 1997(Version 1.1)

XC1700E Family of Serial Conguration PROMs

0 5*

March 30, 1998 (Version 1.0)

Preliminary Product Specification

Features
Serial Conguration one-time programmable (OTP) read-only memory designed to store conguration bitstreams of Xilinx FPGA devices Simple interface to the FPGA requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions All devices support the XC4000EX/XL fast conguration mode (15.0 MHz) Low-power CMOS oating gate process Available in 5 V and 3.3 V versions Available in compact plastic 8-pin DIP, 8-pin SOIC, 8pin VOIC, or 20-pin PLCC packages. Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages.

Description
The XC1700 family of serial conguration PROMs (SCPs) provides an easy-to-use, cost-effective method for storing Xilinx FPGA conguration bitstreams. When the FPGA is in master serial mode, it generates a conguration clock that drives the SCP. A short access time after the rising clock edge, data appears on the SCP DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the conguration. Once congured, it disables the SCP. When the FPGA is in slave mode, the SCP and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all SCPs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or the Foundation series development systems compiles the FPGA design le into a standard HEX format which is then transferred to the programmer.

VCC

VPP

GND

CE RESET/ OE or OE/ RESET CLK Address Counter TC

CEO

EPROM Cell Matrix

Output

OE DATA

X3185

Figure 1: Simplied Block Diagram (does not show programming circuit)

March 30, 1998 (Version 1.0)

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XC1700E Family of Serial Conguration PROMs

Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low.

Serial PROM Pinouts

Pin Name DATA CLK RESET/OE (OE/RESET) CE GND CEO VPP VCC 8-Pin 1 2 3 4 5 6 7 8 20-Pin 2 4 6 8 10 14 17 20

CLK
Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active.

RESET/OE
When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is 3-stated. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW130 programmer software. Third-party programmers have different methods to invert this pin.

Capacity
Device Conguration Bits XC1736E 36,288 XC1765E or EL 65,536 XC17128E or EL 131,072 XC17256E or EL 262,144 XC17512L 524,288 XC1701 or L 1,048,576 Note: The XC1701L, XC17512L and the XC1701 are specied in a separate datasheet.

CE
When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into lowICC standby mode.

CEO
Chip Enable output, to be connected to the CE input of the next SCP in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low.

VPP
Programming voltage. No overshoot above the specied max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP oating!

VCC and GND

VCC is positive supply pin and GND is ground pin.

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March 30, 1998 (Version 1.0)

Number of Conguration Bits, Including Header for Xilinx FPGAs and Compatible SCP Types
Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028EX/XL XC4036EX/XL XC4044XL XC4052XL XC4062XL XC4085XL XC5202 XC5204 XC5206 XC5210 XC5215 Conguration Bits 53,984 95,008 119,840 147,552 178,144 247,968 329,312 422,176 61,100 151,960 283,424 393,632 521,880 668,184 832,528 1,014,928 1,215,368 1,433,864 1,924,992 42,416 70,704 106,288 165,488 237,744 SCP XC17128E1 XC17128E XC17128E XC17256E XC17256E XC17256E XC1701 XC1701 XC17128EL1 XC17256EL XC17512L XC17512L XC17512L XC1701L XC1701L XC1701L XC1701L + XC17256EL XC1701L + XC17512L 2 XC1701L XC1765E XC17128E XC17128E XC17256E XC17256E

Controlling Serial PROMs

Most connections between the FPGA device and the Serial PROM are simple and self-explanatory. The DATA output(s) of the Serial PROM(s) drives the DIN input of the lead FPGA device. The master FPGA CCLK output drives the CLK input(s) of the Serial PROM(s). The CEO output of a Serial PROM drives the CE input of the next Serial PROM in a daisy chain (if any). The RESET/OE input of all Serial PROMs is best driven by the INIT output of the XC4000 lead FPGA device. This connection assures that the Serial PROM address counter is reset before the start of any (re)conguration, even when a reconguration is initiated by a VCC glitch. Other methods such as driving RESET/OE from LDC or system reset assume that the Serial PROM internal power-on-reset is always in step with the FPGAs internal power-on-reset, which may not be a safe assumption. The CE input of the lead (or only) Serial PROM is driven by the DONE/PRGM or DONE output of the lead FPGA device, provided that DONE/PRGM is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum.

FPGA Master Serial Mode Summary

The I/O and logic functions of the Logic Cell Array and their associated interconnections are established by a conguration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA automatically loads the conguration program from an external memory. The Serial Conguration PROM has been designed for compatibility with the Master Serial Mode. Upon power-up or reconguration, an FPGA enters the Master Serial Mode whenever all three of the FPGA modeselect pins are Low (M0=0, M1=0, M2=0). Data is read from the Serial Conguration PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during conguration. Master Serial Mode provides a simple conguration interface. Only a serial data line and two control lines are required to congure an FPGA. Data from the Serial Conguration PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for conguration, it must still be held at

Note: 1. SCP type is determined by compatibility with the

higher conguration frequency of the Xilinx FPGA CCLK. Designers using the default slow conguration frequency (CCLK) can use the XC1765E or XC1765EL for the noted FPGA devices.

March 30, 1998 (Version 1.0)

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XC1700E Family of Serial Conguration PROMs

a dened level during normal operation. The XC4000 family takes care of this automatically with an on-chip default pull-up resistor.

Programming the FPGA With Counters Unchanged Upon Completion

When multiple FPGA-congurations for a single FPGA are stored in a Serial Conguration PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and conguration begins with the rst program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after conguration is complete. Therefore, to reprogram the FPGA with another program, the D/P line is pulled Low and conguration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA conguration process. The FPGA aborts the conguration and then restarts a new conguration, as intended, but the Serial PROM does not reset its address counter, since it never saw a High level on its OE input. The new conguration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK

pulses, up to 16 million (224) and D/P goes High. However, the FPGA conguration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during conguration.

Cascading Serial Conguration PROMs

For multiple FPGAs congured as a daisy-chain, or for future FPGAs requiring larger conguration memories, cascaded SCPs provide additional memory. After the last bit from the rst SCP is read, the next clock signal to the SCP asserts its CEO output Low and disables its DATA line. The second SCP recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After conguration is complete, the address counters of all cascaded SCPs are reset if the FPGA RESET pin goes Low, assuming the SCP reset polarity option has been inverted. To reprogram the FPGA with another program, the D/P line goes Low and conguration begins where the address counters had stopped. In this case, avoid contention between DATA and the congured I/O use of DIN.

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March 30, 1998 (Version 1.0)

* If Readback is Activated, a 3.3-k Resistor is Required in Series With M1 During Configuration the 3.3 k M2 Pull-Down Resistor Overcomes the Internal Pull-Up, but it Allows M2 to be User I/O.

Vcc

M0 M1 PWRDWN DOUT M2 HDC GeneralPurpose User I/O Pins LDC INIT OPTIONAL Daisy-chained FPGAs with Different Configurations

Other I/O Pins OPTIONAL Slave FPGAs with Identical Configurations Vcc

FPGA

RESET

RESET DIN CCLK D/P INIT VCC DATA CLK CE OE/RESET VPP DATA CLK Cascaded Serial CE Memory OE/RESET

SCP CEO

(Low Resets the Address Pointer)

CCLK (OUTPUT)

DIN

DOUT (OUTPUT)

X8256

Figure 2: Master Serial Mode. The one-time-programmable Serial Conguration PROM supports automatic loading of conguration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active.

March 30, 1998 (Version 1.0)

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XC1700E Family of Serial Conguration PROMs

Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input.

Programming the XC1700 Family Serial PROMs

The devices can be programmed on programmers supplied by Xilinx or qualied third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device.

Table 1: Truth Table for XC1700 Control Inputs Control Inputs RESET Inactive Active Inactive Active CE Low Low High High Internal Address if address < TC: increment if address > TC: dont change Held reset Not changing Held reset Outputs DATA active 3-state 3-state 3-state 3-state CEO High Low High High High Icc active reduced active standby standby

Notes: 1. The XC1700 RESET input has programmable polarity

2. TC = Terminal Count = highest address value. TC+1 = address 0.

Important: Always tie the VPP pin to VCC in your application. Never leave VPP oating.

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March 30, 1998 (Version 1.0)

XC1736E, XC1765E, XC17128E and XC17256E Absolute Maximum Ratings

Symbol VCC VPP VIN VTS TSTG TSOL Note: Description Supply voltage relative to GND Supply voltage relative to GND Input voltage relative to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) -0.5 to +7.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V V C C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Operating Conditions
Symbol VCC Description Commercial Industrial Supply voltage relative to GND 0C to +70C junction Supply voltage relative to GND -40C to +85C junction Min 4.75 4.50 Max 5.25 5.50 Units V V

DC Characteristics Over Operating Condition

Symbol VIH VIL VOH VOL VOH VOL ICCA ICCS High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode Supply current, standby mode XC17128E, XC17256E XC1736E, XC1765E IL CIN COUT Note: Input or output leakage current Input Capacitance (VIN = GND, f = 1.0MHz) Output Capacitance (VIN = GND, f = 1.0MHz)
During normal read operation VPP must be connected to VCC

Description

Min 2.0 0 3.86 Commercial

Max VCC 0.8

Units V V V

0.32 3.76 Industrial 0.37 10.0 50.0 1.5 -10.0 10.0 10.0 10.0

V V V mA A mA A pF pF

March 30, 1998 (Version 1.0)

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XC1700E Family of Serial Conguration PROMs

XC1765EL, XC17128EL and XC17256EL Absolute Maximum Ratings

Symbol VCC VPP VIN VTS TSTG TSOL Description Supply voltage relative to GND Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) -0.5 to +4.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V V C C

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Operating Conditions
Symbol VCC Description Commercial Industrial Supply voltage relative to GND 0C to +70C junction Supply voltage relative to GND -40C to +85C junction Min 3.0 3.0 Max 3.6 3.6 Units V V

DC Characteristics Over Operating Condition

Symbol VIH VIL VOH VOL VOH VOL ICCA ICCS High-level input voltage Low-level input voltage High-level output voltage (IOH = -3 mA) Low-level output voltage (IOL = +3 mA) High-level output voltage (IOH = -3 mA) Low-level output voltage (IOL = +3 mA) Supply current, active mode Supply current, standby mode XC17128EL, XC17256EL XC1765EL IL CIN COUT Input or output leakage current Input Capacitance (VIN = GND, f = 1.0MHz) Output Capacitance (VIN = GND, f = 1.0MHz) -10.0 2.4 Industrial 0.4 5.0 50.0 1.5 10.0 10.0 10.0 V mA A mA A pF pF Commercial 0.4 V V Description Min 2.0 0 2.4 Max VCC 0.8 Units V V V

Note: During normal read operation VPP must be connected to VCC

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AC Characteristics Over Operating Condition

CE 9 RESET/OE 11 THOE TLC 7 CLK TOE 2 DATA 4 TOH
X2634

TSCE

9 TSCE

10 THCE

8 THC

6 TCYC

3 TCAC

4 TOH

5 TDF

TCE

Symbol 1 2 3 4 5 6 7 8 9 TOE TCE

Description OE to Data Delay CE to Data Delay

XC1736E XC1765E Min Max 45 60 80

3

XC1765EL Min Max 45 60 200 0

XC17128E XC17256E Min Max 25 45 45 0

XC17128EL XC17256EL Min Max 30 45 45 0

Units ns ns ns ns

TCAC CLK to Data Delay TOH TDF Data Hold From CE, OE, or CLK CE or OE to Data Float Delay 0

2&3

50 100 400 100 100 40 0 100

50 67 20 20 20 0 20

50 67 25 25 25 0 25

50

ns ns ns ns ns ns ns

TCYC Clock Periods TLC THC CLK Low Time

3 3

50 50 25 0 100

CLK High Time

CE Setup Time to CLK (to guarantee TSCE proper counting) CE Hold Time to CLK (to guarantee proper counting) OE Hold Time (guarantees counters are reset)

10 THCE 11 THOE

Notes: 1. AC test load = 50 pF

2. Float delays are measured with minimum tester AC load and maximum DC load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.

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XC1700E Family of Serial Conguration PROMs

AC Characteristics Over Operating Condition (continued)

RESET/OE

CE

CLK 12 TCDF DATA Last Bit 13 TOCK CEO 14 TOCE 14 TOCE

X3183

First Bit 15 TOOE

Symbol

Description

XC1736E XC1765E XC17128E XC17256E Min Max 50 30 35 30

XC1765EL XC17128EL XC17256EL Min Max 50 30 35 30

Units

12 13 14 15

TCDF TOCK TOCE TOOE

CLK to Data Float Delay2 & 3 CLK to CEO Delay CE to CEO Delay
3 3

ns ns ns ns

RESET/OE to CEO Delay3

Notes: 1. AC test load = 50 pF

2. Float delays are measured with minimum tester AC load and maximum DC load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.

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Ordering Information XC17256E VO8

Device Number
XC1736E XC1765E XC1765EL XC17128E XC17128EL XC17256E XC17256EL

C
Operating Range/Processing
C = Commercial (0C to +70C) I = Industrial (40C to +85C)

Package Type
PD8 SO8 VO8 PC20 = = = = 8-Pin Plastic DIP 8-Pin Plastic Small-Outline Package 8-Pin Plastic Small-Outline Thin Package 20-Pin Plastic Leaded Chip Carrier

Valid Ordering Combinations

XC17128EPD8C XC17128EVO8C XC17128EPC20C XC17128EPD8I XC17128EVO8I XC17128EPC20I XC17256EPD8C XC17256EVO8C XC17256EPC20C XC17256EPD8I XC17256EVO8I XC17256EPC20I XC1736EPD8C XC1736ESO8C XC1736EVO8C XC1736EPC20C XC1736EPD8I XC1736ESO8I XC1736EVO8I XC1736EPC20I XC1765EPD8C XC1765ESO8C XC1765EVO8C XC1765EPC20C XC1765EPD8I XC1765ESO8I XC1765EVO8I XC1765EPC20I XC1765ELPD8C XC1765ELSO8C XC1765ELVO8C XC1765ELPC20C XC1765ELPD8I XC1765ELSO8I XC1765ELVO8I XC1765ELPC20I

XC17128ELPD8C XC17128ELVO8C XC17128ELPC20C XC17128ELPD8I XC17128ELVO8I XC17128ELPC20I

XC17256ELPD8C XC17256ELVO8C XC17256ELPC20C XC17256ELPD8I XC17256ELVO8I XC17256ELPC20I

Marking Information
Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package. The XC prex is deleted and the package code is simplied. Device marking is as follows.

17256E
Device Number
XC1736E XC1765E XC1765X XC17128E XC17128X XC17256E XC17256X

C
Operating Range/Processing
C = Commercial (0C to +70C) I = Industrial (40C to +85C)

Package Type
P S V J = = = = 8-Pin Plastic DIP 8-Pin Plastic Small-Outline Package 8-Pin Plastic Small-Outline Thin Package 20-Pin Plastic Leaded Chip Carrier

Note: When marking the device number on the EL parts, an X is used in place of an EL.

March 30, 1998 (Version 1.0)

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XC1700E Family of Serial Conguration PROMs

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Spartan and Spartan-XL Families of Serial Conguration PROMs

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Advance Product Specification

Introduction
The Spartan family of Serial Conguration PROMs (SPROM) provides and easy-to-use, cost-effective method for storing Spartan device conguration bitstreams. When the Spartan device is in Master Serial mode, it generates a conguration clock that drives the Spartan SPROM. A short access time after the rising clock edge, data appears on the SPROM DATA output pin that is connected to the Spartan device DIN pin. The Spartan device generates the appropriate number of clock pulses to complete the conguration. Once congured, it disables the SPROM. When a Spartan device is in Slave Serial mode, the SPROM and the Spartan device must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all SPROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or the Foundation series development systems compiles the Spartan device design le into a standard HEX format which is then transferred to most commercial PROM programmers.

Spartan SPROM Features

Serial Conguration one-time programmable (OTP) read-only memory designed to store conguration bitstreams of Spartan FPGA devices Simple interface to the Spartan device requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) Low-power CMOS oating gate process Available in 5 V and 3.3 V versions Available in compact plastic 8-pin DIP, 8-pin VOIC, or 20-pin SOIC (XC17S40 only) packages. Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages.

Spartan FPGA XCS05 XCS05XL XCS10 XCS10XL XCS20 XCS20XL XCS30 XCS30XL XCS40 XCS40XL

Compatible Spartan SPROM XC17S05 XC17S05XL XC17S10 XC17S10XL XC17S20 XC17S20XL XC17S30 XC17S30XL XC17S40 XC17S40XL

Conguration Bits 65,536 131,072 131,072 131,072 262,144 262,144 262,144 262,144 524,288 524,288

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23

Spartan and Spartan-XL Families of Serial Conguration PROMs

Pin Description
Table 1: Spartan PROM Pinouts Pin Name DATA 8-Pin PDIP & VOIC 1 20-Pin SOIC 1 Pin Description Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is 3-stated. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 programmer software. Third-party programmers have different methods to invert this pin. When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-ICC standby mode. GND is the ground connection. Chip Enable output, to be connected to the CE input of the next SPROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. The VCC pins are to be connected to the positive voltage supply.

CLK

RESET/OE (OE/RESET)

CE GND

4 5

10 11

CEO

13

VCC

7, 8

18, 20

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March 30, 1998 (Version 1.0)

Controlling Serial PROMs

Connecting the Spartan device with the SPROM: The DATA output of the SPROM drives the DIN input of the lead Spartan device. The Master Spartan device CCLK output drives the CLK input of the SPROM. The RESET/OE input of the SPROM is driven by the INIT output of the Spartan device. This connection assures that the SPROM address counter is reset before the start of any (re)conguration, even when a reconguration is initiated by a VCC glitch. Other methods such as driving RESET/OE from LDC or system reset assume that the SPROM internal poweron-reset is always in step with the FPGAs internal power-on-reset, which may not be a safe assumption. The CE input of the SPROM is driven by the DONE output of the Spartan device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum.

If the user-programmable, dual-function DIN pin on the Spartan device is used only for conguration, it must still be held at a dened level during normal operation. The Spartan family takes care of this automatically with an on-chip default pull-up resistor.

Programming the FPGA With Counters Unchanged Upon Completion

When multiple-congurations for a single Spartan device are stored in a Serial Conguration PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and conguration begins with the rst program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after conguration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and conguration begins at the last value of the address counters. This method fails if a user applies RESET during the Spartan device conguration process. The Spartan device aborts the conguration and then restarts a new conguration, as intended, but the SPROM does not reset its address counter, since it never saw a High level on its OE input. The new conguration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the Spartan device is the Master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. However, the Spartan device conguration will be completely wrong, with potential contentions inside the Spartan device and on its output pins. This method must, therefore, never be used when there is any chance of external reset during conguration.

FPGA Master Serial Mode Summary

The I/O and logic functions of the Conguration Logic Block (CLB) and their associated interconnections are established by a conguration program. The program is loaded either automatically upon power up, or on command, depending on the state of the Spartan device MODE pin. In Master Serial mode, the Spartan device automatically loads the conguration program from an external memory. The Spartan SPROM has been designed for compatibility with the Master Serial mode. Upon power-up or reconguration, the Spartan device enters the Master Serial mode when the MODE pin is Low. Data is read from the Serial Conguration PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during conguration. Master Serial mode provides a simple conguration interface. Only a serial data line and two control lines are required to congure the Spartan device. Data from the Serial Conguration PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK.

Cascading Serial Conguration PROMs

For multiple Spartan devices congured as a daisy-chain, cascaded SPROMs provide additional memory. After the last bit from the rst SPROM is read, the next clock signal to the SPROM asserts its CEO output Low and disables its DATA line. The second SPROM recognizes the Low level on its CE input and enables its DATA output. After conguration is complete, the address counters of all cascaded SPROMs are reset if the Spartan device RESET pin goes Low, assuming the SPROM reset polarity option has been inverted. To reprogram the Spartan device with another program, the DONE line goes Low and conguration begins where the address counters had stopped. In this case, avoid contention between DATA and the congured I/O use of DIN.

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Spartan and Spartan-XL Families of Serial Conguration PROMs

Vcc PWRDWN

SPARTAN FPGA
MODE DOUT HDC GeneralPurpose User I/O Pins LDC INIT VCC Other I/O Pins DIN CCLK DONE RESET RESET INIT DATA CLK SPARTAN SPROM CEO CE OE/RESET DATA CLK Cascaded SPARTAN CE SPROMs OE/RESET Vcc

(Low Resets the Address Pointer)

CCLK (OUTPUT)

DIN

DOUT (OUTPUT)

X8472

Figure 1: Master Serial Mode. The one-time-programmable Spartan SPROM supports automatic loading of conguration programs. Multiple devices can be cascaded to support additional Spartan FPGAs. An early DONE inhibits the PROM data output one CCLK cycle before the Spartan FPGA I/Os become active.

Standby Mode
The SPROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input.

Programming the Spartan Family Serial PROMs

The devices can be programmed on programmers supplied by Xilinx or qualied third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device.

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March 30, 1998 (Version 1.0)

VCC

GND

RESET/ OE
or

CE

CEO

OE/ RESET

CLK

Address Counter

TC

EPROM Cell Matrix

Output

OE DATA

X8473

Figure 2: Simplied Block Diagram (does not show programming circuit) Important: Always tie the two VCC pins together in your application. Table 2: Truth Table for XC17S00 Control Inputs Control Inputs Internal Address RESET Inactive Active Inactive Active CE Low Low High High if address < TC: increment if address > TC: dont change Held reset Not changing Held reset DATA active 3-state 3-state 3-state 3-state CEO High Low High High High Icc active reduced active standby standby Outputs

Notes: 1. The XC17S00 RESET input has programmable polarity

2. TC = Terminal Count = highest address value. TC+1 = address 0.

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Spartan and Spartan-XL Families of Serial Conguration PROMs

XC17S05, XC17S10, XC17S20, XC17S30, XC17S40 Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL ESD Note: Description Supply voltage relative to GND Input voltage relative to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Human Body Model MIL-STD-883D Method 3015 Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 4000 Units V V V C C V

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Operating Conditions
Symbol VCC Description Commercial Industrial Note: Supply voltage relative to GND (TA = 0C to +70C) Supply voltage relative to GND (TA = -40C to +85C) Min 4.75 4.50 Max 5.25 5.50 Units V V

During normal read operation both VCC pins must be connected together.

DC Characteristics Over Operating Condition

Symbol VIH VIL VOH VOL VOH VOL ICCA ICCS IL CIN COUT High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode (at maximum frequency) Supply current, standby mode Input or output leakage current Input Capacitance (VIN = GND, f = 1.0MHz) Output Capacitance (VIN = GND, f = 1.0MHz) -10.0 Industrial 3.76 0.37 10.0 50.0 10.0 10.0 10.0 Commercial Description Min 2.0 0 3.86 0.32 Max VCC 0.8 Units V V V V V V mA A A pF pF

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XC17S05XL, XC17S10XL, XC17S20XL, XC17S30XL, XC17S40XL Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL ESD Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Human Body Model MIL-STD-883D Method 3015 Value -0.5 to +4.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 4000 Units V V V C C V

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Operating Conditions
Symbol VCC Description Commercial Industrial Note: Supply voltage relative to GND (TA = 0C to +70C) Supply voltage relative to GND (TA = -40C to +85C) Min 3.0 3.0 Max 3.6 3.6 Units V V

During normal read operation both VCC pins must be connected together.

DC Characteristics Over Operating Condition

Symbol VIH VIL VOH VOL VOH VOL ICCA ICCS IL CIN COUT High-level input voltage Low-level input voltage High-level output voltage (IOH = -3 mA) Low-level output voltage (IOL = +3 mA) High-level output voltage (IOH = -3 mA) Low-level output voltage (IOL = +3 mA) Supply current, active mode (at maximum frequency) Supply current, standby mode Input or output leakage current Input Capacitance (VIN = GND, f = 1.0MHz) Output Capacitance (VIN = GND, f = 1.0MHz) -10.0 Industrial 2.4 0.4 5.0 50.0 10.0 10.0 10.0 Commercial Description Min 2.0 0 2.4 0.4 Max VCC 0.8 Units V V V V V V mA A A pF pF

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Spartan and Spartan-XL Families of Serial Conguration PROMs

AC Characteristics Over Operating Condition

CE 9 RESET/OE 11 THOE TLC 7 CLK TOE 2 DATA 4 TOH
X2634

TSCE

9 TSCE

10 THCE

8 THC

6 TCYC

3 TCAC

4 TOH

5 TDF

TCE

Symbol 1 2 3 4 5 6 7 8 9 10 11 TOE TCE TCAC TOH TDF TCYC TLC THC TSCE THCE THOE OE to Data Delay CE to Data Delay

Description

Min

Max 45 60 80

Units ns ns ns ns

CLK to Data Delay Data Hold From CE, OE, or CLK3 CE or OE to Data Float Delay
2&3

0 50 100 50 50 25 0 25

ns ns ns ns ns ns ns

Clock Periods (TCCLK on FPGA) CLK Low Time

3 3

CLK High Time

CE Setup Time to CLK (to guarantee proper counting) CE Hold Time to CLK (to guarantee proper counting) OE Hold Time (guarantees counters are reset)

Notes: 1. AC test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at +200mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.

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March 30, 1998 (Version 1.0)

AC Characteristics Over Operating Condition When Cascading

RESET/OE

CE

CLK 12 TCDF DATA Last Bit 13 TOCK CEO 14 TOCE 14 TOCE

X3183

First Bit 15 TOOE

Symbol 12 13 14 15 TCDF TOCK TOCE TOOE

Description CLK to Data Float Delay2 & 3 CLK to CEO Delay CE to CEO Delay
3 3

Min

Max 50 30 35 30

Units ns ns ns ns

RESET/OE to CEO Delay3

Notes: 1. AC test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at +200mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.

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Spartan and Spartan-XL Families of Serial Conguration PROMs

Ordering Information XC17S20XL VO8

Device Number
XC17S05 XC17S05XL XC17S10 XC17S10XL XC17S20 XC17S20XL XC17S30 XC17S30XL XC17S40 XC17S40XL

C
Operating Range/Processing C = Commercial (TA = 0C to +70C) I = Industrial (TA =40C to +85C)

Package Type
PD8 = 8-Pin Plastic DIP VO8 = 8-Pin Plastic Small-Outline Thin Package SO20 = 20-Pin Plastic Small-Outline Package

Valid Ordering Combinations

XC17S05PD8C XC17S05VO8C XC17S05PD8I XC17S05VO8I XC17S05XLPD8C XC17S05XLVO8C XC17S05XLPD8I XC17S05XLVO8I XC17S10PD8C XC17S10VO8C XC17S10PD8I XC17S10VO8I XC17S10XLPD8C XC17S10XLVO8C XC17S10XLPD8I XC17S10XLVO8I XC17S20PD8C XC17S20VO8C XC17S20PD8I XC17S20VO8I XC17S20XLPD8C XC17S20XLVO8C XC17S20XLPD8I XC17S20XLVO8I XC17S30PD8C XC17S30VO8C XC17S30PD8I XC17S30VO8I XC17S30XLPD8C XC17S30XLVO8C XC17S30XLPD8I XC17S30XLVO8I XC17S40PDC XC17S40SO20C XC17S40PD8I XC17S40SO20I XC17S40XLPD8C XC17S40XLSO20C XC17S40XLPD8I XC17S40XLSO20I

Marking Information
Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package. The XC prex is deleted and the package code is simplied. Device marking is as follows.

17S20L V C
Device Number
XC17S05 XC17S05L XC17S10 XC17S10L XC17S20 XC17S20L XC17S30 XC17S30L XC17S40 XC17S40L

Package Type
P V S = 8-Pin Plastic DIP = 8-Pin Plastic Small-Outline Thin Package = 20-Pin Plastic Small-Outline Package

Operating Range/Processing C = Commercial (TA = 0C to +70C) I = Industrial (TA = 40C to +85C)

Note: When marking the device number on the XL parts, an L is used in place of an XL.

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3V Products

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

3V Products Table of Contents

3.3 V and Mixed Voltage Compatible Products

FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V FPGAs with On-Chip RAM: XC4000XL and Spartan-XL. . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V FPGAs Without On-Chip RAM: XC3100L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V Zero+ Family of Ultra-Low Power FPGAs: XC3000L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V FPGAs for Mixed-Voltage Systems: XC4000E/EX and Spartan Series . . . . . . . . . . . . . . CPLDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V CPLDs for Mixed-Voltage Systems: XC9500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfacing Between 5.0 V and 3.3 V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V Devices Driving Inputs on 5.0 V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V Devices Driving Inputs on 3.3 V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the XC4000E/EX and Spartan FPGAs in Mixed-Voltage Systems . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-1 6-1 6-1 6-1 6-1 6-1 6-2 6-2 6-2 6-3 6-4

3.3 V and Mixed Voltage Compatible Products

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The use of advanced deep-submicron IC fabrication processes is resulting in rapidly increasing density and performance for programmable logic devices, as evidenced by the XC4000XL FPGA family. However, as device geometries shrink below 0.5 microns, the smallest transistors cannot withstand 5 volts without damage. Thus, the largest and fastest new devices are based on lower supply voltages, such as the 3.3 V standard. To reap the benets of advanced process technology including increased performance, increased density, lower power consumption, and lower price - many programmable logic users are making the transition from the 5.0 V standard to lower voltages. This transition affects not only the supply voltage, but also I/O signaling levels. Xilinx is taking an active lead in working with programmable logic users to plan an orderly transition from one voltage standard to the next. Xilinx introduced the Zero+ product line, the industrys first 3.3 V FPGAs, in 1993. Since then, the number of 3.3 V product offerings has increased dramatically. For example, the new XC4000XL FPGA family, featuring the industrys highest-capacity high-performance FPGAs, is based on the 3.3 V standard. However, many other system components remain available in 5.0 V versions only. Thus, mixed-voltage systems (i.e., systems employing a mix of 5.0 V and 3.3 V components) are likely to be the rule rather than the exception in the immediate future. Xilinx products have been designed with this in mind (see Table 1). 5.0 V input tolerance has been designed into many Xilinx 3.3 V devices; these devices accept 5.0 V signals on all I/Os and can drive TTL levels into any 5.0 V device, eliminating any interface issues. Many Xilinx 5.0 V components can directly interface with 3.3 V devices. Future devices will feature multi-voltage I/Os capable of interfacing between a variety of I/O standards. All Xilinx device inputs maintain their excellent protection against Electro-Static Discharge (ESD), even in mixed-voltage applications. The following is a brief description of Xilinx devices suitable for use in 3.3 V and mixed 3.3/5.0 V systems. Complete data sheets for the products mentioned below can be found in Chapters 3 and 4 of this Data Book. 3.3 V versions of the Serial PROM devices also are available (see Chapter 6).

FPGAs
3.3 V FPGAs with On-Chip RAM: XC4000XL and Spartan-XL
The XC4000XL family is the broadest and highest-capacity 3.3 V FPGA product line in the industry, with ten devices ranging from 465 to 7,448 logic cells (about 5,000 to 85,000 logic gates). The Spartan Series of high-performance, lowcost FPGAs offers ve devices ranging from 238 to 1,862 logic cells. The XC4000XL and Spartan-XL devices meet the specications of 3.3 V PCI applications. See Chapter 4 for complete product descriptions.

3.3 V FPGAs Without On-Chip RAM: XC3100L

The two members of the XC3100L FPGA family are fast 3.3 V FPGAs. See Chapter 4 for complete product descriptions.

3.3 V Zero+ Family of Ultra-Low Power FPGAs: XC3000L

The XC3000L FPGA devices have quiescent supply currents below 1 mA, with some below 50 A. See Chapter 4 for complete product descriptions.

5.0 V FPGAs for Mixed-Voltage Systems: XC4000E/EX and Spartan Series

The 5.0 V XC4000E/EX and Spartan FPGA families feature a unique output structure that makes them suitable for mixed-voltage system applications. When congured in TTL mode, the XC4000E/EX and Spartan devices can be directly mixed with 3.3 V devices, as described below. See Chapter 4 for complete product descriptions.

CPLDs
5.0 V CPLDs for Mixed-Voltage Systems: XC9500
Xilinx CPLDs are an excellent t for mixed-voltage systems. The Input/Output (I/O) ring can be powered by either a 5.0 V VCCIO or a 3.3 V VCCIO. Independent of the VCCIO voltage level, the inputs can accept 5.0 V and 3.3 V inputs. The rail-to-rail output level is dened by VCCIO. These single-chip solutions function extremely well in mixed-voltage systems without any performance penalty. See Chapter 3 for complete product descriptions.

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3.3 V and Mixed Voltage Compatible Products

Table 1: Supply Voltage Options Device Family

Single

Accepts 3.3 V Availability Device Outputs1

Now Now Now Now Now Now Yes Yes Yes Yes Yes Yes

Drives 3.3 V Device Inputs

With limiting resistor With limiting resistor Yes Yes With limiting resistor With limiting resistor

Key Features
Low quiescent current High performance Highest density and performance High performance, low cost Most cost-effective 5.0 V in-system-programmable, pin locking

Supply VCC = 5.0 V

XC3000A XC3100A XC4000E/EX Spartan XC5200 XC9500

Single Supply VCC = 3.3 V

Device Family
XC3000L XC3100L XC4000XL Spartan-XL

Accepts 5.0 V Availability Device Outputs

Now Now Now 3Q98 With limiting resistor With limiting resistor Yes Yes

Drives 5.0 V Device Inputs

Yes Yes Yes Yes

Key Features
Very low powerdown & quiescent current High performance Highest Density & performance Cost-effective, high performance

Dual Supply VCC = 5.0 V VCCIO = 3.3 V

Device Family
XC9500

Accepts 5.0 V Availability Device Outputs

Now Yes

Drives 5.0 V Device Inputs

Yes

Key Features
Mixed-voltage system capable

Notes: 1. Device Inputs must be congured for TTL thresholds.

Interfacing Between 5.0 V and 3.3 V Devices

Today, many designs must accommodate both 3.3 V and 5 V components on the same board. Since both types of supply share a common ground, there are no problems interfacing logic Low levels in either direction, but there are compatibility issues for the logic High levels.

the protection circuits in the XC4000XL and Spartan-XL devices are designed to withstand 5.0 V inputs. Most 5.0 V devices have complementary CMOS outputs where VOH can reach the 5.0 V rail. (All Xilinx 5.0 V FPGAs and CPLDs, except the XC4000E/EX and Spartan series devices in default TTL mode, have complementary CMOS outputs. The XC4000E/EX and Spartan devices can be set to CMOS outputs with the design software.) When driving XC3000L and XC3100L inputs (and most other 3.3 V devices) from such a 5.0 V device, the input current must be limited by a series resistor of no less than 150. This guarantees an input current below 10 mA, owing through the ESD input protection diode backwards into the 3.3 V supply. That amount of input current is generally considered safe, causing neither metal migration nor latch-up problems. Care must be taken to avoid forcing the nominally 3.3 V supply voltage above its 3.6 V maximum whenever a large number of active High inputs drive the 3.3 V device, potentially causing the 3.3 V supply current to reverse direction. The 3.3 V VCC power should be on before driving the device inputs from a 5.0 V device. The I/O structures of the XC4000XL and Spartan-XL FPGAs have been designed to tolerate being driven to a 5.0 V rail by a low-impedance source. These 3.3 V FPGAs can be directly driven by 5.0 V devices with either TTL or CMOS outputs. Power supply sequencing is not a problem; the inputs can be driven to 5.0 V either before or after the 3.3 V VCC power is supplied without risking damage to the devices. In mixed voltage systems, the XC9500 CPLD family can be driven directly by 5.0 V inputs when set up for 3.3 V I/O

3.3 V Devices Driving Inputs on 5.0 V Devices

The lowest output High voltage (VOH) of the 3.3 V device must exceed the VIH requirements of the 5.0 V device. Minimum VOH for all Xilinx 3.3 V devices is 2.4 V, well above the 2.0 V minimum High level for TTL signaling. (This includes the XC3000L, XC3100L, XC4000XL, and Spartan-XL FPGA families and the XC9500 CPLD family when VCCIO = 3.3V.) Thus, all Xilinx 3.3 V devices can drive inputs to devices with TTL-compatible input thresholds, including all 5.0 V Xilinx devices. (Note: Some Xilinx 5.0 V devices can be programmed for TTL or CMOS input thresholds; these devices must be congured for TTL-compatible inputs to be directly driven from a 3.3 V device.)

5.0 V Devices Driving Inputs on 3.3 V Devices

The highest 5.0 V device output voltage must not force excessive current into the input of the 3.3 V device. The input structures of Xilinx 3.3 V FPGAs include input protection circuits. These protection circuits in the XC3000L and XC3100L devices are designed for 3.3 V inputs. However,

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operation (i.e., VCCIO = 3.3 V). The input protection circuits in these CPLDs are always connected to the 5.0 V VCC power line, allowing them to tolerate 5.0 V inputs without the need for current-limiting resistors. If the 5.0 V device has totem-pole n-channel-only outputs (as in the default setting of the XC4000E/EX and Spartan FPGA series), VOH is reduced by one threshold and the series resistor can be eliminated, provided the nominally 5.0 V supply does not exceed 5.25 V (as described in detail in the following section). Thus, the XC4000E/EX and Spartan FPGAs can directly drive any 3.3 V device without the need for current-limiting resistors.

istic of a typical 3.3 V device input. Both supply voltages are at their nominal value, but the die temperatures are at their worst-case value of 85 degrees C, and worst-case processing is assumed. Figure 2 shows the same curves, but with 5.25 V and 3.0 V VCC respectively. The intersection of the two curves denes the worst-case operating point of 3.8 V and 6 mA. That means that the XC4000E/Spartan output drives 6 mA into the forward-biased ESD protection diode, raising the input voltage 0.8 V above 3.0 V, the assumed lowest value of the nominally 3.3 V supply voltage.
I mA 10 9 8 7 6 5 4 3 2 1 VCC 3.0 3.3 3.5 4.0 4.5 5.0 5.5
X5969

IIN

Using the XC4000E/EX and Spartan FPGAs in Mixed-Voltage Systems

As a default option, all XC4000E/EX and Spartan devices have a TTL-like input threshold (compatible with 3.3 V output levels) and an n-channel-only totem-pole or TTL-like output structure, with an n-channel transistor pulling the output to a VOH level that is one threshold below VCC. At a nominal 5.0 V VCC, the unloaded output High voltage VOH is less than 3.7 V. When applied to the input of a device with a nominal 3.3 V VCC, there is no additional input current, and the input level does not violate the conventional specication that prohibits input voltages more than 0.5 V above VCC. See Figure 1. If both 5.0 V and 3.3 V supply voltages track reasonably between their maximum and minimum values, there will never be any additional input current in excess of 1 mA at any commercial or industrial operating temperature. A worst-case analysis of the interface might assume the (unrealistic) condition where the 5.0 V supply is at its maximum value (5.25 V for commercial applications), while the 3.3 V supply is at its minimum value of 3.0 V. Under these conditions, the interface violates the conventional specication, and drives current into the input of the 3.3 V device, as shown in Figure 2. However, as explained below, this interface is reliable. For protection against electro-static discharge (ESD), most CMOS inputs and I/O pins usually have a diode between the pin and the nearest VCC connection. This diode prevents the input from going substantially more positive than VCC, which might destroy the input transistor by rupturing its gate oxide. At room temperature, this ESD protection diode conducts negligible current at < 0.6 V forward bias, and conducts ~1 mA at ~0.7 V forward bias, typical for any silicon junction diode. These voltages have a predictable negative temperature coefcient of 2 mV per degree C. At 85 degrees C, these voltages are, therefore, 120 mV lower. Figure 1 superimposes the output characteristic of the XC4000E/EX and Spartan, and the input current character-

IOUT

Nominal Supply Voltages 85C

Figure 1: XC4000E/Spartan Output in TTL-Mode driving 3.3 V Device Input with Both Supplies at Nominal Voltage (5.0 V and 3.3 V)

I mA 10 9 8 7 6 5 4 3 2 1 IOUT

IIN

VCC 3.0 3.5 4.0 4.5 5.0 5.5

X5970

Figure 2: XC4000E/Spartan Output in TTL-Mode driving 3.3 V Device Input with Both Supplies at Extreme Values (5.25 V and 3.0 V)

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3.3 V and Mixed Voltage Compatible Products

Although this input condition is not covered by the conventional specication, it does not cause any harm and does not affect reliability. ESD protection diodes are designed to conduct hundreds of mA, and the absolute value of the input voltage with respect to ground will never exceed 3.9 V. If the input pin is part of an I/O structure, there is a theoretical possibility of causing latch-up, but all reputable IC manufacturers design their circuits such that latch-up does not occur below 100 mA of input current per pin. The system designer must estimate the sum of all maximum input currents, and calculate the impact of this current owing backwards towards the 3.3 V supply. But even if the total 3.3 V supply current goes to zero, VCC for the 3.3 V device is still limited to < 3.6 V (the highest output voltage of the 5 V device minus the forward voltage drop of the ESD diode).

Conclusion
5 V XC4000E/EX and Spartan devices can be freely mixed with 3.3 V devices, without any current or voltage limiting interface resistors, if the following conditions are met: The 5.0 V XC4000E/EX and Spartan devices are in their default TTL mode with respect to input thresholds and output levels. The upper limit on the 5 V VCC is 5.25 V and the lower limit on the 3.3 V supply is 3.0 V, as per standard commercial specications. For industrial operating conditions with higher VCC max, the user must make sure that the absolute difference between the two supply voltages does not exceed 2.20 V. Specically, if the nominally 5 V VCC is at its max value of 5.50 V, the nominally 3.3 V VCC must not be lower than 3.30 V.

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HardWire FpgASIC Products

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

HardWire Products Table of Contents

Xilinx HardWire FpgASIC Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technology Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advantages of the Xilinx HardWire Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Re-verifying the Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Coverage and Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging and Silicon Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support for the entire Product Life Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HardWire Design/ Production Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Submittal Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of the Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HardWire Product Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx HardWire Product Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC23xx, XC33xx and XC43xx Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC23xx, XC33xx and XC43xx Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC44xxE/EX/XL and XC54xx Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC44xx/E/EX/XL and XC54XX Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XH3 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XH3 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HardWire Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-1 7-1 7-1 7-2 7-2 7-2 7-3 7-3 7-3 7-5 7-5 7-5 7-5 7-5 7-5 7-5 7-6 7-6 7-6 7-6 7-6 7-6 7-6 7-6

Xilinx HardWire FpgASIC Overview

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Introduction
When a system incorporating Xilinx FPGAs moves to high volume production, HardWire FpgASIC products should be the rst consideration for cost reduction. HardWire products are the only devices developed specically for Xilinx FPGAs which provide 100% pin compatible replacements. The HardWire conversion ow coupled with the HardWire test methodology provides a no risk path for customers to achieve dramatic cost reductions. Using Xilinx FPGAs and HardWire technology provides the customer with a single source for systems, software and silicon. This combination provides the fastest method for prototype development and production of systems based on leading edge programmable logic technology. Each HardWire product family is developed to match the performance and features of specic Xilinx FPGAs including the popular XC2xxx, XC3xxx, XC4xxx and XC5xxx series families. The newest family of HardWire FpgASICs are designed to provide a cost reduced device incorporating the latest features of Xilinx FPGAs including E, EX and XL technology.

path that is 100% guaranteed to perform in the users application.

Advantages of the Xilinx HardWire Methodology

Converting a device from programmable logic to a HardWire FpgASIC has many advantages over standard gate array redesign. The most important is that HardWire devices are developed using a fully turnkey process. No additional customer engineering is required to convert the programmable logic design into a fully tested, completely veried HardWire device. This ease of conversion is available only from Xilinx. HardWire devices are developed using the actual physical database previously created and veried in the process of developing the FPGA design. The HardWire conversion methodology preserves all the attributes of the original physical database le. If the design is mapped to a third party library at the schematic level for conversion to another technology, the design must be veried and prototyped. Third party implementations will change the placement and routing, thereby changing the designs performance characteristics. This means the new device must be re-veried and re-tested in the system to be certain that the performance and functionality still meet the applications requirements. A comparison of the activities required to convert a HardWire FpgASIC versus a generic gate array is shown in Figure 1.

Technology Overview
Xilinx Hardwire ASIC products are FPGA specic ASICs (FpgASICs). They are a family of devices ranging from 1.0 single mask mapped ASICs to state-of-the-art sea-ofgates 0.5 and 0.35 multi-mask ASIC devices. The HardWire product families have been developed to match the performance and features of each generation of Xilinx FPGAs. The HardWire ow is the simplest method for cost reducing an FPGA based system. The Xilinx Design Once methodology offers Xilinx customers the advantages of developing prototypes, building pre-production and initial production volumes using Xilinx FPGAs. Once the design is stable and cost reduction is critical, customers can convert the FPGA to a HardWire device developed especially for the features and performance of that FPGA. The turnkey conversion process allows production quality HardWire prototypes to be developed in half the time of traditional gate arrays. The HardWire methodology provides this without using customers engineering resources. HardWire FpgASICs provide a cost - effective alternative to gate arrays. Xilinx HardWire product families use a combination of industry standard and Xilinx patented test generation methods to achieve the most complete fault coverage possible. This testing strategy allows Xilinx to offer a cost reduction November 4, 1997 (Version 2.0)

Re-verifying the Design

In conventional gate array conversion (redesign), the design must be re-veried after the schematic is translated or recaptured. The process of re-verifying a design is rigorous and time consuming. Functional simulation vectors need to be created, and the device must be exhaustively simulated before and after place and route. A suitable test methodology must be considered and implemented. All this is usually done by the customer, at the customers expense and risk. In contrast, no additional effort is required when converting to a HardWire FpgASIC. The HardWire design is self-verifying because the actual FPGA database les are used for the conversion. This makes the HardWire conversion process the only guaranteed, fully turnkey FpgASIC conversion.

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Xilinx HardWire FpgASIC Overview

Working Xilinx FPGA Design

Generic Gate Array Convert netlist to G/A format Logic changes for design compatibility Logic changes for pin compatibility Logic changes for conguration emulation Logic changes for Boundary Scan Design Check Functional Simulation Place and Route Back-Annotation Timing simulation and new models Test Vector generation Create custom masks

Xilinx Hardwire FpgASIC Design Check/Evaluation

Design Conversion

Create Custom Masks

Figure 1: Steps Involved in Converting a PLD Design to a Gate Array as Compared to a HardWire FpgASIC

Fault Coverage and Test Vectors

All designs need to be testable. In a traditional gate array, the designer is required to build in testability and generate test vectors to verify chip performance by exercising as much of the device circuitry as possible. Most designers strive for greater than 90% fault coverage. However, they often settle for signicantly less because the iterative process is time consuming and increases exponentially as fault coverage is increased. A third party conversion from a Xilinx FPGA to a generic gate array or other similar technology will require test vector generation. Typically, the original designers create test vectors, since they are most familiar with the FPGAs design. This method misuses valuable design resources and reverses the value of the decision to use programmable logic for their ease of design and timeto-market advantage. Another method is to contract with the conversion or gate array vendor to create the test vectors. This method is both expensive and time consuming. In some cases, conversion or gate array vendors will accept a design without test vectors, but the customer accepts the liability of determining whether the resulting device is production worthy. In todays competitive market, most projects can not afford the risk of possible re-spins if the design doesnt work. Converting from a Xilinx FPGA to a HardWire FpgASIC requires no test vector generation by the customer. HardWire devices use a combination of industry standard and Xilinx patented test generation methods to achieve the most complete fault coverage possible. Xilinx guarantees greater than 95% fault coverage for most designs. All HardWire FpgASICs are tested using a full scan test methodology. The HardWire conversion and test methodology provides a cost reduction path that is guaranteed to work in the customers application. 7-2

Packaging and Silicon Considerations

All of the physical attributes of HardWire FpgASIC's are virtually identical to the Xilinx FPGA. HardWire devices are manufactured in the same fabrication facilities used by Xilinx for the production of FPGAs. The same design rules, IC process, as well as packaging, assembly, and test facilities are used. This allows a signicant reduction in the time and cost associated with qualifying HardWire devices. Converting from a Xilinx programmable logic device to any third party device means a change in silicon, packaging, assembly and test. Each of these changes adds an element of risk into the qualication process.

Support for the entire Product Life Cycle

Figure 2 shows the typical life cycle of a high-volume product. It illustrates the optimal way of using the programmable and HardWire devices. During development, prototyping and initial production cycles, the programmable device is the best choice. As the system moves into higher volume production and no additional modications are being made to the design, a HardWire FpgASIC can be used in place of the original programmable logic device. Since the HardWire device and the programmable logic device are functionally and physically identical, production can be switched back to the programmable device if the situation warrants. For example, if the demand for the customers product increases dramatically, production can be increased immediately by full-lling the additional demand with programmable devices. The change can be made immediately since there is virtually no lead-time for an off-

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Programmable Logic Volume HardWire FpgASIC Volume Unplanned Upside Production Ramp-Up V O L U M E End-of-Life

HardWire FpgASIC

X5946

Figure 2: Typical High Volume Product Life Cycle the-shelf programmable device. Production can also be switched to the programmable device as the product ends its life cycle and volume decreases. This eliminates the need for end-of-life buys and the risk of obsolescence. Furthermore, designs implemented with multiple static RAM based programmable devices can be cost reduced incrementally, converting one or more of the programmable devices to a HardWire FpgASIC with the balance remaining as FPGAs. As each FPGA is converted to a HardWire device, the user benets by having a lower cost for that device. This also allows the user to maintain the ease of use of off-the-shelf programmable logic in the other sockets. When all of the devices are converted, the storage element (PROM) can be removed, giving even further cost reductions. This exibility is unique to Xilinx, and allows customers to achieve cost reduction quickly with minimal effort. tionality of the FPGA and HardWire device are identical, virtually no customer engineering resources are needed to move from the programmable to the HardWire devices or vice versa. By comparison, using a traditional gate array to reproduce functions implemented in the FPGA would require extensive simulation and test development.

Design Submittal Process

Once the complete design submittal kit is received the HardWire conversion process takes from 3 to 8 weeks. The conversion time will vary with the addition of features such as Select-RAM, Conguration Emulation and JTAG. A complete design submittal kit contains the following: 1. Files: .LCA (or .NGD for M1 designs), .MBO, and .BIT les on disk. 2. Hard copy of a board level schematic showing how the FPGA interfaces with other components on the board (if possible). 3. A detailed explanation of any special requirements for the conversion. 4. A design submittal form and NRE PO. All forms can be found in the HardWire data book and on the Xilinx web page under HardWire products.

HardWire Design/ Production Interface

Figure 3 illustrates how the design, development and production activities for both Programmable Logic devices and HardWire FpgASICs are sequenced. Notice that by using the Xilinx Design Once methodology, no additional customer activity is needed to develop the HardWire FpgASIC. If design simulation is done in the programmable logic device during development, special HardWire speed les may be also be used for design verication. This allows Xilinx to perform a very simple design check procedure prior to generating the HardWire device. After the design check is complete the HardWire prototypes can be manufactured. The customer then performs in-system verication of the prototypes. Once this verication is complete the HardWire FpgASIC can be released to production. Since the func-

Summary of the Conversion Process

The HardWire FpgASIC conversion process is the simplest way to cost reduce systems designed using FPGAs. The customer is involved in tracking and approving milestones. Xilinx handles the day-to-day activities of converting the design to a HardWire device. Once Xilinx receives a complete design submittal kit the conversion process begins.

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Xilinx HardWire FpgASIC Overview

Customer Design Functions

Xilinx Development Interface

Xilinx Manufacturing Functions

Design Concept

Production FPGA HardWire Design Considerations and Verification

Programmable FPGA Design Entry Logic Simulation Xilinx Netlist Format Programmable FPGA Design Implementation Array and Bitstream Production EPROM/PROM Programming

XACTstep-M1 XACTstep Development System Schematic Capture Simulation Design Libraries Automatic Design Implementation

Programmable FPGA Flow

Initial Production with Programmable FPGA High Volume Production Achieved

Inventory of Programmable Array Devices

HardWire FpgASIC Design Review

Purchase Order Initial Design Submittal .LCA(.NGD for M1) .MBO .BIT .RBT Design File

DRC Analysis/Report

HardWire FpgASIC Flow

Automatic Test Generation

Xilinx Design Analysis

Final HardWire FpgASIC Design Verification

HardWire FpgASIC Design Verification NRE Invoiced Custom Masks Made

Prototypes Delivered System Verification

HardWire FpgASIC
Volume Units

Prototypes Built

Protoptye Approval

Signoff
HardWire FpgASIC Production Builds
X7089_01

HardWire FpgASIC Production

Figure 3: Programmable/HardWire Design/Production Interface

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November 4, 1997 (Version 2.0)

Table 1: HardWire Products Device Family XC2xxx XC3xxx XC4xxx XC4xxxE/EX/XL XC4xxxE/EX/XL XC5xxx Speed Grade All All -4 and slower -3 and slower -3 and faster All Features Supported All All No E features E, EX, XL E, EX, XL Non XL Hardwire FpgASIC Family XC2318 XC33xx XC43xx XC44xx XH3xx XC54xx Notes 1 1 1

Note 1: Some devices require re-routing before conversion. Refer to the HardWire Data Book

Xilinx rst reviews the design to determine any items that could impact the performance of the HardWire device. A conversion evaluation report is sent to the customer. After the report has been reviewed and the customer is satised, conversion begins. At the completion of the conversion a Design Verication Report and Design Verication Form (DVF) are sent to the customer. Once the DVF is completed the HardWire les are sent to the mask shop for prototyping. If any custom markings are required they must be submitted to Xilinx with the Design Verication Form (DVF). Prototypes are produced, tested and shipped to the customer for in-system testing. The customer signs the prototype approval form and returns it to Xilinx. Production can begin.

technology, the memory cells and programmable interconnect logic they control are replaced by metal connections. All other circuitry in the resulting HardWire device is identical to the corresponding FPGA internal circuitry. The resulting HardWire FpgASIC is a semi-custom device manufactured to provide a specic function, yet it is completely compatible with the FPGA. This product family is the fastest and most simple method of converting rst generation Xilinx FPGAs. For more details on XC23xx, XC33xx and XC43xx products please see the Xilinx HardWire Data Book.

XC23xx, XC33xx and XC43xx Summary

Features
Designed for conversion of XC2xxx, XC3xxx and XC4xxx (no E features) FPGAs. Single Mask Direct Mapped - Turnkey conversion from FPGA device. On-chip scan path test latches. Fully pin-for-pin compatible. Simple and efcient conversion process. Very fast conversion completion time. Conversion success rate over 95%. No customer developed test vectors needed, 99% fault coverage. Drop-in replacement for Xilinx FPGAs.

HardWire Product Families

Each HardWire product family is developed to support the features, density and performance of a specic generation of Xilinx FPGAs. See Table 1 for product family details. For designs developed using Xilinx XC2xxx, XC3xxx or XC4xxx (no E features) FPGAs, the XC23xx, XC33xx and 43xx product families provide a fast and simple cost reduction path. For designs developed using Xilinx XC4xxx (E, EX and XL) and XC5xxx FPGAs, the XC44xx and XC54xx product families provide the most effective technology, cost and performance. For customers using fast, dense Xilinx XC4xxxE, EX and XL or XC5xxx FPGAs the XH3 product family provides the most efcient and cost effective solution available. Most HardWire FpgASICs are available in 3.3v versions. All HardWire devices support commercial and industrial temperature ranges.

Benets

XC44xxE/EX/XL and XC54xx Product Description

The second generation HardWire FpgASIC product family was developed to match the performance, density and features of Xilinx XC4xxxE, EX, XL and XC5xxx family of FPGAs. This HardWire FpgASIC product family supports all the features of Xilinx second generation FPGAs. This includes 3 speed grades, Conguration Emulation (CE), JTAG and Select-RAM. The XC44xx and XC54xx product family follows a more traditional sea-of-gates approach to mapping used CLBs of the FPGA. The used memory cells and programmable interconnect logic of the FPGA are mapped into a corresponding area of a traditional gate

Xilinx HardWire Product Descriptions

XC23xx, XC33xx and XC43xx Product Description
The initial HardWire product family was developed to match the performance of Xilinx XC2xxx, XC3xxx and slower XC4xxx family FPGAs. This family is still in production today. In standard programmable logic, the functions and interconnections are determined by conguration data stored in memory cells. In the rst generation HardWire November 4, 1997 (Version 2.0)

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Xilinx HardWire FpgASIC Overview

array base. The FPGAs unused CLBs are not mapped into the resulting HardWire device. The HardWire device uses the smallest base array possible while maintaining the performance and functionality of the corresponding FPGA. These devices support most 3.3 volt and 5 volt FPGAs. The feature sizes of the arrays used in the XC44xx and XC54xx product family (1.0 through .45) are highly competitive with traditional gate arrays. The wide range of base array feature sizes available allows Xilinx to provide a HardWire device with the smallest possible die size. The same guaranteed turnkey conversion methodology is used. XC44xx and XC54xx devices provide the most cost-effective method for converting XC4xxxE, XC4xxxEX, XC4xxxXL and XC52xx FPGAs to a low cost HardWire FpgASIC.

mum efciency. The XH3 architecture implements SelectRAM 30% more efciently than generic gate arrays. In generic gate array methodologies, features such as Conguration Emulation, JTAG and Select-RAM usually require additional silicon area. The result is a larger, more expensive die and changes to the FPGA netlist throughout the conversion process. In many cases implementing Xilinx Select-RAM in a third party gate array may require substantially more gates than the Xilinx XH3 device. XH3 devices incorporate these features without silicon overhead or changes to the netlist.

XH3 Summary
Features
Designed for conversion of XC4xxxE, EX, XL and XC5xxx FPGAs. Xilinx FPGA features built in to the base array. Multiple Mask, state-of-the-art 0.5 and 0.35 process technology. Pad counts and gate counts available for the densest FPGA devices. On chip scan path test latches. Fully pin for pin compatible. Package exibility available.

XC44xx/E/EX/XL and XC54XX Summary

Features
Designed for conversion of XC4xxxE, EX, XL and XC5xxx FPGAs. Only used CLBs are mapped. Multiple mask, state-of-the-art, gate array process. On-chip scan path test latches. Fully pin-for-pin compatible. Smallest possible die size. All Xilinx FPGA features supported, including CE, JTAG and Select-RAM. Smallest possible die size used to achieve the lowest possible cost. Technology feature size matched to performance requirements. No customer developed test vectors needed. Greater than 95% fault coverage (design dependent). Drop in replacement for Xilinx FPGAs.

Benets

Benets
All Xilinx FPGA features supported, including CE, JTAG and Select-RAM. Patented, turnkey conversion ow. Pads and package required determine device used. No customer developed test vectors needed. Greater than 95% fault coverage (design dependent). Drop in replacement for Xilinx FPGAs. Conversions to smaller packages available.

XH3 Product Description

The third generation HardWire FpgASIC product family, known as XH3, was developed to match the density, performance and features of the fastest, most fully featured Xilinx XC4xxxEX, XL and XC5xxx family of FPGAs. Initial XH3 products are based on 0.5, 5-volt process technology, followed by 0.35, 3.3-volt XH3L technology. XH3 technology was developed specically for Xilinx FPGA conversions. It uses a dense sea-of-gates CMOS gate array technology. At 0.5 and 0.35, the process geometry is small enough that die sizes are driven by pad count and not gate count. Important features used in Xilinx FPGAs such as Conguration Emulation, JTAG, and Select-RAM are easily implemented in XH3 technology. The control logic for Conguration Emulation, Power on Reset (POR), Oscillators and full JTAG are built into the XH3 base array. These features can usually be implemented with no additional silicon overhead. RAM blocks are incorporated with maxi-

HardWire Summary
Xilinx Hardwire ASIC products are FPGA specic ASICs (FpgASICs). They are a family of devices ranging from 1.0 single mask mapped ASICs to state-of-the-art sea-ofgates 0.5 and 0.35 multi-mask ASIC devices. The HardWire ow is the most simple method of cost reduction for FPGA based systems. They are developed using the FPGAs design les. This guarantees the HardWire FpgASIC will be functionally equivalent to the FPGA. No customer generated test vectors are required with HardWire. Each HardWire device is tested using a combination of industry standard and Xilinx patented test methods in a full scan methodology. The full scan test methodology provides greater than 95% fault coverage depending on the design. HardWire prototypes can be developed in half the time of traditional gate array prototypes. HardWire process technologies, conversion methods and testing procedures provide the most cost - effective alternative to traditional gate arrays.

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High-Reliability and QML Military Products

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

High-Reliability and QML Military Products Table of Contents

High-Reliability and QML Military Products

QML Certification Part of Overall Quality Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unmatched Hi-Rel Product Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Committed to the Hi-Rel Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Die Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Hi-Rel Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-1 8-1 8-1

XC4000X Series High-Reliability Field Programmable Gate Arrays

XC4000X Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Low-Voltage Versions Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

XC4000E High-Reliability Field Programmable Gate Arrays

XC4000E High-Reliability Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx High-Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Horizontal Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . XC4000E Wide Decoder Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . XC4000E CLB Level-Sensitive RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) . . . . . . . . . . . . . . . . XC4000E IOB Input Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4005E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4010E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4013E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4025E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for SMD Part: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for Military Temperature Only Part: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8-11 8-12 8-12 8-12 8-13 8-13 8-14 8-15 8-16 8-19 8-19 8-20 8-21 8-22 8-23 8-25 8-27 8-27 8-28 8-29 8-30 8-33 8-33 8-33

High-Reliability and QML Military Products

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March 16, 1998 (version 1.2)

Xilinx is the worlds leading supplier of High-Reliability Programmable Logic Devices (Hi-REL PLDs) to the aerospace, military, defense electronics, and related markets. These devices are being used in a wide variety of programs, including applications such as electronic warfare, missile guidance and targeting, RADAR/SONAR, communications, signal processing, aerospace and avionics.

Committed to the Hi-Rel Market

Xilinx understands that you need to be able to count on your Hi-Rel supplier. Xilinx is committed to our customers and the Hi-Rel market for the long-term, and we are continually expanding our Hi-Rel support and product portfolio. The unique capabilities of the Xilinx FPGA solution provide increased design exibility, eld-upgradability and system feature integration, while eliminating the NREs, lead-time and inventory problems of custom logic and gate arrays. Now more than ever, Xilinx is your Hi-Rel logic solution.

QML Certication Part of Overall Quality Platform

Being certied to MIL-PRF-38535 QML (Qualied Manufacturer List), complemented by ISO-9000 Certication, results in an overall product quality platform that truly makes Xilinx a world-class supplier of programmable logic. Designers can condently design with Xilinx for Hi-Rel systems knowing there is unsurpassed quality and reliability, and long-term commitment to the Hi-Rel market.

Die Products
Xilinx also provides select products in die form. Working with our partner, Chip Supply of Orlando, Florida, many Xilinx products are available in die form, providing all the advantages of Xilinx FPGAs to designers of hybrids and multi-chip modules. For more information about Xilinx die products, contact the nearest Xilinx Sales ofce or Sales Representative, or Chip Supply direct at (407)298-7100.

Unmatched Hi-Rel Product Offering

Xilinx offers a wide variety of devices, delivering the fastest and biggest Hi-Rel devices available. Products up to 62,000 gates are available today, with even higher densities to come. Xilinx offers multiple product families to allow you to select the right device to meet your design requirements. This broad range of devices is available in a wide variety of speed and package options. Both military temperature and full MIL-PRF-38535 QML/SMD versions are available as standard, off-the-shelf products, in through-hole and surface mount packages. Table 1: High Density and High Performance Products Family XC4000/E/XL Devices XC4003A XC4005/E XC4010/E XC4013/E XC4025E XC4036XL XC4062XL XC3142A XC3190A XC3195A

Xilinx Hi-Rel Products

Table 1 summarizes Xilinx high density and high performance product offerings. The following pages contain a complete listing of current Xilinx QML/SMD (Standard Microcircuit Drawings) devices and B grade equivalents. Architectural descriptions for these FPGA products can be found in Chapter 4. For additional information, contact the nearest Xilinx Sales Ofce or Sales Representative.

XC3100A

Features Highest Density/Most Features Family 3,000-25,000+ gates Up to 256 user-denable I/Os Extensive system features include on-chip user RAM, built-in 1149.1 test support and fast carry logic Most Advanced Family 62,000 + gates, 3.3 V, 5V-compatible I/O Highest Performance Family 2,500-7,500 gates Up to 144 user-denable I/Os

March 16, 1998 (version 1.2)

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High-Reliability and QML Military Products

Table 2: Xilinx SMD (Standard Microcircuit Drawing) XC1700 Products SMD Number 5962-9471701MPA 5962-9561701MPA XC2000 Products* SMD Number 5962-8863803XC 5962-8863804XC 5962-8863805XC XC3000 Products SMD Number 5962-8994801MXC 5962-8994802MXC 5962-8994803MXC 5962-8994801MNC 5962-8994802MNC 5962-8994803MNC 5962-8994801MMC 5962-8994802MMC 5962-8994803MMC 5962-8994801MYA* 5962-8994802MYA* 5962-8994803MYA* 5962-8994801MTA* 5962-8994802MTA* 5962-8994803MTA*

Equivalent B Grade P/N XC1765DDD8B XC17256DDD8B

Speed

Package DD8 DD8

Mark Loc TOP TOP

Equivalent B Grade P/N XC2018-50PG84B XC2018-70PG84B XC2018-100PG84B

Speed -50 -70 -100

Package PG84 PG84 PG84

Mark Loc TOP TOP TOP

* Do Not Use for New Designs. (Products being obsoleted).

Equivalent B Grade P/N XC3020-50PG84B XC3020-70PG84B XC3020-100PG84B XC3020-50CB100B XC3020-70CB100B XC3020-100CB100B XC3020-50CB100B XC3020-70CB100B XC3020-100CB100B XC3020-50CQ100B XC3020-70CQ100B XC3020-100CQ100B XC3020-50CQ100B XC3020-70CQ100B XC3020-100CQ100B

Speed -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100

Package PG84 PG84 PG84 CB100 CB100 CB100 CB100 CB100 CB100 CQ100 CQ100 CQ100 CQ100 CQ100 CQ100

Mark Loc TOP TOP TOP BASE BASE BASE LID LID LID BASE BASE BASE LID LID LID

* Do Not Use for New Designs (package is obsolete). Use CB Package Instead.

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March 16, 1998 (version 1.2)

XC3000 Products (continued) SMD Number Equivalent B Grade P/N 5962-8971301MXC XC3042-50PG84B 5962-8971302MXC XC3042-70PG84B 5962-8971303MXC XC3042-100PG84B 5962-8971301MZC XC3042-50PG132B 5962-8971302MZC XC3042-70PG132B 5962-8971303MZC XC3042-100PG132B 5962-8971301M9C XC3042-50CB100B 5962-8971302M9C XC3042-70CB100B 5962-8971303M9C XC3042-100CB100B 5962-8971301MMC XC3042-50CB100B 5962-8971302MMC XC3042-70CB100B 5962-8971303MMC XC3042-100CB100B 5962-8971301MYA* XC3042-50CQ100B 5962-8971302MYA* XC3042-70CQ100B 5962-8971303MYA* XC3042-100CQ100B 5962-8971301MNA* XC3042-50CQ100B 5962-8971302MNA* XC3042-70CQ100B 5962-8971303MNA* XC3042-100CQ100B

Speed -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100

Package PG84 PG84 PG84 PG132 PG132 PG132 CB100 CB100 CB100 CB100 CB100 CB100 CQ100 CQ100 CQ100 CQ100 CQ100 CQ100

Mark Loc TOP TOP TOP TOP TOP TOP BASE BASE BASE LID LID LID BASE BASE BASE LID LID LID

* Do Not Use for New Designs (package is obsolete). Use CB Package Instead.

SMD Number 5962-8982301MXC 5962-8982302MXC 5962-8982303MXC 5962-8982301MZC 5962-8982302MZC 5962-8982303MZC 5962-8982301MTC 5962-8982302MTC 5962-8982303MTC 5962-8982301MYA* 5962-8982302MYA* 5962-8982303MYA* 5962-8982301MUA* 5962-8982302MUA* 5962-8982303MUA*

Equivalent B Grade P/N XC3090-50PG175B XC3090-70PG175B XC3090-100PG175B XC3090-50CB164B XC3090-70CB164B XC3090-100CB164B XC3090-50CB164B XC3090-70CB164B XC3090-100CB164B XC3090-50CQ164B XC3090-70CQ164B XC3090-100CQ164B XC3090-50CQ164B XC3090-70CQ164B XC3090-100CQ164B

Speed -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100

Package PG175 PG175 PG175 CB164 CB164 CB164 CB164 CB164 CB164 CQ164 CQ164 CQ164 CQ164 CQ164 CQ164

Mark Loc TOP TOP TOP BASE BASE BASE LID LID LID BASE BASE BASE LID LID LID

* Package OBSOLETE. Use CB Package Instead.

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High-Reliability and QML Military Products

XC3100A Products SMD Number 5962-9561001MXC 5962-9561002MXC 5962-9561001MUC 5962-9561002MUC 5962-9561001MYC 5962-9561002MYC 5962-9561001MZC 5962-9561002MZC 5962-9561101MXC 5962-9561102MXC 5962-9561101MYC 5962-9561102MYC 5962-9561101MZC 5962-9561102MZC 5962-9561201MXC 5962-9561202MXC 5962-9561201MYC 5962-9561202MYC 5962-9561201MZC 5962-9561202MZC XC4000 Products SMD Number 5962-9471201MXC 5962-9471202MXC 5962-9471201MYC 5962-9471202MYC 5962-9471201MZC 5962-9471202MZC 5962-9225201MXC 5962-9225202MXC 5962-9225203MXC 5962-9225201MYC 5962-9225202MYC 5962-9225203MYC 5962-9225201MZC 5962-9225202MZC 5962-9225203MZC

Equivalent B Grade P/N XC3142A-5PG84B XC3142A-4PG84B XC3142A-5PG132B XC3142A-4PG132B XC3142A-5CB100B XC3142A-4CB100B XC3142A-5CB100B XC3142A-4CB100B XC3190A-5PG175B XC3190A-4PG175B XC3190A-5CB164B XC3190A-4CB164B XC3190A-5CB164B XC3190A-4CB164B XC3195A-5PG175B XC3195A-4PG175B XC3195A-5CB164B XC3195A-4CB164B XC3195A-5CB164B XC3195A-4CB164B

Speed -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5 -4

Package PG84 PG84 PG132 PG132 CB100 CB100 CB100 CB100 PG175 PG175 CB164 CB164 CB164 CB164 PG175 PG175 CB164 CB164 CB164 CB164

Mark Loc TOP TOP TOP TOP BASE BASE LID LID TOP TOP BASE BASE LID LID TOP TOP BASE BASE LID LID

Equivalent B Grade P/N XC4003A-10PG120B XC4003A-6PG120B XC4003A-10CB100B XC4003A-6CB100B XC4003A-10CB100B XC4003A-6CB100B XC4005-10PG156B XC4005-6PG156B XC4005-5PG156B XC4005-10CB164B XC4005-6CB164B XC4005-5CB164B XC4005-10CB164B XC4005-6CB164B XC4005-5CB164B

Speed -10 -6 -10 -6 -10 -6 -10 -6 -5 -10 -6 -5 -10 -6 -5

Package PG120 PG120 CB100 CB100 CB100 CB100 PG156 PG156 PG156 CB164 CB164 CB164 CB164 CB164 CB164

Mark Loc TOP TOP BASE BASE LID LID TOP TOP TOP LID LID LID BASE BASE BASE

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March 16, 1998 (version 1.2)

XC4000 Products (continued) SMD Number Equivalent B Grade P/N 5962-9752201QXC XC4005E-4PG156B 5962-9752201QYC XC4005E-4CB164B 5962-9752201QZC XC4005E-4CB164B 5962-9230501MXC XC4010-10PG191B 5962-9230502MXC XC4010-6PG191B 5962-9230503MXC XC4010-5PG191B 5962-9230501MYC XC4010-10CB196B 5962-9230502MYC XC4010-6CB196B 5962-9230503MYC XC4010-5CB196B 5962-9230501MZC XC4010-10CB196B 5962-9230502MZC XC4010-6CB196B 5962-9230503MZC XC4010-5CB196B 5962-9752301QXC XC4010E-4PG191B 5962-9752301QYC XC4010E-4CB196B 5962-9752301QZC XC4010E-4CB196B 5962-9473001MXC XC4013-10PG223B 5962-9473002MXC XC4013-6PG223B 5962-9473001MYC XC4013-10CB228B 5962-9473002MYC XC4013-6CB228B 5962-9473001MZC XC4013-10CB228B 5962-9473002MZC XC4013-6CB228B 5962-9752401QXC XC4013E-4PG223B 5962-9752401QYC XC4013E-4CB228B 5962-9752401QZC XC4013E-4CB228B 5962-9752501QXC XC4025E-4PG299B 5962-9752501QYC XC4025E-4CB228B 5962-9752501QZC XC4025E-4CB228B Table 3: Revision History Version 1/98, doc version 1.1

Speed -4 -4 -4 -10 -6 -5 -10 -6 -5 -10 -6 -5 -4 -4 -4 -10 -6 -10 -6 -10 -6 -4 -4 -4 -4 -4 -4

Package PG156 CB164 CB164 PG191 PG191 PG191 CB196 CB196 CB196 CB196 CB196 CB196 PG191 CB196 CB196 PG223 PG223 CB228 CB228 CB228 CB228 PG223 CB228 CB228 PG299 CB228 CB228

Mark Loc TOP BASE LID TOP TOP TOP BASE BASE BASE LID LID LID TOP BASE LID TOP TOP BASE BASE LID LID TOP BASE LID TOP BASE LID

Description High-Reliability and QML Military Products, correct erroneous information page 2 XC3000 Products, delete last page, table - Mil-PRF-3853 QML, Xilinx M Grade and Plastic Commercial Flows

March 16, 1998 (version 1.2)

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High-Reliability and QML Military Products

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XC4000X Series High-Reliability Field Programmable Gate Arrays

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Advance Product Specification

XC4000X Series Features

Available in military temperature range (-55 C to
o o

Low-Voltage Versions Available

Low-Voltage Devices Function at 3.0 - 3.6 Volts XC4000XL: High Performance Low-Voltage Versions of XC4000EX devices 5V tolerant I/Os on XC4000XL 0.35 SRAM process for XC4000XL

125 C, TC) XC4036XL and XC4062XL available in -3 speed XC4028EX available in -4 speed System featured Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Abundant ip-ops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks System Performance beyond 50 MHz Flexible Array Architecture Low Power Segmented Routing Architecture Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12-mA Sink Current Per XC4000X Output Congured by Loading Binary File - Unlimited reprogrammability Readback Capability - Program verication - Internal node observability Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization Highest Capacity Over 130,000 Usable Gates Additional Routing Over XC4000E - almost twice the routing capacity for high-density designs Buffered Interconnect for Maximum Speed New Latch Capability in Congurable Logic Blocks Improved VersaRingTM I/O Interconnect for Better Fixed Pinout Flexibility - Virtually unlimited number of clock signals Optional Multiplexer or 2-input Function Generator on Device Outputs

Introduction
XC4000X Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benets of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs. Refer to the complete Commercial XC4000E and XC4000X Series Field Programmable Gate Arrays Data Sheet for more information on device architecture and timing.

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XC4000X Series High-Reliability Field Programmable Gate Arrays

Table 1: XC4000X Series High Reliability Field Programmable Gate Arrays Max Logic Max. RAM Typical Gates Bits Gate Range (No RAM) (No Logic) (Logic and RAM)* 28,000 32,768 18,000 - 50,000 36,000 41,472 22,000 - 65,000 62,000 73,728 40,000 - 130,000 Number Total of Max. CLBs Flip-Flops User I/O Packages 1,024 2,560 256 PG299, CB228 1,296 3,168 288 PG411, CB228 2,304 5,376 384 PG475, CB228

Logic Device Cells XC4028EX 2432 XC4036XL 3078 XC4062XL 5472

8/15/97

CLB Matrix 32 x 32 36 x 36 48 x 48

* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

Ordering Information Example: XC4062XL-3PG475M

Device Type Speed Grade -4 -3 Number of Pins Temperature Range M = Military (TC = -55 to +125 oC)

Package Type CB = Top Brazed Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array

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XC4000E High-Reliability Series Table of Contents

1 8*

XC4000E High-Reliability Field Programmable Gate Arrays

XC4000E High-Reliability Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx High-Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Horizontal Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . XC4000E Wide Decoder Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . XC4000E CLB Level-Sensitive RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) . . . . . . . . . . . . . . . . XC4000E IOB Input Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4005E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional XC4005E Package Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4010E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional XC4010E Package Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4013E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4025E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for SMD Part: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for Military Tempeture Only Part: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8-11 8-12 8-12 8-12 8-13 8-13 8-14 8-15 8-16 8-19 8-19 8-20 8-21 8-22 8-23 8-25 8-27 8-27 8-27 8-28 8-29 8-29 8-30 8-33 8-33 8-33

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Product Specification - Program verication - Internal node observability Backward Compatible with XC4000 Devices Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization Available in class Q fully compliant QML and Military temperature range only - Certied to MIL-PRF-38535, appendix A QML (Qualied Manufacturers Listing)

XC4000E High-Reliability Features

System featured Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Abundant ip-ops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks System Performance beyond 60 MHz Flexible Array Architecture Low Power Segmented Routing Architecture Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12-mA sink current per XC4000E output Congured by Loading Binary File - Unlimited reprogrammability Readback Capability

Xilinx High-Reliability
XC4000E family is supplied under the following standard microcircuit drawings (SMDs): XC4005E 5962-97522 XC4010E 5962-97523 XC4013E 5962-97524 XC4025E 5962-97525 For more information contact DSCC (Defense Supply Center Columbus) Columbus, Ohio.

Table 1: XC4000E Field Programmable Gate Arrays Max. Typical Logic Max. RAM Gate Range Gates Bits (Logic and (No RAM) (No Logic) RAM)* 5,000 6,272 3,000 - 9,000 10,000 13,000 25,000 12,800 18,432 32,768 Number of Flip-Flops 616 1,120 1,536 2,560 Max. Decode Inputs per side 42 60 72 96

Device XC4005E XC4010E XC4013E XC4025E

CLB Matrix 14 x 14

Total CLBs 196 400 576 1,024

Max. User I/O 112 160 192 256

7,000 - 20,000 20 x 20 10,000 30,000 15,000 45,000 24 x 24 32 x 32

Packages PG156, CB164 PG191, CB196 PG223, CB228 PG299, CB228

* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

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XC4000E High-Reliability Field Programmable Gate Arrays

XC4000E Switching Characteristics

XC4000E Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TSOL TJ
Note 1:

Description Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic packages

Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +150

Units V V V C C C

Note 2:

Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

XC4000E Recommended Operating Conditions

Symbol VCC VIH VIL TIN
Note:

Description Supply voltage relative to GND, TC = -55C to +125C High-level input voltage Low-level input voltage Input signal transition time

TTL inputs TTL inputs

Min 4.5 2.0 0

Max 5.5 VCC 0.8 250

Units V V V ns

At case temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35% per C. Input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS. All specications are subject to change without notice.

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XC4000E DC Characteristics Over Operating Conditions

Symbol VOH VOL ICCO IL CIN IRIN* IRLL*
Note 1: Note 2: *

Description High-level output voltage @ IOH = -4.0mA, VCC min TTL outputs Low-level output voltage @ IOL = 12.0mA, VCC min (Note 1) TTL outputs Quiescent FPGA supply current (Note 2) Input or output leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low

Min 2.4

Max 0.4 50 +10 16 -0.25 2.5

-10 -0.02 0.2

Units V V mA A pF mA mA

With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA congured with the development system Tie option. Characterized Only.

XC4000E Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature) Speed Grade Device XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E -4 Max 7.0 11.0 11.5 12.5 7.5 11.5 12.0 13.0 Units ns ns ns ns ns ns ns ns

Description From pad through Primary buffer, to any clock K From pad through Secondary buffer, to any clock K

Symbol TPG

TSG

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XC4000E Horizontal Longline Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. The following guidelines reect worst-case values over the recommended operating conditions. Speed Grade Device
XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E

Description
TBUF driving a Horizontal Longline (LL):

Symbol TIO1

-4 Max
5.0 8.0 9.0 11.0 6.0 10.5 11.0 12.0 7.0 8.5 8.7 11.0 1.8 3.0 3.5 4.0 23.0 29.0 32.0 42.0 10.0 13.5 15.0 18.0

Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

I going High or Low to LL going High or Low, while T is Low. Buffer is constantly active. (Note1) I going Low to LL going from resistive pull-up High to active Low. TBUF configured as open-drain. (Note1) T going Low to LL going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. (Note1) T going High to TBUF going inactive, not driving LL

TIO2

TON

TOFF

T going High to LL going from Low to High, pulled up by a single resistor. (Note 1) T going High to LL going from Low to High, pulled up by two resistors. (Note1)

TPUS

TPUF

Note 1:

These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.

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XC4000E Wide Decoder Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. The following guidelines reect worst-case values over the recommended operating conditions. Speed Grade Device XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E -4 Max 9.5 15.0 16.0 18.0 12.5 18.0 19.0 21.0 10.5 16.0 17.0 19.0 12.5 18.0 19.0 21.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Description Full length, both pull-ups, inputs from IOB I-pins

Symbol TWAF

Full length, both pull-ups, inputs from internal logic

TWAFL

Half length, one pull-up, inputs from IOB I-pins

TWAO

Half length, one pull-up, inputs from internal logic

TWAOL

Notes: These delays are specied from the decoder input to the decoder output. Fewer than the specied number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.

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XC4000E CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Symbol TILO TIHO THH1O TOPCY TASCY TINCY TSUM TBYP TCKO TICK TIHCK THH1CK THH2CK TDICK TECCK TRCK 4.0 6.1 5.0 4.8 3.0 4.0 4.2 -4 Min Max 3.9 5.9 4.9 4.4 6.8 2.9 5.0 1.0 5.0 Units

Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs C inputs via H to X/Y outputs CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Sequential Delays Clock K to outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive)

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

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XC4000E CLB Switching Characteristic Guidelines (continued)

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the static timing analyzer and used in the simulator. The following guidelines reect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade Device -4 Min 0 0 0 0 0 0 4.5 4.5 5.5 6.5 4005E 4010E 4013E 4025E 4005E 4010E 4013E 4025E 13.0 55.0 70.0 112.0 23.0 60.0 77.0 134.0 Max Units

Description Hold Time after Clock K F/G inputs F/G inputs via H C inputs via H1 through H C inputs via DIN C inputs via EC C inputs via SR, going Low (inactive) Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Master Set/Reset Width (High or Low)

Symbol TCKI TCKIH TCKHH1 TCKDI TCKEC TCKR TCH TCL TRPW TRIO TMRW

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Delay from Global Set/Reset net to Q

TMRQ

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XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted.

Single Port RAM

Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K
Notes:

Speed Grade Size Symbol Min

-4 Units Max

16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1

TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS

15.0 15.0 7.5 7.5 2.8 2.8 0 0 3.5 2.5 0 0 2.2 2.2 0 0 10.3 11.6 1 ms 1 ms

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Applicable Read timing specications are identical to Level-Sensitive Read timing.

Dual-Port RAM
Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K
Note:

Speed Grade Size Symbol Min

-4 Units Max

16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1

TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS

15.0 7.5 2.8 0 2.2 0 2.2 0.3

1 ms

10.0

ns ns ns ns ns ns ns ns ns

Applicable Read timing specications are identical to Level-Sensitive Read timing.

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XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing

TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

TILO

TWOS OLD

DATA OUT

NEW
X6461

XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing

TWPDS WCLK (K) TWSDS WE TDSDS DATA IN TASDS ADDRESS TILO TWODS DATA OUT OLD NEW
X6474

TWHDS

TDHDS

TAHDS

TILO

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XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Description Write Operation Address write cycle time Write Enable pulse width (High) Address setup time before WE Address hold time after end of WE DIN setup time before end of WE DIN hold time after end of WE Read Operation Address read cycle time Data valid after address change (no Write Enable) Read Operation, Clocking Data into Flip-Flop Address setup time before clock K Read During Write Data valid after WE goes active (DIN stable before WE) Data valid after DIN (DIN changes during WE) Read During Write, Clocking Data into Flip-Flop WE setup time before clock K Data setup time before clock K 16x2 32x1 16x2 32x1 TWCK TWCKT TDCK TDCKT 8.0 9.6 7.0 8.0 ns ns ns ns 16x2 32x1 16x2 32x1 TWO TWOT TDO TDOT 10.0 12.0 9.0 11.0 ns ns ns ns 16x2 32x1 TICK TIHCK 4.0 6.1 ns ns 16x2 32x1 16x2 32x1 TRC TRCT TILO TIHO 4.5 6.5 3.9 5.9 ns ns ns ns 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWC TWCT TWP TWPT TAS TAST TAH TAHT TDS TDST TDH TDHT 8.0 8.0 4.0 4.0 2.0 2.0 2.5 2.0 4.0 5.0 2.0 2.0 ns ns ns ns ns ns ns ns ns ns ns ns Size Symbol Min -4 Units Max

Note:

Timing for the 16x1 RAM option is identical to 16x2 RAM timing.

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XC4000E CLB Level-Sensitive RAM Timing Characteristics

T WC ADDRESS

WRITE
TAS WRITE ENABLE T DS T DH T WP T AH

DATA IN

REQUIRED

READ WITHOUT WRITE

T ILO

X,Y OUTPUTS

VALID

VALID

READ, CLOCKING DATA INTO FLIP-FLOP

T ICK CLOCK T CH

T CKO XQ, YQ OUTPUTS VALID (OLD) VALID (NEW)

READ DURING WRITE

WRITE ENABLE

T WP

T DH DATA IN (stable during WE) T WO X, Y OUTPUTS VALID VALID

DATA IN (changing during WE)

OLD T WO T DO VALID (OLD)

NEW

X, Y OUTPUTS

VALID (PREVIOUS)

VALID (NEW)

READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP

T WP WRITE ENABLE T WCK T DCK DATA IN

CLOCK T CKO

XQ, YQ OUTPUTS
X2640

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XC4000E High-Reliability Field Programmable Gate Arrays

XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted. Speed Grade Device
XC4005E XC4010E XC4013E XC4025E

-4
14.0 16.0 16.5 17.0

Description Global Clock to Output (fast) using OFF

TPG Global Clock-to-Output Delay OFF

Symbol TICKOF

Units
ns ns ns ns

. . . . .
X3202

(Max)

Global Clock to Output (slew-limited) using OFF

TPG Global Clock-to-Output Delay OFF

TICKO

. . . . .
X3202

(Max)

XC4005E XC4010E XC4013E XC4025E

18.0 20.0 20.5 21.0

ns ns ns ns

Input Setup Time, using IFF (no delay)

D Input Set - Up & Hold Time IFF TPG

TPSUF

(Min)

XC4005E XC4010E XC4013E XC4025E

2.0 1.9 1.6 1.5

ns ns ns ns

X3201

Input Hold Time, using IFF (no delay)

D Input Set - Up & Hold Time IFF TPG

TPHF

(Min)

XC4005E XC4010E XC4013E XC4025E

4.6 6.0 7.0 8.0

ns ns ns ns

X3201

Input Setup Time, using IFF (with delay)

D Input Set - Up & Hold Time IFF TPG

TPSU

(Min)

XC4005E XC4010E XC4013E XC4025E

8.5 8.5 8.5 9.5

X3201

ns ns ns ns ns ns ns ns ns ns ns ns

Input Hold Time, using IFF (with delay)

D Input Set - Up & Hold Time IFF TPG

TPH

(Min)

XC4005E XC4010E XC4013E XC4025E

0 0 0 0

X3201

OFF = Output Flip-Flop

IFF = Input Flip-Flop or Latch

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November 21, 1997 (Version 1.3)

XC4000E IOB Input Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted. Speed Grade Device All devices All devices XC4005E XC4010E XC4013E XC4025E All devices All devices All devices All devices 0 0 -4 Min Max 3.0 6.0 12.0 12.2 12.6 15.0 6.8 7.3 Units

Description
Propagation Delays (TTL Inputs)

Symbol TPID TPLI TPDLI

Pad to I1, I2 Pad to I1, I2 via transparent latch, no delay with delay

ns ns ns ns ns ns ns ns ns ns

Propagation Delays

Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low)
Hold Times (Note 1)

TIKRI TIKLI TIKPI TIKPID

Pad to Clock (IK), no delay with delay

Note 1: Note 2:

Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pullup (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.

November 21, 1997 (Version 1.3)

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XC4000E High-Reliability Field Programmable Gate Arrays

XC4000E IOB Input Switching Characteristic Guidelines (continued)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Device All devices XC4005E XC4010E XC4013E XC4025E -4 Min 4.0 10.9 11.3 11.8 14.0 Max Units

Description Setup Times (TTL Inputs) Pad to Clock (IK), no delay with delay

Symbol TPICK TPICKD

ns ns ns ns ns ns ns ns ns

(TTL or CMOS) Clock Enable (EC) to Clock (IK), no delay with delay

TECIK TECIKD

All devices XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E

3.5 10.4 10.7 11.1 14.0 12.0 21.0 23.0 29.0 13.0 55.0 70.0 112.0 15.0 20.3 22.0 28.0

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Global Set/Reset (Note 3) Delay from GSR net through Q to I1, I2 GSR width GSR inactive to first active Clock (IK) edge

TRRI

TMRW

TRPO

Note 1: Note 2: Note 3:

Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pullup (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source. Timing is based on the XC4005E. For other devices see the static timing analyzer.

8-24

November 21, 1997 (Version 1.3)

XC4000E IOB Output Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Symbol TOKPOF TOKPOS TOPF TOPS TTSHZ -4 Min Max 7.5 11.5 8.0 12.0 10.0 Units

Description Propagation Delays (TTL Output Levels) Clock (OK) to Pad, fast slew-rate limited Output (O) to Pad, fast slew-rate limited 3-state to Pad hi-Z (slew-rate independent) 3-state to Pad active and valid, fast slew-rate limited
Note 1:

ns ns ns ns ns

TTSONF TTSONS

10.0 13.7

ns ns

Note 2:

Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pullup (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.

November 21, 1997 (Version 1.3)

8-25

XC4000E High-Reliability Field Programmable Gate Arrays

XC4000E IOB Output Switching Characteristic Guidelines (continued)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XC4000E devices unless otherwise noted. Speed Grade Device -4 Min 5.0 0 4.5 4.5 Max Units

Description Setup and Hold Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Clock High Clock Low
Note 1:

Symbol TOOK TOKO TCH TCL

ns ns ns ns

Note 2: Note 3:

Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pullup (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source. Timing is based on the XC4005E. For other devices see the static timing analyzer.

8-26

November 21, 1997 (Version 1.3)

XC4000E High-Reliability Field Programmable Gate Arrays

November 21, 1997 (Version 1.3)

Device-Specic Pinout Tables

Pin Locations for XC4005E Devices
XC4005E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 PG 156 H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 E3 C1 C2 D3 B1 B2 C3 C4 B3 A1 A2 C5 B4 A3 C6 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 C11 B12 A13 A14 C12 B13 B14 A15 C13 A16 C14 B15 B16 CB 164 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P157 P158 P160 P161 P162 P163 P164 P1 P2 P3 P4 P5 P7 P8 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P26 P27 P28 P29 P30 P32 P33 P34 P35 P37 P38 P39 P40 P41 P42 P43 P44 Bndry Scan 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 174 175 XC4005E Pad Name I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O PG 156 D14 C15 D15 E14 C16 F14 F15 E16 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 M16 L15 L14 P16 M14 N15 P15 N14 R16 P14 R15 P13 R14 T16 T15 R13 P12 T14 T13 P11 R11 T11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 CB 164 P45 P46 P48 P49 P50 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P89 P90 P91 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 Bndry Scan 178 181 184 187 190 193 196 199 202 205 208 211 214 217 220 223 226 229 232 235 238 241 244 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 XC4005E Pad Name I/O (D2) I/O I/O I/O GND I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND 8/13/97 PG 156 P7 T5 R6 T4 P6 T3 P5 R4 R3 P4 T2 R2 P3 T1 N3 R1 P2 N2 M3 P1 N1 L3 L2 L1 K3 K2 K1 J1 J2 J3 H2 CB 164 P109 P110 P111 P112 P113 P115 P116 P117 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P130 P131 P132 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 Bndry Scan 313 316 319 322 325 328 331 334 337 340 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 -

Additional XC4005E Package Pins

PG156 A4 D16 M15 T12 8/14/97 N.C. Pins A12 D1 E15 M1 N16 R5 D2 M2 R12 -

CB164 P6 P36 P73 P93 P133 P159 8/14/97 N.C. Pins P9 P25 P47 P51 P74 P88 P114 P118 P134 P155 P31 P52 P92 P129 P156 -

November 21, 1997 (Version 1.3)

8-27

XC4000E High-Reliability Field Programmable Gate Arrays

Pin Locations for XC4010E Devices

XC4010E Pad Name VCC I/O (A8) I/O (A9) I/O (19) I/O (18) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O PG 191 J4 J3 J2 J1 H1 H2 H3 G1 G2 F1 E1 G3 F2 D1 C1 E2 F3 D2 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 C7 A4 A5 B7 A6 C8 A7 B8 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 B11 A12 B12 A13 C12 B13 A14 A15 C13 CB 196 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 Bndry Scan 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203 206 209 212 215 218 221 XC4010E Pad Name I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O PG 191 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 G16 E18 F18 G17 G18 H16 H17 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 M18 M17 N18 P18 M16 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 CB 196 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P104 Bndry Scan 224 227 230 233 236 239 242 245 246 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 346 349 352 355 358 361 364 367 370 373 XC4010E Pad Name I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O PG 191 U15 V17 V16 T13 U14 V15 V14 T12 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 T7 V5 V4 U5 T6 V3 V2 U4 T5 U3 T4 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P2 T1 R1 N2 M3 P1 N1 M2 M1 L3 CB 196 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 Bndry Scan 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44

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November 21, 1997 (Version 1.3)

XC4010E Pad Name I/O I/O I/O I/O (A6) I/O (A7) GND 8/14/97

PG 191 L2 L1 K1 K2 K3 K4

CB 196 P167 P168 P169 P170 P171 P172

Bndry Scan 47 50 53 56 59 -

Additional XC4010E Package Pins

CB196 P5 P192 8/14/97 N.C. Pins P54 P103 P152 -

Pin Locations for XC4013E Devices

XC4013E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1(A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O PG 223 J4 J3 J2 J1 H1 H2 H3 G1 G2 H4 G4 F1 E1 G3 F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 C7 A4 A5 B7 A6 D7 D8 C8 A7 B8 CB 228 P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 P223 P224 P225 P226 P227 P228 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 Bndry Scan 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203 206 XC4013E Pad Name I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O PG 223 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 D11 D12 B11 A12 B12 A13 C12 D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 G16 E18 F18 CB 228 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 Bndry Scan 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287 290 293 294 295 298 301 304 307 310 313 316 319 322 325 328 331 334 XC4013E Pad Name I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O I/O I/O (D6) I/O I/O PG 223 G17 G18 H16 H17 G15 H15 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 L15 M15 M18 M17 N18 P18 M16 N15 P15 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 R14 R13 V17 V16 T13 CB 228 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 Bndry Scan 337 340 343 346 349 352 355 358 361 364 367 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463

November 21, 1997 (Version 1.3)

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XC4000E High-Reliability Field Programmable Gate Arrays

XC4013E Pad Name I/O I/O I/O GND I/O I/O I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O VCC PG 223 U14 V15 V14 T12 R12 R11 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 CB 228 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 Bndry Scan 466 469 472 475 478 481 484 487 490 493 496 499 502 505 508 511 514 517 520 523 526 529 532 XC4013E Pad Name I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O PG 223 V6 U6 R8 R7 T7 R6 R5 V5 V4 U5 T6 V3 V2 U4 T5 U3 T4 V1 R4 U2 R3 T3 U1 P3 R2 CB 228 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 Bndry Scan 535 538 541 544 547 550 553 556 559 562 565 568 571 574 577 580 0 2 5 8 11 XC4013E Pad Name I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND 8/14/97 PG 223 T2 N3 P4 N4 P2 T1 R1 N2 M3 P1 N1 M4 L4 M2 M1 L3 L2 L1 K1 K2 K3 K4 CB 228 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 Bndry Scan 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 -

Pin Locations for XC4025E Devices

XC4025E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O CB 228 P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 PG 299 K1 K2 K3 K5 K4 J1 J2 H1 J3 J4 J5 H2 G1 E1 H3 G2 H4 F2 F1 H5 G3 D1 G4 E2 F3 G5 C1 F4 E3 D2 Bndry Scan 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 XC4025E Pad Name I/O I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O CB 228 P223 P224 P225 P226 P227 P228 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 PG 299 C2 F5 E4 D3 C3 A2 B1 D4 B2 B3 E6 D5 C4 A3 D6 E7 B4 C5 A4 D7 C6 E8 B5 A5 B6 D8 C7 B7 A6 C8 Bndry Scan 179 182 185 188 191 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 XC4025E Pad Name I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O CB 228 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 PG 299 E9 A7 D9 B8 A8 C9 B9 E10 A9 D10 C10 A10 A11 B10 B11 C11 E11 D11 A12 B12 A13 C12 D12 E12 B13 A16 A14 C13 B14 D13 Bndry Scan 257 260 263 266 269 272 275 278 281 284 287 290 293 296 299 302 305 308 311 314 317 320 323 326 329 332 335

8-30

November 21, 1997 (Version 1.3)

XC4025E Pad Name GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O

CB 228 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92

PG 299 A15 B15 E13 C14 A17 D14 B16 C15 E14 A18 D15 C16 B17 B18 E15 D16 C17 A20 A19 C18 B20 D17 B19 C19 F16 E17 D18 C20 F17 G16 D19 E18 D20 G17 F18 H16 E19 F19 E20 H17 G18 G19 H18 VCC* J16 G20 J17 H19 H20 J18 J19 K16 J20 K17 K18 K19 L20 K20 L19 L18 L16 L17 M20 M19

Bndry Scan 338 341 344 347 350 353 356 359 362 365 368 371 374 377 380 383 386 389 390 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484 487 490 493 496 499 502

XC4025E Pad Name I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O I/O I/O I/O

CB 228 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139

PG 299 N20 M18 M17 M16 N19 P20 T20 N18 P19 N17 R19 R20 N16 P18 U20 P17 T19 R18 P16 V20 R17 T18 U19 V19 R16 T17 U18 X20 W20 V18 X19 U17 W19 W18 T15 U16 V17 X18 U15 T14 W17 V16 X17 U14 V15 T13 W16 W15 X16 U13 V14 W14 V13 X15 T12 X14 U12 W13 X13 V12 W12 T11 X12 U11

Bndry Scan 505 508 511 514 517 520 523 526 529 532 535 538 541 544 547 550 553 556 559 562 565 568 571 574 577 580 583 586 589 592 595 598 601 604 607 610 613 616 619 622 625 628 631 634 637 640 643 646 649 652 655 658 661 664 667 670

XC4025E Pad Name I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O

CB 228 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189

PG 299 V11 W11 X10 X11 W10 V10 T10 U10 X9 W9 X8 V9 U9 T9 W8 X7 X5 V8 W7 U8 W6 X6 T8 V7 X4 U7 W5 V6 T7 X3 U6 V5 W4 W3 T6 U5 V4 X1 V3 VCC* U4 GND* W2 V2 R5 T4 U3 V1 R4 P5 U2 T3 U1 P4 R3 N5 T2 R2 T1 N4 P3 P2

Bndry Scan 673 676 679 682 685 688 691 694 697 700 703 706 709 712 715 718 721 724 727 730 733 736 739 742 745 748 751 754 757 760 763 766 769 772 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56

November 21, 1997 (Version 1.3)

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XC4000E High-Reliability Field Programmable Gate Arrays

XC4025E Pad Name I/O VCC I/O I/O I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND 8/14/97 CB 228 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 PG 299 N3 R1 M5 P1 M4 N2 N1 M3 M2 L5 M1 L4 L3 L2 L1 Bndry Scan 59 62 65 68 71 74 77 80 83 86 89 92 95 -

8-32

November 21, 1997 (Version 1.3)

Ordering Information

Example for SMD Part:

Generic Standard Microcircuit Drawing (SMD) Prex Device Type XC4005E = 97522 XC4010E = 97523 XC4013E = 97524 XC4025E = 97525

5962-97523 01 Q X C
Lead Finish C = Gold Package Type X = Pin Grid Y = Quad Flatpack (Base Mark) Z = Quad Flatpack (Lid Mark) QML Certied

Speed Grade 01 = -4

Example for XC4010E Military Temperature Only

Device Type XC4005E XC4010E XC4013E XC4025E

-4 PG 191 M
Temperature Range M = Military (TC = -55o C to +125o C) Number of Pins

Speed Grade

Package Type CB = Top Brazed Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array

November 21, 1997 (Version 1.3)

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XC4000E High-Reliability Field Programmable Gate Arrays

8-34

November 21, 1997 (Version 1.3)

Programming Support

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Programming Support Table of Contents

HW-130 Programmer
HW-130 Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device and Package Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmer Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Software and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmer Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Socket Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Requirements and Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . New Programming Algorithm Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adapter Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9-1 9-1 9-1 9-1 9-1 9-1 9-1 9-2

HW-130 Programmer
0 9*

November 12, 1997 (Version 1.2)

HW-130 Programmer
Programming Socket Adapters
Supports all package styles: PLCC, PQFP, TQFP, VQFP, HQFP, BGA, SOIC, VOIC, PGA and DIP

Device and Package Support

XC1700 Serial PROMs XC9500 CPLDs Supports all Xilinx package types

Programmer Accessories
Universal power supply Power cord options for US/Asia, UK, European and Japanese standards. Serial download cable and adapters Users manual Programmer interface software Vacuum handling tool

Electrical Requirements and Physical Specications

Operating voltage: 100-250 VAC, 50-60 Hz Power consumption: 1.0 Amp Dimensions: 6 x 7.75 x 2 Weight: 1 lb. Safety standards: approved by UL, CSA, TUV

New Programming Algorithm Support

The new programmer algorithms are available via the Xilinx WEB site, and FTP site: To access programmer software from the Xilinx WEB site, go to www.xilinx.comand enter the Answer or Technical Support section. Select the le download area. Within Software Help, select Programmer. To access programmer software from the Xilinx FTP site, use an FTP client to access ftp.xilinx.com. Login as Anonymous. Enter the /pub/swhelp/programmer directory. To view all programmer related les from the Xilinx bulletin board (BBS), select File Manager and Software Help, then select Programmer Support.

Interface Software and System Requirements

The programmer software operates on a variety of different platforms. Table 1 indicates the minimum system requirements for each. In all cases, a CD-ROM drive and an RS232 serial port are required. The DOS driver software is also available on 3.5 disk. A mouse is recommended.

Programmer Functional Specications

Device programming, erasing and verication CPLD security control PROM reset polarity control Checksum calculation and comparison Blank check and signature ID tests Master device upload File transfer and comparison Self check and auto calibration

Table 1: Interface Software and System Requirements

Requirements Memory Needed Hard Disk Space System Software DOS Windows 3.1 Windows 95 Windows NT Sun OS Solaris HP9000/700 IBM RS6000 500KB 4MB 8MB 16MB 2MB 2MB 2MB 2MB 6MB 6MB 6MB 6MB 3.3 or 3.1.x. 4.00 3.1 or greater SunOS 4.1.3 or SunOS 5.3 or HP-UX A09.05 AIX 3.2.5 or greater or greater greater greater, or greater greater (Solaris 2.3 or higher)

November 12, 1997 (Version 1.2)

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HW-130 Programmer

Adapter Selection Table

Product Family XC73001/XC9500 XC73001 XC73001/XC9500 XC73001 XC73001/XC9500 XC73001/XC9500 XC73001/XC9500 XC73001 XC73001, 2 CPLD (XC73001/XC9500)2 XC73001 XC9500 XC9500 XC1700 XC1700 XC1700 Calibration Adapter 1) XC7300 devices are not recommended for new designs. 2) Xilinx manufactures two versions of the HW-133-PQ160 adapter. The correct adapter for programming XC9500 devices has CPLD written on the front label, at the top left side, under the Xilinx logo. Package Types PLCC/CLCC 44 PQFP 44 VQFP 44 PLCC/CLCC 68 PLCC/CLCC 84 PQFP 100 TQFP 100 PGA 144 PQFP 160 PQFP 160 BGA 225 HQFP 208 BGA 352 DIP 8 PLCC20/SO8/VO8 S020 Adapter P/N HW-133-PC44 HW-133-PQ44 HW-133-VQ44 HW-133-PC68 HW-133-PC84 HW-133-PQ100 HW-133-TQ100 HW-133-PG144 HW-133-PQ160 HW-133-PQ160 HW-133-BG225 HW-133-HQ208 HW-133-BG352 HW-137-DIP8 HW-137-PC20/SO8 HW-137-S020 HW-130-CAL

9-2

November 12, 1997 (Version 1.2)

Packages and Thermal Characteristics

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Packages and Thermal Characteristics Table of Contents

Packages and Thermal Characteristics

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Thermal Characterization Methods & Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Some Power Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Electrical Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Mass (Weight) by Package Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Thermally Enhanced Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Moisture Sensitivity of PSMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tape and Reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow Soldering Process Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10-3 10-3 10-9 10-10 10-12 10-13 10-14 10-16 10-18 10-20

Package Drawings
Ceramic DIP Package - DD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Plastic DIP Package - PD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOIC and TSOP Packages - SO8, VO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOIC Package - SO20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLCC Packages - PC20, PC28, PC44, PC68, PC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VQFP Packages - VQ44, VQ64, VQ100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQFP/HTQFP Packages - TQ100, TQ144, TQ176, HT100, HT144, HT176 . . . . . . . . . . . . . . . PQ/HQFP Packages - PQ100, HQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PQ/HQFP Packages - PQ44, PQ160, PQ208, PQ240, HQ160, HQ208, HQ240 . . . . . . . . . . . . PQ/HQFP Packages - PQ304, HQ304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGA Packages - BG225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGA Packages - BG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGA Packages - BG352, BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGA Packages - BG560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG68, PG84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG120, PG132, PG156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG223, PG299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG411. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG475, PG559 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic Brazed QFP Packages - CB100 (XC3000 Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic Brazed Packages - CB164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic Brazed QFP Packages - CB100, CB164, CB196 (XC4000 Version) . . . . . . . . . . . . . . Ceramic Brazed QFP Packages - CB228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31 10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 10-41 10-42 10-43 10-44 10-45 10-46

Packages and Thermal Characteristics

0 10*

November 20, 1997 (Version 2.0)

Package Information
Inches vs. Millimeters
The JEDEC standards for PLCC, CQFP, and PGA packages dene package dimensions in inches. The lead spacing is specied as 25, 50, or 100 mils (0.025", 0.050" or 0.100"). The JEDEC standards for PQFP, HQFP, TQFP, and VQFP packages dene package dimensions in millimeters. These packages have a lead spacing of 0.5 mm, 0.65 mm, or 0.8 mm. Because of the potential for measurement discrepancies, this Data Book provides measurements in the controlling standard only, either inches or millimeters. (See Table 1 for package dimensions.)

EIA Standard Board Layout of Soldered Pads for QFP Devices

M ID

IE

b2 l2 e

Table 1: Dimensions for Xilinx Quad Flat Packs1 Dim. MID MIE e b2 I2 HQ160 PQ160 9.80 9.80 20.40 28.40 9.80 9.80 14.40 28.40 0.80 0.50 0.65 0.65 0.4 - 0.6 0.3 - 0.4 0.3 - 0.5 0.3 - 0.5 1.60 1.60 1.802 1.80 VQ44 VQ64 PQ100 HQ208 PQ208 28.20 28.20 0.50 0.3 - 0.4 1.60 VQ100 TQ100 13.80 13.80 0.50 0.3 - 0.4 1.60 TQ144 TQ176 HQ240 PQ240 32.20 32.20 0.50 0.3 - 0.4 1.60 HQ304 40.20 40.20 0.50 0.3 - 0.4 1.60

19.80 23.80 19.80 23.80 0.50 0.50 0.3 - 0.4 0.3 - 0.4 1.60 1.60

Notes: 1. Dimensions in millimeters 2. For 3.2 mm footprint per MS022, JEDEC Publication 95.

November 20, 1997 (Version 2.0)

10-1

Packages and Thermal Characteristics

Suggested Board Layout of Soldered Pads for BGA

Solder Land (L) diameter Opening in Solder Mask (M) diameter Solder (Ball) Land Pitch (e) Land Width between Via and Land (D) Distance between Via and Land (D) Via Land (VL) diameter Solder Mask Opening on Via (VM) diameter Through Hole (VH), plated diameter Pad Array Matrix or External Row Periphery rows

BG225 0.89 0.65 1.5 0.3 1.06 0.65 0.4 0.3 Full 15 x 15 -

BG256 0.79 0.58 1.27 0.3 0.9 0.65 0.4 0.3 Periphery 20 x 20 4

BG352 0.79 0.58 1.27 0.3 0.9 0.65 0.4 0.3 Periphery 26 x 26 4

BG432 0.79 0.58 1.27 0.3 0.9 0.65 0.4 0.3 Periphery 31 x 31 4

BG560 0.79 0.58 1.27 0.3 0.9 0.65 0.4 0.3 Perihpery 33 x 33 5

Notes: 1. Dimensions in millimeters. 2. 6 x 4 matrix for illustration only, one land pad shown with via connection. 3. Reference J-STD-013, use dog-bone design via connection to land pad.

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Cavity Up or Cavity Down

Most Xilinx devices attach the die against the inside bottom of the package (the side that does not carry the Xilinx logo). This is called cavity-up, and has been the standard IC assembly method for over 25 years. This method does not provide the best thermal characteristics. Pin Grid Arrays (greater than 130 pins) and Ceramic Quad Flat Packs are assembled Cavity Down, with the die attached to the inside top of the package, for optimal heat transfer to the ambient air. For most packages this information does not affect how the package is used because the user has no choice in how the package is mounted on a board. For Ceramic Quad Flat Pack (CQFP) packages however, the leads can be formed to either side. Therefore, for best heat transfer to the surrounding air, CQFP packages should be mounted with the logo up, facing away from the PC board.

are chosen to handle typical designs and gate utilization requirements. For the most part the choice of a package as the primary heat removal casing works well. Occasionally designers exercise an FPGA device, particularly the high gate count variety, beyond typical designs. The use of the primary package without enhancement may not adequately address the devices heat removal needs. Heat removal management through external means or an alternative enhanced package should be considered. Removing heat ensures the functional and maximum design temperature limits are maintained. The device may go outside the temperature limits if heat build up becomes excessive. As a consequence, the device may fail to meet electrical performance specications. It is also necessary to satisfy reliability objectives by operating at a lower temperature. Failure mechanisms and the failure rate of devices depend on device operating temperature. Control of the package and the device temperature ensures product reliability.

Clockwise or Counterclockwise
The orientation of the die in the package and the orientation of the package on the PC board affect the PC board layout. PLCC and PQFP packages specify pins in a counterclockwise direction, when viewed from the top of the package (the surface with the Xilinx logo). PLCCs have pin 1 in the center of the beveled edge while all other packages have pin 1 in one corner, with one exception: The 100- and 165pin CQFPs (CB100 and CB164) for the XC3000 devices have pin 1 in the center of one edge. CQFP packages specify pins in a clockwise direction, when viewed from the top of the package. The user can make the pins run counterclockwise by forming the leads such that the logo mounts against the PC board. However, heat ow to the surrounding air is impaired if the logo is mounted down.

Package Thermal Characterization Methods & Conditions

Method and Calibration
Xilinx uses the indirect electrical method for package thermal resistance characterization. The forward-voltage drop of an isolated diode residing on a special test die is calibrated at constant forcing current of 0.520mA with respect to temperature over a correlation temperature range of 22C to 125C (degree Celsius). The calibrated device is then mounted in an appropriate environment (still air, forced convection, circulating FC-40, etc.) Depending on the package, between 0.5 to 4 watts of power (Pd) is applied. Power (Pd) is applied to the device through diffused resistors on the same thermal die. The resulting rise in junction temperature is monitored with the forward-voltage drop of the precalibrated diode. Typically, three identical samples are tested at each data point. The reproducibility error in the set-up is within 6%.

Thermal Management
Modern high speed logic devices consume an appreciable amount of electrical energy. This energy invariably turns into heat. Higher device integration drives technologies to produce smaller device geometry and interconnections. With smaller chip sizes and higher circuit densities, heat generation on a fast switching CMOS circuit can be very signicant. The heat removal needs for these modern devices must be addressed. Managing heat generation in a modern CMOS logic device is an industry-wide pursuit. However, unlike the power needs of a typical Application Specic Integrated Circuit (ASIC) gate array, the power requirements for FPGAs are not determined as the device leaves the factory. Designs vary in power needs. There is no way of anticipating the power needs of an FPGA device short of depending on compiled data from previous designs. For each device type, primary packages

Denition of Terms
TJ TA TC Junction Temperature the maximum temperature on the die, expressed in C (degree Celsius) Ambient Temperature expressed in C. The temperature of the package body taken at a dened location on the body. This is taken at the primary heat ow path on the package and represents the hottest part on the package expressed in C. The isothermal uid temperature when junction to case temperature is taken expressed in C. The total device power dissipation expressed in watts.

Tl Pd

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Junction-to-Reference General Setup

Type I, 2L/0P board, is single layer with 2 signal planes (one on each surface) and no internal Power/GND planes. The trace density on this board is less than 10% per side. Type II, the 4L/2P board, has 2 internal copper planes (one power, one ground) and 2 signal trace layers on both surfaces. Data may be taken with the package mounted in a socket or with the package mounted directly on the board. Socket measurements typically use the 2L/0P boards. SMT devices may use either board. Published data always reects the board and mount conditions used. Data is taken at the prevailing temperature and pressure conditions (22C to 25C ambient). The board with the DUT is mounted in a cylindrical enclosure. The power application and signal monitoring are the same as JC measurements. The enclosure (ambient) thermocouple is substituted for the uid thermocouple and two extra thermocouples brought in to monitor room and board temperatures. The junction to ambient thermal resistance is calculated as follows: JA = (TJ - TA)/Pd The setup described herein lends itself to the application of various airow velocities from 0 - 800 Linear Feet per Minute (LFM), i.e., 0 - 4.06 m/s. Since the board selection (copper trace density, absence or presence of ground planes, etc.) affects the results of the thermal resistance, the data from these tests shall always be qualied with the board mounting information.

Figure 1: Thermal Measurement Set-Up (Schematic for Junction to Reference)

Junction-to-Case Measurement JC
JC is measured in a 3M Flourinert (FC-40) isothermal circulating uid stabilized at 25C. The Device Under Test (DUT) is completely immersed in the uid and initial stable conditions are recorded. Pd is then applied. Case temperature (TC) is measured at the primary heat-ow path of the particular package. Junction temperature (TJ) is calculated from the diode forward-voltage drop from the initial stable condition before power was applied. JC = (TJ - TC)/Pd The junction-to-isothermal-uid measurement (JI) is also calculated from the same data. JL = (TJ - TI)/Pd The latter data is considered as the ideal JA data for the package that can be obtained with the most efcient heat removal scheme. Other schemes such as airow, heatsinks, use of copper clad board, or some combination of all these will tend towards this ideal gure. Since this is not a widely used parameter in the industry, and it is not very realistic for normal application of Xilinx packages, the JI data is not published. The thermal lab keeps such data for package comparisons.

Data Acquisition and Package Thermal Database

Xilinx gathers data for a package type in die sizes, power levels and cooling modes (air ow and sometimes heatsink effects) with a Data Acquisition and Control system (DAS). The DAS controls the power supplies and other ancillary equipment for hands-free data taking. Different setups within the DAS software are used to run calibration, JA, JC, fan tests, as well as the power effect characteristics of a package. A package is characterized with respect to the major variables that inuence the thermal resistance. The results are stored in a database. Thermal resistance data is interpolated as typical values for the individual Xilinx devices that are assembled in the characterized package. Table 2 shows the typical values for different packages. Specic device data may not be the same as the typical data. However, the data will fall within the given minimum and maximum ranges. The more widely used packages will have a wider range. Customers may contact the Xilinx application group for specic device data.

Junction-to-Ambient Measurement JA
JA is measured on FR4 based PC boards measuring 4.5 x 6.0 x .0625 (114.3mm x 152.4mm x 1.6mm) with edge connectors. There are two main board types.

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Table 2: Summary of Thermal Resistance for Packages PKG-CODE JA still air (Max) C/Watt 37 32 14 13 10 44 29 25 19 114 14 15 13 11 86 51 46 41 82 37 32 32 25 25 24 24 18 16 14 35 29 35 37 35 28 147 37 35 29 162 JA still air (Typ) C/Watt 30 29 12 11 9 41 26 24 18 109 14 14 12 11 10.9 16.0 84 46 42 33 79 34 27 28 23 23 21 20 17 15 13 12.00 34 29 33 32 32 23 147 31 32 28 162 JA still air (Min) C/Watt 24 24 10 9 8 38 25 24 17 97 14 14 12 10 76 42 38 28 73 31 25 24 21 20 18 18 16 14 12 33 28 32 22 26 19 147 31 30 27 162 JA 250 LFM (Typ) C/Watt 19 19 8 8 7 25 17 15 11 90 10 10 9 7 7.3 63 35 31 25 60 24 19 20 15 14 15 15 10 9 9 23 19 29 24 23 17 112 26 25 21 123 JA 500 LFM (Typ) C/Watt 17 17 7 6 6 19 12 11 8 73 8 8 7 5 5.7 56 31 28 21 54 18 15 17 11 11 12 12 9 8 8 18 15 28 21 21 15 105 24 21 18 116 JA 750 LFM (Typ) C/Watt 16 16 6 6 5 17 11 10 7 60 7 7 6 5 5.0 53 29 26 17 50 16 13 15 10 10 11 11 8 7 7 17 13 27 20 19 14 98 23 20 17 108 JC (Typ) C/Watt 3.3 3.2 0.8 0.8 0.8 5.1 3.6 1.8 1.3 8.2 1.0 1.7 1.5 0.9 0.9 2.0 25.8 13.7 9.3 5.3 22.2 5.8 3.6 2.8 2.6 2.6 1.5 1.5 1.9 1.2 1.2 6.0 2.5 5.5 4.6 4.3 2.8 48.3 7.5 5.3 5.3 48.3 Comments

BG225 BG256 BG352 BG432 BG560 CB100 CB164 CB196 CB228 DD8 HQ160 HQ208 HQ240 HQ304 HT144 HT176 PC20 PC44 PC68 PC84 PD8 PG84 PG120 PG132 PG156 PG175 PG191 PG223 PG299 PG411 PG475 PG559 PP132 PP175 PQ100 PQ160 PQ208 PQ240 SO8 TQ100 TQ144 TQ176 VO8

Various 4L/2P-SMT 4L/2P-SMT 4L/2P-SMT Estimated Socketed Socketed Socketed Socketed Socketed 4L/2P-SMT 4L/2P-SMT 4L/2P-SMT 4L/2P-SMT 4L/2P-SMT Estimated 2L/0P-SMT 2L/0P-SMT 2L/0P-SMT 2L/0P-SMT Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Estimated Socketed Socketed 4L/2P-SMT 2L/0P-SMT 2L/0P-SMT 2L/0P-SMT IEEE-(Ref) 4L/2P-SMT 4L/2P-SMT 4L/2P-SMT Estimated

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Table 2: Summary of Thermal Resistance for Packages (Continued) PKG-CODE JA still air (Max) C/Watt 44 44 47 JA still air (Typ) C/Watt 44 41 38 JA still air (Min) C/Watt 44 39 32 JA 250 LFM (Typ) C/Watt 36 34 32 JA 500 LFM (Typ) C/Watt 34 32 30 JA 750 LFM (Typ) C/Watt 33 31 29 JC (Typ) C/Watt 8.2 8.2 9.0 Comments

VQ44 VQ64 VQ100

4L/2P-SMT 4L/2P-SMT 4L/2P-SMT

Notes: 1. Maximum, typical and minimum numbers are based on numbers for all the devices in the specic package at the time of compilation. The numbers do not necessarily reect the absolute limits of that packages. Specic device data should lie within the limits. Packages used for a broader spectrum of devices have a wider range in the table. Specic device data in a package may be obtained from the factory. 2. Package congurations and drawings are in the package section of the data book. 3. 2L/0P - SMT: the data is from a surface mount type I board -- no internal planes on the board. 4. 4L/2P - SMT: the data is from a 4 layer SMT board incorporating 2 internal planes. Socketed data is taken in socket. 5. Air ow is given Linear Feet per Minute (LFM). 500 LFM = 2.5 Meters per Second

Application of Thermal Resistance Data

Thermal resistance data gauges the IC package thermal performance. JC measures the internal package resistance to heat conduction from the die surface, through the die mount material to the package exterior. JC strongly depends on the packages heat conductivity, architecture and geometrical considerations. JA measures the total package thermal resistance including JC. JA depends on the package material properties and such external conditions as convective efciency and board mount conditions. For example, a package mounted on a socket may have a JA value 20% higher than the same package mounted on a 4 layer board with power and ground planes. By specifying a few constraints, devices are ensured to operate within the intended temperature range. This also ensures device reliability and functionality. The system ambient temperature needs to be specied. A maximum TJ also needs to be established for the system. The following inequality will hold. TJ(max) > JA* Pd +TA The following two examples illustrates the use of this inequality.

Example 1:
The manufacturers goal is TJ (max) < 100C A module is designed for a TA = 45C max. A XC3042 in a PLCC 84 has a JA = 32C/watt. Given a XC3042 with a logic design with a rated power Pd of 0.75watt. With this information, the maximum die temperature can be calculated as: TJ = 45 + (32 x .75) ==> 69C. The system manufacturers goal of TJ < 100C is met.

Example 2:
A module has a TA = 55C max. The Xilinx XC4013E is in a PQ240 package (HQ240 is also considered). A XC4013E, in an example logic design, has a rated power of 2.50 watts. The module manufacturers goal is TJ(max.) < 100C. Table 3 shows the package and thermal enhancement combinations required to meet the goal of TJ < 100C.

Table 3: Thermal Resistance for XC4013E in PQ240 and HQ240 Packages JA still air 23.7 12.5 JA (250 LFM) 17.5 8.6 JA (500 LFM) 15.4 6.9 JA (750 LFM) 14.3 6.2 JC 2.7 1.5

Dev Name XC4013E XC4013E

Package PQ240 HQ240

Comments Cu, SMT 2L/0P 4 Layer Board data

Notes: Possible Solutions to meet the module requirements of 100C : 1a.Using the standard PQ240; TJ = 55 + (23.7 x 2.50) ==> 114.25 C. 1b.Using standard PQ240 with 250LFM forced airTJ = 55 + (17.5 x 2.50) ==> 98.75 C 2a.Using standard HQ240TJ = 55 + (12.5 x 2.50) ==> 86.25 C 2b.Using HQ240 with 250 LFM forced airTJ = 55 + (8.6 x 2.50) ==> 76.5 C

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For all solutions, the junction temperature is calculated as: TJ = Power x JA + TA. All solutions meet the module requirement of less than 100C, with the exception of the PQ240 package in still air. In general, depending on ambi-

ent and board temperatures conditions, and most importantly the total power dissipation, thermal enhancements -such as forced air cooling, heat sinking, etc. may be necessary to meet the TJ(max) conditions set.

PQ/HQ Thermal Data Comparison

HQ/PQ Thermal Data
Size effect on JA 35

30

25

JA (C/watt)

20

HQ208 HQ240

15 HQ304 10 PQ208 PQ240 5 200 300 400 500 600 700

Die size (mils)

HQ/PQ Thermal Data

Effect of Forced Air on JA 30 25
JA (C/watt)

20 15 10 5 0 0 200 400 Airflow - LFM XC4010E-HQ208 XC4010E-PQ208 XC4013E-HQ240 XC4013E-PQ240 XC4025E-HQ304 600 800

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PGA 299 Thermal Resistance

Effect of Air Flow on JA 25

20

JA (C/watt)

15

10

0 0 100 200 300 400 500 600 700 Air Flow - LFM PG191-XC4010E PG299-XC4025E PG223-XC4013E PG299-FHS(XC4025E)

PG299 Thermal Resistance

Effects of Active & Passive Heat sinks 20

15

JA (C/watt)

10

0 A B C D E F

PG299 - Various Enhancements

A Standard Pkg B Pkg+Finned HS (Passive) C Pkg+Active Fan (V=0) D Pkg+Active Fan (V=12) E Std Pkg +250LFM F Pkg+Finned HS+ 250LFM

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BGA Thermal Resistance

Effect of Air Flow on JA 40 35 30
JA (C/watt)

25 20 15 10 0 200 400 Air Flow - LFM XC4013E-BG225(4L) XC5210-BG225(2L) 600 800

XC4010E-BG225 (2L) XC73108-BG225(2L)

XC73144-BG225(4L)

Some Power Management Options

FPGA devices are usually not the dominating power consumers in a system, and do not have a big impact on power supply designs. There are obvious exceptions. When the actual or estimated power dissipation appears to be more than the specication of the chosen package, some options can be considered. Details on the engineering designs and analysis of some of these suggested considerations may be obtained from the references listed at the end of the section. The options include: A Xilinx low power (L) version of the circuit in the same package. With the product and speed grade of choice, up to a 40% power reduction can be anticipated. For more information, contact the Xilinx Hotline group. Explore thermally enhanced package options available for the same device. As illustrated above, the HQ240 package has a thermal impedance of about 50% of the equivalent PQ240. Besides, the 240 lead, the 208 lead and the 304 lead Quad packages have equivalent heatsink enhanced versions. Typically 25% to 40% improvement in thermal performance can be expected from these heatsink enhanced packages. Most of the high gate count devices above the XC4013 level come either exclusively in heat enhanced packages or have these packages as options. If the use of a standard PQ appears to be a handicap in this respect, a move to the equivalent HQ package if available may resolve the issue. The heat enhanced packages are pin to pin compatible and they use the same board layout. The use of forced air is an effective way to improve thermal performance. As seen on the graphs and the calculations above, forced air (200 -- 300 LFM) can reduce junction to ambient thermal resistance by 30%. If space will allow, the use of nned external heatsinks can be effective. If implemented with forced air as well, the benet can be a 40% to 50% reduction. The HQ304, all cavity down PGAs, and the BG352 with exposed heatsink lend themselves to the application of external heatsinks for further heat removal efciency. Outside the package itself, the board on which the package sits can have a signicant impact. Board designs may be implemented to take advantage of this. Heat ows to the outside of a board mounted package and is sunk into the board to radiate. The effect of the board will be dependent on the size and how it conducts heat. Board size, the level of copper traces on it, the number of buried copper planes all lower the junction-to-ambient thermal resistance for a package. Some of the heatsink packages with the exposed heatsink on the board side can be glued to the board with thermal compound to enhance heat removal.

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References
Forced Air Cooling Application Engineering COMAIR ROTRON 2675 Custom House Court San Ysidro, CA 92173 1-619-661-6688 Heatsink Application Engineering The following facilities provide heatsink solutions for industry standard packages. AAVID Thermal Technologies 1 Kool Path Box 400 Laconia, NH 03247-0400 1-603-528-3400 Thermalloy, Inc. 2021 W. Valley View Lane Box 810839 Dallas, TX 75381-0839 1-214-243-4321 Wakeeld Engineering, Inc. 60 Audubon Road Wakeeld MA 01880-1255 1-617-245-5900 Xilinx does not endorse these vendors nor their products. They are listed here for reference only. Any materials or services received from the vendors should be evaluated for compatibility with Xilinx components.

Package Electrical Characterization

In high-speed systems, the effects of electrical package parasitics become very critical when optimizing for system performance. Such problems as ground bounce and crosstalk can occur due to the inductance, capacitance, and resistance of package interconnects. In digital systems, such phenomena can cause logic error, delay, and reduced system speed. A solid understanding and proper usage of package characterization data during system design simulation can help prevent such problems. spikes through the IC pin and bondwire induces a voltage drop across the leads and bondwires: V = L * di/dt. The result is a momentary voltage difference between the internal IC ground and system ground, which show up as voltage spikes and unswitched outputs. Factors that affect ground bounce: rise and fall times load capacitance package inductance number of output drivers sharing the same ground path device type

Theoretical Background
There are three major electrical parameters which are used to describe the package performance: resistance, capacitance, and inductance. Also known as interconnect parasitics, they can cause many serious problems in digital systems. For example, a large resistance can cause RC & RL off-chip delays, power dissipation, and edge-rate degradation. Large capacitance can cause RC delays, crosstalk, edge-rate degradation, and signal distortion. The lead inductance, perhaps the most damaging parasitic in digital circuitry, can cause such problems as ground bounce (also known as simultaneous switching noise or delta-I noise), RL delays, crosstalk, edge rate degradation, and signal distortion. Ground bounce is the voltage difference between any two grounds (typically between an IC and circuit board ground) induced by simultaneously switching current through bondwire, lead, or other interconnect inductance. When IC outputs change state, large current spikes result from charging or discharging the load capacitance. The larger the load capacitance and faster the rise/fall times, the larger the current spikes are: I = C * dv/dt. Current

Analytical Formulas for Lead Inductance

1. Rectangular Leadframe/Trace (straight)

- + -Lself = 5 l ln -------------2l w + t 1 2

nH

(no ground)

w + t 8h - + -------------Lself = 5 l ln ------------- w + t 4h
l = lead/trace length w = lead/trace width t = lead/trace thickness h = ground height unit = inches

nH

(above ground)

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2. Bondwire (gold wire)

- -Lwire = 5 l ln ---2l r
l = wire length r = wire radius unit = inches

3 4

nH

parallel combination of leads in the return path, is the selfinductance. The parasitic effects of the return path are small enough to ignore in the context of this method. For mutual-inductance measurement, two adjacent leads are probed. A fast risetime step waveform is sent through one of the leads. The current travels through the lead/bondwire and returns by the path of the low-impedance ground. On the adjacent quiet lead, a waveform is induced due to mutual coupling. This waveform is measured as the mutual inductance. For capacitance measurements, all external leads except for the lead(s) under test are grounded to the DUT xture. For QFP, PLCC, and Power Quad-type of packages, the die-paddle and the heat slug are left oating. Self-capacitance is measured by sending a fast risetime step waveform through the lead under test. The reection waveform from the lead, which includes the sum of all capacitive coupling with respect to the lead under test, is then measured. Appropriately, the self-capacitance can also be called the bulk capacitance since the measured value includes the capacitance between the lead under test and all surrounding metal, including the ground plane and the heat slug. For mutual-capacitance measurement, two adjacent leads are probed. An incident waveform is sent through one lead, and the induced waveform on the neighboring lead is measured as the mutual capacitance. In order to de-embed the electrical parasitics of the DUT xture and the measuring probes, the short and the open compensation waveforms are also measured after each package measurement. This procedure compensates the DUT xture to the very tip of the probes.

General Measurement Procedure

Xilinx uses the Time-Domain Reectometry (TDR) method for parasitic inductance and capacitance measurements. The main components of a TDR setup includes: a digitizing sampling oscilloscope, a fast rise time step generator (<17 ps), a device-under-test (DUT) interface, and an impedance-prole analysis software to extract parasitic models from the TDR reection waveforms. In this method, a voltage step is propagated down the package under test, and the incident and reected voltage waves are monitored by the oscilloscope at a particular point on the line. The resulting characteristic impedance of the package interconnect shows the nature (resistive, inductive, and capacitive) of each discontinuity.

Package & Fixture Preparation

Before performing the measurements, the package and the DUT interface must be xtured. Proper xturing ensures accurate and repeatable measurements. The mechanical sample for all inductance (self & mutual) measurements are nished units with all leads shorted to the internal ground. For packages without an internal ground (i.e. QFP, PLCC, etc.) the die-paddle is used instead. The mechanical sample for all capacitance (self & mutual) measurements are nished units with all internal leads oating. The DUT interface provides a physical connection between the oscilloscope and the DUT with minimum crosstalk and probe/ DUT reection. It also provides small ground loop to minimize ground inductance of the xture.

Inductance & Capacitance Model Extraction

All measured reection waveforms are downloaded to a PC running the analysis software for package parasitic model extraction. The software uses a method called the Z-prole algorithm, or the impedance-prole algorithm, for parasitic analysis. This method translates the downloaded reection waveforms into true impedance waveforms, from which package models for inductance and capacitance are extracted.

Inductance & Capacitance Measurement Procedure

For inductance measurements, a minimum of 25% and maximum of 50% of packages leads, including all leads that are adjacent to the lead(s) under test, are insulated from the DUT xture ground. All other leads, except for the lead(s) under test, are grounded. This insulation forces the current to return through a low impedance path created on the opposite side of the package. It also eliminates mutual coupling from the neighboring leads. Self-inductance is measured by sending a fast risetime step waveform through the lead under test. The inductive reection waveform through the lead and the bondwire is then obtained. This reection waveform, which includes the inductance of the die-paddle (for QFP and PLCC-type packages) and

Data Acquisition and Package Electrical Database

Xilinx acquires electrical parasitic data only on the longest and the shortest lead/traces of the package. This provides the best and the worst case for each package type (dened by package design, lead/ball count, pad size, and vendor). For convenience, the corner interconnects are usually selected as the longest interconnect, while the center interconnects are usually selected as the shortest. For symmetrical quad packages, all four sides of the package are measured and averaged. Three to ve samples are usually measured for accuracy and continuity purposes.

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The average of these samples is then kept as the ofcial measured parasitic data of that package type in the database.

Component Mass (Weight) by Package Type

Package BG225 BG256 BG352 BG432 BG560 CB100 CB100 CB164 CB164 CB196 CB228 DD8 HQ160 HQ208 HQ240 HQ304 PC20 PC44 PC68 PC84 PD8 PG84 PG120 PG132 PG156 PG175 PG191 PG223 PG299 PG299 PG411 PG475 PG559 PP132 PP175 PQ100 PQ160 PQ208 PQ240 SO8 TQ100 TQ144 TQ176 Description MOLDED BGA 27 mm FULL MATRIX MOLDED BGA 27 mm SQ SUPERBGA - 35 X 35 mm PERIPHERAL SUPERBGA - 40 X 40 mm PERIPHERAL SUPERBGA - 42.5 X 42.5 mm SQ NCTB TOP BRAZE 3K VER NCTB TOP BRAZE 4K VER NCTB TOP BRAZE 3K VER NCTB TOP BRAZE 4K VER NCTB TOP BRAZE 4K VER NCTB TOP BRAZE 4K VER .300 CERDIP PACKAGE METRIC 28 28 -.65 mm 1.6H/S DIE UP METRIC 28 X 28 - H/S DIE UP METRIC QFP 32 32 - H/S DIE UP METRIC QFP 40 40-H/S DIE DOWN PLCC JEDEC MO-047 PLCC JEDEC MO-047 PLCC JEDEC MO-047 PLCC JEDEC MO-047 DIP .300 STANDARD CERAMIC PGA CAV UP 11X11 CERAMIC PGA 13 X 13 MATRIX CERAMIC PGA 14 X 14 MATRIX CERAMIC PGA 16 X 16 MATRIX CERAMIC PGA 16 X 16 STD VER. CERAMIC PGA 18 X 18 STD - ALL CERAMIC PGA 18 X 18 TYPE CERAMIC PGA 20 X 20 HEATSINK CERAMIC PGA 20 X 20 TYPE CERAMIC PGA 39 X 39 STAGGER CERAMIC PGA 41 X 41 STAGGER CERAMIC PGA 43 x 43 PLASTIC PGA 14 X 14 MATRIX PLASTIC PGA 16 X 16 BURIED EIAJ 14 X 20 QFP - 1.60 EIAJ 28 X 28 .65 mm 1.60 EIAJ 28 X 28 .5 mm 1.30 EIAJ 32 X 32 .5 mm VERSION 1 - .150/55MIL THIN QFP 1.4 mm thick THIN QFP 1.4 mm thick THIN QFP 1.4 mm thick JEDEC Outline # MO-151-CAL MO-151-CAL MO-151-BAR MO-151-BAU MO-192-BAV MO-113-AD3 MO-113-AD3 MO-113-AA-AD3 MO-113-AA-AD3 MO-113-AB-AD3 MO-113-AD3 MO-036-AA MO-108-DDI MO-143-FA1 MO-143-GA MO-143-JA MO-047-AA MO-047-AC MO-047-AE MO-047-AF MO-001-AA MO-067-AC MO-067-AE MO-067-AF MO-067-AH MO-067-AH MO-067-AK MO-067-AK MO-067-AK MO-067-AK MO-128-AM MO-128-AM MO-128 MO-83-AF MO-83-AH MO-108-CC1 MO-108-DD1 MO-143-FAI MO-143-GA MO-150 MS-026-BDE MS-026-BFB MS-026-BGA Xilinx # OBG0001 OBG0011 OBG0008 OBG0009 OBG0010 OCQ0008 OCQ0006 OCQ0003 OCQ0007 OCQ0005 OCQ0012 OPD0005 OPQ0021 OPQ0020 OPQ0019 OPQ0014 OPC0006 OPC0005 OPC0001 OPC0001 OPD0002 OPG0003 OPG0012 OPG0004 OPG0007 OPG0009 OPG0008 OPG0016 OPG0022 OPG0015 OPG0019 OPG0023 OPG0025 OPG0001 OPG0006 OPQ0013 OPQ0002 OPQ0003 OPQ0010 OPD0006 OPQ0004 OPQ0007 OPQ0008 Mass (g) 2.2 2.2 7.1 9.1 11.5 10.8 10.8 11.5 11.5 15.3 17.6 1.1 10.8 10.8 15.0 26.2 0.8 1.2 4.8 6.8 0.5 7.2 11.5 11.8 17.1 17.7 21.8 26.0 37.5 29.8 36.7 39.5 44.50 8.1 11.1 1.6 5.8 5.3 7.1 0.1 0.7 1.4 1.9

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Component Mass (Weight) by Package Type (Continued)

Package VO8 VQ44 VQ64 VQ100 Description THIN SOIC-II THIN QFP 1.0 thick THIN QFP 1.0 thick THIN QFP 1.0 thick JEDEC Outline # N/A MS-026-ACB MS-026-ACD MS-026-AED Xilinx # OPD0007 OPQ0017 OPQ0009 OPQ0012 Mass (g) 0.1 0.4 0.5 0.6

Notes: 1. Data represents average values for typical packages with typical devices. The accuracy is between 7% to 10%. 2. More precise numbers (below 5% accuracy) for specic devices may be obtained from Xilinx through a factory representative or by calling the Xilinx Hotline. 3. Tie-bar details are specic to Xilinx package. Lead width minimum is 0.056.

Xilinx Thermally Enhanced Packaging

The Package Offering
Xilinx Code HQ160 HQ208 HQ240 HQ304 Body (mm) 28x28 28x28 32x32 40x40 THK (mm) 3.40 3.40 3.40 3.80 Mass (gm) 10.8 10.0 15.0 26.2 Heatsink Location DOWN DOWN DOWN TOP JEDEC No. MO-108-DD1 MO-143-FA MO-143-GA MO-143-JA Xilinx No. OPQ0021 OPQ0020 OPQ0019 OPQ0014

Overview
Xilinx offers thermally enhanced quad at pack packages on certain devices. This section discusses the performance and usage of these packages (designated HQ). In summary: The HQ-series and the regular PQ packages conform to the same JEDEC drawings. The HQ and PQ packages use the same PCB land patterns. The HQ packages have more mass Thermal performance is better for the HQ packages -

package. This was done to ensure pin to pin compatibility with the existing PQ and MQ packages. At the 304 pin count level, the HQ is offered with the heatsink up. This arrangement offers a better potential for further thermal enhancement by the designer.
A Die Up/Heatsink Down

B Die Down/Heatsink Up

Where and When Offered

HQ packages are offered as the thermally enhanced equivalents of PQ packages. They are used for high gate count or high l/O count devices in packages, where heat dissipation without the enhancement may be a handicap for device performance. Such devices include XC4013E, XC4020E, XC4025E, and XC5215. They are also being used in place of MQUAD (MQ) packages of the same lead count for new devices. The HQ series at the 240 pin count level or below are offered with the heatsink at the bottom of the

A Heatsink down orientation B Heatsink up orientation

X5962

Mass Comparison
Because of the copper heatsink, the HQ series of packages are about twice as heavy as the equivalent PQ. Here is a quick comparison. HQ (gm) 10.8 10.8 15.0 26.2 PQ (gm) 5.8 5.3 7.1 N/A

160 Pin 208 Pin 240 Pin 304 Pin

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Thermal Data for the HQ

The data for individual devices may be obtained from Xilinx. Still Air Data Comparison PQ HQ JA (C/watt) JA (C/Watt) 160 Pin 208 Pin 240 Pin 304 Pin
Note:

nants to the die surface and increasing the potential for early device failure. How the effects of moisture in plastic packages and the critical moisture content result in package damage or failure is a complex function of several variables. Among them are package construction details -- materials, design, geometry, die size, encapsulant thickness, encapsulant properties, TCE, and the amount of moisture absorbed. The PSMC moisture sensitivity has, in addition to package cracking, been identied as a contributor to delaminationrelated package failure artifacts. These package failure artifacts include bond lifting and breaking, wire neckdown, bond cratering, die passivation, and metal breakage. Because of the importance of the PSMC moisture sensitivity, both device suppliers and device users have ownership and responsibility. The background for present conditions, moisture sensitivity standardized test and handling procedures have been published by two national organizations. Users and suppliers are urged to obtain copies of both documents (listed below) and use them rigorously. Xilinx adheres to both. JEDEC STANDARD JESD22-A112. Test Method A112 Moisture-Induced Stress Sensitivity for Plastic Surface Mounted Devices. Available through Global Engineering Documents Phone: USA and Canada 800-854-7179, International 1-303-792-2181 IPC Standard IPC-SM-786A Procedures for Characterizing and Handling of Moisture/Reow Sensitive ICs. Available through IPC Phone: 1-708-677-2850 None of the previously stated or following recommendations apply to parts in a socketed application. For board mounted parts careful handling by the supplier and the user is vital. Each of the above publications has addressed the sensitivity issue and has established 6 levels of sensitivity (based on the variables identied). A replication of those listings, including the preconditioning and test requirements, and the factory oor life conditions for each level are outlined in Table 4. Xilinx devices are characterized to their proper level as listed. This information is conveyed to the user via special labeling on the Moisture Barrier Bag (MBB). In Table 4, the level number is entered on the MBB prior to shipment. This establishes the users factory oor life conditions as listed in the time column. The soak requirement is the test limit used by Xilinx to determine the level number. This time includes manufacturers exposure time or the time it will take for Xilinx to bag the product after baking.

13.5-14.5 14-15 12-13 10-11

20.5-38.5 26-35 19-28 N/A

JC is typically between 1 and 2 C/Watt for HQ and MQ Packages. For PQs, it is between 2 and 7 C/Watt.

Data Comparison at Airow - 250 LFM PQ HQ JA (C/watt) JA (C/watt) 160 Pin 208 Pin 240 Pin 304 Pin 9-10 9-10 8-9 6.5-8 15-28.5 14-26 11-21 N/A

Other Information
Leadframe: Copper EFTEC-64 or C7025 Heat Slug: Copper - Nickel plated Heatsink metal is Grounded Lead Finish 85/15 Sn/Pb 300 microinches minimum D/A material - Same as PQ; Epoxy 84-1LMISR4 Mold Cpd. Same as PQ - EME7304LC Packed in the same JEDEC trays

Moisture Sensitivity of PSMCs

Moisture Induced Cracking During Solder Reow
The surface mount reow processing step subjects the Plastic Surface Mount Components (PSMC) to high thermal exposure and chemicals from solder uxes and cleaning uids during users board mount assembly. The plastic mold compounds used for device encapsulation are, universally, hygroscopic and absorb moisture at a level determined by storage environment and other factors. Entrapped moisture can vaporize during rapid heating in the solder reow process generating internal hydrostatic pressure. Additional stress is added due to thermal mismatch, and the Thermal Coefcient of Expansion (TCE) of plastic, metal lead frame, and silicon die. The resultant pressure may be sufcient to cause delamination within the package, or worse, an internal or external crack in the plastic package. Cracks in the plastic package can allow high moisture penetration, inducing transport of ionic contami-

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Table 4: Package Moisture Sensitivity Levels per J-STD-020 Level 1 2 Factory Floor Life Conditions Time 30C / 90% Unlimited RH 30C / 60% 1 year RH X + 24 24 24 0 Soak Requirements (Preconditioning) Time Conditions 168 hours 85C / 85% RH 168 hours Time (hours) Y = 168 72 24/48 6 85C / 60% RH

3 4 5 6
Notes:

30C / 60% RH 30C / 60% RH 30C / 60% RH 30C / 60% RH

168 hours 72 hours 24/28 hours 6 hours

Z 192 96 48/72 6

30C / 60% RH 30C / 60% RH 30C / 60% RH 30C / 60% RH

X = Default value of semiconductor manufacturers time between bake and bag. If the semiconductor manufacturers actual time between bake and bag is different from the default value, use the actual time. Y = Floor life of package after it is removed from dry pack bag. Z = Total soak time for evaluation.

Factory Floor Life

Factory oor life conditions for Xilinx devices are clearly stated on MBB containing moisture sensitive PSMCs. These conditions have been ascertained by following Test Methods outlined in JEDEC JESD22-A112 and are replicated in Table 4. If factory oor conditions are outside the stated environmental conditions (30C/90% RH for level 1, and 30C/60% RH for Levels 2-6) or if time limits have been exceeded, then recovery can be achieved by baking the devices before the reow step. Identied in the next section are two acceptable bake schedules. Either can be used for recovery to the required factory oor level.

the internal humidity level. The loaded bag is then sealed shut under a partial vacuum with an impulse heat sealer. Artwork on the bags provides storage, handling and use information. There are areas to mark the seal date, quantity, and moisture sensitivity level and other information. The following paragraphs contain additional information on handling PSMCs.

Handling Parts in Sealed Bags

Inspection
Note the seal date and all other printed or hand entered notations. Review the content information against what was ordered. Thoroughly inspect for holes, tears, or punctures that may expose contents. Xilinx strongly recommends that the MBB remain closed until it reaches the actual work station where the parts will be removed from the factory shipping form.

Dry Bake Recommendation and Dry Bag Policy

Xilinx recommends, as do the mentioned publications and other industry studies, that all moisture sensitive PSMCs be baked prior to use in surface mount applications, or comply strictly with requirements as specied on the MBB. Tape and Reeled parts are universally dry packed. Level 1 parts are shipped without the need for, or use of, an MBB. Two bake schedules have been identied as acceptable and equivalent. The rst is 24 hours in air at 125C., in shipping media capable of handling that temperature. The second bake schedule is for 192 hours in a controlled atmosphere of 40C, equal to or less than 5% RH. Dry Devices are sealed in special military specication Moisture Barrier Bags (MBB). Enough desiccant pouches are enclosed in the MBB to maintain contents at less than 20% RH for up to 12 months from the date of seal. A reversible Humidity Indicator Card (HIC) is enclosed to monitor

Storage
The sealed MBB should be stored, unopened, in an environment of not more than 90% RH and 40C. The enclosed HIC is the only verication to show if the parts have been exposed to moisture. Nothing in part appearance can verify moisture levels.

Expiration Date
The seal date is indicated on the MBB. The expiration date is 12 months from the seal date. If the expiration date has been exceeded or HIC shows exposure beyond 20% upon opening the bag bake the devices per the earlier stated

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bake schedules. The three following options apply after baking: Use the devices within time limits stated on the MBB. Reseal the parts completely under a partial vacuum with an impulse sealer (hot bar sealer) in an approved MBB within 12 hours, using fresh desiccant and HIC, and label accordingly. Partial closures using staples, plastic tape, or cloth tape are unacceptable. Store the out-of-bag devices in a controlled atmosphere at less than 20% RH. A desiccator cabinet with controlled dry air or dry nitrogen is ideal.

provides room for possible resealing and adhering to the reseal conditions outlined above. After opening, strictly adhere to factory oor life conditions to ensure that devices are maintained below critical moisture levels. Bags opened for less than one hour (strongly dependent on environment) may be resealed with the original desiccant. If the bag is not resealed immediately, new desiccant or the old one that has been dried out may be used to reseal, if the factory oor life has not been exceeded. Note that factory oor life is cumulative. Any period of time when MBB is opened must be added to all other opened periods. Both the desiccant pouches and the HIC are reversible. Restoration to dry condition is accomplished by baking at 125C for 10-16 hours, depending on oven loading conditions.

Other Conditions
Open the MBB when parts are to be used. Open the bag by cutting across the top as close to the seal as possible. This

Tape and Reel

Xilinx offers a tape & reel packing for PLCC, BGA, QFP, and SO packages. The packing material is made of black conductive Polystyrene and protects the packages from mechanical and electrical damage. The reel material provides a suitable medium for pick and place equipment. The tape & reel packaging consists of a pocketed carrier tape, sealed with a protective cover. The device sits on pedestals (for PLCC, QFP packages) to protect the leads from mechanical damage. All devices loaded into the tape carriers are baked, lead scanned before the cover tape is attached and sealed to the carrier. In-line mark inspection for mark quality and package orientation is used to ensure shipping quality.

Material and Construction

Carrier Tape
The pocketed carrier Tape is made of conductive polystyrene material, or equivalent, with a surface resistivity level of less than 106 ohms per square inch. Devices are loaded live bug or leads down, into a device pocket. Each carrier pocket has a hole in the center for automated sensing of whether a unit is in the pocket or not. Sprocket holes along the edge of the carrier tape enable direct feeding into an automated board assembly equipment. An anti-static, transparent, polyester cover tape, with heat activated adhesive coating, sealed to the carrier edges to hold the devices in the carrier pockets. Surface resistivity on both sides is less than 1011 ohms per square inch. The reel is made of anti-static Polystyrene material. The loaded carrier tape is wound onto this conductive plastic reel. A protective strip made of conductive Polystyrene material is placed on the outer part of the reel to protect the devices from external pressure in shipment. Surface resistivity is less than 1011 ohms per square inch. Device loading orientation is in compliance with EIA Standard 481. The bar code label on each reel provides customer identication, device part number, date code of the

Benets
Increased quantity of devices per reel versus tubes improves cycle time and reduces the amount of time to index spent tubes. Tape & reel packaging enables automated pick and place board assembly. Reels are uniform in size enabling equipment exibility. Transparent cover tape allows device verication and orientation. Anti-static reel materials provides ESD protection. Carrier design include a pedestal to protect package leads during shipment. Bar code labels on each reel facilitate automated inventory control and component traceability. All tape & reel shipments include desiccant pouches and humidity indicators to insure products are safe from moisture. Compliant to Electronic Industries Association (EIA) 481.

Cover Tape

Reel

Bar Code Label

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product and quantity in the reel. Print quality are in accordance with ANSI X3.182-1990 Bar Code Print Quality Guidelines. Presentation of Data on labels are EIA-556-A compliant. The label is an alphanumeric, medium density Code 39 labels. This machine-readable label enhances inventory

management and data input accuracy.

Shipping Box
The shipping container for the reels are in a 13 x 13 x 3 C-ute, corrugated, # 3 white pizza box, rated to 200 lb test.

Table 5: Tape & Reel Packaging Package Type PLCC (Plastic Leaded Chip Carrier) Pin Count 20 20 44 68 84 8 100 160 225/256 Carrier Width 16 mm 16 mm 32 mm 44 mm 44 mm 12 mm 44 mm 44 mm 44 mm Cover Width 13.3 mm 13.3 mm 25.5 mm 37.5 mm 37.5 mm 9.2 mm 37.5 mm 37.5 mm 37.5 mm Pitch 12 mm 12 mm 24 mm 32 mm 36 mm 8 mm 32 mm 40 mm 32 mm Reel Size 7 inch 13 inch 13 inch 13 inch 13 inch 7 inch 13 inch 13 inch 13 inch Qty per Reel 250 750 500 250 250 750 250 200 500

SO (Plastic Small Outline) QFP (Plastic Quad Flat Pack) PQ, VQ, TQ, HA BGA (Plastic Ball Grid Array)
Notes:

1.A minimum of 230mm of empty pockets are provided at the beginning (leader) of each reel. 2.A minimum of 160mm of empty pockets are provided at the end (trailer) of each reel. 3.Tape Leader/Trailer requirements are in compliance to EIA Standards 481. 4.Peel Strength between 20 and 120 grams ensures consistency during de-reeling operations and is compliant to EIA Standard 481. 5.Each reel is subject to peel back strength tests. 6.For packages not listed above, please contact your Xilinx sales representative for updated information.

Standard Bar Code Label Locations

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Reow Soldering Process Guidelines

In order to implement and control the production of surface mount assemblies, the dynamics of the solder reow process, and how each element of the process is related to the end result, must be thoroughly understood. The primary phases of the reow process are as follows: 1. Melting the particles in the solder paste 2. Wetting the surfaces to be joined 3. Solidifying the solder into a strong metallurgical bond The sequence of ve actions that occur during this process is shown in Figure 2. Each phase of a surface mount reow prole has min/max limits that should be viewed as a process window. The process requires a careful selection and control of the materials, geometries of the mating surfaces (package footprint vs. PCB land pattern geometries) and the time temperature of the prole. If all of the factors of the process are sufciently optimized, there will be good solder wetting and llet formation (between component leads and the land patterns on the substrate). If factors are not matched and optimized there can be potential problems as summarized in Figure 3.

Potential Reflow Soldering Issues

Reflow Soldering Phases

200
Temperature (C) Solder Melting Completes, Surface Tension Takes Over Solder Balls Melt, Wetting and Wicking Begin

Temperature

4 5 2 3

150

100
Flux Reduces Metal Oxides Solvent Evaporation

Cool Down Phase

Time 1. Insufficient Temperature to Evaporate Solvent 2. Component Shock and Solder Splatter 3. Insufficient Flux Activation 4. Excessive Flux Activity and Oxidation 5. Trapping of Solvent and Flux, Void Formation 6. Component and/or Board Damage
X5975

50

X5976

Time
Figure 2: Soldering Sequence

Figure 3: Soldering Problems Summary

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Figure 4 and Figure 5 show typical conditions for solder reow processing using Vapor Phase or IR Reow. The moisture sensitivity of Plastic Surface Mount Components
T-Max (leads) 220 - 235C 2 - 4C/s
Temperature C

(PSMCs) must be veried prior to surface mount ow.See the preceding sections for a more complete discussion on PSMC moisture sensitivity.
215 - 219C 45 s max Ramp down 2 - 4C/s t183 Dwell = 30 - 60 s Preheat & drying dwell 3 120 s min between 95 - 180C

2 Temperature C

Temp = 183C t183 Preheat & drying dwell 120 - 180 s between 95 - 180C 3 2 Time (s)

Ramp down 2 - 4C/s

60s < t183 < 120s applies to lead area

2

Time (s)
X5973

X5974

Figure 4: Typical conditions for IR reow soldering

Notes: 1. Max temperature range = 220C-235C (leads) Time at temp 30-60 seconds 2. Preheat drying transition rate 2-4C/s 3. Preheat dwell 95-180C for 120-180 seconds 4. IR reow shall be performed on dry packages The IR process is strongly dependent on equipment and loading differences. Components may overheat due to lack of thermal constraints. Unbalanced loading may lead to signicant temperature variation on the board. This guideline is intended to assist users in avoiding damage to the components; the actual prole should be determined by the users using these guidelines.

Figure 5: Typical conditions for vapor phase reow soldering

Notes: 1. Solvent - FC5312 or equivalent - ensures temperature range of leads @ 215-219C 2. Transition rate 4-5C/s 3. Dwell is intended for partial dryout and reduces the difference in temperature between leads and PCB land patterns. 4. These guidelines are for reference. They are based on laboratory runs using dry packages. It is recommended that actual packages with known loads be checked with the commercial equipment prior to mass production.

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Packages and Thermal Characteristics

Sockets
Table 6 lists manufacturers known to offer sockets for Xilinx Package types. This summary does not imply an endorseTable 6: Socket Manufacturers Packages PQ HQ TQ PG VQ PP X ment by Xilinx. Each user has the responsibility to evaluate and approve a particular socket manufacturer.

Manufacturer

DIP SO VO X

PC WC X

CB

BG CG

AMP Inc. 470 Friendship Road Harrisburg, PA 17105-3608 (800) 522-6752 Augat Inc. 452 John Dietsch Blvd. P.O. Box 2510 Attleboro Falls, MA 02763-2510 (508) 699-7646 McKenzie Socket Division 910 Page Avenue Fremont, CA 94538 (510) 651-2700 3M Textool 6801 River Place Blvd. Austin, TX 78726-9000 (800) 328-0411 (612) 736-7167 Wells Electronics 1701 South Main Street South Bend, IN 46613-2299 (219) 287-5941 Yamaichi Electronics Inc. 2235 Zanker Road San Jose, CA 95131 (408) 456-0797

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Package Drawings
0 10*

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Package Drawings
Ceramic DIP Package - DD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Plastic DIP Package - PD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOIC and TSOP Packages - SO8, VO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOIC Package - SO20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLCC Packages - PC20, PC28, PC44, PC68, PC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VQFP Packages - VQ44, VQ64, VQ100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQFP/HTQFP Packages - TQ100, TQ144, TQ176, HT100, HT144, HT176 . . . . . . . . . . . . . . . PQ/HQFP Packages - PQ100, HQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PQ/HQFP Packages - PQ44, PQ160, PQ208, PQ240, HQ160, HQ208, HQ240 . . . . . . . . . . . . PQ/HQFP Packages - PQ304, HQ304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGA Packages - BG225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGA Packages - BG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGA Packages - BG352, BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGA Packages - BG560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG68, PG84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG120, PG132, PG156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG223, PG299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG411. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG475. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages - PG559. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic Brazed QFP Packages - CB100 (XC3000 Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic Brazed Packages - CB164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic Brazed QFP Packages - CB100, CB164, CB196 (XC4000 Version) . . . . . . . . . . . . . . Ceramic Brazed QFP Packages - CB228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31 10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 10-41 10-42 10-43 10-44 10-45 10-46 10-47

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10

Package Drawings

Ceramic DIP Package - DD8

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Plastic DIP Package - PD8

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Package Drawings

SOIC and TSOP Packages - SO8, VO8

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SOIC Package - SO20

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Package Drawings

PLCC Packages - PC20, PC28, PC44, PC68, PC84

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Package Drawings

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VQFP Packages - VQ44, VQ64, VQ100

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Package Drawings

TQFP/HTQFP Packages - TQ100, TQ144, TQ176, HT100, HT144, HT176

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PQ/HQFP Packages - PQ100, HQ100

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Package Drawings

PQ/HQFP Packages - PQ44, PQ160, PQ208, PQ240, HQ160, HQ208, HQ240

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PQ/HQFP Packages - PQ304, HQ304

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10

Package Drawings

BGA Packages - BG225

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BGA Packages - BG256

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Package Drawings

BGA Packages - BG352, BG432

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BGA Packages - BG560

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Package Drawings

November 13, 1997 (Version 1.2)

10

Package Drawings

Ceramic PGA Packages - PG68, PG84

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Ceramic PGA Packages - PG120, PG132, PG156

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Package Drawings

Ceramic PGA Packages - PG175

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Package Drawings

November 13, 1997 (Version 1.2)

10

Ceramic PGA Packages - PG191

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Package Drawings

Ceramic PGA Packages - PG223, PG299

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Ceramic PGA Packages - PG411

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Package Drawings

Ceramic PGA Packages - PG475, PG559

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Ceramic Brazed QFP Packages - CB100 (XC3000 Version)

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Package Drawings

Ceramic Brazed Packages - CB164

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Package Drawings

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10

Ceramic Brazed QFP Packages - CB100, CB164, CB196 (XC4000 Version)

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Ceramic Brazed QFP Packages - CB228

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Testing, Quality, and Reliability

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Testing, Quality, and Reliability Table of Contents

Quality Assurance and Reliability

Quality Assurance Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Die Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Integrity and Assembly Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Cell Design in the FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Temperature Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-2 11-2 11-2 11-2 11-3 11-7 11-7 11-8 11-8 11-8

Quality Assurance and Reliability

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Quality Assurance Program

All aspects of the Quality Assurance Program at Xilinx have been designed to eliminate the root cause of defects, rather than to try to remove them by inspection. A quality system was put in place which is in full compliance with the requirements of ISO9002. Xilinx was found to be in full compliance of the requirements of ISO9002:1994 by an independent auditor in October, 1995. At that time Xilinx was registered for the manufacturing and testing of programmable logic devices. Last November, Xilinx was audited by DSCC and found in full compliance with the requirements of MIL 38535 for a QML supplier. In January 1997 Xilinx was formaly granted transitional QML approval by DSCC. The aspects of ISO compliance in place at Xilinx include the following seventeen points: Management Review: a comprehensive system of management attention and direction for all aspects of company performance that directly affect our customers. These include (among others) Xilinx performance in the areas of Quality, Reliability and OnTime Delivery. Management assures that this quality policy is understood, implemented and maintained at all levels in the organization. Quality Systems: are in place to ensure that product conforms to customer specications. These systems facilitate, measure and continuously improve Xilinx performance in those areas that affect customer satisfaction. Xilinx remains committed to achieving 100% customer satisfaction. Contract Review: is conducted to ensure each contract adequately denes and documents requirements, that differences between customer and Xilinx standard specications are mutually satisfactorily resolved, and that Xilinx has the capability to meet contract requirements. Document Control: procedures are established and maintained to control all documents and data that relate to the performance of Xilinx business and processing requirements. All organizations who need access to such documentation during the performance of their functions are assured availability of the latest, controlled versions of that documentation. Purchasing: procedures are in place to ensure that all purchased products conform to the specied requirements. As Xilinx is a fabless manufacturing company, special attention is paid to our subcontract partners. They are required to demonstrate the type of

control and capabilities that our customers require. All key Xilinx subcontract partners are ISO certied. Product Identication & Traceability: is maintained throughout the manufacturing process. Traceability back to the starting materials is available through unique product identication techniques and markings throughout the manufacturing process. Process Control: is assured by identifying and controlling those processes that directly affect the quality of our products, whether those processes are performed directly by Xilinx, or by our subcontract partners. Inspection & Test: is performed to ensure that incoming product is not used or processed until it has been veried as conforming to required specications. This inspection is done jointly by Xilinx and by its subcontract partners. Inspection, Measuring and Test Equipment: is calibrated in conformance with the requirements of Mil Ref 45662 and/or other international standards. Equipment is maintained in such a manner to ensure that measurement uncertainty is known and is consistent with specication requirements. Inspection & Test Status: of product is uniquely identied throughout the manufacturing process both at Xilinx and at our subcontract partners. Records are kept to identify the authority responsible for the release of conforming production. Control of Non-Conforming Product: is assured through disposition procedures that are dened in such a manner as to prevent the shipping of non-conforming products. The responsibility and authority for the disposition of such products are well dened. Corrective Action: processes are documented and implemented to prevent the recurrence of nonconforming product. These processes are the key to implementing the Xilinx strategy of eliminating the root causes of nonconformity, rather that to apply inspection to try to remove nonconformity. Handling, Storage, Packing & Delivery: procedures are dened and implemented to prevent damage or deterioration of product once the manufacturing process is complete. Quality Records: procedures are established and maintained for the identication, collection, indexing, ling, storage, maintenance and disposition of quality records. Internal Quality Audits: are carried out to verify whether quality activities comply with planned

November 21, 1997 (Version 2.0)

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Quality Assurance and Reliability

arrangements and to determine the effectiveness of the quality system. These audits are regularly supplemented by quality audits performed by our customers, and by our independent ISO auditors. Training: procedures have been established and are maintained to identify the training needs of all personnel affecting quality during the production of Xilinx products. Personnel performing such activities are qualied based upon appropriate education, training and/or experience. Statistical Techniques: are in place at Xilinx and at our subcontract partners for verifying the acceptability of process capabilities and product characteristics.

at 125C (equivalent) to yield the FIT rates shown in Figure 1.

Description of Tests
Die Qualication
1. High Temperature Life: This test is performed to evaluate the long-term reliability and life characteristics of the die. It is dened by the Military Standard from which it is derived as a Die-Related Test and is contained in the Group C Quality Conformance Tests. Because of the acceleration factor induced by higher temperatures, (typically 125C and/or 145C) data representing a large number of equivalent hours at a normal temperature of 25C can be accumulated in a reasonable period of time. 2. Biased Moisture Life: This test is performed to evaluate the reliability of the die under conditions of long-term exposure to severe, high-moisture environments that could cause corrosion. Although it clearly stresses the package as well, this test is typically grouped under the die-related tests. The device is operated at maximumrated voltage, 5.5 Vdc, and is exposed to a temperature of 85C and a relative humidity of 85% throughout the test.

These key requirements are in place at Xilinx and at our subcontract partners to ensure our ability to achieve customer satisfaction through the on-time delivery of quality products that meet customer requirements and are reliable.

Device Reliability
Device reliability is often expressed in a measurement called Failures in Time (FITs). In this measure one FIT equals one failure per billion (109) device operating hours. A failure rate in FITS must include the operating temperature to be meaningful. Hence failure rates are often expressed in FITS at 70C (or some other temperature in excess of the application). Since one billion hours is well in excess of 100,000 years, the FIT rate of modern ICs can only be measured by accelerating the failure rate by testing at a higher junction temperature (usually 125C or 145C). Extensive testing of Xilinx devices (performed on actual production devices taken directly from nished goods) has been accomplished continuously since 1989 and reported quarterly. Quarterly reports on the reliability of Xilinx products are available through your Xilinx sales representative and at the WebLINX web site (www.xilinx.com). During the last two years, over 20,000 devices have accumulated a total of over 36,000,000 hours of both static and dynamic operation

Package Integrity and Assembly Qualication

1. Unbiased Pressure Pot: This test is performed at a temperature of 121C and a pressure of 2 atm of saturated steam to evaluate the ability of the plastic encapsulating material to resist water vapor. Moisture penetrating the package could induce corrosion of the bonding wires and nonglassivated metal areas of the die (bonding pads only for FPGA devices). Under extreme conditions, moisture could cause drive-in and corrosion under the glassivation. Although it is difcult to correlate this test to actual eld conditions, it provides a wellestablished method for relative comparison of plastic

Xilinx Historical Reliability

50 40
XC1700 XC4000

FITs@70C

30
XC3000

20 10 0 -10 Jun-94
XC3100 AVG XC2000

Sep-94

Dec-94

Mar-95

Jun-95 Time

Sep-95

Dec- 95

Mar- 96

Jun--96

Sep-96
X5977

Figure 1: Failure Rates in FITs

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packaging materials and assembly and molding techniques. 2. Thermal Shock: This test is performed to evaluate the resistance of the package to cracking and resistance of the bonding wires and lead frame to separation or damage. It involves nearly instantaneous change in temperature from -65C to +150C (condition C). 3. Temperature Cycling: This test is performed to evaluate the long-term resistance of the package to damage from alternating exposure to temperature extremes. The range of temperatures is -65C to +150C (condition C). The transition time is longer than that in the Thermal Shock test but the test is conducted for many more cycles. 4. Salt Atmosphere: This test was originally designed by the US Navy to evaluate resistance of military-grade ship-board electronics to corrosion from sea water. It is used more generally for non-hermetic industrial and commercial products as a test of corrosion resistance of the package marking and nish. 5. Resistance to Solvents: This test is performed to evaluate the integrity of the package marking during exposure to a variety of solvents. This is an especially important test, since an increasing number of board-

level assemblies are subjected to severe conditions of automated cleaning before system assembly. This test is performed according to the methods specied by MILSTD-883. 6. Solderability: This test is performed to evaluate the solderability of the leads under conditions of low soldering temperature following exposure to the aging effects of water vapor. 7. Lead Fatigue: This test is performed to evaluate the resistance of the completed assembly to vibrations during storage, shipping, and operation.

Testing Facilities
Xilinx has complete capability to perform High Temperature Life Testing, Thermal Shock, Temperature Cycling, Biased Moisture Life Test, Unbiased Pressure Pot, Solderability and Hermeticity, as well as complete Failure Analysis in house. Table 1 and Table 2 show typical qualication requirements for new and/or changed process ows. Table 3 is a list of current failure analysis capabilities. These laboratories are dedicated exclusively to increasing customer satisfaction through continuous improvements in our processes and technologies.

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Quality Assurance and Reliability

Table 1: Plastic Package/Product Qualication Requirements

New Assy Techniques (Matl/Process/Method Test Seq Test Description (note 1) Acc# New S.Size Assy (note 2) Plant New New Pkg Pkg Type I Type II (note3) (note4) New Lead Die Pkg Frame Attach Type III LF Design (note5) Die Coat Wire Bond Mold CLP Lead New Finish Device Mask (note6) New Fab Proc Full Qual

B1 B2 B3 B4 B5 B6 B7 B8 B9

* Phy. Dimension * Resist. to Solvents * Solderability Test (note 7) Solder Heat Test (Optnl) Auto Clave (SPP)(Optnl) 0/76 * Ball Shear/Bond Pull (note 7) ** X-Ray (note 7) * S.A.T/Dye Pen Test (note 7) * Adhesion of L/Finish (Optnl)

0/5 0/3 0/5 0/15 0/76 0/5 0/5 0/10 0/3 0/25 0/5 0/5 Per lot 0/76 0/22 0/76 0/3 0/77 0/3 0/76 0/76 0/30 0/30 0/9 0/11 0/22 0/5 0/22 E.Good

X X X

X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 464 10 474 X X X X X X X X

X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 636 64 700

X X X X X X X X

X X X X X X

B10 * External Visual (note 7) B11 Internal Visual (note 7) B12 * Die Shear (note 7) B13 Flammability Test (note 7) C1-A High Temp Life Test C1-B Low Temp Life Test (note 7) C2 C3 C4 D1 D2 D3 E1 E2 E3 E4 E5 E6 E7 E8 E9 C2-A:HAST (0/22) or C2-B: 85/85 ESD (HBM) High Temp Storage (Optnl) * Lead Integrity Thermal Shock (Optnl) Temp Cycle Electrical Test & Data Log Electrical Characterization T.D.D.B (note 7) Latch-up Electromigration (note 7) Photosensitivity (Optnl) Data Retention Bake EPLD & EPR Input/Output Capacitance Power Cycling (Optnl) Qty required per lot

X X

X X

X X

239 63 302

238 48 286

162 43 205

248 35 283

248 43 291

157 5 162

314 5 319

86 5 91

325 43 368

0 29 29

393 10 403

E.Reject Total

Notes: 1) Test method and stress conditions available upon request. 2) For any QUAL which does not meet the standard requirements, approval from Product Engineering and Product QA is required. 3) Any new package which has not been qualied in the qualied assembly facility. 4) Any new package where the same body size with different lead pitch has been qualied. 5) New leadframe design whereby the paddle size is larger than the existing leadframe paddle size used in the same qualied package. 6) For new mask from same device family, only high temp life test, ESD, Latch & Capacitance are required. 7) In-process monitor data may be used to satisfy this requirement. *) Electrical rejects can be used as test sample. **) This is a non-destructive test, sample can be re-used.

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Table 2: Hermetic Package/Product Qualication Requirements (Commercial)

New Assy Techniques (Matl/Process/Method Test Seq Test Description (note 1) Acc# New S.Size Assy (note 2) Plant New New Lead Die Pkg Pkg Frame Attach Family Qual (note3) Family (note4) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 190 81 271 205 81 286 129 75 204 69 50 119 114 8 122 235 5 240 190 2 192 124 33 157 32 41 73 124 48 172 399 7 406 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 399 50 449 X Die Coat Wire Type of Lead New New Bond Seal Finish Cavity Device Size (note6) (note6) New Fab Proc Full Qual

B1 B2 B3 B4 B5 B6 B7

Solder Heat Test (Optnl) * Resist. to Solvents (note 7) * Solderability Test (note 7) * Die Shear/Stud Pull (note 7) * Bond Pull (note 7) * External Visual (note 7) Internal Visual (note 7)

0/15 0/3 0/3 0/5 0/2 0/25 0/5 0/76 0/22 0/77 0/3 0/15 0/3 0/32 0/32 0/15 0/3 0/2 0/5 0/45 0/30 0/30 0/9 0/11 0/22 0/5 E.Good E.Reject Total

X X X

X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 414 81 495

C1-A High Temp Life Test C1-B Low Temp Life Test (note 7) C2 C3 D1 D2 D3 D4 D5 D6 D7 D8 D9 E1 E2 E3 E4 E5 E6 E7 E8 High Temp Storage (Optnl) ESD (HBM) * Phy. Dimension * Lead Integrity Thermal Shock + Temp Cycl + Moisture Resistance Mech. Shock + Vibration + Constant Acceleration * Salt Atmosphere * Internal Vapor Content (note 7) * Adhesion of L/Finish (Optnl) * Lid Torque Temp Cycle Electrical Test & Data Log Electrical Characterization T.D.D.B (note 7) Latch-up Electromigration (note 7) Photosensitivity (Optnl) Data Retention Bake Input/Output Capacitance Qty required per lot

Notes: 1) Test method and stress conditions available upon request. 2) For any QUAL which does not meet the standard requirements, approval from Product Engineering and Product QA is required. 3) Package Family - A set of package type with the same package, material, Package construction techniques, terminal pitch, lead shape, row spacing and with identical package assembly tech. 4) Package Type - A package with a unique case outline, conguration, material, piece parts and assembly process. 5) Application to new piece parts or leadframe where cavity size is larger than the largest cavity size for the same package. 6) For new mask from same device family, only high temp life test, ESP, Latch & Capacitance are required. 7) In-process monitor data may be used to satisfy this requirement, for Qual data, data from Assy. lot traveler maybe used. *) Electrical rejects can be used as test samples

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Table 3: Failure Analysis Equipment List

Item Equipment Scanning Electron Microscope Gold Sputter (SEM Sample Prep) Energy Dispersive X-Ray F.I.B. - Focused Ion Beam Workstation Vendor JEOL ANATECH OXFORD INST. F.E.I. Model Number JMS-6401F Hummer VIII LINK ISISL200C FIB-600 FXS-100.10 Micro-Scan 4HF-200 MBS-200 XRF-5500 P/N 4330 Visionary 2000 Item Equipment 17 Die-Shear Tester Vendor KELLER Robotic Systems Robotic Systems B&G BID Services Model Number see #7 ST2D RPS-202 004-012-00

1 2 3 4 5 6 7 8

18 Steam Aging System 19 Solder Wave/Pot 20 Lead Fatigue Tester 21 Conventional Oven (C.D.A.) 22 Drill-bit to open MQUADS
+ Decapping vise

Real-Time X-Ray Imaging Sys- FEIN FOCUS tem Scanning Acoustic Microscopy Sonix Ball Shear Strength Tester KELLER

23 Color Printer 24 Stud Pull Tester 25 Work Benches 26 Cabinets 27 Facilities (Lab Area and
Equipment Installation Costs)

Tektronic B&G

XRF Lead Finish/Composition Twin City, Inc. Measurement System 9 Liquid Crystal Hot Spot Detec- Technology tion System/Kit, with 3 temp. Associates Hypervision 10 Emission Microscope for Multilayer Inspection (EMMI) BID Services 11 Curve Tracer

Tektronic Phaser IISD 003-010-00

12 Metallurgical High Power

Microscope

Scientific Instrument Company Scientific Instrument Company TM Associates Computer Modules

see quote (various) see quote (various)

28 Tool Maker Microscope 29 Flowhood & Rinse Station 30 Precision X-Sectioning Equipment

13 Stereozoom Low Power

Microscope - video camera + monitor 14 Micro-Etcher System

15 Viseco Camera Interface with

High Power Microscope 16 Hermeticity Test System - Fine Leak - Gross Leak

31 Plasma Etcher 32 E-Beam IDS-3000

March Instruments

CS-1701

BID Services -Trio-tech 486 - Veeco MS170

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VCC Configuration Data Shift Regiater Q N-1 VCC

DS DR DK SEL

DS DR DK SEL

Q Read

Data Clock

WR/RD

Clock

Address QN-1

CK Precharge Word N Memory Cell Circuit Memory Cell Word Line Driver Configuration Address Shift Regiater

D Memory Cell Word N+1 Memory Cell Memory Cell Word Line Driver CK

Bit M

Bit M+1

X3124

Figure 2: Conguration Memory Cell

Data Integrity
Memory Cell Design in the FPGA Device
An important aspect of SRAM-based FPGA device reliability is the robustness of the static memory cells used to store the conguration program. The basic cell is a single-ended 5-transistor memory element (Figure 2). By eliminating a sixth transistor, which would have been used as a pass transistor for the complementary bit line, a higher circuit density is achieved. During normal operation, the outputs of these cells are xed, since they determine the user conguration. Write and readback times, which have no relation to the device performance during normal operation, will be slower without the extra transistor. In return, the user receives more functionality per unit area. This explains the basic cell, but how is the FPGA user assured of high data integrity in a noisy environment? Consider three different situations: normal operation, a Write operation and a Read operation. In the normal operation, the data in the basic memory element is not changed. Since the two circularly linked inverters that hold the data are physically adjacent, supply transients result in only small relative differences in voltages. Each inverter is truly a complementary pair of transistors. Therefore, whether the output is High or Low, a low-impedance path exists to the supply rail, resulting in extremely high noise immunity. Power supply or ground transients of several volts have no effect on stored data. The transistor driving the bit line has been carefully designed so that whenever the data to be written is opposite the data stored, it can easily override the output of the feedback inverter. The reliability of the Write operation is guaranteed within the tolerances of the manufacturing process. In the Read mode, the bit line, which has a signicant amount of parasitic capacitance, is precharged to a logic one. The pass transistor is then enabled by driving the word line High. If the stored value is a zero, the line is then discharged to ground. Reliable reading of the memory cell is achieved by reducing the word line High level during reading to a level that insures that the cell will not be disturbed.

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Quality Assurance and Reliability

Electrostatic Discharge
Electrostatic-discharge (ESD) protection for each pad is provided by circuitry that uses distributed transistors and/or diodes, represented by the circles in Figure 3. In older devices, these protection circuits are conventional diffused structures. In newer designs, Xilinx utilizes proprietary device structures which exhibit substantially enhanced ESD performance (see Table 4).
VCC ROUT Output

Latchup
Latchup is a condition in which parasitic bipolar transistors form a positive feedback loop (Figure 4), which quickly reaches current levels that permanently damage the device. Xilinx uses techniques based on doping levels and circuit placement to avoid this phenomenon. The beta of each parasitic transistor is minimized by increasing the base width. This is achieved with large physical spacings. The butting contacts effectively short the n+ and p+ regions for both wells, which makes the VBE of each parasitic very close to zero. This also makes the parasitic transistors very hard to forward bias. Finally, each well is surrounded by a dummy collector, which forces the VCE of each parasitic almost to zero and creates a structure in which the base width of each parasitic is large, thus making latchup extremely difcult to induce.
VCC

Ground VCC Pad

Input

RIN

Ground = Symbol for electrostatic discharge protection circuit

X3132

Pad

Figure 3: Input/Output Protection Circuity Table 4: ESD Performance of Xilinx Components

Circuit Human Body Machine

Family

Model Method 3015

>6,000v 1,5002,500v 4,500-7,000v 1,750-5,000v 4,000-8,000v 4,000-8,000v 4,000-6,000v 3,000-5,000v 2,000-4,000v 2,000-5,000v

Model EIAJ 20
500 900v 250325v 325-600v 700-800v 800-900v pend pend pend 250-300v pend

Charged Device Model CDM

X1825

XC1700D XC2000 XC3000A XC3100A XC4000 XC4000E XC4000E XC5200 XC7000 XC9000

>2,000v pend >2,000v >2,000v >1,000v >2,000v >2,000v >2,000v >2,000v >2,000v

Figure 4: SCR Model At elevated temperatures, 100 mA will not cause latchup. At room temperature, the FPGA can withstand more than 300 mA without latchup; the EPLD device can withstand more than 200 mA without latchup. However, to avoid metalmigration problems, continuous currents in excess of 10 mA are not recommended.

High Temperature Performance

Although Xilinx guarantees parts to perform only within the specications of the data sheet, extensive high temperature life testing has been done at 145C with excellent results.

Whenever the voltage on a pad approaches a dangerous level, current ows through the protective structures to or from a power supply rail (VCC or ground). In addition, the capacitances in these structures integrate the pulse to provide sufcient time for the protection networks to clamp the input, avoiding damage to the circuit being protected. Geometries and doping levels are chosen to provide ESD protection on all pads for both positive and negative voltages.

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Technical Support and Services

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Technical Support Table of Contents

Technical Support And Services

WebLINX Web Site (www.xilinx.com) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical and Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . File Access and Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hotline Telephone Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . All regions of the world (WebLINX): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AppLINX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XCell Newsletter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Logic Training Courses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What You Will Learn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start or Complete Your Design During the Training Course. . . . . . . . . . . . . . . . . . . . . . . . Reduce Your Learning Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Make Fewer Design Iterations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Get to Market Faster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lower Production Costs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increase Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time and Cost Savings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Course Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hands-On Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instructors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Course Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FPGA Tools Course Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M1 Update Course . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M1 Update Course Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Seminar (Esperan-Based) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Future Foundation and Synopsys Courses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Training Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Headquarters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . North American Distributor Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . International Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Site Courses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Site Courses Provide Additional Benefits: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Travel Costs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Courses Tailored To Your Needs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Costs: North America . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Costs: International . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Included in class fees:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tuition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Money-back Guarantee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enrollment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cancellations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12-2 12-2 12-2 12-2 12-3 12-3 12-3 12-3 12-3 12-4 12-4 12-4 12-4 12-4 12-4 12-4 12-4 12-4 12-4 12-4 12-4 12-4 12-4 12-4 12-5 12-5 12-5 12-5 12-6 12-6 12-6 12-6 12-6 12-6 12-6 12-6 12-6 12-6 12-6 12-6 12-6 12-6 12-7 12-7 12-7

Technical Support And Services

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A complete and uniquely accessible offering of worldwide technical support services is available to Xilinx users. Xilinx Field Application Engineers, located at sales ofces and technical support centers worldwide, provide local engineering support, including design evaluation of new projects, close consultation throughout the design process, special training assignments, and new product presentations. Because their role as advisors and troubleshooters keeps them constantly on the go, they are best used not for general questions, but for more targeted queries such as those related to architectural recommendations. The worldwide network of Xilinx sales representatives and distributors also provide local technical support for Xilinx users. Technical and applications queries can be directed to WebLINX, the Xilinx world wide web site, or the telephone hotlines. Xilinx provides 24-hour access to the expert Answers database, product and applications information, and a variety of les and utilities via WebLINX and the le download areas. Hotline telephone support provides access to permanent teams of expert Application Engineers located in the United States, United Kingdom, France, Germany, and Japan. These engineers can handle

problems and answer questions right on the spot, and are contributors to, as well as, users of the Answers database, accessible at WebLINX (www.xilinx.com). Many different publications assist users in completing designs quickly and efciently, including technical manuals, data sheets, application notes, the AppLINX CD-ROM (a regularly-updated collection of the latest application notes and design hints), and the quarterly XCell newsletter. Most of these publications are available on the WebLINX web site. For more in-depth support and instruction, a dedicated training organization conducts technical training classes worldwide. Courses geared for both novice and experienced users are available. The following Technical Support Services are discussed in more detail in this chapter: WebLINX World Wide Web site Internet File Download area Hotline telephone support Technical literature Training Courses

WebLINX - The Homepage for Programmable Logic (www.xilinx.com)

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WebLINX Web Site (www.xilinx.com)

WebLINX, the Xilinx World Wide Web site, provides instant access to the latest information, ranging from Product Overviews, Application Notes, and Data Sheets to investor information and employment opportunities. Designed to provide users with quick, easy, and intuitive access to the desired information. WebLINX holds a wealth of Xilinx information, readily available at your ngertips. Whats more, SmartSearch, our industry-wide search engine, is the denitive resource for all Programmable Logic information on the web. SmartSearch searches over 50 different web sites rich in Programmable Logic content, providing central access to a vast amount of data. SmartSearch Agents will watch the Web for you and inform you via e-mail when new or updated information is added to any of the sites served by SmartSearch. SmartSearch Agents allow you to stay up-to-date in the rapidly changing world of Programmable Logic. New information is constantly being added to the Xilinx site. The following is a list of some of the technical information now available on WebLINX (as of July, 1997): Over 60 Application Notes organized by system type (e.g., PCI, DSP , and PCMCIA), function (e.g., memory functions, arithmetic functions, and busses), component product family, and application. Complete and detailed data sheets on all Xilinx products. Over 1900 records in our Technical Answers database that contains answers to frequently-asked technical questions. Xilinx Product Change Notices and Xilinx Customer Updates Access to XCell, our quarterly journal for programmable logic users. Software updates and patches. Links to technical Xilinx presentations via Marshall Electronics NetSeminarTM archives.

Expert Journals that provide ow-specic collections of information including FAQs, Tips, and Hot Topics. Documents and applications material. Information about Worldwide Hotline access and training course availability.

File Access and Transfer

Through the le download areas, users have on-line access to a variety of useful les, including user manuals, automated tutorials, design examples, and utilities. Data les can be exchanged with Application Engineers through a secure area of the le download area.

Hotline Telephone Support

A network of Technical Support Hotlines provides Xilinx users with direct telephone access to Xilinx Application Engineers dedicated to providing resolutions to problems that may arise during the design process. Xilinx Application Engineers use many of the same resources and databases that are now directly available to users via the WebLINX web site. Technical questions also can be submitted via fax or E-mail.

All regions of the world (WebLINX):

web site: www.xilinx.com

North American support:

Hours: Hotline: Fax: E-mail: Mon. - Wed., Fri. 6:30 AM - 5:00 PM Thur. 6:30 AM - 4:00 PM Pacic Time 800-255-7778 or 408-879-5199 408-879-4442 [email protected]

United Kingdom support:

Hours: Mon. - Thur. 9:00 AM - 12:00 PM, 1:00 PM - 5:30 PM Fri. 9:00 AM - 12:00 PM, 1:00 PM - 3:30 PM (44) 1932-820821 (44) 1932-828522 [email protected]

Technical and Applications Information

The Answers area of WebLINX provides access to technical and applications information that assists design engineers in solving problems. The Answers area is accessible from the Xilinx home page either through the Answers icon or by selecting the Support topic. Further, this collection of technical and applications information is immediately accessible through the button bar that is located at the bottom of every Web page. The Answers area provides access to a variety of technical and applications resources including: Over 1900 technical solutions and frequently asked questions. The File Download Area for access to patches, utilities, and updates. Hotline: Fax: E-mail:

France support:
Hours: Hotline: Fax: E-mail: Mon. - Fri. 9:30 AM - 12:30 PM, 2:00 PM - 5:30 PM (33) 1-3463-0100 (33) 1-3463-0959 [email protected]

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Germany support:
Hours: Mon. - Thur. 8:00 AM - 12:00 PM, 1:00PM - 5:00 PM Fri. 8:00 AM - 12:00 PM, 1:00 PM - 3:00 PM (49) 89-93088-130 (49) 89-93088-188 [email protected]

Hotline: Fax: E-mail:

Japan support:
Hours: Mon., Tue., Thur., Fri. 9:00 AM - 5:00 PM Wed. 9:00 AM - 4:00 PM (81) 3-3297-9163 (81) 3-3297-0067 [email protected]

Hotline: Fax: E-mail:

XCell Newsletter
XCell, the quarterly journal for Xilinx programmable logic users, is dedicated to supplying up-to-date information for system designers. A typical issue includes descriptions of new products, updates on component and software availability and revision levels, application ideas, design hints and techniques, and answers to frequently-asked questions. To add your name to the XCell subscription list, please send your name, company afliation, and mailing address to XCell editor, via FAX at 408-879-4676.

Korea support:
Hotline: Fax: E-mail: (82) 2-761-4277 (82) 2-761-4278 [email protected]

Hong Kong support:

Hotline: Fax: E-mail: (85) 2-2424-5200 (85) 2-2424-7159 [email protected]

Programmable Logic Training Courses

All users of Xilinx products should attend one of our training courses. Attending a Xilinx training course is one of the fastest and most efcient ways to learn how to design with FPGA devices from Xilinx. Hands-on expert instruction with the latest information and software will allow you to implement your own designs in less time with more effective use of the devices. Not only design engineers, but also test engineers, component engineers, CAD engineers, technicians, and engineering managers may want to attend the course in order to understand the Xilinx products. A variety of courses are offered to meet your specic needs. Courses are held regularly in centers around the world, and can even be brought to your own facility.

Technical Literature
Xilinx offers many different publications to assist users in completing designs quickly and efciently. These include technical manuals, Data Books, data sheets, application notes, the AppLINX CD, the XCell newsletter, and The Answers Database. Most of these publications are available on-line at the WebLINX web site. As part of the development system products, Xilinx provides manuals and supporting documents for the development system tools, libraries, CAE tool interfaces, and related software tools. Many of these manuals are available on the CD that holds the software as well as in hardcopy format. On-line help facilities also are an integral part of the development system products.

What You Will Learn

Not only will you learn about our products, but we will recommend the best ways to use the software based on our years of experience with thousands of designs. You will learn how to efciently enter, implement, and verify your design. You can use the Xilinx automatic mode, or take a power-user approach and guide the automatic tools to the best implementation of your design.

AppLINX
AppLINX is a collection of current application notes and other new technical documentation provided on a CD-ROM for easy reference by the design engineer. All the material on the CD is provided in Adobe Acrobat format for easy viewing and printing. The AppLINX CD is updated regularly as new material becomes available.

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Prerequisites
Students need only have a background in digital logic design. Basic familiarity with the PC or workstation is helpful, but not required. It will benet you to learn your design entry tool of choice before attending the Xilinx course. If you would like to prepare for the training course to maximize your learning, you should complete the tutorials available in the development system.

tenance and repair costs, and improved customer satisfaction.

Time and Cost Savings

Attending a Xilinx training course is an investment that will pay for itself with the rst Xilinx design that you begin. The courses are fast-paced, each providing as much information as possible in the short time available. Hands-on experiences throughout the courses make sure that the information is retained and applied to practical applications. Just as Xilinx products reduce your development time, attending a training course can reduce your design time. The person attending the course will be an in-house expert who can be utilized by other members of your company. You can reduce your travel costs by attending a course scheduled in your area, or having the class brought right to your facility. The tuition pays for the course notes and expert, in-person instruction, which can be priceless when trying to meet a schedule.

Benets
Start or Complete Your Design During the Training Course
Bring your design to the course and consult with the instructor. Course size is limited to allow more interaction. You can spend extra time getting your design completed before returning home. Call to see if your design entry tool will be available at the course.

Reduce Your Learning Time

Extensive Xilinx documentation and tutorials provide the information you need to complete your design. But attending the training course for focused, interactive learning is faster than a question-and-answer approach on your own. Instead of interruptions and piecemeal self-education, you will quickly become your company's expert in Xilinx designs.

Course Descriptions
Hands-On Experience
Each course includes over two hours each day for handson labs. There is at least one computer for every two people in the course.

Platforms
PC systems using Win95 and NT operational systems.

Make Fewer Design Iterations

By learning the proper approach, you will save time and expense in prototyping and debugging designs. However, if you do need to make changes to your design, you will learn how to do this quickly and efciently.

Instructors
Xilinx training courses have been successfully held worldwide for over seven years. The instructors are Xilinx experts who are skilled at passing that knowledge on to fellow engineers. A dedicated Education organization at Xilinx works closely with the Applications and Engineering groups to keep the courses up-to-date with the latest improvements to Xilinx and third-party tools.

Get to Market Faster

Getting your product to market faster is probably one of the key reasons you are using Xilinx products. Studies have shown that time-to-market often has a greater effect on prots than development costs. Training will allow you to get your product to market on schedule, allowing your company to reap the rewards that follow.

Course Materials
All course materials are supplied by Xilinx. The course notes are bound for easy use and include additional reference material beyond what is covered in the course. Most courses include a full lunch, with morning and afternoon snacks. Let the education registrar know if you have any special dietary needs when registering for a course.

Lower Production Costs

By learning how to use the device effectively, you may be able to get more logic into a smaller device, or operate at a higher speed. As a result, you may be able to save on the cost of the device itself, and the surrounding logic on your board.

Product Coverage
Xilinx courses cover the latest released versions of our devices and development systems. New products are added to the class as they become available. If you have any questions on coverage of a particular product, please call Xilinx Customer Education.

Increase Quality
Effective verication techniques will prove the quality of your Xilinx-based design. Higher quality leads to less main-

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FPGA Tools Course Outline

This Xilinx training course is two and one-half days in length. All North American training sites, and most international locations, teach the same course. This course is heavily focused on the labs, which feature Xilinx Foundation Software. Introduction Basic XC4000X Architecture CPLD Design - 9500 Architecture/Features Design Entry - Design Flow - Xilinx Libraries/ LogiBLOX Components Design Manager - Implementing the design - Design Flow Simulation - Xilinx Simulation/Verication - LogiBLOX Simulation Conguration - Options/Methods/Debugging FPGA Combinatorial Logic Resources Designing for FPGA Registers Designing for FPGA Memory Designing for FPGA I/O Low Cost FPGA Families Constraining the Design - Location/Implementation - Timing Flow Engine Overview - New Terminology Custom Options - MAP, PAR, and Timing Report Options - Flow Options - Advanced Operations

M1 Update Course Outline

Introduction M1 Release - Changes - Future Updates FPGA Architecture - Features - Size - Power Tool Usage - Design Flow - Options - Software Strategies New Features - Checkpoint Verication - Constraints LogiBLOX LogiCORE/AllianceCORE Conversion Guidelines

VHDL Seminar (Esperan-Based)

This one day seminar consists of one-half day of presentation and one-half day of hands-on training using the Foundation tools. The seminar is designed to be an introduction, providing the students with enough training so that they are conversant with the language and can write simple VHDL functions. This course is presented on an as needed basis. Please contact your local Xilinx or distributor sales ofce for additional course and schedule information. The one-day VHDL seminar includes the following topics: VHDL Application Introduction VHDL Language Introduction Signals and Data Types VHDL Operators Concurrent and Sequential Statements Writing VHDL for Synthesis The lab exercises presented during the one-day VHDL seminar consist of: Familiarization with Xilinx Foundation Series Synthesis Tool Familiarization with the Decoder Design Writing Your First VHDL Code Adding the Alarm Signal Adding a Seven Segment Display Driver The Alarm Register A Counter The Alarm Clock Controller (a State Machine)

M1 Update Course
The one day course is focused on the latest released products from Xilinx. An update course is available describing the new features of the M1 release. The course will be offered for a limited time at regional sites, or can be brought to your facility. Those customers who have already attended a Xilinx course or have experience using Xilinx products should consider attending the one-day M1 Update training session. These sessions will be most useful if you have the latest software. Browse the Xilinx Web site for scheduled courses, or contact the Xilinx Education Registrar to hold an Update training session at your site.

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Future Foundation and Synopsys Courses

With the release of the XACTstep version M1 software, the Xilinx education organization is poised to provide additional training courses to our customers. A Foundation schematic-entry course and a Synopsys synthesis course will be offered in the winter 1997 time period. Customers should call the Xilinx Education Registrar for up-to-date course schedules and locations.

On-Site Courses Provide Additional Benets:

No Travel Costs
On-site Xilinx training courses eliminate travel time and expenses: No airfare No hotel bills No car rental

Training Locations
Xilinx Headquarters
Courses are held regularly at Xilinx headquarters in San Jose, California. During the class, you may elect to meet one-on-one with Xilinx Applications engineers to discuss specic issues not covered in the course. Topics may include using a specic third-party tool, optimizing your particular design, or more advanced issues beyond the coverage of the course.

Courses Tailored To Your Needs

On-site courses can be tailored to meet the specic needs of your company: Convenient course time and location Projects of a proprietary nature can be discussed openly Students can use their own equipment and begin an actual design right in course

North American Distributor Locations

Xilinx distributors sponsor training courses jointly with Xilinx, using the same material as the headquarters courses. Since the distributor sponsors the course, the tuition cost is often reduced for customers of the sponsoring distributor. Check with the distributor when registering. Locations include over seventy cities across North America. Contact your local distributor or Xilinx headquarters for information on courses in your area.

Costs: North America

Prices start at $4,500 for a minimum course size of six students. (Prices are subject to change without notice.)

Costs: International
Prices vary; contact your local Xilinx sales representative. (prices are subject to change without notice.) A Xilinx-certied instructor Training materials for each student PC for every two students (or if you prefer, the training labs can be performed on your PCs or workstations)

Included in class fees:

-

International Locations
Xilinx courses are held throughout Europe, Japan, Asia, India, Israel, South Africa, South America, and other international locations. Courses vary in length and tuition, but are based on the same material used in North America. Contact your local Xilinx sales ofce or representative for information about courses in your area.

Registration
Tuition
Course tuition in North America is $1,000 per student for the two and one-half day courses at Xilinx headquarters. The distributor-sponsored courses are offered at a reduced rate of $495 for customers of the sponsoring distributor. Check with the distributor when registering. On-site courses start at $4,500 per class, and vary according to the course and the number of students. For specic pricing of on-site courses, call the Xilinx Education Registrar or your local sales ofce. For international locations, call the local registrar for pricing. (Prices and course schedules are subject to change without notice.)

On-Site Courses
Xilinx can bring the training course to your own facility for the greatest convenience to your company. To schedule a training course at your facility and determine pricing, call the Xilinx sales ofce nearest you, or your local Xilinx sales representative. On-site training courses are popular, so the more advanced notice we have, the better our ability to schedule your course exactly when you want it.

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Location Course Title Xilinx Headquarters FPGA Tools M1 Update Xilinx Sales Office VHDL Course North America Distributor Locations FPGA Tools M1 Update

Tuition $1,000 $99 $99 $495 $99

International

On-Site International Locations On-Site

Starts at $4,500 Varies Varies

Benets Can meet with applications engineers Courses held frequently All class types available One-day introduction to VHDL Courses held frequently; locally available Lower cost for Distributors customers One-day focus on M1 software release Convenience; focus on specic issues Offered in over 21 countries Native language Convenience Can focus on specic issues

Money-back Guarantee
We are so condent you will be satised with the benets of a Xilinx training course that we offer the following guarantee: Full refund of the course cost if you are not completely satised.

Enrollments will be acknowledged with a conrmation letter. We encourage you to sign up early, as courses may ll up quickly.

Cancellations
Course tuition is fully refundable up to two weeks before the scheduled course starts. Cancellations within two weeks of the scheduled course will incur a 25% cancellation fee. Cancellations within one week of the scheduled course date may only be applied toward a future course date. Rescheduling is allowed until three working days before the start of class. Student substitutions may be made at any time. Xilinx Customer Education Registrar Customer Education Registrar Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: (408) 879-5090 Fax: (408) 879-4676, - attn: Customer Education Registrar E-mail: [email protected] Register on-line: http://www.xilinx.com

Enrollment
To enroll in a Xilinx training course, several enrollment methods are available. The fastest and easiest enrollment mechanism is the on-line registration via the Xilinx web site at www.xilinx.com. An alternate method for enrollment is to contact the registrar at the course location, or for Xilinx headquarters courses, call (408) 879-5090 or FAX (408) 879-4676 the Education Registrar for additional course information. Course size is limited, so early enrollment is recommended. Students are considered enrolled only after a check, money order, or purchase order for the course tuition has been received. Please mail your payment to the registrar of the location of your training class. For Xilinxsponsored courses, make checks/P.O. payable to Xilinx, Inc.

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Product Technical Information

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Product Technical Information Table of Contents

Product Technical Information

Product Technical Information Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 XC3000, XC4000, and XC5200: A Technical Overview for the First-Time User . . . . . . . 13-5 Choosing a Xilinx Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 I/O Characteristics of the XL FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 XC4000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 XC3000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 FPGA Configuration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 Configuring Mixed FPGA Daisy Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39 Configuration Issues: Power-up, Volatility, Security, Battery Back-up . . . . . . . . . . . . . 13-41 Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-45 Metastable Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-47 Set-up and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-50 Overshoot and Undershoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-51 Boundary Scan in XC4000 and XC5200 Series Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 13-52

APPLICATION NOTE
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APPLICATION NOTE

XC3000, XC4000, and XC5200: A Technical Overview for the First-Time User
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XAPP 097 September 12, 1997 (Version 1.1)

Application Note by Peter Alfke There are eight such global low-skew clock lines in XC4000, four in XC5200, and two in XC3000 devices.

Introduction
In the XC3000, XC4000, and XC5200 device families, Xilinx offers three evolutionary and compatible generations of Field Programmable Gate Arrays (FPGAs). Here is a short description of their common features. Every Xilinx FPGA performs the function of a custom LSI circuit, such as a gate array, but the FPGA is user-programmable and even reprogrammable in the system. Xilinx sells standard off-the-shelf devices in three families, and many different sizes, speeds, operating-temperature ranges, and packages. The user selects the appropriate device and then converts the schematic or High-Level-Language description into a conguration data le, using the Xilinx development system software running on a PC or workstation, and then loads this le into the Xilinx FPGA. This overview describes two aspects of Xilinx FPGAs: what logic resources are available to the user how the devices are programmed.

Special Features
All devices can implement internal bidirectional busses. The XC4000- and XC5200-family devices have dedicated fast carry circuits that improve the efciency and speed of adders, subtractors, comparators, accumulators and synchronous counters. These families also support boundary scan on every pin. XC4000-series devices can use any of their logic-block look-up tables as distributed RAM, with synchronous write and dual-port options. This makes FIFOs, shift registers and DSP distributed multipliers very fast and efcient.

Inputs/Outputs
All device pins are available as bidirectional user l/O, with the exception of the supply connections and three dedicated conguration pins. All inputs and outputs within each family have identical electrical characteristics, but output current capability varies among families. The outputs on XC3000 and XC5200 devices always swing rail-to-rail. XC4000E/EX outputs have a global choice between TTL = totem pole or CMOS = rail-to-rail output swing. The original families operate from a 5-V supply, but have added 3.3-V variants. These 3.3-V devices, designated by an L in their product name, have rail-to-rail outputs. Inputs of all 5-V devices can be globally congured for either TTL-like input thresholds or mid-rail CMOS thresholds. All 3.3-V devices have CMOS input thresholds (50% of Vcc). All inputs have hysteresis (Schmitt-trigger action) of 100 to 200 mV. XC4000XL inputs are unconditionally 5-V tolerant, even while their supply voltage is as low as 0 V. This eliminates all power-supply sequencing problems.

User Logic
Different in structure from traditional logic circuits, or PALs, EPLDs and even gate arrays, the Xilinx FPGAs implement combinatorial logic in small look-up tables (16 x 1 ROMs); each such table either feeds the D-input of a ip-op or drives other logic or I/O. Each FPGA contains a matrix of identical logic blocks, usually square, from 8 x 8 in the XC3020 to 56 x 56 in the XC4085XL. Metal lines of various lengths run horizontally and vertically in-between these logic blocks, selectively interconnecting them or connecting them to the input/output blocks.

Logic Blocks
This modular architecture is rich in registers and powerful function generators that can implement any function of up to ve variables. For wider inputs, function generators are easily concatenated. Generous on-chip buffering makes logic block delays insensitive to loading by the interconnect structure, but interconnect delays are layout-dependent and must be analyzed if they are performance-critical.

Global Reset
All Xilinx FPGAs have a global asynchronous reset input affecting all device ip-ops. In the XC4000- and XC5200family devices, any pin can be congured as a reset input; in XC3000-families, RESET is a dedicated pin.

Clocks
Clock lines are well-buffered and can drive all ip-ops with < 2 ns skew from chip corner to corner, even throughout the biggest device. The user need not worry about clock loading or clock-delay balancing, or about hold-time issues on the chip, if the designated global clock lines are used.

Power Consumption
Since all Xilinx FPGAs use CMOS-SRAM technology, their quiescent or stand-by power consumption is very low, microwatts for XC3000 devices, max 25 mW to 75 mW for the other 5-V families. The operational power consumption is totally dynamic, proportional to the transition frequency of 13-5

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XC3000, XC4000, and XC5200: A Technical Overview for the First-Time User

inputs, outputs, and internal nodes. Typical power consumption is between 100 mW and 5 W, depending on device size, clock rate, and the internal logic structure. XC3000-family devices can be powered-down, and in this state their conguration can be maintained by a >2.3 V battery. Current consumption is only a few microamps. The device 3-states all outputs, ignores all inputs, and resets its ip-ops, but retains its conguration. All devices monitor VCC continuously and shut down when VCC drops to 3 V (2 V for 3.3-V devices). The device then 3states all outputs and prepares for reconguration.

Power-up Sequence
Upon power-up, the device waits for VCC to reach an acceptable level, then clears the conguration memory, holds all internal ip-ops reset, and 3-states the outputs but activates their weak pull-up resistors. The device then initiates conguration, either as a master, (clocking a serial PROM to receive the serial bitstream or addressing a byteparallel EPROM), or as a slave, (accepting a clock and bitserial or 8-bit parallel data from an external source).

Bit-Serial Conguration
The Xilinx serial PROM is the simplest way to congure the FPGA, using only three or four device pins. Typical conguration time is around one microsecond per bit, but this can be reduced by a factor of eight. Conguration thus takes from a few milliseconds to a several hundred milliseconds. Xilinx serial PROMs come in sizes from 18,144 to 262,144 bits, and megabit versions are in development. Serial PROMs can also be daisy-chained to store a longer bitstream.

Programming or Conguring
Design Entry
A design usually starts as a schematic, drawn with one of the popular CAE tools, or as a High-Level Language textual description. Most CAE tools have an interface to the Xilinx development system, running on PCs or workstations.

Design Implementation
After schematic- or HLL design entry, the logic is automatically converted to a Xilinx Netlist Format (XNF) or EDIF. The Xilinx software rst partitions the design into logic blocks, then nds a near-optimal placement for each block, and nally selects the interconnect routing. This process of partitioning the logic, placing it on the chip, and routing the interconnects runs automatically, but the user may also affect the outcome by imposing specic timing constraints, or selectively editing critical portions of the design, using the graphic design editor. The user thus has a wide range of choices between a fully automatic implementation and detailed involvement in the layout process. Once the design is complete, a detailed timing report is generated and a serial bitstream can be downloaded into the FPGA, into a PROM programmer, or made available as a computer le.

Byte-Parallel Conguration
Xilinx FPGA devices can also be congured with byte-wide data, either from an industry-standard PROM or from a microprocessor. The FPGA drives the PROM addresses directly, or it handshakes with the microprocessor like a typical peripheral. The byte-wide data is immediately converted into an internal serial bitstream, clocked by the internal Conguration Clock (CCLK). Parallel conguration modes are, therefore, not faster than serial modes. XC5200 devices, however, can also be congured in Express mode, with byte-wide data at 10 MHz. The largest device, XC5215, can thus be congured in only 3 ms.

Reconguration
The user can recongure the device at any time by pulling the PROGRAM pin Low, to initiate a new conguration sequence. During this process, outputs not used for conguration are 3-stated. Partial reconguration is not possible. For high-volume applications, Xilinx offers lower-cost, xedprogrammed HardWire versions of these FPGAs.

Conguring the FPGA

The user then exercises one of several options to load this le into the Xilinx FPGA device, where it is stored in latches, arranged to resemble one long shift register. The data content of these latches customizes the FPGA to perform the intended digital function. The number of conguration bits varies with device type, from 14,819 bits for the smallest device (XC3020) to 1,924,992 bits for the largest device presently available (XC4085XL). Multiple FPGA devices can be daisy-chained and congured with a common concatenated bitstream. Device utilization does not change the number of conguration bits. Inside the device, these conguration bits control or dene the combinatorial circuitry, ip-ops, interconnect structure, and the I/O buffers, as well as their pull-up or pull-down resistors, input threshold and output slew rate.

Readback of Conguration Data

After the device has been programmed, the content of the conguration "shift register" can be read back serially, without interfering with device operation. XC4000- and XC5200-family devices include a synchronized simultaneous transfer of all user-register information into the conguration registers.

Quality and Reliability

Since 1985, Xilinx has shipped over 70 million FPGA devices. Industry-leading quality and reliability (ESD protection, AQL and FIT) and aggressive price reductions have undoubtedly contributed to this success. XAPP 097 September 12, 1997 (Version 1.1)

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Choosing a Xilinx Product Family

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XAPP 100 November 10, 1997 (Version 1.2) Summary

Application Note by Peter Alfke

This Application Note describes the various Xilinx product families. Differences between the families are highlighted. The focus of the discussion is how to choose the appropriate family for a particular application. Xilinx Families XC3000, XC4000, XC5000, XC6000, XC9000

Table of Contents
SRAM-Based FPGAs FLASH-Based CPLDs Selecting the Appropriate Xilinx Family

SRAM-Based FPGAs
Xilinx SRAM-based FPGAs fall into two distinct categories. All are recongurable and can be programmed in-system; only the XC6200 family can be partially recongured and offers a built-in microprocessor interface. The two categories of devices are separately described below.

Introduction
Xilinx offers Field-Programmable Logic circuits, mass-produced standard integrated circuits that the user can customize for the specic application. Xilinx products offer the following advantages: High integration (less space, lower power, higher reliability, lower cost) than solutions based on existing standard devices like MSI and PALs. No non-recurring engineering charges and associated risk, typically required for mask-programmed gate array solutions. Fast design time and easy design modication, important for early time-to-market. Designs can be upgraded in the eld for added functionality.

SRAM-Based FPGAs (XC3000, XC3100, XC4000, XC5200)

These families represent an ongoing evolution of the original Xilinx FPGA architecture, characterized by structural exibility and an abundance of ip-ops. Logic is implemented in look-up tables, and is interconnected by a hierarchy of metal lines controlled by pass transistors. Attractive systems features include on-chip bidirectional busses and individual output 3-state and slew-rate control, common reset for all ip-ops, and multiple global low-skew clock networks. The conguration can be loaded while the devices are connected into a system, and can be changed an unlimited number of times by reloading the bitstream, the series of bits used to program the device. Conguration must be reloaded whenever Vcc is re-applied. Reconguration takes 20 to 200 ms, during which time all outputs are inactive. Static power consumption is very low, down to microwatts for some of the families. Dynamic power consumption is proportional to the clock frequency, and depends on the logic activity inside the device and on the outputs. The description SRAM-based refers primarily to the standard high-volume manufacturing process, and secondarily to the fact that conguration data is stored in latches. Different from typical SRAMs, these latches use low-impedance active pull-up and pull-down transistors. An on-chip voltage monitor 3-states the outputs and initiates reconguration when Vcc drops signicantly (to 3.2 V in a 5V system).

Some potential users might be confused by the wide diversity of Xilinx product offerings. This application note provides a broad overview from the users perspective. Xilinx offers programmable logic circuits in two distinctly different technologies. SRAM-based FPGAs, the original Xilinx offering, now encompassing the XC3000, XC4000, XC5200, and XC6200 series and their sub-families, like the XC3000A, XC3000L, XC3100A, XC4000E, XC4000EX, and XC4000XL. Flash-based complex PLDs, the XC9500 family.

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These FPGAs are available in different sizes and many different packages. Usually each device type is available in many package types. Any package can accommodate different sized devices with compatible pinouts, so the user can migrate to a larger or smaller device without changing the PC-board layout.

Overview of SRAM-Based FPGA Families

XC2000: Soon to be obsoleted, do not use for new designs. The XC3000 or XC5200 FPGA families or the XC9500 CPLD family, may be an alternative. XC2000L: 3.3V version of XC2000; soon to be obsoleted, do not use for new designs. Use the XC3000L instead. XC3000: Superseded Dont use this venerable family for new designs, since it has been superseded by the improved, but fully backwards compatible, XC3000A family. XC3000A: Newest version of the popular XC3000 family Five device types cover a complexity range from 1,300 to 7,500 gates, with 256 to 928 ip-ops. Logic is implemented in 4-input look-up tables; two tables can be combined to implement any logic function of ve variables with only one combinatorial delay of 4 or 5 ns. Flip-op toggle rate is over 110 MHz. Global choice of input thresholds (1.2 V or 2.5V), output slew-rate control, and an on-chip crystal oscillator circuit are attractive system features. Use for medium-speed, medium-complexity applications. Accept lack of dedicated carry circuits, resulting in less efcient and slower arithmetic and counters than in XC4000E families. No on-chip RAM; data storage is thus limited to the available 256 to 928 ip ops.

XC3100A devices are functionally and bitstream identical with the XC3000A, and are available in the same packages with the same pinouts. The only difference is the higher speed of the XC3100A, with a look-up table delay of 1.5 to 4 ns, and the slightly higher standby current of 8 to 14 mA. One additional high-end family member, the XC3195A, can implement up to 9,000 gates and 1,320 ip-ops. Use for high performance design with system clock rates up to 100 MHz. Accept lack of dedicated carry circuits, resulting in less efcient and possibly slower arithmetic and counters than in XC4000E. No on-chip RAM; data storage is thus limited to the available 256 to 1,320 ip-ops.

XC3100L: 3.3V version of XC3100A Use for 3.3V applications. Accept signicantly slower speed at 3.3V, compared to XC3100A at 5V, as well as higher quiescent power and much higher powerdown current than XC3000L at 3.3V.

XC4000: Superseded Dont use this family for new designs, since it has been superseded by the improved, but fully backwards compatible XC4000E family. XC4000A: Superseded Dont use this family for new designs, since it has been superseded by the improved, faster, less expensive, and pinout-compatible but not bitstream-compatible XC4000E family. XC4000E: Enhanced superset of the XC4000 family The XC4000E family is recommended for new designs. The ten devices in this family stretch from 2,000 to 25,000 gate complexity. The emphasis is on systems features and speed. The function generators are more versatile than in the XC3000-Series parts, and there is a dedicated carry network to speed up arithmetic and counters and make them more efcient. Most importantly, the function generators can be used as user RAM with asynchronous or synchronous write addressing, even as dual-port RAMs. This capability makes register les, shift registers and especially FIFOs faster and much more efcient than in any other FPGA. Dedicated carry logic can speed up wide arithmetic and long counters. Use for general-purpose logic and data-path logic that can take advantage of internal busses and fast arithmetic carry logic. Use for on-chip distributed RAMs, e.g. >50-MHz FIFOs up to 64 deep, 32 bits wide. Accept lack of crystal oscillator circuitry and lack of Powerdown feature.

XC3000L: 3.3V version of XC3000A Use for battery-operated applications. Accept signicantly slower speed at 3.3V, compared to XC3000A at 5V.

XC3100: Superseded Dont use this family for new designs, since it has been superseded by the improved, but fully backwards compatible XC3100A family. XC3100A: Newest version of the popular high-speed XC3100 family

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XC4000EX: Larger version of the XC4000E family. Extension of the XC4000E family from 28k to 36k gates, with greatly increased routing resources, faster clocking options and more versatile output logic. Use for designs beyond 20,000 gate complexity.

Partially-Recongurable SRAM-Based FPGA with Bus Interface (XC6200)

This new ne-grained architecture is very different from the other Xilinx families. It offers partial and very fast recongurability, supported by an 8/16/32 bit wide microprocessor bus interface. This interface can directly write to and read from any internal cell, and can even treat part of the internal conguration as user RAM. Use for innovative recongurable-processor solutions, and for general purpose solutions where fast (re)conguration is an advantage, or for registerintensive, datapath-oriented, highly structured designs.

XC4000H: High I/O - count version of XC4000. Soon to be obsoleted, do not use for new designs. Consider XC5200 as a lower-cost alternative when internal RAM is not required.

XC4000XL: 3.3V FPGA Complete family stretching from 5000 gates to >100,000 gates. Basic features are identical to the XC4000E but with additional routing resources and 5V tolerant input, even when Vcc is <3.0V. Use for 3.3V designs.

FLASH-Based CPLDs (XC9500)

These devices are extensions of the popular PAL architecture, implementing logic as wide AND gates, ORed together, driving either a ip-op or an output directly. The simple logic structure makes these devices easy to understand, and results in both fast design compilation and short pin-to-pin delays. Wide input gating and fast system clock rates up to 150 MHz are attractive features for state machines and complex synchronous counters. The XC9500 in-system programmable family, based on FLASH technology, eliminates the need for a separate programmer. These new devices also offer boundary scan (JTAG) to simplify board testing.

XC5200: Low-cost FPGA New architecture optimized for low cost, good routability, and the ability to lock pinout while internal logic is being modied. Dedicated carry structure similar to XC4000, but no RAM. Four-input function generators avoid the XC3000 input constraints. IOBs are less rigidly coupled to the internal matrix of CLBs and interconnects, which greatly improves the exibility of pin-locked designs. IOBs have no ip-ops. The XC5200 family offers the lowest cost per gate of all Xilinx FPGAs, whenever RAM is not required. Performance is similar to XC3000A, but dedicated carry logic can speed up wide arithmetic and long counters. Use for medium-speed general-purpose logic, and for data-path logic that can take advantage of internal busses and fast arithmetic carry logic. Alternative to XC3000A at lower cost, and with additional benets, such as dedicated carry for arithmetic and counters, improved routing, and ability to cope with locked pinout. High I/O count. Package pinout compatible with XC4000. Accept lack of internal RAM and lack of crystal oscillator circuitry.

Overview of CPLD Families

XC7300: Superseded Do not use for new designs. Use XC9500 instead. XC9500: FLASH-Based CPLD Six devices cover the range from 36 to 288 macrocells. The new XC9500 family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. Delays are deterministic, and compile times are very short. Use for high-speed logic, short pin-to-pin delays, for state machines and exible address decoding, and as PAL replacement. Accept higher power consumption and fewer available ip-ops compared to SRAM FPGA.

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Selecting the Appropriate Xilinx Family

It is not always obvious which Xilinx family is the right choice for a particular application. To make a decision, start with the known data, the target application. Then address the following questions: What type of logic is used in the application? What special features are required? XC6200 achieves fast compilation through its ASIC-like small granularity, which requires no logic partitioning effort. 6. For lowest cost per gate, when on-chip RAM is not required: Use XC5200, XC3000A. 7. For pinout compatibility within and between families: Use XC4000E/EX/XL, XC5200. These families are carefully designed to t the same pinout in any given available package. This allows easy migration to different device sizes or families in the same package. The user can add logic or streamline the design or even use a less costly or faster family without any need to change the existing PC-board layout. 8. For Digital Signal Processing (multiply-accumulate) applications: Use XC4000E/EX/XL. The look-up-table architecture and the dedicated carry structure are very efcient for distributed arithmetic, a fast and effective way to implement xed-point multiplication in digital lters.

Type of Logic
All Xilinx devices are general-purpose. Any family can implement any type of logic. There are, however, some features that make certain families more appropriate than others. The following items should be interpreted as soft suggestions, not as absolute, unequivocal choices. 1. For shortest pin-to-pin delays and fastest ip-ops: Use XC9500, or, if fan-in is sufcient, XC3100A, XC4000E/ EX/XL. XC9500 CPLDs have a PAL-like AND/OR structure that is inherently very fast. XC3100 has extremely fast logic blocks, but the single-level fan-in is limited to ve. XC4000E/EX/XL have slower logic blocks, but a wider fanin of nine. XC4000EX/XL FPGAs offer a very fast pin-to-pin path using a fast buffer and a 2-input function generator in the IOB. 2. For fastest state machines: For encoded state machines, use XC9500. For one-hot state machines, use XC3100A, XC4000E/ EX/XL, XC5200. 3. For fast counters/adders/subtractors/accumulators/ comparators: Use XC4000E/EX/XL, XC5200 or XC9500 for wide functions. Use XC3100A for very fast, but short or simple counters. XC4000E/EX/XL and XC5200 have dedicated carry-logic that is most effective over the range of 8 to 32 bits. XC3100A achieves high speed for short word-length and simple operations (such as non-loadable counters) through its extremely fast logic blocks. 4. For I/O-intensive applications with a high ratio of I/O to gates: Use XC5200. 5. For shortest design compilation time: Use XC9500, or XC6200. XC9500 achieves fast compilation through the simplicity of its PAL-like architecture.

Special Features Required

The sixteen items below describe specic features and characteristics available only in the listed families. These are, therefore, hard selection criteria. 9. For on-chip RAM: Use XC4000E, XC4000EX, XC4000XL, or XC6200. XC4000E/EX/XL has many 16x1 or 32x1 RAMs with synchronous or asynchronous write and dual-port capability. XC6200 can implement an arbitrary portion of the conguration-memory space as user RAM. 10. For on-chip (bidirectional) bussing: Use XC3000A, XC3100A, XC4000XL, XC5200, XC9500. XC4000E, XC4000EX,

XC3000A, XC3100A, XC4000, and XC5200 families have horizontal Longlines that can be driven by internal 3-state drivers. XC9500 devices implement busses indirectly using the wired-AND capability in the switch matrix. 11. For on-chip crystal oscillator circuitry: Use XC3000A/L, XC3100A/L. The on-chip circuit is just a dedicated single-stage inverting amplier that can be congured between two dedicated pins. It is not recommended for designs requiring very low power consumption or crystal frequencies below 1 MHz.

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12. For very fast or partial reconguration, and for a dedicated microprocessor interface: Use XC6200. All other SRAM-based families must be completely recongured. 13. For non-volatile single-chip solutions: Use XC9500 or any HardWire device. The SRAM-based devices require an external conguration source, which may be contained in the microprocessors memory. XC3000A and XC3000L devices can be used with a battery-backed-up supply, thus eliminating the need for external conguration storage. 14. For lowest possible static power consumption at 5V: Use XC3000A and, to a lesser extent, XC5200, XC4000E, XC4000EX. For Icc down to a few microamps, use XC3000A/L in powerdown. The other families consume a few milliamps. Congurations for CMOS input thresholds on all inputs reduce supply current signicantly. 15. For avoiding pin-locking problems with routingintensive designs: Use XC9500, XC4000EX, XC4000XL, XC5200. XC9500 devices have special architectural features to enable pin locking. XC4000EX, XC4000XL, and XC5200 provide additional routing channels, called VersaRing, between the core logic and the I/O. 16. For Boundary-Scan support: Use XC4000E, XC4000EX, XC4000XL, XC5200, XC9500. 17. For rail-to-rail output voltage swing at 5V Vcc: Use XC3000A, XC3100A, XC4000XL, XC5200, XC6200. XC4000E, XC4000EX,

XC4000E/EX/XL can be congured with a global choice of either totem-pole or rail-to-rail outputs. 18. For 3.3V operation: Use XC3000L, XC4000L, XC4000XL. 19. For 5V operation Interfacing with 3.3V devices: Use XC9500 or XC4000E/EX. Any XC4000E/EX/XL totem-pole output drives 3.3V inputs safely, and the TTL-like input threshold can be driven from 3.3V logic. 20. For In-system programmability: Use all Xilinx families. 21. For PCl compatibility: Use XC4000E/EX/XL and XC9500. Target and Initiator designs are available for the XC4000E. 22. For Hi-Rel, military, or mil temperature-range applications: Use XC3000, XC3100A, XC4003A, XC4005, XC4010, XC4013. 23. For battery-operated applications requiring low stand-by current: Use XC3000A/L, XC4000E/EX, XC5200, XC6200. XC3000L devices have inherently very low static power consumption. XC3000A devices can use powerdown to ignore all input activity and tolerate Vcc down to 2.3V, while maintaining conguration. XC4000E/EX must be congured for CMOS input thresholds, and the user must shut down clock and logic activities externally. 24. For best protection against Illegal copying of a design (design security): Use XC9500 with security bit activated. Use XC3000A or XC3000L with powerdown battery-backup conguration.

(In XC4000/E/EX/XL, rail-to-rail is a user-option.) XC4000 and XC9500 have a totem-pole output structure with lower Voh.

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Further Information
For further information on any of the Xilinx products discussed in this application note, see the Xilinx WEBLINX at http://www.xilinx.com, or call your local sales ofce. Table 1: Selecting a Xilinx Family XC4000EX XC4000XL XC3000A XC3100A XC4000E XC3000L XC3100L XC4000L XC5200 XC6200 XC9500 X X X X X X X X X option X X X X X option X X X X X X X option X X X X X X option X X X X X X X X X X X X X X X X X X X

Feature 1. Shortest pin-to-pin 2. Fastest state machines 3. Fastest arithmetic counters 4. High I/O to gate ratio 5. Fastest compilation 6. Lowest cost, no RAM 7. Footprint compatible families 8. DSP (multiply/accumulate) 9. RAM 10. Bidirectional busses 11. Crystal oscillator 12. Fast/partial configuration 13. Non-volatile/single chip 14. Low power @ 5V 15. Tolerates pin-locking 16. Boundary scan 17. Full-swing 5V output 18. 3.3V operation 19. 5V out drives 3.3V 20. In-system programmable 21. PCI-compatible 22. Hi-rel, mil, mil-temp 23. Low standby current 24. Design security

X X X

X X X

X X

X X X

X X X X X X X X

X X

X X

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13-12

XAPP 100 November 10, 1997 (Version 1.2)

APPLICATION NOTE
1

I/O Characteristics of the XL FPGAs

1 13*

XAPP 088 November 24, 1997 (Version 1.0)

Application Note by PETER ALFKE and BOB CONN

Summary
Data sheets describe I/O parameters in digital terms, providing tested and guaranteed worst-case values. This application note describes I/O parameters in analog terms, giving the designer a better understanding of the circuit behavior. Such parameters are, however, not production-tested and are, therefore, not guaranteed.

Xilinx Families
XC4000XL, XC4000XV, and Spartan-XL

Inputs
Input threshold, the voltage where a 0 changes to a 1 and vice versa, is stable over temperature, but proportional to VCC: 37 to 38% of VCC for the falling threshold, 39 to 42% for the rising threshold. There is 50 mV to 150 mV of hysteresis, smallest at hot and high VCC, largest at cold and low VCC.

ant, and the user can ignore all interface precautions, and need not worry about power sequencing. Excellent ESD protection (up to several thousand volts) is achieved by means of a patented diode-transistor structure that connects to ground, and not to VCC. The structure behaves like a Zener diode; it becomes conductive at >6 V and diverts the charge or current directly to ground. It can handle current spikes of several hundred milliamps, but continuous current must be kept below 20 mA to avoid reliability problems caused by on-chip metal migration. See also the application note Supply-Voltage Migration, 5 V to 3.3 V, XAPP080, available at www.xilinx.com.

5-V Tolerant Inputs

Currently, many systems use a mixture of older 5-V devices and newer 3.3-V devices. This can pose a problem when a 5V logic High drives a 3.3-V input. See Figure 1. On most CMOS ICs each signal pin has a clamp diode to VCC, to protect the circuit against electrostatic discharge (ESD). This diode starts conducting when the pin is driven more than 0.7 V positive with respect to its VCC. In mixed-voltage systems, this diode presents a problem since it might conduct tens of milliamps whenever a 5-V logic High is connected to a 3.3 V input. In the XC4000XL/XV and SpartanXL devices, Xilinx has overcome this difculty by eliminating the clamp diode between the device pins and VCC. The pins can thus be driven as High as 5.5 V, irrespective of the actual supplyvoltage on the receiving input. These devices are, therefore, unconditionally 5-V tolerVCC = 5 V C M O S T T L 2.4 2.0 VIH 5 V Tolerance 3.8 VOH 2.4 2.0 3.8 VCC = 3.0 3.6 V T T L C M O S 3.5

PCI-Compliance
The XL-I/O is designed to be PCI compliant and also to be 5-V tolerant. 3.3-V PCI compliance requires a clamping diode to VCC. 5-V PCI compliance does not explicitly require such a diode, but requires passing the specied PCI overshoot test. 5-V tolerance does not permit such a diode. To satisfy these conicting requirements, an internal diode is added to each output, with its cathode connected to an internal VTT rail. See Figure 2.
VCC Output pull-up well-bias circuit Global VTT Bus

VOH

Output Drive Transistors

VIH

I/O Pad

5-V Device

3.3-V Device
VIL 0.4

5-V Device
VIL C M O S 1.0

In

Bipolar ESD Circuit

PCI Clamp Diode

Optional Bond Wire

0.8 VOL 0.4

0.8

T T L

X7167

VTT Pad

VTT Pin
X7168

Figure 2: Interface Levels

Figure 3: Simplied XL-I/O Structure

XAPP 088 November 24, 1997 (Version 1.0)

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I/O Characteristics of the XL FPGAs

In the PCI-compliant XC4000XLT devices, this rail is internally bonded to eight device pins which externally must be connected to the appropriate VCC supply (5 V or 3.3 V). In all other XL devices, the VTT rail is internally left unconnected, thus assuring 5-V tolerance.

Effect of Additional Capacitive Load

Transition Time
At the specied 50 pF external load, the rise time is 2.4 ns, and the fall time is 2.0 ns. For additional capacitive loads, add 60 ps/pF to the rise time, and 40 ps/pF to the fall time.

Outputs
Sink and Source Capability
The IBIS les describe the strength of the CMOS output drivers as black boxes, giving only voltage/current values without revealing proprietary circuit details. IBIS gives an unnecessarily large set of numbers, when most users just want to know the strength of the pull-down transistor (sink capability) and the pull-up transistor (source capability). Close to either rail, the outputs are resistive, i.e. voltage is proportional to current. Table 1 condenses the information and expresses it as output resistance in Ohm for a sink voltage less than 1 V above ground, and a source voltage less than 1 V below VCC. (Data based on SPICE simulation). Table 2: Sink and Source Capability Sink Source Resistance to Resistance to GND VCC 22.1 - 27.7 53.3 - 90.5 Ohm 14.4 - 18.8 48.0 - 58.7 Ohm 14.4 - 20.5 28.0 - 41.0 Ohm 8.0 - 12.0* 20.0 - 30.0* Ohm

Delay
Add 30 ps/pF to the rising-edge delay at 3.0 V. Add 23 ps/pF to the rising-edge delay at 3.6 V. Add 25 ps/pF to the falling-edge delay at any voltage. The values were derived from XC4028XL measurements using the fast output option, but the slew-rate limited output option behaves almost identically. These results are consistent with the IBIS-derived output impedance, since the delay increases with approximately one RC time constant, and the rise and fall times increase each with approximately two time constants. These are not guaranteed and tested parameters; they are established by measuring a few devices. Xilinx, therefore, suggests that the user add a 20% guardband (multiply by 1.20) when calculating additional delay due to capacitive load above the guaranteed test limit of 50 pF. For the same reason, subtract 20% (multiply by 0.80) when calculating the delay reduction due to a capacitive load that is less than 50 pF external. See Figure 4. When comparing Xilinx numbers to those from other vendors who use 35 pF as a standard load, reduce the Xilinx-specied delay by 0.4 ns. Reduce the Xilinx-specied rise time by 1.0 ns and the fall time by 0.6 ns, thus changing both to 1.4 ns. Example: For an external lumped capacitive load of 200 pF, the risingedge delay at 3.0 V increases by 1.2 150 30 = 5.4 ns over the guaranteed data sheet value. The rising-edge transition time increases by an amount of 1.2 150 pF 60 ps/pF = 10.8 ns over the 50-pF transition time of 2.4 ns. The rise time is thus 13.2 ns.
3 2 Delta Delay (ns) 1 2 Volts 3 4 5
X7166

Device Family XC4000E XC4000EX XC4000XL/XV Spartan-XL Optional on all XC4000XV*

* This per-pin option will also be available on all XC4000XL and Spartan-XL devices later in 1998.

200 180 160 140 120 mA 100 80 60 40 20 0

1 0 -1 -2

Figure 4: Output Voltage/ Current Characteristics (default for XC4000XL,

20

40

60 80 100 Capacitance (pF)

120

140
X7169

Figure 5: Additional Delay at Various Capactive Loads 13-14 XAPP 088 November 24, 1997 (Version 1.0)

APPLICATION NOTE
0

APPLICATION NOTE

XC4000 Series Technical Information

0 13*

XAPP 045 November 24, 1997 (Version 1.1) Summary

Application Note

This Application Note contains additional information that may be of use when designing with XC4000 Series devices. This information supplements the product descriptions and specications, and is provided for guidance only. Xilinx Family XC4000/XC4000E/XC4000EX/XC4000L

Introduction
This application note describes the electrical characteristics of the output drivers, their static output characteristics or I/V curves, the additional delay caused by capacitive loading, and the ground bounce created when many outputs switch simultaneously.

Voltage/Current Characteristics of XC4000-Family Outputs

Figures 1 and 2 show the output source and sink currents, both drawn as absolute values. Note that the XC4000E/EX families offer a conguration choice between an n-channel only, totem-pole like output structure that pulls a High output to a voltage level that is one threshold drop lower than VCC, and a conventional complementary output with a p-channel transistor pulling to the positive supply rail. When driving inputs that have a 1.4-V threshold, the lower VOH of the totem-pole (TTL) output offers faster speed and more symmetrical switching delays.
200 180 160 140 120 mA 100 80 60 40 20 0 1 2 IOH TTL CMOS IOL

These curves represent typical devices. Measurements were taken at nominal VCC, TA = 25C. These characteristics vary by manufacturing lot, and will be affected by future changes in minimum device geometries. These characteristics are not production-tested as part of the normal device test procedure; they can, therefore, not be guaranteed. Although these measurements show that the output sink and source capability far exceeds the guaranteed data sheet limits, continuous high-current operation beyond the data sheet limits can cause metal migration of the on-chip metal traces, permanently damaging the device. Output currents in excess of the data-sheet limits are, therefore, not recommended for continuous operation. These output characteristics can, however, be used to calculate or model output transient behavior, especially when driving transmission lines or large capacitive loads.

200 180 160 140 120 mA 100 80 60 40 20 3 4 5

X5291

IOL

IOH

Volts

Volts

5
X5292

Figure 1: Output Voltage/Current Characteristics for XC4000E

Figure 2: Output Voltage/Current Characteristics for XC4000XL

XAPP 045 November 24, 1997 (Version 1.1)

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XC4000 Series Technical Information

Additional Output Delays When Driving Capacitive Load

Xilinx Product Specications in chapter 4 give guaranteed worst-case output delays with a 50-pF load. The values below are based on actual measurements on a small number of mid-93 production XC4005-5, all in PQ208 packages, measured at room temperature and VCC = 5.5 V. Listed is the additional output delay, measured crossing 1.5 V, relative to the delays specied in this Data Book. These parameters are not part of the normal production test ow, and can, therefore, not be guaranteed. Table 1: Increase in Output Delay When Driving Light Capacitive Loads (<150 pF) High-to-Low Slew Mode Slow Fast 10 -1.6 -1.6 50 0* 0* 100 Low-to-High 10 50 0* 0* 100 pF 1.4 1.1 ns ns

Ground Bounce in XC4000 Devices

Ground-bounce is a problem with high-speed digital ICs, when multiple outputs change state simultaneously causing undesired transient behavior on an output, or in the internal logic. This is also referred to as the Simultaneous Switching Output (SSO) problem. Ground bounce is primarily due to current changes in the combined inductance of ground pins, bond wires, and ground metallization. The ICinternal ground level deviates from the external system ground level for a short duration (a few nanoseconds) after multiple outputs change state simultaneously. Ground bounce affects outputs that are supposed to be stable Low, and it also affects all inputs since they interpret the incoming level by referencing it to the internal ground. If the ground bounce amplitude exceeds the actual instantaneous noise margin, then a non-changing input will be interpreted as a short pulse with a polarity opposite to the ground bounce. VCC bounce is not as important as ground bounce, because it is of lower magnitude due to the weaker pull-up transistors. Also, the noise immunity in the High state is usually better than in the Low state, and input levels are referenced to ground, not VCC. All this is the result of our industrys TTL heritage.

XC4000
Note:

1.4 -1.4 1.2 -1.2

*Zero by denition

Table 2: Increase in Output Delay When Driving Heavy Capacitive Loads (>150 pF) Slew Mode XC4000 Example: T High-to-Low for XC4005-5 with Fast-mode output driving 250 pF: 1.2 ns (from Table 1) plus (250-100) pF 1.5 ns/100 pF = 1.2 ns + 2.25 ns = 3.45 ns Total propagation delay, clock to pad: TOKPOF + 3.45 ns = 7.0 ns + 3.45 ns = 10.45 ns Slow Fast High-toLow 1.7 1.5 Low-toHigh 1.2 1.2

Test Method
ns/100 pF ns/100 pF Data was taken on XC4005-5, devices in the PQ208 package, soldered to the Xilinx Ground Bounce Test Board. Pin 82, two pins away from the nearest ground pin, was congured as a permanently Low output driver, effectively monitoring the internal ground level. The simultaneously switching outputs were on pins 80 and 83, for two outputs switching; additionally, pins 80 and 86 were used for four outputs switching. The closest ground pins are 79 and 90. Four ground-bounce parameters were measured at room temperature, with Vcc set at 5.5 V as shown in Figure 3. VOLP-HLPeak ground noise when switching High-to-Low VOLV-HLValley ground noise when switching High-to-Low VOLP-LHPeak ground noise switching Low-to-High VOLV-LHValley ground noise switching Low-to-High
VOH

All four parameters can affect system reliability.

VOH

Switching Outputs VOL VOL

VOLP-HL Non-Switching Active-Low Output VOLV-HL

VOLP-LH VOL VOLV-LH

X5299

Figure 3: Ground Bounce 13-16 XAPP 045 November 24, 1997 (Version 1.1)

The two positive peak values can cause problems with a signal leaving the ground bounce chip, driving another chip. The positive ground bounce voltage is added to the VOL, and may exceed the receiving inputs noise margin. A continuously logic Low input may thus be interpreted as a short-duration High pulse. The two negative valley parameters can cause problems with a signal arriving at the ground-bounce chip, reducing the Low-level noise immunity. The incoming voltage may not be Low enough, and may, therefore, be interpreted as a short-duration High input pulse. Table 3: Ground Bounce, 16 Outputs Switching, Each With 50 or 150 pF Load, VCC = 5.5 V Load 16 x 50 pF 16 x 150 pF Slew Rate Slow Fast Slow Fast High-to-Low VOLP VOLV 670 480 1,170 710 740 330 1,180 420 Low-to-High VOLP VOLV 240 240 480 660 210 280 350 710 Unit mV mV mV mV

the slew-rate mode of these outputs. Switching outputs closer to the monitoring output also cause larger peaks and valleys than outputs further away.

Guidelines for Reducing Ground-Bounce Effects

Minimize the impedance of the system ground distribution network and its connection to the IC pins. PQFPs are best suited, PGAs are worst, and PLCCs are in-between. Use PC-boards with ground- and VCC-planes, connected directly to the ICs supply pins. Place decoupling capacitors very close to these ground and VCC pins. Keep the ground plane as undisturbed as possible. A row of vias can easily cause a dynamic ground-voltage drop. Keep the clock inputs physically away from the outputs that create ground bounce, and connect clocks to input pins that are close to a ground pin. Make sure that all clock and asynchronous inputs have ample noise margin, especially in the Low state. If possible, avoid simultaneous switching by staggering output delays, e.g. through additional local routing of signals or clocks. Spread simultaneously switching outputs around the IC periphery. For a 16-bit bus, use two outputs each on either side of four ground pins.

Interpretation of the Results

Ground bounce is a linear phenomenon. When multiple outputs switch, the total ground bounce is the sum of the ground-bounce values caused by individual outputs switching. Since the actual switching of multiple outputs is usually not quite simultaneous, small timing differences between the switching outputs, caused by routing delays, can indirectly affect the amplitude. With low capacitive loading, < 50 pF, the peaks and valleys might even partially cancel each other. With larger capacitive loads, the tendency is for valleys to combine with valleys and peaks to combine with peaks. In most devices tested, the load capacitance does not directly affect the ground-bounce amplitude, but it does affect the duration of the ground-bounce signals. On the fastest outputs, minimal load capacitance created a ground-bounce resonant frequency of 340 MHz, with a half-cycle time of 1.5 ns. Such a signal exceeds 90% of its peak amplitude for about 0.4 ns. With a 50 pF load on the switching outputs, the ground bounce resonant frequency is 90 MHz, with a half-cycle time of 5 ns, staying 1.7 ns above 90% of peak amplitude. With a 150 pF load on the switching outputs, the ground bounce resonant frequency is 40 to 60 MHz, with a halfcycle time of 8 to 12 ns, staying 3 ns above 90% of peak amplitude. The main problem with large load capacitances is not an increase in amplitude, but rather an increase in duration of the ground-bounce signal. The amplitude is mainly affected by the number of outputs switching simultaneously, and by
Ground-Bounce Voltage (mV)

Ground-Bounce vs Delay Trade-Off

After the external sources of ground bounce have been reduced or eliminated. the designer can trade reduced ground bounce for additional delay by selecting between families and slew-rate options. Figure 4 shows the trade-off for 16 outputs switching simultaneously High-to-Low.
1800 1600 1400 1200 1000 800 600 400 200 0 SLOW SLEW RATE 16 x 50 pF 16 x 150 pF FAST SLEW RATE 16 x 50 pF 16 x 150 pF

5 Additional 6 Delay (ns)

X5981

Figure 4: Ground-Bounce vs. Delay Trade-off for 16 Outputs Switching 50 and 150 pF Each

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XC4000 Series Technical Information

XC4000 and XC4000E Power Consumption

Below are the dynamic power consumption values for typical design elements in XC4000 and XC4000E. The differences between XC4000 and XC4000E are too small to be statistically relevant: Global clocks in XC4000E are 3% higher, and Longlines and unloaded outputs in XC4000E are 5 to 10% lower than in XC4000. Power consumption is given at nominal 5.0-V supply and 25C. Power is proportional to the square of the supply voltage, but is almost constant over temperature changes. Power is given as mW per million transitions per second, since the more commonly used MHz can be ambiguous. When a 10-MHz clock toggles a ip-op, the clock line obviously makes 20 MTps, the ip-op output only 10 MTps. The rst six elements are device-size independent, i.e. they are applicable to all XC4000 or XC4000E devices operating at 5-V Vcc. One CLB ip-op driving nothing but a neighboring ipop in the same or adjacent CLB (a typical shift register design): 0.1 mW per million transitions per second = 0.1 mW/MTps One CLB ip-op driving its neighbor plus 9 lines of interconnect: 0.2 mW per million transitions per second = 0.2 mW/MTps One unloaded or unbonded TTL-level output: 0.25 mW per million transitions per second = 0.25 mW/MTps 50 pF on a TTL-level output: add 0.5 mW/MTps = 1.0 mW/MHz One unloaded or unbonded XC4000E CMOS-level output: 0.31 mW per million transitions per second = 0.31 mW/MTps 50 pF on a CMOS-level output: add 0.625 mW/MTps = 1.25 mW/MHz

The following elements are obviously device-size dependent: One Global Clock driving all CLB ip-ops, but no ipop changing: in XC4005: 4 mW/MTps = 8 mW/MHz in XC4010: 8 mW/MTps = 16 mW/MHz in XC4013: 12 mW/MTps = 24 mW/MHz in XC4020: 16 mW/MTps = 32 mW/MHz in XC4025: 20 mW/MTps = 40 mW/MHz One full-length horizontal or vertical Longline with one driving CLB source and one driven CLB load: in XC4005: 0.10 mW/MHz = 0.20 mW/MHz in XC4010: 0.15 mW/MTps = 0.30 mW/MHz in XC4013: 0.18 mW/MTps = 0.36 mW/MHz in XC4020: 0.20 mW/MTps = 0.40 mW/MHz in XC4025: 0.24 mW/MTps = 0.48 mW/MHz

These numbers do not account for the 10 mA of static power consumption when all device inputs are congured in TTL mode, which is always the default mode, and in XC4000 is actually the only user-accessible mode. These numbers assume short rise and fall times on all inputs, avoiding the cross-current when both the n-channel pull-down and the p-channel pull-up transistor in the input buffer might conduct simultaneously. Tutorial Comments: In its pure form, a CMOS output driving a capacitive load has a power consumption that is independent of drive impedance or rise and fall time. For a full-swing signal, the power consumed when charging the capacitor is C x V2 x f where f is the frequency of charge operations. In each charge operation, half the total energy consumed ends up on the capacitor, and the other half of the energy is dissipated in the current-limiting resistor or transistor, whatever its value may be. The subsequent discharge cycle does not take any new energy from the power supply, but dissipates in the currentlimiting resistor/transistor all the energy that was formerly stored in the capacitor. It is assumed here that the frequency is low enough so that the capacitors are completely charged and discharged in each half-cycle.

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XAPP 045 November 24, 1997 (Version 1.1)

APPLICATION NOTE
0

APPLICATION NOTE

XC3000 Series Technical Information

0 13*

XAPP 024 November 24, 1997 (Version 1.0) Summary

Application Note By Peter Alfke and Bernie New

This Application Note contains additional information that may be of use when designing with the XC3000 series of FPGA devices. This information supplements the data sheets, and is provided for guidance only. Xilinx Family XC3000/XC3000A/XC3000L/XC3100/XC3100A/XC3100L

Contents
CLBs Function Generators Flip-flops Longline Access IOBs Inputs Outputs Routing Horizontal Longlines Bus contention Vertical Longlines Vertical Longlines Clock Buffers Vertical Longlines Clock Buffers Power Dissipation Crystal Oscillator CCLK Frequency Stability and Low-time restriction Powerdown and Battery-Backup Configuration and Start-Up Reset Beware of slow rise-time

Congurable Logic Blocks

The XC3000/XC3100 CLB, shown in Figure 1, contains a combinatorial function generator and two D-type ip-ops. Two output pins may be driven by either the function generators or the ip-ops. The ip-op outputs may be routed directly back to the function generator inputs without going outside of the CLB. The function generator consists of two 4-input look-up tables that may be used separately or combined into a single function. Figure 2 shows the three available options. Since the CLB only has ve inputs to the function generator, inputs must be shared between the two look-up tables. In the FG mode, the function generator provides any two 4input functions of A, B and C plus D or E; the choice between D and E is made separately for each function. In the F mode, all ve inputs are combined into a single 5input function of A, B, C, D and E. Any 5-input function may be emulated. The FGM mode is a superset of the F mode, where two 4-input functions of A, B, C and D are multiplexed together according to the fth variable, E. In all modes, either of the B and C inputs may be selectively replaced by QX and QY, the ip-op outputs. In the FG mode, this selection is made separately for the two look-up tables, extending the functionality to any two functions of four variables chosen from seven, provided two of the variables are stored in the ip-ops. This is particularly useful in state-machine-like applications. In the F mode, the function generators implement a single function of ve variables that may be chosen from seven, as described above. The selection of QX and QY is constrained to be the same for both look-up tables. The FGM mode differs from the F mode in that QX and QY may be selected separately for the two look-up tables, as in the FG mode. This added exibility permits the emulation of selected functions that can include all seven possible inputs.

Introduction
The background information provided in this Application Note supplements the XC3000, XC3000A, XC3000L, XC3100A and XC3100L data sheets. It covers a wide range of topics, including a number of electrical parameters not specied in the data sheets, and unless otherwise noted, applies to all six families. These additional parameters are sufciently accurate for most design purposes; unlike the parameters specied in the data sheets, however, they are not worst-case values over temperature and voltage, and are not 100% production tested. They can, therefore, not be guaranteed.

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XC3000 Series Technical Information

Data In

DI 0 MUX 1 D Q

F DIN G A B C D E QX F Combinatorial Function G QY F DIN G

RD

QX X F CLB Outputs G Y QY

Logic Variables

0 MUX 1

Enable Clock

EC RD 1 (Enable) K

Clock Reset Direct

RD

0 (Inhibit) (Global Reset)

X3217

Figure 1: Congurable Logic Block (CLB)

Function Generator Avoids Glitches

The combinatorial logic in all CLBs is implemented as a function generator in the form of a multiplexer, built out of transfer gates. The logic inputs form the select inputs to this multiplexer, while the conguration bits drive the data inputs to the multiplexer. The Xilinx circuit designers were very careful to achieve a balanced design with similar (almost equal) propagation delays from the various select inputs to the data output. The delay from the data inputs to the output is, of course, immaterial, since the data inputs do not change dynamically. They are only affected by conguration. This balanced design minimizes the duration of possible decoding glitches when more than one select input changes. Note that there can never be a decoding glitch when only one select input changes. Even a non-overlapping decoder cannot generate a glitch problem, since the node capacitance will retain the previous logic level until the new transfer gate is activated about a nanosecond later. When more than one input changes simultaneously, the user should analyze the logic output for any possible intermediate code. If any such code permutation produces a different result, the user must assume that such a glitch might occur and must make the system design immune to it. The glitch might be only a few nanoseconds long, but that is long enough to upset an asynchronous design. If none of the possible address sequences produces a different result, the user can be sure that there will be no glitch. The designer of synchronous systems generally doesn't worry about such glitches, since synchronous designs are fundamentally immune to glitches on all signals except clocks or direct SET/RESET inputs.
A B QX QY C D E A B QX QY C D E 2a FG Mode Any Function of Up To 4 Variables G Any Function of Up To 4 Variables F

A B QX QY C D E Any Function of 5 Variables G F Mode F

2b

A B QX QY C D M U X QX QY C D E 2c FGM Mode
X3218

Any Function of Up To 4 Variables F

A B Any Function of Up To 4 Variables

Figure 2: CLB Logic Options

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XAPP 024 November 24, 1997 (Version 1.0)

The automatic logic-partitioning software in the XACTstep development system only uses the FG and F modes. However, all three modes are available with manual partitioning, which may be performed in the schematic. If FG or F modes are required, it is simply a matter of including in the schematic CLBMAP symbols that dene the inputs and outputs of the CLB. The FGM mode is only slightly more complicated. Again, a CLBMAP must be used, with the signal that multiplexes between the two 4-input functions locked onto the E pin. The CLB will be congured in the FGM mode if the logic is drawn such that the gates forming the multiplexer are shown explicitly with no additional logic merged into them. The two D-type ip-ops share a common clock, a common clock enable, and a common asynchronous reset signal. An asynchronous preset can be achieved using the asynchronous reset if data is stored in active-low form; the Low created by reset corresponds to the bit being asserted. The ip-ops cannot be used as latches. If input data to a CLB ip-op is derived directly from an input pad, without an intervening ip-op, the data-pad-toclock-pad hold time will typically be non-zero. This hold time is equal the delay from the clock pad to the CLB, but may be reduced according to the 70% rule, described later in the IOB Input section of this Application Note. Under this rule, the hold time is reduced by 70% of the delay from the data pad to the CLB, excluding the CLB set-up time. The minimum hold time is zero, even when applying the 70% rule results in a negative number. The CLB pins to which Longlines have direct access are shown in Table 1. Note that the clock enable pin (EC) and the TBUF control pin are both driven from to the same vertical Long Line. Consequently, EC cannot easily be used to enable a register that must be 3-stated onto a bus. Similarly, EC cannot easily be used in a register that uses the Reset Direct pin (RD). Table 1: Longline to CLB Direct Access
CLB Longline Left Most Vertical (GCLK) Left Middle Vertical Right Middle Vertical Right Most Vertical (ACLK) Upper Horizontal Lower Horizontal TBUF

Input/Output Blocks
The XC3000/XC3100 IOB, shown in Figure 3, includes a 3state output driver that may be driven directly or registered. The polarities of both the output data and the 3-state control are determined by conguration bits. Each output buffer may be congured to have either a fast or a slow slew rate. The IOB input may also be direct or registered. Additionally, the input ip-op may be congured as a latch. When an IOB is used exclusively as an input, an optional pull-up resistor is available, the value of which is 40-150 k. This resistor cannot be used when the IOB is congured as an output or as a bidirectional pin. Unused IOBs should be left uncongured. They default to inputs pulled High with the internal resistor.

Inputs
All inputs have limited hysteresis, typically in excess of 200 mV for TTL input thresholds and in excess of 100 mV for CMOS thresholds. Exceptions to this are the PWRDWN pin, and the XTL2 pin when it is congured as the crystal oscillator input. Experiments show that the input rise and fall times should not exceed 250 ns. This value was established through a worst-case test using internal ring oscillators to drive all I/O pins except two, thus generating a maximum of on-chip noise. One of the remaining I/O pins was congured as an input, and tested for single-edge response; the other I/O was used as an output to monitor the response. These test conditions are, perhaps, overly demanding, although it was assumed that the PC board had negligible ground noise and good power-supply decoupling. While conservative, the resulting specication is, in most instances, easily satised. IOB input ip-ops are guaranteed to operate correctly without data hold times (with respect to the device clockinput pad) provided that the dedicated CMOS clock input pad and the GCLK buffer are used. The use of a TTL clock or a different clock pad will result in a data-hold-time requirement. The length of this hold time is equal to the delay from the actual clock pad to the GCLK buffer minus the delay from the dedicated CMOS clock pad to the GCLK buffer. To ensure that the input ip-op has a zero hold time, delay is incorporated in the D input of the ip-op, causing it to have a relatively long set-up time. However, the set-up time specied in the data sheet is with respect to the clock reaching the IOB. Since there is an unavoidable delay between the clock pad and the IOB, the input-pad-to-clockpad set-up time is actually less than the data sheet number.

A B C D E K EC RD X X X X X X X X X X

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XC3000 Series Technical Information

Program-Controlled Memory Cells

VCC Slew Rate Passive Pull Up

Out Invert

3-State Invert

Output Select

3-State (OUTPUT ENABLE)

Out

FlipFlop

Output Buffer

I/O Pad R Direct In Registered In I Q Q D FlipFlop or Latch R OK IK (Global Reset)

TTL or CMOS Input Threshold

CK1

Program Controlled Multiplexer = Programmable Interconnection Point or PIP

CK2

X3216

Figure 3: Input/Output Block (IOB) Part of the clock delay can be subtracted from the internal set-up time. Ideally, all of the clock delay could be subtracted, but it is possible for the clock delay to be less than its maximum while the internal set-up time is at its maximum value. Consequently, it is recommended that, in a worst-case design, only 70% of the clock delay is subtracted. The clock delay can only be less than 70% of its maximum if the internal set-up time requirement is also less than its maximum. In this case, the pad-to-pad set-up time actually required will be less than that calculated. For example, in the XC3000-125, the input set-up time with respect to the clock reaching the IOB is 16 ns. If the delay from the clock pad to the IOB is 6 ns, then 70% of this delay, 4.2 ns, can be subtracted to arrive at a maximum pad-topad set-up time of ~12 ns. The 70% rule must be applied whenever one delay is subtracted from another. However, it is recommended that delay compensation only be used routinely in connection with input hold times. Delay compensation in asynchronous circuits is specically not recommended. In any case, the compensated delay must not become negative. If 70% of the compensating delay is greater than the delay from which it is deducted, the resulting delay is zero.

The 70% rule in no way denes the absolute minimum values delays that might be encountered from chip to chip, and with temperature and power-supply variations. It simply indicates the relative variations that might be found within a specic chip over the range of operating conditions.
Typically, all delays will be less than their maximum, with some delays being disproportionately faster than others. The 70% rule describes the spread in the scaling factors; the delay that decreases the most will be no less than 70% of what it would have been if it had scaled in proportion to the delay that decreased the least. In particular, in a worstcase design where it is assumed that any delay might not have scaled at all, and remains at its maximum value, other delays will be no less than 70% of their maximum.

Outputs
All XC3000/XC3100 FPGA outputs are true CMOS with nchannel transistors pulling down and p-channel transistors pulling up. Unloaded, these outputs pull rail-to-rail. Some additional ac characteristics of the output are listed in Table 2. Figure 4 and Figure 5 show output current/voltage curves for typical XC3000 and XC3100 devices.

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200 180 160 140 120 mA 100 80 60 40 20 0 1 2 3 4 5

X5294

IOB latches have active-Low Latch Enables; they are transparent when the clock input is Low and are closed when it is High. The latch captures data on what would otherwise be the active clock edge, and is transparent in the half clock period before the active clock edge.
IOL

Routing
IOH

Horizontal Longlines
As shown in Table 3, there are two horizontal Longlines (HLLs) per row of CLBs. Each HLL is driven by one TBUF for each column of CLBs, plus an additional TBUF at the left end of the Longline. This additional TBUF is convenient for driving IOB data onto the Longline. In general, the routing resources to the T and I pins of TBUFs are somewhat limited. Table 3: Number of Horizontal Longlines

Volts

Figure 4: Output Current/Voltage Characteristics for XC3000, XC3000A, XC3100 and XC3100A Devices Output-short-circuit-current values are given only to indicate the capability to charge and discharge capacitive loads. In accordance with common industry practice for other logic devices, only one output at a time may be short circuited, and the duration of this short circuit to VCC or ground may not exceed one second. Xilinx does not recommend a continuous output or clamp current in excess of 20 mA on any one output pin. The data sheet guarantees the outputs for no more than 4 mA at 320 mV to avoid problems when many outputs are sinking current simultaneously. The active-High 3-state control (T) is the same as an active-Low output enable (OE). In other words, a High on the T-pin of an OBUFZ places the output in a high impedance state, and a Low enables the output. The same naming convention is used for TBUFs within the FPGA device.

Part Name
XC3020 XC3030 XC3042 XC3064 XC3090 XC3195

Rows x Columns
8x8 10 x 10 12 x 12 16 x 14 20 x 16 22 x 22

CLBs
64 100 144 224 320 484

Horizontal Longlines
16 20 24 32 40 44

TBUFs per HLL

9 11 13 15 17 23

Optionally, HLLs can be pulled up at either end, or at both ends. The value of each pull-up resistor is 3-10 k. In addition, HLLs are permanently driven by low-powered latches that are easily overridden by active outputs or pullup resistors. These latches maintain the logic levels on HLLs that are not pulled up and temporarily are not driven. The logic level maintained is the last level actively driven onto the line. When using 3-state HLLs for multiplexing, the use of fewer than four TBUFs can waste resources. Multiplexers with four or fewer inputs can be implemented more efciently using CLBs.

I/O Clocks
Internally, up to eight distinct I/O clocks can be used, two on each of the four edges of the die. While the IOB does not provide programmable clock polarity, the two clock lines serving an IOB can be used for true and inverted clock, and the appropriate polarity connected to the IOB. This does, however, limit all IOBs on that edge of the die to using only the two edges of the one clock. Table 2: Additional AC Output Characteristics AC Parameters Unloaded Output Slew Rate Unloaded Transition Time Additional rise time for 812 pF normalized Additional fall time for 812 pF normalized Fast* 2.8 V/ns 1.45 ns 100 ns 0.12 ns/pF 50 ns 0.06 ns/pF Slow* 0.5 V/ns 7.9 ns 100 ns 0.12 ns/pF 64 ns 0.08 ns/pF

Internal Bus Contention

XC3000 and XC4000 Series devices have internal 3-state bus drivers (TBUFs). As in any other bus design, such bus drivers must be enabled carefully in order to avoid, or at least minimize, bus contention. (Bus contention means that one driver tries to drive the bus High while a second driver tries to drive it Low). Since the potential overlap of the enable signals is lay-out dependent, bus contention is the responsibility of the FPGA user. We can only supply the following information: While two internal buffers drive conicting data, they create a current path of typically 6 mA. This current is tolerable, but should not last indenitely, since it exceeds our (conser13-23

* Fast and Slow refer to the output programming option.

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XC3000 Series Technical Information

vative) current density rules. A continuous contention could, after thousands of hours, lead to metal migration problems. In a typical system, 10 ns of internal bus contention at 5 MHz would just result in a slight increase in Icc. 16 bits x 6 mA x 10 ns x 5 MHz x 50% probability = 2.5 mA. There is a special use of the 3-state control input: When it is directly driven by the same signal that drives the data input of the buffer, i.e. when D and T are effectively tied together, the 3-state buffer becomes an open collector driver. Multiple drivers of this type can be used to implement the wiredAND function, using resistive pull-up. In this situation there cannot be any contention, since the 3state control input is designed to be slow in activating and fast in deactivating the driver. Connecting D to ground is an obvious alternative, but may be more difcult to route.

local interconnect should only be considered for individual ip-ops.

Power Dissipation
As in most CMOS ICs, almost all FPGA power dissipation is dynamic, and is caused by the charging and discharging of internal capacitances. Each node in the device dissipates power according to the capacitance in the node, which is xed for each type of node, and the frequency at which the particular node is switching, which can be different from the clock frequency. The total dynamic power is the sum of the power dissipated in the individual nodes. While the clock line frequency is easy to specify, it is usually more difcult to estimate the average frequency of other nodes. Two extreme cases are binary counters, where half the total power is dissipated in the rst ip-op, and shift registers with alternating zeros and ones, where the whole circuit is exercised at the clocking speed. A popular assumption is that, on average, each node is exercised at 20% of the clock rate; a major EPLD vendor uses a 16-bit counter as a model, where the effective percentage is only 12%. Undoubtedly, there are extreme cases, where the ratio is much lower or much higher, but 15 to 20% may be a valid approximation for most normal designs. Note that global clock lines must always be entered with their real, and obviously well-known, frequency. Consequently, most power consumption estimates only serve as guidelines based on gross approximations. Table 4 shows the dynamic power dissipation, in mW per MHz, for different types of XC3000 nodes. While not precise, these numbers are sufciently accurate for the calculations in which they are used, and may be used for any XC3000/ XC3100 device. Table 5 shows a sample power calculation. Table 4: Dynamic Power Dissipation XC3020 XC3090
One CLB driving three local interconnects One device output with a 50 pF load One Global Clock Buffer and line One Longline without driver 0.25 1.25 2.00 0.10 0.25 1.25 3.50 0.15 mW/MHz mW/MHz mW/MHz mW/MHz

Vertical Longlines
There are four vertical Longlines per routing channel: two general purpose, one for the global clock net and one for the alternate clock net.

Clock Buffers
XC3000/XC3100 devices each contain two high-fan-out, low-skew clock-distribution networks. The global-clock net originates from the GCLK buffer in the upper left corner of the die, while the alternate clock net originates from the ACLK buffer in the lower right corner of the die. The global and alternate clock networks each have optional fast CMOS inputs, called TCLKIN and BCLKIN, respectively. Using these inputs provides the fastest path from the PC board to the internal ip-ops and latches. Since the signal bypasses the input buffer, well-dened CMOS levels must be guaranteed on these clock pins. To specify the use of TCLKIN or BCLKIN in a schematic, connect an IPAD symbol directly to the GCLK or ACLK symbol. Placing an IBUF between the IPAD and the clock buffer will prevent TCLKIN or BCLKIN from being used. The clock buffer output nets only drive CLB and IOB clock pins. They do not drive any other CLB inputs. In rare cases where a clock needs to be connected to a logic input or a device output, a signal should be tapped off the clock buffer input, and routed to the logic input. This is not possible with clocks using TCLKIN or BCLKIN. The clock skew created by routing clocks through local interconnect makes safe designs very difcult to achieve, and this practice is not recommended. In general, the fewer clocks that are used, the safer the design. High fan-out clocks should always use GCLK or ACLK. If more than two clocks are required, the ACLK net can be segmented into individual vertical lines that can be driven by PIPs at the top and bottom of each column. Clock signals routed through

Table 5: Sample Power Calculation for XC3020 Quantity

1 5 10 40 8 20

Node
Clock Buffer CLBs CLBs CLBs Longlines Outputs

MHz
40 40 20 10 20 20

mW/MHz

mW

2.00 80 0.25 50 0.25 50 0.25 100 0.10 16 1.25 500 Total Power ~800

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Crystal Oscillator
XC3000 and XC3100 devices contain an on-chip crystal oscillator circuit that connects to the ACLK buffer. This circuit, Figure 5, comprises a high-speed, high-gain inverting amplier with its input connected to the dedicated XTL2 pin, and its output connected to the XTL1 pin. An external biasing resistor, R1, with a value of 0.5 to 1 M is required. A crystal, Y1, and additional phase-shifting components, R2, C1 and C2, complete the circuit. The capacitors, C1 and C2, in series form the load on the crystal. This load is specied by the crystal manufacturer, and is typically 20 pF. The capacitors should be approximately equal: 40 pF each for a 20 pF crystal. Either series- or parallel-resonant crystals may be used, since they differ only in their specication. Crystals constrain oscillation to a narrow band of frequencies, the width of which is <<1% of the oscillating frequency; the exact frequency of oscillation within this band depends on the components surrounding the crystal. Series-resonant crystals are specied by their manufacturers according to the lower edge of the frequency band, parallel-resonant crystals according to the upper edge. The resistor R2 controls the loop gain and its value must be established by experimentation. If it is too small, the oscillation will be distorted; if it is too large, the oscillation will fail to start, or only start slowly. In most cases, the value of R2 is non-critical, and typically is 0 to 1 k. Once the component values have been chosen, it is good practice to test the oscillator with a resistor (~1 k) in series with the crystal. If the oscillator still starts reliably, independent of whether the power supply turns on quickly or slowly, it will always work without the resistor. For operation above 20 to 25 MHz, the crystal must be operated at its third harmonic. The capacitor C2 is replaced by a parallel-resonant LC tank circuit tuned to ~2/3 of the desired frequency, i.e., twice the fundamental frequency of the crystal. Table 6 shows typical component values for the tank circuit. Crystal operation below 1 MHz is not supported. Low-frequency crystals have a high resonant impedance and require more gain than provided by the single stage inverter in the XC3000 devices. Low-frequency applications are usually also more power-conscious and would not accept the power consumption of the fast general-purpose Xilinx oscillator circuit. Inexpensive complete oscillator packages are often a better choice.
XTAL_OUT

XTAL_IN

FPGA

R1 R2 Y1

C1

C2

L 3RD Overtone Only

X6128

Figure 5: Crystal Oscillator

Table 6: Third-Harmonic Crystal Oscillator Tank-Circuit Frequency LC Tank (MHz) L (H) C2 (pF) Freq (MHz) R2 () C1 (pF) 32 1 60 20.6 430 23 35 1 44 24.0 310 23 49 1 31 28.6 190 23 72 1 18 37.5 150 12

Crystal-Oscillator Considerations
There is nothing Xilinx-specic about the oscillator circuit. Its a wide-band inverting amplier, as used in all popular microcontrollers. When a crystal and some passive components close the feedback path, this circuit becomes a reliable and stable clock source. The path from XTAL2 to XTAL1 inside the LCA device is a single-stage inverting amplier, which means it has a lowfrequency phase response of 180, increasing by 45 at the 3-dB frequency. Input impedance is 10-15 pF, input threshold is CMOS, but dc bias must be supplied externally through a megohm resistor from XTAL1 to XTAL2. Low-frequency gain is about 10, rolling off 3dB at 125 MHz. Output impedance is between 50 and 100 and the capacitance on the output pin is 10 to 15 pF. Pulse response is a delay of about 1.5 ns and a rise/fall time of about 1.5 ns.

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XC3000 Series Technical Information

For stable oscillation, the loop gain must be exactly one, i.e., the internal gain must be matched by external attenuation, and the phase shift around the loop must be 360 or an integer multiple thereof. The external network must, therefore, provide 180 of phase shift.

circuit equals the gain in the FPGA device, and where the total phase shift, internal plus external, equals 360. Figure 7 explains the function. At the frequency of oscillation, the series-resonant circuit is effectively an inductor, and the two capacitors act as a capacitive voltage divider, with the center-point grounded. This puts a virtual ground somewhere along the inductor and causes the non-driven end of the crystal to be 180 out of phase with the driven end, which is the external phase shift required for oscillation. This circuit is commonly known as a Pierce oscillator.

A crystal is a piezoelectric mechanical resonator that can be modeled by a very high-Q series LC circuit with a small resistor representing the energy loss. In parallel with this series-resonant circuit is unavoidable parasitic capacitance inside and outside the crystal package, and usually also discrete capacitors on the board. The impedance as a function of frequency of this whole array starts as a small capacitor at low frequencies (Figure 6). As the frequency increases, this capacitive reactance decreases rapidly, until it reaches zero at the series resonant frequency.

XC2000/XC3000

Inductive
XTAL
X5321

jL

Series Resonance

Parallel Resonance

Frequency

Figure 7: Pierce Oscillator

1 jC Capacitive
C L R

Practical Considerations
The series resonance resistor is a critical parameter. To assure reliable operation with worst-case crystals, the user should experiment with a discrete series resistor roughly equal to the max internal resistance specied by the crystal vendor. If the circuit tolerates this additional loss, it should operate reliably with a worstcase crystal without the additional resistor. The two capacitors affect the frequency of oscillation and the start-up conditions. The series connection of the two capacitors is the effective capacitive load seen by the crystal, usually specied by the crystal vendor. The two capacitors also determine the minimum gain required for oscillation. If the capacitors are too small, more gain is needed, and the oscillator may be unstable. If the capacitors are too large, oscillation is stable but the required gain may again be higher. There is an optimum capacitor value, where oscillation is stable, and the required gain is at a minimum. For most crystals, this capacitive load is around 20 pF, i.e., each of the two capacitors should be around 40 pF. Crystal dissipation is usually around 1 mW, and thus of no concern. Beware of crystals with drive-level dependence of the series resistor. They may not start up. Proper drive level can be checked by varying Vcc. The frequency should increase slightly with an increase in Vcc. A decreasing frequency or unstable amplitude indicate an over-driven crystal. Excessive swing at the

X2818

Figure 6: Reactance as a Function of Frequency At slightly higher frequencies, the reactance is inductive, starting with a zero at series resonance, and increasing very rapidly with frequency. It reaches innity when the effective inductive impedance of the series LC circuit equals the reactance of the parallel capacitor. The parallel resonance frequency is a fraction of a percent above the series-resonance frequency. Over this very narrow frequency range between series and parallel resonance, the crystal impedance is inductive and changes all the way from zero to innity. The energy loss represented by the series resistor prevents the impedance from actually reaching zero and innity, but it comes very close. Microprocessor- and FPGA-based crystal oscillators all operate in this narrow frequency band, where the crystal impedance can be any inductive value. The circuit oscillates at a frequency where the attenuation in the external

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XTAL2 input results in clipping near Vcc and ground. An additional 1 to 2 k series resistor at the XTAL1 output usually cures that distortion problem. It increases the amplier output impedance and assures additional phase margin, but results in slower start-up. Be especially careful when designing an oscillator that must operate near the specied max frequency. The circuit needs excess gain at small signal amplitudes to supply enough energy into the crystal for rapid start-up. High-frequency gain may be marginal, and start-up may be impaired. Keep the whole oscillator circuit physically as compact as possible, and provide a single ground connection. Grounding the crystal can is not mandatory but may improve stability.

and fastest Xilinx FPGA is compatible with the oldest and slowest device ever manufactured. The CCLK frequency is fairly insensitive to changes in VCC, varying only 0.6% for a 10% change in VCC. It is, however, very temperature dependent, increasing 40% as the temperature drops from 25C to -30C, (Table 7.) Table 7: Typical CCLK Frequency Variation VCC 4.5 V 5.0 V 5.5 V 4.5 V 4.5 V Temp 25C 25C 25C -30C +130C Frequency 687 kHz 691 kHz 695 kHz 966 kHz 457 kHz

CCLK Low-Time Restriction

Series Resonant or Parallel Resonant?
Crystal manufacturers label some crystals as seriesresonant, others as parallel-resonant, but there really is no difference between these two types of crystals, they all operate in the same way. Every crystal has a series resonance, where the impedance of the crystal is extremely low, much lower than at any other frequency. At a slightly higher frequency, the crystal is inductive and in parallel resonance with the unavoidable stray capacitance or the deliberate capacitance between its pins. The only difference between the two types of crystal is the manufacturer's choice of specifying either of the two frequencies. If series resonance is specied, the actual frequency of oscillation is a little higher than the specied value. If parallel resonance is specied, the frequency of oscillation is a little lower. In most cases, these small deviations are irrelevant. When used as an input in Slave Serial and Readback modes, CCLK does not tolerate a Low time in excess of 5 s. For very low speed operation, the CCLK High time can be stretched to any value, but the Low time must be kept short. XC4000 and XC5200 devices do not have this restriction.

Battery Back-up
Since SRAM-based FPGAs are manufactured using a high-performance low-power CMOS process, they can preserve the conguration data stored in the internal static memory cells even during a loss of primary power. This is accomplished by forcing the device into a low-power nonoperational state, while supplying the minimal current requirement of VCC from a battery. Circuit techniques used in XC3100, XC4000 and XC5200 devices prevent ICC from being reduced to the level need for battery back-up. Consequently, battery back-up should only be used for XC2000, XC2000L, XC3000, XC3000A and XC3000L devices. There are two primary considerations for battery backup which must be accomplished by external circuits. Control of the Power-Down (PWRDWN) pin Switching between the primary VCC supply and the battery.

CCLK Frequency Variation

The on-chip R-C oscillator that is brought out as CCLK also performs several other internal functions. It generates the power-on delay, 216 = 65,536 periods for a master, 214 = 16,384 periods for a slave or peripheral device. It generates the shift pulses for clearing the conguration array, using one clock period per frame, and it is the clock source for several small shift registers acting as low-pass lters for a variety of input signals. The nominal frequency of this oscillator is 1 MHz with a max deviation of +25% to -10%. The clock frequency, therefore, is between 1.25 MHz and 0.5 MHz. In the XC4000 family, the 1-MHz clock is derived from an internal 8-MHz clock that also can be used as CCLK source. Xilinx circuit designers make sure that the internal clock frequency does not get faster as devices are migrated to smaller geometries and faster processes. Even the newest

Important considerations include the following. Insure that PWRDWN is asserted logic Low prior to VCC falling, is held Low while the primary VCC is absent, and returned High after VCC has returned to a normal level. PWRDWN edges must not rise or fall slowly. Insure glitch-free switching of the power connections to the FPGA device from the primary VCC to the battery and back. Insure that, during normal operation, the FPGA VCC is maintained at an acceptable level, 5.0 V 5% (10% for Industrial and Military).

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XC3000 Series Technical Information

Figure 8 shows a power-down circuit developed by Shel Epstein of Epstein Associates, Wilmette, IL. Two Schottky diodes power the FPGA from either the 5.2 V primary supply or a 3 V Lithium battery. A Seiko S8054 3-terminal power monitor circuit monitors VCC and pulls PWRDWN Low whenever VCC falls below 4 V.
Seiko S8054 Specifications Detect Voltage 3.995 V min 4.305 V max 208 mV typ Hysteresis Temp. Coeff. 0.52 mV/C 2.6 A typ ICC @ + 6V

by activating internal bus drivers with conicting data onto the same Longline. These two situations are farfetched, but they are possible and will result in considerable power consumption. It is quite easy to simulate these conditions since all inputs are stable and the internal logic is entirely combinatorial, unless latches have been made out of function generators. During powerdown, the Vcc monitoring circuit is disabled. It is then up to the user to prevent Vcc dips below 2.3 V, which would corrupt the stored conguration. During conguration, the PWRDWN pin must be High, since conguration uses the internal oscillator. Whenever Vcc goes below 4 V, PWRDWN must already be Low in order to prevent automatic reconguration at low Vcc. For the same reason, Vcc must rst be restored to 4 V or more, before PWRDWN can be made High. PWRDWN has no pull-up resistor. A pull-up resistor would draw supply current when the pin is Low, which would defeat the idea of powerdown, where Icc is only microamperes.

VCC IN5817

IN5817 B35 Lithium Battery

2 SEIKO 1 PWRDWN S 8054 3

VCC FPGA

X5997

Figure 8: Battery Back-up Circuit

Conguration and Start-up

Start-Up
Start-up is the transition from the conguration process to the intended user operation. This means a change from one clock source to another, and a change from interfacing parallel or serial conguration data where most outputs are 3-stated, to normal operation with I/O pins active in the user-system. Start-up must make sure that the user-logic wakes up gracefully, that the outputs become active without causing contention with the conguration signals, and that the internal ip-ops are released from the global Reset or Set at the right time. Figure 10 describes Start-up timing for the XC3000 families in detail. DONE can be programmed to go High one CCLK period before or after the I/O become active. Independent of DONE, the internal global Reset is de-activated one CCLK period before or after the I/O become active. The default option, and the most practical one, is for DONE to go High rst, disconnecting the conguration data source and avoiding any contention when the I/Os become active one clock later. Reset is then released another clock period later to make sure that user-operation starts from stable internal conditions. This is the most common sequence, shown with heavy lines in Figure 11, but the designer can modify it to meet particular requirements. Until the chip goes active after conguration, all I/O pins not involved in the conguration process remain in a highimpedance state with weak pull-up resistors; all internal ip-ops and latches are held reset. Multiple FPGA devices hooked up in a daisy chain will all go active simultaneously

Powerdown Operation
A Low level on the PWRDWN input, while Vcc remains higher than 2.3 V, stops all internal activity, thus reducing Icc to a very low level: All internal pull-ups (on Long lines as well as on the I/O pads) are turned off. The crystal oscillator is turned off All package outputs are three-stated. All package inputs ignore the actual input level, and present a High to the internal logic. All internal ip-ops or latches are permanently reset. The internal conguration is retained. When PWRDWN is returned High, after VCC is at its nominal value, the device returns to operation with the same sequence of buffer enable and D/P as at the completion of conguration.

Things to Remember
Powerdown retains the conguration, but loses all data stored in the device. Powerdown three-states all outputs and ignores all inputs. No clock signal will be recognized, and the crystal oscillator is stopped. All internal ip-ops and latches are permanently reset and all inputs are interpreted as High, but the internal combinatorial logic is fully functional.

Things to Watch Out For

Make sure that the combination of all inputs High and all internal ip-op outputs Low in your design will not generate internal oscillations or create permanent bus contention

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Length Count Match

CCLK Period

CCLK
F DONE I/O

unasserted, but D remains High since the function generator acts as an R-S latch; Q stays Low, and RESET is still pulled High by the external resistor. On the rst system clock after conguration ends, Q is clocked High, resetting the latch and enabling the output driver. which forces RESET Low. This resets the whole chip until the Low on Q permits RESET to be pulled High again. The whole chip has thus been reset by a short pulse instigated by the system clock. No further pulses are generated, since the High on LDC prevents the R-S latch from becoming set.

Global Reset
X5967

Figure 9: Start-up Timing on the same CCLK edge. This is well documented in the data sheets. Not documented, however, is how the internal combinatorial logic comes alive during conguration: As conguration data is shifted in and reaches its destination, it activates the logic and also looks at the IOB inputs. Even the crystal oscillator starts operating as soon as it receives its conguration data. Since all ip-ops and latches are being held reset, and all outputs are being held in their high-impedance state, there is no danger in this staggered awakening of the internal logic. The operation of the logic prior to the end of conguration is even useful; it ensures that clock enables and output enables are correctly dened before the elements they control become active. Once conguration is complete, the FPGA device is activated. This occurs on a rising edge of CCLK, when all outputs and clocks that are enabled become active simultaneously. Since the activation is triggered by CCLK, it is an asynchronous event with respect to the system clock. To avoid start-up problems caused by this asynchronism, some designs might require a reset pulse that is synchronized to the system clock. The circuit shown in Figure 10 generates a short Global Reset pulse in response to the rst system clock after the end of conguration. It uses one CLB and one IOB, and also precludes the use of the LDC pin as I/O. During Conguration, LDC is asserted Low and holds the D-input of the ip-op High, while Q is held Low by the internal reset, and RESET is kept High by internal and external pull-up resistors. At the end of conguration, the LDC pin is

Beware of a Slow-Rising XC3000 Series RESET Input

It is a wide-spread habit to drive asynchronous RESET inputs with a resistor-capacitor network to lengthen the reset time after power-on. This can also be done with Xilinx FPGAs, but the user should question the need, and should beware of certain avoidable problems. Xilinx FPGAs contain an internal voltage-monitoring circuit, and start their internal housekeeping operation only after VCC has reached ~3.5 V. The internal housekeeping and conguration memory clearing operation then takes between about 10 and 100 ms, depending on conguration mode and processing variations. Any RC delay shorter than 40 ms for a device in master conguration mode, or shorter than 10 ms for a device in slave conguration mode, is clearly redundant. A signicantly longer RC delay can be used to hold off conguration. Without the use of an external Schmitt trigger circuit, the rise time on the RESET input will be very slow, and is likely to cross the threshold of ~1.4 V several times, due to external or internal noise. This can cause the FPGA to start conguration, then immediately abort it, then start it again, after having automatically cleared the conguration memory once more. This is no problem for the FPGA, but it requires that the source of conguration data, especially an XC1700 serial PROM, be reset accordingly. This is another reason to use the INIT output of the lead FPGA, instead of LDC, to drive the RESET input of the XC1700 serial PROMs.

VCC OE = High T = Low D System Clock Low CLB MR IOB RESET Q

High IOB

LDC
X3222

Figure 10: Synchronous Reset

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XC3000 Series Technical Information

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APPLICATION NOTE
0

APPLICATION NOTE

FPGA Conguration Guidelines

0 13*

XAPP 090 November 24, 1997 (Version 1.1)

Application Note By Peter Alfke

Summary
These guidelines describe the conguration process for all members of the XC2000, XC3000, XC4000 and XC5200 FPGA devices and their derivatives. The average user need not understand or remember all these details, but should refer to the debugging hints when problems occur.

The XC2000-, XC3000-, XC4000- and XC5200-family FPGAs share a basic conguration concept, and can be combined in a common conguration bitstream, but there are also small differences among the four families as described below. Following their initial power-on conguration-memory initialization, these Xilinx FPGAs are congured by a serial conguration bitstream. The byte-parallel conguration modes just activate an internal parallel-to-serial converter, and then use the serial bitstream internally. (Express mode in the XC5200 congures eight bits in parallel, but this mode is not covered in this application note.) The software generates a bitstream that starts with a 40-bit header (48bit header for XC5200), see Figure 1. Each device uses a few of the leading ones to prepare for conguration, then detects the 0010 pattern and stores the following 24 bits as a length-count value in an internal register. The content of this register is continuously compared against a running counter that increments on every rising CCLK edge. CCLK is either an output (in Master and Asynchronous Peripheral modes) or an input (in Slave Serial and Synchronous Peripheral modes). In all modes, even in Master Serial, it is the externally observable Low-to-High transition on the CCLK pin that causes the internal action. Every CCLK rising edge that occurs while INIT and RESET are High is counted, even during the preamble. Note that XC2000 and XC3000 use quasi-static circuitry which imposes a 5 ms max limit on the CCLK Low time, while XC4000 and XC5200 are completely static and have no max CCLK time limit. This is, of course, only of interest in XC2000 and XC3000 Slave Serial mode, where CCLK is generated by the user. While it is permissible, although not meaningful, to modify the number of leading ones by adding additional ones, or subtracting up to four ones, this would inevitably affect the number of CCLK pulses received by the counter, and thus change the moment when the internal counter is equal to the value stored in the length-count register. Dont add or delete preamble-leading ones!

Each device passes the incoming header, including the length-count value, on to the DOUT pin, delayed by half a CCLK period, i.e. the bits are clocked out on a falling CCLK edge. In this way, the header is passed on to all devices that might be connected in a daisy-chain. After the lengthcount data has been passed on, DOUT goes active High and stays High until the device has been lled with the appropriate number of conguration frames. After that, DOUT again passes all incoming conguration data on to other devices that might be part of the daisy chain. DOUT is thus the best observation point to see whether the conguration process has started properly. Immediately following the header, conguration data is received, formatted in a device-specic sequence of frames. Each frame starts with a single zero as start bit (XC5200 starts with a byte of seven leading ones and a single trailing zero), followed by a device-specic number of conguration bits per frame, followed by three ones as stop bits (XC2000, XC3000) or, in XC4000 and XC5200, by four bits that are either 0110, or four bits of a running 16-bit CRC error-checking code. The choice is made in the bitstream generator, where the default is CRC disabled. The header is excluded from the CRC calculation. Each frame is physically shifted into a serial shift register that had been preset to all ones. When the zero start bit hits the far end of this shift register, the data frame is transferred in parallel into the conguration memory, as addressed by the position of an internal token or pointer. The three stop or four error-check bits provide ample time for this transfer, even at a 10 MHz CCLK rate. After this transfer, the shift-in procedure continues with the following frame. Note that there is no counter for the number of bits in the frame nor for the number of frames. The operation is self-synchronized by detecting the presence of a start bit at the far end of the shift register, and by moving the frame pointer.

11111111 0010 (MSB) 24-Bit Length Count (LSB) 1111 Data

X5553

Figure 1: 40-Bit Header

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Each Xilinx FPGA requires a number of conguration bits that is device-dependent, but independent of the conguration content, and independent of the conguration mode. The number of conguration bits per device ranges from 12,038 for the XC2064 to 1,924,992 for the XC4085XL, approximately 20 bits per available user gate. Exact values are listed in the specic family data sheets.

Daisy-Chain Operation
Multiple FPGAs can be congured by a single concatenated bitstream. The device daisy chain is formed by connecting DOUT to the next devices DIN, and connecting all CCLK pins in parallel. DOUT goes active on a falling clock edge, and DIN accepts data on the subsequent rising clock edge. Each DOUT-to-DIN connection adds one extra bit of delay to the bitstream. Since the header is passed through all devices, they all receive the same header information delayed by one bit per device, but all devices maintain perfect synchronism between their CCLK counters, since all receive the same CCLK. Xilinx recognizes the need for all devices in a daisy chain to nish conguration and begin user operation simultaneously, as a result of one common CCLK edge. Therefore, all devices in a daisy-chain need a common timing reference. They cannot rely on the start pattern received through the pipelined chain, but must all count the common CCLK pulses exactly the same way. This explains the importance of precise conguration clocking, and the danger of reections and ringing on the CCLK line.

Protection Against Data or Format Errors

The serial conguration scheme has proven reliable in thousands of designs and millions of devices, but there have been cases where an erroneous bitstream was loaded accidentally. The original XC2000 and XC3000 devices provide no effective protection against this type of error. If long enough, any random sequence of 0s and 1s will congure such a device. This inevitably takes additional CCLK pulses, more than specied in the length-count value. This means that the CCLK counter already matches the length-count value before the last FPGA in the chain is lled. This comparison is, therefore, ignored, and an additional ~16 million CCLK pulses are required to roll the 24-bit length counter and nish the conguration. Such a conguration will, of course, be wrong and might result in excessive power consumption due tol contentions. XC3000A, XC3100A, XC3000L and XC3100L devices use a simple and effective method to protect against erroneous conguration les or against loss (or gain) of CCLK pulses: All Xilinx FPGA devices recognize a new frame when its leading zero reaches the end of the shift register. XC2000, XC3000, and XC3100 devices do not check for the presence of valid stop bits, but XC3000A/XC3100A/XC3000L/ XC3100L devices always check whether the three bits at the end of the dened frame length are 111. If this check fails, INIT is pulled Low and the internal conguration is stopped, although a master CCLK keeps running. The user must recognize this state and start a new conguration by applying a >6 s Low level on RESET. This simple check does not protect against single-bit random errors, but it offers almost 100% protection against erroneous conguration les, defective conguration data sources, synchronization errors between conguration source and FPGA, as well as PC-board defects, such as broken lines or solder bridges. The XC4000 and XC5200 devices use, optionally, four bits of a running 16-bit cyclic redundancy check code at the end of each frame, combined with additional CRC bits at the end of the bit stream. These error-detecting CRC codes provide excellent protection against errors, even those that do not change the frame structure. When an error is detected, INIT goes Low and stays Low until the user initiates a reconguration. A master device does, however, continue generating CCLK pulses and even incrementing or decrementing the parallel PROM address.

Start-Up Procedure
During conguration, all outputs that are not involved in the conguration process are 3-stated, although the crystal oscillator circuit is activated as soon as possible. All internal ip-ops and latches are held reset (set or reset in XC4000), and the DONE output is held Low. At the end of conguration, these three conditions must change: As shown in detail in Figure 2, the various families offer different options: XC2000 has no options; the I/Os go active one CCLK period after length-count match. One CCLK period later, DONE goes active and the global reset is released. XC3000 makes the I/Os go active two CCLK periods after length-count match; but DONE and the release of the global reset can each occur either one CCLK period before or after the I/Os go active. The default is "early DONE and late release of the global reset". This makes the outputs go active while the internal logic is still held reset. The other option, "early release of global reset", lets the internal logic be clocked out of its reset state before the outputs go active. Normally, there is no dened timing relationship between the last conguration events triggered by the rising edge of CCLK, and the subsequent events that are controlled by the system clock. The user must be aware of the potential timing problems of this asynchronous relationship between the two clocks. See the XC4000/XC5200 solution described below. XC4000 and XC5200 have more options for the relative timing of I/Os, DONE and GSR, the release of the global set or reset.

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Length Count Match

CCLK Period

CCLK
F DONE

XC2000

I/O

Global Reset F

XC3000

DONE I/O

Global Reset F DONE C1 C2 C3 C4

XC4000/ XC5200
CCLK_NOSYNC

I/O C2 GSR Active C2 DONE IN F DONE C3 C4 C3 C4

XC4000/ XC5200
CCLK_SYNC

C1, C2 or C3 I/O

Di
GSR Active

Di+1

Di

Di+1
F

DONE C1 U2 U3 U4

XC4000/ XC5200
UCLK_NOSYNC

I/O U2 GSR Active U2 DONE IN F DONE C1 U2 U3 U4 U3 U4

XC4000/ XC5200
UCLK_SYNC

I/O

Di
GSR Active

Di+1

Di+2

Synchronization Uncertainty
Note: Thick lines are default option

Di

Di+1

Di+2

UCLK Period F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing

X5972

Figure 2: Start-up Timing

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These families can also use DONE as an input to hold off the activation of the I/Os and the release of GSR, until DONE is no longer pulled Low. The change then takes place either immediately upon the release of DONE, or as a result of the next CCLK rising edge. When all DONE pins in a daisy chain are interconnected, this start-up mode guarantees that all devices in the chain go active only when all of them have reached the DONE state, an additional protection against potential conguration errors. XC4000 and XC5200 can also be congured to employ the system (user) clock instead of CCLK, again either using DONE as an output, or as a bidirectional pin. The user clock provides a properly synchronized and racefree transition from the end of conguration to the beginning of user operation. The unspecied on-chip delay in the release of GSR (about 100 as in XC4013E) requires some caution, however, when using a high clock frequency for conguration. While devices from different families can be arbitrarily interspersed in a daisy-chain, there is one restriction: the lead device must belong to the highest-numbered family in the chain. If the chain contains XC5200 devices, the lead device cannot be XC4000, XC3000 or XC2000; if the chain contains XC4000 devices, the lead device cannot be XC3000 or XC2000; if the chain contains XC3000, then the lead device cannot be XC2000. The reason is shown in Figure 2. Since all devices in the chain store the same lengthcount value and generate or receive one common sequence of CCLK pulses, they all recognize length-count match on the same CCLK edge. The master device then generates additional CCLK pulses until it reaches its nish point F. As shown in Figure 2, the different families generate and require different numbers of additional CCLK pulses until they reach F. Not reaching F means that the device has not really nished its conguration process, although DONE may have gone High, the outputs have become active, and the internal reset has been released. For XC4000 and XC5200, not reaching F means that READBACK cannot be initiated, and most boundary scan instructions cannot be used. The limitation in daisy-chain order has been criticized by designers who want to use an inexpensive lead device in Peripheral Mode, and save the more precious XC4000 I/O pins. Here is a solution for that case (Figure 3): One CLB and one IOB in the lead XC3000 device are used to generate the additional CCLK pulse required by the XC4000 devices. When the lead device releases its internal reset signal, the 2-bit shift register starts responding to its clock input, and it generates an active Low output signal for the duration of one clock period. An external connection between this IOB pin and the CCLK pin thus creates the extra CCLK pulse. This solution requires one CLB, one IOB and pin, and an internal clock source with a frequency of up to 5 MHz. Obviously, the XC3000 lead device must be con-

OE/T Reset 0 0 1 0 1 1 0 1 0 1 etc

Output Connected to CCLK

Active Low Output Active High Output 3-Stated Output 3-Stated Output
X5552

Figure 3: Additional CCLK-Pulse Generator gured with late internal reset, which happens to be the default option.

Conguration Modes
There are six different conguration modes, hardwareselected by applying logic levels to the three mode inputs, M0, M1, and M2. The six modes are: Master Serial, Master Parallel Up, Master Parallel Down, Synchronous Peripheral (XC4000 and XC5200 only), Asynchronous Peripheral, and Slave Serial. A seventh mode, Express Mode, is only available in XC5200 devices, and is not described here. In Master modes, the FPGA addresses an external PROM or EPROM storage device, and reads data from it. No additional timing or control signals are used. In Peripheral mode, the FPGA accepts byte-wide data (bitserial in XC2000), and interacts with the source of data, usually a microprocessor, with a Ready/Busy handshake. In Slave mode, the FPGA receives bit-serial data and a clock from an external data and timing source, either from a microprocessor, or from the lead device in an FPGA-daisy chain. The modes are selected by putting the appropriate logic levels on the three mode inputs, M0, M1, and M2 prior to the beginning of conguration. These three pins can be hardwired to VCC or Ground, but they can then never be used as user I/O. It is better to force a mode pin Low with a 3 k pull-down resistor to ground, acting against the 20 to 100 k internal pull-up resistor, and to rely on the built-in pull-up resistor to establish a High level on the M1, M2 mode pins, but use a 50 k external pull-up resistor on M0. This eliminates the restrictions on using mode pins for user logic or readback. When mode pin levels are driven by external logic, these levels must be established very soon after power-up. Establishing a mode level too late might eliminate the extra master power-on delay that makes a master wait for slave devices to be ready after power-on. Delaying mode levels until the beginning of conguration will obviously cause the

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conguration to fail. Note that some CPLD devices have surprisingly long power-up delays. Be very careful when controlling mode levels in any creative way.

Selecting the Best Conguration Mode

The selection of the most appropriate conguration mode is inuenced by many factors, like the need for interface simplicity, the need for rapid conguration, the need for multiple conguration sources, the availability of a microprocessor-based conguration driver.

The simplest interface is Master Serial, using only two FPGA pins, CCLK and DIN, and no external timing or control signals. The fastest conguration mode is Slave Serial or XC4000/ XC5200 Synchronous Peripheral. In these modes, the user can supply a well-dened CCLK frequency of up to 10 MHz for 5-Volt devices. Only Express mode can be faster than that. For prototyping and rapid conguration change, the PC can congure the FPGA directly in Slave Serial mode, using the Xilinx-provided Download Cable or XChecker. Multiple conguration codes are most conveniently stored in a microprocessor memory, using Peripheral mode to congure the FPGA. Peripheral mode also offers the greatest exibility for eld upgrades. New les can be supplied via diskette or modem, and can be downloaded by the microprocessor.

When Conguration Fails

General Debugging Hints for all Families
If the DONE output does not go High, there are several things to check. Checking all supply and conguration-related pins with an oscilloscope or logic analyzer can reveal wiring errors, bad socket pins, noisy ground, noisy CCLK, a serial conguration PROMs VPP pin not connected to VCC, PWRDWN not pulled High, poor or noisy RESET, missing pull-up resistors on DONE (or INIT in the XC3000), bad levels on mode pins, etc. Check all pins: Any dc voltage between 0.5 V and 3.0 V is a sign of serious trouble. Monitor the DOUT pin of the lead device, i.e. the FPGA that is either congured alone, or forms the beginning of a daisy chain. At the start of conguration, you should see the 40 (or 48)-bit header shown in Figure 1. After this sequence, the DOUT pin remains High until the device has received all its data. Then, the device becomes transparent and passes additional data (provided there is a daisy chain) through the DOUT pin to the Slave devices. If you dont see this pattern, you have a gross error somewhere. Check the following

items: INIT going Low again after conguration start indicates a conguration bitstream or framing error. If RESET is used to delay conguration, make sure it has a rise time of <100 ns and that it is glitch-free. Ringing on the CCLK line, caused by pc-board reections, can result in spurious double- clocking and loss of frame synchronization in the FPGA. Conguration functions can be disrupted by signal contention between conguration inputs and the FPGA user outputs which become active at the end of conguration. This change is indicated by I/O pins going active and HDC/LDC no longer at their conguration levels. Contention can be avoided by rearranging pin-outs, maintaining additional 3-state control of user-I/O outputs, or matching start-up output levels to the conguration input levels on inputs other than chip-select. As a last resort, it is also possible to use a series resistor (1-10 k) to provide isolation between conicting signal sources that could occur after conguration is complete. If an FPGA heats up signicantly, this is usually the result of applying the wrong bitstream, e.g. the bitstream for a different device, causing contention. Legitimate bitstreams have been screened by the Design Rule Checker software, and are guaranteed free of inherent contention problems, provided the conguration is loaded into the designated device. The user can obviously still cause contention on internal Longlines and on connections outside the device. During reprogramming, user logic must generate a time-out that insures all devices have completed the Clear cycle before any conguration data is sent. Removing the FPGA supply voltage while externally powered signals continue to drive input pins, might keep the FPGA VCC pins at a 0.5-to-2.0 V level, which can leave the FPGA in an invalid state. The FPGA input-protection diodes are there to clamp input-voltage excursions to the two supply connections. When the FPGA supply voltage falls more than 0.5 V below an active input signal, this input signal will supply degenerate VCC levels. If the input signals are not current-limited, the FPGA inputs can even be damaged by the excessive input current. If extraneous CCLK pulses are applied after Clear but before the beginning of the header, they are counted internally, and the internal clock count will then become equal to the stored length-count value before the conguration data is completely loaded. In this case, the DONE output does not become active until the clock counter equals length count a second time. This requires 224 extra clocks, about 20 s at the typical rate of 0.7 MHz, or about 2 seconds at the nominally 8-MHz fastest CCLK rate. Whenever conguration takes several or many seconds, this is due to a mismatch between length count and the number of CCLK pulses

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received. XChecker or the XACT Download Cable provide an alternate method of conguration to verify conguration data and to isolate wiring errors, such as interchanged or inverted conguration data or control signals. Try a different device. Although the chips are 100% factory-tested, an individual device might have been damaged after the test.

FPGA output. Verify that the FPGA is sending addresses to the PROM. If it is not, check the FPGA mode pins. M0 = 0, M1 = 0, M2 = 1 for Master Parallel Up M0 = 0, M1 = 1, M2 = 1 for Master Parallel Down Make sure VCC, RESET and PWRDWN are close to VCC and all ground pins are at 0 V.

General Debugging Hints for the XC2000 and XC3000 Families

An undened (oating) or active Low PWRDWN during conguration can disturb the operation. A Low level on PWRDWN immediately before the start of conguration causes problems in XC2000, forces XC3000 into Slave mode, but is acceptable in XC3000A and L. In the XC2000 and XC3000 families, the congurationclock input signal drives quasi-static circuitry that does not function correctly with a Low time of more than 5 ms. At power-up, make sure VCC rises in 25 ms or less. If this cannot be guaranteed, hold RESET active on the FPGAs and on the serial PROMs until VCC has reached 4.5 V. A slowly rising or noisy RESET can cause multiple FPGAs to get out of synchronization. Always debounce reset switches.

Check that the PROM is receiving addresses and is sending out data. If it is not, check that the PROM is enabled and has VCC and ground connected, and verify that the PROM is programmed with the correct data. Check for contention between the PROM address or data pins and other signals on the board. Check that the FPGA is addressing the correct memory segment. In Master Parallel Up mode, the FPGA starts at address 0000 hex and counts up; in Master Parallel Down mode it starts at address FFFF hex (3FFFF hex in XC4000) and counts down. If the PROM requires different addressing, that must be taken care of by external hardware. Check for ringing and noise on address and data lines. Make sure the data in the PROM is correct. You can check it against the Rawbits le. Review the general debugging hints. Verify that the FPGA is generating a clock signal on its CCLK pin and that this signal is reaching the CLK pin of the XC1700-series Serial-Conguration PROM. If it is not, check the mode pins. M0 = 0, M1 = 0, M2 = 0 for Master Serial mode

Master Serial Mode

General Debugging Hints for the XC4000 and XC5000 Families

At power-up, make sure VCC rises in 25 ms or less. If this cannot be guaranteed, hold PROGRAM or INIT active Low on the FPGAs and hold the serial PROMs reset until VCC has reached 4.5 V. The boundary scan input pins are active during conguration, even if boundary scan is not used in the design. Toggling TCK, TMS and TDI during conguration might send the device into EXTEST mode, which interferes with conguration. Keeping at least one of these three inputs continuously High during conguration avoids this problem.

Verify that the XC1700-series Serial Conguration PROM is sending data. If it is not, check that power and ground are applied to the Serial PROM, and VPP is connected to VCC.

Do Not Let the VPP Pin Float

A oating VPP pin results in temperature-dependent operation, the most notorious cause of unreliable conguration. Check that the DATA pin of the Serial PROM is connected to the DIN pin of the FPGA, and that the PROM is enabled with CE Low and OE active. Note that the OE/RESET pin is programmable for either polarity. Check whether this pin is driven from the INIT output. This is the preferred method of guaranteeing SPROM reset. Verify that the PROM is programmed with the correct data. At power-up, make sure VCC rises from 2.0 V to 4.5 V in

Additional Mode-Specic Debugging Hints for All Families

Master Parallel Up and Down Mode
Review the general debugging hints. Check that the PROM data pins are connected to the FPGA input pins D0-D7. Check that the PROM address pins are connected to the FPGA output pins A0-A15. Verify that all these connections are in the right order. Monitor the FPGA pins, not the socket pins. Make sure the socket is good. If the PROM is dedicated to the FPGA, the CS and OE PROM inputs should be driven from the DONE or LDC

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less than 25 ms. If it does not, hold the FPGA RESET and the PROM RESET active until VCC reaches 4.5 V. A typical result of a slow VCC rise time is that the FPGA sends out CCLK continuously, the CEO pin on the PROM(s) goes Low, but the DONE pin never goes High. If you abort conguration by asserting XC3000 RESET or by pulling XC4000/XC5000 PROGRAM Low, you must also reset the serial PROM by asserting its RESET. This occurs automatically if the SROM is reset from INIT.

signals on the board. Except in XC2000, data is received as eight bits in parallel. Make sure bit 0 is connected to the D0 pin, bit 1 to D1 pin, etc. (In XC2000 family, data is received serially. If a PROM le is used as a data source, check that data is properly serialized LSB rst. Data must be LSB rst, although length count is MSB rst. This is not intuitively obvious.)

Slave Serial Mode

Review the general debugging hints. Check the mode pin levels. M0 =1, M1 = 1, M2 = 1 for Slave Serial mode See schematics in the data sheet for the FPGA family. Make sure Vcc, RESET, and PWRDWN are at 5 V, and ground pins are at 0 V. Verify that the FPGA is receiving data on DIN and that it is receiving a valid clock signal on CCLK. Check the device sending the data. Check the device sending the clock signal, and make sure the clock meets the timing requirements specied in the product family documentation. Dont violate the XC3000 and XC2000 CCLK Low time specication of 5.0 s. A CCLK generated by a Master FPGA automatically meets the timing requirements. Make sure the FPGA is ready to receive data. XC3000 Family: On power up, make sure the INIT pin is High or wait at least 34 ms before you begin sending data to the FPGA. XC2000 Family: On power up, make sure that the FPGA has had time to wake up at least 34 ms, before sending it data. At power up, make sure VCC rises from 2.0 V to 4.5 V in less than 25 ms. If it does not, hold RESET Low until the VCC pins reach 4.5 V.

Asynchronous Peripheral Mode

Review the general debugging hints. Check the mode pin levels. M0 = 1, M1 = 0, M2 = 1 for Peripheral mode Use an external 1 kilohm resistor from READY/BUSY pin to ground. On power-up, before the FPGA has interrogated the mode lines, this prevents the pin from being pulled High by its internal pull-up, which would give an early erroneous READY signal. Verify that the FPGA is receiving data at its input pin(s) and that it is receiving valid Write-Strobe and ChipSelect signals. If not, check the device driving the FPGA. Make sure that these signals meet the timing requirements listed in the product family documentation. XC3000 Family: Check that the minimum Write-Strobe active time (TCA min = 100 ns) is met and observe the RDY/BUSY signal. XC2000 Family: Be sure maximum and minimum Write-Strobe active times (TCA max = 5.0 ms, min = 0.25 ms) are met. Make sure that the FPGA is ready to receive data. XC3000 Family: On power up, make sure that the INIT pin has gone High, or wait at least 34 ms before you begin sending data to the FPGA. Make sure that the RDY/BUSY signal is High before sending each data byte. XC2000 Family: On power up, make sure that the FPGA has had time to "wake up," at least 34 ms, before sending it data. Check for contention between the Chip Select and Write Strobe signals and monitor the levels on those pins after conguration. It is safest to use the Chip Select pins only as inputs after conguration. Avoid contention if they are used as outputs. With XC2000 family devices, the I/Os become active before the FPGA receives its nal data bits and clocks, and also before the DONE pin goes High. In other families, this relative timing is programmable. If the user function for any of the Chip Selects or the Write Strobe become outputs after conguration, they might contend and, in effect, de-select the FPGA so that it never receives its nal data bits. Beware of contention! Check for contention between the FPGA pins and other

Daisy Chain Debugging Hints

The key to debugging daisy-chain congurations is to isolate the problem and attempt to congure a single FPGA. Remove all but the rst device from the board and congure it. Then insert the second device and congure both. Repeat as you add one device at a time until they all congure. The rst device in the chain can be in any of the conguration modes. Debug it rst, using the hints provided for the appropriate mode. All devices after the rst one are in Slave Serial mode, so refer to the Slave Serial mode debugging hints above to solve any problems with Slave device. Monitor the DOUT pin of each device in the chain and verify that the 40-bit header (48-bit with XC5200 as the lead device) appears at the beginning of conguration, staggered by one CCLK period per device. If the Master device in the chain is an XC2000-family device and the Slaves are XC3000-family, make sure

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the XC3000-family devices are congured with early DONE.

Miscellaneous Notes
CCLK is the most important conguration signal. Once the INIT output is High, each device counts every Low-to-High transition of this conguration clock. In all modes except Slave Serial and Synchronous Peripheral, CCLK is a very fast output that cannot be made slew-rate limited. (it is now slew-rate limited in the newest XC4000X and XC5200 devices). When distributing this clock, the user should pay special attention to glitches, overshoots, and undershoots. In severe cases, a 33 resistor in series with the CCLK output might improve the signal integrity. In other cases, it might be better to provide a pull-up resistor at the far end of the CCLK net. Since the clock net has a transmission-line characteristic impedance of always less than 100 , the limited output drive capability of the CCLK output precludes proper parallel termination. DOUT is an excellent observation point, since every device must output the preamble on this pin, irrespective of the selected conguration mode, and irrespective of the position in, or the existence of, a daisy chain. INIT of all devices in a daisy chain should be interconnected to prevent the conguration from starting before all devices are ready. A 10 k pull-up resistor is recommended. The parallel INIT of the daisy-chained devices must be connected to the INIT of the lead XC4000/XC5200 device, or to the RESET input of the lead XC3000 device. This is especially important for re-conguration, where the master does not have a four-times longer wait period. The DONE output indicates the end of the conguration process. In XC2000 and XC3000 systems, it makes sense to ground DONE permanently. The RESET input then becomes the reconguration input, and cannot be used as the dedicated asynchronous user RESET input. LDC can be used to indicate end of conguration. PWRDWN (on XC2000 and XC3000 devices) must be High before and during the conguration process. Dont let PWRDWN oat!

Potential Length-Count Problem in Parallel or Peripheral Modes

It is highly desirable that the complete change from conguration to user operation occur as the result of one single byte-wide input. The activation of outputs and DONE, the de-activation of the global reset (set/reset in XC4000), and the progression to the nished state F (see Figure 2) should all occur as a result of one common byte input. Under normal circumstances, the software achieves this by manipulating the length-count value appropriately, taking into account the additional bits between devices, and adjusting for the fact that byte-wide interfaces always leave the last bit sitting in the P-S converter, shifting it out at the beginning of the next byte. These complexities, combined with the many possible daisy-chain arrangements have occasionally led to problems, where the device outputs go active before the last required byte had been received. This has sometimes lead to contention on the address outputs or data inputs and might prevent the device from going DONE, or reaching the real end of its conguration sequence. Not reaching this nished state limits the use of readback and boundary scan. A new option solves this problem: The default option is Length-Count aligned which adjusts the length-count value such that length-count match occurs during the rst bit in the last conguration byte. This assures sufcient CCLK pulses to complete any selected type of start-up sequence. The other option is DONEaligned, which adjusts the length count value to make DONE go active at the end of a conguration data byte, which can cause problems in Peripheral mode. Only Peripheral modes seem to be sensitive to the difference between these two options.

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APPLICATION NOTE

Conguring Mixed FPGA Daisy Chains

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XAPP 091 November 24, 1997 (Version 1.0)

Application Note by Peter Alfke

Length Count Match

Overview
Xilinx FPGAs can be congured in a common daisy-chain structure, where the lead device generates CCLK pulses and feeds serial conguration information into the next downstream device, which in turn feeds data into the next downstream device, etc. There is no limit to the number of devices in a daisy chain, and XC2000, XC3000, XC4000, and XC5200 series devices can be mixed freely with only one constraint: the lead device must be a member of the highest-order family used in the chain. (For the purposes of this discussion, there is no difference between the XC4000 series and the XC5200 family, when XC5200 is used in any conguration mode except Express Mode). The lead device must generate a sufcient number of CCLK pulses after length-count-match was achieved, but XC3000-series devices generate fewer CCLK pulses than XC4000-series or XC5200-family devices require, and XC2000 devices generate even fewer CCLK pulses after length-count match. See Figure 1. In a daisy-chain, all CCLK pins are interconnected, and DOUT of any upstream device feeds the DIN input of its downstream neighbor. Those are the basic connections. For control purposes, it is advisable to interconnect all the slave INIT pins (the XC2000 does not have this pin) and connect them to the INIT pin of the lead XC4000/XC5200 device or the RESET input of the lead XC3000 device. Interconnected INIT pins prevent the master from starting the conguration process until all slaves are ready. For power-up this is assured automatically, since the master uses four times as many internal clocks for the power-up as any slave does, but, when re-conguring, master and slave devices consume the same number of clocks to clear a frame, and a fast master might be ready before a slow slave is. Interconnecting INITs solves this problem. The DONE/PROG (D/P) and RESET pins (XC2000, XC3000) and the XC4000/XC5200 PROGRAM pins can be used in different ways, depending on the designers preferences regarding reconguration, pin utilization, and need for a global RESET input. If there is no need for a global logic RESET input, then it is best to permanently ground the XC2000/3000 D/P pin, which means that the RESET input functions as the Recongure input, and should be connected to all XC4000/ XC5200 PROGRAM inputs.
CCLK

CCLK Period

F DONE

XC2000

I/O

Global Reset F

XC3000

DONE I/O

Global Reset F DONE C1 C2 C3 C4

XC4000/ XC5200
CCLK_NOSYNC

I/O C2 GSR Active C2 DONE IN F DONE C3 C4 C3 C4

XC4000/ XC5200
CCLK_SYNC

C1, C2 or C3 I/O

Di
GSR Active

Di+1

Di

Di+1
F

DONE C1 U2 U3 U4

XC4000/ XC5200
UCLK_NOSYNC

I/O U2 GSR Active U2 DONE IN F DONE C1 U2 U3 U4 U3 U4

XC4000/ XC5200
UCLK_SYNC

I/O

Di
GSR Active

Di+1

Di+2

Synchronization Uncertainty
Note: Thick lines are default option

Di

Di+1

Di+2

UCLK Period F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing

X5972

Figure 1: Start-up Timing

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VCC 5K REPROGRAM GLOBAL RESET 5K From All INIT Pins Wired Together To RESET of Lead Device
X5982

To All D/P Wired Together To All RESET, Except Lead Device

put) and that, if Serial mode is chosen for the lead device, the XC1700 device(s) store only one conguration for the whole daisy chain. The serial PROM(s) must, therefore, be reset before the daisy chain is to be (re)programmed. There are three possible types of daisy chains using XC3000 and XC4000/XC5200 devices. Here are the recommended connections for the conguration control pins. Case 1: Daisy chain consists of nothing but XC3000-series devices: Use lead devices LDC to drive XC1700 CE. Use lead devices INIT to drive XC1700 RESET. Interconnect all slave INITs and connect them to the lead RESET input. Interconnect all DONE pins. Interconnect all slave RESET inputs Instigate Reprogram by pulling the slave RESET net Low for at least 6 s while all DONE pins are Low. (DONE can be permanently wired Low, but that sacrices the use of RESET as a global reset of the user logic. If DONE is not wired Low, reprogram must pull DONE Low with an open-collector or open-drain driver). Case 2: Lead device is XC4000-series or XC5200 family, driving any mixture of XC3000, XC4000 and XC5200 devices: Use lead devices LDC to drive XC1700 CE. Use lead devices INIT to drive XC1700 RESET. Interconnect all INIT pins. Interconnect all DONE pins. Interconnect all XC4000/XC5200 PROGRAM inputs. Interconnect all XC3000 RESET inputs. Combine these two nets into one PROGRAM/RESET net Instigate Reprogram by pulling the combined PROGRAM/ RESET Low. Case 3: Daisy chain consists of nothing but XC4000/ and XC5200-type devices: Use lead devices LDC to drive XC1700 CE. Use lead devices INIT to drive XC1700 RESET. Interconnect all INIT pins. Interconnect all DONE pins (only required for UCLK-SYNC option). Interconnect all XC4000/XC5200 PROGRAM inputs. Instigate Reprogram by pulling PROGRAM Low.

VCC

Figure 2: If there is a need for a global logic RESET input that can reset all ip-ops in the user logic without causing reconguration, then external logic must combine RESET and D/P in such a way, that pulling Low RESET does not affect D/P, but pulling Low D/P also pulls down RESET. See Figure 2. The following simple recommendations guarantee a welldened beginning for any FPGA conguration or reconguration process, after the initialization and clearing of the conguration memory in all FPGAs has been completed, and the address counter in the serial PROM(s) has been reset. The connections described below guarantee reliable operation even under adverse operating conditions such as VCC glitches. The lead device can use any conguration mode available. In all modes except Slave Serial, its CCLK pin is the output that clocks all other devices. Obviously, all CCLK and XC1700 CLK pins must be interconnected, the DATA outputs from multiple XC1700 serial PROMs must be interconnected and connected to the DIN input of the lead device, and the daisy-chain must be established by connecting each DOUT output to the downstream DIN input.

Conguration control pins are:

XC3000A, XC3000L, XC3100, XC3100A: DONE/PROGRAM (open-drain output/input) RESET (input) INIT (open-drain output) XC4000 Series (XC4000E, XC4000X) and XC5200 family: DONE (open-drain output / input) PROGRAM (input) INIT (open-drain output / input) XC1700: RESET (input with programmable polarity) The following recommendations assume that there are no XC2000 devices in the daisy chain (they lack the INIT out-

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APPLICATION NOTE

Conguration Issues: Power-up, Volatility, Security, Battery Back-up

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XAPP 092 November 24, 1997 (Version 1.1) Summary

Application Note by Peter Alfke

This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to powersupply glitches? Is there any danger of picking up erroneous data and conguration? What can be done to maintain conguration during loss of primary power? What can be done to secure a design against illegal reverse-engineering? Xilinx Families XC2000, XC3000, XC4000, XC5200

Power-Up
Here is a detailed description of XC3000 Series, XC4000 Series and XC5200 device behavior during supply ramp-up and ramp-down. When Vcc is rst applied and is still below about 3 V, the device wakes up in the pre-initialization mode. HDC is High; INIT, LDC and DONE or DONE/PROG (D/P) are Low, and all other outputs are 3-stated with a weak pull-up resistor. When VCC has risen to a value above ~3 V, and a 1 and a 0 have been successfully written into two special cells in the conguration memory, the initialization power-on time delay is started. This delay compensates for differences in VCC detect threshold and internal CCLK oscillator frequency between different devices in a daisy chain. The initialization delay counts clock periods of an on-chip oscillator (CCLK) which has a 3:1 frequency uncertainty depending on processing, voltage and temperature. Timeout, therefore, takes between 11 and 33 ms for a slave device, four times longer for a master device. This factor of four makes sure that even the fastest master will always take longer than any slave. We assume that the worst- case difference between 33 ms and 4 x 11 ms is enough to compensate for the VCC rise time spent between threshold differences (max 2 V) of devices in a daisy chain. Only in cases of very slow VCC rise time (>25 ms), must the user hold RESET Low until VCC has reached a proper level. Interconnecting the INIT pins of all devices in a daisy-chain is a better method of synchronizing start-up, but cannot be used with XC2000 devices, since they lack an INIT pin. After the end of the initialization time-out, each device clears its conguration memory in a fraction of a millisecond, then tests for inactive RESET or PROGRAM, stores the MODE value and starts the conguration process, as described in the Data Sheet. After the device is congured, the 5-V VCC may dip to about 3.5 V without any signicant consequences beyond an increase in delays (circuit speed

is proportional to Vcc), and a reduction in output drive. If Vcc drops into the 3-V range, it triggers a sensor that forces the device back to the pre-initialization mode described above. All ip-ops are reset, HDC goes High; INIT, LDC and D/P or DONE go Low, and all other outputs are 3-stated with a weak resistive pull-up. If VCC dips substantially lower, the active outputs become weaker, but the device stays in this preinitialization mode. When VCC rises again, a normal conguration process is initiated, as described above.

Sensitivity to VCC Glitches

The user need not be concerned about power supply dips: The XC3000/XC4000/XC5200 devices stay congured for small dips and they are smart enough to recongure themselves (if a master) or to ask for reconguration by pulling INIT and D/P or DONE Low (if a slave). The devices will not lock up; the user can initiate re-conguration at any time just by pulling D/P or PROGRAM Low or, if D/P is Low, by forcing a High-to-Low transition on RESET. Any digital logic device with internal data storage in latches or ip-ops is sensitive to power glitches. This includes every RAM, microprocessor, microcontroller, and peripheral circuit. Only purely combinatorial circuits can be guaranteed to survive a severe power glitch without any problem. Xilinx SRAM-based FPGAs store their conguration in latches that lose their data when the supply voltage drops below a critical value (which is substantially below 3 V for the 5-V devices), but conguration data is extremely robust and reliable while VCC stays above 3 V. All Xilinx conguration latches are implemented as cross-coupled complementary inverters with active pull-down n-channel transistors and active pull-up p-channel transistors. Both High and Low logic levels have an impedance of less than 5k with respect to their respective supply rail. Typical SRAM memory devices use passive poly-silicon pull-up resistors with an impedance of about 5,000 M. A

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Conguration Issues: Power-up, Volatility, Security, Battery Back-up

current of one nanoamp (!) is sufcient to upset the typical SRAM cell, whereas it takes a million times more current to upset the Xilinx conguration latch. This does not mean that SRAMs are unreliable, it just shows that the levels in Xilinx conguration latches are six orders of magnitude more resistant to upsets caused by external events, like cosmic rays or alpha particles. Xilinx has never heard about any occurrence of a spontaneous change in the conguration store in any of its ~50 million FPGA devices sold over the past twelve years. Whereas most digital circuits rely on Vcc staying within specication, Xilinx FPGAs have an internal voltage monitoring circuit. For example, in the 5-Volt devices, whenever the supply voltage dips below 3 V, the internal monitoring circuit causes the Xilinx FPGA to stop normal operation. All outputs go 3-state, and the device waits for the supply voltage to rise closer to 4 V, when it either demands (slave or peripheral mode) or initiates (master mode) a reconguration. In the range between 5.5 and 3 V, all typical CMOS devices maintain their functionality and their data storage, they just get slower as the voltage goes down. Xilinx has made sure that the FPGA cannot be corrupted by a power glitch. The most sensitive circuit is the low-voltage detector. It kicks in while all other conguration storage and user logic is still guaranteed to be functional. The voltagemonitoring feature in the Xilinx device can even be used to protect other circuitry, or it can be coordinated with external monitoring circuits. There is no possibility of a VCC dip causing the device to malfunction, i.e., to operate with erroneous conguration information. If VCC stays above the trip point, the device functions normally, albeit at reduced speed, like any other CMOS device. If VCC dips below the trip point, the device 3-states all outputs and waits for reconguration.

tor or other control register due to an undetected power glitch, with disastrous consequences to the subsequent operation. A Xilinx FPGA detects the power glitch and always plays it safe by agging the problem. No complex system of any kind can function reliably when Vcc is unreliable. Xilinx FPGAs do the safest thing possible, whenever such problems occur.

Design Security
Some Xilinx customers are concerned about the security of their designs. How can they protect their designs against unauthorized copying or reverse-engineering? We must distinguish between two very different situations: Conguration data in accessible from a serial or parallel EPROM or in a microprocessor's memory. This is the normal case. Conguration data is hidden from the user, since the design does not permanently store a source of conguration data. After the FPGA was congured, the EPROM or other source was removed from the system, and conguration is kept alive in the FPGA through battery-back-up.

Design Security when Conguration Data is Accessible

In the rst case, it is obviously very easy to make an identical replica of the design by copying the conguration data and the pc-board interconnect pattern of the standard devices, but it is virtually impossible to interpret the bitstream in order to understand the design or make intelligent modications to it. Xilinx keeps the interpretation of the bitstream a closely guarded secret. Reverse-engineering an FPGA would require an enormously tedious analysis of each individual conguration bit, which would still only generate an XACT view of the FPGA, not a usable schematic. The best protection against a mindless copy is legal. The bitstream is easily protected by copyright laws that have proven to be more successfully enforced than the intellectual property rights of circuit designs. The combination of copyright protection, and the almost insurmountable difculty of creating any design variation for the intended function, provides good design security. The recent successes of small companies in reverse-engineering microprocessors and microprocessor support circuits show that a non-programmable device can actually be more vulnerable than an FPGA. For advice on legal protection of the conguration bitstream, see the following paragraphs.

Xilinx production-tests the VCC-dip tolerance of all XC3000 devices in the following way. After the device is congured, VCC is reduced to 3.5 V, and then raised back to 5.0 V. Conguration data is then read back and compared against the original conguration bit stream. Any discrepancy results in rejection of the device. Subsequently, VCC is reduced to 1.5 V and then raised to 5.0 V. The device must rst go 3-state, then respond with a request for reconguration. Both these tests are performed at high temperature (>85C for commercial parts, >100C for military). Any part failing any of these tests is rejected as a functional failure. As a result of these careful precautions, we contend that Xilinx FPGAs are safer than all other types of circuitry (except purely combinatorial circuits). A microprocessor can loose the content of its address register, its accumula-

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XAPP 092 November 24, 1997 (Version 1.1)

Legal Protection of Conguration Bit-Stream Programs The bit-stream program loaded into the FPGA may qualify as a computer program as dened in Section 101, Title 17 of the United States Code, and as such may be protectable under the copyright law. It may also be protectable as a trade secret if it is identied as such. We suggest that a user wishing to claim copyright and/or trade secret protection in the bit stream program consider taking the following steps. Place an appropriate copyright notice on the FPGA device or adjacent to it on the PC board to give notice to third parties of the copyright. For example, because of space limitations, this notice on the FPGA device could read 1996 XYZ Company or, if on the PC board, could read Bit Stream )1996 XYZ Company. File an application to register the copyright claim for the bit-stream program with the U.S. Copyright Office. If practicable, given the size of the PC board, notice should also be given that the user is claiming that the bit- stream program is the user's trade secret. A statement could be added to the PC board such as: Bitstream proprietary to XYZ Company. Copying or other use of the bitstream program except as expressly authorized by XYZ Company is prohibited. To the extent that documentation, data books, or other literature accompanies the FPGA-based design, appropriate wording should be added to this literature providing third parties with notice of the user's claim of copyright and trade secret in the bit-stream program. For example, this notice could read: Bit-Stream)1996 XYZ Company. All rights reserved. The bit-stream program is proprietary to XYZ Company and copying or other use of the bit- stream program except as expressly authorized by XYZ Company is expressly prohibited. To help prove unauthorized copying by a third party, additional nonfunctional code should be included at the end of the bit-stream program. Therefore, should a third party copy the bit-stream program without proper authorization, if the non-functional code is present in the copy, the copier cannot claim that the bit-stream program was independently developed. These are only suggestions, and Xilinx makes no representations or warranties with respect to the legal effect or consequences of the above suggestions. Each user is advised to consult legal counsel with respect to seeking protection of a bit-stream program and to determine the applicability of these suggestions to the specic circumstances. If the user has any questions, contact the Xilinx legal department at 408-879-4984.

Design Security by Hiding the Conguration Data

If the design does not contain the source of conguration data, but relies on battery-back-up of the FPGA conguration, then there is no conceivable way of copying this design. Opening up the package and probing thousands of latches in undocumented positions to read out their data without ever disturbing the conguration is impossible. This mode of operation offers the ultimate design security. It is being used by several Xilinx customers who have reason to be concerned about illegal pirating of their designs.

Battery Back-up and Powerdown

Since SRAM-based FPGAs are manufactured using a high-performance low-power CMOS process, they can preserve the conguration data stored in the internal static memory cells even during a loss of primary power. This is accomplished by forcing the device into a low-power nonoperational state, while supplying the minimal current requirement of VCC from a battery. Circuit techniques used in XC3100, XC4000 and XC5200 devices prevent ICC from being reduced to the level needed for battery back-up. Consequently, battery back-up should only be used for XC2000, XC2000L, XC3000, XC3000A and XC3000L devices. There are two primary considerations for battery backup which must be accomplished by external circuits. Control of the Power-Down (PWRDWN) pin Switching between the primary VCC supply and the battery.

Important considerations include the following. Insure that PWRDWN is asserted logic Low prior to VCC falling, is held Low while the primary VCC is absent, and returned High after VCC has returned to a normal level. PWRDWN edges must not rise or fall slowly. Insure glitch-free switching of the power connections to the FPGA device from the primary VCC to the battery and back. Insure that, during normal operation, the FPGA VCC is maintained at an acceptable level, 5.0 V 5% (10% for Industrial and Military).

Figure 1 shows a power-down circuit developed by Shel Epstein of Epstein Associates, Wilmette, IL. Two Schottky diodes power the FPGA from either the 5.2 V primary supply or a 3 V Lithium battery. A Seiko S8054 3-terminal power monitor circuit monitors VCC and pulls PWRDWN Low whenever VCC falls below 4 V.

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Conguration Issues: Power-up, Volatility, Security, Battery Back-up

Things to Remember:
Seiko S8054 Specifications Detect Voltage 3.995 V min 4.305 V max 208 mV typ Hysteresis Temp. Coeff. 0.52 mV/C 2.6 A typ ICC @ + 6V

VCC IN5817

IN5817 B35 Lithium Battery

Powerdown retains the conguration, but loses all data stored in the device. Powerdown three-states all outputs and ignores all inputs. No clock signal will be recognized, and the crystal oscillator is stopped. All internal ip- ops and latches are permanently reset and all inputs are interpreted as High, but the internal combinatorial logic is fully functional.

2 SEIKO 1 PWRDWN S 8054 3

VCC FPGA

Things to Watch Out for:

Make sure that the combination of all inputs High and all internal ip-op outputs Low in your design will not generate internal oscillations or create permanent bus contention by activating internal bus drivers with conicting data onto the same long line. These two situations are farfetched, but they are possible and will result in considerable power consumption. It is quite easy to simulate these conditions since all inputs are stable and the internal logic is entirely combinatorial, unless latches have been made out of function generators. During powerdown, the VCC monitoring circuit is disabled. It is then up to the user to prevent VCC dips below 2.3 V, which might corrupt the stored conguration. During conguration, the PWRDWN pin must be High, since conguration uses the internal oscillator. Whenever VCC goes below 4 V, PWRDWN must already be Low in order to prevent automatic reconguration at low VCC. For the same reason, VCC must rst be restored to 4 V or more, before PWRDWN can be made High. PWRDWN has no pull-up resistor. A pull-up resistor would draw supply current when the pin is Low, which would defeat the idea of powerdown, where ICC is only microamperes.

X5997

Figure 1: Battery Back-up Circuit

Powerdown Operation
A Low level on the PWRDWN input, while VCC remains higher than 2.3 V, stops all internal activity, thus reducing ICC to a very low level: All internal pull-ups (on Long lines as well as on the I/O pads) are turned off. The crystal oscillator is turned off All package outputs are three-stated. All package inputs ignore the actual input level, and present a High to the internal logic. All internal ip-ops or latches are permanently reset. The internal conguration is retained. When PWRDWN is returned High, after VCC is at its nominal value, the device returns to operation with the same sequence of buffer enable and D/P as at the completion of conguration.

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APPLICATION NOTE
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APPLICATION NOTE

Dynamic Reconguration
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XAPP 093 November 10, 1997 (Version 1.1)

Application Note by Peter Alfke

Introduction
All Xilinx SRAM-based FPGAs can be in-system congured and re-congured an unlimited number of times. The XC6200 family has additional features that allow partial and very fast (re-)conguration from a microprocessor bus. See the XC62000 product documentation for details. This application note describes the procedures for reconguring the more traditional Xilinx FPGAs of the XC3000, XC4000, and XC5200 families. All conguration information is stored in latches that are loaded serially, conceptually like a shift register. There are several different bit-serial or byte-parallel conguration data interfaces, selected by logic levels on three mode inputs, but with the exception of the XC5200 Express mode they all result in the bit-serial loading of the conguration latches. The byte-parallel interfaces in Master Parallel and Peripheral modes act just as an 8-bit parallel-to-serial converter. Between devices in a daisy-chain, the conguration information is transmitted bit-serially with a common Conguration Clock (CCLK). In Master and Peripheral modes, CCLK is generated by the lead FPGA device, in Slave Serial mode, CCLK comes from an external source. Reconguration of an operational device, or a daisy-chain of devices, goes through the following sequence of events: Reconguration is initiated by pulling a specic device pin Low. First, all outputs are 3-stated, except HDC = High, LDC and DONE = Low Then, all internal registers, ip-ops and latches, as well as the conguration storage latches are cleared. During this time, the INIT output is being pulled Low. Then, the Mode inputs and RESET or PROGRAM inputs are sampled to determine the selected conguration mode and whether to start the new conguration process, or to wait. Then conguration data is accepted and loaded into the internal latches and distributed through the daisy-chain. When all conguration information has been entered, the user outputs are activated, DONE goes High and the internal reset is released, all in the order specied in the conguration bitstream. All devices in a daisy-chain perform each of these operations in synchronism.

Important Considerations
Reconguration is all or nothing. There is no way to restrict reconguration to a part of the chip (Note that XC6200 devices do not have this limitation). Reconguration takes a specic time, determined only by device type, size and clock speed, independent of the particular conguration pattern. Conguration takes from tens to hundreds of milliseconds. During that time, all user-outputs of the device, or the whole daisy-chain of devices, are 3-stated with weak internal pull-ups, except for HDC and LDC, which are active High or Low respectively. All user-data stored in registers, ip-ops or latches is erased. There is no way to retain data inside the device from one conguration to the next. These limitations are absolute. If they are not acceptable, the user must resort to creative solutions, like piggy-backing multiple devices. The designer of recongurable applications should be familiar with the normal conguration process of each device, as described in the individual product descriptions. There is also pertinent information about daisy-chain operation, especially about mixed daisy chains, in other application notes. Interconnecting the INIT pins of all devices in a daisy-chain is mandatory for reconguration, since this is the only way to guarantee that the master device does wait for the rest of the daisy-chain to be cleared, before starting the reconguration. Only the rst conguration after power-up makes the master device spend four times as many clock periods as any slave during the initial clear operation, so that the master cannot possibly get ahead of the slaves. Reconguration, however, does not slow down the master this way, so the interconnection of all INIT pins must serve that same purpose. In Master Serial mode, it is highly recommended that the active Low level of INIT be used to reset the XC1700-family Serial PROM.

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Reconguration Time
Reconguration time is usually more critical than the original power-on conguration time, which is often masked by the general power-on delays. Here are some suggestions to reduce reconguration time. A daisy-chain is obviously not conducive to fast conguration, it should be broken up into shorter blocks, perhaps single devices. Multiple devices can be congured in parallel, but can still use a common CCLK, and can also be made to start up together. If the devices differ in size or family, they should all be given the same length count as the largest device in the group. Conguration Mode Parallel and Peripheral modes are not any faster than Master Serial mode, since all modes (with the exception of XC5200 Express mode) internally operate on serial data. The internally generated CCLK frequency is guard-banded to never approach the upper limit of what the device can tolerate. Therefore, the fastest possible conguration mode for XC3000 and XC4000-series devices is Slave Serial, with an external well-controlled source for CCLK. Its frequency can be up to 10 MHz for all 5-V devices, and there are ways to increase the average clock rate well beyond that, but they require dynamic clock frequency changes and an intimate understanding of the conguration frame structure. At 10 MHz, conguration time per device ranges from 1.5 ms for the XC3020A to 42 ms for the XC4025E and 192 ms for the XC4085XL. Possible Contention Problems: Certain user outputs become active during the conguration process: Address outputs during Master Parallel mode, Chip Select and Ready/Busy during Peripheral modes. The designer must make sure that these active outputs do not cause contention with other logic that might use the same pins as device inputs.

This is the simplest scheme, but it precludes the use of RESET to clear the ip-ops and latches in the operating user-design. RESET must be pulled Low for more than six microseconds to overcome its internal low-pass ltering. Conguration starts when RESET has gone High again. 2. Pull DONE Low with an open-drain (open-collector) output. This assumes that DONE was High, i.e. that the previous conguration was successful. Reconguration starts as soon as the internal memory has been cleared. DONE can be released anytime. 3. Pull DONE Low with an open-drain (open-collector) output and pull RESET Low. Keep RESET Low for at least six microseconds while DONE is Low. DONE can be released anytime after that, or not released at all. See alternative 1.

XC4000 Series and XC5200 Family

Pull the PROGRAM input Low for at least 0.3 microseconds to initiate clearing the conguration memory, then pull PROGRAM up to start the new conguration process. While PROGRAM is held Low, a Low level on INIT indicates that the device is continuously clearing the conguration memory. When PROGRAM has been pulled up, INIT stays Low during one more clear operation, then goes High. All device families, except the original XC4000, have a continuously active pull-up resistor on the PROGRAM pin.

FPGAs Can Control Their Own Reconguration

Pulling PROGRAM, RESET or DONE low can trigger a reconguration, as described above. When a user output is connected to drive the reconguration pin, the FPGA can trigger its own reconguration. Although the triggering output will go 3-state once reconguration is initiated, this trigger operation is reliable. Such auto-reconguration offers interesting opportunities for small systems using a single FPGA in Master Parallel conguration mode. A manually operated switch selects the most signicant address bits of the PROM, and the FPGA compares the switch settings against a stored value. Upon detecting a difference, it can trigger reconguration that is loaded from the newly selected PROM address range. Or an external CMOS register can be loaded with the intended reconguration address range and then control the upper bits of the PROM address

Initiating Reconguration in Different Xilinx Device Families

XC3000 Series
There are three alternatives: 1. Pull RESET Low while DONE is permanently grounded externally.

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XAPP 093 November 10, 1997 (Version 1.1)

APPLICATION NOTE
0

APPLICATION NOTE

Metastable Recovery
0 13*

XAPP 094 November 24, 1997 (Version 2.1)

Application Note By Peter Alfke and Brian Philofsky tination might clock in the nal data state while the other does not. With the help of a self-contained circuit, Xilinx evaluated the XC4000 and XC3000-series ip-ops. The result of this evaluation shows the Xilinx ip-op to be superior in metastable performance to many popular MSI and PLD devices. Since metastability can only be measured statistically, this data was obtained by conguring several different Xilinx FPGAs with a detector circuit shown in Figure 1. The ipop under test receives the asynchronous ~1-MHz signal on its D input, and is clocked by a much higher manually adjustable frequency. The output QA feeds two ip-ops in parallel, one (QB) being clocked by the same clock edge, the other (QC) being clocked by the opposite clock edge. When clocked at a low frequency, each input change gets captured by the rising clock edge and appears rst on QA, then, after the falling clock edge, on QC, and nally, after the subsequent rising clock edge, on QB. If a metastable event in the rst ip-op increases the settling time on QA so much that QC misses the change, but QB still captures it on the next rising clock edge, this error

Introduction
Whenever a clocked ip-op synchronizes an asynchronous input, there is a small probability that the ip-op output will exhibit an unpredictable delay. This happens when the input transition not only violates the setup and hold-time specications, but actually occurs within the tiny timing window where the ip-op accepts the new input. Under these circumstances, the ip-op can enter a symmetrically balanced transitory state, called metastable (meta = between). While the slightest deviation from perfect balance will cause the output to revert to one of its two stable states, the delay in doing so depends not only on the gain-bandwidth product of the circuit, but also on how perfect the balance is, and on the noise level within the circuit; the delay can, therefore, only be described in statistical terms. The problem for the system designer is not the illegal logic level in the balanced state (it's easy enough to translate that to either a 0 or a 1), but the unpredictable timing of the nal change to a valid logic state. If the metastable ip-op drives two destinations with differing path delays, one des-

Asynchr, Input

QA

QB

QC

QD

16-Bit Counter

Clock

16 LEDs

Clock

Asynchr, Input

QA

QB NO ERROR QC ERROR QD NO ERROR

X5985

ERROR

Figure 1: Test Circuit and Timing Diagram

XAPP 094 November 24, 1997 (Version 2.1)

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Metastable Recovery

can be detected by feeding the XOR of QB and QC into a falling-edge triggered ip-op. Its output (QD) is normally Low, but goes High for one clock period each time the asynchronous input transition caused such a metastable delay in QA. The frequency of metastable events can be observed with a 16-bit counter driven by QD. By changing the clock frequency, and thus the clock halfperiod, the amount of acceptable metastable delay on the QA output can be varied, and the resulting frequency of metastable events can be observed on the counter outputs. As expected, no metastable events were observed at clock rates below 70 MHz for the XC4005-6, or below 100 MHz for the XC4005E-3, since a half clock period at those frequencies is adequate for almost any metastability-resolution delay. Increasing the clock rate slightly brought a sudden burst of metastable events. Careful adjustment of the clock frequency gave repeatable, reliable measurements.

K2 is derived by dividing ln 64,000 by the half-period difference. Table 1: Metastable Measurement Results FL (MHz) 111.5 109.0 73.0 71.2 70.8 152.2 107.4 46.6 41.9 FH Half-period K2 (MHz) Difference (ns) (1/ ns) 131.6 0.685 16.1 124.4 0.568 19.4 90.0 1.294 8.5 88.8 1.392 7.9 79.8 0.80 13.7 206.6 0.87 12.7 211.3 2.29 4.8 61.5 2.60 4.2 64.8 4.22 2.6

Device XC4005E-3 IOB XC4005E-3 CLB XC4005-6 IOB XC4005-6 CLB XC5206-5 CLB XC3142A-09 IOB XC3142A-09 CLB XC3042-70 IOB XC3042-70 CLB

Metastability Measurements
The circuit of Figure 1 was implemented in ve different Xilinx devices: two cutting-edge devices using 0.5 micron, 3layer-metal technology, the XC4005E-3 and the XC3142A09, one device, the XC5206 using 0.6 micron, 3-layermetal, and, for comparison purposes, also in two oldertechnology devices, the XC4005-6 and the XC3042-70. In each device two different implementations put QA, the ip-op under test, into an IOB and a CLB (Except for the XC5200 family which has no ip-ops in the IOB). The XC4000-series devices showed little difference between IOB and CLB behavior, but in the XC3000-series devices, the IOB ip-ops showed dramatically better metastable performance than the CLB ip-ops. This difference can be traced to subtle differences in circuit design and layout, and will guide us to further improvements in metastable performance in future designs. Metastable measurement results are listed in Table 1, and are plotted in Figure 2. The results for XC4000E-3 (IOB and CLB) and for XC3100A-09 IOB ip-ops are outstanding, far superior to most metastable data published anywhere else. When granted 2 or 3 ns of extra settling delay, these devices come close to eliminating the problems caused by metastability, since their MTBF exceeds millions of years. The older-technology devices are obviously less impressive, but they still show acceptable performance, especially in the IOB input ip-ops that are normally used to synchronize asynchronous input signals. Table 1 lists the experimental results from which the exponential factor K2 was derived. The clock frequency was adjusted manually, while observing the LSB and the MSB of the 16-bit error counter. FL is the clock frequency that generated a ~1 Hz error rate, FH generated a ~64,000 Hz error rate.

Metastability Calculations
The Mean Time Between Failures (MTBF) can only be dened statistically. It is inversely proportional to the product of the two frequencies involved, the clock frequency and the average frequency of the asynchronous data changes, provided that these two frequencies are independent and have no correlation. The generally accepted equation for MTBF is MTBF = eK2 * t F1 * F2 * K1

K1 represents the metastability-catching set-up time window, which describes the likelihood of going metastable. K2 is an exponent that describes the speed with which the metastable condition is being resolved. K2 is an indication of the gain-bandwidth product in the feedback path of the master latch of the master-slave ip-op. A small increase in K2 results in an enormous improvement in MTBF. With F1 = 1 MHz, F2 = 10 MHz and K1 = 0.1 ns = 10-10 s: MTBF (in seconds) = 103 * eK2*t Experimentally derived (see Table 1): K2 = 16.1 per ns, for the XC4005E-3 IOB ip-ops K2 = 19.4 per ns, for the XC4005E-3 CLB ip-ops K2 = 8.5 per ns, for the XC4005-6 IOB ip-ops K2 = 7.9 per ns, for the XC4005-6 CLB ip-ops K2 = 13.7 per ns, for the XC5206-5 CLB ip-ops K2 = 12.7 per ns, for the XC3142A-09 IOB ip-ops K2 = 4.8 per ns, for the XC3142A-09 CLB ip-ops K2 = 4.2 per ns, for the XC3042-70 IOB ip-ops K2 = 2.6 per ns, for the XC3042-70 CLB ip-ops

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XAPP 094 November 24, 1997 (Version 2.1)

MTBF

XC4005E-3 XC4005E-3 XC5206-5 CLB IOB CLB

XC3142A-09 IOB

XC4005-6 IOB

XC4005-6 CLB

1 Million Years 13 12 11 10 Log Seconds 9 8 1 Year 7 6 5 4 3 2 1 0 -1 -2 -3 1 2 3 Acceptable Extra Delay (ns) X5986 4 5 6 1 Minute 1 Day XC3042-70 IOB XC3142A-09 CLB

1,000 Years

1 Hour XC3042-70 CLB

Figure 2: Mean Time Between Failure for various IOB and CLB ip-op outputs when synchronizing a ~1 MHz asynchronous input with a 10 MHz clock. For other operating conditions, divide MTBF by the product of the two frequencies. For a ~10 MHz asynchronous input synchronized by a 40 MHz clock, the MTBF is 40 times shorter than plotted; for a ~50 kHz signal synchronized by a 1 MHz clock, the MTBF is 200 times longer than plotted here.

XAPP 094 November 24, 1997 (Version 2.1)

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APPLICATION NOTE
0

APPLICATION NOTE

Set-up and Hold Times

0 13*

XAPP 095 November 24, 1997 (Version 1.0)

Application Brief by Peter Alfke If the receiving device has a hold time requirement, the source of data must guarantee an equivalent minimum value for its clock-to-output delay. Almost no IC manufacturer is willing to do this, and in the few cases where it is done, the minimum value is usually a token 1 ns. Any input hold time requirement is, therefore, an invitation to system failure. Any clock distribution skew on the PC-board can compound this issue and wipe out even the specied short minimum delay. Xilinx has addressed this problem by adding a deliberate delay to every FPGA data input. In XC3000, and XC3100 FPGAs, this delay is xed and always present; in XC4000 and XC5200 FPGAs, this delay is optional, and its value is tailored to the clock distribution delay (i.e. it is larger for bigger devices). As a result we can claim that no Xilinx FPGA Data input has a hold-time problem (i.e., none has a positive hold time with respect to the externally applied clock), when the design uses the internal global clock distribution network (and, in XC4000 and XC5200, uses the delayed input option). Most competitive devices do not offer this feature.
External Clock Internal Clock Conventional Input Pin Set-up and Hold Time Input Pin Set-up Time With Delay SET-UP
X5971

Introduction
Beware of hold-time problems, because they can lead to unreliable, temperature-sensitive designs that can fail even at low clock rates. Set-up time and hold time describe the timing requirements on the data input of a ip-op or register with respect to the clock input. The set-up and hold times describe a window of time during which data must be stable in order to guarantee predictable performance over the full range of operating conditions and manufacturing tolerances. A positive set-up time describes the length of time that the data must be available and stable before the active clock edge. A positive hold time, on the other hand, describes the length of time that the data to be clocked into the ip-op must remain available and stable after the active clock edge. A positive set-up time limits the maximum clock rate of a system, but a positive hold time can cause malfunction at any clock rate. Thus, chip designers and system designers strive to eliminate hold-time requirements. The IC design usually guarantees that any individual ipop does not require a positive hold time with respect to the clock signal at this ip-op. Hold-time requirements between ip-ops or registers on the same chip can be avoided by careful design of the onchip clock distribution network. If the worst-case clock-skew value is shorter than the sum of minimum clock-to-Q plus minimum interconnect delays, there is never any on-chip hold-time problem. It is, however, far more difcult to avoid a hold time problem in the device input ip-ops, with respect to the device clock input pin. When specifying the data pin-to-clock pin set-up and hold times, the chip-internal clock distribution delay must be taken into consideration. It effectively moves the timing window to the right (see gure), thus subtracting from the specied internal set-up time (which is good), but adding to the hold time (which is very bad). If the clock distribution delay is any longer than the data input delay and it easily might be the device data input has a hold-time requirement with respect to the clock input. This means that the data source, usually another IC driven by the same clock, must guarantee to maintain data beyond the clock edge. In other words, the data source is not allowed to be very fast. If it is, the receiver might erroneously input the new data instead of the data created by the previous clock, as it should. This is called a race condition, and can be a fatal system failure.

Internal Clock Delay

SET-UP H

XAPP 095 November 24, 1997 (Version 1.0)

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APPLICATION NOTE
0

APPLICATION NOTE

Overshoot and Undershoot

0 13*

XAPP 096 September 9, 1997 (Version 1.0)

Application Note By Peter Alfke

Introduction
The Absolute Maximum Ratings table in the Xilinx Data Book restricts the signal-pin voltage to a maximum 500 mV excursion above VCC and below ground. The reason for this tight specication is to prevent uncontrolled current in the input-clamping ESD-protection diodes. Such tight specications are common in the industry; some manufacturers limit the excursion to 300 mV. This specication seems to be clean and simple, but it is violated in almost every practical design. When users put modern CMOS devices on PC boards, and interconnect them with unterminated traces, there are reections, commonly called ringing, that cause overshoots and undershoots of substantial amplitude (2 V and more). The recent migration to smaller device geometries has made the IC outputs even faster and increased the slew-rate, causing more reections even on short PC-board traces. Fortunately, this problem has an easy solution: The concern is not the input voltage, but rather the current through the input protection diode and other input structures. Excessive current can cause latch-up if it exceeds hundreds of milliamps AND if it lasts for microseconds (shorter duration current spikes do not activate the SCRlike latch-up mechanism). PC-board reections, on the other hand, usually have a short duration of just a few nanoseconds, and have an impedance of 40 to 100 , which makes them incapable of causing latch-up. They dont drive enough current and they dont last long enough to cause any harm. Here is the new Xilinx specication: Maximum DC overshoot or undershoot above VCC or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns.

XAPP 096 September 9, 1997 (Version 1.0)

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APPLICATION NOTE
1

Boundary Scan in XC4000 and XC5200 Series Devices

1 13*

XAPP017 April 9, 1998 (Version 2.1) Summary

Application Note

XC4000 and XC5200 Series FPGA devices contain boundary-scan facilities that are compatible with IEEE Standard 1149.1. This Application Note describes those facilities in detail, and explains how boundary scan is incorporated into an FPGA design. Xilinx Family XC4000 Series, XC5200

Introduction
In production, boards must be tested to assure the integrity of the components and the interconnections. However, as integrated circuits have become more complex and multilayer PC-boards have become more dense, it has become increasingly difcult to test assembled boards. Originally, manufacturers used functional tests, applying input stimuli to the input connectors of the board, and observing the results at the output. Later, bed-of-nails testing became popular, where a customized xture presses sharp, nail-like stimulus- and test-probes into the exposed traces on the board. These probes were used to force signals onto the traces and observe the response. However, increasingly dense multi-layer PC boards with ICs surface-mounted on both sides have stretched the capability of bed-of-nail testing to its limit, and the industry is forced to look for a better solution. Boundary-scan techniques provide that solution. The inclusion of boundary-scan registers in ICs greatly improves the testability of boards. Boundary scan provides a mechanism for testing component I/Os and inter-connections, while requiring as few as four additional pins and a minimum of additional logic in each IC. Component testing may also be supported in ICs with self-test capability. Devices containing boundary scan have the capability of driving or observing the logic levels on I/O pins. To test the external interconnect, devices drive values onto their outputs and observe input values received from other devices. A central test controller compares the received data with expected results. Data to be driven onto outputs is distributed through a chain of shift registers, and observed input data is returned through the same shift-register path. Data is passed serially from one device to the next, thus forming a boundary-scan path or loop that originates at the test controller and returns there. Any device can be temporarily removed from the boundary-scan path by bypassing

its internal shift registers, and passing the serial data directly to the next device. XC4000/XC5200 FPGA devices contain boundary-scan registers that are compatible with the IEEE Standard 1149.1, that was derived from a proposal by the Joint Test Action Group (JTAG). External (I/O and interconnect) testing is supported; there is also limited support for internal self-test.

Overview of XC4000/XC5200 Boundary-Scan Features

XC4000/XC5200 devices support all the mandatory boundary-scan instructions specied in the IEEE Standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD and BYPASS instructions. The TAP can also support two USERCODE instructions. Note: If boundary scan is not used after the device is congured, the user can use the special boundary scan pads as input or output pins. During conguration, be sure not to toggle the TAP pins, since inadvertent toggling of the TAP pins can turn the boundary scan circuitry on. The TDI, TMS, and TCK pads can be used as unrestricted I/O. The TDO pad can be used as an output pad. In the XC5200 family, all four pins have full I/O capability. And like the regular IOBs, these input and output pins have pullups and pulldowns available. Boundary-scan operation is independent of individual IOB conguration and package type. All IOBs are treated as independently controlled bidirectional pins, including any unbonded IOBs. Retaining the bidirectional test capability even after conguration affords tremendous exibility for interconnect testing. Additionally, internal signals can be captured during EXTEST by connecting them to unbonded IOBs, or to the unused outputs in IOBs used as unidirectional input pins. This partially compensates for the lack of INTEST support. 13-52

XAPP017 April 9, 1998 (Version 2.1)

The public boundary-scan instructions are always available prior to conguration. After conguration, the public instructions and any USER1/USER2 instructions are only available if boundary scan specied in the schematic/HDL code. While SAMPLE and BYPASS are available during conguration, it is recommended that boundary-scan operations not be performed during this transitory period. In addition to the test instructions outlined above, the boundary-scan circuitry can also be used to congure the FPGA device, and read back the conguration data. The following description assumes that the reader is familiar with boundary-scan testing and the IEEE Standard. Only issues specic to the XC4000/XC5200 implementation are discussed in detail. For general information on boundary scan, please refer to the bibliography.

It should also be noted that the Test Data Register contains three Xilinx test bits (BSCANT.UPD, TDO.O and TDO.T) and that bits of the register may correspond to unbonded or unused pins. Additionally, the EXTEST instruction incorporates INTESTlike functionality that is not specied in the standard, and system clock inputs are not disabled during EXTEST, as recommended in the standard. The TAP pins (TMS, TCK, TDI and TDO) are scanned, but connections to the TAP controller are made before the boundary-scan logic. Consequently, the operation of the TAP controller cannot be affected by boundary-scan test data. When the TAP is in the shift-DR state the contents of all data registers are shifted; if you are in the middle of shifting out data from the data register, complete shifting out of all data rst, before switching to the instruction or bypass register.

Deviations from the IEEE Standard

The XC4000/XC5200 boundary scan implementation deviates from the IEEE standard in that three dedicated pins (CCLK, PROGRAM and DONE) are not scanned.

TEST-LOGIC-RESET 0

RUN-TEST/IDLE

SELECT-DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0

1 SELECT-IR-SCAN 0 1 CAPTURE-IR 0 0 SHIFT-IR 1 0

EXIT1-IR 0 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0

NOTE: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK.

X2680

Figure 1: State Diagram for the TAP Controller

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Boundary Scan in XC4000 and XC5200 Series Devices

Boundary-Scan Hardware
Test Access Port
The boundary-scan logic is accessed through the Test Access Port (TAP), which comprises four semi-dedicated pins: Test Mode Select (TMS), Test Clock (TCK), Test Data Input (TDI) and Test Data Output (TDO), as dened in the IEEE specication. The TAP pins are permanently connected to the boundaryscan circuitry. However, once the device is congured, the connections may be ignored unless the use of boundary scan is specied in the design. See Using Boundary Scan on page 13-57. If the use of boundary scan is specied, the TAP input pins (TMS, TCK and TDI) may still be shared with other logic, subject to limitations imposed by external connections and the operation of the TAP Controller. In designs that do not use boundary scan after conguration, the TAP pins can be used as inputs or outputs from the user logic in the FPGA device. TMS, TCK and TDI are available as unrestricted I/Os, while TDO only provides a 3-state output. In the XC5200 family, all four pins are available as I/O. Before the FPGA is congured, it is important not to toggle the TAP pins (TDI, TMS, TCK), since these pins turn-on boundary scan. Before an FPGA is congured, at a minimum, do not toggle TCK. Similarly, if boundary scan is enabled in a design after the FPGA is congured, care must be taken not to toggle the TAP pins (TDI, TMS, TCK) to prevent turning on boundary scan by accident.

Table 1: Boundary Scan Instructions Instruction Test I2 I1 I0 Selected 0 0 0 EXTEST 0 0 1 SAMPLE/ PRELOAD 0 1 0 USER 1 0 1 1 USER 2 1 0 0 READBACK 1 0 1 CONFIGURE 1 1 0 RESERVED 1 1 1 BYPASS
I0 is closest to TDO

TDO Source DR DR BSCAN.TDO1 BSCAN.TDO2 Readback Data DOUT Bypass Register

I/O Data Source DR Pin/Logic User Logic User Logic Pin/Logic Disabled

Note: Whenever the TAP Controller is in the Shift-DR state, all data registers are shifted, regardless of the instruction. DR data is modied even if a BYPASS instruction is executed. The instruction register is used not only to hold the current instruction. If the TAP is in the capture-IR state and TCK goes high, the instruction register captures the current boundary-scan state of the device. I0 is 1 by default. I1 is 0 by default. I2 is 0 if the device is in congure by boundary scan mode. Before and after congure by boundary scan mode, I2 will capture 1. Note that I0 is shifted out of TDO rst, then I1, and then I2.

The Boundary-Scan Data Register

The Data Register (DR) is a serial shift register implemented in the IOBs of the FPGA device, (Figure 2). Potentially, each IOB can be congured as an independently controlled bidirectional pin. Therefore, three data register bits are provided per IOB: for input data, output data and 3state control. In practice, many of these bits are redundant, but they are not removed from the scan chain. An update latch accompanies each bit of the DR, and is used to hold injected test data stable during shifting. The update latch is opened during the Update-DR state of the TAP Controller when TCK is Low. In a typical DR instruction, the DR captures data during the Capture-DR state (on the rising edge of TCK). This data is then shifted out and replaced with new test data. Subsequently, the update latch opens, and the new test data becomes available for injection into the logic or the interconnect. The injection of data occurs only if an EXTEST instruction is in progress. Note: The update latch is opened whenever the TAP Controller is in the Update-DR state, regardless of the instruction. Care must be exercised to ensure that appropriate data is contained in the update latch prior to initiating an EXTEST. Any DR instruction, including BYPASS, that is executed after the test data is loaded, but before the EXTEST commences, changes the test data. XAPP017 April 9, 1998 (Version 2.1)

TAP Controller
The TAP Controller is a 16-state machine that controls the operation of the boundary-scan circuitry in response to TMS. This state machine implements the state diagram specied by the IEEE standard (Figure 1) and is clocked by TCK. Upon power-on, or if the boundary scan logic is not used in the application, the TAP controller is forced into the TestLogic-Reset state. After conguration, the controller remains disabled, unless its use is explicitly specied in the user design. PROGRAM resets the latched decodes for EXTEST, CONFIGURE, and READBACK instructions. Loading a 3-bit instruction into the Instruction Register (IR) determines the subsequent operation of the boundaryscan logic, Table 1. The instruction selects the source of the TDO pin, and selects the source of device input and output data (boundary-scan register or input pin/user logic).

13-54

From TDI

1 0 D Q D LE

sd Q

Pull-Up Pull-Down To Global Clock Buffer (CLK Pad Only) 1 0 VCC

IOB.I
(To FPGA Interconnect)

IOB 1 0 D Q D LE 1 IOB.O
(From FPGA Interconnect)

sd Q

0 0 Q 1

IOB.T 1 0 D Q D LE Towards TDO Shift/Capture DRCK Update Test Logic Reset sd

EXTEST
X5998

Figure 2: Boundary Scan Logic in a Typical IOB The IEEE Standard does not require the ability to inject data into the on-chip system logic and observe the results during EXTEST. However, this capability helps compensate for the lack of INTEST. Logic inputs may be set to specic levels by a SAMPLE/PRELOAD or EXTEST instruction and the resulting logic outputs captured during a subsequent EXTEST. It must be recognized, however, that all DR bits are captured during an EXTEST and, therefore, may change. Pull-up and pull-down resistors remain active during boundary scan. Before and during conguration, all pins are pulled up. After conguration, the IOB can be congured with a pull-up resistor, a pull-down resistor or neither. Note: Internal pull-up/pull-down resistors must be taken into account when designing test vectors to detect open circuit PC traces. The primary and secondary global clock inputs (PGCK1-4 and SGCK1-4 in XC4000, GCK1-4 in XC5200) are taken directly from the pins, and cannot be overwritten with boundary-scan data. However, if necessary, it is possible to drive the clock input from boundary scan. The external clock source is 3-stated, and the clock net is driven with boundary scan data through the output driver in the clockpad IOB. If the clock-pad IOBs are used for non-clock signals, the data may be overwritten normally. Figure 3 shows the data-register cell for a TAP pin. An ORgate permanently disables the output buffer if boundaryscan operation is selected. Consequently, it is impossible for the outputs in IOBs used by TAP inputs to conict with TAP operation. TAP data is taken directly from the pin, and cannot be overwritten by injected boundary-scan data.

Bit Sequence
Table 2 lists, in data-stream order, the boundary-scan cells that make up the DR for the XC4000 Series. The cell closest to TDO corresponds to the rst bit of the data-stream, and is at the top of the table. This order is consistent with the BSDL description.

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Boundary Scan in XC4000 and XC5200 Series Devices

From TDI

1 0 D Q D LE

sd Q

Pull-Up Pull-Down

To Tap Controller 1 VCC

IOB.I IOB
(To FPGA Interconnect)

0 1 0 D Q D LE 1 sd Q

IOB.O
(From FPGA Interconnect)

IOB.T 1 0 D Q Boundary Scan Enabled Device Not Configured EXTEST

X5999

Towards TDO Shift/Capture DRCK Update Test Logic Reset

Figure 3: Boundary Scan Logic in a TAP Input (TMS, TCK, and TDI Only) Each IOB corresponds to three bits in the DR. The 3-state control is rst (closest to TDO), the output is next, and the input is last. Other signals correspond to individual register bits. IOB locations assume that the die is viewed from the top, as in the device-level editors XDE or EPIC. In the XC4000, the input-only M0 and M2 mode pins contribute only the In bit to the boundary scan I/O register. Table 2: XC4000 Boundary Scan Order Note: All IOBs remain in the DR, independent of whether they are actually used, or even bonded. Three bits, BSCANT.UPD, TDO.O and TDO.T, are included for Xilinx test purposes, and may be ignored by other users. CCLK, PROGRAM and DONE are not included in the boundary scan. Tables in the data sheets show the DR order for all XC4000/XC5200 family devices. The DR also includes the following non-pin bits: TDO.T and TDO.I, which are always bits 0 and 1 of the DR, respectively, and BSCANT.UPD which is always the last bit of the DR.

Bit 0 ( TDO end) Bit 1 Bit 2

TDO.T TDO.O Top-edge IOBs (Right to Left)

The Bypass Register

This is a 1-bit shift register that passes the serial data directly to TDO when a BYPASS instruction is executed.

Left-edge IOBs (Top to Bottom) MD1.T MD1.O MD1.I MD0.I MD2.I Bottom-edge IOBs (Left to Right)

User Registers
The XC4000 and XC5200 boundary-scan instruction set includes two USERCODE instructions, USER1 and USER2. Connections are provided to the TAP and TAP controller that, together with direct connections to the TAP pins, permit the user to include boundary-scan self-test features in the design. The XC4000 boundary scan symbol has six connections for user registers: SEL1, SEL2, TDO1, TDO2, DRCK and IDLE. TDI is available directly from the IOB that provides the TDI pin. The XC5200 boundary scan symbol has three

Right-edge IOBs (Bottom to Top) (TDI end) B SCANT.UPD

X2674

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XAPP017 April 9, 1998 (Version 2.1)

additional pins which make the creation of a user register easier: RESET, UPDATE, and SHIFT. Note: The TDI signal supplied to user test logic is overwritten by boundary-scan test data during EXTEST. During user tests, it is not altered. SEL1, SEL2 SEL1 and SEL2 enable user logic. They are asserted (High) when the instruction register contains instructions USER1 and USER2, respectively. TDO1, TDO2 TDO1 and TDO2 are inputs to the TDO output multiplexer, permitting user access to the serial boundary-scan output. They are selected when executing the instructions USER1 and USER2, respectively. Input to user data registers can be derived directly from the TDI pin, thus completing the boundary-scan chain. There is a one ip-op delay between TDO1/TDO2 and the TDO output. This ip-op is clocked on the falling edge of TCK. DRCK Data register clock (DRCK) is a gated and uninverted version of TCK. It is provided to clock user test-data registers. TDI data should be sampled with the falling edge of DRCK (rising edge of TCK). The TDO output ip-op accepts data on the rising edge of DRCK (falling edge of TCK). DRCK is active only during the Capture-DR and Shift-DR states of the TAP controller. When not active in the XC4000, DRCK is Low. In the XC5200, when DRCK is not active, it is High. IDLE IDLE is a second gated and inverted version of TCK. It is active during the RUN-TEST/IDLE state of the TAP controller, and may be used to clock user test logic a set number of times, determined through TMS by the central test controller. RESET - This pin is only available on the XC5200 boundary scan symbol. Whenever the TAP is in the TEST-LOGICRESET state, the RESET pin is High, in all other cases the RESET pin is Low. UPDATE - This pin is only available in the XC5200 boundary scan symbol. Whenever the USER1 or USER2 instructions are used, UPDATE is an inverted version of TCK. In all other cases, UPDATE is Low. SHIFT - This pin is only available in the XC5200 boundary scan symbol. When the USER1 or USER2 instructions are used, SHIFT is High, in all other cases SHIFT is Low.

Figure 4 is a ow chart of the XC4000 FPGA start-up sequence that shows when the boundary-scan instructions are available. Since PROGRAM resets the TAP controller, boundary-scan operations cannot commence until PROGRAM has been taken High. .

Boundary Scan Instructions Available:

VCC >3.5 V Yes

No

Test M0 Generate One Time-Out Pulse of 16 or 64 ms

PROGRAM = Low Yes

Keep Clearing Configuration Memory

EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory CONFIGURE* Once More (* if PROGRAM = High)

~1.3 s per Frame

INIT High? if Master Yes

No

Master Waits 50 to 250 s Before Sampling Mode Lines

Sample Mode Lines Master CCLK Goes Active Load One Configuration Data Frame

Frame Error No SAMPLE/PRELOAD BYPASS Configuration memory Full Yes Pass Configuration Data to DOUT

Yes

Pull INIT Low and Stop

No

CCLK Count Equals Length Count Yes

No

Full access to the built-in boundary-scan logic is always available between power-up and the start of conguration. Optionally, the built-in logic is fully available after conguration if boundary scan is specied in the design. At this time, user test logic is also available, and may be accessed through the boundary-scan port. During conguration, a reduced boundary-scan capability remains available: the SAMPLE/PRELOAD and BYPASS instructions only.

EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK

Operational

If Boundary Scan is Selected

X6076

Figure 4: XC4000 Start-up Sequence

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I/O Active

Using Boundary Scan

Start-Up Sequence
F

LDC Output = L, HDC Output = H

Boundary Scan in XC4000 and XC5200 Series Devices

Full boundary-scan capabilities are available until INIT is High. Without external intervention, INIT automatically goes High after ~1 ms. If more time is required for boundary-scan testing, INIT may be held Low beyond this period by applying an external Low signal to the INIT pin until testing is complete. Once INIT has gone High, all clocks on the TCK pin are counted as conguration clocks for data and length count. See CONFIGURE on page 13-59. for more details. Boundary scan can be accessed before the FPGA is congured and after the FPGA is congured. If you want to access boundary scan before the device is congured, then when you power-up the device, hold the INIT pin Low until VCC has risen to VCC(min). If you have already started conguring the device, and data frames are already being sent to the FPGA, then you have two choices. You can either access full-boundary scan mode, or limited boundary scan mode. If you want to access full-boundary scan mode, then both INIT and PROGRAM must be brought Low (Hold INIT and PROG Low for over 300 ns and then release PROGRAM.) After releasing PROGRAM, continue to hold INIT Low while sending signals to the TAP. If you can use the limited boundary scan mode (which means you only can use the SAMPLE/PRELOAD and BYPASS instructions), then just bring INIT Low. Accessing boundary scan after the device is congured has one requirement. The BSCAN symbol must be instantiated/inserted into your design with the correct syntax (see Figure 5). In this case, activating boundary scan after conguration amounts to toggling the TAP pins. .
BSCAN TDI TMS TCK TDI TMS TCK TDO1 TDO2 TDO DRCK IDLE SEL1 SEL2 TDO

the TDO pad primitive to an OBUF or OBUFT as required (see Figure 6.)
From User Logic OBUFT

TDO
X2676

Figure 6: Typical Non-Boundary-Scan TDO Connection

Boundary Scan Instructions

The XC4000/XC5200 boundary scan supports three IEEEdened instructions (EXTEST, SAMPLE/PRELOAD and BYPASS), two user-denable instructions (USER1 and USER2), and two FPGA-specic instructions (CONFIGURE and READBACK). The instruction codes are shown in See Table 1 on page 13-54.

EXTEST
While the EXTEST instruction is present in the IR, the data presented to the device output buffers is replaced by data previously loaded through the boundary-scan DR and stored in the update latch (Figure 7). SImilarly, the output 3state controls are replaced, and the data passed to internal system logic from input pins is replaced. When a DR instruction cycle is executed, data arriving at the device input pins is loaded into the DR. The data from the system logic that drives output buffers and their 3-state controls is also loaded. This action occurs during the CAPTURE-DR state of the TAP controller (Figure 1 on page 1353). Data is serially shifted out of the DR during the SHIFTDR state; simultaneously, new data is shifted in. In the UPDATE-DR state, the new data is transferred into the update latch for use as replacement data, as described above. The replacement of system data with update latch data starts as soon as the EXTEST instruction is loaded into the IR. For this data to be valid, it must have been loaded by a previous EXTEST or SAMPLE/PRELOAD operation.

4k BSCAN Syntax for BSCAN after configure symbol BSCAN IBUF TDI TMS TCK IBUF TMS IBUF TCK TDO1 TDO2 IDLE SEL1 SEL2
X5966

OBUF TDI TDO DRCK

TDO

Since the DR and update latch are modied during any DR instruction cycle, including BYPASS, the data in the update latch is only valid if it was loaded in the last DR instruction cycle executed before EXTEST is asserted. The IEEE denition of EXTEST only requires that test data be driven onto outputs, that 3-state output controls be overridden, and that input data be captured. The capture of output data and 3-state controls and the forcing of test data into the system logic is normally performed during INTEST. The XC4000/XC5200 effectively performs EXTEST and INTEST simultaneously. This added functionality permits the testing of internal logic, and compensates for the absence of a separate INTEST instruction. However, when performing an EXTEST, care must be taken as to what sig-

5k BSCAN Syntax for BSCAN after configure symbol

Figure 5: Boundary-Scan Schematic Symbols

If the BSCAN symbol is not included, boundary scan is not selected, and the IOBs used by the TAP input pins are freely available as general purpose IOBs. The TDO output pin may be used as a logic output by explicitly connecting

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Capture DR Update DR From Previous Cell Test Data Register DRCK To Next Cell

Update Latch EN Update DR

System Logic

O Pad I EXTEST

X2677

Figure 7: EXTEST Data Flow nals are driven into the system logic. Data captured from internal system logic must be masked out of the test-data stream before performing check-sum analysis. Test clocks and paths to TDO are provided, together with two signals that indicate that user instructions have been loaded. See User Registers on page 13-56. User tests depend upon CLBs and interconnect that must be congured to operate. Consequently, they may only be performed after conguration.

SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction permits visibility into system operation by capturing the state of the I/O. It also permits valid data to be loaded into the update register before commencing an EXTEST. The DR and update latch operate exactly as in EXTEST (see above). However, data ows through the I/O unmodied.

CONFIGURE
Steps to follow to congure a Xilinx XC4000 or XC5200 device via JTAG: The bitstream format is identical for all conguration modes. A user can use a design.BIT le or a design.RBT le, depending on whether the user wants to read a binary le (.BIT) or an ASCII le (.RBT). 1. Enable the boundary scan circuitry. This can be done one of three ways, either during power-up, or by conguring the device with boundary scan enabled, or by pulling the PROGRAM pin low. To enable boundary scan during power-up, hold the INIT pin Low when power is turned on. When VCC has

BYPASS
The BYPASS instruction permits data to be passed synchronously to the next device in the boundary-scan path. There is a 1-bit shift register between the TDI and TDO ipop.

USER1, USER2
These instructions permit test logic, designed by the user and implemented in CLBs, to be accessed through the TAP. XAPP017 April 9, 1998 (Version 2.1)

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Boundary Scan in XC4000 and XC5200 Series Devices

reached VCC(min), the TAP inputs can be toggled to enter JTAG instructions. The INIT pin can be held Low one of two ways, either manually or with a pulldown. If you choose to manually hold the INIT low, then the INIT pin must be held low until the CONFIGURE instruction is the current instruction. If you choose a pulldown, use a pulldown which pulls the INIT pin down to approximately 0.5V. The pulldown has the merit of holding INIT low whenever the FPGA is powered-up, and letting the user observe the INIT pin during conguration. After the FPGA has been congured, if you want to recongure a congured device that has boundary scan enabled after conguration, then just start toggling the boundary scan TAP pins. 2. Load the Xilinx CONFIGURE instruction into the Instruction Register (IR). The Xilinx CONFIGURE instruction is 101(I2 I1 I0). I0 is the bit shifted rst into the IR. 3. After shifting in the Xilinx CONFIGURE instruction, make the CONFIGURE instruction the current JTAG instruction by going to the UPDATE-IR state. When TCK goes low in the UPDATE-IR state, the FPGA is now in the JTAG conguration mode and will start clearing the conguration memory. The CONFIGURE instruction is now the current instruction, which must be followed by a rising edge on TCK. If you chose to manually hold the INIT pin Low, then the INIT pin must be held Low until the CONFIGURE instruction is the current instruction. 4. Once the Xilinx CONFIGURE instruction has been made the current instruction, the user must go to the RUN-TEST/IDLE state, and remain in the RUN-TEST/ IDLE state until the FPGA has nished clearing its conguration memory. The approximate time it takes to clear the FPGA conguration memory is: 2 * 1 us * (number of frames per device bitstream). When the FPGA has nished clearing its conguration memory, the open-collector INIT has gone high impedance. At this point, the user should advance to the SHIFT-DR state. Once the TAP is in the SHIFT-DR state and the INIT pin has been released, clocks on the TCK pin will be considered conguration clocks for data and length count. 5. In the SHIFT-DR state, start shifting in the bitstream. Continue shifting in the bitstream until DONE has gone High and the startup sequence has nished. During the time you are shifting in the bitstream via the TAP, the conguration pins LDC, HDC, INIT, PROGRAM, DOUT, and DONE all function as they normally do during non-JTAG conguration. These pins can be probed by the user. After completion of conguration, or

if conguration failed, the SAMPLE/PRELOAD instruction can be used to view these IOBs (except PROGRAM and DONE.) LDC is Low during conguration. HDC is High during conguration. INIT will be high impedance during conguration, but if a CRC error or frame error is detected, INIT will go Low. If a pulldown is present on INIT then the user must probe INIT with a meter or scope. With a pulldown (as in step 1) attached to the INIT pin, the user will see a drop from approximately 0.5V to 0V if INIT drops Low to indicate a data error. PROGRAM can still be used to abort the conguration process. DOUT and TDO will echo TDI until the preamble and length count are shifted into TDI. After the preamble and length count have been shifted into the FPGA, DOUT will remain High. DONE will go High when conguration is nished. Until conguration is nished, DONE will remain Low.

Additional Notes
(a) It is possible to congure several XC4000/XC5200 devices in a JTAG chain. But unlike non-JTAG daisy-chain conguration, this does not necessarily mean merging all the bitstreams into one bitstream. In the case of JTAG conguration of Xilinx devices in a JTAG chain, all devices, except the one being congured, will be placed in BYPASS mode. The one device in CONFIGURE mode will have its bitstream downloaded to it. After conguring this device it will be placed in BYPASS, and another device will be taken out of BYPASS into CONFIGURE. (b) If you are conguring a long daisy-chain of JTAG devices (TDI connected to TDO of the previous device), the bitstream for the device with the CONFIGURE instruction may need to have its bitstream modied. For example, assume that the a user has the following daisy-chain of devices: source -----> device1 -----> device2 -----> device3 Device1's TDO pin is connected to device2's TDI pin, and device2's TDO pin is connected to device3's TDI pin. The way to congure this chain is to place one device in CONFIGURE, and the other two in BYPASS. Further assume that device1 and device2 congure in this way, but device3 never congures. Specically, device3's DONE pin never goes High. The problem is the bitstream length count. A possible cause, aside from bitstream corruption, is that the nal value of the length count computed by the user/software was reached before the loading was complete. There are two solutions. One solution involves just continually clocking TCK (for about 15 seconds) until DONE goes High. The other solution is to modify the bitstream; increase the length count by the number of devices ahead of the device under conguration.

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In the preceding example, the user would increase the length count value by 2. (In a daisy-chain of devices conguring via boundary scan, devices in BYPASS will supply the extra 1s needed at the head of the bitstream.) (c) In general for the XC4000 and XC5200, if you are conguring these devices via JTAG, nish conguring the device rst before executing any other JTAG instructions. Once conguration through boundary scan is started, the conguration operation must be nished. (d) If boundary scan is not included in the design being congured, then make sure that the release of I/Os is the last event in the startup sequence. If boundary scan is not available, the FPGA is congured, and the I/Os are released before the startup sequence is nished, the FPGA will not respond to input signals and outputs will not respond at all. (e) Re-issuing a boundary scan CONFIGURE instruction after the clearing of conguration memory will cancel the CONFIGURE instruction. The proper method of re-issuing a CONFIGURE instruction after the conguration memory is cleared is to issue another boundary scan instruction, and follow it by the CONFIGURE instruction. (f) If conguration through boundary scan fails, there are only two boundary scan instructions available: SAMPLE/ PRELOAD and BYPASS. If another reconguration is to be attempted, then the PROGRAM pin must be pulled Low, or the FPGA must be repowered. (g) When the CONFIGURE instruction is the current instruction, clocks on the TCK pin are not considered conguration clocks until the INIT pin has gone high impedance, and the TAP is in the SHIFT-DR state. (h) If the user is attempting to congure a chain of devices, it is recommended that the user only congure the chain in all boundary scan mode, or use the non-boundary scan conguration modes. It is possible to congure a daisychain of devices, some in boundary scan and some in nonboundary scan conguration. Conguring in a mixed mode will not necessarily give the user a continuous boundary scan chain, which may or may not be a problem for a particular user's applications. (j) Currently, there is no software to congure a Xilinx FPGA via the boundary scan pins. The user must provide this. (k) Conguring a chain of Xilinx FPGAs via boundary scan does not require merging all the bitstreams into one bitstream, as in non-boundary scan conguration daisychains. When the FPGA is in boundary scan conguration, the same conguration circuitry used for non-boundary scan conguration is used. So, if a user would like, it is possible to merge all bitstreams into one bitstream, using the PROM File Formatter or MakePROM/promgen. In a case where the user wants to merge the bitstreams into one bit-

stream, the user should congure as in note (a) above. Additionally, the user will have to tie all INIT pins together. All DONE pins will also have to be tied together. NOTE: The intention of conguration for a daisy-chain was to use either all the devices in boundary scan, or all the devices in non-boundary scan conguration.

READBACK
Readback through boundary scan allows the user to access the readback features of the device, which would normally need to be accessed through user-specied pins. All limits of normal readback are the same with readback through the TAP. Like regular readback, readback through the TAP is at a minimum of 100 KHz and at a maximum of 2 MHz. Like regular readback, the readback bitstream through boundary scan has the same format. Unlike regular readback, which can be done repeatedly, readback through the TAP requires the following circuit: 1. In your schematic, or top-level synthesis design, instantiate the BSCAN and READBACK symbols. 2. Connect the BSCAN symbol pins TDI, TMS, TCK, and TDO to the boundary scan pads TDI, TMS, TCK, and TDO, respectively. 3. Next, connect the net between the TCK pad and TCK pin on the BSCAN symbol to an IBUF. Take the output of the IBUF and connect it to the CLK pin of the READBACK symbol. See Figure 8.
BSCAN TDI TMS TCK TDI TMS TCK TDO1 TDO2 TDO DRCK IDLE SEL1 SEL2 IBUF 4k BSCAN Symbol setup for multiple READBACKS through TAP For the 5k, add IBUFs to TDI, TMS, and TCK. For TDO, add an OBUF. (see figure 5) READBACK CLK TRIG DATA RIP TDO

X5968

Figure 8: Symbol Setup for Multiple Readbacks For the XC5200, the equivalent circuit must be implemented using the XACT Design Editor (XDE) program EditLCA, or EPIC in the M1-based tools. After placing and routing your XC5200 design, load the design.LCA le into EditLCA, and follow the procedures below: (<ENTER> means hit the enter key on your keyboard) (a) Once EditLCA has displayed the design.LCA le, type the following: eb bscan <ENTER> This will bring up the Editblock window for the XC5200 BSCAN symbol.

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Boundary Scan in XC4000 and XC5200 Series Devices

(b) In the Editblock window, select the used option, which is in the upper left corner of the screen. (c) Now type: endb <ENTER> This brings you back to the EditLCA screen. (d) Next type the following: addnet username tckpin.i rdbk.ck <ENTER> where tckpin is the pin number of the TCK pin of your XC5200 device. username is a net name of your choIce. For example, if your design used an XC5202PC84, then the above command line would be: addnet mynet p16.i rdbk.ck <ENTER> (e) At this point you should see a net go from the TCK pin to the CK pin of the Readback symbol. (f) Save your changes to the LCA le and exit XDE. 4. After entering the above circuit, compile the design to an LCA le. 5. Make the bitstream le for the LCA le by using the following option with makebits, or use the M1 Bitstream Generator: -f readclk:rdbk For example, at a unix prompt: % makebits -f readclk:rdbk design 6. Now the FPGA is ready to perform consecutive readbacks. Readback is performed by loading the IR with the READBACK instruction and then shifting out the captured data from the SHIFT-DR state in the TAP. Readback data is captured when READBACK is made the current instruction in the TAP. Perform the rst readback by loading the IR with the READBACK instruction. This rst readback must be nished, which means shifting out the *entire* readback bitstream. To be safe, shift out the entire bitstream and then send three additional TCKs. 7. After performing the rst readback, another readback can be performed by going to the TEST-LOGIC-RESET state, and re-loading the READBACK instruction and performing the Readback as described in the previous paragraph. In summary, consecutive readbacks are performed by starting from TEST-LOGIC-RESET, loading the IR with the READBACK instruction, shifting out the readback bitstream plus three additional TCKs, and then going back to the TEST-LOGIC-RESET state.

Alternatively, if you do not want to go back to the TESTLOGIC-RESET state, realize that after shifting out the readback bitstream, a minimum of three additional clocks are needed on the readback register. So, after doing a readback, instead of going back to TEST-LOGIC-RESET, a user can opt to execute some other JTAG instruction, and then perform another readback. Also, this procedure is only needed if you intend to do more than one readback. If you intend only do a readback once, then the connection between the BSCAN symbol and the READBACK symbol is not needed. In that case, all that is needed is the BSCAN symbol instantiated with the boundary scan pads (TDI, TMS, TCK, & TDO) on the top level of the design.

Boundary Scan Description Language Files

Boundary Scan Description Language (BSDL) les describe boundary-scan-capable parts in a standard format used by automated test-generation software. The order and function of bits in the boundary-scan data register are included in this description. BSDL les are available in the Xilinx File Download area via the Xilinx WebLINX web site (www.xilinx.com).

Bibliography
The following publications contain information about the IEEE Standard 1149.1, and should be consulted for general boundary-scan information beyond the scope of this application note. Colin M. Maunder & Rodham E. Tulloss. The Test Access Port and Boundary Scan Architecture. IEEE Computer Society Press, 10662 Los Vaqueros Circle, P.O. Box 3014, Los Alamitos, CA 90720-1264. See www.computer.org/ cspress/catalog/st01096.htm John Fluke Mfg. Co. Inc. The ABC of Boundary Scan Test. John Fluke Mfg. Co. Inc., P.O. Box 9090, Everett, WA 98206. GenRad Inc. Meeting the Challenge of Boundary Scan. GenRad Inc., 300 Baker Ave., Concord, MA 01742-2174. Ken Parker. The Boundary Scan Handbook. Kluwer Academic Publications, (617) 871-6600. IEEE Standards, standards.ieee.org Texas Instruments, www.ti.com/sc/docs/jtag/jtaghome.htm

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Index

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Book Index
0 14*

Numerics
1 13-13 3-state buffer Spartan Series 4-204 XC3000 Series 4-326, 4-335, 13-23 XC4000 Series 4-27 XC5200 4-254 3-state net, global. See Global 3-State 5-input function XC3000 Series 13-19 XC5200 4-251 70% rule 13-22

DECODE 4-28 INIT 4-16, 4-202 LOC 4-36, 4-38, 4-40 MEDDELAY 4-23, 4-24 NODELAY 4-23, 4-194, 4-255 available products high-reliability 8-1 XC1700D 5-21, 5-32 XC3000 Series 4-395 XC4000 Series 4-151 XC9500 3-6

B
bar code 10-17 Base System Foundation Series (PC) 2-4, 2-5, 2-6, 2-7 basic moisture life test 11-2 battery backup in XC3000 Series 13-27, 13-43 BCLKIN 13-24 pin description XC3000 Series 4-357 BGA packages BG225 package drawings 10-32 BG256 package drawings 10-33 BG352, BG432 package drawings 10-34 BG560 package drawings 10-35 bidirectional (bidi) buffer XC3000 Series 4-329 bitstream combining for daisy chain 4-48, 4-209, 4-269 combining with MakePROM 4-338 copyrighting 13-43 format for configuration Spartan Series 4-210 XC4000 Series 4-49, 4-271 boundary scan access to 13-57 avoiding inadvertent activation 4-46, 4-207, 4-265 bypass register 13-56 configuration with 4-55, 4-213, 4-276 daisy chain configuration 13-60 data register 13-54 effect on GTS 4-25, 4-205, 4-256 implementing in schematic 4-45, 4-207, 4-264 Spartan Series 4-207 XC4000 Series 4-45, 4-264 library symbol 4-42, 4-45, 4-207, 4-230, 4-264, 4-267

A
A Simple Method of Estimating Power in XC4000XL/EX/E FPGAs 13-13 absolute maximum ratings overshoot and undershoot 13-51 specifications XC1700D 5-6, 5-17, 5-28 XC3000A 4-360 XC3000L 4-366 XC3100A 4-372 XC3100L 4-378 XC4000E 4-97, 8-12 XC5200 4-291 ACLK symbol 13-24 adaptor selector for programmer 9-2 address pins pin descriptions XC3000 Series 4-357 XC4000 Series 4-42, 4-267 advance specifications, definition of 1-1, 4-97, 4-291 algorithms, programmer 9-1 Answers database 12-2 applications Information 12-2 AppLINX CD 12-3 asynchronous peripheral configuration mode debugging hints 13-37 specifications XC3000 Series 4-348 XC4000 Series 4-68 XC3000 Series 4-347 XC4000 Series 4-42, 4-67, 4-267, 4-284 asynchronous RAM 4-15 attribute

14-1

Book Index

pin descriptions Spartan Series 4-229 XC4000 Series 4-41, 4-266 Spartan Series 4-205 specifications XC4000E 4-108, 4-112, 4-296 TAP controller 13-54 test access port (TAP) 13-54 user registers 13-56 XC4000 Series 4-27, 4-43, 4-257, 13-52 XC5200 4-262, 13-52 XC9500 3-16 Boundary Scan Description Language. See BSDL BSCAN symbol 4-42, 4-45, 4-207, 4-230, 4-264, 4-267 BSDL files Spartan Series 4-207 XC4000 Series 4-45, 4-264, 13-62 XC5200 13-62 XC9500 Series 3-16 buffer, 3-state Spartan Series 4-204 XC3000 Series 4-326, 4-335, 13-23 XC4000 Series 4-27 XC5200 4-254 buffer, bidirectional XC3000 Series 4-329 buffered switch matrix 4-32 BUFG symbol 4-260 BUFGE symbol 4-40, 4-42 BUFGLS symbol 4-38, 4-42 BUFGP symbol 4-36, 4-199 BUFGS symbol 4-36, 4-199 BUFT symbol 4-27 bus contention, internal 13-23 bypass register 13-56

C
carry logic Spartan Series 4-202 XC4000 Series 4-18 XC5200 4-252 cascade logic XC5200 4-253 CBQFP packages CB100 package drawings 10-43 CB100, CB164, CB196 package drawings 10-45 CB164 package drawings 10-44 CB228 package drawings 10-46 CCLK frequency variation XC3000 Series 13-27 in configuration debug 13-38 low-time restriction in XC3000 Series 13-27 pin description Spartan Series 4-229

XC3000 Series 4-356 XC4000 Series 4-41, 4-266 setting frequency Spartan Series 4-210 XC4000 Series 4-49, 4-270 use as configuration clock Spartan Series 4-208 XC3000 Series 4-340 XC4000 Series 4-47, 4-268 ceramic packages DIP DD8 package drawings 10-22 class, customer training 12-3 CLB. See configurable logic block clock diagram Spartan 4-198 XC4000E 4-37 XC4000EX 4-37 CMOS input Spartan Series 4-194 XC3000 Series 4-326 XC4000 Series 4-21, 4-255 XC5200 4-255 CMOS output Spartan Series 4-195 XC3000 Series 4-326, 13-22 XC4000 Series 4-24, 13-18 XC5200 4-255 configurable logic block (CLB) block diagram XC3000 Series 4-327 XC4000 Series 4-10 XC5200 4-251 carry logic Spartan Series 4-202 XC4000 Series 4-18 XC5200 4-252 cascade logic XC5200 4-253 flip-flop XC3000 Series 4-327, 13-21 XC4000 Series 4-10, 4-253 XC5200 4-251 function generator XC3000 Series 4-328, 13-19 XC4000 Series 4-9 XC5200 4-251 latch XC4000EX 4-10, 4-253 XC5200 4-251 RAM 4-12 routing associated with XC3000 Series 13-21 XC4000 Series 4-29 Spartan Series 4-191 specifications

14-2

XC3000A 4-361 XC3000L 4-367 XC3100A 4-373 XC3100L 4-379 XC5200 4-293 XC3000 Series 4-327, 13-19 XC4000 Series 4-9 XC5200 4-250, 4-251 differences from XC4000 and XC3000 4-248 configuration 13-45 asynchronous peripheral mode debugging hints 13-37 XC3000 Series 4-347 XC3000 Series specifications 4-348 XC4000 Series 4-42, 4-67, 4-267, 4-284 XC4000 Series specifications 4-68 bitstream copyrighting 13-43 bitstream format Spartan Series 4-210 XC4000 Series 4-49, 4-271 boundary scan pins, using 4-55, 4-213, 4-276, 13-60 clock. See CCLK configuration sequence Spartan Series 4-212 XC4000 Series 4-51, 4-272 control pins 13-40 daisy chain debugging hints 13-37 mixed family 4-48, 4-269, 13-39 Spartan Series 4-209 XC3000 Series 4-340 XC4000 Series 4-47, 4-269 debugging 13-35 express mode daisy chain 4-270 XC4000EX 4-266, 4-270, 4-271, 4-275, 4-286 initiating reconfiguration 13-46 length count 4-49, 4-55, 4-210, 4-271, 4-275, 4-338 master modes, general Spartan Series 4-208 XC3000 Series 4-337, 4-340 XC4000 Series 4-47, 4-55, 4-268, 4-275 XC4000 Series specifications 4-69 XC5200 specifications 4-289 master parallel mode debugging hints 13-36 XC3000 Series 4-345 XC3000 Series specifications 4-346 XC4000 Series 4-41, 4-63, 4-266, 4-280 XC4000 Series specifications 4-64, 4-281 master serial mode debugging hints 13-36 Spartan Series 4-208 Spartan Series specifications 4-209 XC3000 Series 4-343 XC3000 Series specifications 4-344

XC4000 Series 4-62, 4-279 XC4000 Series specifications 4-62, 4-279 memory cell 4-324, 13-41 mode selection of 13-35 modes, table of XC3000 Series 4-337 XC4000 Series 4-47, 4-268 peripheral mode XC3000 Series 4-347 XC3000 Series specifications 4-348 peripheral modes, general debugging hints 13-38 XC3000 Series 4-340 XC4000 Series 4-41, 4-47, 4-266, 4-269 pin descriptions Spartan Series 4-229 XC3000 4-356 XC4000 Series 4-41, 4-266 pin functions during Spartan Series 4-208 XC3000 Series 4-358 XC4000 Series 4-59, 4-60 XC5200 4-288 power-on reset XC3000 Series 4-337 reducing time 13-46 slave serial mode debugging hints 13-37 Spartan Series 4-209, 4-229 Spartan Series specifications 4-210 XC3000 Series 4-340, 4-349 XC3000 Series specifications 4-350 XC4000 Series 4-41, 4-47, 4-61, 4-266, 4-269, 4-278 XC4000 Series specifications 4-61 Spartan Series 4-208 specifications XC3000 Series 4-343 XC4000 Series 4-61, 4-278 start-up sequence XC3000 Series 13-28 XC4000 Series 4-52, 4-274 switching characteristics XC5200 4-289 synchronous peripheral mode XC4000 Series 4-41, 4-65, 4-266, 4-282 XC4000 Series specifications 4-66 XC3000 Series 4-337, 13-28 XC4000 Series 4-46, 4-268 XC5200 differences from XC4000 and XC3000 4-248 copyrighting bitstream 13-43 CPLD overview 1-2, 1-4, 13-9 product selection guide 13-7, 13-10

14-3

Book Index

CQ100 package pinout table XC3000 Series 4-387 CRC error checking Spartan Series 4-211 XC4000 Series 4-50, 4-271 crystal oscillator XC3000 Series 4-336, 4-342, 13-25 CS in configuration debug 13-36 CS0, CS1 pin descriptions XC4000 Series 4-42, 4-267 CS0, CS1, CS2 pin descriptions XC3000 Series 4-357 customer training 12-3 cyclic redundancy check (CRC) Spartan Series 4-211 XC4000 Series 4-50, 4-271

D
daisy chain creating bitstream 4-338 debugging hints 13-37 express mode XC4000EX 4-270 mixed family 4-48, 4-269, 13-39 Spartan Series 4-209 XC3000 Series 4-340 XC4000 Series 4-47, 4-269 data integrity 11-7 data pins pin descriptions XC3000 Series 4-357 XC4000 Series 4-43, 4-267 data register 13-54 data retention, XC9500 3-23, 3-31, 3-39, 3-47, 3-57, 3-67 data stream. See bitstream DC characteristics specifications XC3000A 4-359 XC3000L 4-365 XC3100A 4-371 XC3100L 4-377 XC4000E 4-98, 4-217, 8-13 XC5200 4-291 DD8 package package drawing 10-22 debugging configuration 13-35 DECODE attribute 4-28 decode logic. See cascade logic, edge decoder delay input delay 13-50

XC3000 Series 13-21 of configuration after power-up Spartan Series 4-213 XC4000 Series 4-52, 4-274 optional input delay XC4000 Series 4-23, 4-255 output XC4000 Series 13-16 with fast capture latch 4-24 design security XC9500 3-16 device literature 12-3 DIN in daisy chain Spartan Series 4-209 XC3000 Series 4-340 XC4000 Series 4-47, 4-269 pin description Spartan Series 4-230 XC3000 Series 4-357 XC4000 Series 4-43, 4-267 DIP package ceramic 10-22 plastic 10-23 direct interconnect XC3000 Series 4-329 XC4000EX 4-33 XC5200 4-250, 4-258 disk space requirements programmer 9-1 DONE during power-up 13-41 express mode configuration 4-270 going High after configuration XC3000 Series 4-341 XC4000 Series 4-55, 4-275 in configuration debug 13-36 not going High after configuration 13-35 pin description Spartan Series 4-229 XC4000 Series 4-41, 4-266 DONE/PROG during power-up 13-41 pin description XC3000 Series 4-356 double-length routing Spartan Series 4-198 XC4000 Series 4-32 XC5200 4-260 DOUT in daisy chain express mode 4-270 Spartan Series 4-209 XC3000 Series 4-340 XC4000 Series 4-47, 4-269 pin description

14-4

Spartan Series 4-230 XC3000 Series 4-357 XC4000 Series 4-43, 4-267 dry bag 10-15 dry bake 10-15 dual-port RAM 4-15, 4-200

E
edge decoder 4-28 edge-triggered RAM 4-13 advantages of 4-12, 4-202 EIAJ standards 10-1 electrical parameters programmer 9-1 electrostatic discharge (ESD) 11-8 endurance, XC9500 3-16 error checking, bitstream 4-50, 4-211, 4-271, 4-342 Spartan Series 4-211 XC3000 Series 4-342 XC4000 Series 4-50, 4-271 express configuration mode CRC not supported 4-271 synchronized to DONE XC4000EX 4-275 XC4000EX 4-266, 4-270, 4-271, 4-275, 4-286

forced air cooling vendors 10-10 Foundation Series 2-3 Base System (PC) 2-4, 2-5, 2-6, 2-7 FPGA advantages of 13-7 data integrity 11-7 overview 1-2, 1-4 product selection guide 1-6, 1-7, 1-8, 13-7, 13-10 security 13-42 function block XC9500 3-7 function generator in CLB XC3000 Series 4-328, 13-19 XC4000 Series 4-9 XC5200 4-251 in IOB XC4000EX 4-26 using as RAM 4-12

G
gate array advantages of FPGAs 1-3 GCK1 - GCK8 clock diagram 4-37 pin descriptions XC4000EX 4-42 GCLK symbol 13-24 general routing matrix (GRM) XC5200 4-249, 4-250, 4-257, 4-258 glitch avoidance in XC3000 Series 13-20 power supply 13-41 Global 3-State (GTS) Spartan Series 4-205 XC4000 Series 4-25, 4-40, 4-256 global buffer Spartan 4-198 specifications XC3000A 4-360 XC3000L 4-366 XC3100A 4-372 XC3100L 4-378 XC5200 4-292 XC3000 Series 4-335, 13-24 XC4000 Series 4-36 XC4000E 4-36 XC4000EX 4-38 XC5200 4-260 Global Early buffer (BUFGE) 4-26, 4-39, 4-42 fast pin-to-pin path 4-26 with fast capture latch 4-24 Global Low-Skew buffer (BUFGLS) 4-38, 4-42 Global Set/Reset (GSR) in CLB

F
factory floor life 10-15 failure analysis 11-3, 11-6 failures in time 11-2 fast capture latch 4-24 fast carry logic. See carry logic FastCONNECT switch matrix 3-13 FastFlash technology XC9500 3-19 FCLK1 - FCLK4 clock diagram 4-37 FDCE symbol 4-11, 4-254 FIFO implementing in XC4000 Series RAM 4-12 FITs 11-2 flip-flop in CLB XC3000 Series 4-327, 13-21 XC4000 Series 4-10, 4-11, 4-253, 4-254 XC5200 4-251 in IOB metastability 13-47 none in XC5200 4-255 Spartan Series 4-195, 4-196 XC3000 Series 4-326, 13-21 XC4000 Series 4-23, 4-24 in macrocell 3-8

14-5

Book Index

Spartan Series 4-205 XC4000 Series 4-11, 4-254 in IOB Spartan Series 4-195 XC4000 Series 4-26 GRM. See general routing matrix ground bounce XC4000 Series 13-16 GSR. See Global Set/Reset GTS. See Global 3-state

H
HardWire overview 1-4 HDC during power-up 13-41 pin description Spartan Series 4-230 XC3000 Series 4-340, 4-356 XC4000 Series 4-42, 4-267 heatsink vendors 10-10 hermeticity test 11-3 high temperature life test 11-2, 11-8 high-reliability (Hi-Rel) 8-1 overview 1-5 product availability 8-1 hold time on data input 13-50 XC4000 Series 4-23, 4-255 hotline support 12-2 HQ packages 10-13 thermal data 10-7 HQFP packages HQ100 package drawings 10-29 HQ160, HQ208, HQ240 package drawings 10-30 HQ304 package drawings 10-31 HTQFP packages HT100, HT144, HT176 package drawings 10-28 HW-130 programmer 9-1 hysteresis XC3000 Series 13-21

I
I/O block see also input/output block see also input/output cell XC9500 3-14 I/O count XC3000 Series 4-383 XC5200 4-318 I/V characteristics. See V/I characteristics IEEE Standard 1149.1 13-62 IFD symbol 4-21, 4-194 ILD symbol 4-21, 4-194

ILFFX symbol 4-24 ILFLX symbol 4-24 INIT during power-up 13-41 in configuration debug 13-38 in daisy chain 13-39 pin description Spartan Series 4-230 XC3000 Series 4-356 XC4000 Series 4-42, 4-267 INIT attribute 4-16, 4-202 initializing RAM 4-16, 4-202 input/output block (IOB) clock XC3000 Series 13-23 CMOS input Spartan Series 4-194 XC3000 Series 4-326 XC4000 Series 4-21, 4-255 XC5200 4-255 CMOS output Spartan Series 4-195 XC3000 Series 4-326, 13-22 XC4000 Series 4-24, 13-18 XC5200 4-255 delay on input 13-50 XC3000 Series 13-21 XC4000 Series 4-23, 4-255 during configuration Spartan Series 4-229 XC3000 Series 4-341 XC4000 Series 4-40, 4-265 fast capture latch 4-24 flip-flop metastability 13-47 function generator on output 4-26 maximum available I/O XC3000 Series 4-383 XC5200 4-318 multiplexer on output 4-26 optional delay with fast capture latch 4-24 pull-down resistor Spartan Series 4-195 XC4000 Series 4-26, 4-256 pull-up resistor Spartan Series 4-195 XC3000 Series 4-326, 4-357 XC4000 Series 4-26, 4-256 rise/fall time XC3000 Series 13-21 routing associated with Spartan Series 4-198 XC4000 Series 4-33 XC5200 4-250, 4-262 slew rate control Spartan Series 4-195

14-6

XC3000 Series 4-326 XC4000 Series 4-25, 4-256 XC5200 4-255 Spartan Series 4-193 specifications XC3000A 4-363 XC3000L 4-369 XC3100A 4-375 XC3100L 4-381 XC5200 4-295 TTL input Spartan Series 4-194 XC3000 Series 4-326 XC4000 Series 4-21, 4-255 XC5200 4-255 TTL output none in XC5200 4-255 Spartan Series 4-195 XC3000 Series 4-326 XC4000 Series 4-24 unused I/O Spartan Series 4-229 XC4000 Series 4-40, 4-265 VersaRing Spartan Series 4-198 XC4000 Series 4-33 XC5200 4-250, 4-262 XC3000 Series 4-325, 13-21 clock 13-23 XC4000 Series 4-21, 4-255 XC5200 4-255 XC9500 3-14 in-system programming XC9500 3-16 interconnect. See routing ISO9002 1-5, 11-1

J
JEDEC standards 10-1 JTAG. See boundary scan junction temperature junction-to-ambient 10-4 junction-to-case 10-4

L
latch fast capture latch 4-24 in CLB XC4000EX 4-10, 4-11, 4-253, 4-254 XC5200 4-251 in IOB none in XC5200 4-255 Spartan Series 4-194

XC3000 Series 4-326 XC4000 Series 4-21 latchup 11-8 LC. See logic cell LDC during power-up 13-41 in configuration debug 13-36 pin description Spartan Series 4-230 XC3000 Series 4-340, 4-356 XC4000 Series 4-42, 4-267 LDCE symbol 4-11, 4-254 lead fatigue test 11-3 length count configuration debugging hints 13-38 Spartan Series 4-210 XC3000 Series 4-338 XC4000 Series 4-49, 4-55, 4-67, 4-271, 4-275, 4-284 level-sensitive RAM 4-15 library symbol 3-state buffer BUFT, XC4000 Series 4-27 WAND1 4-27 WOR2AND 4-27 AND-gate in IOB OAND2 4-26 boundary scan BSCAN 4-42, 4-45, 4-207, 4-230, 4-264, 4-267 TCK, TDI, TDO, TMS 4-42, 4-45, 4-207, 4-230, 4-264, 4-267 fast capture latch ILFFX 4-24 ILFLX 4-24 flip-flop FDCE, XC4000 Series CLB 4-11, 4-254 IFD, Spartan Series IOB 4-194 IFD, XC4000 Series IOB 4-21 Global 3-State STARTUP 4-25, 4-205, 4-256 global buffer ACLK, XC3000 Series 13-24 BUFG, XC5200 4-260 BUFGE, XC4000EX 4-40, 4-42 BUFGLS, XC4000EX 4-38, 4-42 BUFGP, Spartan 4-199 BUFGP, XC4000E 4-36 BUFGS, Spartan 4-199 BUFGS, XC4000E 4-36 GCLK, XC3000 Series 13-24 Global Set/Reset STARTUP 4-11, 4-205, 4-254 latch ILD, Spartan Series IOB 4-194 ILD, XC4000 Series IOB 4-21 LDCE, XC4000EX CLB 4-11, 4-254 mode pins

14-7

Book Index

MD0, MD1, MD2 4-46, 4-268 oscillator OSC, Spartan Series 4-205 OSC4, XC4000 Series 4-28 OSC52, XC5200 4-257 output multiplexer OMUX2 4-26 readback READBACK 4-56, 4-214, 4-277 resistor PULLDOWN 4-26, 4-195, 4-257 PULLUP 4-26, 4-195, 4-257 wide decoder WAND1 4-28 LIM. See local interconnect matrix literature, technical 12-3 LOC attribute 4-36, 4-38, 4-40 local interconnect matrix (LIM) XC5200 4-250, 4-257 local phone support 12-2 logic cell (LC) XC5200 4-248, 4-249 longline Spartan Series 4-198 specifications XC5200 4-292 XC3000 Series 4-333, 13-21, 13-23 XC4000 Series 4-32 XC5200 4-260 lookup table (LUT). See function generator low voltage device XC4000 Series 4-5, 4-155, 8-7 XC4000XLT Family 4-175

M
M0, M1, M2. See mode pins M0/RTRIG pin description XC3000 Series 4-356 M1/RDATA pin description XC3000 Series 4-356 M2 pin description XC3000 Series 4-356 macrocell XC9500 3-8 MakeBits program bitstream generation XC3000 Series 4-339 crystal oscillator selection 4-342 start-up timing XC3000 Series 4-339 tie option 4-339 MakePROM program

combining bitstreams 4-338, 4-339 manufacturers. See vendors mass, package 10-12 master configuration modes, general Spartan Series 4-208 XC3000 Series 4-337, 4-340 XC4000 Series 4-47, 4-55, 4-268, 4-275 XC4000 Series specifications 4-69 XC5200 specifications 4-289 master parallel configuration mode debugging hints 13-36 specifications XC3000 Series 4-346 XC4000 Series 4-64, 4-281 XC3000 Series 4-345 XC4000 Series 4-41, 4-63, 4-266, 4-280 master serial configuration mode debugging hints 13-36 Spartan Series 4-208 specifications Spartan Series 4-209 XC3000 Series 4-344 XC4000 Series 4-62, 4-279 XC3000 Series 4-343 XC4000 Series 4-62, 4-279 maximum I/O XC3000 Series 4-383 XC5200 4-318 MD0, MD1, MD2 symbols 4-46, 4-268 Mean Time Between Failures (MTBF) metastability 13-48 MEDDELAY attribute 4-23, 4-24 memory cell, configuration 4-324, 11-7, 13-41 memory requirements programmer 9-1 metastability 13-47 MIL-STD-883B 1-5 mode pins pin descriptions XC4000 Series 4-41, 4-266 XC3000 Series 4-337 XC4000 Series 4-46, 4-268 moisture sensitivity in surface mount packages 10-14 multiplexer XC4000EX IOB 4-26

N
newsletter, XCell 12-3 NODELAY attribute 4-23, 4-194, 4-255

O
OAND2 symbol 4-26 octal routing 4-33

14-8

OE in configuration debug 13-36 OMUX2 symbol 4-26 on-chip oscillator. See oscillator, on-chip open-drain output 4-25, 4-256 operating conditions specifications XC1700D 5-6, 5-17, 5-28 XC3000A 4-359 XC3000L 4-365 XC3100A 4-371 XC3100L 4-377 XC4000E 4-97, 4-216, 8-12 XC5200 4-291 ordering information Spartan Series 4-242 XC1700D 5-10, 5-21, 5-32 XC4000 Series 4-113, 4-151 XC5200 4-318 OSC symbol 4-205 OSC4 symbol 4-28 OSC52 symbol 4-257 oscillator crystal XC3000 Series 4-336, 4-342, 13-25 on-chip 13-41 Spartan Series 4-205 XC3000 Series 13-27 XC4000 Series 4-28 XC5200 4-249, 4-257 output current XC3000 Series 13-23 XC4000 Series 4-24, 4-40, 4-256, 4-265, 13-15 XC5200 4-255 output multiplexer in XC4000EX IOB 4-26 output slew rate Spartan Series 4-195 XC3000 Series 4-326 XC4000 Series 4-25, 4-256 XC5200 4-255 overshoot 13-51

P
package availability high-reliability 8-1 XC3000 Series 4-395 XC4000 Series 4-151 XC9500 3-7 package drawing BG225 package 10-32 BG256 package 10-33 BG352, BG432 package 10-34 BG560 package 10-35 CB100 package 10-43 CB100, CB164, CB196 package 10-45

CB164 package 10-44 CB228 package 10-46 DD8 package 10-22 HQ100 package 10-29 HQ160, HQ208, HQ240 package 10-30 HQ304 package 10-31 HT100, HT144, HT176 package 10-28 PC20, PC28, PC44, PC68, PC84 package 10-26 PD8 package 10-23 PG120, PG132, PG156 package 10-37 PG175 package 10-38 PG191 package 10-39 PG223, PG299 package 10-40 PG411 package 10-41 PG475 package 10-42 PG68, PG84 package 10-36 PQ100 package 10-29 PQ304 package 10-31 PQ44, PQ160, PQ208, PQ240 package 10-30 SO20 package 10-25 SO8 package 10-24 TQ100, TQ144, TQ176 package 10-28 VO8 package 10-24 VQ44, VQ64, VQ100 package 10-27 packaging bar code 10-17 data acquisition 10-4 dimensions 10-1 dry bag 10-15 dry bake 10-15 EIAJ standards 10-1 EIJ standard board layout 10-3 factory floor life 10-15 handling and storage 10-15 JEDEC standards 10-1 mass 10-12 moisture sensitivity 10-14 orientation 10-3 reflow soldering 10-18 tape & reel packing 10-16 thermal characteristics 10-3 thermal database 10-4 thermal management 10-3 thermal resistance applying data 10-6 table of 10-5 thermally enhanced 10-13 vendors 10-10, 10-20 weight 10-12 PC44 package pinout table XC3000 Series 4-383 PC68 package pinout table XC3000 Series 4-385 PC84 package

14-9

Book Index

pinout table XC3000 Series 4-386 PCI compatibility XC4000 Series 4-7 PD8 package package drawing 10-23 performance XC3000 Series 4-353 XC5200 4-251 peripheral configuration mode specifications XC3000 Series 4-348 XC3000 Series 4-347 peripheral configuration modes, general debugging hints 13-38 specifications XC4000 Series 4-69 XC5200 4-289 XC3000 Series 4-340 XC4000 Series 4-41, 4-47, 4-266, 4-269 peripheral configuration modes. See also asynchronous peripheral, synchronous peripheral PG132 package pinout table XC3000 Series 4-388 PG175 package pinout table XC3000 Series 4-391 PG84 package pinout table XC3000 Series 4-385 PGA packages PG120, PG132, PG156 package drawings 10-37 PG175 package drawings 10-38 PG191 package drawings 10-39 PG223, PG299 package drawings 10-40 PG411 package drawings 10-41 PG475 package drawings 10-42 PG68, PG84 package drawings 10-36 PGCK1 - PGCK4 clock diagram 4-37, 4-198 pin descriptions 4-42, 4-230 phone support 12-2 pin description Spartan Series 4-229 pin descriptions functions during configuration Spartan Series 4-208 XC3000 Series 4-358 XC4000 Series 4-59, 4-60 XC5200 4-288 XC3000 Series 4-356 XC4000 Series 4-40, 4-265 pin locking XC9500 3-15 pinout table

CQ100 package XC3000 Series 4-387 device-specific Spartan Series 4-231 XC3000 Series 4-394 XC4000 Series 4-113 package-specific XC3000 Series 4-383 PC44 package XC3000 Series 4-383 PC68 package XC3000 Series 4-385 PC84 package XC3000 Series 4-386 PG132 package XC3000 Series 4-388 PG175 package XC3000 Series 4-391 PG84 package XC3000 Series 4-385 PQ100 package XC3000 Series 4-387 PQ160 package XC3000 Series 4-390 PQ208 package XC3000 Series 4-393 Spartan Series 4-231 TQ100 package XC3000 Series 4-387 TQ144 package XC3000 Series 4-389 TQ176 package XC3000 Series 4-392 VQ100 package XC3000 Series 4-387 VQ64 package XC3000 Series 4-384 XC3000 Series 4-383 XC3195 4-394 XC4000 Series 4-113 XC4003E 4-113 XC4005E/L 4-114 XC4006E 4-115 XC4008E 4-117 XC4010E/L 4-118 XC4013E/L 4-120 XC4013XLT 4-178 XC4020E 4-123 XC4025E 4-125, 4-128 XC4028EX/XL 4-125, 4-128 XC4028XLT 4-180 XC4044EX/XL 4-131 XC4052XL 4-135 XC5202 4-297 XC5204 4-299 XC5206 4-303

14-10

XC5210 4-306 XC5215 4-311 XC95108 3-42 XC95144 3-50 XC95216 3-60 XC95288 3-70 XC9536 3-26 XC9572 3-34 XCS05 4-231 XCS10 4-232 XCS20 4-233 XCS30 4-235 XCS40 4-237 pin-to-pin specifications XC5200 4-294 plastic packages DIP PD8 package drawings 10-23 PLCC packages PC20, PC28, PC44, PC68, PC84 package drawings 10-26 power consumption reduction of 10-9 XC3000 Series 4-355, 13-24 XC4000 Series 13-18 power distribution XC3000 Series 4-354 XC4000 Series 4-40, 4-265 power-down mode none in XC4000 Series 4-40 none in XC5200 4-249 XC3000 Series 4-337, 4-355, 13-27, 13-43 power-on reset XC3000 Series 4-337 power-up 13-41 power-up. See also start-up after configuration PQ packages thermal data 10-7 PQ100 package pinout table XC3000 Series 4-387 PQ160 package pinout table XC3000 Series 4-390 PQ208 package pinout table XC3000 Series 4-393 PQFP packages PQ100 package drawings 10-29 PQ304 package drawings 10-31 PQ44, PQ160, PQ208, PQ240 package drawings 10-30 preliminary specifications, definition of 1-1, 4-97, 4-291 Primary Global Buffer (BUFGP) 4-36, 4-42, 4-198, 4-230 product availability high-reliability 8-1

Spartan Series 4-241 XC3000 Series 4-395 XC4000 Series 4-151 XC9500 3-6 product qualification requirements 11-4 product selection guide CPLD 13-7, 13-10 FPGA 1-6, 1-7, 1-8, 13-7, 13-10 product term allocator XC9500 3-10 PROGRAM during power-up 13-41 inititating reconfiguration 13-46 pin description Spartan Series 4-229 XC4000 Series 4-41, 4-266 program cycles, XC9500 3-23, 3-31, 3-39, 3-47, 3-57, 3-67 programmable switch matrix (PSM) Spartan Series 4-197 XC3000 Series 4-329 XC4000 Series 4-30 programmer 9-1 algorithms 9-1 software 9-1 specifications 9-1 programming, in-system XC9500 3-16 programming. See configuration PROM bitstream generation Spartan Series 4-209 XC4000 Series 4-48, 4-269 configuration Spartan Series 4-190 XC3000 Series 4-343, 4-345 XC4000 Series 4-6, 4-62, 4-63, 4-279, 4-280 in configuration debug 13-36 overview 1-4 programmer 9-1 size Spartan 4-211 XC4000E 4-50 pseudo daisy chain for express mode XC4000EX 4-270 pull-down resistor IOB Spartan Series 4-195 XC4000 Series 4-26, 4-256 PULLDOWN symbol 4-26, 4-195, 4-257 pull-up resistor IOB Spartan Series 4-195, 4-229 XC3000 Series 4-326, 4-357 XC4000 Series 4-26, 4-41, 4-256, 4-266 longline

14-11

Book Index

none in XC5200 4-260 XC3000 Series 4-335 XC4000 Series 4-32 PULLUP symbol 4-26, 4-195, 4-257 PWRDWN 13-27 battery backup mode 13-43 in configuration debug 13-38 pin description XC3000 Series 4-356

Q
quad routing 4-32 qualification requirements 11-4 quality assurance 11-1

R
RAM asynchronous 4-15 configuration options XC4000 Series 4-12 dual-port 4-15, 4-200 edge-triggered 4-13 in CLB 4-12 initialization of 4-16, 4-202 level-sensitive 4-15 readback of contents 4-57, 4-214 setting mode 4-12 synchronous 4-13 RCLK pin description XC3000 Series 4-357 XC4000 Series 4-41, 4-266 RDY/BUSY pin description XC3000 Series 4-357 XC4000 Series 4-41, 4-266 readback CRC error checking Spartan Series 4-211 XC4000 Series 4-50, 4-271 Spartan Series 4-213, 4-229 specifications Spartan 4-215 XC3000 Series 4-351 XC4000E 4-58, 4-290 XC3000 Series 4-341 XC4000 Series 4-41, 4-56, 4-266, 4-276 XChecker cable 4-57, 4-215, 4-277 READBACK symbol 4-56, 4-214, 4-277 reconfiguration XC4000 Series 4-6 reconfiguration. See also configuration reflow soldering 10-18

reliability 11-2 RESET during power-up 13-41 in configuration debug 13-38 in daisy chain 13-39 inititating reconfiguration 13-46 pin description XC3000 Series 4-356 rise time requirement in XC3000 Series 13-29 reset Spartan Series See also Global Set/Reset XC3000 Series 4-342 XC4000 Series 4-40 See also Global Set/Reset resistance to solvents test 11-3 resistor IOB Spartan Series 4-195 XC3000 Series 4-326, 4-357 XC4000 Series 4-26, 4-256 pull-up on longline none in XC5200 4-260 XC3000 Series 4-335 XC4000 Series 4-32 with crystal oscillator 13-26 rise/fall time on input XC3000 Series 13-21 routing bidirectional (bidi) buffer 4-329 buffered switch matrix 4-32 direct interconnect XC3000 Series 4-329 XC4000EX 4-33 XC5200 4-250, 4-258 double-length Spartan Series 4-198 XC4000 Series 4-32 XC5200 4-260 global buffer Spartan 4-198 XC4000E 4-36 XC4000EX 4-38 longline Spartan Series 4-198 XC3000 Series 4-333, 13-21, 13-23 XC4000 Series 4-32 XC5200 4-260 octal 4-33 programmable switch matrix (PSM) Spartan Series 4-197 XC3000 Series 4-329 XC4000 Series 4-30 quad 4-32 single-length Spartan Series 4-197

14-12

XC4000 Series 4-30 XC5200 4-260 Spartan Series 4-196 VersaRing (IOB routing) Spartan Series 4-198 XC4000 Series 4-33 XC5200 4-250, 4-262 XC3000 Series 4-328, 13-21 XC4000 Series 4-29 XC5200 4-250, 4-258 differences from XC4000 and XC3000 4-248 RS pin description XC4000 Series 4-42, 4-267

S
salt atmosphere test 11-3 Secondary Global Buffer (BUFGS) 4-36, 4-42, 4-198, 4230, 4-267 security 3-16, 13-42 selection guide FPGA 1-6, 1-7, 1-8 service overview 1-5 setup time on data input 13-48, 13-50 XC3000 Series 13-21 SGCK1 - SGCK4 clock diagram 4-37, 4-198 pin description 4-42, 4-230, 4-267 single-length routing Spartan Series 4-197 XC4000 Series 4-30 XC5200 4-260 sink current. See output current slave serial configuration mode debugging hints 13-37 Spartan Series 4-209, 4-229 specifications Spartan Series 4-210 XC3000 Series 4-350 XC4000 Series 4-61, 4-69 XC5200 4-289 XC3000 Series 4-340, 4-349 XC4000 Series 4-41, 4-47, 4-61, 4-266, 4-269, 4-278 slew rate Spartan Series 4-195 XC3000 Series 4-326 XC4000 Series 4-25, 4-256 XC5200 4-255 SmartSearch 12-2 SMD. See Standard Microcircuit Drawing SO8 package package drawing 10-24 socket vendors 10-20 soft startup

Spartan Series 4-195 XC3000 Series 4-342 XC4000 Series 4-25, 4-256 software Foundation Series 2-3 Base System (PC) 2-4, 2-5, 2-6, 2-7 programmer 9-1 SOIC packages package drawings 10-24 SO20 package drawings 10-25 solderability test 11-3 Spartan clock diagram 4-198 global buffer 4-198 Primary Global Buffer (BUFGP) 4-198 Secondary Global Buffer (BUFGS) 4-198 Spartan Series 4-211 3-state buffer 4-204 bitstream format 4-210 boundary scan 4-205 BSDL files 4-207 carry logic 4-202 CMOS input 4-194 CMOS output 4-195 configurable logic block (CLB) 4-191 configuration 4-208 input/output block (IOB) 4-193 interconnect 4-196 on-chip oscillator 4-205 ordering information 4-242 pin description 4-229 pinout tables 4-231 product availability 4-241 readback 4-213 routing 4-196 soft startup 4-195 TTL input 4-194 TTL output 4-195 specifications absolute maximum ratings XC1700D 5-6, 5-17, 5-28 XC3000A 4-360 XC3000L 4-366 XC3100A 4-372 XC3100L 4-378 XC4000E 4-97, 8-12 XC5200E 4-291 XC9500 3-23, 3-31, 3-39, 3-47, 3-57, 3-67 advance, definition of 1-1, 4-97, 4-291 boundary scan XC4000E 4-108, 4-112, 4-296 CLB XC3000A 4-361 XC3000L 4-367 XC3100A 4-373 XC3100L 4-379

14-13

Book Index

XC5200 4-293 configuration XC3000 Series 4-343 XC4000 Series 4-61, 4-278 DC characteristics XC1700D 5-6, 5-17, 5-28 XC3000A 4-359 XC3000L 4-365 XC3100A 4-371 XC3100L 4-377 XC4000E 4-98, 4-217, 8-13 XC5200 4-291 global buffer XC3000A 4-360 XC3000L 4-366 XC3100A 4-372 XC3100L 4-378 XC5200 4-292 IOB XC3000A 4-363 XC3000L 4-369 XC3100A 4-375 XC3100L 4-381 XC5200 4-295 longline XC5200 4-292 operating conditions XC1700D 5-6, 5-17, 5-28 XC3000A 4-359 XC3000L 4-365 XC3100A 4-371 XC3100L 4-377 XC4000E 4-97, 4-216, 8-12 XC5200 4-291 XC9500 3-23, 3-31, 3-39, 3-47, 3-57, 3-67 pin-to-pin XC5200 4-294 XC9500 3-24, 3-32, 3-40, 3-48, 3-58, 3-68 preliminary, definition of 1-1, 4-97, 4-291 programmer 9-1 readback Spartan 4-215 XC3000 Series 4-351 XC4000E 4-58, 4-290 wide edge decoder XC4000E 4-100, 4-101, 8-15, 8-16 XC3000A 4-359 XC3000L 4-365 XC3100A 4-371 XC3100L 4-377 XC4000E 4-97 XC5200 4-291 speed grades available high-reliability 8-1 XC3000 Series 4-395 XC4000 Series 4-151

SRAM. See FPGA Standard Microcircuit Drawing (SMD) 1-5, 8-1 start-up after configuration XC3000 Series 13-28 XC4000 Series 4-52, 4-274 STARTUP symbol implementing Global 3-State 4-25, 4-205, 4-256 implementing Global Set/Reset 4-11, 4-205, 4-254 support 12-1 technical support hotline 12-2 surface mount packages moisture sensitivity 10-14 switch matrix, programmable (PSM) Spartan Series 4-197 XC3000 Series 4-329 XC4000 Series 4-30 synchronous peripheral configuration mode specifications XC4000 Series 4-66 XC4000 Series 4-41, 4-65, 4-266, 4-282 synchronous RAM 4-13 advantages of 4-12, 4-202

T
TAP controller 13-54 tape & reel packing 10-16 TCK,TDI,TDO,TMS. See boundary scan TCLKIN 13-24 pin description XC3000 Series 4-357 technical Information 12-2 technical literature 12-3 technical support 12-1 hotline 12-2 overview 1-5 telephone support 12-2 temperature cycling test 11-3 test access port (TAP) 13-54 testing 11-2 thermal characteristics 10-3 thermal data PQ/HQ packages 10-7 thermal management 10-3 thermal resistance applying data 10-6 table of 10-5 thermal shock test 11-3 theta-JA 10-4 theta-JC 10-4 time-to-market 1-3 timing model XC9500 3-17 TQ100 package pinout table XC3000 Series 4-387

14-14

TQ144 package pinout table XC3000 Series 4-389 TQ176 package pinout table XC3000 Series 4-392 TQFP packages TQ100, TQ144, TQ176 package drawings 10-28 training 1-5, 12-3 TSOP packages package drawings 10-24 TTL input Spartan Series 4-194 XC3000 Series 4-326, 4-341 XC4000 Series 4-21, 4-255 XC5200 4-255 TTL output none in XC5200 4-255 Spartan Series 4-195 XC3000 Series 4-326 XC4000 Series 4-24

VQFP packages VQ44, VQ64, VQ100 package drawings 10-27

W
WAND1 symbol 4-27, 4-28 Web site for Xilinx 1-1, 1-5, 12-2 WebLINX 1-1, 1-5, 12-2 Answers database 12-2 SmartSearch 12-2 weight, package 10-12 wide edge decoder 4-28 specifications XC4000E 4-100, 4-101, 8-15, 8-16 WOR2AND symbol 4-27 World Wide Web site for Xilinx 1-1, 1-5, 12-2 WS pin description XC3000 Series 4-357 XC4000 Series 4-42, 4-267

U
unbiased pressure pot test 11-2 undershoot 13-51 unused I/O Spartan Series 4-229 XC4000 Series 4-40, 4-265 user registers in boundary scan 13-56

X
XC1700 programmer 9-1 XC2000 13-7 overview 13-8 XC3000 13-7 overview 13-8 XC3000 Series 4-321, 4-342, 13-7, 13-19 3-state buffer 4-326, 4-335, 13-23 5-input function 13-19 available I/O 4-383 battery backup 13-27, 13-43 CCLK frequency variation 13-27 CMOS input 4-326 CMOS output 4-326, 13-22 configurable logic block (CLB) 4-327, 13-19 configuration 4-337, 13-28 specifications 4-343 crystal oscillator 4-336, 4-342, 13-25 feature summary 4-321 glitch avoidance 13-20 global buffer 4-335, 13-24 hysteresis 13-21 input/output block (IOB) 4-325, 13-21 internal bus contention 13-23 on-chip oscillator 13-27 output current 13-23 overview 13-8 performance 4-353 pin descriptions 4-356 pinout tables 4-383 power consumption 4-355, 13-24 power distribution 4-354

V
V/I characteristics XC3000 Series 13-22 XC4000 Series 13-15 vendors forced air cooling 10-10 heatsink 10-10 socket 10-20 VersaBlock 4-249 VersaRing Spartan Series 4-198 XC4000 Series 4-33 XC5200 4-250, 4-262 VO8 package package drawing 10-24 VPP in configuration debug 13-36 VQ100 package pinout table XC3000 Series 4-387 VQ64 package pinout table XC3000 Series 4-384

14-15

Book Index

power-down mode 4-337, 4-355 product availability 4-395 readback 4-341 rise/fall time 13-21 routing 4-328 soft startup 4-342 specifications configuration 4-343 XC3000A 4-359 XC3000L 4-365 XC3100A 4-371 XC3100L 4-377 TTL input 4-326 TTL output 4-326 V/I characteristics 13-22 XC3000A overview 4-322 specifications 4-359 XC3000L overview 4-322 specifications 4-365 XC3100 13-7 overview 13-8 XC3100A overview 4-322, 13-8 specifications 4-371 XC3100L overview 4-322, 13-8 specifications 4-377 XC3195 pinout table 4-394 XC4000 overview 13-8 XC4000 Series 4-5, 4-50, 4-155, 4-271, 13-7 3-state buffer 4-27 bitstream format 4-49, 4-271 boundary scan 4-43, 13-52 BSDL files 13-62 carry logic 4-18 CMOS input 4-21, 4-255 CMOS output 4-24, 13-18 configurable logic block (CLB) 4-9 configuration 4-46, 4-268 specifications 4-61, 4-278 CRC error checking 4-271 edge decoder 4-28 feature summary 4-5, 4-155 global buffer 4-36 ground bounce 13-16 input/output block (IOB) 4-21, 4-255 interconnect 4-29 internal bus contention 13-23 low voltage device 4-5, 4-155, 8-7 on-chip oscillator 4-28 ordering information 4-113, 4-151 output current 4-24, 4-256, 13-15

output delay 13-16 pin descriptions 4-40, 4-265 pinout tables 4-113 power consumption 13-18 power distribution 4-40, 4-265 product availability 4-151 RAM 4-12 readback 4-56, 4-276 routing 4-29 soft startup 4-25, 4-256 specifications configuration 4-61, 4-278 XC4000E 4-97 TTL input 4-21, 4-255 TTL output 4-24 V/I characteristics 13-15 wide edge decoder 4-28 XC4000A overview 13-8 XC4000E clock diagram 4-37 compared to XC4000 4-7 global buffer 4-36 overview 13-8 Primary Global Buffer (BUFGP) 4-36 Secondary Global Buffer (BUFGS) 4-36 specifications 4-97 XC4000EX buffered switch matrix 4-32 clock diagram 4-37 compared to XC4000 4-7, 4-8 fast capture latch on inputs 4-24 function generator in IOB 4-26 global buffer 4-38 Global Early buffer (BUFGE) 4-24, 4-39 Global Low-Skew buffer (BUFGLS) 4-38 interconnect 4-29 latch in CLB 4-10, 4-253 multiplexer in IOB 4-26 octal routing 4-33 overview 13-9 quad routing 4-32 routing 4-29 VersaRing (IOB routing) 4-33, 4-198 XC4000H overview 13-9 XC4000XL 4-5, 8-7 XC4000XLT Family 4-175 feature summary 4-175 low voltage device 4-175 XC4003E pinout table 4-113 XC4005E/L pinout table 4-114 XC4006E pinout table 4-115

14-16

XC4008E pinout table 4-117 XC4010E/L pinout table 4-118 XC4013E/L pinout table 4-120 XC4013XLT pinout table 4-178 XC4020E pinout table 4-123 XC4025E pinout table 4-125, 4-128 XC4028EX/XL pinout table 4-125, 4-128 XC4028XLT pinout table 4-180 XC4044EX/XL pinout table 4-131 XC4052XL pinout table 4-135 XC5200 13-7 3-state buffer 4-254 5-input function 4-251 available I/O 4-318 boundary scan 4-262, 13-52 BSDL files 13-62 carry logic 4-252 cascade logic 4-253 CMOS input 4-255 CMOS output 4-255 compared to XC4000 and XC3000 4-248 configurable logic block (CLB) 4-250, 4-251 differences from XC4000 and XC3000 4-248 configuration differences from XC4000 and XC3000 4-248 general routing matrix (GRM) 4-249, 4-250, 4-257, 4-258 global buffer 4-260 input/output block (IOB) 4-255 interconnect 4-250, 4-258 latch in CLB 4-251 local interconnect matrix (LIM) 4-250, 4-257 logic cell (LC) 4-248, 4-249 on-chip oscillator 4-257 ordering information 4-318 output current 4-255 overview 13-9 performance 4-251 routing 4-250, 4-258 differences from XC4000 and XC3000 4-248 specifications 4-289, 4-291 XC5200 4-291 TTL input 4-255 TTL output not supported 4-255 VersaBlock 4-249 VersaRing (IOB routing) 4-250, 4-262

XC5202 pinout table 4-297 XC5204 pinout table 4-299 XC5206 pinout table 4-303 XC5210 pinout table 4-306 XC5215 pinout table 4-311 XC6200 overview 13-9 XC7200A overview 13-9 XC7300 overview 13-9 XC9500 BSDL files 3-16 design security 3-16 endurance 3-16 FastCONNECT switch matrix 3-13 function block 3-7 I/O block 3-14 in-system programming 3-16 overview 3-5, 13-9 package availability and device I/O pins 3-7 pin locking capability 3-15 product availability 3-6 product term allocator 3-10 timing model 3-17 XC95108 pinout table 3-42 XC95144 pinout table 3-50 XC95216 pinout table 3-60 XC95288 pinout table 3-70 XC9536 pinout table 3-26 XC9572 pinout table 3-34 XCELL newsletter 1-1 XCell newsletter 12-3 XChecker cable readback Spartan Series 4-215 XC4000 Series 4-57, 4-277 XCS05 pinout table 4-231 XCS10 pinout table 4-232 XCS20 pinout table 4-233 XCS30 pinout table 4-235

14-17

Book Index

XCS40 pinout table 4-237 Xilinx about the company 1-2 quality assurance and reliability 11-1 technical support 1-5 Web site 1-1, 1-5, 12-2 XCELL newsletter 1-1

XCell newsletter 12-3 xtal oscillator. See crystal oscillator XTL1 pin description XC3000 Series 4-357 XTL2 pin description XC3000 Series 4-357

14-18