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74F10 Triple 3-Input NAND Gate 74F11 Triple 3-Input AND Gate

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0% found this document useful (0 votes)
65 views8 pages

74F10 Triple 3-Input NAND Gate 74F11 Triple 3-Input AND Gate

data

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radu
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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INTEGRATED CIRCUITS

74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate
Product specification IC15 Data Handbook 1989 Sep 20

Philips Semiconductors

Philips Semiconductors

Product specification

Gates
74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate
TYPE 74F10 74F11 TYPICAL PROPAGATION DELAY 3.5ns 4.2ns TYPICAL SUPPLY CURRENT (TOTAL) 3.3mA 5.3mA 14-pin plastic DIP 14-pin plastic SO

74F10, 74F11

ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F10N, N74F11N N74F10D, N74F11D PKG DWG # SOT27-1 SOT108-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE


PINS Dna, Dnb, Dnc Qn Qn Data inputs Data output (74F10) Data output (74F11) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 50/33 50/33 LOAD VALUE HIGH/LOW 20A/0.6mA 1.0mA/20mA 1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.

PIN CONFIGURATIONS
74F10
D0a D0b D1a D1b D1c Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC D0c Q0 D2c D2b D2a Q2 D0a D0b D1a D1b D1c Q1 GND 1 2 3 4 5 6 7

74F11
14 13 12 11 10 9 8 VCC D0c Q0 D2c D2b D2a Q2

SF00055

SF00056

LOGIC SYMBOLS
74F10
1 2 13 3 4 5 9 10 11 1 2 13

74F11
3 4 5 9 10 11

D0a

D0b D0c D1a

D1b

D1c

D2a

D2b

D2c

D0a

D0b D0c D1a

D1b

D1c

D2a

D2b

D2c

Q0

Q1

Q2

Q0

Q1

Q2

VCC = Pin 14 GND = Pin 7

12

VCC = Pin 14 GND = Pin 7

12

SF00057

SF00058

September 20, 1989

8530329 97683

Philips Semiconductors

Product specification

Gates

74F10, 74F11

IEC/IEEE SYMBOLS
74F10
1 2 13 3 4 5 9 10 11 8 6

74F11
1 12 2 13 3 4 5 9 10 11 8 6

&

&
12

SF00059

SF00060

LOGIC DIAGRAMS
74F10
1 D0a 2 D0b 13 D0c D1a D1b D1c D2a D2b VCC = Pin 14 GND = Pin 7 D2c 3 4 5 9 10 11 VCC = Pin 14 GND = Pin 7 8 Q2 6 Q1 D0c D1a D1b D1c D2a D2b D2c 3 4 5 9 10 11 8 Q2 6 Q1 12 Q0 D0b 13 D0a 2 12 Q0 1

74F11

SF00061

SF00062

FUNCTION TABLE
INPUTS Dna L L L L H H H Dnb L L H H L L H Dnc L H L H L H L OUTPUTS 74F10 Qn H H H H H H H L 74F11 Qn L L L L L L L H

H H H NOTES: 1. H = High voltage level 2. L = Low voltage level

September 20, 1989

Philips Semiconductors

Product specification

Gates

74F10, 74F11

ABSOLUTE MAXIMUM RATINGS


(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING 0.5 to +7.0 0.5 to +7.0 30 to +5 0.5 to VCC 40 0 to +70 65 to +150 UNIT V V mA V mA C C

RECOMMENDED OPERATING CONDITIONS


LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 18 1 20 +70 NOM 5.0 MAX 5.5 V V V mA mA mA C UNIT

DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX Low level output voltage Low-level Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 74F10 ICC Supply current (total) 74F11 ICCH ICCL ICCH ICCL VCC = MIN, VIL = MAX VIH = MIN, IOl = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX VIN = GND VIN = 4.5V VIN = 4.5V VIN = GND 60 1.8 6.0 4.7 7.2 10%VCC 5%VCC 10%VCC 5%VCC LIMITS MIN 2.5 2.7 3.4 0.35 0.35 0.73 0.50 0.50 1.2 100 20 0.6 150 2.1 7.7 6.2 9.7 mA V A A mA mA mA V TYP2 MAX UNIT

VOH O

High level output voltage High-level

VOL O VIK II IIH IIL IOS

VCC = MAX

NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.

September 20, 1989

Philips Semiconductors

Product specification

Gates

74F10, 74F11

AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL Propagation delay Dna, Dnb, Dnc to Qn Propagation delay Dna, Dnb, Dnc to Qn 74F10 74F11 Waveform 1 Waveform 2 2.4 1.5 3.0 2.5 TYP 3.7 3.2 4.2 4.1 MAX 5.0 4.3 5.6 5.5 VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 2.4 1.5 3.0 2.5 MAX 6.0 5.3 6.6 6.5 ns ns UNIT

AC WAVEFORMS
For all waveforms, VM = 1.5V.

Dna, Dnb, Dnc

VM tPHL

VM tPLH

Dna, Dnb, Dnc

VM tPLH

VM tPHL

Qn

VM

VM

Qn

VM

VM

SF00064

SF00063

Waveform 1. Propagation Delay for Inverting Outputs (74F10)

Waveform 2. Propagation Delay for Non-Inverting Outputs (74F11)

TEST CIRCUIT AND WAVEFORM


VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)

tTLH (tr ) 90% POSITIVE PULSE VM 10% tw

tTHL (tf ) AMP (V) 90% VM 10% 0V

Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.

Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006

September 20, 1989

Philips Semiconductors

Product specification

Gates

74F10, 74F11

DIP14: plastic dual in-line package; 14 leads (300 mil)

SOT27-1

1989 Sep 20

Philips Semiconductors

Product specification

Gates

74F10, 74F11

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

1989 Sep 20

Philips Semiconductors

Product specification

Gates

74F10, 74F11

Data sheet status


Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

Production

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions
Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers
Life support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 940883409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05056

Philips Semiconductors
yyyy mmm dd 8

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