APPLICATION

NOTE
AP-70
ApiiI 1980
Using the Intel MCS-51
Boolean Processing
Capabilities
JOHN WHARTON
MICROCONTROLLFR APPLICATIONS
Order Number 203830-001
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COPYRIGHT INTEL CORPORATION 1996
USING THE INTEL MCS-51
BOOLEAN PROCESSING
CAPABILITIES
CONTENTS PAGE
10 INTRODUCTION 1
20 BOOLEAN PROCESSOR
OPERATION 2
Processing Elements 3
Direct Bit Addressing 5
Instruction Set 8
Simple Instruction Combinations 10
30 BOOLEAN PROCESSOR
APPLICATIONS 12
Design Example 1Bit Permutation 12
Design Example 2Software Serial
IO 17
Design Example 3Combinational
Logic Equations 19
Design Example 4Automotive
Dashboard Functions 23
Design Example 5Complex Control
Functions 30
Additional Functions and Uses 39
40 SUMMARY 40
APPENDIX A A-1
AP-70
10 INTRODUCTION
The InteI miciocontioIIei famiIy now has thiee new
membeis: the InteI 8031, 8051, and 8751 singIe-chip
miciocomputeis. These devices, shown in Figuie 1, wiII
aIIow whoIe new cIasses of pioducts to benefit fiom
iecent advances in Integiated FIectionics. Thanks to
InteIs new HMOS technoIogy, they piovide Iaigei pio-
giam and data memoiy spaces, moie fIexibIe I/O and
peiipheiaI capabiIities, gieatei speed, and Iowei system
cost than any pievious-geneiation singIe-chip micio-
computei.
2038301
Figure 1 8051 Family Pinout Diagram
TabIe 1 summaiizes the quantitative diffeiences be-
tween the membeis of the MCS-48 and 8051 famiIies.
The 8751 contains 4K bytes of FPROM piogiam mem-
oiy fabiicated on-chip, whiIe the 8051 iepIaces the
FPROM with 4K bytes of Iowei-cost mask-
piogiammed ROM. The 8031 has no piogiam memoiy
on-chip, instead, it accesses up to 64K bytes of piogiam
memoiy fiom exteinaI memoiy. Otheiwise, the thiee
new famiIy membeis aie identicaI. Thioughout this
Note, the teim 8051 wiII iepiesent aII membeis of the
8051 FamiIy, unIess specificaIIy stated otheiwise.
The CPU in each miciocomputei is one of the indus-
tiys fastest and most efficient foi numeiicaI caIcuIa-
tions on byte opeiands. But contioIIeis often deaI with
bits, not bytes: in the ieaI woiId, switch contacts can
onIy be open oi cIosed, indicatois shouId be eithei Iit oi
daik, motois aie eithei tuined on oi off, and so foith.
Foi such contioI situations the most significant aspect
of the MCS-51 aichitectuie is its compIete haidwaie
suppoit foi one-bit, oi Boolean vaiiabIes (named in
honoi of Mathematician Oeoige BooIe) as a sepaiate
data type.
The 8051 incoipoiates a numbei of speciaI featuies
which suppoit the diiect manipuIation and testing of
individuaI bits and aIIow the use of singIe-bit vaiiabIes
in peifoiming IogicaI opeiations. Taken togethei, these
featuies aie iefeiied to as the MCS-51 Boolean Proces-
sor. WhiIe the bit-piocessing capabiIities aIone wouId be
adequate to soIve many contioI appIications, theii tiue
powei comes when they aie used in conjunction with
the miciocomputeis byte-piocessing and numeiicaI ca-
pabiIities.
Many concepts embodied by the BooIean Piocessoi wiII
ceitainIy be new even to expeiienced miciocomputei
system designeis. The puipose of this AppIication Note
is to expIain these concepts and show how they aie
used.
Foi detaiIed infoimation on these paits iefei to the In-
tel Microcontroller Handbook oidei numbei 210918.
The instiuction set, assembIy Ianguage, and use of the
8051 assembIei (ASM51) aie fuithei desciibed in the
MCS-51 Macro Assembler Users Guide for DOS
Systems oidei numbei 122753.
Table 1 Features of Intels Single-Chip Microcomputers
EPROM ROM External Program Data Instr Input
Interrupt Reg
Program Program Program Memory Memory Cycle Output
Sources Banks
Memory Memory Memory (IntMax) (Bytes) Time Pins
8748 8048 8035 1K 4K 64 25 ms 27 2 2
8049 8039 2K 4K 128 136 ms 27 2 2
8751 8051 8031 4K 64K 128 10 ms 32 5 4
1
AP-70
20 BOOLEAN PROCESSOR
OPERATION
The BooIean Piocessing capabiIities of the 8051 aie
based on concepts which have been aiound foi some
time. DigitaI computei systems of wideIy vaiying de-
signs aII have foui functionaI eIements in common (Fig-
uie 2):
a centiaI piocessoi (CPU) with the contioI, timing,
and Iogic ciicuits needed to execute stoied instiuc-
tions:
a memoiy to stoie the sequence of instiuctions mak-
ing up a piogiam oi aIgoiithm:
data memoiy to stoie vaiiabIes used by the pio-
giam:
and
some means of communicating with the outside
woiId.
The CPU usuaIIy incIudes one oi moie accumuIatois oi
speciaI iegisteis foi computing oi stoiing vaIues duiing
piogiam execution. The instiuction set of such a
piocessoi geneiaIIy incIudes, at a minimum, opeiation
cIasses to peifoim aiithmetic oi IogicaI functions on
piogiam vaiiabIes, move vaiiabIes fiom one pIace to
anothei, cause piogiam execution to jump oi condi-
tionaIIy bianch based on iegistei oi vaiiabIe states, and
instiuctions to caII and ietuin fiom subioutines. The
piogiam and data memoiy functions sometimes shaie a
singIe memoiy space, but this is not aIways the case.
When the addiess spaces aie sepaiated, piogiam and
data memoiy need not even have the same basic woid
width.
A digitaI computeis fIexibiIity comes in pait fiom
combining simpIe fast opeiations to pioduce moie com-
pIex (aIbeit sIowei) ones, which in tuin Iink togethei
eventuaIIy soIving the piobIem at hand. A foui-bit CPU
executing muItipIe piecision subioutines can, foi exam-
pIe, peifoim 64-bit addition and subtiaction. The sub-
ioutines couId in tuin be buiIding bIocks foi fIoating-
point muItipIication and division ioutines. FventuaIIy,
the foui-bit CPU can simuIate a fai moie compIex vii-
tuaI machine.
In fact, any digitaI computei with the above foui func-
tionaI eIements can (given time) compIete any aIgo-
iithm (though the pioveibiaI ioom fuII of chimpanzees
at woid piocessois might fiist ie-cieate Shakespeaies
cIassics and this AppIication Note)! This fact offeis Iit-
tIe consoIation to pioduct designeis who want pio-
giams to iun as quickIy as possibIe. By definition, a
ieaI-time contioI aIgoiithm must pioceed quickIy
enough to meet the pieoidained speed constiaints of
othei equipment.
One of the factois deteimining how Iong it wiII take a
miciocomputei to compIete a given choie is the num-
bei of instiuctions it must execute. What makes a given
computei aichitectuie paiticuIaiIy weII- oi pooiIy-suit-
ed foi a cIass of piobIems is how weII its instiuction set
matches the tasks to be peifoimed. The bettei the
piimitive opeiations coiiespond to the steps taken by
the contioI aIgoiithm, the Iowei the numbei of instiuc-
tions needed, and the quickei the piogiam wiII iun. AII
eIse being equaI, a CPU suppoiting 64-bit aiithmetic
diiectIy couId cIeaiIy peifoim fIoating-point math fast-
ei than a machine bogged-down by muItipIe-piecision
subioutines. In the same way, diiect suppoit foi bit
manipuIation natuiaIIy Ieads to moie efficient pio-
giams handIing the binaiy input and output conditions
inheient in digitaI contioI piobIems.
2038302
Figure 2 Block Diagram for Abstract Digital Computer
2
AP-70
Processing Elements
The intioduction stated that the 8051s bit-handIing ca-
pabiIities aIone wouId be sufficient to soIve some con-
tioI appIications. Lets see how the foui basic eIements
of a digitaI computei-a CPU with associated iegisteis,
piogiam memoiy, addiessabIe data RAM, and I/O ca-
pabiIity-ieIate to BooIean vaiiabIes.
CPU. The 8051 CPU incoipoiates speciaI Iogic devoted
to executing seveiaI bit-wide opeiations. AII toId, theie
aie 17 such instiuctions, aII Iisted in TabIe 2. Not
shown aie 94 othei (mostIy byte-oiiented) 8051 instiuc-
tions.
Program Memory. Bit-piocessing instiuctions aie
fetched fiom the same piogiam memoiy as othei aiith-
metic and IogicaI opeiations. In addition to the instiuc-
Table 2 MCS-51 Boolean
Processing Instruction Subset
Mnemonic Description Byte Cyc
SETB C Set Carry flag 1 1
SETB bit Set direct Bit 2 1
CLR C Clear Carry flag 1 1
CLR bit Clear direct bit 2 1
CPL C Complement Carry flag 1 1
CPL bit Complement direct bit 2 1
MOV Cbit Move direct bit to Carry flag 2 1
MOV bitC Move Carry flag to direct bit 2 2
ANL Cbit AND direct bit to Carry flag 2 2
ANL Cbit AND complement of direct 2 2
bit to Carry flag
ORL Cbit OR direct bit to Carry flag 2 2
ORL Cbit OR complement of direct 2 2
bit to Carry flag
JC rel Jump if Carry is flag is set 2 2
JNC rel Jump if No Carry flag 2 2
JB bitrel Jump if direct Bit set 3 2
JNB bitrel Jump if direct Bit Not set 3 2
JBC bitrel Jump if direct Bit is set 3 2
Clear bit
Address mode abbreviations
CCarry flag
bit128 software flags any IO pin control or status
bit
relAll conditional jumps include an 8-bit offset byte
Range is a127 b128 bytes relative to first byte of the
following instruction
AII mnemonics copyiighted

InteI Coipoiation 1980.

tions of TabIe 2, seveiaI sophisticated piogiam contioI
featuies Iike muItipIe addiessing modes, subioutine
nesting, and a two-IeveI inteiiupt stiuctuie aie usefuI in
stiuctuiing BooIean Piocessoi-based piogiams.
BooIean instiuctions aie one, two, oi thiee bytes Iong,
depending on what function they peifoim. Those in-
voIving onIy the caiiy fIag have eithei a singIe-byte
opcode oi an opcode foIIowed by a conditionaI-bianch
destination byte (Figuie 3a). The moie geneiaI instiuc-
tions add a diiect addiess byte aftei the opcode to
specify the bit affected, yieIding two oi thiee byte en-
codings (Figuie 3b). Though this foimat aIIows poten-
tiaIIy 256 diiectIy addiessabIe bit Iocations, not aII of
them aie impIemented in the 8051 famiIy.
opcode
SETB C
CLR C
CPL C
opcode displacement
JC rel
JNC rel
a) Carry Control and Test Instructions
opcode bit address
SETB bit
CLR bit
CPL bit
ANL C bit
ANL C bit
ORL C bit
ORL C bit
MOV C bit
MOV bitC
opcode bit address displacement
JB bit rel
JNB bit rel
JBC bit rel
b) Bit Manipulation and Test Instructions
Figure 3 Bit Addressing Instruction Formats
3
AP-70
2038303
a) RAM Bit Addresses b) Special Function Register Bit Addresses
Figure 4 Bit Address Maps
Data Memory. The instiuctions in Figuie 3b can opei-
ate diiectIy upon 144 geneiaI puipose bits foiming the
BooIean piocessoi RAM. These bits can be used as
softwaie fIags oi to stoie piogiam vaiiabIes. Two opei-
and instiuctions use the CPUs caiiy fIag (C) as a
speciaI one-bit iegistei: in a sense, the caiiy is a BooIe-
an accumuIatoi foi IogicaI opeiations and data tians-
feis.
InputOutput. AII 32 I/O pins can be addiessed as indi-
viduaI inputs, outputs, oi both, in any combination.
Any pin can be a contioI stiobe output, status (Test)
input, oi seiiaI I/O Iink impIemented via softwaie. An
additionaI 33 individuaIIy addiessabIe bits ieconfiguie,
contioI, and monitoi the status of the CPU and aII on-
chip peiipheiaI functions (timei counteis, seiiaI poit
modes, inteiiupt Iogic, and so foith).
4
AP-70
(MSB) (LSB)
CY AC F0 RS1 RS0 OV P
Symbol Position Name and Significance
CY PSW7 Carry flag
Setcleared by hardware or
software during certain arithme-
tic and logical instructions
AC PSW6 Auxiliary Carry flag
Setcleared by hardware during
addition or subtraction instruc-
tions to indicate carry or borrow
out of bit 3
F0 PSW5 Flag 0
Setclearedtested by software
as a user-defined status flag
RS1 PSW4 Register bank Select control
bits
RS0 PSW3 1 0 Setcleared by software
to determine working register
bank (see Note)
OV PSW2 Overflow flag
Setcleared by hardware during
arithmetic instructions to indi-
cate overflow conditions
PSW1 (reserved)
P PSW0 Parity flag
Setcleared by hardware each
instruction cycle to indicate an
oddeven number of one bits
in the accumulator ie even
parity
Note- the contents of (RS1 RS0) en-
able the working register banks
as follows
(00) - Bank 0 (00H07H)
(01) - Bank 1 (08H0FH)
(10) - Bank 2 (10H17H)
(11) - Bank 3 (18H1FH)
Figure 5 PSWProgram Status Word Organization
(MSB) (LSB)
RD WR T1 T0 INT1 INT0 TXD RXD
Symbol Position Name and Significance
RD P37 Read data control output
Active low pulse generated by
hardware when external data
memory is read
WR P36 Write data control output
Active low pulse generated by
hardware when external data
memory is written
T1 P35 Timercounter 1 external input
or test pin
T0 P34 Timercounter 0 external input
or test pin
INT1 P33 Interrupt 1 input pin
Low-level or falling-edge trig-
gered
INT0 P32 Interrupt 0 input pin
Low-level or falling-edge trig-
gered
TXD P31 Transmit Data pin for serial port
in UART mode Clock output in
shift register mode
RXD P30 Receive Data pin for serial port
in UART mode Data IO pin in
shift register mode
Figure 6 P3Alternate IO Functions of Port 3
Direct Bit Addressing
The most significant bit of the diiect addiess byte se-
Iects one of two gioups of bits. VaIues between 0 and
127 (00H and 7FH) define bits in a bIock of 32 bytes of
on-chip RAM, between RAM addiesses 20H and 2FH
(Figuie 4a). They aie numbeied consecutiveIy fiom the
Iowest-oidei bytes Iowest-oidei bit thiough the high-
est-oidei bytes highest-oidei bit.
Bit addiesses between 128 and 255 (80H and 0FFH)
coiiespond to bits in a numbei of speciaI iegisteis,
mostIy used foi I/O oi peiipheiaI contioI. These posi-
tions aie numbeied with a diffeient scheme than RAM:
the five high-oidei addiess bits match those of the ieg-
isteis own addiess, whiIe the thiee Iow-oidei bits iden-
tify the bit position within that iegistei (Figuie 4b).
5
AP-70
Notice the coIumn IabeIed SymboI in Figuie 5. Bits
with speciaI meanings in the PSW and othei iegisteis
have coiiesponding symboIic names. OeneiaI-puipose
(as opposed to caiiy-specific) instiuctions may access
the caiiy Iike any othei bit by using the mnemonic CY
in pIace of C, P0, P1, P2, and P3 aie the 8051s foui
I/O poits: secondaiy functions assigned to each of the
eight pins of P3 aie shown in Figuie 6.
Figuie 7 shows the Iast foui bit addiessabIe iegisteis.
TCON (Timei ContioI) and SCON (SeiiaI poit Con-
tioI) contioI and monitoi the coiiesponding peiiphei-
aIs, whiIe IF (Inteiiupt FnabIe) and IP (Inteiiupt Pii-
oiity) enabIe and piioiitize the five haidwaie inteiiupt
souices. Like the ieseived haidwaie iegistei addiesses,
the five bits not impIemented in IF and IP shouId not
be accessed: they can not be used as softwaie fIags.
Addressable Register Set Theie aie 20 speciaI function
iegisteis in the 8051, but the advantages of bit addiess-
ing onIy ieIate to the 11 desciibed beIow. Five poten-
tiaIIy bit-addiessabIe iegistei addiesses (0C0H, 0C8H,
0D8H, 0F8H, & 0F8H) aie being ieseived foi possibIe
futuie expansion in miciocomputeis based on the
MCS-51 aichitectuie. Reading oi wiiting non-existent
iegisteis in the 8051 seiies is pointIess, and may cause
unpiedictabIe iesuIts. Byte-wide IogicaI opeiations can
be used to manipuIate bits in aII non-bit addiessabIe
iegisteis and RAM.
6
AP-70
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Symbol Position Name and Significance
TF1 TCON7 Timer 1 overflow Flag
Set by hardware on timercoun-
ter overflow Cleared when in-
terrupt processed
TR1 TCON6 Timer 1 Run control bit
Setcleared by software to turn
timercounter onoff
TF0 TCON5 Timer 0 overflow Flag
Set by hardware on timercoun-
ter overflow Cleared when in-
terrupt processed
TR0 TCON4 Timer 0 Run control bit
Setcleared by software to turn
timercounter onoff
IE1 TCON3 Interrupt 1 Edge flag
Set by hardware when external
interrupt edge detected
Cleared when interrupt process-
ed
IT1 TCON2 Interrupt 1 Type control bit
Setcleared by software to
specify falling edgelow level
triggered external interrupts
IE0 TCON1 Interrupt 0 Edge flag
Set by hardware when external
interrupt edge detected
Cleared when interrupt process-
ed
IT0 TCON0 Interrupt 0 Type control bit
Setcleared by software to
specify falling edgelow level
triggered external interrupts
a) TCONTimerCounter ControlStatus Register
(MSB) (LSB)
SM0 SM1 SM2 REN TB8 RB8 TI RI
Symbol Position Name and Significance
SM0 SCON7 Serial port Mode control bit 0
Setcleared by software (see
note)
SM1 SCON6 Serial port Mode control bit 1
Setcleared by software (see
note)
SM2 SCON5 Serial port Mode control bit 2
Set by software to disable re-
ception of frames for which bit 8
is zero
REN SCON4 Receiver Enable control bit
Setcleared by software to en-
abledisable serial data recep-
tion
TB8 SCON3 Transmit Bit 8
Setcleared by hardware to de-
termine state of ninth data bit
transmitted in 9-bit UART mode
RB8 SCON2 Receive Bit 8
Setcleared by hardware to indi-
cate state of ninth data bit re-
ceived
TI SCON1 Transmit Interrupt flag
Set by hardware when byte
transmitted Cleared by soft-
ware after servicing
RI SCON0 Receive Interrupt flag
Set by hardware when byte re-
ceived Cleared by software af-
ter servicing
Note- the state of (SM0 SM1) selects
(00)Shift register IO
expansion
(01)8-bit UART variable
data rate
(10)9-bit UART fixed data
rate
(11)9-bit UART variable
data rate
b) SCONSerial Port ControlStatus Register
Figure 7 Peripheral Configuration Registers
7
AP-70
(MSB) (LSB)
EA ES ET1 EX1 ET1 EX0
Symbol Position Name and Significance
EA IE7 Enable All control bit
Cleared by software to disable
all interrupts independent of
the state of IE4IE0
IE6 (reserved)
IE5
ES IE4 Enable Serial port control bit
Setcleared by software to en-
abledisable interrupts from TI
or RI flags
ET1 IE3 Enable Timer 1 control bit
Setcleared by software to en-
abledisable interrupts from tim-
ercounter 1
EX1 IE2 Enable External interrupt 1 con-
trol bit Setcleared by software
to enabledisable interrupts
from INT1
ET0 IE1 Enable Timer 0 control bit
Setcleared by software to en-
abledisable interrupts from tim-
ercounter 0
EX0 IE0 Enable External interrupt 0 con-
trol bit Setcleared by software
to enabledisable interrupts
from INT0
c) IEInterrupt Enable Register
(MSB) (LSB)
PS PT1 PX1 PT0 PX0
Symbol Position Name and Significance
IP7 (reserved)
IP6 (reserved)
IP5 (reserved)
PS IP4 Serial port Priority control bit
Setcleared by software to
specify highlow priority inter-
rupts for Serial port
PT1 IP3 Timer 1 Priority control bit
Setcleared by software to
specify highlow priority inter-
rupts for timercounter 1
PX1 IP2 External interrupt 1 Priority con-
trol bit Setcleared by software
to specify highlow priority inter-
rupts for INT1
PT0 IP1 Timer 0 Priority control bit
Setcleared by software to
specify highlow priority inter-
rupts for timercounter 0
PX0 IP0 External interrupt 0 Priority con-
trol bit Setcleared by software
to specify highlow priority inter-
rupts for INT0
d) IPInterrupt Priority Control Register
Figure 7 Peripheral Configuration Registers (Continued)
The accumuIatoi and B iegisteis (A and B) aie noimaI-
Iy invoIved in byte-wide aiithmetic, but theii individuaI
bits can aIso be used as 16 geneiaI softwaie fIags. Add-
ed with the 128 fIags in RAM, this gives 144 geneiaI
puipose vaiiabIes foi bit-intensive piogiams. The pio-
giam status woid (PSW) in Figuie 5 is a coIIection of
fIags and machine status bits incIuding the caiiy fIag
itseIf. Byte opeiations acting on the PSW can theiefoie
affect the caiiy.
Instruction Set
Having Iooked at the bit vaiiabIes avaiIabIe to the Boo-
Iean Piocessoi, we wiII now Iook at the foui cIasses of
instiuctions that manipuIate these bits. It may be heIp-
fuI to iefei back to TabIe 2 whiIe ieading this section.
State Control AddiessabIe bits oi fIags may be set,
cIeaied, oi IogicaIIy compIemented in one instiuction
cycIe with the two-byte instiuctions SFTB, CLR, and
CPL. (The B affixed to SFTB distinguishes it fiom
the assembIei SFT diiective used foi symboI defini-
tion.) SFTB and CLR aie anaIogous to Ioading a bit
with a constant: 1 oi 0. SingIe byte veisions peifoim the
same thiee opeiations on the caiiy.
The MCS-51 assembIy Ianguage specifies a bit addiess
in any of thiee ways:
by a numbei oi expiession coiiesponding to the di-
iect bit addiess (0255):
8
AP-70
by the name oi addiess of the iegistei containing the
bit, the dot operator symboI (a peiiod: .), and the
bits position in the iegistei (70):
in the case of contioI and status iegisteis, by the
piedefined assembIei symboIs Iisted in the fiist coI-
umns of Figuies 57.
Bits may aIso be given usei-defined names with the as-
sembIei BIT diiective and any of the above tech-
niques. Foi exampIe, bit 5 of the PSW may be cIeaied
by any of the foui instiuctions.
U$R FL0 Bl1 F$.5 _ User $ymIol Iefinition
... ...
0LR 0I5H _ AIsolute Auuressin
0LR F$.5 _ Use of Iot 0perator
0LR F0 _ Fre-Iefineu AssemIler
_ $ymIol
0LR U$R FL0 _ User-Iefineu $ymIol
Data Transfers The two-byte MOV instiuctions can
tianspoit any addiessabIe bit to the caiiy in one cycIe,
oi copy the caiiy to the bit in two cycIes. A bit can be
moved between two aibitiaiy Iocations via the caiiy by
combining the two instiuctions. (If necessaiy, push and
pop the PSW to pieseive the pievious contents of the
caiiy.) These instiuctions can iepIace the muIti-instiuc-
tion sequence of Figuie 8, a piogiam stiuctuie appeai-
ing in contioIIei appIications whenevei fIags oi outputs
aie conditionaIIy switched on oi off.
2038304
Figure 8 Bit Transfer Instruction Operation
Logical Operations Foui instiuctions peifoim the Iogi-
caI-AND and IogicaI-OR opeiations between the caiiy
and anothei bit, and Ieave the iesuIts in the caiiy. The
instiuction mnemonics aie ANL and ORL, the absence
oi piesence of a sIash maik (/) befoie the souice
opeiand indicates whethei to use the positive-Iogic vaI-
ue oi the IogicaI compIement of the addiessed bit. (The
souice opeiand itseIf is nevei affected.)
Bit-test Instructions The conditionaI jump instiuctions
JC ieI (Jump on Caiiy) and JNC ieI (Jump on
Not Caiiy) test the state of the caiiy fIag, bianching if
it is a one oi zeio, iespectiveIy. (The Ietteis ieI de-
note ieIative code addiessing.) The thiee-byte instiuc-
tions JB bit.ieI and JNB bit.ieI (Jump on Bit and
Jump on Not Bit) test the state of any addiessabIe bit in
a simiIai mannei. A fifth instiuction combines the
Jump on Bit and CIeai opeiations. JBC bit.ieI condi-
tionaIIy bianches to the indicated addiess, then cIeais
the bit in the same two cycIe instiuction. This opeiation
is the same as the MCS-48 JTF instiuctions.
AII 8051 conditionaI jump instiuctions use piogiam
countei-ieIative addiessing, and aII execute in two cy-
cIes. The Iast instiuction byte encodes a signed dis-
pIacement ianging fiom
b
128 to
a
127. Duiing execu-
tion, the CPU adds this vaIue to the inciemented pio-
giam countei to pioduce the jump destination. Put an-
othei way, a conditionaI jump to the immediateIy foI-
Iowing instiuction wouId encode 00H in the offset byte.
A section of piogiam oi subioutine wiitten using onIy
ieIative jumps to neaiby addiesses wiII have the same
machine code independent of the codes Iocation. An
assembIed ioutine may be iepositioned anywheie in
memoiy, even ciossing memoiy page boundaiies, with-
out having to modify the piogiam oi iecompute desti-
nation addiesses. To faciIitate this fIexibiIity, theie is an
unconditionaI Shoit Jump (SJMP) which uses ieIa-
tive addiessing as weII. Since a piogiammei wouId have
quite a choie tiying to compute ieIative offset vaIues
fiom one instiuction to anothei, ASM51 automaticaIIy
computes the dispIacement needed given onIy the desti-
nation addiess oi IabeI. An eiioi message wiII aIeit the
piogiammei if the destination is out of iange.
The so-caIIed Bit Test instiuctions impIemented on
many othei miciopiocessois simpIy peifoim the Iogi-
caI-AND opeiation between a byte vaiiabIe and a con-
stant mask, and set oi cIeai a zeio fIag depending on
the iesuIt. This is essentiaIIy equivaIent to the 8051
MOV C.bit instiuction. A second instiuction is then
needed to conditionaIIy bianch based on the state of the
zeio fIag. This does not constitute abstiact bit-addiess-
ing in the MCS-51 sense. A fIag exists onIy as a fieId
9
AP-70
within a iegistei: to iefeience a bit the piogiammei
must know and specify both the encompassing iegistei
and the bits position theiein. This constiaint seveieIy
Iimits the fIexibiIity of symboIic bit addiessing and ie-
duces the machines code-efficiency and speed.
Interaction with Other Instructions The caiiy fIag is
aIso affected by the instiuctions Iisted in TabIe 3. It can
be iotated thiough the accumuIatoi, and aIteied as a
side effect of aiithmetic instiuctions. Refei to the Us-
eis ManuaI foi detaiIs on how these instiuctions opei-
ate.
Simple Instruction Combinations
By combining geneiaI puipose bit opeiations with cei-
tain addiessabIe bits, one can custom buiId seveiaI
hundied usefuI instiuctions. AII eight bits of the PSW
can be tested diiectIy with conditionaI jump instiuc-
tions to monitoi (among othei things) paiity and ovei-
fIow status. Piogiammeis can take advantage of 128
softwaie fIags to keep tiack of opeiating modes, ie-
souice usage, and so foith.
The BooIean instiuctions aie aIso the most efficient
way to contioI oi ieconfiguie peiipheiaI and I/O iegis-
teis. AII 32 I/O Iines become test pins, foi exampIe,
tested by conditionaI jump instiuctions. Any output pin
can be toggIed (compIemented) in a singIe instiuction
cycIe. Setting oi cIeaiing the Timei Run fIags (TR0 and
TR1) tuin the timei/counteis on oi off, poIIing the
same fIags eIsewheie Iets the piogiam deteimine if a
timei is iunning. The iespective oveifIow fIags (TF0
and TF1) can be tested to deteimine when the desiied
peiiod oi count has eIapsed, then cIeaied in piepaiation
foi the next iepetition. (Foi the iecoid, these bits aie aII
pait of the TCON iegistei, Figuie 7a. Thanks to sym-
boIic bit addiessing, the piogiammei onIy needs to ie-
membei the mnemonic associated with each function.
In othei woids, dont bothei memoiizing contioI woid
Iayouts.)
In the MCS-48 famiIy, instiuctions coiiesponding to
some of the above functions iequiie specific opcodes.
Ten diffeient opcodes seive to cIeai compIement the
softwaie fIags F0 and F1, enabIe/disabIe each intei-
iupt, and stait/stop the timei. In the 8051 instiuction
set, just thiee opcodes (SFTB, CLR, CPL) with a diiect
bit addiess appended peifoim the same functions. Two
test instiuctions (JB and JNB) can be combined with
bit addiesses to test the softwaie fIags, the 8048 I/O
pins T0, T1, and INT, and the eight accumuIatoi bits,
iepIacing 15 moie diffeient instiuctions.
TabIe 4a shows how 8051 piogiams impIement soft-
waie fIag and machine contioI functions associated
with speciaI opcodes in the 8048. In eveiy case the
MCS-51 soIution iequiies the same numbei of machine
cycIes, and executes 2.5 times fastei.
Table 3 Other Instructions Affecting
the Carry Flag
Mnemonic Description Byte Cyc
ADD ARn Add register to 1 1
Accumulator
ADD Adirect Add direct byte to 2 1
Accumulator
ADD A

Ri Add indirect RAM to 1 1

Accumulator
ADD Adata Add immediate data 2 1
to Accumulator
ADDC ARn Add register to 1 1
Accumulator with
Carry flag
ADDC Adirect Add direct byte to 2 1
Accumulator with
Carry flag
ADDC A

Ri Add indirect RAM to 1 1

Accumulator with
Carry flag
ADDC Adata Add immediate data 2 1
to Acc with Carry flag
SUBB ARn Subtract register from 1 1
Accumulator with
borrow
SUBB Adirect Subtract direct byte 2 1
from Acc with borrow
SUBB A

Ri Subtract indirect RAM 1 1

from Acc with borrow
SUBB Adata Subtract immediate 2 1
data from Acc with
borrow
MUL AB Multiply A B 1 4
DIV AB Divide A by B 1 4
DA A Decimal Adjust 1 1
Accumulator
RLC A Rotate Accumulator 1 1
Left through the Carry
flag
RRC A Rotate Accumulator 1 1
Right through Carry
flag
CJNE Adirectrel Compare direct byte 3 2
to Acc Jump if Not
Equal
CJNE Adatarel Compare immediate 3 2
to Acc Jump if Not
Equal
CJNE Rndatarel Compare immed to 3 2
register Jump if Not
Equal
CJNE

Ridatarel Compare immed to 3 2
indirect Jump if Not
Equal
All mnemonics copyrighted Intel Corporation 1980
10
AP-70
Table 4a Contrasting 8048 and 8051 Bit Control and Testing Instructions
8048
Bytes Cycles mSec
8x51
Bytes Cycles mSec
Instruction Instruction
Flag Control
CLR C 1 1 25 CLR C 1 1
CPL F0 1 1 25 CPL F0 2 1
Flag Testing
JNC offset 2 2 50 JNC rel 2 2
JF0 offset 2 2 50 JB F0rel 3 2
JB7 offset 2 2 50 JB ACC7rel 3 2
Peripheral Polling
JT0 offset 2 2 50 JB T0rel 3 2
JN1 offset 2 2 50 JNB INT0rel 3 2
JTF offset 2 2 50 JBC TF0rel 3 2
Machine and Peripheral Control
STRT T 1 1 25 SETB TR0 2 1
EN 1 1 1 25 SETB EX0 2 1
DIS TCNT1 1 1 25 CLR ET0 2 1
Table 4b Replacing 8048 Instruction Sequences with Single 8x51 Instructions
8048
Bytes Cycles mSec
8051
Bytes Cycles mSec
Instruction Instruction
Flag Control
Set carry
CLR C
CPL C
e
2 2 50
SETB C 1 1
Set Software Flag
CLR F0
CPL F0
e
2 2 50
SETB F0 2 1
Turn Off Output Pin
ANL P10FBH
e
2 2 50 CLR P12 2 1
Complement Output Pin
IN AP1
XRL A04H
OUTL P1A
e
4 6 150 CPL P12 2 1
Clear Flag in RAM
MOV R0FLGADR
MOV A

R0
ANL AFLGMASK
MOV

R0A
e
6 6 150 CLR USER

FLG 2 1
11
AP-70
Table 4b Replacing 8048 Instruction Sequences with Single 8x51 Instructions (Continued)
8048
Bytes Cycles mSec
8x51
Bytes Cycles mSec
Instruction Instruction
Flag Testing
Jump if Software Flag is 0
JF0 $
a
4
JMP offset
e
4 4 100 JNB F0rel 3 2
Jump if Accumulator bit is 0
CPL A
JB7 offset
CPL A
e
4 4 100 JNB ACC7rel 3 2
Peripheral Polling
Test if Input Pin is Grounded
IN AP1
CPL A
JB3 offset
e
4 5 125 JNB P13rel 3 2
Test if Interrupt Pin is High
JN1 $
a
4
JMP offset
e
4 4 100 JB INT0rel 3 2
30 BOOLEAN PROCESSOR
APPLICATIONS
So what! Then what does aII this buy you!
Qualitatively nothing. AII the same capabiIities could
be (and often have been) impIemented on othei ma-
chines using awkwaid sequences of othei basic opeia-
tions. As mentioned eaiIiei, any CPU can soIve any
piobIem given enough time.
Quantitatively the diffeiences between a soIution aI-
Iowed by the 8051 and those iequiied by pievious ai-
chitectuies aie numeious. What the 8051 FamiIy buys
you is a fastei, cIeanei, Iowei-cost soIution to micio-
contioIIei appIications.
The opcode space fieed by condensing many specific
8048 instiuctions into a few geneiaI opeiations has been
used to add new functionaIity to the MCS-51 aichitec-
tuie-both foi byte and bit opeiations. 144 softwaie
fIags iepIace the 8048s two. These fIags (and the caiiy)
may be diiectIy set, not just cIeaied and compIemented,
and aII can be tested foi eithei state, not just one. Opei-
ating mode bits pieviousIy inaccessibIe may be iead,
tested, oi saved. Situations wheie the 8051 instiuction
set piovides new capabiIities aie contiasted with 8048
instiuction sequences in TabIe 4b. Heie the 8051 speed
advantage ianges fiom 5x to 15x!
Combining BooIean and byte-wide instiuctions can
pioduce gieat syneigy. An MCS-51 based appIication
wiII piove to be:
simpIei to wiite since the aichitectuie coiieIates
moie cIoseIy with the piobIems being soIved:
easiei to debug because moie individuaI instiuctions
have no unexpected oi undesiiabIe side-effects:
moie byte efficient due to diiect bit addiessing and
piogiam countei ieIative bianching:
fastei iunning because fewei bytes of instiuction
need to be fetched and fewei conditionaI jumps aie
piocessed:
Iowei cost because of the high IeveI of system-inte-
giation within one component.
These iathei unabashed cIaims of exceIIence shaII not
go unsubstantiated. The iest of this chaptei examines
Iess tiiviaI tasks simpIified by the BooIean piocessoi.
The fiist thiee compaie the 8051 with othei micio-
piocessois, the Iast two go into 8051-based system de-
signs in much gieatei depth.
Design Example 1Bit Permutation
Fiist off, weII use the bit-tiansfei instiuctions to pei-
mute a Iengthy pattein of bits.
12
AP-70
A steadiIy incieasing numbei of data communication
pioducts use encoding methods to piotect the secuiity
of sensitive infoimation. By Iaw, inteistate financiaI
tiansactions invoIving the FedeiaI banking system must
be tiansmitted using the FedeiaI Infoimation Pio-
cessing Data Encryption Standard (DFS).
BasicaIIy, the DFS combines eight bytes of pIaintext
data (in binaiy, ASCII, oi any othei foimat) with a 56-
bit key, pioducing a 64-bit enciypted vaIue foi tians-
mission. At the ieceiving end the same aIgoiithm is
appIied to the incoming data using the same key, iepio-
ducing the oiiginaI eight byte message. The aIgoiithm
used foi these peimutations is fixed, diffeient usei-de-
fined keys ensuie data piivacy.
It is not the puipose of this note to desciibe the DFS in
any detaiI. Suffice it to say that enciyption/deciyption
is a Iong, iteiative piocess consisting of iotations, excIu-
sive -OR opeiations, function tabIe Iook-ups, and an
extensive (and quite bizaiie) sequence of bit peimuta-
tion, packing, and unpacking steps. (Foi fuithei detaiIs
iefei to the June 21, 1979 issue of Electronics maga-
zine.) The bit manipuIation steps aie incIuded, it is iu-
moied, to impede a geneiaI puipose digitaI supeicom-
putei tiying to bieak the code. Any aIgoiithm impIe-
menting the DFS with pievious geneiation micio-
piocessois wouId spend viituaIIy aII of its time diddIing
bits.
The bit manipuIation peifoimed is typified by the Key
ScheduIe CaIcuIation iepiesented in Figuie 9. This step
is iepeated 16 times foi each key used in the couise of a
tiansmission. In essence, a seven-byte, 56-bit Shifted
Key Buffei is tiansfoimed into an eight-byte, Peimu-
tation Buffei without aIteiing the shifted Key. The
aiiows in Figuie 9 indicate a few of the tiansIation
steps. OnIy six bits of each byte of the Peimutation
Buffei aie used, the two high-oidei bits of each byte aie
cIeaied. This means onIy 48 of the 56 Shifted Key Buff-
ei bits aie used in any one iteiation.
Diffeient miciopiocessoi aichitectuies wouId best im-
pIement this type of peimutation in diffeient ways.
Most appioaches wouId shaie the steps of Figuie 10a:
InitiaIize the Peimutation Buffei to defauIt state
(ones oi zeioes):
IsoIate the state of a bit of a byte fiom the Key
Buffei. Depending on the CPU, this might be ac-
compIished by iotating a woid of the Key Buffei
thiough a caiiy fIag oi testing a bit in memoiy oi an
accumuIatoi against a mask byte:
Peifoim a conditionaI jump based on the caiiy oi
zeio fIag if the Peimutation Buffei defauIt state is
coiiect:
Otheiwise ieveise the coiiesponding bit in the pei-
mutation buffei with IogicaI opeiations and mask
bytes.
Fach step above may iequiie seveiaI instiuctions. The
Iast thiee steps must be iepeated foi aII 48 bits. Most
miciopiocessois wouId spend 300 to 3,000 miciosec-
onds on each of the 16 iteiations.
Notice, though, that this fIow chait Iooks a Iot Iike
Figuie 8. The BooIean Piocessoi can peimute bits by
simpIy moving them fiom the souice to the caiiy to the
destination-a totaI of two instiuctions taking foui
bytes and thiee micioseconds pei bit. Assume the Shift-
ed Key Buffei and Peimutation Buffei both ieside in
bit-addiessabIe RAM, with the bits of the foimei as-
signed symboIic names SKB
-
1, SKB
-
2, . . . SKB
-
56, and that the bytes of the Iattei aie named PB
-
1,
. . . PB
-
8. Then woiking fiom Figuie 9, the softwaie
foi the peimutation aIgoiithm wouId be that of Fxam-
pIe 1a. The totaI ioutine Iength wouId be 192 bytes,
iequiiing 144 micioseconds.
Permuted and Shifted 56-Bit Key Buffer
2038305
48-Bit Key K
I
Figure 9 DES Key Schedule Transformation
13
AP-70
2038306
Figure 10a Flowchart for Key Permutation Attempted with a Byte Processor
14
AP-70
2038307
Figure 10b DES Key Permutation with Boolean Processor
15
AP-70
The aIgoiithm of Figuie 10b is just sIightIy moie effi-
cient in this time-ciiticaI appIication and iIIustiates the
syneigy of an integiated byte and bit piocessoi. The
bits needed foi each byte of the Peimutation Buffei aie
assimiIated by Ioading each bit into the caiiy (1 ms.)
and shifting it into the accumuIatoi (1 ms.). Fach byte
is stoied in RAM when compIeted. Foity-eight bits
thus need a totaI of 112 instiuctions, some of which aie
Iisted in FxampIe 1b.
Woist-case execution time wouId be 112 micioseconds,
since each instiuction takes a singIe cycIe. Routine
Iength wouId aIso deciease, to 168 bytes. (ActuaIIy, in
the context of the compIete enciyption aIgoiithm, each
peimuted byte wouId be piocessed as soon as it is as-
simiIated-saving memoiy and cutting execution time
by anothei 8 ms.)
To date, most banking teiminaIs and othei systems us-
ing the DFS have needed speciaI boaids oi peiipheiaI
contioIIei chips just foi the enciyption/deciyption pio-
cess, and stiII moie haidwaie to foim a seiiaI bit stieam
foi tiansmission (Figuie 11a). An 8051 soIution couId
pack most of the entiie system onto the one chip (Fig-
uie 11b). The whoIe DFS aIgoiithm wouId iequiie Iess
than one-fouith of the on-chip piogiam memoiy, with
the iemaining bytes fiee foi opeiating the banking tei-
minaI (oi whatevei) itseIf.
Moieovei, since tiansmission and ieception of data is
peifoimed thiough the on-boaid UART, the unen-
ciypted data (pIaintext) nevei even exists outside the
miciocomputei! NatuiaIIy, this wouId affoid a high de-
giee of secuiity fiom data inteiception.
FxampIe 1. DFS Key Peimutation Softwaie.
a.) Biute Foice technique
N07 0,$KB l
N07 FB l.l,0
N07 0,$KB 2
N07 FB 4.0,0
N07 0,$KB
N07 FB 2.5,0
N07 0,$KB 4
N07 FB l.0,0
... .....
... .....
N07 0,$KB 55
N07 FB 5.0,0
N07 0,$KB 58
N07 FB 7.2,0
b.) Using AccumuIatoi to CoIIect Bits
0LR A
N07 0,$KB l4
RL0 A
N07 0,$KB l7
RL0 A
N07 0,$KB ll
RL0 A
N07 0,$KB 24
RL0 A
N07 0,$KB l
RL0 A
N07 0,$KB 5
RL0 A
N07 FB l,A
... .....
... .....
N07 0,$KB 29
RL0 A
N07 0,$KB 2
RL0 A
N07 FB 3,A
16
AP-70
2038308
a) Using Multi-Chip Processor Technology
2038309
b) Using One Single-Chip Microcomputer
Figure 11 Secure Banking Terminal Block Diagram
Design Example 2Software
Serial IO
An exeicise often imposed on beginning miciocomput-
ei students is to wiite a piogiam simuIating a UART.
Though doing this with the 8051 FamiIy may appeai to
be a moot point (given that the haidwaie foi a fuII
UART is on-chip), it is stiII instiuctive to see how it
wouId be done, and maintains a pioduct Iine tiadition.
As it tuins out, the 8051 miciocomputeis can ieceive oi
tiansmit seiiaI data via softwaie veiy efficientIy using
the BooIean instiuction set. Since any I/O pin may be a
seiiaI input oi output, seveiaI seiiaI Iinks couId be
maintained at once.
Figuies 12a and 12b show aIgoiithms foi ieceiving oi
tiansmitting a byte of data. (Anothei section of pio-
giam wouId invoke this aIgoiithm eight times, synchio-
nizing it with a stait bit, cIock signaI, softwaie deIay, oi
timei inteiiupt.) Data is ieceived by testing an input
pin, setting the caiiy to the same state, shifting the
caiiy into a data buffei, and saving the paitiaI fiame in
inteinaI RAM. Data is tiansmitted by shifting an out-
put buffei thiough the caiiy, and geneiating each bit
on an output pin.
A side-by-side compaiison of the softwaie foi this com-
mon bit-banging appIication with thiee diffeient mi-
ciopiocessoi aichitectuies is shown in TabIe 5a and 5b.
The 8051 soIution is moie efficient than the otheis on
eveiy count!
17
AP-70
20383010
a) Reception
20383011
b) Transmission
Figure 12 Serial IO Algorithms
18
AP-70
Table 5 Serial IO Programs for Various Microprocessors
20383030
Design Example 3Combinatorial
Logic Equations
Next weII Iook at some simpIe uses foi bit-test instiuc-
tions and IogicaI opeiations. (This exampIe is aIso pie-
sented in AppIication Note AP-69.)
ViituaIIy aII haidwaie designeis have soIved compIex
functions using combinatoiiaI Iogic. WhiIe the haid-
waie invoIved may vaiy fiom ieIay Iogic, vacuum
tubes, oi TTL oi to moie esoteiic technoIogies Iike fIu-
idics, in each case the goaI is the same: to soIve a piob-
Iem iepiesented by a IogicaI function of seveiaI BooIean
vaiiabIes.
Figuie 13 shows TTL and ieIay Iogic diagiams foi a
function of the six vaiiabIes U thiough Z. Fach is a
soIution of the equation.
Q e (U (V a W)) a (X Y) a Z
Fquations of this soit might be ieduced using Kai-
naugh Maps oi aIgebiaic techniques, but that is not the
puipose of this exampIe. As the Iogic compIexity in-
cieases, so does the difficuIty of the ieduction piocess.
Fven a minoi change to the function equations as the
design evoIves wouId iequiie tedious ie-ieduction fiom
sciatch.
19
AP-70
20383012
Q e (U (V a W)) a (X Y) a Z
a) Using TTL
20383013
b) Using Relay Logic
Figure 13 Hardware Implementations of Boolean Functions
Foi the sake of compaiison we wiII impIement this
function thiee ways, iestiicting the softwaie to thiee
piopei subsets of the MCS-51 instiuction set. We wiII
aIso assume that U and V aie input pins fiom diffeient
input poits, W and X aie status bits foi two peiipheiaI
contioIIeis, and Y and Z aie softwaie fIags set up eaiIi-
ei in the piogiam. The end iesuIt must be wiitten
to an output pin on some thiid poit. The fiist two im-
pIementations foIIow the fIow-chait shown in Figuie
14. Piogiam fIow wouId embaik on a ioute down a
test-and-bianch tiee and Ieaves eithei the Tiue oi
Not Tiue exit ASAP-as soon as the piopei iesuIt
has been deteimined. These exits then iewiite the out-
put poit with the iesuIt bit iespectiveIy one oi zeio.
20
AP-70
20383014
Figure 14 Flow Chart for
Tree-Branching Algorithm
Othei digitaI computeis must soIve equations of this
type with standaid woid-wide IogicaI instiuctions and
conditionaI jumps. So foi the fiist impIementation, we
wont use any geneiaIized bit-addiessing instiuctions.
As we shaII soon see, being constiained to such an in-
stiuction subset pioduces somewhat sIoppy softwaie
soIutions. MCS-51 mnemonics aie used in FxampIe 2a:
othei machines might fuithei cIoud the situation by
iequiiing opeiation-specific mnemonics Iike INPUT,
OUTPUT, LOAD, STORF, etc., instead of the MOV
mnemonic used foi aII vaiiabIe tiansfeis in the 8051
instiuction set.
The code which iesuIts is cumbeisome and eiioi pione.
It wouId be difficuIt to piove whethei the softwaie
woiked foi aII input combinations in piogiams of this
soit. Fuitheimoie, execution time wiII vaiy wideIy with
input data.
Thanks to the diiect bit-test opeiations, a singIe in-
stiuction can iepIace each move mask conditionaI jump
sequence in FxampIe 2a, but the aIgoiithm wouId be
equaIIy convoIuted (see FxampIe 2b). To Iessen the
confusion a bit each input vaiiabIe is assigned a sym-
boIic name.
A moie eIegant and efficient impIementation (FxampIe
2c) stiings togethei the BooIean ANL and ORL func-
tions to geneiate the output function with stiaight-Iine
code. When finished, the caiiy fIag contains the iesuIt,
which is simpIy copied out to the destination pin. No
fIow chait is needed-code can be wiitten diiectIy fiom
the Iogic diagiams in Figuie 14. The iesuIt is simpIicity
itseIf: fast, fIexibIe, ieIiabIe, easy to design, and easy to
debug.
An 8051 piogiam can simuIate an N-input AND oi
OR gate with at most N
a
1 Iines of souice piogiam-
one foi each input and one Iine to stoie the iesuIts. To
simuIate NAND and NOR gates, compIement the cai-
iy aftei computing the function. When some inputs to
the gate have inveision bubbIes, peifoim the ANL oi
ORL opeiation on inveited opeiands. When the fiist
input is inveited, eithei Ioad the opeiand into the caiiy
and then compIement it, oi use DeMoigans Theoiem
to conveit the gate to a diffeient foim.
FxampIe 2. Softwaie SoIutions to Logic Function of
Figuie 13.
a.) Using onIy byte-wide IogicaI instiuctions
:BFUR0l $0L7E RARI0N L00l0
_ FUR01l0R 0F 8 7ARlABLE$
_ BY L0AIlR0 ARI NA$KlR0
_ 1HE AFFR0FRlA1E Bl1$ lR
_ 1HE A00UNULA10R. 1HER
_ EXE0U1lR0 00RIl1l0RAL
_ 5UNF$ BA$EI 0R 7ER0
_ 00RIl1l0R. |AFFR0A0H U$EI
_ BY BY1E-0RlER1EI
_ AR0Hl1E01URE$., BY1E ARI
_ NA$K 7ALUE$ 00RRE$F0RI 10
_ RE$FE01l7E BY1E AIIRE$$
_ ARI Bl1 F0$l1l0R$.
_
0U1BUF IA1A 22H
_0U1FU1 FlR $1A1E NAF
_
21
AP-70
1E$17: N07 A,F2
ARL A,00000l00B
5R7 1E$1U
N07 A,100R
ARL A,00l00000B
57 1E$1X
1E$1U: N07 A,Fl
ARL A,000000l0B
5R7 $E1@
1E$1X: N07 A,100R
ARL A,0000l000B
57 1E$17
N07 A,20H
ARL A,0000000lB
57 $E1@
1E$17: N07 A,2lH
ARL A,000000l0B
57 $E1@
0LR@: N07 A,0U1BUF
ARL A,llll0lllB
5NF 0U1@
$E1@: N07 A,0U1BUF
0RL A,0000l000B
0U1@: N07 0U1BUF,A
N07 F,A
b.) Using onIy bit-test instiuctions
:BFUR02 $0L7E A RARI0N L00l0
_ FUR01l0R 0F 8 7ARlABLE$
_ BY IlRE01LY F0LLlR0 EA0H
_ Bl1. |AFFR0A0H U$lR0
_ N0$-5l URl@UE Bl1-1E$1
_ lR$1RU01l0R 0AFABlLl1Y.,
_ $YNB0L$ U$EI lR L00l0
_ IlA0RAN A$$l0REI 10
_ 00RRE$F0RIlR0 3x5l Bl1
_ AIIRE$$E$.
_
U Bl1 Fl.l
7 Bl1 F2.2
Bl1 1F0
X Bl1 lEl
Y Bl1 20H.0
7 Bl1 2lH.l
@ Bl1 F.
_ ... ....
1E$1 7: 5B 7,1E$1 U
5RB ,1E$1 X
1E$1 U: 5B U,$E1 @
1E$1 X: 5RB X,1E$1 7
5RB Y,$E1 @
1E$1 7: 5RB 7,$E1 @
0LR @: 0LR @
5NF RX11$1
$E1 @: $E1B @
RX11$1:|00R1lRUA1l0R 0F
:FR00RAN,
c.) Using IogicaI opeiations on BooIean vaiiabIes
:FUR0 $0L7E A RARI0N L00l0
_ FUR01l0R 0F 8 7ARlABLE$
_ U$lR0 $1RAl0H1 LlRE
_ L00l0AL lR$1RU01l0R$ 0R
_ N0$-5l B00LEAR 7ARlABLE$.
_
N07 0,7
0RL 0, _0U1FU1 0F 0R 0A1E
ARL 0,U _0U1FU1 0F 10F ARI 0A1E
N07 F0,0 _$A7E lR1ERNEIlA1E $1A1E
N07 0,X
ARL 0,Y _0U1FU1 0F B0110N ARI 0A1E
0RL 0,F0 _lR0LUIE 7ALUE $A7EI AB07E
0RL 0,7 _lR0LUIE LA$1 lRFU1
_7ARlABLE
N07 @,0 _0U1FU1 00NFU1EI RE$UL1
22
AP-70
An uppei-Iimit can be pIaced on the compIexity of soft-
waie to simuIate a Iaige numbei of gates by summing
the totaI numbei of inputs and outputs. The actual totaI
shouId be somewhat shoitei, since caIcuIations can be
chained, as shown. The output of one gate is often
the fiist input to anothei, bypassing the inteimediate
vaiiabIe to eIiminate two Iines of souice.
Design Example 4Automotive
Dashboard Functions
Now Iets appIy these techniques to designing the soft-
waie foi a compIete contioIIei system. This appIication
is patteined aftei a famiIiai ieaI-woiId appIication
which isnt neaiIy as tiiviaI as it might fiist appeai:
automobiIe tuin signaIs.
Imagine the thiee position tuin Ievei on the steeiing
coIumn as a singIe-poIe, tiipIe-thiow toggIe switch. In
its centiaI position aII contacts aie open. In the up oi
down positions contacts cIose causing coiiesponding
Iights in the ieai of the cai to bIink. So fai veiy simpIe.
Two moie tuin signaIs bIink in the fiont of the cai, and
two otheis in the dashboaid. AII six buIbs fIash when
an emeigency switch is cIosed. A theimo-mechanicaI
ieIay (accessibIe undei the dashboaid in case it weais
out) causes the bIinking.
AppIying the biake pedaI tuins the taiI Iight fiIaments
on constantIy . . . unIess a tuin is in piogiess, in which
case the bIinking taiI Iight is not affected. (Of couise,
the fiont tuin signaIs and dashboaid indicatois aie not
affected by the biake pedaI.) TabIe 6 summaiizes these
opeiating modes.
Table 6 Truth Table for Turn-Signal Operation
Input Signals Output Signals
Brake Emerg
Left Right Left Right
Left Right
Switch Switch
Turn Turn Front Front
Rear Rear
Switch Switch Dash Dash
0 0 0 0 Off Off Off Off
0 0 0 1 Off Blink Off Blink
0 0 1 0 Blink Off Blink Off
0 1 0 0 Blink Blink Blink Blink
0 1 0 1 Blink Blink Blink Blink
0 1 1 0 Blink Blink Blink Blink
1 0 0 0 Off Off On On
1 0 0 1 Off Blink On Blink
1 0 1 0 Blink Off Blink On
1 1 0 0 Blink Blink On On
1 1 0 1 Blink Blink On Blink
1 1 1 0 Blink Blink Blink On
23
AP-70
But weie not done yet. Fach of the exteiioi tuin signaI
(but not the dashboaid) buIbs has a second, somewhat
dimmei fiIament foi the paiking Iights. Figuie 15
shows TTL ciicuitiy which couId contioI aII six buIbs.
The signaIs IabeIed High Fieq. and Low Fieq. iep-
iesent two squaie-wave inputs. BasicaIIy, when one of
the tuin switches is cIosed oi the emeigency switch is
activated the Iow fiequency signaI (about 1 Hz) is gated
thiough to the appiopiiate dashboaid indicatoi(s) and
tuin signaI(s). The ieai signaIs aie aIso activated when
the biake pedaI is depiessed piovided a tuin is not be-
ing made in the same diiection. When the paiking Iight
switch is cIosed the highei fiequency osciIIatoi is gated
to each fiont and ieai tuin signaI, sustaining a Iow-in-
tensity backgiound IeveI. (This is to eIiminate the need
foi additionaI paiking Iight fiIaments.)
In most cais, the switching Iogic to geneiate these func-
tions iequiies a numbei of muItipIe-thiow contacts. As
many as 18 conductois thiead the steeiing coIumn of
some automobiIes soIeIy foi tuin-signaI and emeigency
bIinkei functions. (The authoi discoveied this iecentIy
to his astonishment and dismay when iepIacing the
whoIe assembIy because of one buined contact.)
A muItipIe-conductoi wiiing hainess iuns to each coi-
nei of the cai, behind the dash, up the steeiing coIumn,
and down to the bIinkei ieIay beIow. Connectois at
each teimination foi each fiIament Iead to extia cost
and Iaboi duiing constiuction, Iowei ieIiabiIity and
safety, and moie costIy iepaiis. And consideiing the
systems piesent compIexity, incieasing its ieIiabiIity oi
detecting faiIuies wouId be quite difficuIt.
Theie aie two ieasons foi going into such painfuI detaiI
desciibing this exampIe. Fiist, to show that the messiest
pait of many system designs is deteimining what the
contioIIei shouId do. Wiiting the softwaie to soIve
these functions wiII be compaiativeIy easy. SecondIy, to
show the many potentiaI faiIuie points in the system.
Latei weII see how the peiipheiaI functions and inteIIi-
gence buiIt into a miciocomputei (with a IittIe cieativi-
ty) can gieatIy ieduce exteinaI inteiconnections and
mechanicaI pait count.
The Single-Chip Solution
The ciicuit shown in Figuie 16 indicates five input pins
to the five input vaiiabIes-Ieft-tuin seIect, iight-tuin
seIect, biake pedaI down, emeigency switch on, and
paiking Iights on. Six output pins tuin on the fiont,
ieai, and dashboaid indicatois foi each side. The mi-
ciocomputei impIements aII IogicaI functions thiough
softwaie, which peiiodicaIIy updates the output signaIs
as time eIapses and input conditions change.
20383015
Figure 15 TTL Logic Implementation of Automotive Turn Signals
24
AP-70
20383016
Figure 16 Microcomputer Turn-Signal Connections
Design FxampIe 3 demonstiated that symboIic ad-
diessing with usei-defined bit names makes code and
documentation easiei to wiite and maintain. Accoid-
ingIy, weII assign these I/O pins names foi use
thioughout the piogiam. (The foimat of this exampIe
wiII diffei somewhat fiom the otheis. Segments of the
oveiaII piogiam wiII be piesented in sequence as each is
desciibed.)
_
_ lRFU1 FlR IE0LARA1l0R$:
_|ALL lRFU1$ ARE F0$l1l7E-1RUE L00l0,
_
BRAKE Bl1 Fl.0 _BRAKE FEIAL
_IEFRE$$EI
ENER0 Bl1 Fl.l _ENER0ER0Y BLlRKER
_A01l7A1EI
FARK Bl1 Fl.2 _FARKlR0 Ll0H1$ 0R
l 1URR Bl1 Fl. _1URR LE7ER I0R
R 1URR Bl1 Fl.4 _1URR LE7ER UF
_
_ 0U1FU1 FlR IE0LARA1l0R$:
_
l FRR1 Bl1 Fl.5 _FR0R1 LEF1-1URR
_lRIl0A10R
R FRR1 Bl1 Fl.8 _FR0R1 Rl0H1-1URR
_lRIl0A10R
l IA$H Bl1 Fl.7 _IA$HB0ARI LEF1-1URR
_lRIl0A10R
R IA$H Bl1 F2.0 _IA$HB0ARI Rl0H1-
_1URR lRIl0A10R
l REAR Bl1 F2.l _REAR LEF1-1URR
_lRIl0A10R
R REAR Bl1 F2.2 _REAR Rl0H1-1URR
_lRIl0A10R
_
Anothei key advantage of symboIic addiessing wiII ap-
peai fuithei on in the design cycIe. The Iocations of
cabIe connectois, signaI conditioning ciicuitiy, voItage
ieguIatois, heat sinks, and the Iike aII affect P.C. boaid
Iayout. Its quite IikeIy that the somewhat aibitiaiy pin
assignment defined eaiIy in the softwaie design cycIe
wiII piove to be Iess than optimum, ieaiianging the I/O
pin assignment couId weII aIIow a moie compact mod-
uIe, oi eIiminate costIy jumpeis on a singIe-sided boaid.
(These consideiations appIy especiaIIy to automotive
and othei cost-sensitive appIications needing singIe-
chip contioIIeis.) Since othei aichitectuies mask bytes
oi use cIevei aIgoiithms to isoIate bits by iotating
them into the caiiy, ie-iouting an input signaI (fiom bit
1 of poit 1, foi exampIe, to bit 4 of poit 3) couId iequiie
extensive modifications thioughout the softwaie.
The BooIean Piocessois diiect bit addiessing makes
such changes absoIuteIy tiiviaI. The numbei of the poit
containing the pin is iiieIevent, and masks and compIex
25
AP-70
piogiam stiuctuies aie not needed. OnIy the initiaI
BooIean vaiiabIe decIaiations need to be changed,
ASM51 automaticaIIy adjusts aII addiesses and symboI-
ic iefeiences to the ieassigned vaiiabIes. The usei is
assuied that no additionaI debugging oi softwaie veiifi-
cation wiII be iequiied.
_ ... .....
_lR1ERRUF1 RA1E $UBIl7lIER
$UB Il7 IA1A 20H
_Hl0H-FRE@UER0Y 0$0lLLA10R Bl1
Hl FRE@ Bl1 $UB Il7,0
_L0-FRE@UER0Y 0$0lLLA10R Bl1
L0 FRE@ Bl1 $UB Il7,7
_ ...
0R0 0000H
5NF lRl1
_ ... .....
0R0 l00H
_FU1 1lNER 0 lR N0IE l
lRl1_ N07 1N0I,0000000lB
_lRl1lALl7E 1lNER RE0l$1ER$
N07 1L0,0
N07 1H0,1l8
_$UBIl7lIE lR1ERRUF1 RA1E BY 244
N07 $UB Il7,244
_ERABLE 1lNER lR1ERRUF1$
$E1B E10
_0L0BALLY ERABLE ALL lR1ERRUF1$
$E1B EA
_$1AR1 1lNER
$E1B 1R0
_
_|00R1lRUE l1H BA0K0R0URI FR00RAN,
_
_FU1 1lNER 0 lR N0IE l
_lRl1lALl7E 1lNER RE0l$1ER$
_$UBIl7lIE lR1ERRUF1 RA1E BY 244
_ERABLE 1lNER lR1ERRUF1$
_0L0BALLY ERABLE ALL lR1ERRUF1$
_$1AR1 1lNER
Timei 0 (one of the two on-chip timei counteis) ie-
pIaces the theimo-mechanicaI bIinkei ieIay in the dash-
boaid contioIIei. Duiing system initiaIization it is con-
figuied as a timei in mode 1 by setting the Ieast signifi-
cant bit of the timei mode iegistei (TMOD). In this
configuiation the Iow-oidei byte (TL0) is inciemented
eveiy machine cycIe, oveifIowing and inciementing the
high-oidei byte (TH0) eveiy 256 ms. Timei inteiiupt 0
is enabIed so that a haidwaie inteiiupt wiII occui each
time TH0 oveifIows.
An eight-bit vaiiabIe in the bit-addiessabIe RAM aiiay
wiII be needed to fuithei subdivide the inteiiupts via
softwaie. The Iowest-oidei bit of this countei toggIes
veiy fast to moduIate the paiking Iights: bit 7 wiII be
tuned to appioximateIy 1 Hz foi the tuin- and emei-
gency-indicatoi bIinking iate.
Loading TH0 with -16 wiII cause an inteiiupt aftei
4.096 ms. The inteiiupt seivice ioutine ieIoads the
high-oidei byte of timei 0 foi the next inteivaI, saves
the CPU iegisteis IikeIy to be affected on the stack, and
then deciements SUB
-
DIV. Loading SUB
-
DIV.
with 244 initiaIIy and each time it deciements to zeio
wiII pioduce a 0.999 second peiiod foi the highest-oi-
dei bit.
0R0 000BH _1lNER 0 $ER7l0E 7E010R
N07 1H0,-l8
FU$H F$
FU$H A00
FU$H B
I5R7 $UB Il7,10$ER7
N07 $UB Il7,244
The code to sampIe inputs, peifoim caIcuIations, and
update outputs-the ieaI meat of the signaI contioI-
Iei aIgoiithm-may be peifoimed eithei as pait of the
inteiiupt seivice ioutine oi as pait of a backgiound
piogiam Ioop. The onIy concein is that it must be exe-
cuted at Ieast seiveiaI dozen times pei second to pie-
vent paiking Iight fIickeiing. We wiII assume the foi-
mei case, and inseit the code into the timei 0 seivice
ioutine.
Fiist, notice fiom the Iogic diagiam (Figuie 15) that
the subteim (PARK H
-
FRFQ), asseited when the
paiking Iights aie to be on dimIy, figuies into foui of
the six output functions. AccoidingIy, we wiII fiist
compute that teim and save it in a tempoiaiy Iocation
named DIM. The PSW contains two geneiaI puipose
fIags: F0, which coiiesponds to the 8048 fIag of the
same name, and PSW.1. Since the PSW has been saved
and wiII be iestoied to its pievious state aftei seivicing
the inteiiupt, we can use eithei bit foi tempoiaiy stoi-
age.
IlN Bl1 F$.l _IE0LARE 1ENF
_$10RA0E FLA0
_ ... .....
N07 0,FARK _0A1E FARKlR0
_Ll0H1 $l10H
ARL Hl FRE@ _l1H Hl0H
_FRE@UER0Y
_$l0RAL
N07 IlN,0 _ARI $A7E lR
_1ENF. 7ARlABLE
This simpIe thiee-Iine section of code iIIustiates a ie-
maikabIe point. The softwaie indicates in veiy abstiact
teims exactIy what function is being peifoimed, inde-
26
AP-70
pendent of the haidwaie configuiation. The fact that
these thiee bits incIude an input pin, a bit within a
piogiam vaiiabIe, and a softwaie fIag in the PSW is
totaIIy invisibIe to the piogiammei.
Now geneiate and output the dashboaid Ieft tuin sig-
naI.
_
N07 0,L 1URR _$E1 0ARRY lF
_1URR
0RL 0,ENER0 _0R ENER0ER0Y
_$ELE01EI
ARL 0,L0 FRE@ _0A1E lR l H7
_$l0RAL
N07 l IA$H,0 _ARI 0U1FU1 10
_IA$HB0ARI
To geneiate the Ieft fiont tuin signaI we onIy need to
add the paiking Iight function in F0. But notice that the
function in the caiiy wiII aIso be needed foi the ieai
signaI. We can save effoit Iatei by saving its cuiient
state in F0.
_
N07 F0,0 _$A7E FUR01l0R
_$0 FAR
0RL 0,IlN _AII lR FARKlR0
_Ll0H1 FUR01l0R
N07 L FRR1,0 _ARI 0U1FU1 10
_1URR $l0RAL
FinaIIy, the ieai Ieft tuin signaI shouId aIso be on when
the biake pedaI is depiessed, piovided a Ieft tuin is not
in piogiess.
N07 0,BRAKE _0A1E BRAKE
_FEIAL $l10H
ARL 0,L 1URR _l1H 1URR
_LE7ER
0RL 0,F0 _lR0LUIE 1ENF.
_7ARlABLE FR0N IA$H
0RL 0,IlN _ARI FARKlR0
_Ll0H1 FUR01l0R
N07 L REAR,0 _ARI 0U1FU1 10
_1URR $l0RAL
Now we have to go thiough a simiIai sequence foi the
iight-hand equivaIents to aII the Ieft-tuin Iights. This
aIso gives us a chance to see how the code segments
above Iook when combined.
N07 0.R 1URR _$E1 0ARRY H-
_1URR
0RL 0.ENER0 _0R ENER0ER0Y
_$ELE01EI
ARL 0,L0 FRE@ _lF $0. 0A1E lR l
_H7 $l0RAL
N07 R IA$H.0 _ARI 0U1FU1 10
_IA$HB0ARI
N07 F0.0 _$A7E FUR01l0R
_$0 FAR
0RL 0.IlN _AII lR FARKlR0
_Ll0H1 FUR01l0R
N07 R FRR1.0 _ARI 0U1FU1 10
_1URR $l0RAL
N07 0.BRAKE _0A1E BRAKE
_FEIAL $l10H
ARL 0. R 1URR _l1H 1URR
_LE7ER
0RL 0.F0 _lR0LUIE 1ENF.
_7ARlABLE FR0N
_IA$H
0RL 0.IlN _ARI FARKlR0
_Ll0H1 FUR01l0R
N07 R REAR.0 _ARI 0U1FU1 10
_1URR $l0RAL
(The peiceptive ieadei may notice that simpIy ieai-
ianging the steps couId eIiminate one instiuction fiom
each sequence.)
Now that aII six buIbs aie in the piopei states, we can
ietuin fiom the inteiiupt ioutine, and the piogiam is
finished. This code essentiaIIy needs to ieveise the
status saving steps at the beginning of the inteiiupt.
Table 7 Non-Trivial Duty Cycles
Sub

Div Bits Duty Cycles

7 6 5 4 3 2 1 0 125% 250% 375% 500% 625% 750% 875%
X X X X X 0 0 0 Off Off Off Off Off Off Off
X X X X X 0 0 1 Off Off Off Off Off Off On
X X X X X 0 1 0 Off Off Off Off Off On On
X X X X X 0 1 1 Off Off Off Off On On On
X X X X X 1 0 0 Off Off Off On On On On
X X X X X 1 0 1 Off Off On On On On On
X X X X X 1 1 0 Off On On On On On On
X X X X X 1 1 1 On On On On On On On
27
AP-70
F0F B _RE$10RE 0FU
_RE0l$1ER$.
F0F A00
F0F F$
RE1l
Program Refinements The Iuminescence of an incan-
descent Iight buIb fiIament is geneiaIIy non-Iineai: the
50% duty cycIe of HI
-
FRFQ may not pioduce the
desiied intensity. If the appIication iequiies, duty cy-
cIes of 25%, 75%, etc. aie easiIy achieved by ANDing
and ORing in additionaI Iow-oidei bits of SUB
-
DIV.
Foi exampIe, 30 H/ signaIs of seven diffeient duty cy-
cIes couId be pioduced by consideiing bits 20 as
shown in TabIe 7. The onIy softwaie change iequiied
wouId be to the code which sets-up vaiiabIe DIM,
N07 0,$UB Il7.l_$1AR1 l1H 50
_FER0ER1
ARL 0,$UB Il7.0_NA$K I0R 10 25
_FER0ER1
0RL 0,$UB Il7.2_ARI BUlLI BA0K 10
_82 FER0ER1
N07 IlN,0 _IU1Y 0Y0LE F0R
_FARKlR0 Ll0H1$.
Inteiconnections inciease cost and deciease ieIiabiIity.
The simpIe buffeied pin-pei-function ciicuit in Figuie
16 is insufficient when many outputs iequiie highei-
than-TTL diive IeveIs. A Iowei-cost soIution uses the
8051 seiiaI poit in the shift-iegistei mode to augment
I/O. In mode 0, wiiting a byte to the seiiaI poit data
buffei (SBUF) causes the data to be output sequentiaIIy
thiough the RXD pin whiIe a buist of eight cIock
puIses is geneiated on the TXD pin. A shift iegistei
connected to these pins (Figuie 17) wiII Ioad the data
byte as it is shifted out. A numbei of speciaI peiipheiaI
diivei ciicuits combining shift-iegistei inputs with high
diive IeveI outputs have been intioduced iecentIy.
Cascading muItipIe shift iegisteis end-to-end wiII ex-
pand the numbei of outputs even fuithei. The data iate
in the I/O expansion mode is one megabaud, oi 8 ms.
pei byte. This is the mode which the seiiaI poit defauIts
to foIIowing a ieset, so no initiaIization is iequiied.
The softwaie foi this technique uses the B iegistei as a
map coiiesponding to the diffeient output functions.
The piogiam manipuIates these bits instead of the out-
put pins. Aftei aII functions have been caIcuIated the B
iegistei is shifted by the seiiaI poit to the shift-iegistei
diivei. (WhiIe some outputs may gIitch as data is shift-
ed thiough them, at 1 Megabaud most peopIe wouIdnt
notice. Some shift iegisteis piovide an enabIe bit to
hoId the output states whiIe new data is being shifted
in.)
This is wheie the eaiIiei decision to addiess bits sym-
boIicaIIy thioughout the piogiam is going to pay off.
This majoi I/O iestiuctuiing is neaiIy as simpIe to im-
pIement as ieaiianging the input pins. Again, onIy the
bit decIaiations need to be changed.
l FRR1 Bl1 B.0 _FR0R1 LEF1-1URR
_lRIl0A10R
R FRR1 Bl1 B.l _FR0R1 Rl0H1-1URR
_lRIl0A10R
l IA$H Bl1 B.2 _IA$HB0ARI LEF1-1URR
_lRIl0A10R
R IA$H Bl1 B. _IA$HB0ARI Rl0H1-1URR
_lRIl0A10R
l REAR Bl1 B.4 _REAR LEF1-1URR
_lRIl0A10R
R REAR Bl1 B.5 _REAR Rl0H1-1URR
_lRIl0A10R
20383017
Figure 17 Output Expansion Using Serial Port
28
AP-70
The oiiginaI piogiam to compute the functions need
not change. Aftei computing the output vaiiabIes, the
contioI map is tiansmitted to the buffeied shift iegistei
thiough the seiiaI poit.
N07 $BUF,B _L0AI BUFFER ARI 1RAR$Nl1
The BooIean Piocessoi soIution hoIds a numbei of ad-
vantages ovei oIdei methods. Fewei switches aie ie-
quiied. Fach is simpIei, iequiiing fewei poIes and Iowei
cuiient contacts. The fIashei ieIay is eIiminated entiie-
Iy. OnIy six fiIaments aie diiven, iathei than 10. The
wiiing hainess is theiefoie simpIei and Iess expensive-
one conductoi foi each of the six Iamps and each of the
five sensoi switches. The fewei conductois use fai few-
ei connectois. The whoIe system is moie ieIiabIe.
And since the system is much simpIei it wouId be feasi-
bIe to impIement iedundancy and oi fauIt detection on
the foui main tuin indicatois. Fach couId stiII be a
standaid doubIe fiIament buIb, but with the fiIaments
diiven in paiaIIeI to toIeiate singIe-eIement faiIuies.
Fven with iedundancy, the Iights wiII eventuaIIy faiI.
To handIe this inescapabIe fact cuiient oi voItage sens-
ing ciicuits on each main diive wiie can veiify that
each buIb and its high-cuiient diivei is functioning
piopeiIy. Figuie 18 shows one such ciicuit.
Assume aII of the Iights aie tuined on except one: i.e.,
aII but one of the coIIectois aie giounded. Foi the buIb
which is tuined off, if theie is continuity fiom
a
12V
thiough the buIb base and fiIament, the contioI wiie, aII
connectois, and the P.C. boaid tiaces, and if the tian-
sistoi is indeed not shoited to giound, then the coIIec-
toi wiII be puIIed to
a
12V. This tuins on the base of
Q8 thiough the coiiesponding iesistoi, and giounds the
input pin, veiifying that the buIb ciicuit is opeiationaI.
The continuity of each ciicuit can be checked by soft-
waie in this way.
20383018
Figure 18
29
AP-70
Now tuin all the buIbs on, giounding aII the coIIectois.
Q7 shouId be tuined off, and the Test pin shouId be
high. Howevei, a contioI wiie shoited to
a
12V oi an
open-ciicuited diive tiansistoi wouId Ieave one of the
coIIectois at the highei voItage even now. This too
wouId tuin on Q7, indicating a diffeient type of faiIuie.
Softwaie couId peifoim these checks once pei second
by executing the ioutine eveiy time the softwaie count-
ei SUB
-
DIV is ieIoaded by the inteiiupt ioutine.
I5R7 $UB Il7,10$ER7
N07 $UB Il7,244 _REL0AI 00UR1ER
0RL Fl,lll00000B _$E1 00R1R0L
_0U1FU1$ Hl0H
0RL F2,00000lllB
0LR l FRR1 _FL0A1 IRl7E
_00LLE010R
5B 10,FAUL1 _10 $H0ULI BE
_FULLEI L0
$E1B L FRR1 _FULL 00LLE010R
_BA0K I0R
0LR L IA$H
5B 10,FAUL1
$E1B L IA$H
0LR L REAR
5B 10,FAUL1
$E1B L REAR
0LR R FRR1
5B 10,FAUL1
$E1B R FRR1
0LR R IA$H
5B 10,FAUL1
$E1B R IA$H
0LR R REAR
5B 10,FAUL1
$E1B R REAR
_
_l1H ALL 00LLE010R$ 0R0URIEI. 10
$H0ULI BE Hl0H
_lF $0. 00R1lRUE l1H lR1ERRUF1
R0U1lRE.
5B 10,10$ER7
FAUL1: _ELE01Rl0AL
_FAlLURE
_FR00E$$lR0
_R0U1lRE
_|LEF1 10
_REAIER$
_lNA0lRA1l0R,
10$ER7: _00R1lRUE l1H
_lR1ERRUF1
_FR00E$$lR0
_
_
The compIete assembIed piogiam Iisting is piinted in
Appendix A. The iesuIting code consists of 67 piogiam
statements, not counting decIaiations and comments,
which assembIe into 150 bytes of object code. Fach pass
thiough the seivice ioutine iequiies (coincidentIy)
67 ms pIus 32 ms once pei second foi the eIectiicaI test.
If executed eveiy 4 ms as suggested this softwaie wouId
typicaIIy ieduce the thioughput of the backgiound pio-
giam by Iess than 2%.
Once a miciocomputei has been designed into a system,
new featuies suddenIy become viituaIIy fiee. Softwaie
couId make the emeigency bIinkeis fIash aIteinateIy oi
at a iate fastei than the tuin signaIs. Tuin signaIs couId
oveiiide the emeigency bIinkeis. Adding moie buIbs
wouId aIIow muItipIe taiI Iight sequencing and syncopa-
tion-tiue fIash factoi, so to speak.
Design Example 5Complex Control
Functions
FinaIIy, weII mix byte and bit opeiations to extend the
use of 8051 into extiemeIy compIex appIications.
Piogiammeis can aibitiaiiIy assign I/O pins to input
and output functions onIy if the totaI does not exceed
32, which is insufficient foi appIications with a veiy
Iaige numbei of input vaiiabIes. One way to expand the
numbei of inputs is with a technique simiIai to muIti-
pIexed-keyboaid scanning.
Figuie 19 shows a bIock diagiam foi a modeiateIy com-
pIex piogiammabIe industiiaI contioIIei with the foI-
Iowing chaiacteiistics:
64 input vaiiabIe sensois:
12 output signaIs:
CombinationaI and sequentiaI Iogic computations:
Remote opeiation with communications to a host
piocessoi via a high-speed fuII-dupIex seiiaI Iink:
Two piioiitized exteinaI inteiiupts:
InteinaI ieaI-time and time-of-day cIocks.
WhiIe many miciopiocessois couId be piogiammed to
piovide these capabiIities with assoited peiipheiaI sup-
poit chips, an 8051 miciocomputei needs no othei inte-
giated ciicuits!
The 64 input sensois aie IogicaIIy aiianged as an 8x8
matiix. The pins of Poit 1 sequentiaIIy enabIe each coI-
umn of the sensoi matiix: as each is enabIed Poit 0
ieads in the state of each sensoi in that coIumn. An
eight-byte bIock in bit-addiessabIe RAM iemembeis
the data as it is iead in so that aftei each compIete scan
cycIe theie is an inteinaI map of the cuiient state of aII
sensois. Logic functions can then diiectIy addiess the
eIements of the bit map.
30
AP-70
20383019
Figure 19 Block Diagram of 64-Input Machine Controller
The computeis seiiaI poit is configuied as a nine-bit
UART, tiansfeiiing data at 17,000 bytes-pei-second.
The ninth bit may distinguish between addiess and data
bytes.
The 8051 seiiaI poit can be configuied to detect bytes
with the addiess bit set, automaticaIIy ignoiing aII oth-
eis. Pins INT0 and INT1 aie inteiiupts configuied ie-
spectiveIy as high-piioiity, faIIing-edge tiiggeied and
Iow-piioiity, Iow-IeveI tiiggeied. The iemaining 12 I/O
pins output TTL-IeveI contioI signaIs to 12 actuatois.
Theie aie seveiaI ways to impIement the sensoi matiix
ciicuitiy, aII IogicaIIy simiIai. Figuie 20a shows one
possibiIity. Fach of the 64 sensois consists of a paii of
simpIe switch contacts in seiies with a diode to peimit
muItipIe contact cIosuies thioughout the matiix.
The scan Iines fiom Poit 1 piovide eight un-encoded
active-high scan signaIs foi enabIing coIumns of the
matiix. The ietuin Iines on iows wheie a contact is
cIosed aie puIIed high and iead as Iogic ones. Open
ietuin Iines aie puIIed to giound by one of the 40 kX
iesistois and aie iead as zeioes. (The iesistoi vaIues
must be chosen to ensuie aII ietuin Iines aie puIIed
above the 2.0V Iogic thieshoId, even in the woist-case,
31
AP-70
wheie aII contacts in an enabIed coIumn aie cIosed.)
Since P0 is piovided open-coIIectoi outputs and high-
impedance MOS inputs its input Ioading may be con-
sideied negIigibIe.
The ciicuits in Figuies 20b20d aie vaiiations on this
theme. When input signaIs must be eIectiicaIIy isoIated
fiom the computei ciicuitiy as in noisy industiiaI envi-
ionments, phototiansistois can iepIace the switch diode
paiis and piovide opticaI isoIation as in Figuie 20b.
AdditionaI opto-isoIatois couId aIso be used on the con-
tioI output and speciaI signaI Iines.
The othei ciicuits assume that input signaIs aie aIieady
at TTL IeveIs. Figuie 20c uses octaI thiee-state buffeis
enabIed by active-Iow scan signaIs to gate eight signaIs
onto Poit 0. Poit 0 is avaiIabIe foi memoiy expansion
oi peiipheiaI chip inteifacing between sensoi matiix
scans. Fight-to-one muItipIexeis in Figuie 20d seIect
one of eight inputs foi each ietuin Iine as deteimined
by encoded addiess bits output on thiee pins of Poit 1.
(Five moie output pins aie thus fieed foi moie contioI
functions.) Fach output can diive at Ieast one standaid
TTL oi up to 10 Iow-powei TTL Ioads without addi-
tionaI buffeiing.
Ooing back to the oiiginaI matiix ciicuit, Figuie 21
shows the method used to scan the sensoi matiix. Two
compIete bit maps aie maintained in the bit-addiessabIe
iegion of the RAM: one foi the cuiient state and one
foi the pievious state iead foi each sensoi. If the need
aiises, the piogiam couId then sense input tiansitions
and oi debounce contact cIosuies by compaiing each
bit with its eaiIiei vaIue.
The code in FxampIe 3 impIements the scanning aIgo-
iithm foi the ciicuits in Figuie 20a. Fach coIumn is
enabIed by setting a singIe bit in a fieId of zeioes. The
bit maps aie positive Iogic: ones iepiesent contacts that
aie cIosed oi isoIatois tuined on.
Example .
lRFU1 $0AR: _$UBR0U1lRE 10 REAI
_0URRER1 $1A1E
_0F 84 $ER$0R$ ARI
_$A7E lR RAN 20H-27H
N07 R0,20H _lRl1lALl7E
_F0lR1ER$
N07 Rl,23H _F0R Bl1 NAF
_BA$E$
N07 A,30H _$E1 FlR$1 Bl1
_lR A00
$0AR_ N07 Fl,A _0U1FU1 10 $0AR
_LlRE$
RR A _$HlF1 10 ERABLE
_REX1 00LUNR
_REX1
N07 R2,A _RENENBER 0UR-
_RER1 $0AR
_F0$l1l0R
N07 A,F0 _REAI RE1URR
_LlRE$
X0H A,R0 _$l10H l1H
_FRE7l0U$ NAF
_Bl1$
N07 Rl,A _$A7E FRE7l0U$
_$1A1E A$ ELL
lR0 R0 _BUNF F0lR1ER$
lR0 Rl
N07 A,R2 _REL0AI $0AR
_LlRE NA$K
5RB A00,7_$0AR:_L00F UR1lL ALL
_El0H1 00LUNR$
_REAI
RE1
32
AP-70
20383020
a) Using Switch ContactDiode Matrix
Figure 20 Sensor Matrix Implementation Methods
33
AP-70
20383021
b) Using Optically-Coupled Isolators
Figure 20 Sensor Matrix Implementation Methods (Continued)
34
AP-70
20383022
c) Using TTL Three-State Buffers
Figure 20 Sensor Matrix Implementation Methods (Continued)
35
AP-70
20383023
d) Using TTL Data Selectors
Figure 20 Sensor Matrix Implementation Methods (Continued)
36
AP-70
20383024
Figure 21 Flowchart for
Reading in Sensor Matrix
What happens aftei the sensois have been scanned de-
pends on the individuaI appIication. Rathei than in-
venting some aitificiaI design piobIem, softwaie coiie-
sponding to commonpIace Iogic eIements wiII be dis-
cussed.
Combinatorial Output Variables An output vaiiabIe
which is a simpIe (oi not so simpIe) combinationaI
function of seveiaI input vaiiabIes is computed in the
spiiit of Design FxampIe 3. AII 64 inputs aie iepiesent-
ed in the bit maps: in fact, the sensoi numbeis in Figuie
20 coiiespond to the absoIute bit addiesses in RAM!
The code in FxampIe 4 activates an actuatoi connected
to P2.2 when sensois 12, 23, and 34 aie cIosed and
sensois 45 and 56 aie open.
FxampIe 4.
SimpIe CombinatoiiaI Output VaiiabIes.
_$E1 F2.24|l2,|2,|4,| 45,| 58,
N07 0,l2
ARL 0,2
ARL 0,4
ARL 0, 45
ARL 0, 58
N07 F2.2,0
Intermediate Variables The examination of a typicaI
ieIay-Iogic Iaddei diagiam wiII show that many of the
iungs contioI not outputs but iathei ieIays whose con-
tacts figuie into the computation of othei functions. In
effect, these ieIays indicate the state of inteimediate
vaiiabIes of a computation.
The MCS-51 soIution can use any diiectIy addiessabIe
bit foi the stoiage of such inteimediate vaiiabIes. Fven
when aII 128 bits of the RAM aiiay aie dedicated (to
input bit maps in this exampIe), the accumuIatoi, PSW,
and B iegistei piovide 18 additionaI fIags foi inteimedi-
ate vaiiabIes.
Foi exampIe, suppose switches 0 thiough 3 contioI a
safety inteiIock system. CIosing any of them shouId de-
activate ceitain outputs. Figuie 22 is a Iaddei diagiam
foi this situation. The inteiIock function couId be ie-
computed foi eveiy output affected, oi it may be com-
puted once and save (as impIied by the diagiam). As
the piogiam pioceeds this bit can quaIify each output.
37
AP-70
FxampIe 5. Incoipoiating Oveiiide signaI into actu-
atoi outputs.
_ 0ALL lRFU1 $0AR
N07 0,0
0RL 0,l
0RL 0,2
0RL 0,
N07 F0,0
_ .... .....
_ 00NFU1E FUR01l0R 0
_
ARL 0, F0
N07 FL0,0
_ .... .....
_ 00NFU1E FUR01l0R l
_
ARL 0, F0
N07 Fl,l,0
_ .... .....
_ 00NFU1E FUR01l0R 2
_
ARL 0, F0
N07 Fl,2,0
_ .... .....
20383025
Figure 22 Ladder Diagram for
Output Override Circuitry
Latching Relays A Iatching ieIay can be foiced into
eithei the ON oi OFF state by two coiiesponding input
signaIs, wheie it wiII iemain untiI foiced onto the oppo-
site state-anaIogous to a TTL Set/Reset fIip-fIop. The
ieIay is used as an inteimediate vaiiabIe foi othei caIcu-
Iations. In the pievious exampIe, the emeigency condi-
tion couId be iemembeied and iemain active untiI an
emeigency cIeaied button is piessed.
Any fIag oi addiessabIe bit may iepiesent a Iatching
ieIay with a few Iines of code (see FxampIe 6).
FxampIe 6. SimuIating a Iatching ieIay.
_l $E1 $E1 FLA0 0 lF 04l
l $E1: 0RL 0,F0
N07 F0,0
_
_l R$E1 RE$E1 FLA0 0 lF 04l
l R$E1: 0F$ 0
ARL 0,F0
N07 F0,0
_
Time Delay Relays A time deIay ieIay does not ie-
spond to an input signaI untiI it has been piesent (oi
absent) foi some piedefined time. Foi exampIe, a baI-
Iast oi Ioad iesistoi may be switched in seiies with a
D.C. motoi when it is fiist tuined on, and shunted fiom
the ciicuit aftei one second. This soit of time deIay may
be simuIated by an inteiiupt ioutine diiven by one of
the two 8051 timei counteis. The pioceduie foIIowed
by the ioutine depends heaviIy on the detaiIs of the
exact function needed: time-outs oi time deIays with
iesettabIe oi non-iesettabIe inputs aie possibIe. If the
inteiiupt ioutine is executed eveiy 10 miIIiseconds the
code in FxampIe 7 wiII cIeai an inteimediate vaiiabIe
set by the backgiound piogiam aftei it has been active
foi two seconds.
FxampIe 7. Code to cIeai USRFLO aftei a fixed
time deIay.
5RB U$R FL0,RX11$1
I5R7 ILAY 00UR1,RX11$1
0LR U$R FL0
N07 ILAY 00UR1,200
RX11$1_ _.. .....
38
AP-70
Serial Interface to Remote Processor When it detects
emeigency conditions iepiesented by ceitain input
combinations (such as the eaiIiei Fmeigency Oveiiide),
the contioIIei couId shut down the machine immediate-
Iy and/oi aIeit the host piocessoi via the seiiaI poit.
Code bytes indicating the natuie of the piobIem couId
be tiansmitted to a centiaI computei. In fact, at 17,000
bytes-pei-second, the entiie contents of both bit maps
couId be sent to the host piocessoi foi fuithei anaIysis
in Iess than a miIIisecond! If the host decides that con-
ditions waiiant, it couId aIeit othei iemote piocessois
in the system that a piobIem exists and specify which
shut-down sequence each shouId initiate. Foi moie in-
foimation on using the seiiaI poit, consuIt the MCS-51
Useis ManuaI.
Response Timing
One diffeience between ieIay and piogiammed indus-
tiiaI contioIIeis (when each is consideied as a bIack
box) is theii iespective ieaction times to input chang-
es. As iefIected by a Iaddei diagiam, ieIay systems con-
tain a Iaige numbei of iungs opeiating in paiaIIeI. A
change in input conditions wiII begin piopagating
thiough the system immediateIy, possibIy affecting the
output state within miIIiseconds.
Softwaie, on the othei hand, opeiates sequentiaIIy. A
change in input states wiII not be detected untiI the next
time an input scan is peifoimed, and wiII not affect the
outputs untiI that section of the piogiam is ieached.
Foi that ieason the iaw speed of computing the IogicaI
functions is of extieme impoitance.
Heie the BooIean piocessoi pays off. Every instruction
mentioned in this Note compIetes in one oi two micio-
seconds-the minimum instiuction execution time foi
many othei miciocontioIIeis! A Iaddei diagiam con-
taining a hundied iungs, with an aveiage of foui con-
tacts pei iung can be iepIaced by appioximateIy five
hundied Iines of softwaie. A compIete pass thiough the
entiie matiix scanning ioutine and aII computations
wouId iequiie about a miIIisecond: Iess than the time it
takes foi most ieIays to change state.
A piogiammed contioIIei which simuIates each BooIe-
an function with a subioutine wouId be Iess efficient by
at Ieast an oidei of magnitude. Fxtia softwaie is needed
foi the simuIation ioutines, and each step takes Iongei
to execute foi thiee ieasons: seveiaI byte-wide IogicaI
instiuctions aie executed pei usei piogiam step (iathei
than one BooIean opeiation): most of those instiuctions
take Iongei to execute with miciopiocessois peifoiming
muItipIe off-chip accesses: and caIIing and ietuining
fiom the vaiious subioutines iequiies oveihead foi
stack opeiations.
In fact, the speed of the BooIean Piocessoi soIution is
IikeIy to be much fastei than the system iequiies. The
CPU might use the time Ieft ovei to compute feedback
paiameteis, coIIect and anaIyze execution statistics,
peifoim system diagnostics, and so foith.
Additional Functions and Uses
With the buiIding-bIock basics mentioned above many
moie opeiations may be synthesized by shoit instiuc-
tion sequences.
Exclusive-OR Theie aie no common mechanicaI devic-
es oi ieIays anaIogous to the FxcIusive-OR opeiation,
so this instiuction was omitted fiom the BooIean
Piocessoi. Howevei, the FxcIusive-OR oi FxcIusive-
NOR opeiation may be peifoimed in two instiuctions
by conditionaIIy compIementing the caiiy oi a BooIean
vaiiabIe based on the state of any othei testabIe bit.
_EX0LU$l7E-_0R FUR01l0R lNF0$EI 0R 0ARRY
_U$lR0 F0 l$ lRFU1 7ARlABLE.
_X0R F0: 5RB F0,X0R0R1 _|5B F0R X-R0R,
0FL 0
_X0R0R1: ... .....
XCH The contents of the caiiy and some othei bit may
be exchanged (switched) by using the accumuIatoi as
tempoiaiy stoiage. Bits can be moved into and out of
the accumuIatoi simuItaneousIy using the Rotate-
39
AP-70
thiough-caiiy instiuctions, though this wouId aItei the
accumuIatoi data.
_EX0HAR0E 0ARRY l1H U$RFL0
X0HBl1: RL0 A
N07 0,U$R FL0
RR0 A
N07 U$R FL0,0
RL0 A
Extended Bit Addressing The 8051 can diiectIy addiess
144 geneiaI-puipose bits foi aII instiuctions in Figuie
3b. SimiIai opeiations may be extended to any bit any-
wheie on the chip with some Ioss of efficiency.
The IogicaI opeiations AND, OR, and FxcIusive-OR
aie peifoimed on byte vaiiabIes using six diffeient ad-
diessing modes, one of which Iets the souice be an im-
mediate mask, and the destination any diiectIy addiess-
abIe byte. Any bit may thus be set, cIeaied, oi compIe-
mented with a thiee-byte, two-cycIe instiuction if the
mask has aII bits but one set oi cIeaied.
Byte vaiiabIes, iegisteis, and indiiectIy addiessed RAM
may be moved to a bit addiessabIe iegistei (usuaIIy the
accumuIatoi) in one instiuction. Once tiansfeiied, the
bits may be tested with a conditionaI jump, aIIowing
any bit to be poIIed in 3 micioseconds-stiII much fast-
ei than most aichitectuies-oi used foi IogicaI caIcuIa-
tions. (This technique can aIso simuIate additionaI bit
addiessing modes with byte opeiations.)
Parity of bytes or bits The paiity of the cuiient accu-
muIatoi contents is aIways avaiIabIe in the PSW, fiom
whence it may be moved to the caiiy and fuithei
piocessed. Fiioi-coiiecting Hamming codes and simi-
Iai appIications iequiie computing paiity on gioups of
isoIated bits. This can be done by conditionaIIy compIe-
menting the caiiy fIag based on those bits oi by gathei-
ing the bits into the accumuIatoi (as shown in the DFS
exampIe) and then testing the paiaIIeI paiity fIag.
Multiple byte shift and CRC codes
Though the 8051 seiiaI poit can accommodate eight- oi
nine-bit data tiansmissions, some piotocoIs invoIve
much Iongei bit stieams. The aIgoiithms piesented in
Design FxampIe 2 can be extended quite ieadiIy to 16
oi moie bits by using muIti-byte input and output buff-
eis.
Many mass data stoiage peiipheiaIs and seiiaI commu-
nications piotocoIs incIude CycIic Redundancy (CRC)
codes to veiify data integiity. The function is geneiaIIy
computed seiiaIIy by haidwaie using shift iegisteis and
FxcIusive-OR gates, but it can be done with softwaie.
As each bit is ieceived into the caiiy, appiopiiate bits
in the muIti-byte data buffei aie conditionaIIy compIe-
mented based on the incoming data bit. When finished,
the CRC iegistei contents may be checked foi zeio by
ORing the two bytes in the accumuIatoi.
40 SUMMARY
A tiuIy unique facet of the InteI MCS-51 miciocomput-
ei famiIy design is the coIIection of featuies optimized
foi the one-bit opeiations so often desiied in ieaI-woiId,
ieaI-time contioI appIications. IncIuded aie 17 speciaI
instiuctions, a BooIean accumuIatoi, impIicit and diiect
addiessing modes, piogiam and mass data stoiage, and
many I/O options. These aie the woiIds fiist singIe-
chip miciocomputeis abIe to efficientIy manipuIate, op-
eiate on, and tiansfei eithei bytes oi individuaI bits as
data.
This AppIication Note has detaiIed the infoimation
needed by a miciocomputei system designei to make
fuII use of these capabiIities. Five design exampIes weie
used to contiast the soIutions aIIowed by the 8051 and
those iequiied by pievious aichitectuies. Depending on
the individuaI appIication, the 8051 soIution wiII be eas-
iei to design, moie ieIiabIe to impIement, debug, and
veiify, use Iess piogiam memoiy, and iun up to an oi-
dei of magnitude fastei than the same function impIe-
mented on pievious digitaI computei aichitectuies.
Combining byte- and bit-handIing capabiIities in a sin-
gIe miciocomputei has a stiong syneigistic effect: the
powei of the iesuIt exceeds the powei of byte- and bit-
piocessois Iaboiing individuaIIy. ViituaIIy aII usei ap-
pIications wiII benefit in some way fiom this duaIity.
Data intensive appIications wiII use bit addiessing foi
test pin monitoiing oi piogiam contioI fIags: contioI
appIications wiII use byte manipuIation foi paiaIIeI I/O
expansion oi aiithmetic caIcuIations.
It is hoped that these design exampIes give the ieadei
an appieciation of these unique featuies and suggest
ways to expIoit them in his oi hei own appIication.
40
AP-70
APPENDIX A
Automobile Turn-Indicator
Controller Program Listing
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