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Negative Setup and Hold Time

Setup and hold times define the timing window around a clock edge during which the input to a flip-flop must remain stable to ensure correct operation. Setup time specifies how long before the clock edge the input must be stable, while hold time specifies how long after the clock edge the input must remain stable. Negative setup or hold times allow the input to change slightly before or after the clock edge, respectively. Violations of setup or hold times can be addressed by optimizing logic delays, using low voltage threshold cells, or adding delay buffers.

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355 views

Negative Setup and Hold Time

Setup and hold times define the timing window around a clock edge during which the input to a flip-flop must remain stable to ensure correct operation. Setup time specifies how long before the clock edge the input must be stable, while hold time specifies how long after the clock edge the input must remain stable. Negative setup or hold times allow the input to change slightly before or after the clock edge, respectively. Violations of setup or hold times can be addressed by optimizing logic delays, using low voltage threshold cells, or adding delay buffers.

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Masterbrain Brain
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as DOCX, PDF, TXT or read online on Scribd
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Setup and Hold time

Our designs are restricted by the data transfer between the flip-flops. Routing delay, logic cell delay and the FF parameters determine the maximum speed of the circuit. There is a timing window around the clocking event during which the synchronous input must remain stable and unchanged in order to be recognized. This window is defined by the setup and hold times. If either is violated correct operation of the FF is not guaranteed. Setup Time: It is the minimum time before the clocking event by which the synchronous input must be stable, so that the data is properly sampled by the clock. Hold Time: It is the minimum time after the clocking event during which the synchronous input must remain stable, so that data is reliably sampled.

Fig: Setup and Hold time

The window associated with the clock region does not have to be centered around the clock edge. The region can be right or left to the clock edge when setup or hold times are negative.

When the hold time is negative, the valid region is to the left of the clock edge. Negative hold time allows the clock input to change slightly before the clock edge without disturbing the operation of the clock. This happens when delay for data from the pin of the flop to internal latch point is larger than corresponding clock delay.

Fig: Negative Hold time

When the setup time is negative the valid region is on the right of the clock edge. Negative setup time allows the input to change slightly after the clock edge and still meet the time check.

Fig: Negative setup time Note: 1. Both setup and hold times cannot be negative at the same time. Guess why? (Left to the reader to explore) 2. 3. Setup is checked at next clock edge. Hold is checked at same clock edge.

Steps to tackle setup violations: a. Reducing the combinational logic delay between the flip-flops by optimizing the logic. i.e. reducing the logic depth b. Use of Low Vt cells which in turn reduce the standard cells delay. But this has a tradeoff on the leakage power which increases drastically. So, this step should be done carefully and selectively keeping overall leakage into account. c. Enabling useful skew is also an option. Steps to tackle hold violations:

a. The first step to avoid hold violations is to build a good clock tree with skew as minimum as possible. b. By adding delay cells (delay buffers) in the combinational path.

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