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Delay

The document discusses noise margins and gate delay in logic circuits. It defines noise margins as the amount of noise a gate input can tolerate before incorrectly recognizing the input. It also defines propagation delay and contamination delay. RC delay models are used to estimate gate delays, where the transistors are modeled as resistors and capacitances. An example estimates the rising and falling delays of a 2-input NAND gate driving identical loads as the sum of a parasitic delay and an effort delay proportional to the load. CMOS inverter delay is approximated using a constant average current model.

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109 views

Delay

The document discusses noise margins and gate delay in logic circuits. It defines noise margins as the amount of noise a gate input can tolerate before incorrectly recognizing the input. It also defines propagation delay and contamination delay. RC delay models are used to estimate gate delays, where the transistors are modeled as resistors and capacitances. An example estimates the rising and falling delays of a 2-input NAND gate driving identical loads as the sum of a parasitic delay and an effort delay proportional to the load. CMOS inverter delay is approximated using a constant average current model.

Uploaded by

varun186
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Noise Margin and Gate Delay

Debdeep Mukhpadhyay IIT Madras

Logic levels
Solid logic 0/1 defined by VSS/VDD. Inner bounds of logic values VL/VH are not directly determined by circuit properties, as in some other logic families.
VDD

logic 1 unknown
VH VL

VSS

logic 0

Logic level matching


Levels at output of one gate must be sufficient to drive next gate.

Transfer characteristics
Transfer curve shows static input/output relationshiphold input voltage, measure output voltage.

Noise Margins
How much noise can a gate input see before it does not recognize the input?
Output Characteristics Logical High Output Range VDD Input Characteristics Logical High Input Range Indeterminate Region Logical Low Input Range

VOH NMH VIH VIL NML

Logical Low Output Range

VOL GND

Logic Levels
To maximize noise margins, select logic levels at
Vout VDD

p / n > 1 Vin Vout

0 VDD

Vin

Logic Levels
To maximize noise margins, select logic levels at
unity gain point of DC transfer characteristic
Vout VDD VOH p / n > 1 Vin Vout Unity Gain Points Slope = -1

VOL 0 Vtn VIL VIH VDD- VDD |Vtp|

Vin

Noise margin
Noise margin = voltage difference between output of one gate and input of next. Noise must exceed noise margin to make second gate produce wrong output.

Delay Definitions
tpdr: tpdf: tpd: tr: tf: fall time

Delay Definitions
tpdr: rising propagation delay From input to rising output crossing VDD/2 tpdf: falling propagation delay From input to falling output crossing VDD/2 tpd: average propagation delay tpd = (tpdr + tpdf)/2 tr: rise time From output crossing 0.2 VDD to 0.8 VDD tf: fall time From output crossing 0.8 VDD to 0.2 VDD

Delay Definitions
tcdr: rising contamination delay
From input to rising output crossing VDD/2

tcdf: falling contamination delay


From input to falling output crossing VDD/2

tcd: average contamination delay


tpd = (tcdr + tcdf)/2

Simulated Inverter Delay


Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write
2.0

1.5

1.0 (V)

Vin
0.5

tpdf = 66ps

tpdr = 83ps

Vout

0.0

0.0

200p

400p t(s)

600p

800p

1n

Delay Estimation
We would like to be able to easily estimate delay Not as accurate as simulation But can we give estimates? The step response usually looks like a 1st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that tpd = RC Characterize transistors by finding their effective R Depends on average current as gate switches

RC delay
Load is resistor + capacitor, driver is resistor.

tf

= 0.69 R CL For rise time replace by the PMOS resistance.

RC Delay Models
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C

Capacitance proportional to width Resistance inversely proportional to width d


s g d k s R/k g kC s kC kC d k s kC g kC d kC 2R/k g

Example: 3-input NAND


Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

Example: 3-input NAND


Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
2 2 2 3 3 3

3-input NAND Caps


Annotate the 3-input NAND gate with gate and diffusion capacitance.
2 2 2

3 3 3

3-input NAND Capacitors


Annotate the 3-input NAND gate with gate and diffusion capacitance.
2C 2 2C 2C 2C 2 2C 2C 3 3 3 2C 2 2C 2C 3C 3C 3C 3C

3C 3C 3C

3-input NAND Capacitors


Annotate the 3-input NAND gate with gate and diffusion capacitance.
2 5C 5C 5C 2 2 3 3 3 9C 3C 3C

Elmore Delay
ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t pd Ri to sourceCi

= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) C N


R1 R2 C1 R3 C2 C3 RN CN

nodes i

Example: 2-input NAND


Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.
2 A B 2 2 2x
h copies

Example: 2-input NAND


Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
2 A B 2 2 2x 6C 2C Y 4hC
h copies

Example: 2-input NAND


Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
2 A B
R Y (6+4h)C

2 2 2x 6C 2C

Y 4hC
h copies

t pdr =

Example: 2-input NAND


Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
2 A B
R Y (6+4h)C

2 2 2x 6C 2C

Y 4hC

h copies

t pdr = ( 6 + 4h ) RC

Example: 2-input NAND


Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
2 A B 2 2 2x 6C 2C

Y 4hC
h copies

Example: 2-input NAND


Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
2 A B 2 2 2x 6C 2C Y 4hC
h copies

x R/2

R/2 2C

Y (6+4h)C

t pdf =

Example: 2-input NAND


Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
2 A B
R/2 2C

2 2 2x 6C 2C

Y 4hC

h copies

x R/2

Y (6+4h)C

R R t pdf = ( 2C ) ( R + 6 + 4 h C + ( ) ) ( 2 2 2)

= ( 7 + 4h ) RC

Delay Components
Delay has two parts
Parasitic delay
6 or 7 RC Independent of load

Effort delay
4h RC Proportional to load capacitance

An approximate method:

CMOS inverter delay


V1=Vcc V2=Vcc I1

Assume constant Iavg The NMOS and the PMOS are in saturated region and provide a constant current.

t PHL

CloadVCC = 2 k n (VCC VTn ) k p (VCC VTP CloadVCC

t PLH =

t1

t2

Iavg = I1

Some Points
The delay of a gate, be it the rise or the fall time is inversely proportional to VDD. Point to ponder: Effect of sizing on the inverter gate delay.

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