Backend - Chapter 11

Text Book: Silicon VLSI Technology Fundamentals, Practice and Modeling Authors: J J. D D. Plummer Plummer, M M. D D. Deal Deal, and P. B. Griffin

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Backend - Chapter 11

Frontend vs. Backend

Backend Frontend

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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Backend - Chapter 11

Backend Technology
Aluminum Oxide N+ Sili Silicon Oxide

Backend technology: fabrication of interconnects and the dielectrics that electrically isolate them. Early structures were simple by today's standards.

More metal interconnect levels increases circ circuit it f functionality nctionalit and speed. Interconnects are separated into local interconnects (polysilicon, (p y silicides, TiN) and intermediateglobal interconnects (Cu or Al). Backend processing is becoming more important important. Larger fraction of total structure and processing. Starting to dominate total speed of circuit.
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Backend - Chapter 11

Interconnection Considerations
Wire lengths
Intra-cell routing I t Inter-cell ll routing ti Local intra-block routing Global inter-block routing, clock, power
TI Presentations Slides: Impact of (Metal) Interconnect Scaling and Process Variation on Performance, Mayur Joshi, Nagaraj NS, Anthony Hill, Texas Instruments (http://www cmoset com/uploads/Joshi pdf) (http://www.cmoset.com/uploads/Joshi.pdf)

Si ifi Significant C Concerns

Wire resistance Wire capacitance Signal skew (interconnect variation) Wire delays vs. gate delays (wire beginning to dominate) Planarization Vias vs. lines Local interconnect Connection to gates
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Inherent Considerations

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

Backend - Chapter 11

Chemical-Mechanical Polishing
Wafer carrier Wafer (facing down) Slurry Polishing pad Polishing table

The most common solution for planarization today is CMP, which works very well well. It is capable of forming very flat surfaces as shown in the example.
Oxide slurry Polishing pad (semi-rigid)

Close-up of wafer/pad interface: Silicon

Deposit thick oxide

Plasma etchback

CMP

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling Locally planarized topography remains By Plummer, Deal & Griffin

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Backend Structure Schematic

With PECVD oxide/PECVD nitride passivation bilayer on top of final metal level PECVD SiO2 PECVD SiO2 PECVD SiO2 PECVD SiO2 CVD SiO2 BPSG CVD SiO2 Field Oxide

SOG or SOD

Metal 2 W

SOG or SOD W
N+

Metal 1

Silicon

One possible dielectric multi multi-structure structure scheme scheme. Other variations include HDP oxide or the use of CMP.

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Backend - Chapter 11

Backend Structure SEM

Two backend structures. o Left: three metal levels and encapsulated BPSG for the first level dielectric; SOG (encapsulated top and bottom with PECVD oxide) and CMP in the intermetal dielectrics. The multilayer metal layers and W plugs l are also l clearly l l seen. o Right: five metal levels, HDP oxide (with PECVD oxide on top) and CMP in the intermetal dielectrics.

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Backend - Chapter 11

Measurement Methods
Resistance and Resistivity
Metals and silicides

R=

L
H W

s =

L R = s W

C Contact R Resistance i
Cross-bridge Kelvin Probed Structure

Rc =
Multiple contacts in series

c
L W

RTotal = n Rc + m1 R1 + m2 R2

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Backend - Chapter 11

Electrical Measurements of Contacts

Low resistance

lt =

S Silicon

Representative of a complex series resistance computation

Rc =
KELVIN BRIDGE

c
lt W

gives i overestimation ( RC ) of the contact properties

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

2000 by Prentice Hall Upper Saddle River NJ

Backend - Chapter 11

Models and Simulation

Backend process simulation obviously relies heavily on the deposition and etching simulation tools discussed in Chapters 9 and 10. Thin Film Deposition and Etching are key to processing. SPEEDIE, SPEEDIE ATHENA and d TAURUS previously i l mentioned i d are all ll used d o Silicide Formation o Chemical Mechanical Polishing o Reflow o Grain Growth o Electromigration g

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Backend - Chapter 11

Titanium Silicide Formation

a)
Si + Ti TiSi 2 newly formed TiSi2 Ti TiSi 2 Si Silicon Si Silicon N

b)
N+ Ti TiN Si + Ti TiSi 2

TiN Ti TiSi 2

Si or N diffusion through the material

Silicide S c de formation o at o is so often te modeling ode g us using g the t e Deal-Grove ea G o e linearea parabolic model. Titanium Silicide growth based on a selective salicide formation. 1 nm of TI consumes 2.27 nm of Si producing 2.51 nm of TiSi2 xs2 x + s = t + B B/ A
A t + 1 xs = 1 + 2 A / 4B 2

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Backend - Chapter 11

Alternate Silicide Formations

CoSi2 Model TiSi2 Model

Concern shorting of source-gate or gate-drain One solution: simultaneously grow TiN during the anneal
TiN is may also be used as a local interconnect if not removed TiN is also a diffusion barrier for most dopants

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Backend - Chapter 11

From Dr. Saraswat

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

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Backend - Chapter 11

Titanium Silicide Modeling

Simulation of TiSi2 formation using FLOOPS [11.32] on a 0.35 m wide gate structure. Left: before formation anneal step. Right: after formation anneal step: 30 sec at 650C in a nitrogen atmosphere
Titanium -0.4 Oxide spacer -0.2 Polysilicon

Pinning point -0.4

Titanium silicide

Titanium Titanium nitride

-0.2 x in microns

x in microns

0
Silicon dioxide Silicon

0.2

0.2

Titanium Silicon silicide dioxide

Silicon

0.4 -0.8

-0.4

0.0 y in microns

0.4

0.8

0.4 -0.8

-0.4

0.0 y in microns

0.4

0.8

Titanium Deposition

After Anneal in Nitrogen TiSi2 forms over silicon and polysilicon, not over SiO2.

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Backend - Chapter 11

Salicide: Table 11-5 p. 700

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Backend - Chapter 11

Chemical Mechanical Polishing

CMP models d l have h also l been b incorporated i t d in i process simulators. i l t Models for CMP attempt to determine the relative pressure at each point and then calculate the relative removal rate at each point assuming that it is linearly yp proportional p to the local p pressure (see ( text). )

a)
1 micro ons

b)

c)

microns

20

microns

20

microns

20

ATHENA simulation of chemical-mechanical polishing of SiO2 over Al lines: a before polishing; a. b. after 3 minutes of polishing; c. after 6 minutes of polishing li hi

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Backend - Chapter 11

Chemical Mechanical Polishing

microns

05 0.5 SiO2 0 W

05 0.5 SiO2 0 W

microns

10

microns

10

ATHENA simulation of chemical-mechanical polishing of a tungsten via structure: o Left: before polishing; o Right: after polishing polishing. Due to the faster polishing of tungsten compared to silicon dioxide and the semi-rigid pad, dishing of the tungsten plug can result.
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Backend - Chapter 11

Reflow
Reflow occurs to minimize the total energy of the system. In this case, the surface energy of the structure is reduced by minimizing the curvature. Surface S f diffusion diff i is i one reflow fl mechanism h i (metals ( l at high hi h T). T) Atoms will move to regions of lower chemical potential, , which is a function of the curvature. K = s Force = s s where s is the per-area surface energy, is the atomic volume of the atom, Ki is the th curvature, t and d s is i the th length l th along l the th surface. f The curvature, K, is equal to the inverse of the radius of curvature, R, at that point: p 1 K= R The force acting upon an atom is in the direction away from a point of higher curvature to a point of lower curvature. curvature A smoothing of the topography results.
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Backend - Chapter 11

Reflow (2)
R2 R1

1 Force 2

The surface flux of atoms, Fs then equals:

Ds 2K s 2 Fs = kT s where is the number of atoms per unit area, and Ds is the surface diffusivity of the atoms.
2.0
(a)

2.0 1.5 Heigh ht (microns) 1.0 0.5

0.0

-0.5 -1.0 3 4 5 6 Width (microns) 7

Heigh ht (microns)

initial profile 15 min., 800K 30 min. 60 min.

1.5 1.0 0.5

initial profile 3 min., 800K 9 min. 18 min.

(b)

0.0

-0.5 -1.0 3 4 5 6 Width (microns)

initial profile 3 min., 800K 12 min. 18 min. 24 min.

2.0 Heigh ht (microns) 1.5 1.0 0.5 00 0.0

-0.5 -1.0

SILICON TECHNOLOGY 7 3 VLSI 4 5 6 (microns) Fundamentals,Width Practice and Modeling By Plummer, Deal & Griffin

Heigh ht (microns)

initial profile 2 min., 800K 4 min. 8 min.

(c)

3.0 2.0 1.0 0.0

(d)

-1.0 2 4 6 Width (microns) 8

Simulations of R. Brain, for reflow of Cu at 800K for different trench sizes: o a. 1 x 1 m; o b. 0.5 x 1 m; o c. 0.33 x 1 m; and o d. d three 0 0.5 5 x 1 m trenches spaced 0.5 m apart. (parameters given in Table 11.8, p. 751, in text.) Note filling of trenches and smoothing of topography.
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Grain Growth
All materials used for interconnections are polycrystalline. That is, they are made up of regions of single crystal material where atoms are lined up perfectly that contact irregularly at crystal grain boundaries. Grain boundaries may have significantly different properties than the grains. (traps, density, etc.) With heating, heating average grain size grows. Grain growth is similar to reflow. Grain growth occurs along existing boundaries, with growth occurring where another grain is losing material.

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Grain Growth Simulations

Normal grain growth with time. Based on work k by b Frost F t and d colleagues ll referenced f d in the text. y state, , average g grain g size In steady determined by sqrt(t).
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin

Grain growth within a strip in time. The limit to grain growth is related to the structure. For polycrystalline films growth proceeds until the average p g g grain diameter is approximately 2 to 3 times the film thickness.
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Backend - Chapter 11

The Future of Backend Technology

Remember: R b
Year of Production Technology N ode (half pi tch) MPU Printed Gate Leng th Min Meta l 1 Pitch (nm) Wiring Levels - Logic Me tal 1 Aspect Ratio (Cu) Contact As pec t Ratio (D RAM ) STI Trenc T h As A pec t Ratio R ti Me tal Res istivi ty (ohm-cm) Interlevel Dielectric Con stant 3.3, 2.2 3.9 2.2 3.7 2.2 3.7

1 1 L = 0.89RC 0 89RC = 0.89 0 89 K I K ox oL + Hx ox WLS

1998 2000 2002 130 nm 70 nm 2004 90 nm 53 nm 214 10 1.7 15 48 4.8 2.2 <2.7 2007 65 nm 35 nm 152 11 1.7 16 59 5.9 2.2 <2.4 2010 45 nm 25 nm 108 12 1.8 >20 79 7.9 2.2 <2.1 2013 32 nm 18 nm 76 12 1.9 >20 10 3 10.3 2.2 <1.9

2016 22 nm 13 nm 54 14 2.0 >20 14 2.2 <1.7

2018 18 nm 10 nm 42 14 2.0 >20 16 4 16.4 2.2 <1.7

250 nm 180 nm 100 nm

Reduce metal resistivity - use Cu instead of Al. Aspect ratio - advanced deposition, etching and planarization methods. Reduce R d di l t i constant dielectric t t - use low-K l K materials. t i l
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Backend - Chapter 11

Summary of Key Ideas

Backend processing (interconnects and dielectrics) have taken on increased importance in recent years. Interconnect delays now contribute a significant component to overall circuit performance in many applications. Early backend structures utilized simple aluminum to silicon contacts. Reliability R li bilit i issues, th the need df for many l levels l of fi interconnect t t and d planarization l i ti issues have led to much more complex structures today involving multilayer metals and dielectrics. CMP i is th the most t common planarization l i ti t technique h i t today. d Copper and low-K dielectrics are now found in some advanced chips and their use will likely be common in the future. Beyond these materials changes, interconnect options in the future include architectural (design) approaches to minimizing wire lengths, optical interconnects, electrical repeaters and RF broadcasting. All of these areas will see significant i ifi t research hi in th the next tf few years.
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SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin