Dr.

Mariam Md Ghazaly BEKC4883

GROUND RULE
Discussion on related topic only Formality tolerate Can stop any time for emergency case, but raise hand first Try to have fun Three Ways Communication

Industrial Talk; Manufacturing Systems in E&E Sector

Prepared by Mohd Azizi bin Chik SilTerra Malaysia April 28th 2013

Expected candidates in this class

Everyone that new to Wafer Fab operation new employee, partnership, internships, researchers, or visitors of SilTerra. Others that equivalent are also invited

Content Guidelines (2 of 2)
Introduction to Manufacturing operation (02:00pm 04.00pm), Group discussion (2:30 pm to 3:30 pm), Results reviews
1 Electrical & Electronic (E&E) Outlook

Simulation modeling for Manufacturing Operation

Capacity, Bottleneck, & Product Mixed Dispatching Rules Policies and review basic company case study

Session I

Brief on Semiconductor Fabrication

Working Group Presentation (1hrs, Group presentation 5 min each)

Exercise for Dispatching Rules Presentation and proposal (Discussion)

Advance Manufacturing Application Outlook

Session II

Introduction to Manufacturing Operation & Production Scheduling

Dr. Mariam Md Ghazaly BEKC4883

Source, Malaysia Economic Transformation Annual Report 2012

Source, Malaysia Economic Transformation Annual Report 2012

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Source, Malaysia Economic Transformation Annual Report 2012 Source, Malaysia Economic Transformation Annual Report 2012
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ELECTRONIC PROCESS SUPPLY CHAIN

Global Semiconductor Forecast

Semiconductor outlook for the next 3 years is still healthy 7.9 CAGR 2012- 2015 (IC foundry Almanac 2012). Stable Demand for 8 matured technology and conversion of 6 to 8 by IDM (Gartner Oct 2011).

Raw Wafer Fabrication

Wafer Fabrication

The most complicated process compared to others in electronic chain

Packaging & Assembly

PCBA

Final Product Assembly

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Dr. Mariam Md Ghazaly BEKC4883

Wafer Fabrication & Bumping Facility at Hsinchu, Taiwan

Fab Cluster Expanding in China

(6 fab facilities)

(1 fab facility)

(7 fab facilities)

(1 fab facility)

(1 fab facility) (1 fab facility)

(1 fab facility)
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(1 fab facility)

(1 fab facility)
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Wafer Fabrication & Bumping Facility at Woodlands, Singapore

Woodlands
Semiconductor Back End Intel AMD Linear Spansion Marvell Globetro nic Osram Lumileds Altera IDT Avago ASE Fairchild Hitachi Sumitom o System / Module / Device Seagate Plexus Knowles Smart Kingston Jabil Mo Sanmina Kontron Flextroni c Solectro Komag Molex n Equipm Semiconductor Back End ent Carsem Unisem IDS Dell Solectro VDO System / n Module / Device Murata Agilent Sanyo LKT Inventec Ben-Q Penta Semiconductor Back End Clarion Bosch Vitrox On Semi NXP System / Module / Device Alps TDK NHK Equipm ent Samsun Xyratex g

Malaysias Electronic Clusters

Semiconductor Front End Silterra Hamad Infineo a n Semiconductor Back End AIC Intel Hitachi System / Module / Device Sharp Fuji Akrion Applied Materials ASML KLA Tencor Asyst Celestica Metex Wong Equipment Sharp Onkyo Aviza Axcelis Intevac Back VarianEnd Semiconductor LamST Micro QT Services ST Memory Research System / Module / Device

Kedah

Silterra
Penang Perak

(1 fab facility) (6 fab facilities) (1 fab facility)

Selangor / KL Negeri Sembilan Semiconductor Back End Infineon Qimonda Dominant NS System / Module / Device TEAC Qualiteck Muhlbeuer Flextronic Equipment Panasonic Creative Melaka

(1 fab facility) (1 fab facility) (1 fab facility)

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Semiconductor Front End S.E.H. MEMC Semiconductor Back End Freescal TI Toshiba e Spansion ChipPac NEC k System / Module / Device Sensata Flextron Nichia ic ChungHu a Equipment WD Semiconductor Epson Samsung Front End Panasoni Sony Flextronic X-Fab c s Seagate Mitsui Mitsutoy Hitachi System / Module / Sharp Onkyo o Device Canon Nemic-Lamda PCA Taiyo Toko Tech Yuden Ronnie Hokuden FCI Sanmina Komag Komag Pioneer Equipment Sarawak Brother Celestica Sharp Flextroni Kenwoo Sanyo Johor cs d Mitsubis Panasoni Podoyo hi c Mitsumi Seiko

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2010 Foundry Ranking by Gartner. Clear lines are drawn. Its Top 4 and the rest

Silterra Malaysia Sdn Bhd

Top Fab 2002 Frost & Sullivan 2009 Award High Voltage Tech Implementation Product Excellent Award 2009 Capacity 30K Wafers per Month Consistent Utilization of more than 100% SilTerra continues at full utilization last year. In 2010, SilTerra supplied 25.6% of DDIs global market (source RSSM 2011).

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Dr. Mariam Md Ghazaly BEKC4883

Breakdown by Degrees of Engineering in FAB

Q&A OR DISCUSSION
At least 3

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Short Video
1 Electrical & Electronic (E&E) Outlook

SilTerra

Session I

Brief on Semiconductor Fabrication

Advance Manufacturing Application Outlook

Session II

Introduction to Manufacturing Operation & Production Scheduling

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Whats in a Chip

Relative Size Comparison (Size does matter!)

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Dr. Mariam Md Ghazaly BEKC4883

PROCESS COMPLEXITY
Wafer fabrication process, is a process to make mask layers. These represent basic structure like transistors, capacitor, insulator and etc. Process steps are between 300 to 900 steps, almost 100% re-entrance to same equipment. More than 35% Reentrance at 10 to 18 times. Cycle time varies from 30 to 90 days. Cycle time measurement is DPML = days per mask layer

Introduction: Adding Layers

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Short Video
Silicon Magic

Q&A OR DISCUSSION
At least 3

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1970s
1 Electrical & Electronic (E&E) Outlook

Session I

Brief on Semiconductor Fabrication

Advance Manufacturing Application Outlook

Session II

Introduction to Manufacturing Operation & Production Scheduling

Toshiba Corporation
Source Iwai RSSM 2011

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Dr. Mariam Md Ghazaly BEKC4883

300 mm Fab TSMC

In a future No person is necessary!

Now
Toshiba Oita Works

300 mm Super clean room in Tsukuba,Selete

Source: Iwai RSSM 2011

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Source: Iwai RSSM 2011

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FAB LAYOUT

w1

Further Advanced Manufacturing Systems Architecture

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Fab7 Command and Control Center (C3) dbut in 2007

APF New Architecture

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Slide 34 w1 - Try to keep titles consistent, if "F7" indicates "Fab 7" then we suggest keeping to "Fab 7" as previous slides indicate it as such.
wuuf, 8/18/2004

Dr. Mariam Md Ghazaly BEKC4883

Example: Server configuration for dispatching/data collection related

Storage

Knowledge and Imagination

Imagination is more important than knowledge. Knowledge is limited. Imagination encircles the world

Albert Einstein Scientist

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Product Time-to-Market Is Vital

1 Electrical & Electronic (E&E) Outlook

The impact of being late to market is becoming very significant. Faster cycle time needed, also resulted in lowered down equipment capacity
Games DVD PCS Cellular PC VCR Color TV Cable TV B&W TV

Session I

Brief on Semiconductor Fabrication

Advance Manufacturing Application Outlook

One Million Units

Session II

Introduction to Manufacturing Operation & Production Scheduling

Sales Volume

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Years After Introduction

Source: Semico Research

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PRODUCT COMPLEXITY PART OF LIFE

Better Performance, More Functions

Re-Entrance Process to same equipment

13 steps 8 steps CMP Implant

29 steps TFD/TFM

9 steps Diffusion

24 steps Etch

Con Mask Met1 Mask Poly Mask Met5 Mask Viax Mask Isl Mask Met2 Mask Metx Mask

Intra bay

Photolithography

DUV01 DUV02 DUV03

15 steps
Inter bay

Smaller Size, Lower Cost

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Dr. Mariam Md Ghazaly BEKC4883

High Ranges Product Mix vs. Variable Process Cycle Time

Introduction: OHMs Law

V = IR Variability = Income Reduction

Dr James Ignizio, Intel ISSM 2003

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Introduction: Sources of Variability

There are many sources of variability
Process variability Flow variability Equipment failure Batch Sizes Equipment Setup Changeover Times AMHS delivery times In consistent WIP levels Huge Data collection Loading Plan or Demand Plan Inefficient dispatch policies Inconsistent dispatching

DISPATCHING RULE GOAL

Overall main goal
Lot delivery time (OTD)
Dispatching based on priority, due date (Critical Ratio, CR = ((due date current date)/remaining cycle time) with quality consideration given*

Reduce Cost (high move, more capacity, improve Efficiency)

Optimum possible batching, not breaking allowable queue time

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Others Common Dispatching Rule available

Others Business Rule available, are
FCFS ( First Come First Come First Serve) SPT ( Shortest processing Time) EDD (Earliest Due Date) CR* (Critical Ratio) * Currently used for dispatching

First Come First Serve (FCFS)

Selection of the product to be process is based on the arrival time. Product reach first, will be selected to be process first. In factory, Its it preferred to use in the situation of low loading or utilization. (traditional method to serve common interest in service industry)

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Dr. Mariam Md Ghazaly BEKC4883

Shortest Processing Time

Selection of the product to be process is based on the shortest processing time. Usually when there is significant amount of WIP due to unexpected down-time from module. This is temporary dispatching policies during high WIP situation and when certain criteria met.

Earliest Due Date

Selection of the product to be process is based on the earliest due date. Usually during moderate loading with less product-mixed

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Critical Ratio
Selection of the product to be process is based on the smallest ratio of due date vs remaining processing time. Mainly used during moderate WIP level for production required re-entrance processing, and high productmixed.

GROUP ASSIGNMENT

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Dispatching Rule Computation

Calculation is being done for 5 seconds
Collect the required information from various systems Data structure formatting

BREAK 10 MINUTES

Formula computation

Calculation for CR,, lot assignments, What & Where Display difference color & at what equipment

Organizing the output configuration

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Dr. Mariam Md Ghazaly BEKC4883

DISPATCHING (PHOTO)

DISPATCHING (DIFFUSION)

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Example of APF Programming

Close similar to C ++ programming

CASE STUDY ALIKE

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Roles of APF/RTD at SilTerra

APF Reports and RTD are one of the key tools to improve manufacturing efficiency and the breakdowns are as follows with examples in the next few slides.

Current Dispatching Policies

Total Dispatch Rule = 72, Almost all are design to optimize move in each tool type capability.

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Dr. Mariam Md Ghazaly BEKC4883

Benchmarking Dispatching Policies

OPTIONS: HYBRID DISPATCH POLICIES

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Hybrid Type Sample: Critical Ratio with Starvation Avoidance

Critical Ratio : To meet customer delivery date Starvation Avoidance : To ensure bottleneck tools always have WIP to run

Calculations Details
Critical Ratio :
(Due Date Current Time) / Remaining Plan Cycle Time

Starvation Avoidance :
Time Required at the bottleneck / Lot Plan cycle time to bottleneck Time Required at Bottleneck : (( (Time_to_BN x WIP)) - (Time_to_BN x WIP)) + (Bottleneck TCT x Bottleneck WIP)) - Buffer

It Means..
(Total Work Time for WIP to BN) + (Work Time at BN ) WIP Buffer Time

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Starvation Avoidance

Critical Ratio Vs Starvation Avoidance

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Dr. Mariam Md Ghazaly BEKC4883

Final Ranking

Q&A

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Summary
New Learning regards
Overall picture about semiconductor fabrication, its complexity and our application in today environment Advanced Manufacturing, current practice. Semiconductor Manufacturing operation Production Scheduling & Dispatching

Thank You
[email protected]

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