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Design For Testability

The document discusses testing considerations in chip design. It covers topics like fault models, observability and controllability, and design for test techniques like scan chains and built-in self-test. Scan chains allow the contents of flip-flops to be observed and controlled for testing. Built-in self-test allows blocks to generate test patterns and check results without external test equipment. Boundary scan adds test capabilities to chip pins to facilitate board-level testing. Thorough testing is important due to the high costs of failures and recalls.

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Denise Nelson
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Download as PDF, TXT or read online on Scribd
43 views

Design For Testability

The document discusses testing considerations in chip design. It covers topics like fault models, observability and controllability, and design for test techniques like scan chains and built-in self-test. Scan chains allow the contents of flip-flops to be observed and controlled for testing. Built-in self-test allows blocks to generate test patterns and check results without external test equipment. Boundary scan adds test capabilities to chip pins to facilitate board-level testing. Thorough testing is important due to the high costs of failures and recalls.

Uploaded by

Denise Nelson
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Lecture 12: Design for Testability

Outline
Testing Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan
12: Design for Testability CMOS VLSI Design 4th Ed. 2

Testing
Testing is one of the most expensive parts of chips Logic verification accounts for > 50% of design effort for many chips Debug time after fabrication has enormous opportunity cost Shipping defective parts can sink a company Example: Intel FDIV bug (1994) Logic error not caught until > 1M units shipped Recall cost $450M (!!!)
12: Design for Testability CMOS VLSI Design 4th Ed. 3

Logic Verification
Does the chip simulate correctly? Usually done at HDL level Verification engineers write test bench for HDL Cant test all cases Look for corner cases Try to break logic design Ex: 32-bit adder Test all combinations of corner cases as inputs: 0, 1, 2, 231-1, -1, -231, a few random numbers Good tests require ingenuity
12: Design for Testability CMOS VLSI Design 4th Ed. 4

Silicon Debug
Test the first chips back from fabrication If you are lucky, they work the first time If not Logic bugs vs. electrical failures Most chip failures are logic bugs from inadequate simulation Some are electrical failures Crosstalk Dynamic nodes: leakage, charge sharing Ratio failures A few are tool or methodology failures (e.g. DRC) Fix the bugs and fabricate a corrected chip
12: Design for Testability CMOS VLSI Design 4th Ed. 5

Shmoo Plots
How to diagnose failures? Hard to access chips Picoprobes Electron beam Laser voltage probing Built-in self-test Shmoo plots Vary voltage, frequency Look for cause of electrical failures
12: Design for Testability CMOS VLSI Design 4th Ed. 6

Manufacturing Test
A speck of dust on a wafer is sufficient to kill chip Yield of any chip is < 100% Must test chips after manufacturing before delivery to customers to only ship good parts Manufacturing testers are very expensive Minimize time on tester Careful selection of test vectors

12: Design for Testability

CMOS VLSI Design 4th Ed.

Manufacturing Failures

SEM images courtesy Intel Corporation

12: Design for Testability

CMOS VLSI Design 4th Ed.

Stuck-At Faults
How does a chip fail? Usually failures are shorts between two conductors or opens in a conductor This can cause very complicated behavior A simpler model: Stuck-At Assume all failures cause nodes to be stuck-at 0 or 1, i.e. shorted to GND or VDD Not quite true, but works well in practice

12: Design for Testability

CMOS VLSI Design 4th Ed.

Examples

12: Design for Testability

CMOS VLSI Design 4th Ed.

10

Observability & Controllability


Observability: ease of observing a node by watching external output pins of the chip Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip Combinational logic is usually easy to observe and control Finite state machines can be very difficult, requiring many cycles to enter desired state Especially if state transition diagram is not known to the test engineer
12: Design for Testability CMOS VLSI Design 4th Ed. 11

Test Pattern Generation


Manufacturing test ideally would check every node in the circuit to prove it is not stuck. Apply the smallest sequence of test vectors necessary to prove each node is not stuck. Good observability and controllability reduces number of test vectors required for manufacturing test. Reduces the cost of testing Motivates design-for-test
12: Design for Testability CMOS VLSI Design 4th Ed. 12

Test Example
A3 A2 A1 A0 n1 n2 n3 Y SA1 {0110} {1010} {0100} {0110} {1110} {0110} {0101} {0110} SA0 {1110} {1110} {0110} {0111} {0110} {0100} {0110} {1110}
A3 A2 n2 n1 Y n3 A1 A0

Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}


12: Design for Testability CMOS VLSI Design 4th Ed. 13

Design for Test


Design the chip to increase observability and controllability If each register could be observed and controlled, test problem reduces to testing combinational logic between registers. Better yet, logic blocks could enter test mode where they generate test patterns and report the results automatically.

12: Design for Testability

CMOS VLSI Design 4th Ed.

14

Scan
Convert each flip-flop to a scan register SCAN Only costs one extra multiplexer SI D Normal mode: flip-flops behave as usual Scan mode: flip-flops behave as shift register
scan-in

CLK Flop
Flop Flop outputs Flop Flop scanout

Contents of flops can be scanned out and new values scanned in


12: Design for Testability

Flop

Flop

inputs Flop

Logic Cloud Flop

Flop

Flop

Logic Cloud

Flop

CMOS VLSI Design 4th Ed.

Flop

15

Scannable Flip-flops
SCAN SCAN CLK Flop D (a) SI D 0 1 Q SI (b) d SCAN d D d s SI s X Q Q X Q Q

s (c)

12: Design for Testability

CMOS VLSI Design 4th Ed.

16

ATPG
Test pattern generation is tedious Automatic Test Pattern Generation (ATPG) tools produce a good set of vectors for each block of combinational logic Scan chains are used to control and observe the blocks Complete coverage requires a large number of vectors, raising the cost of test Most products settle for covering 90+% of potential stuck-at faults

12: Design for Testability

CMOS VLSI Design 4th Ed.

17

Built-in Self-test
Built-in self-test lets blocks test themselves Generate pseudo-random inputs to comb. logic Combine outputs into a syndrome With high probability, block is fault-free if it produces the expected syndrome

12: Design for Testability

CMOS VLSI Design 4th Ed.

18

PRSG
Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
Step
CLK Flop Flop D D D Flop Q[0] Q[1] Q[2]

Q 111 110 101 010 100 001 011 111 (repeats)


19

0 1 2 3

Flops reset to 000

4 5 6 7

12: Design for Testability

CMOS VLSI Design 4th Ed.

BILBO
Built-in Logic Block Observer Combine scan with PRSG & signature analysis
D[0] C[0] C[1] D[1] D[2]

Flop

Flop

SI

1 0

Q[0]

Q[1]

PRSG

Logic Cloud

Signature Analyzer

MODE Scan Test Reset Normal

C[1] 0 0 1 1

Flop

Q[2] / SO

C[0] 0 1 0 1

12: Design for Testability

CMOS VLSI Design 4th Ed.

20

Boundary Scan
Testing boards is also difficult Need to verify solder joints are good Drive a pin to 0, then to 1 Check that all connected pins get the values Through-hold boards used bed of nails SMT and BGA boards cannot easily contact pins Build capability of observing and controlling pins into each chip to make board test easier

12: Design for Testability

CMOS VLSI Design 4th Ed.

21

Boundary Scan Example


PackageInterconnect

CHIP B

CHIP C

Serial Data Out

CHIP A

CHIP D

IO pad and Boundary Scan Cell Serial Data In

12: Design for Testability

CMOS VLSI Design 4th Ed.

22

Boundary Scan Interface


Boundary scan is accessed through five pins TCK: test clock TMS: test mode select TDI: test data in TDO: test data out TRST*: test reset (optional) Chips with internal scan chains can access the chains through boundary scan for unified test strategy.
12: Design for Testability CMOS VLSI Design 4th Ed. 23

Testing Your Class Project


Presilicon Verification Test vectors: corner cases and random vectors HDL simulation of schematics for functionality Use 2-phase clocking to avoid races Use static CMOS gates to avoid electrical failures Use LVS to ensure layout matches schematic Dont worry about timing Postsilicon Verification Run your test vectors on the fabricated chip Use a functional chip tester Potentially use breadboard or PCB for full system

12: Design for Testability

CMOS VLSI Design 4th Ed.

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TestosterICs
TestosterICs functional chip tester Designed by clinic teams and David Diaz at HMC Reads your test vectors, applies them to your chip, and reports assertion failures

12: Design for Testability

CMOS VLSI Design 4th Ed.

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Summary
Think about testing from the beginning Simulate as you go Plan for test after fabrication If you dont test it, it wont work! (Guaranteed)

12: Design for Testability

CMOS VLSI Design 4th Ed.

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