EDK Tutorial 1 Introduction to EDK 9.

2 and the ML403 Platform

-Introduction
These labs will be designed under the structure listed below. The tutorials will range from the simple and introductory to much more complicated and involved. All of the tutorials will be developed using the Xilinx Embedded Development Kit commonly referred to as EDK. This tutorial will be the first in a series of tutorials as shown below.

Figure 1. Entire list of tutorials

This lab will be an introduction to design techniques for EDK as it is related to the ML403 platform. It will explain the basics of building a project with the wizard and then expanding the project to include a hello world option. It will be necessary to have a nullmodem cable to communicate between the Hyper Terminal on the PC and the ML403 FPGA platform.

-Objective
The objective is to understand the basics of the EDK software. This will be accomplished through the implementation of a UART in an FPGA. The circuit will be designed in such a way that the phrase hello world will be displayed to a HyperTerminal.

-Process
1. Step through the project design steps. 2. Verify outputs on HyperTerminal.

-Implementation
1. Open the Xilinx Platform Studio by selecting it from the start menu.

Figure 2. XPS Project Selection

2. The Xilinx Platform Studio, or XPS, Base System Builder will launch. For the purposes of this tutorial, it is important to use the Wizard. Select the top option.

Figure 3. Project Directory Selection

3. Choose a directory for the sample project. Avoid directory names with spaces in them.

Figure 4. BSB Screen

4.

Choose to create a new design. The BSB (Base System Builder) allows the user to be able to open a new design or to import the BSB settings from a previous project. Click Next and it will show the Base System Builder window.

Figure 5. Board Selection

5. The board selection will be the Xilinx ML 403. There is only one revision of this board so this selection is easy. Click Next

Figure 6. Processor Type

6. Select Next, saving the PowerPC as the processor to use in this design. (The EDK software allows the user to create a project for one of two types of processors. The first is a virtual processor called the Microblaze. This processor is created within the fabric of the FPGA. The second type (and the one selected) is the PowerPC. This is the IBM PPC405 which is actually embedded into the fabric of the FPGA.)

Figure 7. Basic Selections

7. Select Next, saving the default settings. (This is a menu specifically designed to configure the PowerPC. If there were a desire to change the clock frequencies then they could be done here. By clicking on the More Info button, more information on the changeable values can be obtained.)

Figure 8. Screen 1 of 3 for Interfaces

8. This is the first of three screens for choosing input and output interfaces. As shown in the screen above, select the XPS UARTLITE. Deselect all other options, and then click Next. This project will only have two items associated with the Processor Local Bus or PLB. The two items used will be the UART and the BRAM.

Figure 9. Screen 2 of 3 for Interfaces

9. This is the second screen for adding interfaces. For this tutorial, deselect all the options, and then click Next.

Figure 10. Screen 3 of 3 for Interfaces

10. This is the last screen of the IO options. Once again, deselect all the options, and then click Next.

Figure 11. Internal Peripherals

11. Choose 64KB of BRAM, and then select Next.

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Figure 12. Software Setup

12. This is the Software Setup screen. It is where choices are made as to which items will be used by STDIN and STDOUT. In the case of this tutorial, HyperTerminal will use the RS232_Uart for both sets of communications. Since the project is using only one type of memory, the section is easy. For the purposes of this tutorial, deselect Memory test and Peripheral selftest. Click Next.

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Figure 13. Address Maps

13. The address maps displayed above show that there are two items assigned to the PLB: BRAM and UART. The BRAM has FFFF or 64K of memory assigned. Select Generate.

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Figure 14. BSB Completion

14. Select Finish and the BSB will generate the embedded system and return the user to XPS.

(Step 17)

Figure 15. PLB Connections

15. The PLB connections are now shown. The user can see where the PLB makes connections with the BRAM and the UART. Figure 15 shows that there is only one software project associated so far, Default:ppc405_0_bootloop. Default:ppc405_0_bootloop contains the MicroBlaze or PowerPC bootloop 13

executables that cause the MicroBlaze or PowerPC embedded processors to loop at the reset vector. This guarantees that the embedded processor stays in a known good state. XPS creates the bootloops automatically for each new project. To make use of the bootloop, mark the bootloop application in your XPS project for initialization of block RAMs (BRAMs). Ensure that multiple applications are not initialized into the BRAMs at the same time.

Figure 16. Add Project

16. Double click on the Add Software Application Project. Choose a suitable project name, such as HelloWorld. Dont forget that the project name cannot have spaces. Select OK.

Figure 17. Add Source File

17. Once the project is created, it is necessary to add the embedded source file(s). Right click on the Sources icon and choose to Add New File.

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Figure 18. Hello World

18. For clarity and easy of file management, it is recommended that you create a directory and store all your source files in it. For this example, a new directory called SourcesC was created and the source file HWorld.c was created and stored there. This will be an empty file.

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Figure 19. HelloWorld.c

19. Expand Sources, and then double click on the HWorld.c file to open it. All that is needed in this source file is the seven lines shown above. This will print to the STDIO (UART) the phrase hello world.

Figure 20. Linker Script

20. Right-click on the Project: HelloWorld and select Generate Linker Script.

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Figure 21. Memory Assignments

21. Click OK. Note The default linker script uses a fixed start address of 0xFFFF0000 for PowerPC. Modify the start address to reflect the address corresponding to the memory defined in your hardware system. Default linker scripts assume a contiguous memory starting from the address defined as the start address. If the application cannot fit into this contiguous region, or if the application needs to be split across different memories in the system, then a custom linker script is needed. Run the Generate Linker Script command to create a custom linker script for the application.

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Figure 22. Initialize BRAM

22. It is necessary to initialize the BRAM with the hello world project. Right-click on Default:ppc405_0_bootloop and deselect the Mark to Initialize BRAMs option. Choose the Mark to Initialize BRAMs option for Project: HelloWorld. There should no longer be a red x on the Project: HelloWorld icon.

Figure 23. Download Bitstream

23. Under Device Configuration, choose Update Bitstream.

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Figure 24. HyperTerminal

24. Start the HyperTerminal software. As stated above, it is necessary to have a nullmodem cable to communicate between the Hyper Terminal on the PC and the ML403 FPGA platform. Hyper Terminal should be configured to connect using the port assigned to the USB-to-Serial cable.

Figure 25. Port Confirmation

25. If you are unsure about which COM Port you are using, you can see by going to the Device Manager under the hardware tab. To get there, go to control panel and then system. As shown above, the USB-to-Serial adapter that is connected to this PC is connected to COM6, therefore Hyper Terminal is also configured to connect using COM6.

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Figure 26. HyperTerminal Parameters

26. Choose these settings for the Hyper Terminal on the PC to conform with the settings used on the ML403. Once you choose these settings, click on Apply. This will allow the user to just choose Restore Defaults each following time they launch Hyper Terminal.

Figure 27. Download Bitstream

27. If the entire software application fits on FPGA block RAM (BRAM) blocks, the system can be initialized by updating the hardware bitstream with the BRAM initialization data. This updated bitstream can then be downloaded to the FPGA. Under Device Configuration, choose Download Bitstream. The bitstream is initialized with the executable. In the XPS (non-submodule) flow, this will result in 20

the generation of the <project>/implementation/download.bit bitstream file containing both hardware and software.

Figure 28. Results Output

28. Once the project has completed and downloaded, the HyperTerminal will display hello world.

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