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ECE 171 Digital Circuits: Prof. Mark G. Faust Maseeh College of Engineering and Computer Science

This document discusses integrated circuits and their characteristics. It begins by introducing IC packaging, logic families, key parameters like propagation delay and power dissipation. It then covers taxonomies of ICs based on density, design methodology and technology. Specific logic families like TTL and CMOS are examined. IC costs, packages, parameters and a sample datasheet are reviewed. It concludes with an example schematic using common ICs.

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Minh Hoang
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67 views

ECE 171 Digital Circuits: Prof. Mark G. Faust Maseeh College of Engineering and Computer Science

This document discusses integrated circuits and their characteristics. It begins by introducing IC packaging, logic families, key parameters like propagation delay and power dissipation. It then covers taxonomies of ICs based on density, design methodology and technology. Specific logic families like TTL and CMOS are examined. IC costs, packages, parameters and a sample datasheet are reviewed. It concludes with an example schematic using common ICs.

Uploaded by

Minh Hoang
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE171 DigitalCircuits

Prof.MarkG.Faust MaseehCollegeofEngineering andComputerScience

Lecture7
Topics
TheRealWorldofICLogic g
ICPackages ICLogicFamilies KeyICParameters CMOSICDatasheets DetailedSchematicsusingICs

TaxonomiesofICs
Density/LevelofIntegration
SSI( (SmallScaleIntegration) g )~10gates/IC g / MSI(MediumScaleIntegration)102 gates/IC LSI(LargeScaleIntegration)103 gates/IC VLSI(VeryLargeScaleIntegration)107108gates/IC

TaxonomiesofICs
DesignMethodology
StandardComponents(SSI/MSI/LSI)
OfftheshelfComponents BasicUniversalBuildingBlocks(AND,OR,NAND,NOR)

ApplicationSpecificStandardParts(ASSP)
TargetSpecificApplicationArea,butnotCustomer e.g. e g PrinterController Controller,USBInterfaceIC, IC HDDI/F

ApplicationSpecificIC(ASIC)
CustomDesignofICTargetingSpecificMarket Fullcustom,standardcell,gatearrays e.g.ATI3DGraphicsEngine

Programmable g Logic g Devices( (PLD) )


Canbeusedtoimplementwidevarietydesigns e.g.FPGA(FieldProgrammableGateArrays)
4

TaxonomiesofICs
Technology
Bipolar
TTL(TransistorTransistorLogic) ECL(EmitterCoupledLogic) others
Advantages
Inexpensive High level of integration High speed V l Very low quiescent i (static) ( i ) power consumption i Rail-to-Rail outputs

CMOS

Disadvantages
Susceptible to electrostatic discharge (ESD) damage Susceptible to latch-up

Has become dominant logic technology

TaxonomiesofICs
Families
TTL
STDTTL:StandardTTL LSTTL:LowPowerSchottkyTTL ASTTL:AdvancedSchottkyTTL ALSTTL:AdvancedLowPowerSchottkyTTL F/FASTTTL:FairchildAdvancedSchottkyTTL AC:AdvancedCMOS ACT:AdvancedCMOS(TTLCompatible) HC:HighSpeedCMOS HCT:High g Speed p CMOS( (TTLCompatible) p )
6

CMOS

IntegratedCircuitCosts

Die

AMDOpteron

DIP(DualInLinePackage)Details

AdditionalICPackageTypes

10

KeyICParameters
Vcc(PowerSupplyVoltage) LogicLevels
VIH,VIL,VOH,VOL NoiseMargin

PropagationDelay(tpd) Rise/FallTimes(Tr,Tf) PowerDissipation FanOut


11

Vcc PowerSupply pp yVoltage g


Commonacrossalogicfamily(e.g.5VforallHCparts) Vcc and dGnd G d commonly l called ll d powersupply l rails il
SometimesVdd andVss forCMOSdevices +5V

12

Logic g Levels
Commonacrossalogicfamily(e.g.allHCparts) VIH,VIL,VOH,VOL
+5V VIHMinimuminputvoltageguaranteedtoberecognizedasH VILMaximuminputvoltageguaranteedtoberecognizedasL VOHMinimumoutputvoltageguaranteedproducedforH VOLMaximumoutputvoltageguaranteedproducedforL Typical CMOS Values VOH Vcc 0.1V 0 1V VIH VIL 70% of Vcc 30% of Vcc
13

VOL Gnd + 0.1V

Logic g Levels
Commonacrossalogicfamily(e.g.allHCparts) VIH,VIL,VOH,VOL
V =5 Vcc 5.0V 0V +5V High VIH = 3.5V 3 5V Undefined VOH = 4.44V

VIL = 1.5V 0.0V

Low

VOL = 0.5V
14

LogicLevels
Input A 5V VIH = 3.5V VIL = 1.5V 0V Output F 5V VOH = 4.44V VOL = 0.5V 0V
15

NoiseMargin g
Ensurescorrectbehaviordespitetypicalconditions
Vcc=5.0V VIH=3.5V Undefined VIL=1.5V 0 0V 0.0V NoiseMarginhigh =VOH VIH NoiseMarginlow =VIL VOL High VOH=4.44V

Low

VOL=0.5V
16

FamilyLogicLevelComparison

17

PropagationDelay(Tpd d,Tplh lh,Tphl hl)


Outputs O t t dont d tinstantaneously i t t l reflect fl tinput i tchanges h Propagationdelayisameasureofthistime Delay D l f fromHtoLlik likely l todiff differentthan h f fromLtoH
50% 0%

50%
18

RiseandFallTime(Tr,Tf)
Takes T k ti timef forsignal i lt toreach hit itsoutput t tvoltage lt Willbeaffectedbycapacitance,fanout Al known Also k asslew l rate Typicallymeasuredfrom10%/90%ofVOL/VOH swing
90% 10% VOH VOL
19

tr

tf

CMOSVoltagevs. vs Speed

20

CurrentandFanOut
IIH, IIL, IOH, IOL
IIH Maximum current that flows into the input p in H state IIL Maximum current that flows into the input in L state IOH Maximum current that output can source in H state while maintaining output voltage of at least VOH IOL Maximum current that output can sink in L state while maintaining output voltage of no more than VOL

21

FanOut
Sourcing current IOH = (IIH)

22

FanOut
Sinking current IOL = (IIL)

23

PowerDissipation p
Powerdissipationandconsumption Static(quiescent)powerdissipation
Whendeviceoutputsnotchanging VerylowforCMOS

Dynamicpowerdissipation

PD = (CPD + CL ) V f
2 CC
CPD = Power dissipation capacitance (constant for logic family) CL = Capacitive load on output (driving other devices) VCC = Supply voltage f
24 = Transition frequency (0.5 x number of output transitions/second)

CMOSVoltageRoadmap

25

ProductLifeCycle

26

Brief description P kdevice Package options i and dpinouts i Partnumber:SN54/74<family><function> SN54 military;SN74commercial HC highspeedCMOSfamily 08Quad2inputpositive(logic)ANDgates

SampleDataSheet(Part1)

Mainfeatures/benefitsofdevice(featuresbullets)

Description

SampleDataSheet(Part2)

Note different environmental conditions specified for 74/54 Package style Availability and corresponding orderable part number

28

SampleDataSheet(Part3)

Not Operating Conditions!

29

Maximum Nominal Minimum

~70%

30

Sometimescalleddcsection

SampleDataSheet(Part5)

31

Sometimescalledacsection

32

DeviceNameandPackage Designators

33

DetailedSchematicUsingICs

34

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