A (3:0) B (3:0) Y (3:0) CB M: Xilinx ISE Lab #3 - Spring 2011 Name
A (3:0) B (3:0) Y (3:0) CB M: Xilinx ISE Lab #3 - Spring 2011 Name
2012 R. W. Allison
XilinxISELab#3Spring2011
Name ______________________________
GeneralStatement: Using the 1-bit Adder/Subtractor logic from the previous lab, you are to design and implement a combinational circuit that adds or subtracts two 4-bit binary numbers together, A(3:0) plus/minus B(3:0), producing the 4-bit binary result Y(3:0), plus a carry/borrow out CB. The mode input, M, controls whether the logic will subtract or add according to the following:
If M == 0, then {CB, Y[3:0]} = A[3:0] + B[3:0]. If M == 1, then {CB, Y[3:0]} = A[3:0] B[3:0].
A(3:0)
B(3:0)
A3 A2 A1 A0 M
B3 B2 B1 B0 Cin
Add_Sub4
CB Y3 Y2 Y1 Y0
Y(3:0)
Deliverables: You are to draw the circuit using the Schematic Editor, then simulate it using the Simulator. Lastly, you are to get a printout of the results. You must turn (1) this cover sheet, followed by (2) a printout of the circuit from the Schematic Editor, followed by (3) a printout of the timing diagrams from ModelSim. Once you've verified the logic, you are to implement it and download it into the FPGA on the Digilab board. Connect input M to push button BTN0, connect inputs (A3..A0, B3..B0) to the 8 slide switches (SW7..SW0) respectively, connect the outputs (CB,Y3,Y2,Y1,Y0) to 5 LED's (LD4..LD0), respectively. Due Date: Tuesday, March 13, 2012
Combinational Logic Lab # 3 Page 1
{Tues. of week 8}
CECS 201
2012 R. W. Allison
Now create a New Source schematic file to create the new 4-bit adder/subtractor (if you have not already done so). Once you are within the Xilinx Schematic Editor to create/edit the 4-bit adder/subtractor, open up the other FAS.sch schematic file. You will now have two files open in the Schematic Editor. The new user defined symbol that we are going to create will be within the new 4-bit adder/subtractor schematic. From within the schematic editor select the Symbol Wizard option from the Tools menu. Select the Using Schematic option for Pin Name Source, then choose the name of your 1-bit adder/subtractor schematic from the pull down menu (see right). Then click the Next button. The FAS symbol will automatically be created for you (click the Next button on next two dialog boxes and the Finish button on the last one). You should now be able to see the block diagram of your new user defined symbol (e.g. fas.sym). Close the Symbol Wizard.
To instantiate your 1-bit adder/subtractor within the 4-bit adder/subtractor circuit, you simply go to the Symbols tab in the Schematic Editor, and look for the name of your new symbol, select it and drop four instances into your schematic just like any other gate or logic element that youve used before.
CECS 201
2012 R. W. Allison
Busses
Buses are a convenient way to group related signals. However, buses can be any group of signals, related or not. This grouping produces a less cluttered, functionally clearer drawing and clarifies the connection between the main circuit and a block symbol. Buses are especially useful for the following: Routing a number of signals from one side of the schematic to the other Connecting more than one signal to a block signal using one I/O marker Bus taps allow you to take an individual net of a bus and connect it to a scalar pin on a symbol. You can also connect multiple nets from a bus or an entire bus to a bus pin on a symbol. In all cases, the number of signals and number of pins must match.
Creating Busses
A bus is a single wire that represents multiple nets. You create a bus by adding a net to a schematic, then promoting the net to a bus by naming the net using a bus specifier as described in this procedure. What to Do First Add a net to the schematic. To Create a Bus on a Schematic 1. Select Net Name from the Add menu, or click the Add Net Name toolbar button. The Options tab shows the Add Net Name Options. 2. In the Options tab, click Name the branch. 3. In the Name field, enter the name for the bus. The bus must be named according to the rules described in Bus Names. 4. Click the net to promote to a bus.
CECS 201
2012 R. W. Allison
Figure 2 Example of Inputting Hexadecimal Values into Test Bench Waveform Editor