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A (3:0) B (3:0) Y (3:0) CB M: Xilinx ISE Lab #3 - Spring 2011 Name

4-bit adder / subtractor adds or subtracts two 4-bit binary numbers together. Mode input, M, controls whether the logic will subtract or add according to the following. 4-bit output will be implemented as a 4-bit output "bus"

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0% found this document useful (0 votes)
29 views4 pages

A (3:0) B (3:0) Y (3:0) CB M: Xilinx ISE Lab #3 - Spring 2011 Name

4-bit adder / subtractor adds or subtracts two 4-bit binary numbers together. Mode input, M, controls whether the logic will subtract or add according to the following. 4-bit output will be implemented as a 4-bit output "bus"

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harry75700
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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CECS 201

Digital Logic Design

2012 R. W. Allison

XilinxISELab#3Spring2011

Name ______________________________

GeneralStatement: Using the 1-bit Adder/Subtractor logic from the previous lab, you are to design and implement a combinational circuit that adds or subtracts two 4-bit binary numbers together, A(3:0) plus/minus B(3:0), producing the 4-bit binary result Y(3:0), plus a carry/borrow out CB. The mode input, M, controls whether the logic will subtract or add according to the following:
If M == 0, then {CB, Y[3:0]} = A[3:0] + B[3:0]. If M == 1, then {CB, Y[3:0]} = A[3:0] B[3:0].

A(3:0)

B(3:0)

A3 A2 A1 A0 M

B3 B2 B1 B0 Cin

Add_Sub4
CB Y3 Y2 Y1 Y0

Y(3:0)

Block Diagram of an 4-bit Adder/Subtractor


The design of the 4-bit adder/subtractor is to be done by interconnecting four instances of a 1-bit adder/subtractor module. You are to create your own 1-bit full adder/subtractor symbol (FAS) using the Symbol Editor in the Xilinx Schematic Capture tool (see page 2). Note that the carry-in to the first 1-bit adder/subtractor should be connected to "logic 0" (GND symbol in Xilinx). The two 4-bit inputs will be implemented as two 4-bit input busses, and the 4-bit output will be implemented as a 4-bit output bus. An explanation of how to creating busses and use bus taps is given on page 3.An example of implementing input/output busses is shown in Figure 1 on page 4. Note that bus taps are used to pull individual wires off of the input or output bus (see page 3). Each individual wire that is pulled off of a bus must be given the appropriate name. For example, A(3) is the MSB of A(3:0). Although there are 512 combinations of input stimulus that we could apply (29 = 512), you are only responsible for the following eight hexadecimal patterns for M, A3..0 and B3..0: for adding (i.e. M=0) let 8 / 7, A / 8, 6 / D, E / E, and C / 4; for subtracting (i.e. M=1) let the A / B pairs be 9 / 5, D / E, 7 / 2, 6 / F and 1 / 9. These patterns of input can be put into the Test Bench Waveform tool as the example shown in Figure 2, on page 4. Be sure to set the radix to hexadecimal before inputting the stimulus values.

Deliverables: You are to draw the circuit using the Schematic Editor, then simulate it using the Simulator. Lastly, you are to get a printout of the results. You must turn (1) this cover sheet, followed by (2) a printout of the circuit from the Schematic Editor, followed by (3) a printout of the timing diagrams from ModelSim. Once you've verified the logic, you are to implement it and download it into the FPGA on the Digilab board. Connect input M to push button BTN0, connect inputs (A3..A0, B3..B0) to the 8 slide switches (SW7..SW0) respectively, connect the outputs (CB,Y3,Y2,Y1,Y0) to 5 LED's (LD4..LD0), respectively. Due Date: Tuesday, March 13, 2012
Combinational Logic Lab # 3 Page 1

{Tues. of week 8}

CECS 201

Digital Logic Design

2012 R. W. Allison

Creating User Defined Schematic Symbols


A powerful function of any design tool is the ability to take advantage of hierarchical design techniques. Software and hardware designers frequently build larger, more complex functions out of smaller, less complex building blocks. The Xilinx Schematic Editor allows us to do this by creating libraries of user defined symbols for logic functions not found in the standard set of symbols. In the previous lab, we created a 1-bit adder/subtractor circuit using gates. We now want to package this logic up as a symbol named (FAS). You will not have to redraw your schematic from the previous lab; you merely will add it as a source file to lab4 (below left). In the Add Existing Sources dialog box, specify what directory your 1-bit adder schematic is in and select the sch file (e.g. FAS.sch shown below). Then click the Open button.

Now create a New Source schematic file to create the new 4-bit adder/subtractor (if you have not already done so). Once you are within the Xilinx Schematic Editor to create/edit the 4-bit adder/subtractor, open up the other FAS.sch schematic file. You will now have two files open in the Schematic Editor. The new user defined symbol that we are going to create will be within the new 4-bit adder/subtractor schematic. From within the schematic editor select the Symbol Wizard option from the Tools menu. Select the Using Schematic option for Pin Name Source, then choose the name of your 1-bit adder/subtractor schematic from the pull down menu (see right). Then click the Next button. The FAS symbol will automatically be created for you (click the Next button on next two dialog boxes and the Finish button on the last one). You should now be able to see the block diagram of your new user defined symbol (e.g. fas.sym). Close the Symbol Wizard.

To instantiate your 1-bit adder/subtractor within the 4-bit adder/subtractor circuit, you simply go to the Symbols tab in the Schematic Editor, and look for the name of your new symbol, select it and drop four instances into your schematic just like any other gate or logic element that youve used before.

Combinational Logic Lab # 3 Page 2

CECS 201

Digital Logic Design

2012 R. W. Allison

Busses
Buses are a convenient way to group related signals. However, buses can be any group of signals, related or not. This grouping produces a less cluttered, functionally clearer drawing and clarifies the connection between the main circuit and a block symbol. Buses are especially useful for the following: Routing a number of signals from one side of the schematic to the other Connecting more than one signal to a block signal using one I/O marker Bus taps allow you to take an individual net of a bus and connect it to a scalar pin on a symbol. You can also connect multiple nets from a bus or an entire bus to a bus pin on a symbol. In all cases, the number of signals and number of pins must match.

Creating Busses
A bus is a single wire that represents multiple nets. You create a bus by adding a net to a schematic, then promoting the net to a bus by naming the net using a bus specifier as described in this procedure. What to Do First Add a net to the schematic. To Create a Bus on a Schematic 1. Select Net Name from the Add menu, or click the Add Net Name toolbar button. The Options tab shows the Add Net Name Options. 2. In the Options tab, click Name the branch. 3. In the Name field, enter the name for the bus. The bus must be named according to the rules described in Bus Names. 4. Click the net to promote to a bus.

Connecting Nets to a Bus


A bus tap is the point at which signals enter or leave a bus. By adding a bus tap to a bus, connecting a wire to the bus tap, and giving the wire the proper net name, you can tap off one or more of the bus nets. What to Do First Create a bus in the schematic. To Connect Nets to a Bus 1. After selecting the Add Wire tool, select the Automatically add a bus tap option under the Options tab (shown at right) 2. Click on the terminal of the part you want to connect to the bus and then pull the wire to the bus you want to connect to. The Schematic tool will automatically add the bus tap. 3. Name the wire with the appropriate net name as described in Naming a Net or Naming a Bus. You can give the wire a name for a single net (for example, Addr(15)) or a name that specifies multiple nets (a sub-bus, for example, Data(15:8)).

Net Names for Nets Connected to a Bus


When you connect a net to a bus through a bus tap, these naming rules apply: If you are connecting to a bus named using sequential notation (for example, data(7:0) or address (31:0), the name for the net you are connecting must include parentheses or braces. The names data(3) or address(16) are valid; data3 or address16 are not. You can create a sub-bus by giving the net you are connecting a bus specifier for a name. For example, if you are connecting to a bus named data(3:0) you can connect two nets (and create a subbus) by naming the net data(1:0).

Combinational Logic Lab # 3 Page 3

CECS 201

Digital Logic Design

2012 R. W. Allison

Figure 1 Example of Using Input and Output Busses

Figure 2 Example of Inputting Hexadecimal Values into Test Bench Waveform Editor

Figure 3 Example of Resulting Simulator Waveforms


Combinational Logic Lab # 3 Page 4

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