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Pcirf 3 3 Mos 2

The document discusses modeling of MOS transistors including large-signal DC and small-signal AC models. It covers key topics such as effective channel length, finite output resistance in saturation due to channel length modulation, derivation of the ID equation accounting for channel length modulation, and definition of key small-signal parameters like transconductance and output conductance. It also discusses modeling of various MOS capacitor elements and the low-frequency small-signal model of a MOS transistor in saturation.

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Marius Ferdy
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117 views25 pages

Pcirf 3 3 Mos 2

The document discusses modeling of MOS transistors including large-signal DC and small-signal AC models. It covers key topics such as effective channel length, finite output resistance in saturation due to channel length modulation, derivation of the ID equation accounting for channel length modulation, and definition of key small-signal parameters like transconductance and output conductance. It also discusses modeling of various MOS capacitor elements and the low-frequency small-signal model of a MOS transistor in saturation.

Uploaded by

Marius Ferdy
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Agenda

MOS Transistor Modeling


Large-Signal DC Model Small-Signal AC Model MOS Capacitors

Drawn & Effective Channel Lengths


[Razavi]

Leff = Ldrawn 2 LD
The transistor gate overlaps both the source and drain region by a length of LD due to side diffusion in the fabrication process This results in the effective transistor gate length, Leff, being shorter than the drawn length, Ldrawn Throughout the remainder of the course, L will generally refer to Leff

Finite Output Resistance in Saturation


[Sedra/Smith]

In saturation, as VDS is increased the channel pinch-off point moves slightly towards the source This phenomenon is called channel-length modulation and is characterized by a parameter
5

Finite Output Resistance in Saturation


ID = =

nCox
2 2

W (VGS VTn )2 L L

nCox W

1 2 ( VGS VTn ) L 1 L L L (VGS VTn )2 1 + L

[Sedra/Smith]

nCox W
2 L

The current will increase slightly with VDS in saturation, resulting in a finite incremental output resistance Note, the channel-length modulation parameter is inversely proportional to L

L = VDS ID =

nCox W
2 L

VDS (VGS VTn )2 + 1

=
ID =

nCox W
2 L

(VGS VTn )2 (1 + VDS )


6

TAMU-474-08

J. Silva-Martinez

OUTPUT RESISTANCE (SATURATION REGION)


Channel Length Modulation
B S G D

IDS

Drain current

0
N+ P+ Lch Leff Depletion region substrate P+

VGS2

=0
VD
S

Channel length modulation is a second (unreliable) order effect! (Badly) Represented in SPICE by using or a more complex model. Simulated and experimental results might be off by more than 100%

iD

COX 2

W Leff

[VGS VT ]2 [1 + VDS ]

Measure this parameter!


-7-

MOS Large-Signal Output Characteristic with Finite Output Resistance


[Sedra/Smith]

Triode : I D = nCox

W (VGS VTn 0.5VDS )VDS L 2 L

Saturation : I D =

nCox W

(VGS VTn )2 (1 + VDS )


8

MOS Large-Signal Transfer Characteristic


[Sedra/Smith]

ID =

nCox W
2 L

(VGS VTn )2 (1 + VDS )

Impact of Bulk Voltage

ID =

nCox W
2 L

(VGS VTn ) (1 + VDS )


2

[Razavi]

VT = VT 0 +

2 F + VSB 2 F VT 0 VSB =0
10

Large-Signal DC Response

11

Large-Signal DC + Small-Signal AC Response

For small-signal analysis, we linearize the response about the DC operating point If the signal is small enough, linearity holds and the complete response is the summation of the large-signal DC response and the small-signal AC response
12

Low-Frequency Small-Signal Model


[Razavi]

13

Transconductance, gm
Transistor transfer characteristic is used to extract transconductance, gm
In Saturation (Neglecting Effects) ID = gm = iD vgs

COX W
2 Leff

(VGS VT )2
W Leff

COX
Q

(VGS VT )
Q

[Sedra/Smith]
14

Output Conductance, go
Transistor output characteristic is used to extract output conductance, go
In Saturation (Including Effects) ID = go = iD vds

COX W
2 Leff

(VGS VT )2 (1 + VDS )
W Leff

COX
Q

(VGS VT )2
Q

I D

[Sedra/Smith]
15

Body Transconductance, gmb


The small-signal drain current changes with VBS modulation due to changes in VT
[Razavi]
g mb i = D vbs
Q

In Saturation (Neglecting Effects) COX W [VGS VT ] Leff V * T vbs Q g m 2 2F + VSB Q

16

Low-Frequency Small-Signal Model


[Razavi]

gm =

iD v gs

COX
Q

W Leff

(VGS VT )
Q

i g0 = D vds g mb

C OX 2 COX

W 2 ( ) VGS VT Leff
Q

i = D vbs

W [VGS VT ] Leff

V * T vbs Q

g m 2 2 F + VSB Q

17

MOS Transistor Capacitances


[Razavi]

Gate - Channel Cap = CGC = WLeff Cox Channel - Bulk Cap = CCB = WLeff q Si N sub 4 F

Gate - Source Overlap (Fringing) Cap = CGSov = WCov Note, Cov Cox LD Gate - Drain Overlap (Fringing) Cap = CGDov = WCov Source - Bulk Junction Cap = CSBJ = AS C j + PS C jsw Drain - Bulk Junction Cap = CDBJ = ADC j + PDC jsw Cj = C j0 VBX 1 + B
m

C jsw =

C jsw 0 VBX 1 + B
msw

18

MOS Transistor Capacitances (Off)


[Razavi]

Gate - Drain Cap = CGD = CGDov = WCov Gate - Source Cap = CGS = CGDov = WCov Gate - Bulk Cap = CGB = CGC CCB CGC + CCB

Drain - Bulk Cap = CDB = CDBJ Source - Bulk Cap = CSB = CSBJ

19

MOS Transistor Capacitances (Triode)


[Razavi]

1 Gate - Drain Cap = CGD = CGDov + CGC 2 1 Gate - Source Cap = CGS = CGSov + CGC 2 Gate - Bulk Cap = CGB 0 1 Drain - Bulk Cap = CDB = CDBJ + CCB 2 1 Source - Bulk Cap = CSB = CSBJ + CCB 2

20

MOS Transistor Capacitances (Saturation)


[Razavi]

Gate - Drain Cap = CGD = CGDov 2 Gate - Source Cap = CGS = CGSov + CGC 3 Gate - Bulk Cap = CGB 0 Drain - Bulk Cap = CDB = CDBJ 2 Source - Bulk Cap = CSB = CSBJ + CCB 3

21

MOS Gate Capacitors Response


Note, Cov Cox LD

[Razavi]

22

MOS Source & Drain Junction Capacitors


[Razavi]
AS = AD = WE PS = PD = 2(W + E ) Junction CSB = CDB = AC j + PC jsw = WEC j + 2(W + E )C jsw

23

Source/Drain Junction Perimeter Caps Disclaimer


Note, there is some ambiguity on how to model the source/drain junction perimeter (sidewall) capacitance on the side of the gate
This is due to the channel occupying a portion of the sidewall area Different textbooks present different approaches

The Razavi text conservatively assumes that the sidewall perimeter capacitance is the same on all sides The Johns/Martin text (used in 2010) optimistically sets the sidewall perimeter cap to zero under the gate The correct answer is somewhere in the middle This semester I will follow the Razavi method and assume that the sidewall perimeter capacitance is the same on all sides (even under the gate)
I will try to make it clear on any problem description
24

MOS Source & Drain Junction Capacitors


[Razavi]
AS = AD = WE PS = PD = 2(W + E ) Junction CSB = CDB = AC j + PC jsw = WEC j + 2(W + E )C jsw

Folding into 2 fingers & sharing drain


W AS = 2 E = WE 2 AD = W E 2

Folding into 2 fingers

W PS = 2 2 + E 2 W PD = 2 + E 2

Folding the transistor allows for approximately half the drain junction capacitance with a small increase in source junction capacitance

Junction CSB = AS C j + PS C jsw = WEC j + 2(W + 2 E )C jsw Junction CDB = ADC j + PDC jsw = W EC j + (W + 2 E )C jsw 2

25

TAMU-474-08

J. Silva-Martinez

Other resistors: Source/Drain


Drain/Source Resistance

D/S

Drain/Source Resistance In addition to the contact resistance , the diffusion resistance has to be considered.

iD

P+

Top view LR
iD

LR (R[] ) Rseries = W LR Rseries = W t


W
In SPICE, R[] is defined as RSH

- 26 -

TAMU-474-08

J. Silva-Martinez

Small Signal Model (Saturation region)


D G Cgs S Cbs B
i gm = D v gs g0 = iD vds COX
Q

B Cdb gmvg
s

Cg
d

D gmbvbs go
ID =

COX W
2 Leff

[VGS VT ]2 [1 + VDS ]
2F + VSB 2F

S
Small signal model (saturation region)

VT = VT 0 + iD

]
+
Q

COX W
2 Leff

[VGS VT ]2 [1 + VDS ]

W Leff

(VGS VT )
Q

i iD i vgs + D vds + D vbs vgs Q vds Q vbs Q

C OX 2 COX

W 2 ( VGS VT ) Leff
Q

i D I D +g m v gs +g 0 v ds +g mb v bs
g m 2 2 F + VSB Q
- 27 -

g mb =

iD vbs

W [VGS VT ] Leff

V * T vbs Q

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