Scribd
Upload
203 views

Rort

The document describes the specifications, physical design, and physical design flow of a Cortex A9 Tri-core processor implementation. Key aspects include the gate count, size, timing status at different stages, and power optimization techniques used. Clock gating was employed to reduce clock tree power by up to 30% and total power by up to 10%, while improving performance up to 100MHz for GHz designs and reducing clock tree area by up to 30%.

Uploaded by

Pramod Reddy R
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
203 views

Rort

The document describes the specifications, physical design, and physical design flow of a Cortex A9 Tri-core processor implementation. Key aspects include the gate count, size, timing status at different stages, and power optimization techniques used. Clock gating was employed to reduce clock tree power by up to 30% and total power by up to 10%, while improving performance up to 100MHz for GHz designs and reducing clock tree area by up to 30%.

Uploaded by

Pramod Reddy R
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 7

Cortex A9 Tri-core Implementation

Specifications of the Processor: (Key Features) Functions (abilities) of the Design: Different modules in the design and its functions (in Brief) DMIPS of Processor Effective Speed of the Processor L1 and L2 access speed (cache coherent interconnect) Size of L1 and L2 memories. Working of tag memories (module)

Physical Design Predictions: Design Size and Physical Design Observations: Gate Count: /india/proj_es2Arm/explore/pd/ca9/Run1_Pra7july_dwtsCcopt/checknetlist.rpt Instance Count: Vt flavors in Netlist: Netlist Timing Status: /india/proj_es2Arm/explore/pd/ca9/Run4_Pra9july_ShieldCcopt/LOG/../nk_rpt/prePlac e/cortex_a9_mp_pl310_prePlace.summary Number of macros: Macro Area: Number of Pins: Size of the Cores: Max Logic Depth Average Logic Depth Critical Paths in Synthesis and the Logic depth Clock gating percentage

Physical Design Flow: 1. FloorPlan: Macro size and Placement Channel width Cpu core placement Pin Placement Reason for Rectilinear shape of both core and the wrapper (advantages)

2. Power Planning: Stripe Width Stripe spacing Layers used for stripes

3. Placement and Prects Opt Obtain module interaction Details Placement of the Modules with manual guidance. Set the required margins, max cap, and max trans values. Optimize incrementally using giga opt. Trial route the design and check Timing MMMC flow setup and usage Advantages by EDI Special settings of switches Timing Status and cells added Density and congestion status

4. CTS Clock Architecture (total no. clocks and architectural clock gates) Criticality in clock tree CCopt usage for cts Advantage of CCopt Timing status, Number of cells added NDR used, max trans, max cap Levels of clock tree. Placement and routing congestion status

5. Post CTS Post Cts optimization using giga opt engine and use NRGR. Control the max length of the nets Timing status, margins added and cell count increase. Status of routing congestion. 6. Route and Post Route Resources for routing. Criticality Nano router and giga opt optimizer usage. Timing Status DRC count (EDI vs Sign off) PDV status. Signal EM status. MMMC timing status

7. Timing Sign off (ECO MMMC) ETS and EDI correlation DMMMC flow in ETS to fix all mode all corner timing Top Level Integration ECO round.

Init Stage: MMMC flow: Timing Corners Cworst: 125 Cbest: -40

Timing Modes:

Dft mbist Dft_scan_shift Dft scan capture

Max Route Layer 8 Min route layer 1 <FF> ============================================== <FF> Derating Factors

<FF> ============================================== <FF> INFO: max: <FF> INFO: data_cell_early = 0.975 <FF> INFO: clock_cell_early = 0.920 <FF> INFO: data_cell_late = 1.025 <FF> INFO: clock_cell_late = 1.025 <FF> INFO: min: <FF> INFO: data_cell_early = 0.975 <FF> INFO: clock_cell_early = 0.975 <FF> INFO: data_cell_late = 1.025 <FF> INFO: clock_cell_late = 1.080

<FF>

Extraction Options

<FF> ----------------------------------------------------<FF> Relative C Threshold = 0.03 <FF> Total C Threshold = 0

<FF> Coupling C Threshold = 3 <FF> ----------------------------------------------------<FF> Signal Integrity Options

<FF> ----------------------------------------------------<FF> Process = 40

<FF> Delta Delay Threshold = -1 <FF> Celtic Settings = set_virtual_attacker -mode current -gtol 0 -switch_prob 1 -skiptw; set_parm gtol 0.025 ; set_align_mode -mode peak ; set_thresh -delta_absolute 0

setTrialRouteMode -useNanoRoute true setPlaceMode -maxDensity 0.95 setNanoRouteMode -drouteAutoStop false -routeWithSiDriven true -routeWithTimingDriven true setNanoRouteMode -routeStrictlyHonorNonDefaultRule true setOptMode -maxLength 400

------ Design Summary: Total Standard Cell Number (cells) : 387277 Total Block Cell Number (cells) : 67

Total I/O Pad Cell Number (cells) : 0 Total Standard Cell Area Total Block Cell Area Total I/O Pad Cell Area ( um^2) : 1316979.30 ( um^2) : 9138890.42 ( um^2) : 0.00

------ Design Statistics:

Number of Instances Number of Nets

: 387344 : 1173300

Average number of Pins per Net : 1.14 Maximum number of Pins in Net : 59410

------ I/O Port summary

Number of Primary I/O Ports : 1760 Number of Input Ports Number of Output Ports : 954 : 806

Number of Bidirectional Ports : 0 Number of Power/Ground Ports : 2 Number of Floating Ports *: 65

Number of Ports Connected to Multiple Pads *: 0 Number of Ports Connected to Core Instances : 1695

specifySelectiveBlkgGate cell set_max_transition 0.2 [current_design] set_max_fanout 32 [current_design]

Uncertainity 150ps createSoftGuide

setPlaceMode -softGuideStrength high setNanoRouteMode -drouteMinLengthForWireSpreading 250 -droutePostRouteSpreadWire true

setPlaceMode -clkGateAware true setPlaceMode -groupFlopToMacro true setPlaceMode -groupFlopToMacroLevel 1 setPlaceMode -groupFlopToMacroStrength 500 ################sh######################## setPlaceMode -groupFlopToGate true setPlaceMode -groupFlopToGateHalfPerim 200

Power: Clock tree power reduction up to 30%, and total power reduction up to 10% Performance: Improvements up to 100 MHz for a GHZ design Area: Clock tree area reduction up to 30%

You might also like