Section 12.

Input Capture
HIGHLIGHTS
This section of the manual contains the following major topics: 12.1 Introduction .................................................................................................................. 12-2 12.2 Input Capture Registers ............................................................................................... 12-3 12.3 Capture Event Generation ........................................................................................... 12-4 12.4 Capture Buffer Operation............................................................................................. 12-6 12.5 Input Capture Interrupts ............................................................................................... 12-8 12.6 Input Capture Operation in Power-Saving States ...................................................... 12-12 12.7 I/O Pin Control ........................................................................................................... 12-12 12.8 Register Maps............................................................................................................ 12-13 12.9 Design Tips ................................................................................................................ 12-14 12.10 Related Application Notes.......................................................................................... 12-15 12.11 Revision History ......................................................................................................... 12-16

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12.1 INTRODUCTION
This section describes the Input Capture module and its associated operational modes. The Input Capture module is used to capture a timer value from one of two selectable time bases on an event on an input pin. The input capture features are quite useful in applications that require frequency (time period) and pulse measurement. Figure 12-1 is a simplified block diagram of the Input Capture module. The Input Capture module has multiple operating modes. The operating modes are selected via the Input Capture Control (ICxCON) register and include: Capture timer value on every falling edge of the input applied at the ICx pin Capture timer value on every rising edge of the input applied at the ICx pin Capture timer value on every 4th rising edge of the input applied at the ICx pin Capture timer value on every 16th rising edge of the input applied at the ICx pin Capture timer value on every rising and every falling edge of the input applied at the ICx pin Device wake-up from Sleep and Idle mode on the rising edge of the input applied at the ICx pin

The Input Capture module has a four-level First-In First-Out (FIFO) buffer. The user application can select the number of capture events required to generate a CPU interrupt. Note: Each dsPIC33F device variant has one or more Input Capture modules. An x used in the names of pins, control/status bits and registers denotes the particular Input Capture module number. For more details, refer to the specific device data sheets.

Figure 12-1:

Input Capture Block Diagram

ICM<2:0> Prescaler Mode (16th Rising Edge)

101

Prescaler Mode (4th Rising Edge)

TMR2 100 ICTMR

TMR3

Rising Edge Mode ICx pin 011 Capture Event FIFO CONTROL To CPU

Falling Edge Mode 010

ICxBUF FIFO

Edge Detection Mode

ICI<1:0> 001

ICM<2:0>

/N Sleep/Idle Wake-up Mode 001 111

Set Flag ICxIF (in IFSx Register)

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12.2 INPUT CAPTURE REGISTERS
Each capture channel available on dsPIC33F family devices has these registers: ICxCON: Input Capture Control register ICxBUF: Input Capture Buffer register Register 12-1: U-0 bit 15 R/W-0 ICTMR bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 HC = Cleared in Hardware W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown R/W-0 R/W-0 ICI<1:0> R-0, HC ICOV R-0, HC ICBNE R/W-0 R/W-0 ICM<2:0> bit 0 ICxCON: Input Capture x Control Register U-0 R/W-0 ICSIDL U-0 U-0 U-0 U-0 U-0 bit 8 R/W-0

Unimplemented: Read as 0 ICSIDL: Input Capture x Stop in Idle Control bit 1 = Input capture halts in CPU Idle mode 0 = Input capture continues to operate in CPU Idle mode Unimplemented: Read as 0 ICTMR: Input Capture x Timer Select bit 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICBNE: Input Capture x Buffer Empty Status Flag bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty ICM<2:0>: Input Capture x Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (Input Capture module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge rising and falling (the ICI<1:0> bits do not control interrupt generation for this mode) 000 = Input capture module turned off

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Input Capture

bit 12-8 bit 7

bit 6-5

bit 4

bit 3

bit 2-0

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12.3 CAPTURE EVENT GENERATION
12.3.1 Timer Selection

Each dsPIC33F family device has one or more input capture channels. Each channel can select between Timer2 and Timer3 for its time base. Selection of the timer resource is accomplished through the Input Capture Timer Select (ICTMR) bit in the Input Capture Control (ICxCON<7>) register. This timer can be set using the internal clock source (FOSC/2), or an external clock source applied at the TxCK pin.

12.3.2

Input Capture Event Modes

The Input Capture module captures the 16-bit value of the selected timer (Timer2 or Timer3), when a capture event occurs. A capture event is defined as a write of a timer value into the capture buffer. The Input Capture modes are configured by setting the appropriate Input Capture Mode (ICM<2:0>) bits in the Input Capture Control (ICxCON<2:0>) register. Table 12-1 lists the Input Capture mode and capture events for the different bit settings. The user application must disable the Input Capture module (i.e., ICM<2:0> = 000) before changing a capture mode. Figure 12-2 illustrates the capture events for various capture modes. Table 12-1: ICM<2:0> Value 000 001 010 011 100 101 110 111 Input Capture Modes Input Capture Mode Module disabled Edge Capture mode Falling Edge mode Rising Edge mode Prescaler mode (divided by 4) Prescaler mode (divided by 16) Unused (module disabled) Sleep/Idle Wake-up mode Capture Event Generation On both rising and falling edge of the capture input signal On the falling edge of the capture input signal On the rising edge of the capture input signal On every 4th rising edge of the capture input signal On every 16th rising edge of the capture input signal No capture event

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Section 12. Input Capture

Figure 12-2: Input Capture Event Generation
ICx Pin

Capture Event (Rising Edge Mode)

Capture Event (Falling Edge Mode)

Capture Event (Edge Detection Mode)

Capture Event (Prescaler Mode - /4)

Note 1: The input capture pin has minimum high time and low time specifications. For details, refer to the specific device data sheet. 2: The latency from the time the transition happens at the Input Capture (ICx) pin to the time the capture event is generated is two instruction cycles.

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12.4 CAPTURE BUFFER OPERATION
The Input Capture module can select Timer2 or Timer3 as its time base. The selected timer value is captured and stored in a four-deep FIFO buffer on every capture event as shown in Figure 12-3. The ICxBUF register provides access to the FIFO buffer as it is memory mapped. Two status flags are associated with the FIFO buffer: Input Capture x Buffer Empty Status (ICBNE) flag Input Capture x Overflow Status (ICOV) flag These status flags are cleared: On any device Reset When the module is disabled by the Input Capture Mode Selection (ICM<2:0>) bits

12.4.1

Input Capture Buffer Not Empty (ICBNE)

The ICBNE read-only status bit (ICxCON<3>) is set on the first input capture event and remains set until all capture events are read from the capture buffer. For example, if three capture events occurr, then three reads of the capture buffer are required before the ICBNE (ICxCON<3>) bit is cleared. Similarly, if four capture events occur, four reads are required to clear the bit. Each read of the capture buffer allows the remaining word(s) to move to the next available top location.

12.4.2

Input Capture Overflow (ICOV)

The ICOV read-only status (ICxCON<4>) bit is set when the capture buffer overflows. In the event that the buffer is full with four capture events, and a fifth capture event takes place before the buffer is read, an overrun condition occurs, and the ICOV (ICxCON<4>) bit is set to logic 1. To clear the overrun condition, the capture buffer must be read four times. Upon the fourth read, the ICOV (ICxCON<4>) status flag is cleared. The capture event does not write timer values into the FIFO buffer when it is full.

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Section 12. Input Capture

Figure 12-3: Timer Value Capture
Timer is Reset on Period Match

500 400 TMR2 300 or TMR3 200 100

Capture Event

1st Capture

2nd Capture 100 200 xxxx xxxx

3rd Capture 100 200 300 xxxx

Capture FIFO

100 xxxx xxxx xxxx

4th Capture 100 200 300 400

5th Capture 100 200 300 400

ICBNE Flag is set

ICOV Flag is set

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Input Capture

Note 1: The latency from the time the transition happens at the capture input (ICx pin) to the time the capture event is generated is two instruction cycles. 2: The Overflow flag remains cleared in Edge Detect Mode (ICM = 0b001).

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12.5 INPUT CAPTURE INTERRUPTS
The input capture channel can generate an interrupt based upon the selected number of capture events, as illustrated in Figure 12-4. The number of events is set by the Input Capture Interrupt (ICI<1:0>) bits in the Capture Control (ICxCON<6:5>) register, as provided in Table 12-2. The user application must disable the Input Capture module (ICM<2:0> = 000) before changing the ICI<1:0> bits. When the capture interrupt is generated on every capture event (ICI<1:0> = 00), the FIFO overflow condition does not inhibit the capture interrupt. If the capture interrupt is not generated on every capture event, the FIFO overflow condition inhibits the capture interrupt. Therefore, all the captured values must be read from the capture buffer on every capture interrupt. For example, if the capture interrupt is generated on every second capture event (ICI = 01), the capture buffer must be read two times. Similarly, if the capture interrupt is generated on every third capture event (ICI = 10), the capture buffer must be read three times. Note: In Edge Detection Mode (ICM = 001), the interrupt is generated on every capture event and the Input Capture Interrupt (ICI<1:0>) bits are ignored. Input Capture Interrupt Selection Input Capture Interrupt Generation Interrupt on every capture event Interrupt on every second capture event Interrupt on every third capture event Interrupt on every fourth capture event

Table 12-2:

ICI<1:0> Value 00 01 10 11 Figure 12-4: Input Capture Interrupt Generation

Capture Event

Capture Interrupt (ICI<1:0> = 0b00)

Capture Interrupt (ICI<1:0> = 0b01)

Capture Interrupt (ICI<1:0> = 0b10)

Capture Interrupt (ICI<1:0> = 0b11)

Note:

Each input capture channel has interrupt flag status bits (ICxIF), interrupt enable bits (ICxIE) and interrupt priority control bits (ICxIP<2:0>). For further information on peripheral interrupts, refer to Section 6. Interrupts.

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12.5.1 Code Example for Period Measurement

The following code example shows the time period measurement using the Input Capture module. The capture event is generated on every rising edge and the capture interrupt is generated after taking two time stamps for period measurement, as illustrated in Figure 12-5. Example 12-1: Capture Code Example
// // // // Disable Input Capture 1 module Select Timer2 as the IC1 Time base Interrupt on every second capture event Generate capture event on every Rising edge

// Initialize Capture Module IC1CONbits.ICM= 0b00; IC1CONbits.ICTMR= 1; IC1CONbits.ICI= 0b00; IC1CONbits.ICM= 0b001; // Enable Capture Interrupt And Timer2 IPC0bits.IC1IP = 1; IFS0bits.IC1IF = 0; IEC0bits.IC1IE = 1;

// Setup IC1 interrupt priority level // Clear IC1 Interrupt Status Flag // Enable IC1 interrupt

// Capture Interrupt Service Routine unsigned int timePeriod= 0; void __attribute__((__interrupt__)) _IC1Interrupt(void) { unsigned int t1,t2; t2=IC1BUF; t1=IC1BUF; IFS0bits.IC1IF=0; if(t2>t1) timePeriod = t2-t1; else timePeriod = (PR2 - t1) + t2 }

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Figure 12-5: Time Period Measurement

V2 TMR2 or TMR3 V1

V3 V4

ICx

Capture Event

Capture Interrupt (ICI<1:0> = 01) Read captured Value in ISR

V1 xxxx xxxx xxxx 1st Capture V1 V2 xxxx xxxx 2nd Capture V3 V2 xxxx xxxx 3rd Capture

Read captured Value in ISR

V3 V4 xxxx xxxx 4th Capture

Capture FIFO

Note:

In this illustration, the Timer ramp is not to scale.

12.5.2

Input Capture Operation with DMA

Some dsPIC33F family devices include a Direct Memory Access (DMA) module, which allows data to be transferred from the Input Capture module to data memory without CPU intervention. Consult the specific dsPIC33F device data sheet to see if DMA is present on your particular device. For more information on the DMA module, refer to Section 22. Direct Memory Access (DMA). When the Input Capture module and DMA channel are appropriately configured, the Input Capture module issues a DMA request for every capture event. The DMA transfers data from the Input Capture Buffer (ICxBUF) register into RAM, and issues a CPU interrupt after a predefined number of transfers. The DMA channel must be initialized with the following: The DMA Request Source Selection (IRQSEL<6:0>) bits in the DMA Request (DMAxREQ<6:0>) register must select the DMA transfer request from Input Capture module The DMA Channel Peripheral Address (DMAxPAD) register must be initialized with the address of the Input Capture Buffer (ICxBUF) register The Transfer Direction (DIR) bit in DMA Control (DMAxCON<13>) register must be cleared. In this condition, data is read from the peripheral and written to the dual port DMA memory In addition, the input capture interrupt bits must be cleared (ICI<1:0> = 00) to generate DMA request for every capture event.

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Section 12. Input Capture

Example 12-2 provides sample code that transfers the capture values to RAM with DMA. DMA Channel 0 is set up for the Input Capture module with the following configuration: Example 12-2: Transfer data from the Input Capture module to RAM One-shot operating mode Register Indirect with Post-Increment addressing Single buffer 256 transfers per buffer Transfer words

Input Capture with DMA

// // // // Disable Input Capture 1 module Select Timer2 as the IC1 Time base Interrupt on every second capture event Generate capture event on every Rising edge

// Initialize Capture Module IC1CONbits.ICM = 0b00; IC1CONbits.ICTMR = 1; IC1CONbits.ICI = 0b00; IC1CONbits.ICM = 0b001; Setup DMA for Input Capture:

// Define Buffer in DMA RAM unsigned int BufferA[256] __attribute__((space(dma))); DMA0CONbits.AMODE = 0b00; // Register indirect with post increment DMA0CONbits.MODE = 0b01; // One Shot, Ping-Pong mode Disabled DMA0CONbits.DIR = 0; // Peripheral to RAM DMA0PAD = (int)&IC1BUF; // Address of the capture buffer register DMA0REQ = 1;// Select IC module as DMA request source DMA0CNT = 255; // Number of words to buffer DMA0STA = __builtin_dmaoffset(&BufferA); IFS0bits.DMA0IF = 0; IEC0bits.DMA0IE = 1; DMA0CONbits.CHEN = 1; Setup DMA Interrupt Handler void __attribute__((__interrupt__)) _DMA0Interrupt(void) { // Process the captured values IFS0bits.DMA0IF = 0; } // Clear the DMA0 Interrupt Flag // Clear the DMA interrupt flag bit // Enable DMA interrupt enable bit

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Input Capture

12.5.3

Capture Pin as External Interrupt

The Input Capture (ICx) pin can be used as an auxiliary external interrupt source by clearing the Input Capture Interrupt (ICI = 00) bits. In this condition an interrupt is generated on every capture event, and the FIFO overflow condition does not inhibit the capture interrupt. Consequently, the input capture buffer need not be read in the Capture Interrupt Service Routine (ISR). The Input Capture Mode (ICM<2:0>) bits can be used to select the edge polarity for the interrupt.

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12.6 INPUT CAPTURE OPERATION IN POWER-SAVING STATES
12.6.1 Input Capture Operation in Sleep Mode

The Input Capture module does not operate when the device is in Sleep mode. In Sleep mode the Input Capture (ICx) pin can only function as an external interrupt source for wake-up. This mode is enabled by setting the Input Capture Mode bits (ICM<2:0> = 111). In this mode, if the input capture interrupt is enabled, a rising edge on the capture pin generates capture interrupt. The capture interrupt wakes up the device from Sleep, and the following occurs: If the assigned priority for the interrupt is less than, or equal, to the current CPU priority, the device wakes up and continues code execution from the instruction following the PWRSAV instruction that initiated Sleep mode. If the assigned priority level for the interrupt source is greater than the current CPU priority, the device wakes up and the CPU exception process begins. Code execution continues from the first instruction of the capture ISR.

12.6.2

Input Capture Operation in Idle Mode

When the device enters Idle mode, the system clock sources remain functional and the CPU stops executing code. The Input Capture Stop-in Idle (ICSIDL) bit selection in the Input Capture Control (ICxCON<13>) register determines if the module stops in Idle mode or continues to operate in Idle mode. If ICSIDL = 0 (ICxCON<13>), the module continues to operate in Idle mode, providing full functionality of the Input Capture module, including the 4:1 and 16:1 prescaler capture settings. The prescaler capture settings are defined by control bits ICM<2:0> (ICxCON<2:0>). These modes require that the selected timer is enabled during Idle mode as well. If ICSIDL = 1 (ICxCON<13>), the module stops in Idle mode. The module performs the same functions when stopped in Idle mode as for Sleep mode (refer to Section 12.6.1 Input Capture Operation in Sleep Mode).

12.7

I/O PIN CONTROL

When the Input Capture module is enabled, the user application must ensure that the I/O pin direction is configured for an input by setting the associated TRIS bit. The pin direction is not set when the Input Capture module is enabled. All other peripherals multiplexed with the input pin must be disabled.

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12.8

REGISTER MAPS
The summaries of the registers associated with the dsPIC33F Input Capture module are provided in Table 12-3.

Input Capture

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Table 12-3:
File Name ICxBUF ICxCON Legend:

Input Capture Register Map

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000

Input Capture x Register ICSIDL ICTMR

x = unknown value on Reset, = unimplemented, read as 0. Reset values are shown in hexadecimal.

Table 12-4:
File Name TMR2 TMR3 PR2 PR3 T2CON T3CON Legend:

Timer Register Map

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx FFFF FFFF TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T32 TCS TCS 0000 0000

Timer2 Register Timer3 Register Period Register 2 Period Register 3 TON TON TSIDL TSIDL

Preliminary
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x = unknown value on Reset, = unimplemented, read as 0. Reset values are shown in hexadecimal.

Table 12-5:
File Name IFS0 IFS1 IFS2 IEC0 IEC1 IEC2 IPC0 IPC1 IPC5 IPC9 IPC10 Legend:

Interrupt Controller Register Map

Bit 15 Bit 14 Bit 13 IC8IP<2:0> IC5IP<2:0> Bit 12 Bit 11 Bit 10 Bit 9 IC7IP<2:0> IC4IP<2:0> Bit 8 IC6IF IC6IE Bit 7 IC8IF IC5IF IC8IE IC5IE Bit 6 IC7IF IC4IF IC7IE IC4IE Bit 5 IC2IF IC3IF IC2IE IC3IE IC1IP<2:0> IC2IP<2:0> IC3IP<2:0> Bit 4 Bit 3 Bit 2 Bit 1 IC1IF IC1IE IC6IP<2:0> Bit 0 All Resets 0000 0000 0000 0000 0000 0000 4444 4440 4440 4440 4440

Section 12. Input Capture

= unimplemented, read as 0. Reset values are shown in hexadecimal.

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12.9 DESIGN TIPS
Question 1: Answer: Can the Input Capture module be used to wake the device from Sleep mode? Yes. When the Input Capture module is configured to ICM<2:0> = 111 and the respective channel interrupt enable bit is set (ICxIE = 1), a rising edge on the capture pin wakes up the device from Sleep mode (refer to Section 12.6 Input Capture Operation in Power-Saving States).

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12.10 RELATED APPLICATION NOTES
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC33F device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Input Capture module are: Title Using the CCP Module(s) Implementing Ultrasonic Ranging Application Note # AN594 AN597

Note:

For additional application notes and code examples for the dsPIC33F family of devices, visit the Microchip web site (www.microchip.com).

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12.11 REVISION HISTORY
Revision B (April 2007)
This is the initial release of this document.

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