feature | Next Generation SerDes Design

Signal Integrity Simulation of PCI Express Gen 2 Channel

Guest Author Jason Boh, Agilent Technologies
Overview
In the electronics industry, there has been an architectural shift over the past several years from parallel bus interfaces to serial communication links. The benefits of employing serial links over parallel I/O schemes include fewer device pins, reduced board space requirements, smaller connectors, easier PCB layouts, and less susceptibility to noise. However, there are unique challenges associated with serial link design. The high data rate signals pose challenges previously only familiar to analog RF and microwave designers. Today, many existing serial I/O standards operate at multi-Gbps speeds. These standards are evolving, and the next generation versions of the standards aim to increase (or perhaps even double) the data rates achievable in a single lane. For example, PCI Express (PCIe) Gen 1 operates at 2.5 GT/s, while PCIe Gen 2 and PCIe Gen 3 are 5.0 GT/s and 8.0 GT/s, respectively. Further complicating things is the fact that high-speed serial links often require special data processing, such as SerDes (serializer/deserializer), equalization, and line coding (i.e. 8B10B or 64B66B). For multi-Gbps serial links, a robust approach to signal integrity simulation must be followed in order to avoid costly design iterations. Figure 1 illustrates a typical link, which consists of driver and receiver ICs, their packages, several connnectors, and PCBs. The passive components of the link are collectively called the channel. To ensure signal integrity, it is crucial to carefully design all aspects of these passive interconnects. At high data rates, it is critical that the channel simulation accurately takes into account the distributed nature and loss mechanisms of the transmission lines, coupling between the traces of differential pairs and any adjacent aggressors/victims, and impedance mismatches. A good practice is to create a virtual prototype of the entire link in a signal integrity EDA (electronic design automation) tool and simulate the eye diagram performance. To illustrate this design flow, a PCIe Gen 2 system, operating at 5 GT/s, is built and simulated in Agilents high-frequency/high-speed EDA tool called ADS (Advanced Design System).

Fast Channel Simulation

There is a new, easy to use tool in ADS 2009 called the Channel Simulator. It has huge benefits over traditional SPICE, such as dramatically faster simulation speed and capacity, easy and direct incorporation of S-parameter models, and efficient post processing for large numbers of simulated bits. Further, there is no sacrifice in accuracy in using the Channel Simulator, as long as the channel can be assumed to be an LTI (linear, time-invariant) system. Since all typical interconnects are passive and linear, this is a safe assumption, and classical transient simulation results will overlay perfectly with results from the Channel Simulator. Figure 2 shows a generalized block diagram of systems that can be rapidly analyzed using the Channel Simulator. It supports one transmitter (TX), any number of crosstalk sources (XTLK1, XTLK2, XTLKN), any arbitrary linear channel model, and a receiver (RX).

Figure 2. Generalized System Architecture Supported in the Channel Simulator

Figure 1. Typical High Speed Serial Link

The user has great flexibility in choosing the types of components to include in the channel model in ADS. This is an important feature, since signal integrity engineers tend to obtain models in many different formats. For example, connector vendors may supply their customers with S-parameter files, SPICE-equivalent circuit models, or even CAD models that need to be simulated in a 3D electromagnetic (EM) solver. The types of models that can be used to build the virtual channel prototype in ADS include S-parameter files, lumped RLC components, transmission lines, ADS multi-layer library models, HSPICE or Spectre netlists, W-elements, and dynamically-linked electromagnetic models (full 3D or planar). The channel model can even consist of a combination or arbitrary hierarchy of these different model types. When the Channel Simulator is used for a channel that contains models which happen to be constructed in the frequency domain, such as an S-parameter file or certain transmission line models, ADS will automatically invoke the convolution engine to create a casual, passive, and accurate impulse response in the time domain. This allows the user to easily mix time-domain and frequency-domain models.

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Next Generation SerDes Design | Jason Boh

Figure 3 shows a PCIe Gen 2 channel built in ADS. From left to right (ignoring the resistive and capacitive loads) there are a differential transmitter, package, via breakout, add-in card, connector, system board, via breakout, package, and an Eye Probe. This channel consists of a variety of model types. The via breakout is modeled by a single 8 port Touchstone S-parameter file. The 4 inch traces on the add-in card and the 12 inch traces on the system board are all modeled using the multilayer library in ADS. This library has the advantage of being fully parameterized and therefore easily tunable and optimizable, making it extremely useful for pre-layout what-if analysis of transmission lines and vias. For example, the system board and add-in card traces have parameters for length, width, spacing, and layer number. The package is modeled using a combination of coupled transmission lines and an 8 port S-parameter file for the BGA solder balls. Some of the parameters of the transmitter model are shown in Figure 5. A psuedo-random bit sequence (PRBS) is generated at a bit rate of 5 Gbps. The voltage levels and rise/fall times are set as shown. 8B10B encoding is enabled in the Encoder tab (not shown). For this first simple example, transmitter de-emphasis, random jitter, duty cycle distortion, and periodic jitter are all disabled, and there are no receivers or crosstalk sources present.

Figure 5.PRBS Parameters for Tx Model Figure 3. ADS Schematic for PCIe Gen 2 Channel Simulation

Additionally, a substrate definition component and a ChannelSim controller must be placed in the schematic, as shown in Figure 4. The most important purpose of the ChannelSim controller is to set the total number of bits that will be simulated. For most channels, simulations of tens of thousands of bits take less than 1 minute, and simulation of 1 million bits can be completed in only 1 to 2 minutes on a typical computer. The substrate definition component is used by the multi-layer library models and defines all the properties of the stack-up, such as the dielectric and metal thicknesses, their electrical properties, and the layer mappings. The Svensson/Djordjevic loss model is used such that the transmission lines will maintain causality in the time domain. All of the signal traces on the add-in card and board are mapped to Layer 1, which is defined as the signal layer. Directly below Layer 1 is the dielectric layer, and located below the dielectric is Layer 2, the ground layer. For this example, the stack up definition yields a simple microstrip configuration. However, the multi-layer library does support multiple signal, power, and ground layers.

The eye measurements that are available in the differential Eye Probe are shown in Figure 6. The selected measurements are Level 1, Level 0, Width, Height, and Density; therefore, these will be the outputs of the simulation. For convenience, there is graphical help for each of these measurements that appears when it is highlighted (see Figure 6, where the width measurement is highlighted and it shows graphical help). One of the reasons that the Channel Simulator is so efficient in post-processing data for tens of thousands or even millions of bits is that it utilizes these fast and efficient Eye Probes that save only the necessary data to disk.

Figure 6.Differental Eye Probe Measurements Figure 4. Substrate Definition and ChannelSim Controller

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Figure 7 shows the simulation results for the initial PCIe channel simulation. This includes the eye diagram plot and a table containing the rest of the measurements requested in the Eye Probe. Once Vshelf is found, the values for the cursor and post cursor tap coefficients are calculated using two equations. One equation is created by using the fact that tap coefficients are normalized, which implies that the difference between the cursor tap and the post cursor tap coefficient equals 1. The second equation is formulated by assuming the input bit sequence of two consecutive 1s will lead to a voltage equal to Vshelf. Solving the two equations and two unknowns in Figure 9 provides the two tap coefficients and achieves 6 dB de-emphasis.

Figure 7. Eye Digram Measurements for Initial PCIe Gen 2 Channel Simulation

Transmitter De-Emphasis
PCI Express uses transmit de-emphasis to compensate for high frequency channel losses. The PCIe standard defines two different levels of de-emphasis. One level is in the range of 3 to 4 dB, while the other is defined to be from 5.5 to 6.5 dB. For every channel, there is an optimum value of de-emphasis which provides the best possible performance. Simply using the maximum value of de-emphasis usually does not yield the optimum eye diagram. This optimum value can be determined using the ADS Channel Simulator, Eye Probes, and Batch Mode simulation capability. The Channel Simulator requires that transmit de-emphasis be defined in terms of FIR filter tap coefficients. Therefore, the corresponding tap coefficients for a specific value of de-emphasis must be calculated. A de-emphasized waveform is defined in terms of the voltage levels called Vshelf and Vswing. Vshelf is calculated first for a given level of de-emphasis, using the expression shown in Figure 8. For example, if the desired de-emphasis level is 6 dB, and Vswing is equal to 1 V, then Vshelf can be calculated as 0.5011872 V.

Figure 9. Calculating the Taps of the FIR Filter

As previously mentioned, each unique channel has some optimum amount of transmitter de-emphasis that will deliver the best eye performance. To find this optimum level, the method shown thus far will now be generalized. The value of de-emphasis is swept using Batch Mode simulation in ADS, while the eye diagram performance is concurrently measured using a fast Eye Probe. Several equations are added to the schematic page to calculate the tap coefficients for a given deemphasis level. These tap coefficients, called tap1 and tap2, are then fed into the transmitter model. The Batch Mode simulation controller is also added to the schematic in order to sweep transmit de-emphasis from 3 dB to 7 dB. Figure 10 shows the equations and the Batch Mode simulation controller.

Figure 10. Variables and Batch Controller for Finding Optimum De-Emphasis Level

Figure 8. Calculating Level of De-emphasis in dB

Once the simulation is complete, eye height and eye width are plotted as a function of de-emphasis level, as shown in Figure 11. The optimum value of de-emphasis is the crossover point between the two plots, as it provides a tradeoff between the value of eye height and eye width. The optimum de-emphasis level for this channel is thus found to be around 3.7 dB. The tap coefficient values needed to provide the 3.7 dB de-emphasis are calculated as 0.826565 and -0.173435. Using these tap settings in the transmitter, the channel is re-simulated and the eye diagram measurement results are shown in Figure 12. As expected, the eye width and height are improved, and they are equal to the target width and height that were found by the Batch Mode sweep of de-emphasis levels. The original channel simulation without using de-emphasis is also shown in Figure 12 as a side-by-side comparison.

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files, netlists, etc., in any simulation. In order to pick the best connector model performance from the channel simulation results, it is possible to simply plot the eye height and width and visually find the best trade-off (the crossover point) between the two figures of merit, as was done previously in finding the optimum de-emphasis level. However, this time lets instead define a new figure of merit called EyeOpening, and let it be equal to eye height multiplied by eye width. Figure 14 shows a plot of EyeOpening as a function of connector model. From this plot, Connector 3 is determined to provide the best eye performance for this particular channel.

Figure 11. Batch Mode Simulation for Finding Optimum Tx De-Emphasis Level

Figure 14. Channel Eye Diagram Results for 5 Different Connector Models

Including Electromagnetic Simulations

Figure 12. Eye Diagram Measurements With and Without 3.7 dB De-emphasis

Sweeping the Connector Model

It is a common requirement for signal integrity engineers to assess the performance of multiple variations of an interconnect so that design trade-offs can be made. For example, lets assume there are 5 candidate connectors which need to be compared. The 5 different connector S-parameter files are plotted in Figure 13. In order to keep the plots to a minimum, only the S-parameters which relate to the intended forward transmission path are plotted. None of the reverse paths or adjacent paths are plotted.

Figure 13. Connector S-Parameter Plots

All of the connector models are automatically and sequentially swapped using the Batch Mode simulation capability in ADS, which allows you to sweep across virtually any type of model parameter or file, such as different IBIS files, data

So far, the multi-layer library has been used to model the transmission lines on the add-in card, system board, and package. Using this library of models is extremely valuable for quick what-if pre-layout analysis. In order to include the most realistic package and PCB simulations possible, EM simulations are performed as a post-layout verification of the design. To illustrate this design flow, the package and add-in card models are replaced by dynamically-linked EM models. The layouts are imported from Cadence Allegro using the Allegro Design Flow Integration (Allegro DFI) tool, which is included in ADS. Using Allegro DFI for ADS, the differential traces, vias, power/ground planes, and stack-up information for the add-in card and BGA package are all easily imported into the layout environment in ADS for EM simulation. Figures 15 and 16 show the ADS layouts for the add-in card and BGA package, respectively. Once the CAD layouts are imported, they can be included directly in the schematic as a dynamically-linked EM component. What this means is that if there are any changes made to the ADS layout (for example, a change in the separation between two differential traces or a vias antipad diameter), then these changes will be reflected and accounted for in a new, accurate EM simulation automatically. In addition to adding the layouts to the channel simulation schematic, an asynchronous crosstalk source is added which will generate an unwanted aggressor signal at the same data rate as the transmitter. The crosstalk sources phase relationship to the Tx, the voltage levels, rise/fall times, and jitter are all user-controllable. If the phase relationship to the Tx is set to Random, then the crosstalk source is called asynchronous. Finally, a receiver model and an additional Eye Probe (placed at the output of the receiver) are added. The new schematic containing all of these changes is shown in Figure 17. The results of the final simulation of the PCIe Gen 2 channel include the effects of

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transmitter and receiver random jitter, crosstalk, and EM, and are shown in Figure 18.

Figure 18. Final PCIe Gen 2 Channel Simulation

Summary
Figure 15. Add-in Card

There are many design considerations for todays multi-Gbps serial links. Signal integrity designers need to quickly evaluate channel designs in order to make critical trade-offs. Traditional SPICE simulators have too many limitations on speed, capacity, and frequency-domain model support. A PCIe Gen 2 channel was simulated using the Channel Simulator in ADS, which has many advantages over classical SPICE tools. Transmitter de-emphasis and connector model selection were optimized for the channel by using Batch Mode simulations. Electromagnetic simulations of the package and add-in card were also included as a post-layout verification step.
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About the author Jason Boh is an applications engineer for Agilent EEsof EDA (www.agilent.com/ find/eesof) in the greater Boston area. He received his Masters Degree in Electrical Engineering from the University of South Florida, where he participated in the Wireless and Microwave Information Systems (WAMI) program. His areas of focus include high frequency analog circuit design and high speed digital signal integrity simulation.

Figure 16. High Speed BGA package

www.agilent.com Product specifications and descriptions in this document subject to change without notice. Agilent Technologies, Inc. 2009 Printed in USA, March 23, 2009 5990-3889EN
Figure 17.Channel Schematic with Actual CAD Layouts, Crosstalk Source, and Rx

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