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GATE Digital Electronics, Gate Digital Questions, Gate Exam Digital Electronics Questions Objective

1) The 2's complement representations of -25, -9, and -57 are 11001, 1001, and 111001 respectively. 2) The simplified logic function Y = A(B + C(AB + AC)’) is AB. 3) The minimum number of two-input NAND gates required to implement XY’+X’Y without X and Y complements is 5.

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407 views4 pages

GATE Digital Electronics, Gate Digital Questions, Gate Exam Digital Electronics Questions Objective

1) The 2's complement representations of -25, -9, and -57 are 11001, 1001, and 111001 respectively. 2) The simplified logic function Y = A(B + C(AB + AC)’) is AB. 3) The minimum number of two-input NAND gates required to implement XY’+X’Y without X and Y complements is 5.

Uploaded by

vlsijp
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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1.

11001, 1001 and 111001 correspond to the 2s complement representation of the


following set of numbers
(A) 25, 9 and 57 respectively
(B) -6, -6 and -6 respectively
(C) -7, -7 and -7 respectively
(D) -25, -9 and -57 respectively
2. The simplified form of a logic function Y = A(B + C(AB + AC)) is
(A) AB

(B) AB

(C) AB

(D) AB

3. If the X and Y logic inputs are available and their complements X and Y are not
available, the minimum number of two-input NAND required to implement XY+XY is
(A) 4

(B) 5

(C) 6

(D) 7

4. A logical function of four variables is given as f (A, B, C, D) = (A + B C) (B + CD). The


function as a sum of product is
(A) A + BC + ACD + BCD
(B) A + BC + ACD + BCD
(C) AB + BC + ACD + BCD
(D) AB + AB + ACD + BCD
5. What is the value of f1f2 =?

(A) x0 x1 x2

(B) x0

x1

x2

(C) 1

(D) 0

6. The MUX shown in fig. is 4 X 1 multiplexer. The output Z is

(A) ABC

(B)A

(C) AuBuC

(D) A + B + C

7. Four memory chips of 16 X 4 sizes have their address buses connected together. This
system will be of size
(A) 64 X 4

(B) 32 X 8

(C) 16 X 16

(D) 256 X 1

8. The address bus width of a memory of size 1024 X 8bits is


(A) 10 bits

(B) 13 bits

(C) 8 bits

(D) 18 bits

9. What is the value of f = ?

(A) wxyz + wxyz + xy + yz

(B) wxyz + wxyz + xy +yz

(C) wxyz + wxyz + yz + zx

(D) MUX is not enable

10. The 4to1 multiplexer shown in fig. implements the Boolean expression f (w, x, y, z) =
m( 4, 5, 7, 8, 10, 12, 15) The input to I1 and I3 will be

(B) y + z, y u z

(A) yz, y + z
(C) y + z, y

(D) x + y, y

11. The circuit shown in fig. is

(A) a MOD2 counter


(B) a MOD3 counter
(C) generate sequence 00, 10, 01, 00.....
(D) generate sequence 00, 10, 00, 10, 00 ......
12. The counter shown in the fig. has initially Q2Q1Q0 = 000. The status of Q2Q1Q0 after the
first pulse is

(A) 0 0 1

(B) 0 1 0

(C) 1 0 0

(D) 1 0 1

13. A 4 bit modulo6 ripple counter uses JK flip-flop. If the propagation delay of each FF is
50 ns, the maximum clock frequency that can be used is equal to
(A) 5 MHz

(B) 10 MHz

(C) 4 MHz

(D) 20 Mhz

14. A 4-bit right shift register is initialized to value 1000 for (Q3, Q2, Q1, Q0). The D input is
derived from Q0, Q2 and Q3 through two XOR gates as shown in fig. The pattern 1000
will appear at

A) 3rd pulse

(B) 7th pulse

(C) 6th pulse

(D) 4th pulse

15. To count from 0 to 1024 the number of required flip-flop is


(A) 10

(B) 11

(C) 12

(D) 13

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