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Analog and Digital CMOS Study Notes

The document discusses MOS switches and CMOS transmission gates. It provides details on: - The characteristics and properties of MOS switches, including symmetrical switching, resistance, and noise. - The voltage requirements for a MOS switch to operate properly between input signals ranging from 0-3V. - The I-V characteristics and on resistance of MOS switches as a function of gate voltage. - Factors that influence switch performance such as finite on/off resistance and charge injection. - The operation and advantages/disadvantages of CMOS transmission gates, which use complementary signals to provide bidirectional switching between nodes.

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87 views

Analog and Digital CMOS Study Notes

The document discusses MOS switches and CMOS transmission gates. It provides details on: - The characteristics and properties of MOS switches, including symmetrical switching, resistance, and noise. - The voltage requirements for a MOS switch to operate properly between input signals ranging from 0-3V. - The I-V characteristics and on resistance of MOS switches as a function of gate voltage. - Factors that influence switch performance such as finite on/off resistance and charge injection. - The operation and advantages/disadvantages of CMOS transmission gates, which use complementary signals to provide bidirectional switching between nodes.

Uploaded by

skumar_945094
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Analog and Digital CMOS IC Design

1. MOS SWITCH
SUMMARY OF MOS SWITCHES Symmetrical switching characteristics High OFF resistance Moderate ON resistance (OK for most applications) Clock feed thro gh is proportional to si!e of switch (") and in#ersely $roportional to switching capacitors% Complementary switches help increase dynamic range% &s power s pply red ces' switches (ecome more diffic lt to f lly t rn on% Switches contri( te a k)*C noise which folds (ack into the (ase(and% Switching Characteristics: Switch Properties:

MOS SWITCH VOLTAGE RA GES &ss me the MOS switch connects to circ its and the analog signal can #ary from + to ,-% "hat are the #oltages re. ired at the terminals of the MOS switch to make it work properly%

The bulk voltage must be less than or equal to zero to insure that the bulk-source and bulk-drain are reverse biased. The gate voltage must be greater than 5 + VT in order to turn the switch on. Therefore,

VBulk V V! 5 + VT

I-V CHARACTERISTICS OF THE MOS SWITCH "#$%& '( %haracteristics of the )'" "witch

MOS SWITCH ON RESISTANCE AS A FUNCTION OF VGS "#$%& '( *esistance of the )'" "witch

INFLUENCE OF SWITCH IMPERFECTIONS ON PERFORMANCE Finite ON /esistance Non0!ero charging and discharging rate%

Finite OFF C rrent

Charge Injection Sensitivity to Gate Signal Rate

Case 1 - Slow Fall Time:


1ate is in#erted as

Channel time constant small eno gh so that the charge on CHold is a(sor(ed (y VI ! "hen gate #oltage reaches VI "VT' the de#ice t rns off and feed thr occ rs #ia the o#erlap capacitance%

VG goes negati#e%

Case # - Fast Fall Time:


1ate is in#erted as

VG goes negati#e%

Fall rate is faster than the channel time constant so that feed thr occ rs #ia the channel capacitance onto CHold which is not a(sor(ed (y VI % Feed thr contin es when VG reaches VI "VT% )otal feed thr consists of that d e to (oth the channel capacitance and the o#erlap capacitances%

$ther Considerations:
So rce resistance effects the amo nt of charge shared (etween the drain and the so rce% )he ma2im m gate #oltage (efore negati#e transition effects the amo nt of charge in3ected%

C%$S S&ITCH'S 4)ransmission 1ate4

(dvantages 5%) 6arger dynamic range% 7%) 6ower ON resistance% )isadvantages -

5%) /e. ires complementary clock% 7%) /e. ires more area% )* (%IC R( G' +I%IT(TI$ S $F S&ITCH'S 00 M st ha#e s fficient -1S to gi#e a s fficiently low on resistance

,roo-lyn ,ridge '..ect


8f N0channel and $0channel de#ices are 9resisti#ely: scaled (i%e%' si!ed to ha#e the same cond ctance at e. i#alent terminal

conditions) the resistance #ers s #oltage (common mode) will appear as shown (elow%

VOLTAGE DOUBLER USE TO PROVIDE GATE OVERDRIVE


;2ample <

Operation:

Transmission Gates (Pass Gates)


The CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel The gate voltages applied to these two transistors are also set to e complementar! signals" #s s$ch, the CMOS TG operates as a idirectional switch etween the nodes # and % which is controlled ! signal C"

&f the control signal C is logic'high, i"e", e($al to VDD, then oth transistors are t$rned on and provide a low'resistance c$rrent path etween the nodes # and %"

&f, on the other hand, the control signal C is low, then oth transistors will e off, and the path etween the nodes # and % will e an open circ$it" This condition is also called the high'impedance state"

The inp$t node (#) is connected to a constant logic'high voltage, Vin = VDD. The control signal is also logic'high, th$s ens$ring that oth transistors are t$rned on" The o$tp$t node (%) ma! e connected to a capacitor, which represents capacitive loading of the s$ se($ent logic stages driven ! the transmission gate" )e will now investigate the inp$t'o$tp$t c$rrent'voltage relationship of the CMOS TG as a f$nction of the o$tp$t voltage *o$t" The drain'to'so$rce and the gate'to'so$rce voltages of the nMOS transistor are

Th$s, the nMOS transistor will e t$rned off for V!"t > VDD ' *Tn and will operate in the sat$ration mode for V0ut < VDD ' *Tn" The VDS and VGS voltages of the pMOS transistor are

Conse($entl!, the pMOS transistor is in sat$ration for V0ut < +*Tp+, and it operates in the linear region for V0ut > |VTp|" ,ote that, $nli-e the nMOS transistor, the pMOS transistor remains t$rned on, regardless of the o$tp$t voltage level *o$t This anal!sis has shown that we can identif! three operating regions for the CMOS transmission gate, depending on the o$tp$t voltage level" These operating regions are

The total c$rrent flowing thro$gh the transmission gate is the s$m of the nMOS drain c$rrent and the pMOS drain c$rrent"

we ma! devise an equivalent resistance for each transistor in this str$ct$re,

Com ining the e($ivalent resistance val$es fo$nd for the three operating regions, we can now plot the total resistance of the CMOS transmission gate as a f$nction of the o$tp$t voltage *o$t

The implementation of CMOS transmission gates in logic circ$it design $s$all! res$lts in compact circ$it str$ct$res which ma! even re($ire a smaller n$m er of transistors than their standard CMOS co$nterparts" ,ote that the control signal and its complement m$st e availa le sim$ltaneo$sl! for TG applications"

Domino CMOS Logic

+omino logic, ('*, logic

The circuits are classified into two main categories, i.e., static circuits and d-namic circuits. The static %)'" circuits are further divided into sub-categories such as classical .fullcom/lementar-0 %)'" circuits, transmission-gate logic circuits, /ass transistor logic circuits and cascade voltage switch logic .%V"10 circuits. The d-namic %)'" circuits are divided into subcategories such as domino logic, ('*,, and true single-/hase clock .T"#%0 circuits.

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