Scribd
Upload
178 views

Experiment2-Basic Logic Gates

This document describes an experiment using logic gates to implement basic logic functions. The experiment involves using IC chips containing NOT, AND, OR, NAND, and NOR gates. The procedures describe connecting the chips in a breadboard with inputs and outputs, then recording the output states in truth tables for each gate. The document concludes by designing a multi-input logic function using the gates and implementing it on the breadboard hardware.

Uploaded by

Subhash Chandra Sahu
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
178 views

Experiment2-Basic Logic Gates

This document describes an experiment using logic gates to implement basic logic functions. The experiment involves using IC chips containing NOT, AND, OR, NAND, and NOR gates. The procedures describe connecting the chips in a breadboard with inputs and outputs, then recording the output states in truth tables for each gate. The document concludes by designing a multi-input logic function using the gates and implementing it on the breadboard hardware.

Uploaded by

Subhash Chandra Sahu
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 13

Experiment2 : Logic gates

Objective: This lab will allow you to gain familiarity with basic logic gates (Not, AND, OR, NAND, and NOR). Equipment Components needed: IDL-800 Digital Lab trainer
Wires IC chips (74LS00, 74LS08, 74LS02, 74LS00, 74LS32) IC extractor

1- NOT Gate Experiment 1.1 Symbol:


A Y

Figure.1: Not Gate symbol Where A is the input and Y is the output

1.2 Pin configuration of the 7404 NOT Gate IC :

Figure.2: Pins configuration of 7404 IC

1.3 Theory:
Referring to figure 2 compete the following: The 7404 IC contains. one-Input NOT Gates. Pins number and designation:

Pin(s) number Designation Inputs . . . . . . . . . . . . Outputs . . . . . . . . . . . . Positive polarity . . Ground . . Table.1: Pins number and their designation for the 7404 IC

1.4 Practice Procedures:


Step1: Place the 7404 in the Breadboard. Step2: Connect Pin7 (GND) to 0V and Pin14 (Vcc) to +5V. Step3: According to circuit shown in figure3, connect the Input "A" to Data Switch SW4 (or any other switcher of your choice) and connect the Output "Y" to Led display.

Y LED

SW4

GND

GND

VCC (+5V)

Figure.3: NOT Gate circuit Step4: Turn the power of the ID-800 and turn Data switcher SW4 from "0" to "1" and back to "0", observe the Output situation of Not Gate, then record it in table2.

A 0 1
Step5: Write the expression for Y: Y = ..

Table.2: Truth table of NOT Gate

2- AND Gate Experiment


2.1 Symbol:
A Y B

Figure.4: AND Gate Symbol Where A and B are the inputs and Y is the output

2.2 Pin configuration of the 74LS08 And Gate IC :

Figure.5: Pins configuration of 7408 IC

2.3 Theory:
Referring to figure 5 compete the following: The 74LS08 IC contains. two-Inputs And Gates. Pins number and designation:

Pin(s) number Designation Inputs . . . . . . . . . . . . Outputs . . . . . . . . . . . . Positive polarity . . Ground . . Table.3: Pins number and their designation for the 7408 IC

2.4 Practice Procedures:


Step1: Place the 7408 in the Breadboard. Step2: Connect Pin7 (GND) to 0V and Pin14 (Vcc) to +5V. Step3: According to circuit shown in figure6, connect the Input "A" to Data Switch SW4 and the Input "B" to Data Switch SW2 (or any other switchers of your choice) and connect Output "Y" to LED display.
A Y B LED

SW4

SW2

GND

GND

VCC (+5V)

GND

VCC (+5V)

Figure.6: AND Gate circuit Step4: Turn the power of the ID-800 and turn Data switchers SW4 and SW2 from "0" to "1" and back to "0", observe the Output situation of And Gate, then record it in table4.

A 0 0 1 1

B 0 1 0 1

Table.4: Truth table of AND Gate Step5: Write the expression for Y: Y = ..

3- OR Gate Experiment
3.1 Symbol:
A B Y

Figure.7: OR Gate Symbol Where A and B are the inputs and Y is the output

3.2 Pin configuration of the 74LS32 OR Gate IC :

Figure.8: Pins configuration of 74LS32 IC

3.3 Theory:
Referring to figure 8 compete the following: The 74LS32 IC contains. two-Inputs And Gates. Pins number and designation:

Pin(s) number Designation Inputs . . . . . . . . . . . . Outputs . . . . . . . . . . . . Positive polarity . . Ground . . Table.5: Pins number and their designation for the 74LS32 IC

3.4 Practice Procedures:


Step1: Place the 74LS32 in the Breadboard. Step2: Connect Pin7 (GND) to 0V and Pin14 (Vcc) to +5V.

Step3: According to circuit shown in figure9, connect the Input "A" to Data Switch SW4 and the Input "B" to Data Switch SW2 (or any other switchers of your choice) and connect Output "Y" to LED display.

A Y B LED

SW4

SW2

GND

GND

VCC (+5V)

GND

VCC (+5V)

Figure.9: OR Gate circuit Step4: Turn the power of the ID-800 and turn Data switchers SW4 and SW2 from "0" to "1" and back to "0", observe the Output situation of And Gate, then record it in table6.

A 0 0 1 1

B 0 1 0 1

Table.6: Truth table of OR Gate Step5: Write the expression for Y: Y = ..

2- NAND Gate Experiment


3.5 Symbol:
A B Y

Figure.10: NAND Gate Symbol Where A and B are the inputs and Y is the output

3.6 Pin configuration of the 74LS00 NAND Gate IC :

Figure.11: Pins configuration of 74LS00 IC

3.7 Theory:
Referring to figure11 compete the following: The 74LS00 IC contains. two-Inputs And Gates. Pins number and designation:

Pin(s) number Designation Inputs . . . . . . . . . . . . Outputs . . . . . . . . . . . . Positive polarity . . Ground . . Table.7: Pins number and their designation for the 74LS00 IC

3.8 Practice Procedures:


Step1: Place the 74LS00 in the Breadboard. Step2: Connect Pin7 (GND) to 0V and Pin14 (Vcc) to +5V.

Step3: According to circuit shown in figure12, connect the Input "A" to Data Switch SW4 and the Input "B" to Data Switch SW2 (or any other switchers of your choice) and connect Output "Y" to LED display.
A Y B LED

SW4

SW2

GND

GND

VCC (+5V)

GND

VCC (+5V)

Figure.12: NAND Gate circuit Step4: Turn the power of the ID-800 and turn Data switchers SW4 and SW2 from "0" to "1" and back to "0", observe the Output situation of And Gate, then record it in table8.

A 0 0 1 1

B 0 1 0 1

Table.8: Truth table of NAND Gate Step5: Write the expression for Y: Y = ..

4- NOR Gate Experiment


4.1 Symbol:
A B Y

Figure.13: NOR Gate Symbol Where A and B are the inputs and Y is the output

4.2 Pin configuration of the 74LS02 NAND Gate IC :

Figure.14: Pins configuration of 74LS02 IC

4.3 Theory:
Referring to figure14 compete the following: The 74LS02 IC contains. two-Inputs And Gates. Pins number and designation:

Pin(s) number Designation Inputs . . . . . . . . . . . . Outputs . . . . . . . . . . . . Positive polarity . . Ground . . Table.9: Pins number and their designation for the 74LS02 IC

4.4 Practice Procedures:


Step1: Place the 74LS02 in the Breadboard. Step2: Connect Pin7 (GND) to 0V and Pin14 (Vcc) to +5V.

Step3: According to circuit shown in figure12, connect the Input "A" to Data Switch SW4 and the Input "B" to Data Switch SW2 (or any other switchers of your choice) and connect Output "Y" to LED display.

A Y B LED

SW4

SW2

GND

GND

VCC (+5V)

GND

VCC (+5V)

Figure.15: NAND Gate circuit Step4: Turn the power of the ID-800 and turn Data switchers SW4 and SW2 from "0" to "1" and back to "0", observe the Output situation of And Gate, then record it in table8.

A 0 0 1 1

B 0 1 0 1

Table.10: Truth table of NOR Gate Step5: Write the expression for Y: Y = ..

5- Implementing a function
Consider the following 3-variables logic function: F(A, B, C) = A.B + A'.B'.C + B.C 5-1 Complete the Truth table below (Table11). A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Table.11: Theory result 5-2 Draw the logic diagram for F using NOT, AND, and OR gates. A B C A' B' A.B A'.B'.C B.C F

F(A, B, C)

Figure.16: diagram of the Logic function F

5-3 Implement the function on the IDL-800 Kit, turn Data switchers (inputs A, B, C) from 000 to 111, observe the Output situation (output F), then record it in table12. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F

Table.12: Experimental result 5-4 Compare between logic states of F recorded in table11 and table12.

You might also like