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CR-5000, System Designer, Board Designer, PWS, Package Synthesizer and Lightning are trademarks or registered trademarks of Zuken, Inc. The other company names and product names are trademarks or registered trademarks of each company.

This manual was prepared as an educational text. For details on specific product features, refer Documentation.

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The contents of this manual are subject to change without notice. Copying the contents of this manual without permission from Zuken Inc. is prohibited by law. 2007 ZUKEN Incorporated.

Preface

Welcome to the world of the PCB Design Library

The Master Training <PCB Design Library> is designed to provide you knowledge required and operation about registration and management for libraries except component which use for PCB design. This is an essential training course to understand in depth the whole system of the CR-5000 system.

Beginners Training

The aim is to attain a level where you can help operators. You will learn the flow of board design.

Beginners Training <PCB Design>

Simple operations for PCB design

Master Training
Library
Master Training <Component Library>
Registration and management of libraries

The aim is to attain the knowledge necessary to be an operator.

Board Design
Master Training <PCB Design>
Detailed operation for PCB design

Master Training <PCB Design Library>

Registration and management of PCB design libraries

Master Training <CAM>

Operation for manufacturing panel design through CAM output

Master Training <Engineering Change/Operation>

Operation and knowledge related to engineering design change/operation

Users engaged only in library design and management should study up through Library but we also recommend reading Board Design. Users only engaged in board design are expected to mainly study Board Design but are recommended to previously read and try out Library.

Preface

Preface - 1

Contents
Preface Welcome to the world of the PCB Design Library

Chapter 1

Using PCB Design Library Tool For The First Time

1. Overview of the Lesson ................................................................................................1-1

Chapter 2

The PCB Design Library

1. The PCB Design Library ...............................................................................................2-1 2. Resource Files ..............................................................................................................2-3

Resource files ................................................................................................................................2-3 Resource files for each tool............................................................................................................2-4 Managing the PCB library list file (library.rsc).................................................................................2-5 Editing the PCB library list file (library.rsc)......................................................................................2-7

Chapter 3

Technology Library

1. Registering a Technology Library..................................................................................3-1

Technology library ..........................................................................................................................3-1 Starting up the Technology Editor...................................................................................................3-4 * Resource file................................................................................................................................3-5 Registering technology...................................................................................................................3-6 * Edit Layer Mapping ....................................................................................................................3-17 * Items which can be set from menu bar ......................................................................................3-20

2. Operating the Technology Library ...............................................................................3-22

Specifications According to Destination........................................................................................3-22 Using a Single-Side Board ...........................................................................................................3-24 Determining Footprint Layer and PCB Layer................................................................................3-25

Chapter 4

Design Rule Library

1. Registering a Design Rule Library ................................................................................4-1

The Design Rule Library.................................................................................................................4-1 Starting up the Design Rule Library Edit Tool .................................................................................4-2 * Resource files. .............................................................................................................................4-2 * Footprint specification name ........................................................................................................4-5 * Loading existing design rules.......................................................................................................4-6 * Define search key ........................................................................................................................4-8 Defining Design Rules....................................................................................................................4-9 * The setting method for each item...............................................................................................4-24

Appendix
1. Design Rule Unit Setting Value List ............................................................................. A-1

1. Overview of the Lesson

The Master Training <PCB Design Library> introduces you to the operations for the functions and registering methods for libraries (Technology Library and Design Rule Library) that are necessary in board designing. These files are in the part surrounded by a dotted line in the figure below.

CDB

System Designer

Technology Library

Design Rule Library

PRT

PKG

FTP

NDF
Net

RUF
Rule ruleA ruleB

RUL

PCB

Design Rule PC Board Database Database

What is the PCB Design Library?

This chapter explains the workflow to design a PC board using the CR-5000 and describes required items and knowledge before starting the actual designing.
Reference
Refer to [Chapter 2 The PCB Design Library].

Design flow Required items Resource files

Registering in the Technology Library

This chapter explains how to prepare conductive layers, symbol mark layers, user defined layers and other items required by a library for PC board design. It also shows how to specify layers in which component shapes to be read to the board are included.
Reference
Refer to [Chapter 3 Technology Library]. Two-layer board Four-layer board A Four-layer board B

Registering in the Design Rule Library

This chapter explains how to extract general rules from design rules necessary for PC board design and prepare them as a library in advance.
Reference
Refer to [Chapter 4 Design Rule Library].

Clearance values Pattern width Via used in wiring Grid

Chapter 1

Using PCB Design Library Tool For The First Time

1-1

1. The PCB Design Library

The following flowchart shows the workflow of PCB design using the CR-5000.

Registering a Component Library (CDB)

Reference

Refer to "Master Training (Component Library)."

These procedures are introduced in this manual.

Registering a Technology Library Registering a Design Rule Library Library registration PC board design

Generating a PC Board Database

(Editing PC board-dedicated design rules)

Inputting PC Board Shape Trial Placement of Components Placement of Components Wiring Inputting Manufacturing Data Check
Reference

Refer to "Master Training (PCB Design)."

Paneling Outputting CAM

Reference

Refer to "Master Training (CAM)."

Chapter 2

The PCB Design Library

2-1

1. The PCB Design Library

Prepare the following items before starting PC design:

Component Library
Registers shapes, attributes, names, other factors for the components to be used.

Reference

Refer to "Master Training <Component Library> as for the details of Component library.

Technology Library
Registers the configuration and attributes of the PC board layer

Two-layer board

Four-layer board (single power)

Four-layer board (multiple power)

Reference Refer to Chapter 3 Technology Library" as for the details of Technology library.

Design Rule Library

Defines rules

Reference Refer to Chapter 4 "Design Rule Library" as for details of Design Rule library.

Information from Schematic (Net List, Design Rule List)

Extracts connecting information, electric rules and others for the board to be designed from System Designer.

Net List (NDF)

"SIGN12": "SIGN2" : "SIGN8": "GND" :GROUND "SIGN22": "SIGN9" : "SIGN12": : "SN74LS08": "AND2" : "IC9" : "1" : : "SN74LS08": "AND2" : "IC9" : "2" : : "SN74LS08": "AND2" : "IC9" : "3" : : "SN74LS08": : "IC9" : "7" : : "SN74LS08": "AND2" : "IC9" : "11" : : "SN74LS08": "AND2" : "IC9" : "12" : : "SN74LS08": "AND2" : "IC9" : "13" : : "1.cmp13": "A" : "1.cmp13 : "B" : "1.cmp13": "Y" : : : "1.cmp16": "Y" : "1.cmp16": "A" : "1.cmp16": "B" : : : : : : :

Design Rule List (RUF)

(design expcb1.cir (header) (rule (net AA[0] (pinList (funcTerm (funcTerm (net WAIT (pinList (comp

1.cmp25 1.cmp89

A0) 4Y)))

(part SN74LS08) (stockId Z121A1121))) IC14

2-2

Chapter 2

The PCB Design Library

2. Resource Files
Resource files
"Resource files" are provided for each of CR-5000's tool to allow users to define the operating environment. When a resource file is stored in a specified directory in a specified format, it is automatically loaded at each tool's startup, determining the tool's operating environment and initial file value.

Tool startup

Resource file

Chapter 2

The PCB Design Library

2-3

2. Resource Files

Resource files for each tool

The PCB library references the following resource files: Library Resource Priority 1 %HOME%\cr5000\ue\library.rsc (local resource) Priority 2 %CR5_PROJECT_ROOT%\zue\info\library.rsc (project resource) Priority 3 %ZUEROOT%\info\library.rsc (master resource)
Sets file names and storage directories for libraries required in designing, including the components library, technology library, design rule library, and manufacturing rule library.

Differences in roles and usage among the above libraries are shown below.
Caution

The environment variables shown above (e.g. %ZUEROOT%) are shown as they appear in Windows. In UNIX, they are represented in the form $ZUEROOT. (e.g. Parameter definition resource for PCB/PNL data generation: $ZUEROOT/info/parameter.rsc)

The followings are items in a library resource (library.rsc) referenced by a PCB design library.

Component libraries

Caution

Only one library file name can be set for one type of library. Even if a file name for one library type is written in two or more columns, all descriptions after the first are ignored.

2-4

Chapter 2

The PCB Design Library

2. Resource Files

Managing the PCB library list file (library.rsc)

As shown above, a library.rsc can be stored in the following three paths. If there are several library.rsc, only the file with the highest priority is referenced, while the others are ignored. Priority 1 Priority 2 Priority 3 %HOME%\cr5000\ue\library.rsc (local resource) %CR5_PROJECT_ROOT%\zue\info\library.rsc (project resource) %ZUEROOT%\info\library.rsc (master resource)

%HOME%\cr5000\ue\library.rsc (local resource = personal environment) %HOME% = A home directory for the login user that can be set for each login user. This is a resource file dedicated to the corresponding user. %CR5_PROJECT_ROOT%\zue\info\library.rsc (project resource = project environment) %CR5_PROJECT_ROOT% = Users can set this directory freely, including a directory for mounting destination. This is a common resource file that can be handled by users with different machines. %ZUEROOT%\info\library.rsc (master resource = program environment) %ZUEROOT% = A directory in which the program is installed. This is a common resource file for all users using the same program server. When the program is installed in individual machines, this directory cannot be shared by users with different machines.
Caution

The environment variables shown above (ex. $ZUEROOT) are represented as in UNIX. In Windows, they are represented as in %ZUEROOT%. Keep in mind that this manual represents environment variables in UNIX format.

Example

Example 1) When login users lesson1 and lesson2 are in machine Host1:

Host1

In this example, user lesson1 has a local resource and references it, but not a master resource. User lesson2 has no local resource file and references the master resource.

Chapter 2

The PCB Design Library

2-5

2. Resource Files

Example 2) When login users lesson1 and lesson2 are in machine Host1 and login user lesson3 is in another machine, Host2. Also, when Host2 mounts on Host1: Host1 Mount Host2

$ZUEROOT = /opt/cr5000/zue $CR5_PROJECT_ROOT = /home/prjrt lesson1: $HOME = /home/lesson1 lesson2: $HOME = /home/lesson2

$ZUEROOT = /opt/cr5000/zue $CR5_PROJECT_ROOT = host1 /home/prjrt lesson3: $HOME = /home/lesson3

User lesson1 in Host1 has a local resource and references it, but does not reference master and project resources. Since lesson2 in Host1 and lesson3 in Host2 have no local resources, they search the project resource and reference it. The master resource is not referenced. $CR5_PROJECT_ROOT for Host1 and $CR5_PROJECT_ROOT for Host2 refer to the same directory on Host1. Therefore, by using this environment variable it is possible to design in the same environment even among different machines. We recommend using each resource according to the environment: Master resource when designing in the same environment by a specific terminal Project resource when designing in the same environment by several terminals Local resource when designing in a specific environment by specific users.
The environment variable %CR5_PROJECT_ROOT% is not automatically set at installation. This variable must be set for each client in order to use it.

2-6

Chapter 2

The PCB Design Library

2. Resource Files

Editing the PCB library list file (library.rsc)

The library.rsc file can be edited with the "PCB design library list file editor", as well as by the UNIX vi editor and the Word Pad for Windows. This section shows how to edit the library.rsc using the PCB design library list file editor. The PCB design library list file editor can edit all types of library.rsc for the master resource (program environment), project resource (project environment) and local resource (personal environment). Edit a personal environment library.rsc prepared for the lesson, according to the lesson environment. Resource file to be edited %HOME%/cr5000/ue/library.rsc (local resource = personal environment) (C:\home\lesson2) Library to be referenced (library has already been prepared) Part library C:\home\lesson2\cdb\cdb2.prt Package library C:\home\lesson2\cdb\cdb2.pkg Footprint library C:\home\lesson2\cdb\cdb2.ftp Technology library C:\home\lesson2\tch\lay.tch Design rule library C:\home\lesson2\rule.rul Start up the PCB design library list file editor. 1. Start up the editor by clicking the start button on the task bar, then select Programs CR-5000 Board Designer 10.0 Utilities PCB Design Library List File Editor from the menu.

Lesson

UNIX

1. Start up the editor by clicking Utilities PCB library list file editor on the menu.

Click

Chapter 2

The PCB Design Library

2-7

2. Resource Files

2. The PCB design library list file editor is started up.

3. Click File Open User from the menu bar.

The user environment library.rsc file, %HOME%\cr5000\ue\library.rsc, is opened.

2-8

Chapter 2

The PCB Design Library

2. Resource Files

4. Change the part library path. Click the part library path to highlight it.

Click

Click

Click

Change .

A dialog box for name change is opened.

Click

Specify a library name from the file selector.

Select C:\home\lesson2\cdb\cdb2.prt, then click OK .

C:\home\lesson2\cdb\cdb2.prt is already prepared.

Click

Click OK .

Chapter 2

The PCB Design Library

2-9

2. Resource Files

5. Change the names of the other libraries as shown on page 2-7.

Check that the Directory for Library Searcher is set up as shown on the left.

It is not necessary to change the Manufacture Rule Library and the Directory for Manufacture Panel Template.

6. Save the data after all path names are changed. Then exit from the tool.

Click

Click

2 - 10

Chapter 2

The PCB Design Library

1. Registering a Technology Library

Technology library
The layer configuration for the PC board to be designed is registered in a technology library (TCH). To design one PC board, a variety of objects including patterns, symbol marks and resists are input to "layers". Define all layers required in designing one PC board to a technology library.

Conductive layer1 Conductive layer2 Side A resist layer Side B resist layer Side A symbol mark layer Side B symbol mark layer

Layers are defined by each object, taking films at manufacturing into consideration.

A layer required in designing a PC board (PCB layer) differs depending on the number of layers and specifications of the PC board. The technology library registers all layer definitions that are expected to be used in PC board designing, into one file. And one of technologies suitable for the board specification is selected when a new PCB file is generated.

TCH

Single Layer

4-Layer Board (1)

[4-Layer Board (1)] 4-Layer Board (2) 6-Layer Board

Chapter 3

Technology Library

3-1

1. Registering a Technology Library

Layer Mapping

Now, please recall the footprint layer definition described in "Registering a Component Library (CDB)". A layer for the component registration called "footprint layer" is also defined in the CDB library, and the objects are input to each footprint layer.

Example
A side conductive layer B side conductive layer Inner conductive layer Resist layer Symbol mark layer Hole layer

Layers must be defined for this footprint layer so that it can be used for any board, regardless of the number of layers on the board to be designed. Therefore, the footprint layer which is defined separately, must be assigned to the PCB layer to use the component in the PC board. The technology library assigns the footprint layers to PCB layers, too. 2-Layer Board

Conductive layer1

Footprint Layer
Component side conductive layer Inner conductive layer Solder side conductive layer

Conductive layer2

4-Layer Board
Conductive layer1 Conductive layer2 Conductive layer3 Conductive layer4

Correspondence between the footprint and PCB layers is referred to as "Layer Mapping". As shown above, a footprint can correspond with any PCB layers, including 2-layer and 4-layer boards.

3-2

Chapter 3

Technology Library

1. Registering a Technology Library

When registering a footprint layer, component shapes are registered from a view of the component side. When inputting components into the PC board, however, the object's input layer varies depending on whether the placement side is Side A or B. PCB Layer A-side placement Footprint Layer
Conductive Resist Symbol mark

Layer1(A side) Layer2(B side) Resist(A side) Resist(B side) Symbol(A side) Symbol(B side)

B-side placement

For this reason, the Technology Library makes it possible to change the input layer by defining Side A mappings and Side B mappings. When a shape does not change even if the placement side changes, an object-input layer is switched automatically by changing the mapping for each placement side, without having to create another footprint. When placing on Side B, a footprint is mirror-inverted automatically to design the PC board from the component side.

Footprint

When placed on B-side When placed on A-side

As a resist shape may be changed when a placement side changes, the resist shape can be changed with the same footprint if the footprint-layer definition and mapping are used well.

Reference For detailed information on operation using mapping, 2. Operating the Technology Library on page 3-22 will be explained.

Chapter 3

Technology Library

3-3

1. Registering a Technology Library

Starting up the Technology Editor

Edit technology

The Technology Editor is used to register the technology library. This section explains what kind of information will be registered to the technology library, through the lesson. 1. Before starting up the Technology Editor, be sure to check whether the names of the technology library files to be registered and component library file to be referenced are defined correctly in the resource file. A local library resource is used in this lesson.
For detailed information on how to define and edit the resource file, refer to "Editing PCB design library list file (library.rsc)" on page 2-7.

Lesson

Reference

<Library Resource> [ C:\home\lesson2\cr5000\ue\library.rsc]

Check that the setting is as shown in the left. "C" indicates the drive. When training data is set in another drive, it is stored in the path starting from that drive name.

UNIX

Check that the setting is as shown to the left. When training data is set in another directory, it is stored under the corresponding directory.

Caution

CDB layer information is necessary to map layers when a technology library is registered.

3-4

Chapter 3

Technology Library

1. Registering a Technology Library

2. Click the start button on the task bar, and select Programs CR-5000 Board Designer 10.0 PCB Design Common Environment from the menu. Then click Edit Technology .

UNIX

(PCB Design Common Environment) from the CR-5000 route menu. 2. Click Then click Edit Technology.

Click Click

* Resource file When the Technology Editor is started up, the name of the library that loads the following resources for registration and reference is determined: Priority1 %HOME%\cr5000\ue\library.rsc Priority2 %CR5_PROJECT_ROOT%\zue\info\library.rsc Priority3 %ZUEROOT%\info\library.rsc (local resource) (project resource) (master resource)

The library name is determined at start-up. However this can be changed to another library file after start-up. Select Set Set Library from the menu bar:

Reference

For detailed information on how to define and operate the resource file, refer to "Managing PCB design library list file (library.rsc)" on page 2-5.

Chapter 3

Technology Library

3-5

1. Registering a Technology Library

Registering technology
The following technology will now be registered. After a lesson on registering, this section then will explain how to set items. Check the contents for the following technology to be registered before proceeding to the lesson on the next page. Technology Name: [layer4-PBBP] Conductive layer 4-Layer board Non-conductive layer Reserved layer Positive Full surface Full surface Positive Reflow

Flow (Layer1 and 4) (Layer1 and 4) (Layer1 and 4) (Layer1 and 4) (Layer1 and 4) (Layer1 and 4)

Symbol Mark Solder Resist Metal Mask Height Limit Area Component Area Thermal Shape

User defined layer

Wiring Keep-out layer (Layer1 and 4, common to all layers)

Placement Keep-out layer (Layer1 and 4) Via Keep-out layer (Layer1 and 4) Adjusting Mark layer Data input layer to exfoliate inner copper Mapping between footprint and PCB layers PCB layer Conductive-1 Conductive-2 Conductive-3 Conductive-4 Footprint layer Comp-conductive-1 Comp-symbol Comp-resist1 Comp-metalmask Comp-comparea1 Comp-comparea2 Symbol-A Resist-A MetalMask-A HeightLimit-A CompArea-A ThermalShape-A Symbol-B Resist-B MetalMask-B HeightLimit-B CompArea-B ThermalShape-B Inhibit(wir)-A Inhibit(wir)-B Inhibit(wir)-C Inhibit(plc)-A Inhibit(plc)-B Inhibit(via)-A Mark No-conductive HOLE Conductive layer

Non-conductive layer (Reserved layer)

Comp-inh(wir)1 Comp-inh(wir)2 Comp-inh(plc)1 Comp-inh(plc)2 Comp-mark Comp-hole

Non-conductive layer (User-defined layer)

3-6

Chapter 3

Technology Library

1. Registering a Technology Library

Lesson

1. Specify the technology name. Type in layer4-PBBP into a box on the right of "Technology Name". Press Return to apply. And then type in 4 or enter it from the numeric input dialog box.
A new technology is created by typing in a file name which does not exist.

Caution

Be sure to set the layer count first. 2. Define the number of conductive layers.

A comment can add to the technology to create and it is displayed by the technology selector dialog.

Select Soldering on conductive Layer 1 and click Reflow from the optional list .

Select Lay Attribute cell and click Positive from the optional list.

Set each layer as shown in the left. Soldering (flow/reflow/reflow x 1/undefined)

Specify a soldering method for the outside layer only. The attributes specified here have an effect on the following items in PC board design:

Different clearance can be defined for flow and reflow by Resist-Conductive check The component placement side is limited by defining soldering corresponding to the part library (Unlimited/flow disabled/one-time reflow enabled).
Undefined Technology Flow Reflow 1 Reflow Combinations in the left table represented by a circle can be placed.

Part

Unlimited Flow disabled One-time reflow

Layer Attributes
Specify the layer attributes for each layer. The attributes specified here limit the objects that can be input and affect on automatic change of land status. Positive Layer to which normal positive-image figures are input. Posi-Negative Layer to which multiple power/GND is input or a layer that includes mixed positive and negative figures. Power plane Power plane with single power/GND Thermal shape is automatically generated for vias on the same net. Wiring keepout Layer in which no figure is input Used for single PC board.

Chapter 3

Technology Library

3-7

1. Registering a Technology Library

3. Save the settings. Click File Save .

Click

Click Save and save the settings specified in the main menu before displaying sub-menus, such as the non-conductive layer edit menu and mapping menu. If you are going to open the sub-menu without save to the file, the following dialog box appears:
Clicking Yes on this dialog box saves the settings in the main menu.

4. Registers a non-conductive layer. Click

Register Noncond. Layer .

Click

List Display Area

Names of registered non-conductive layers are displayed in a list. This area is used when defining a comment to a non-conductive layer.

Registration and Editing Area

This area is used when registering and editing a non-conductive area.

5. Select

User Created Layer

for Target to edit:

Click

3-8

Chapter 3

Technology Library

1. Registering a Technology Library

6. Type in Inhibit(wir)-A to a blank box in the registration and editing area and then click Add on the lower right of the window.

Click

7. Click the Layer Comment cell for Inhibit(wir)-A that is displayed in the list display area, then enter [Side A Wiring Keepout Layer] as the layer comment.

Click

8. Register all the following layers after repeating the above procedures: Non-Conductive Layer Name Inhibit(wir)-A Inhibit(wir)-B Inhibit(wir)-C Inhibit(plc)-A Inhibit(plc)-B Inhibit(via)-C Mark No-Conductive
Note

Layer Comment
Wiring Keepout for A side Wiring Keepout for B side Wiring Keepout for both A and B side Placement Keepout for A side Placement Keepout for B side Via Keepout for all layers Fiducial Mark Data for Flaking Copper

Layer Function
Layer that includes an area where wiring of Side A is prohibited. Layer that includes an area where wiring of Side B is prohibited. Layer that includes an area where wiring of Sides A and B are both prohibited. Layer that includes an area where placement of Side A is prohibited. Layer that includes an area where placement of Side B is prohibited. Layer that includes a via prohibited area common for Sides A and B. Adjusted mark layer Layer that includes copper foil flaking data for full surface.

Click

When an incorrect name is added to the non-conductive layer name, delete it in the following steps:
1. 2. 3.
Click

Click the layer comment for the wrong name in the list display Check that the layer comment with the wrong name is displayed in a blank box in the registration and editing area. Click Delete .

Chapter 3

Technology Library

3-9

1. Registering a Technology Library

9. Click OK after registering all the layers in order to exit the Register Noncond. Layer menu.

Click

Note

The layer comment is reflected on the PCB database layer attribute dialog box and the visible layer dialog box.

Edit Noncond. Layer This is used to register a layer that is required for PCB design other than the conductive layer. Non-conductive layer has four kinds. 1. System Layer 2.Variant Hole Layer 3.Reserved Layer 4. User Created Layer 1. System Layer The following 3 layers are being prepared as System Layer. Each role of layer is being decided as a layer which the system recognizes. PC Board Shape Layout Area Hole
Layer to input a PC board shape Layer to input a design area where placement and wiring are possible Layer to input hole

2. Variant Hole Layer The data input on this layer are handled as the "hole data2. Following data are possible to input. Line Area Pad

3. Reserved Layer The minimum layers required in designing and manufacturing PCBs are automatically prepared as reserved layers by the system. Since these layers are each pre-assigned a role, enter only an object corresponding to that role. By doing this, the checking function prevents the designing of a PCB that violates the design conditions. Symbol-A, B Resist-A, B MetalMask-A, B HeightLimit-A, B CompArea-A, B ThermalShape-A, B
Caution

Layer to input silk characters and silk figures Layer to input resists Layer to input metal mask figures Layer to input height limitation area in the PCB Component area layer (used for component overlap check) Layer to input thermal shape (used for quick thermal)

System layer and System reserved layer names are fixed.

3 - 10

Chapter 3

Technology Library

1. Registering a Technology Library

4. User Created Layer Layers that are expected to be needed for PCB design other than conductive layers and system-reserved layers are registered. The following layers can be considered as layers to be registered as user-defined layers: Layer to input data for placement, wiring and via keep-out area Layer to input data for adjustment mark, etc Layer to input data for mount drawing data Layer to input data for hole mark Spare layer

Note

If two or more symbol mark layers or resist layers are needed for each A or B placement side on the PC board, this can be solved by defining two or more system reserved layers. Turn ON the setting of multiple reserved layers.

Change to Reserved Layer as Target to Edit and click the list icon for Nocond. Layer.

Click

Click

Select Symbol-* from the reserved layer list and add. This adds Symbol-A-1 and Symbol-B-1.

In the figure to the left, Symbol-A, Symbol-A-1, Symbol-B, and Symbol-B-1 are handled as a symbol mark layer.

Caution

Multiple reserved layer names cant change.

Chapter 3

Technology Library

3 - 11

1. Registering a Technology Library

10. Specify relating between a user-created layer and conductive layer. Specify 1 as the conductive layer number for Noncond. Layer related to cond. Layer . A layer can also be selected by clicking the inside of a soldering frame or layer attribute frame for conductive Layer 1.
Information on the conductive layer in light blue is displayed in the Noncond. Layer related to cond. Layer list on the right.

Click

11. Click

Inhibit(wir)-A in the Noncond. Layer Name list.

Click Click

12. Set Wire + Via Keepout click Add .

for the Nocond. Layer related to cond. layer and then

Click

Inhibit(wir)-A

is added to the list.

When an incorrect layer name or type is added, delete it once and then add the correct one. To delete an item, click the incorrect column on the list to check that the name or type displayed in Noncond. Layer: is wrong, then click Delete .

13. Repeat the above steps so that the following is set for conductive Layer 1.

Inhibit(wir)-A Inhibit(wir)-C Inhibit(plc)-A Inhibit(via)-C

(Wire + Via Keep-out) (Wire + Via Keep-out) (Placement Keep-out) (Only Via Keep-out)

3 - 12

Chapter 3

Technology Library

1. Registering a Technology Library

14. In the same way, set the following to the conductive Layer 4. Inhibit(wir)-B Inhibit(wir)-C Inhibit(plc)-B Inhibit(via)-C (Wire & Via Keep-out) (Wire & Via Keep-out) (Placement Keep-out) (Only Via Keep-out)

In this lesson, the non-conductive layer does not need to be set for Layers 2 and 3.

Non-Conductive Layer Relating A non-conductive layer can be related to a conductive layer. The system will recognize the non-conductive layer as a layer to input an object that corresponds to the conductive layer after associating. For example, when Inhibit(wir)-A is related as a wiring keepout layer for conductive Layer 1, it becomes a wiring keepout layer for conductive Layer 1. Non-conductive Layers
Inhibit(wir)-A Inhibit(wir)-B

Conductive Layers

Conductive Layer 1 Inhibit(wir)-A

This becomes a wiring keep-out area for the related conductive layer by inputting objects such as a line and surface.

There are six layer types for specification:

Placement Keepout A layer to input an object used for match checking with components placed on a conductive layer. Wire & Via Keepout A layer to input an object used for match checking with a wiring pattern and via for a conductive layer. Only Via Keepout A layer to input an object used for match checking with a via to be input to a conductive layer. Only Wire Keepout A layer to input an object used for match checking with a wiring pattern for a conductive layer. Via Hole Keepout A layer to input an object used for match checking with a via hole to be input to a specified layer. Others Select this type if you want to relate the non-conductive layer for a purpose other than the above five. When this setting is selected, relating becomes insignificant.

In this lesson, Inhibit(wir)-A and Inhibit(wir)-B are specified as Wire & Via Keepout for Layer 1 and Layer 4, respectively. On the other hand, Inhibit(wir)-C becomes a Common Wire & Via Keepout layer for both Layer 1 and Layer 4 since it is related to both sides.

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15. Save all settings made to this point. Click File Save .

Click

16. Define the mapping for the footprint and PC board layers. Click Edit Layer Mapping .

Click

17. Switch to the conductive-layer-only display by using the displayed layer switching button to the upper left of the window.

Click

18. Click Comp-conductive1 in the footprint layer list from the optional list at the Conductive-1 Side A map cell.

Click

When an arrow mark displayed on right side of the selected frame is clicked, the layer attribute is checked and only footprint layers that match the attribute are displayed in the list.

19. Click

Function

List Footprint Layers

from the menu bar.

All prepared footprint layers are displayed in the list with the attributes, as well as their names.

Click

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20. Move the red highlighted bar to the Conductive-4 Comp-conductive1 in the footprint layer list.

Side B map and then click

Click

The layer attributes are checked at this time. Only footprint layers that match these attributes are displayed for selection.

As described above, there are three ways to specify footprint layer: 1. Select only layers matching the layer attributes from the list by clicking an arrow mark inside each frame. 2. Select a layer that matches the layer attributes after displaying all footprint layers once on the list. 3. Copy a layer name in the cell then paste it.

21. Similarly, perform mapping as shown below. Conductive Layer

Reserved Layer (Non-conductive Layer)

Keepout Layer (Non-conductive Layer)

User Created Layer (Non-conductive Layer)

Note
Reference

A keepout layer and user created layer indication of the order don't necessarily indicate the above. Please confirm that the layer mapping is correct.

Refer to [*Items which can be set from menu bar] on page3-20 for the way of changing the order of the layer.

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22. Specify the next hole layer. Click

Comp-hole

from the optional list of the hole layer.

Caution

Even though the hole layers are also displayed in the footprint layer list, shown by selecting Function List Footprint Layers from the menu bar, you cannot select a hole layer from this list. Be sure to select a hole layer from the list shown by clicking the list icon.

22. After completing registration up to hole layers, change to All Layers for the Target to edit and confirm that the editor menu is registered as follows. And then click OK to exit the Edit Layer Mapping menu.

Click

Note

Layer mapping of another technology can be copied and reused by selecting Load Layer Mapping from the menu bar.

Function

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*Edit Layer Mapping Mapping of a footprint layer and PCB layer (corresponding each component to the PCB layer) is executed in Edit Layer Mapping. The mapping determines the input destination layer on the PCB for objects (e.g., padstacks and lines) that are input through Set Footprint Layer. Even if there is only one component shape, the layer to be mapped varies depending on the placement side. Therefore, mapping when components are placed on Side A and Side B can be set separately by Edit Layer Mapping. PCB Footprint
Comp-conductive1 Comp-resist1 Comp-symbol

Placed component on A-side

Placed component on B-side

Conductive-1 Conductive-2 Resist-A Resist-B Symbol-A Symbol-B

Technology <Layer mapping>

The set example of the above mapping

In case of components that terminal shapes penetrate to the bottom layer such as insertion-mounting type components, the pad shape must be registered for all conductive layers. Mapping of padstacks with through attributes set to Through are executed according to the setting of the Side A Penetration Map and Side B Penetration Map.
Padstack with "Through" attribute

Objects that were input by Footprint Registration Tool

PCB
Placed component Placed component on A-side on B-side
Conductive-1

Footprint
Comp-conductive1 Comp-resist1 Comp-symbol Comp-comparea1 Comp-comparea2

Conductive-2 Resist-A Resist-B Symbol-A Symbol-B Comparea-A Comparea-B

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Technology <Layer mapping>

The set example of the previous mapping

Mapping for padstacks other than through padstacks for Side A components

Mapping for padstacks other than through padstacks for Side B components

Mapping for through padstacks for Side A components

Mapping for through padstacks for Side B components

As shown above, four types of mapping are executed for each PCB layer in Edit Layer Mapping, to support different component placement sides and through attributes (through or non-through). Side A Mapping Side B Mapping Side A Penetration Map Side B Penetration Map
For components on the top surface For components on the bottom surface For through padstacks of components on the top surface For through padstacks of components on the bottom surface

Surface -mounting type components on Side A

Surface -mounting type components on Side B

Insertion -mounting type components on Side A

Insertion -mounting type components on Side B

For insertion-mounting type components, Side A and B Penetration Maps are referred for objects including pins and resists that use through padstacks. Side A and B Mapping are referred for other objects, including symbol marks and component areas that are input on the footprint. For surface-mounting type components and others that do not use any through padstacks, Side A and B Mapping is referred for all objects.

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24. Select

default

for the padstack group.

Reference

Refer to online help for details on the padstack group,.

25. Now, one technology is completed. Click File Save to save the contents you have registered.

Click

26. Click File Exit to exit the Technology Editor.

Click

27. Exit the PCB Design/Manufacture Common Tool. Click File Exit from the menu bar.

Click

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* Items which can be set from menu bar It describes items which can be set by the Set of the menu bar in Technology Editor.

1. 2. 3. 4.

The display order of layers can be specified. The special rule for area can be specified. The sub-layer for connecting between conductive data can be specified. This item is used by HIC design. HIC is an optional module.

1. Specifying the display order of layer name. Set Change Order of Layer Name

The display order of the layer name is changed on dialog where it started.

The line which selected is changed to up or down and then the display order is changed.

2. Using the RulesbyArea Layer. Set RulesByArea

The RulesByArea can specify special rule (e.g. Design Rule Stack name, Wiring Width Stack name for an area and Default Padstack name) and the area is input by the specified rule. When the RulesByArea is set to "ON" in the Technology editor and then the Board Generation tool is performed, the layer that name is [RulesByArea] is added to the PCB data and the area which specified special rules can be created on the PCB. PCB database
Design Rule A

RulesByAre

Design Rule B

Caution

If you want to set the RulesByArea layer to an existing PCB data, you need to update the technology specified by the PCB Technology Update tool to reflect it to the PCB data after RulesByArea was specified. For details of the operations which RulesByArea are used for, refer to [Master Training <Engineering Change/Operation].

Reference

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3. Using Sub-conductive layers.

Set

Sub Cond. Layers

The Sub-conductive layer is the layer which the data to connect a different net such as tie point are input to. Some different nets in the schematic are connected on the tie point but their nets are handled as same net on PCB design. Board Designer can't connect between different nets. So the Sub-conductive layer is used. When the data was input to the Sub-conductive layer, they can be output as same net by the Pattern Connection Pinlist Output program (bdnetout). When the Sub Cond. Layers is set to "ON" in the Technology editor and then the Board Generation tool is performed, layers names are [Subconductive-1] and [Subconductive-2] etc are added with specified conductive count to the PCB.

Conductive-1(Conductive Layer) SubConductive-1(Sub Layer Non-conductive Layer) Conductive-2(Conductive Layer) SubConductive-2(Sub Layer Non-conductive Layer)

Caution

If you want to set the Sub-conductive layer to a existing PCB data, you need to update the technology specified by the PCB Technology Update tool to reflect it to the PCB data after Sub Cond. Layers was specified. Refer to online help [Batch Program Help] for details of Pattern Connection Pinlist Output.

Reference

4. Using Sub Dielectric layers. Set Set Dielectric Area

The dielectric area layer is used when a cross glass of the Embedded Component Design Module (HIC) is generated. The Embedded Component Design Module is optional module. Specify the count of dielectric layers on the dialog where it started.

Click

Reference

Refer to the online help for details of Embedded Component Design Module.

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2. Operating the Technology Library

This section explains the setting items for the Technology Library that you have up until now only seen. In order to deepen your knowledge, this section offers instructions on how to actually operate the Technology Library.

Specifications According to Destination

A component shape may change according to the destination. But in case of that the destination component can be used properly with one footprint by layer mapping. When a silk shape changes according to the destination:
Company A

Company B

When a component shape changes depending on the board density:

Low-density High-density

As shown above, even when mounting the same components, the shape may require delicate changes. If you try to support such changes by separately registering each on a footprint, the number of components becomes too large and the configuration of the CDB library cannot be utilized fully. Therefore, it is best to group the same components and manage them in one footprint, and to handle the differences in component shape depending on destination by using a technology library. The following introduces Change in Specifications by Mapping as a handling method.

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Change of Specification by Mapping

Specifications can be changed to support most destinations by mapping the footprint layer and the PCB layer. For example, when a silk shape is different between Companies A and B;
Technology for Company A
Conductive layer for A-side

Conductive (Terminal )

Conductive layer for B-side

Symbol mark layer for Company A Symbol mark for Company A

Technology for Company B

Symbol mark for Company B Conductive layer for A-side

Conductive layer for B-side

Symbol mark layer for Company B

Prepare Symbol mark layer for Company A and Symbol mark layer for Company B in the footprint layer in advance, and input each symbol mark into the corresponding layer. Then, create a technology mapping for Company A and one for Company B by using the technology library. This method can support differences in high or low board density.
Technology for High-density
Conductive layer for A-side

Conductive for Low-density (Terminal)

Conductive layer for B-side

Conductive for High-density (Terminal)

Symbol mark layer

Technology for Low-density

Symbol mark Conductive layer for A-side

Conductive layer for B-side

Symbol mark layer

Caution must be taken, however, since the number of footprint layers to be prepared will increase and the mapping operation may become complex when you use mapping to solve all such support.

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Using a Single-Side Board

When designing a single-side board with the CR-5000, layer configuration needs to be considered carefully as follows.

Footprint (Padstack) registration

A different hole diameter by single-side board and multi-layers board may be used. In such a case, observe the following for padstack registration:
Multi-layers board
Hole for multi-layers board Hole for single-layer board Conductive Resist

Single-layer board

Note

When they are designed by same hole even if their designing boards are different spec like single-side board and multi-layers board, the above registration is unnecessary.

Technology registration
Even though the number of conductive layers for a single-side layer is 1, the layer count is defined as 2 layers here. If one layer is defined, the symbol mark layer and resist layer also becomes one, resulting in silk print only on the one side. Therefore, define a two-layer board and prohibit wiring on one side of the conductive layer.
LayerAttribute : Wire Keepout

When a hole layer for the single-side board exists in the footprint layer, be sure to specify it for layer mapping.

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Determining Footprint Layer and PCB Layer

In the preceding Technology Library explanation, we can see that several types of board having various specifications can be designed through mapping between the footprint layer and PCB layer. Whether an effective mapping is executed depends on the footprint layer. It is difficult to change the set footprint layer definition after registering many components. Therefore, we recommend that you determine the footprint layer and PCB layer before starting library construction. Determine these according to the operation purpose after completely understanding the mapping between the footprint layer and PCB layer. The following is a flow chart on determining the footprint layer.

1. Identifying the component shapes for registration

Insertionmounting type component Surfacemounting type component Chip type component QFP type component

Edge connector

Adjusting mark

Logo mark

Drawing frame

ZUKEN
2. Identifying the board specifications to be designed
Single-side board/Multi-layers board Single-side board Both-side board Multi-layers board

High -/low-density Pin pitch two/three/four Whether to change the resist shape depending on flow/reflow For Company A/B

3. Identifying layers required for board design

Conductive layer Resist layer Symbol mark layer Metal mask layer Wire keepout layer Mount drawing layer Hole mark layer

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4. Find layers that can be used in common after consideration of Steps2 and 3.
Layers that can be used in common Single-side board Conductive layerLayer 1) Resist layer Symbol mark layer (for A-side) Symbol mark layer (for B-side) Metalmask layer Both-side board Conductive layerLayer 1) Conductive layerLayer 2) Resist layerfor A-side Resist layerfor B-side Symbol mark layer (for A-side) Symbol mark layer (for B-side) Metalmask layerfor A-side Metalmask layerfor B-side Layers that can be used in common

Select a common layer if the pin shape and metalmask shape are same for single-side and both-side boards.

5. Identifying layers required for footprint after consideration of Step4.

Conductive layer Resist layer for single-side board) Resist layerfor both-side layer board) Symbol mark layer for single-side board) Symbol mark layerfor both-side layer board) Metalmask layer

Dimension line layer Pin No. input layer Comment layer

If there is a necessary layer when a component is only registered, they are added to identified layers and finally all footprint layers are determined The more detail the footprint layer is divided into, the easier it will be to reuse. For example, if the shapes of the conductives on Sides A and B are definitely the same, a common layer should be used. There will be difficulties in dividing if you want to add other components with different shapes later. Be sure to divide the footprint layer when a different shape may be required. However, it takes more time for footprint shape registration if the footprint layer is divided excessively. Therefore, first take sufficient consideration.

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The Design Rule Library
The design rule library (RUL) registers general rules for PC board design. Clearance values Pattern width Via used in wiring Grid
Example

A new PC board is generated by specifying design rules from the design rule library that are most similar to the PC board specifications. General design rules are then duplicated to generate a design rule database (RUL).
Technology library Design rule library

TCH

Specification Specification Specification A B C

General design rules

Board Generation

PCB

RUL

Design rules specific to the PC board

PC Board Database

Design Rule Database

Detailed specifications belonging to each PC board (e.g., pattern width for each net name) are defined in a design rule database using another tool.
Reference
Refer to [Master Training <PCB Design>] for details on design rules specific to PCB.

The design rule library is designed to have several design rules according to the number of PC board layers and setting values. Each design rule configures a file.

Directory for Design Rules

Design rule library specifies the directory name in the library.rsc file.

A.rul

B.rul

C.rul

D.rul

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Starting up the Design Rule Library Edit Tool

Edit Design Rules

The design rule library executes registration and editing using the Design Rule Library Edit Tool. This section first introduces the setting items in the design rule library, then shows actual registration. 1. Click Programs CR-5000 Board Designer 10.0 PCB Design Common Environment from the start menu. Then click Edit Design Rule .

Lesson

(PCB Design/Manufacture Common Tool) on the CR-5000 route menu, 1. Click then click Edit Design Rule.
UNIX

Click Click

* Resource files When the Design Rule Library Editor is started up, the following resource file is loaded and the library name which is registered and referred to is determined Priority 1. %HOME%\cr5000\ue\library.rsc (Local resource) Priority 2. %CR5_PROJECT_ROOT%\zue\info\library.rsc (Project resource) Priority 3. %ZUEROOT%\info\library.rsc (Master resource) The library name is determined at startup. But the names can be changed after tool startup. Select Set Library from the menu bar.

Library names cannot be set or changed after specifying a design rule name.

Reference

Refer to "Managing the PCB design library list file (library.rsc)" on page 2-5 for detailed information on how to define and operate the resource file.

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2. Specify a design rule name. Enter design rule name ruleA to be generated and decide by Return key.
When registering a new design rule library, a file named design rule name.rul is automatically made in the design rule directory simultaneously when a design rule name is entered. A message appears when registering a new design rule library, since a technology name is undefined at this time.
Click

Click

OK .

3. Specify a technology name. In this lesson, use layer4-PBBP. Click on the list icon for the technology name.
Click

Click

Select

layer4-PBBP

and click

OK .

Click

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4. Set a footprint specification name. Since the component library named used in this lesson is defined as default, specify this name.

Click

Select the list icon on the Footprint Spec Name.

Click

Click default from the Footprint Spec Name List.

Click

Click Add>> and then click OK after confirming that default is displayed in the Specified Footprint Spec Name List.

Click

The priority can be changed when multiple footprint specification names are existing

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* Footprint Specification name The footprint specification name is a name for a footprint in the package information on the component library (CDB). The configuration of the CDB is as follows:

Normally, one footprint name is assigned to the package LS08_DIP. But if one footprint cannot be supported, multiple footprint names can be assigned. In such a case, footprint specification name can be assigned to each footprint. The footprint specification name specifies the corresponding priority for prepared footprints at PC board designing.
Example

Z80A-QFP Specification name default fine

Footprint name ABC AAA

LS04-DIP Specification name default low

Footprint name XYZ ZZZ

Click footprint specifications in priority from the displayed list in footprint specification name specification in the design rule library. Clicking fine default low specifies AAA and XYZ as footprints for Z80A-QFP and LS04-DIP, respectively.

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The following introduces the function on the menu bar of Design Rule Library Editor.

Saves the design rule that is being edited. Saves the design rule that is being edited in another name. Restores the setting contents to the state before edition. Deletes the design rule that is being edited. Exits from the tool after saving the design rule that is being edited.

Undo the previous edit process Restore before undo the edit process Checks whether there are any blanks in settings. Loads all existing design rule libraries (refer to the description below). Loads a portion of existing design rule libraries (refer to the description below). Loads design rules dedicated to the existing PC board (refer to the description below). Relates a design rule with a keyword that is used to search the design rule. Start up the Design Rule Stack dialog. Start up the Wiring Width Stack dialog. Start up the Grid dialog. Sets library file names to be referenced (refer to page 4-2).

Starts up the library searcher (Caution: the library searcher is an option).

* Loading existing design rules Design rules consist of ones that are generated for each PC board by executing Board Generation Tool, in addition to ones generated by the Design Rule Library Editor. Both of them can be loaded. Utilities Load (whole) from Library Utilities Load (partial) from Library Utilities Load rule (whole) from database Technology library Design rule library TCH
Spec A RUL Spec B RUL Spec C RUL

Library

Board Generation

PCB Board database

RUL Design rule database

Design Rule

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Load (whole) from Library This function is used to move all attributes that can be edited from the design rule database of the existing design rule library to the design rule database that is being edited.
Select an existing design rule database from the list.

Click OK to start processing.

Caution

Care must be taken before executing Load Whole Library function, because the status before loading cannot be restored after executing this function, even by clicking Cancel . Normally, loading starts from the design rule library that is prepared as a template or a design rule library that can be reused when generating a new design rule library.

Load (partial) from Library This function can move items from the design rule database of the existing design rule library to the design rule database that is being edited. There are two selectable loading modes: Replace and Merge.

Items that can be loaded in Load (partial) from Library are listed.

Switch whether each item is to be loaded or not.

Replace Clears the original data and replaces with the specified library data. Merge Adds the specified library data while leaving the original data as-is. Objects having the same name cannot be loaded.

Caution

The status before loading cannot be restored after executing this function, even by clicking

Cancel .

Reference

Refer to online help for details on Design Rule Library Loading.

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* Define search Key A user can define design rule items for search to each design rule file in the design rule library using this function. This makes it possible to classify the design rule library for management, and items to be edited or referenced in a library can be searched simply by specifying a rule.
Example

For example, when the PC board specs are different according to customers as shown in the figure to the right, the design rule files can be managed simply by relating a corresponding rule item to each file. Utilities Define search Key

Customer Company A Company B Company C

PC board spec. Normal Build up Normal Build up Normal Build up

Design rule file ruleA ruleB ruleC ruleD ruleE ruleF

Users item name

Keyword

Create a users item name and keyword for relating.

Assign a keyword to the created users item name that is suitable for the design rule file under edition.

As shown above, the related design rule files can be searched by defining the keyword during new PC board generation or design rule file edition. For example, when the customer is Company A and you want to edit a design rule file with a Normal PC board specification, set the corresponding keyword to each users item using the DesignRule Selector to search the target design rule file.
Select a keyword for the users item from the list and set it.

The design rule file that is searched by the search rule (keyword) is displayed.

Reference

Refer to online help for details on how to set Define search Keys....

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Defining Design Rules

Each design rule can be defined on the Design Rule Library Setup Screen. Design Rule Library Setup Screen Each setup screen can be changed by each tab.

Each tab is classifying definition rule.

Design Rule Stack the menu bar.

[Design Rule Stack]

Wiring Width Stack

[Wiring Width Stack]

and

Grid

are defined by
[Grid]

Set

of

A decoupling capacitor and a jumper are defined by the button of

[Component Objects]

Comp. Objects .

Items on this screen are introduced from the next page.

Note
The design rules include several setting items that define rules required by optional programs, as well as ones required by the Board Designer. Refer to the following pages for details.

Online documentation "Appendix 2. Correspondence table between net and component properties, and commands (tools)" in [Board Designer/Board Producer Environment Configuration Guide].

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Design Info.
A comment for the board and a footprint spec name are defined.
A comment for the board specification. (Can be omitted) A comment for the board. (Can be omitted)

Board Spec
A board thickness and each layer thickness are defined. Physical Spec Physical information on bare boards. These specifications are used for each simulator, and can be omitted if no simulation will be executed. But be sure to set up the Board Size X,Y.
Size of square including the PC board. This setting is referenced to estimate and determine the screen display area in the beginning of the layout design. Be sure to enter this setting, even a rough value is allowed. This value is also referenced by the auto router.

Enter a name that represents the PC board material. (Can be omitted)

Specify the thermal conductivity transmitted in the PC board.

Specify the PC board thickness.

Layer Construction Layer construction on bare boards. These specifications are used for each simulator, and can be omitted if no simulation will be executed. And the Core Layer is filled in the check mark when core layers exist in the buildup board, and core layer numbers are specified

Specify whether there is a core layer.

Define the attribute for each conductive/insulate layer.

Layer thickness/Material/Dielectric constant

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Placement
The specification regarding placement and a clearance value for component placement are defined. Placement Placement side and Grid are defined.
Specifies single-side placement or both-side placement. * This item is not currently referenced. Specifies a default grid for component placement Starts up the grid registration dialog.

Clearance Clearance value regarding placement is defined.

Specifies a clearance regarding component placement.
Component Area-Component Area

Component Area-Height Limit Area

Component Area-Component Area Height

Grouping components and different clearances are defined by the group and the placement direction.

Component Area-Height Limit Area Height

Component Area-Placement Keepout Area

The component DRC group attribute list that was defined by Package or Footprint is displayed. A component placement direction is defined. wide A clearance value is defined. narrow

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Wiring Rule
A spec regarding wiring and a pattern width which can be used are defined.
Starts up the wiring width stack registration dialog. Starts up the grid registration dialog. Specifies default wiring width stack name.
Minimum number of bridges that are connected to the power plane (refer to the DRC function for the inside layer) Bridge

Stub length

Specifies default grid name which is used when a wiring is entered.

Minimum pad width when the round cutting function is used (refer to the round cutting function)

[ Wiring Width Limit. ]

List of available pattern widths

Specifies an available pattern width by entering a real number.

[ Layer Spec. ]

Specifies the primary wiring pattern direction by X , Y, 45 degree, 135 degree, X-Y direction or 45-135 degree direction.

Allowed length for which a wiring pattern can be drawn ignoring the primary wiring direction. * This setting is not referenced currently.

Defines a wiring grid for each conductive layer. If this setting is omitted, the grid specified by the default wiring grid is applied.

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Via / Area Spec

A via (padstack) which can be used and a spec of area are specified. Via Spec. A via (padstack) to be used on the board and a layer combination which can be entered are defined.
Starts up the grid registration dialog.

Specifies default padstack name which is used when a via is entered.

Specifies default grid name which is used when a via is entered.

Specifies whether to use the interstitial via and whether to limit the layer combination. Defines combining layers when there is a limitation for layer combination.

[ Qualified Padstack ]

[ Available Padstack ]

Defines padstacks to use preferentially by the layer combination.

Defines padstacks to be used except default padstack or qualified padstack.

Area Spec. A cut-out figure to be used by the Mesh are defined.

Defines whether to limit the mesh

Defines the diameters of available cut-out figures

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Wiring Clearance
A wiring clearance is specified.
Default design rule stack Starts up the design rule stack registration dialog.

Specifies the value for a clearance between holes that exists in a padstack. (These values are referred to when Area DRC command is executed.) Buildup Via - Buildup Via : Clearance between holes in buildup via BuildupViaHole - Hole : Clearance between a hole in the buildup via and a hole in any other padstack. Hole - Hole : Clearance between holes in a padstack, except for buildup via padstacks. Hole - Layout Area : Clearance between a hole in a padstack (other than buildup via padstacks) and the layout area. Different insulate layer Same insulate layer

When it doesn't have the space of the common layer.

When it has the space of the common layer.

[Parallel Wire Length Limit./Tandem Wire Length Limit. ]

Specifies the parallel wiring length limitation and the clearance on the same layer or between adjacent layers. (These values are referred to when Area DRC command is executed.) Parallel Wire Length Limit.
Width Limit Length

Parallel wiring length in the same layer Parallel wiring length between adjacent layers Layer 1 Width Limit Length
Layer 2

Tandem Wire Length Limit.

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Differential Clearance Clearance values for differential pairs are defined.

Differential Pair Differential Pair

Differential Pair Power/Ground

Differential Pair Signal Net Starts up the list dialog of design rule stack.

Application Rule. The clearance and the priority which are referred to by the application (each check command) are defined.

Controls the clearance which is referred to by each command (Area DRC/Shield Generation) in Placement /Wiring tool.

Reference Refer to [Master Training <PCB Design>] for details of the Application Rule.

Artwork
A spec regarding manufacturing data is specified.
Starts up the grid registration dialog. Default grid in Artwork tool

Symbol Mark Spec. The spec regarding silk text is defined. (It is referred to when the Area MRC is performed.)
Minimum text width that is possible to input Minimum text height that is possible to input Minimum text spacing that is possible to input

Angle that is possible to input

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Clearance Clearance values between the resist and other objects are defined. And between the symbol mark and other objects are defined, too. (They are referred to when the area MRC is performed.)
Resist-Resist (Flow)

Resist-Resist (Reflow) Defines clearance between the resist or the symbol mark and other objects. (They are referred to by the area MRC command and the symbol mark cut.) Resist-Conductive (Flow)

Resist-Conductive (Reflow)

Symbol Mark - Resist

Symbol Mark - Hole

Comp. Objects
A jumper and a decoupling capacitor are defined. When a part name is added, part information is copied to PC board as a part that can be used as a jumper or a decoupling capacitor in new board generation.

Select a part which registers and add. Jumper : Jumper attribute (Part) Decoupling Capacitor : 2-terminals part

Defined objects are displayed by switching the tab. The placement side and the placement angle can be specified by each part.

When Jumper is selected

When decoupling capacitor is selected

Decoupling capacitor

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Design Rule Stack

The value of clearance between objects is defined.
Caution

The design rule stack, the wiring width stack and the grid start up from

Set .

The flow of the definition

(1) Generates the [Rule Unit] which defined each clearance. unit0.2
pattern_pattern pattern_via 0.2 0.2

(2) Generates the [Rule Stack] which assigned the rule unit by each conductive layer. all-0.2 unit0.2 unit0.2 unit0.2 unit0.2 all-0.3 unit0.3 unit0.3 unit0.3 unit0.3 0.2-0.3 unit0.2 unit0.3 unit0.3 unit0.2

Clearance possible to define by the rule unit Clearance

The value of each clearance between objects is defined when target objects are different net and when they are same net.
Pattern Area

Though Pin SMD Pin Various Keep-out area

Padstack
The value of each clearance between specified padstacks is defined when both padstacks are different net and when they are same net.

Pattern VIA0.8-1.5 NTH1.0-2.0

BLD0.5

Reference

Refer to [Appendix 1 Design Rule Unit Setting Value List] for details of setting items.

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Wiring Width Stack

The wiring width to be used is defined. The wiring width stack which defined the standard, maximum and minimum wiring pattern width and also minimum overlap land length for each layer are created.
Specifies the minimum height required by the land when dividing a via.

Minimum land overlap

Land generated after dividing

Land before division

When this height is not satisfied, a line is generated between lands.

Specifies the standard wiring pattern width, maximum wiring pattern width and minimum wiring pattern width for each layer.

Wiring Pattern Width Maximum Wiring Pattern Width (used by the online DRC) Minimum Wiring Pattern Width (used by the online DRC
or for neck-down

The most suitable width is calculated by the layer thickness, the dielectric constant and the minimum wiring width and it is defined to the wiring width stack.

Defines the Target Impedance and then executes the Calculate wiring width.

Grid
The grid is defined.

The combination of grid to want to use is defined.

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Lesson

The following shows an example of setting the design rule rule A. 1. Define the Board Spec. Board Sizes X,Y 130 110 Board Thickness .... 1.00 Thermal Conductivity[W/mK] Omit Material . FR-4 Core layer None Layer Construction (Layer Thickness) Conductive Layer 0.04 Resist Layer . 0.05 Insulate Layer .. 0.25 Layer Construction (Material ) Conductive Layer . FR-4

2. Define the Placement. Placement Side .. Double

Click Click

Click the Register Grid.

Enter G-2.54 to the Grid Name and then click the Add.
Click

Similarly, register the following grid names. G-1.27 G-0.635 G-0.508 G-0.3175 G-5.0 G-2.0 G-1.0 G-0.5 G-0.25 G-0.2 G-0.1

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Click

Click the inside of the Pitch X box for G-0.1 and enter 0.1 from the keyboard and then is set it by Return .

Click Copy from the assist menu .

Click

Select the inside of the Pitch Y box for G-0.1 and click Paste from the assist menu.
Click

Grid pitch is set.

Similarly, set all grids.

Click File Save from the menu bar.

Click Click

Select G-2.54 of the grid name and click Send.

Click File Exit from the menu bar.

The placement grid is set.

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3. Define the Wiring Spec.

Click

Click Register Wiring Width Stack.

Enter line0.2_0.2 to Wiring Width Stack and click Add.

Click

Click

Click the cell of Wiring Width for conductive layer 1.

Enter 0.2 from the keyboard and is set it by Return.

Similarly, set wiring width to layer 4 from layer 2.

Hold

Release Click

Select the line for wiring width (Hold & Release) and click Copy from the assist menu.

Hold

Release Click

Select the line for minimum wiring width (Hold & Release) and click Paste from the assist menu.

The Minimum Wiring Width is set.

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1. Registering a Design Rule Library

Similarly, add a Wiring Width Stack as the name is line 0.5_0.2 and set the following parameter. Wiring pattern width . 0.5mm Minimum wiring pattern width 0.2mm

Click File Save from the menu bar.

Click

Click

Select line0.2_0.2 of the wiring width stack name and click Send.

Click File Exit from the menu bar.

Click

The Wiring Width Stack is set.

4. Define the Wiring Grid. Set the following parameter. Wiring Grid . G-0.508 Maximum Stub Length 0.2mm Minimum Pad Width 0.2mm Minimum Thermal Bridge . 3 Set the following parameter. Primary Wiring Direction 1:X 2:Y 3:X 4:Y Prim. Wire. Dir. Violation Tolerance Undefined Wiring Grid Undefined

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5. Define the Wiring Width Limit.

Click

Fill in the box of Wiring Width Limit. and click the button of Register Wiring Width.

Click

Enter 0.2 to Wiring Width and click Add .

Click

Similarly, register the following wiring width. 0.3 0.4 0.5 0.6 0.7 Click OK. 0.8 0.9 1.0 2.0 3.0

Click

They are registered as the left figure.

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1. Registering a Design Rule Library

* The setting method for each item The Design Rule Library Edit Tool performs the setting from a table type dialog, a list dialog or a calculation dialog. The following introduces the operation for each setting.

1. Setting from a table type dialog.

Direct input

Copy & Paste

Select a line

Select a row

Select optional cells

Caution

When the paste of Copy&Paste is performed, the assist menu is displayed. In that time, the cursor needs to exist on the cell where they will be input.

2. Setting from a list dialog or a calculation dialog.

When the value which can specify in the cell is determined, it can be entered from a list dialog. List dialog
Click

Calculation dialog
Click

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6. Define the Via/Area Spec. Click the list icon for via grid.
Click

Select G-0.508 from the list and click OK .

Click

Click

Click

Click the list icon for default padstack.

Select V0.6-1.0 from the list and click OK.

Click

The via spec. is set as the left figure. 7. Define the Available Padstack. Click Register Available Padstack.
Click

Click

Ctrl

Click

Select VIA0.7-1.3" and VIA0.8-1.4 pressing Ctrl key, and click Add. Add .

key, and click

Click

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1. Registering a Design Rule Library

Click OK.

Click

The available padstack is set as the left figure.

Other Via/Area spec. is undefined.

8. Define the Wiring Clearance.

Click

Click Register Design Rule Stack.

Click Design Rule Unit from the started up dialog.

Click

Enter unit0.2 to design Rule Stack and click Add.

Click

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Click Utilities Fill all clearance from the menu bar.

Click

Enter 0.2 and click OK.

Click

"0.2" is set as the left figure to all the cells.

Reference

Refer to [*The setting method for each item] on page 4-24, for other input method.

The clearance for Padstack is undefined.

Similarly, add a rule unit as the name is unit0.3 and set the following clearance. Clearance 0.3mm for all Padstack . Undefined

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1. Registering a Design Rule Library

Click File Exit from the menu bar.

Click

Click Yes from the confirmation dialog.

Click

Register a Design Rule Unit and register a design rule stack. Enter all-0.2 to the Design Rule Stack and click Add.

Click

Select the cell of Design Rule Unit for conductive layer1 and click the action button.

Click

Select unit0.2 and click OK.

Click

Click

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Select the cell of the Design Rule Unit for layer 1 and click Copy from the assist menu.

Click

Select the line of the Design Rule Unit (Hold & Release) and click Paste.
Hold

Release Click

It is set as the left figure.

Similarly, add a design rule stack as the name is all-0.3 and set the following parameter. Design Rule Unit unit0.3 for all

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Click File Save from the menu bar.

Click

Select all-0.2 of the Design Rule Stack name and click Send.
Click

Click

Click File Exit from the menu bar.

Click

The design rule stack is set.

9. Define the Via Hole Clearance and Wiring Length Limitation. Set Via Hole Clearance as the following.

Buildup Via - Buildup Via 0.1mm for all Buildup Via Hole ... 0.1mm for all Hole Hole ... 0.2mm Hole Layout Area .. 0.5mm Parallel Wire Length Limit and Tandem Wire Length Limit are undefined.

10. Define the Differential Clearance. Set Differential Clearance as the following. Differential Pair Differential Pair all-0.2 Differential Pair Power/Ground all-0.3 Differential Pair Signal Net all-0.2

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11. Define the Application Rule. Set Application Rule as the following.

Clearance Priority : ON Shield Gap Priority : Shield Gap Differential Clearance Priority : Differential Clearance 12. Define the Artwork Grid.
Click

Click the list icon for Artwork Grid .

Select G-1.0 from the list and click OK.

Click

Click

The artwork grid is set as the left figure. 13. Define the Symbol Mark Spec.. Set Symbol Mark Spec. as the following. Minimum Text Width .. 1.0mm Minimum Text Height . 1.0mm Minimum Text Spacing .. Undefined Text Angle Limit. . Limit 0 degree and 90 degree for both A-side and B-side 14. Define the Clearance regarding Artwork. Set Clearance as the following. Resist Resist Flow Resist Resist Reflow Resist Conductive Flow Resist Conductive Reflow Symbol Mark Hole Symbol Mark Resist :0.5mm :0.4mm :0.1mm :0.1mm :0.6mm :0.2mm

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15. Define the Component Objects. Click Comp. Objects from the design rule edit dialog.
Click

Set a Jumper component.

Click

Click the icon of the part name.

Click

Select Jumper and click OK.

Click

The Jumper is set.

After setting the Jumper, set a Decoupling Capacitor.

Click

After the tab switched to the tab for Decoupling Capacitor, click the list icon of the part name.

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Click

Select OK .

0.33uF

and click

Click

The Decoupling Capacitor is set.

Click File the menu bar.

Click

Exit

from

Click Yes from the confirmation dialog.

Click

16. That finishes all settings. Exit the Design Rule library Edit Tool. Click Utilities Design Rule Check menu bar. Click Yes from the confirmation dialog.
Click

Click

from the

You can confirm all the settings have been completed.

Click
Click

Close .

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1. Registering a Design Rule Library

Click File Exit Tool from the menu bar.

Click

17. Also exit the PCB Design/Manufacture Common Tool.

Click

Click File the menu bar.

Exit

from

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1. Design Rule Unit Setting Value List

Clearance value possible to set by the Design Rule Unit
Clearance value between the various objects are set by the Design Rule Unit. Those details are introduced in the following.

Clearance
Clearance value between the objects is defined at every combination of objects. (The following clearance value can be set by same net or different net.) Clearance for Wiring (except Area)
Targert1 Target2

Wire (Except Area)

Wire (Except Area) Area (Wire) Through Pin SMD Pin Through Via Internal Via Landless Through Via Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14

A13 Through Via A9 Buildup Via A1 A5 A6 A2

A3

A4

A7

A8

Landless Landless Internal Via Through Via Internal Via A10 A11 Landless Skip/Stack A14

Skip/Stack A12

A15

Through Via in core layer

A15 Landless Landless Internal Via Through Via Internal Via in core layer in core layer in core layer

Note

Through Via in core layer/Internal Via in core layer/Landless Through Via in core layer/ Landless Internal Via in core layer can be defined when Via Clearance for Core Layer in Wiring Clearance - Application Rule is filled in.

Clearance for Area (Wiring)

Targert1 Target2

Area (Wire)

Area (Wire) Through Pin SMD Pin Through Via Internal Via Landless Through Via Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14

Through Via B8 Buildup Via B11 B4 B5 B1

B2

B3

B6 Landless Through Via B10

B7 Landless Internal Via

Internal Via

Skip/Stack

Landless Skip/Stack B13

Through Via in core layer

B14 B12 Landless Internal Via Landless Internal Via in core layer Through Via in core layer in core layer

Appendix

A-1

1.Design Rule Unit Setting Value List

Clearance for Through Pin

Targert1 Target2

Through Pin

Through Pin SMD Pin Through Via Internal Via Landless Through Via Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13

C1 C3

C2 C4

C5

C6

Through Via C7

Landless Internal Via Landless Inaternal Via Through Via C8 C9 Landless Skip/Stack C12 C13

Buildup Via C10

Skip/Stack C11

Through Via in core layer

Landless Internal Via Through Via in core layer in core layer

Landless Internal Via in core layer

Clearance for SMD Pin

Targert1 Target2

SMD Pin

SMD Pin Through Via Internal Via Landless Through Via Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12

Through Via D2

D1 D 3 Internal Via D6 D7

D4 Landless Through Via D8 Landless Skip/Stack D11

D5 Landless Inaternal Via

Buildup Via D9

Skip/Stack

D10 Through Via in core layer Landless Internal Via Through Via in core layer in core layer

D12 Landless Internal Via in core layer

Clearance for Through Via

Targert1 Target2
C3 C4 C5 C6

Through Via

Through Via Internal Via Landless Through Via Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11
Buildup Via C10 Skip/Stack C11 Landless Skip/Stack C12 C13 Through Via C7 Landless Internal Via Landless Inaternal Via Through Via C8 C9

Through Via in core layer

Landless Internal Via Through Via in core layer in core layer

Landless Internal Via in core layer

A-2

Appendix

1. Design Rule Unit Setting Value List

Clearance for Internal Via

Targert1 Target2

F1

F2

F3

F4

Internal Via

Internal Via Landless Through Via Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
Through Via in core layer Skip/Stack F7 Internal Via F5

Landless Landless Through Via Internal Via F6 Landless Skip/Stack F8

Buildup Via

F9

F10

Internal Via in core layer

Landless Through Via in core layer

Landless Internal Via in core layer

Clearance for Landless Through Via

Targert1 Target2

G1

G2

G3

G4

Landless Through Via

Landless Through Via Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

G1 G2 G3 G4 G5 G6 G7 G8 G9
Through Via in core layer Landless Through Via G5

Landless Internal Via Buildup Via

Skip/Stack

G6

G7

G8

G9

Internal Via in core layer

Landless Through Via in core layer

Landless Internal Via in core layer

Clearance for Landless Internal Via

Targert1 Target2

Landless Internal Via

Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack

Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

H1 H2 H3 H4 H5 H6 H7 H8

H1

H2

H3

H4

Landless Internal Via H5

Buildup Via Skip/Stack H6 H7

Landless Skip/Stack H8

Through Via in core layer

Internal Via in core layer

Landless Through Via in core layer

Landless Internal Via in core layer

Clearance for Buildup Via

Targert1 Target2

I1

I2

I3 Landless Skip/Stack I6 I7

Buildup Via

Buildup Via Skip/Stack Landless Skip/Stack

Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

I1 I2 I3 I4 I5 I6 I7
Buildup Via Skip/Stack I4 I5

Through Via in core layer

Internal Via in core layer

Landless Through Via in core layer

Landless Internal Via in core layer

Appendix

A-3

1.Design Rule Unit Setting Value List

Clearance for Skip/Stack

Targert1 Target2

J1

J2 Landless Skip/Stack J4 J5 J6

Skip / Stack

Skip/Stack Landless Skip/Stack

Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

J1 J2 J3 J4 J5 J6

Skip/Stack J3

Landless Through Via Internal Via Through Via in core layer in core layer in core layer

Landless Internal Via in core layer

Clearance for Landless Skip/Stack

Targert1 Target2

K1 Landless Skip/Stack K2 K3 K4 K5

Landless Skip / Stack

Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

K1 K2 K3 K4 K5

Landless Through Via Internal Via Through Via in core layer in core layer in core layer

Landless Internal Via in core layer

Clearance for Through Via in core layer

Targert1 Target2 Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer
L1 L2 L3 L4

Through Via in core layer

L1 L2 L3 L4
Through Via in core layer Landless Internal Via Through Via in core layer in core layer Landless Internal Via in core layer

Clearance for Internal Via in core layer

Targert1

Internal Via in core layer

Target2 Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

M1

M2

M3

M1 M2 M3
Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

Clearance for Landless Through Via in core layer

Targert1

Landless Through Via in core layer

Target2 Landless Through Via in core layer Landless Internal Via in core layer

N1

N2

N1 N2
Landless Through Via in core layer Landless Internal Via in core layer

Clearance for Landless Internal Via in core layer

Targert1 Target2 Landless Internal Via in core layer

Landless Internal Via in core layer

O1

O1

Landless Internal Via in core layer

A-4

Appendix

1. Design Rule Unit Setting Value List

Clearance for Hole

Targert1 Target2

Hole

Wire (Except Area) Area (Wire) Through Pin SMD Pin Through Via Internal Via Landless Through Via Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

P1 P3

P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15

Through Via in core layer Buildup Via P12 Through Via P9 P5 P4

P 2

P6

P7

P8 Landless Internal Via

Internal Via P10

Landless Through Via P11 Landless Skip/Stack P14

Skip/Stack P1 3

P15

Landless Landless Internal Via Through Via Internal Via in core layer in core layer in core layer

Clearance for Layout Area

Targert1 Target2

Q2

Q3

Layout Area

Wire (Except Area) Area (Wire) Through Pin SMD Pin Through Via Internal Via Landless Through Via Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15

Q1

Q4 Q5 Q8 Landless Internal Via

Q6

Q7

Landless Through Via Internal Via Through Via Q9 Buildup Via Q10

Q11 Landless Skip/Stack

Skip/Stack

Q12

Q13

Q14

Q15

Through Via in core layer

Landless Landless Internal Via Through Via Internal Via in core layer in core layer in core layer

Note

There is no definition between same net and different net regarding Hole and Layout Area.

Appendix

A-5

1.Design Rule Unit Setting Value List

Clearance for Others

Targert1 Target2

Wire Via Via Hole

Wire Keepout Area Via Keepout Area Via Hole Keepout Area From SMD Pin

R1 R2 R3
Wiring Keep-out Area R1 R2 R3

Via Keep-out Area

R4 R5

R4 R7

Via Hole keep-out Area

Distance To First Turn In-component Clearance

From Though Pin SMD Pin SMD Pin Through Pin Through Pin

R6 R7

R6 R5

Padstcks
Clearance value between specific padstacks or between specific padstack and each objects are defined. (The following clearance value can be set by same net or different net.) Clearance between padstacks Padstack Padstack

S1

S1

Padstack ("VIA0.8-1.4")

Padstack ("NTH1.8-2.2")

Clearance between padstack and other objects

Target2

Padstack

Wire (Except Area) Area (Wire) Through Pin SMD Pin Through Via Internal Via Landless Through Via Landless Internal Via Buildup Via Skip/Stack Landless Skip/Stack
Through Via in core layer Internal Via in core layer Landless Through Via in core layer Landless Internal Via in core layer Hole Layout Area

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17

Internal Via Landless in core layer Through Via in core layer T17 T16 Landless Internal Via in core layer Buildup Via T12 Skip/Stack T13 T5 T2 T6 T7 T8 T1 T3 T4

Through Via T9

Landless Internal Via Landless Internal Via Through Via T10 T11 Landless Skip/Stack T14 T15

Hole

Layout Area

A-6

Appendix

Zuken Inc. Master Training <PCB Design Library> Serial ID C2B1001E